M30802SGP-BL

Renesas Technology Corp

RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

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RENE SAS 16-BIT SING LE-C HIP MIC R OCO MP U TE R M1 6C FAMILY / M16C/80 SERIES M16C/80 Group16 Rev. 1.00 Revision date: Aug. 02, 2005 Hardware Manual www.renesas.com Before using this material, please visit our website to verify that this is the most updated document available. REJ09B0187-0100

Keep safety first in your circuit designs! Notes regarding these materials 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with ap- propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap. 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, pro- grams, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, pro- grams and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers con- tact Renesas Technology Corp. or an authorized Renesas Technology Corp. product dis- tributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by vari- ous means, including the Renesas Technology Corp. Semiconductor home page (http:// www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all informa- tion as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liabil- ity or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or repro- duce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be im- ported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.

1.Introduction This hardware manual provides detailes information on the M16C/80 group microcomputers. Users are exoected to have basic knowledge of electric circuits,logical circuits and microcomputers. 2.Register Diagram The symbols,and descriptions,used for bit function in each register are shown below. R: Read W: Write When write, value can be "0" or "1" Blank:Set to "0" or "1" according to intended use 0: Set to "0" 1: Set to "1" X: Nothing is assigned Terms to use here are explained as follows.

Nothing is assigned Nothing is assigned to the bit concerned. When write, set "0" for new function in future plan.
Inhibited Not select. The operation at having selected is not guaranteed.
Reserved bit Reserved bit. Set the specified value.
Function varies with each operation mode Bit function changes according to the mode of peripheral functions.
Must be fixed to "0" in A mode Set the bit concerned to "0" in A mode.
Invalid in A mode The bit concerned has no function in A mode. Set the specified value.
Valid when bit A="0" When bit A is "1", the bit concerned has no function. When bit A is "0", the bit concerned has function. XXX register Symbol Address When reset XXX XXX 00 16 Bit nameBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 XXX select bit 1 0 : XXX 0 1 : XXX 1 0 : Inhibited 1 1 : XXX b1 b0 XXX1 XXX0 XXX Reserved bit XXX XXX XXX Function Nothing is assigned. When write, set "0". When read, its content is indeterminate. XXX flag Function varies with each operation mode Must always b set to "0" /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines *1 *2

M16C Family Documents The following documents were prepared for the M16C family. (1) Document Contents Short Sheet Hardware overview Data Sheet Hardware overview and electrical characteristics Hardware Manual Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, timing charts) Software Manual Detailed description of assembly instructions and microcomputer perfor- mance of each instruction Application Note • Application examples of peripheral functions

Sample programs
Introduction to the basic functions in the M16C family
Programming method with Assembly and C languages RENESAS TECHNICAL UPDATE Preliminary report about the specification of a product, a document, etc. NOTES : 1. Before using this material, please visit the our website to verify that this is the most updated document available.

9.9 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL) ... 64 19. Clock-asynchronous serial I/O mode (compliant with the SIM interface) ___151

Watchdog timer start register Watchdog timer control register Processor mode register 0 Address match interrupt register 0 Address match interrupt register 1 Wait control register System clock control register 0 System clock control register 1 Address match interrupt enable register Protect register Processor mode register 1 External data bus width control register Main clock division register Address match interrupt register 2 Address match interrupt register 3 Emulator interrupt vector table register Emulator interrupt detect register Emulator protect register ROM areaset register Debug monitor area set register Expansion area set register 0 Expansion area set register 1 Expansion area set register 2 Expansion area set register 3 DRAM control register DRAM refresh interval set register Timer A1 interrupt control register UART0 transmit interrupt control register Timer A0 interrupt control register Timer A2 interrupt control register UART0 receive interrupt control register UART2 transmit/NACK interrupt control register UART1 receive interrupt control register DMA2 interrupt control register DMA0 interrupt control register Key input interrupt control register A/D conversion interrupt control register Bus collision detection(UART3) interrupt control register UART2 receive/ACK interrupt control register INT1 interrupt control register Timer B0 interrupt control register Timer B2 interrupt control register Timer A3 interrupt control register INT2 interrupt control register INT0 interrupt control register Timer B1 interrupt control register Timer A4 interrupt control register INT3 interrupt control register Timer B5 interrupt control register Timer B4 interrupt control register Timer B3 interrupt control register INT5 interrupt control register INT4 interrupt control register UART3 receive/ACK interrupt control register UART4 receive/ACK interrupt control register UART3 transmit/NACK interrupt control register UART4 transmit/NACK interrupt control register Exit priority register UART1 transmit interrupt control register DMA1 interrupt control register DMA3 interrupt control register Bus collision detection(UART2) interrupt control register Bus collision detection(UART4) interrupt control register Blank spaces are reserved. No access is allowed. WDTS WDC PM0 RMAD0 RMAD1 WCR CM0 CM1 AIER PRCR PM1 DS MCD RMAD2 RMAD3 EIAD EITD EPRR ROA DBA EXA0 EXA1 EXA2 EXA3 DRAMCONT REFCNT TA1IC S0TIC TA0IC TA2IC S0RIC S2TIC S1RIC DM2IC DM0IC KUPIC ADIC BCN3IC S2RIC INT1IC TB0IC TB2IC TA3IC INT2IC INT0IC TB1IC TA4IC INT3IC TB5IC TB4IC TB3IC INT5IC INT4IC S3RIC S4RIC S3TIC S4TIC RLVL S1TIC DM1IC DM3IC BCN2IC BCN4IC Address Register pageSymbol Address Register pageSymbol 183 185 Quick Reference by Address

X0 register ,Y0 register X1 register, Y1 register X2 register ,Y2 register X3 register,Y3 register X4 register , Y4 register X5 register , Y5 register X6 register ,Y6 register X7 register ,Y7 register X8 register , Y8 register X9 register,Y9 register X10 register,Y10 register X11 register, Y11 register X12 register, Y12 register X13 register,Y13 register X14 register,Y14 register X15 register, Y15 register XY control register UART4 special mode register UART4 receive buffer register UART4 transmit buffer register UART4 transmit/receive control register 0 UART4 transmit/receive mode register UART4 transmit/receive control register 1 UART4 bit rate generator UART4 special mode register 2 Timer A1-1 register Timer A2-1 register Dead time timer Timer B2 interrupt occurrence frequency set counter Three-phase PWM control register 0 Three-phase PWM control register 1 Thrree-phase output buffer register 0 Thrree-phase output buffer register 1 Timer B3 register Timer B4 register Timer B5 register Timer B3, 4, 5 count start flag Timer B3 mode register Timer B4 mode register Timer B5 mode register Interrupt cause select register UART2 special mode register UART2 receive buffer register UART2 transmit buffer register UART2 transmit/receive control register 0 UART2 transmit/receive mode register UART2 transmit/receive control register 1 UART2 bit rate generator Timer A4-1 register UART2 special mode register 2 UART3 special mode register UART3 receive buffer register UART3 transmit buffer register UART3 transmit/receive control register 0 UART3 transmit/receive mode register UART3 transmit/receive control register 1 UART3 bit rate generator UART3 special mode register 2 UART4 special mode register 3 UART2 special mode register 3 UART3 special mode register 3 Blank spaces are reserved. No access is allowed. Address Register pageSymbol Address Register pageSymbol X0R,Y0R X1R,Y1R X2R,Y2R X3R,Y3R X4R,Y4R X5R,Y5R X6R,Y6R X7R,Y7R X8R,Y8R X9R,Y9R X10R,Y10R X11R,Y11R X12R,Y12R X13R,Y13R X14R,Y14R X15R,Y15R XYC U4SMR U4RB U4TB U4C0 U4MR U4C1 U4BRG U4SMR2 U4SMR3 TA11 TA21 DTT ICTB2 INVC0 INVC1 IDB0 IDB1 TB3 TB4 TB5 TBSR TB3MR TB4MR TB5MR IFSR U2SMR U2RB U2TB U2C0 U2MR U2C1 U2BRG TA41 U2SMR2 U3SMR U3RB U3TB U3C0 U3MR U3C1 U3BRG U3SMR2 U2SMR3 U3SMR3 181 134 129 132 130 133 129 135 180 136 114 112 113 107 107 106 134 129 131 130 133 129 135 134 129 129 132 130 133 129 135 136 136 Quick Reference by Address

Address Register pageSymbol Address Register pageSymbol Timer A0 register Timer A1 register Timer A2 register Timer B0 register Timer B1 register Timer B2 register Count start flag One-shot start flag Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Up-down flag Timer A3 register Timer A4 register Timer A3 mode register Timer A4 mode register Trigger select register Clock prescaler reset flag UART0 transmit/receive mode register UART0 transmit buffer register UART0 receive buffer register UART1 transmit/receive mode register UART1 transmit buffer register UART1 receive buffer register UART0 bit rate generator UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 UART1 bit rate generator UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 DMA1 request cause select register DMA0 request cause select register CRC data register CRC input register UART transmit/receive control register 2 A/D register 7 A/D register 0 A/D register 1 A/D register 2 A/D register 3 A/D register 4 A/D register 5 A/D register 6 Function select register C Function select register A1 Function select register A0 Function select register B0 Function select register B1 Function select register A3 Function select register A2 Function select register B2 A/D control register 0 A/D control register 1 D/A register 0 D/A register 1 D/A control register A/D control register 2 DMA3 request cause select register DMA2 request cause select register Function select register B3 Flash memory control register 0 Flash memory control register 1 Blank spaces are reserved. No access is allowed. TA0 TA1 TA2 TB0 TB1 TB2 TABSR ONSF TA0MR TA1MR TA2MR TB0MR TB1MR TB2MR UDF TA3 TA4 TA3MR TA4MR TRGSR CPSRF U0MR U0TB U0RB U1MR U1TB U1RB U0BRG U0C0 U0C1 U1BRG U1C1 DM1SL DM0SL CRCD CRCIN UCON DM3SL DM2SL FMR0 FMR1 U1C0 AD7 AD0 AD1 AD2 AD3 AD4 AD5 AD6 PSC PS1 PS0 PSL0 PSL1 PS3 PS2 PSL2 ADCON0 ADCON1 DA0 DA1 DACON ADCON2 PSL3 107 106 130 129 129 130 129 131 133 129 178 134 276 129 131 133 169 168 177 177 177 169 200 202 201 202 203 203 Quick Reference by Address

Port P0 direction register Port P1 Port P1 direction register Port P2 Port P2 direction register Port P3 Port P3 direction register Port P4 Port P4 direction register Port P5 Port P5 direction register Port P6 Port P6 direction register Port P7 Port P7 direction register Port P8 Port P8 direction register Port P9 Port P9 direction register Port P10 Port P10 direction register Pull-up control register 0 Pull-up control register 1 Pull-up control register 2 Port control register Pull-up control register 3 Port P0 Port P0 direction register Port P1 Port P1 direction register Port P2 (P2) Port P2 direction register Port P3 (P3) Port P3 direction register Port P4 Port P4 direction register Port P5 Port P5 direction register Port P6 Port P6 direction register Port P7 Port P7 direction register Port P8 Port P8 direction register Port P9 Port P9 direction register Port P10 Port P10 direction register Pull-up control register 0 Pull-up control register 1 Pull-up control register 2 Port control register Pull-up control register 3 Port P11 Port P11 direction register Port P12 Port P12 direction register Port P13 Port P13 direction register Port P14 Port P14 direction register Port P15 Port P15 direction register Pull-up control register 4 Blank spaces are reserved. No access is allowed. <100-pin version> <144-pin version> Address Register pageSymbol Address Register pageSymbol PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 P10 PD10 PUR0 PUR1 PUR2 PCR PUR3 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 P10 PUR0 PUR1 PCR PUR3 P11 PD11 P12 PD12 P13 PD13 P14 PD14 P15 PD15 PUR4 PD10 197 195 197 195 197 195 204 204 206 205 197 195 197 195 197 195 197 195 197 195 197 195 204 206 205 197 195 198 196 204 197 195 197 195 197 195 PUR2 198 196 197 195 Quick Reference by Address

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 1 1. OverviewpuorG08/C61M 1. Overview The M16C/80 group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/80 Series CPU core and are packaged in a 100-pin and 144-pin plastic molded QFP. The peripheral functions of 100-pin and 144-pin are common. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 16M bytes of address space, they are capable of executing instructions at high speed. They also feature a built-in multi- plier and DMAC, making them ideal for controlling office, communications, industrial equipment, and other high-speed processing applications.

1.1 Features

Mask ROM, external ROM and flash memory versions 2.7 to 5.5V (f(X IN)=10MHz) Mask ROM, external ROM and flash memory versions (f(XIN) = 20MHz without software wait,Vcc=5V) sources; 7 levels (including key input interrupt) 1 line (P85 shared with NMI pin) (built-in feedback resistance, and external ceramic or quartz oscillator)

1.2 Applications

Audio, cameras, office equipment, communications equipment, portable equipment, etc.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 2 1. OverviewpuorG08/C61M 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 12 22 32 42 52 62 72 82 93 0 515253545556575859606162636465666768697071727374757677787980 100 P00/D0 P01/D1 P02/D2 P03/D3 P04/D4 P05/D5 P06/D6 P07/D7 0/D 1/D 2/D 3/D 4/D VREF AV SS V CCX IN X OUTV SS RESETCNVssP8 7/X CIN 6/X COUTBYTE 0/A 0(/D 1/A 1(/D 2/A 2(/D 3/A 3(/D 4/A 4(/D 5/A 5(/D 6/A 6(/D 7/A 7(/D 0/A 8(MA0)(/D 1/A 9(MA1)(/D 2/A (MA2)(/D 3/A (MA3)(/D 4/A (MA4)(/D 5/A (MA5)(/D 6/A (MA6)(/D 7/A (MA7)(/D 0/A (MA8) 1/A (MA9) 2/A (MA10) 3/A (MA11) 4/TA2 OUT 6/TA3 OUT 7/TA3 IN P55/HOLD P54/HLDA/ALE P53/BCLK/ALE/CLKOUT VccVss P57/RDY P45/CS2/A21 P46/CS1/A22 AVcc P63/TXD 0 P65/CLK1 P66/RxD1 P67/TXD 1 P61/CLK0 P62/RxD0 P100/AN0 P101/AN1 P102/AN2 P103/AN3 5/ANEX0/CLK 6/ANEX1/T XD 4/SDA 4/SRxD 1/TB1 IN XD 3/SCL 3/STxD 2/TB2 IN XD 3/SDA 3/SRxD 0/TA4 OUT P60/CTS0/RTS0 P64/CTS1/RTS1/CTS0/CLKS1 2/CLK 2/TA1 OUT 2/INT 1/RxD 2/SCL 2/TA0 IN /TB5 IN (Note) 3/INT 5/NMI P97/ADTRG /RXD 4 /SCL4/STxD4 P44/CS3/A20(MA12) 0/TB0 IN /CLK 0/T XD 2/SDA 2/TA0 OUT (Note) 4/INT 1/TA4 IN 3/CTS 2/RTS 2/TA1 IN 5/TA2 IN 5/D /INT3 6/D /INT4 7/D /INT5 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P52/RD/DW P51/WRH/BHE/CASH P50/WRL/WR/CASL P47/CS0/A23 4/DA 1/TB4 IN /CTS 4/RTS 4/SS 3/DA 0/TB3 IN /CTS 3/RTS 3/SS P56/ALE/RAS Note: This port is N-channel open drain output. M16C/80 Group

1.3 Pin Configuration

Figures 1.1 and 1.2 show the pin configuration (top view) for 100-pin and Figure 1.3 shows the pin configu- ration (top view) for 144-pin. PIN CONFIGURATION (top view) Package: 100P6S-A Figure 1.1 Pin configuration for 100-pin version (top view) (1)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 3 1. OverviewpuorG08/C61M PIN CONFIGURATION (top view) 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 12 22 32 42 5 51525354555657585960616263646566676869707172737475 100 P00/D0 P01/D1 P02/D2 P03/D3 P04/D4 P05/D5 P06/D6 P07/D7 P10/D8 P11/D9 P12/D10 3/D 4/D VREF AV SS V CCX IN X OUTV SS RESETCNVssP8 7/X CIN 6/X COUT 4/TA2 OUT 6/TA3 OUT 7/TA3 IN AVcc P100/AN0 P101/AN1 P102/AN2 P103/AN3 0/TA4 OUT 2/INT 3/INT 5/NMI 4/INT P72/CLK2/TA1OUT /V P71/RxD2/SCL2/TA0IN/TB5IN (Note) P70/TXD 2/SDA2/TA0OUT (Note) 5/TA2 IN 3/CTS 2/RTS 2/TA1 IN 5/D /INT 6/D /INT 7/D /INT P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 1/TA4 IN P42/A18(MA10) P43/A19(MA11) 0/A 0(/D 1/A 1(/D 2/A 2(/D 3/A 3(/D 4/A 4(/D 5/A 5(/D 6/A 6(/D 7/A 7(/D 0/A 8(MA0)(/D 1/A 9(MA1)(/D 2/A (MA2)(/D 3/A (MA3)(/D 4/A (MA4)(/D 5/A (MA5)(/D 6/A (MA6)(/D 7/A (MA7)(/D 0/A (MA8) 1/A (MA9) VccVss P95/ANEX0/CLK 4 P96/ANEX1/TXD 4/SDA4/SRxD4 P97/ADTRG /RXD 4/SCL4/STxD4 BYTE 0/TB0 IN /CLK P55/HOLD P54/HLDA/ALE P53/BCLK/ALE/CLKOUT P57/RDY P45/CS2/A21 P46/CS1/A22 P63/TXD 0 P65/CLK1 P66/RxD1 P67/TXD 1 P61/CLK0 P62/RxD0 P60/CTS0/RTS0 P64/CTS1/RTS1/CTS0/CLKS1 P44/CS3/A20(MA12) P52/RD/DW P51/WRH/BHE/CASH P50/WRL/WR/CASL P47/CS0/A23 P56/ALE/RAS 1/TB1 IN XD 3/SCL 3/STxD 2/TB2 IN XD 3/SDA 3/SRxD 3/DA 0/TB3 IN /CTS 3/RTS 3/SS 4/DA 1/TB4 IN /CTS 4/RTS 4/SS Note: This port is N-channel open drain output. Package: 100P6Q-A Figure 1.2 Pin configuration for 100-pin version (top view) (2) M16C/80 Group

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 4 1. OverviewpuorG08/C61M 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 6/ANEX 1/T XD 4/SDA 4/SRxD 5/ANEX 0/CLK 2/TB 2IN XD 3/SDA 3/SRxD 1/TB 1IN XD 3/SCL 3/STxD 0/TB 0IN /CLK3P14 P14 P14 P14 P14 P14 P14 BYTECNV SS 7/X CIN 6/X COUT X OUT V SS X IN V CC 0/TA 4OUT 7/TA 3IN 6/TA 3OUT 4/TA 2OUT 2/CLK 2/TA 1OUT (Note) 1/R XD 2/SCL 2/TA 0IN /TB 5IN (Note) 4/DA 1/TB 4IN /CTS 4/RTS 4/SS 3/DA 0/TB 3IN /CTS 3/RTS 3/SS RESET P8 5/NMI 4/INT 3/INT 2/INT 1/TA 4IN 5/TA 2IN 3/CTS 2/RTS 2/TA 1IN P70/TXD 2/SDA2/TA0OUT P67/TXD 1 VCC P66/RXD 1 VSS P65/CLK1 P63/TXD 0 P62/RXD 0 P61/CLK0 P137 P136 P135 P134 P133 VSS P132 VCC P131 P130 P53/BCLK/ALE/CLKOUT P127 P126 P125 P64/CTS1/RTS1/CTS0/CLKS1 P60/CTS0/RTS0 P56/ALE/RAS P55/HOLD P54/HLDA/ALE P52/RD/DW P51/WRH/BHE/CASH P50/WRL/WR/CASL P47/CS0/A23 P46/CS1/A22 P45/CS2/A21 P44/CS3/A20(MA12) 3/A (MA11) V CC 2/A (MA10) V SS 1/A (MA9) 0/A (MA8) 7/A (MA7)(/D 6/A (MA6)(/D 5/A (MA5)(/D 4/A (MA4)(/D 3/A (MA3)(/D 2/A (MA2)(/D 1/A 9(MA1)(/D P12 P12 P12 P12 P12 V CC 0/A 8(MA0)(/D 7/A 7(/D 6/A 6(/D 5/A 5(/D 4/A 4(/D 3/A 3(/D 2/A 2(/D 1/A 1(/D 0/A 0(/D V SS 4/D 3/D 2/D 1/D 5/D /INT3 6/D /INT4 7/D /INT5 P10/D8 P07/D7 P06/D6 P05/D5 P04/D4 P114 P113 P112 P111 P110 P03/D3 P02/D2 P01/D1 P00/D0 P157 P156 P155 P154 P153 P152 P151 VSS P150 VCC P103/AN3 P102/AN2 P101/AN1 AV SS P100/AN0 VREF AV CC P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P97/ADTRG /RXD 4 /SCL4/STxD4 7374757677798081828384858687888990919293949596979899100101102103104105106107108 78 P57/RDY 123 4 7 6 8 9 1 01 1 1 2 1 31 41 5 1 6 1 7 1 81 92 0 2 1 2 22 32 42 52 62 72 82 93 05 31 32 33 34 35 36 Note: This port is N-channel open drain output. M16C/80 Group PIN CONFIGURATION (top view) Package: 144P6Q-A Figure 1.3 Pin configuration for 144-pin version (top view)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 5 1. OverviewpuorG08/C61M

1.4 Block Diagram

Figure 1.4 is a block diagram of the M16C/80 group. Figure 1.4 Block diagram of the M16C/80 group /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines R0LR0H R1H R1L /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines I/O ports 88 8 8 8 8 8 Internal peripheral functions Timer Timer TA0 (16 bits) Timer TA1 (16 bits) Timer TA2 (16 bits) Timer TA3 (16 bits) Timer TA4 (16 bits) Timer TB0 (16 bits) Timer TB1 (16 bits) Timer TB2 (16 bits) Timer TB3 (16 bits) Timer TB4 (16 bits) Timer TB5 (16 bits) Watchdog timer (15 bits) D/A converter (8 bits X 2 channels) A/D converter (10 bits X 8 channels Expandable up to 10 channels) UART /clock synchronous SI/O (8 bits X 5 channels) XY converter (16 bits X 16 bits) CRC arithmetic circuit (CCITT) (Polynomial : X +X +X +1) System clock generator XIN - XOUT XCIN - XCOUT Memory DRAM controller M16C/80 series 16-bit CPU core Registers R0H R0L R1H R1L FB SB DRAM controller Multiplier Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Port P7 Port P8 Port P8 Port P9 Port P10 FLG INTB ISP USP PC SVF SVP VCT 1216 5 ROM (Note 1) RAM (Note 2) Note 1: ROM size depends on MCU type. Note 2: RAM size depends on MCU type. Note 3: Ports P11 to P15 exist in 144-pin version. Port P15 Port P14 Port P13 Port P12 Port P11 87 8 8 5 (Note 3)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 6 1. OverviewpuorG08/C61M Item Performance Number of basic instructions 106 instructions Shortest instruction execution time 50ns(f(X IN)=20MHz) Memory See ROM expansion figure. capacity 10 to 24 K bytes I/O port P0 to P10 (except P8 5) 8-bit x 10, 7-bit x 1 P0 to P15 (except P85) 8-bit x 13, 7-bit x 2, 5-bit x 1 Input port 1 bit x 1 Multifunction 16 bits x 5 timer 16 bits x 6 Serial I/O (UART or clock synchronous) x 5 A/D converter 10 bits x (8 + 2) channels D/A converter 8 bits x 2 DMAC 4 channels DRAM controller CAS before RAS refresh, self-refresh, EDO, FP CRC calculation circuit CRC-CCITT XY converter 16 bits X 16 bits Watchdog timer 15 bits x 1 (with prescaler) Interrupt 29 internal and 8 external sources, 5 software sources, 7 levels Clock generating circuit 2 built-in clock generation circuits (built-in feedback resistance, and external ceramic or quartz oscillator) Supply voltage 4.2 to 5.5V (f(X IN)=20MHz) Mask ROM, external ROM and flash memory versions 2.7 to 5.5V (f(X IN)=10MHz) Mask ROM, external ROM and flash memory versions Power consumption 45mA (f(XIN) = 20MHz without software wait,Vcc=5V) Mask ROM 128 Kbytes version I/O 5V characteristics 5mA Memory expansion Available (up to 16M bytes) Operating ambient temperature –40 to 85oC Device configuration CMOS high performance silicon gate Package 100-pin and 144-pin plastic mold QFP Table 1.1 Performance outline of M16C/80 group

1.5 Performance Outline

Table 1.1 is a performance outline of M16C/80 group. ROM RAM 100-pin 144-pin TA0, TA1, TA2, TA3,TA4 TB0, TB1, TB2, TB3, TB4, TB5 UART0, UART1, UART2, UART3, UART4 I/O withstand voltage Output current

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 7 1. OverviewpuorG08/C61M Renesas plans to release the following products in the M16C/80 group: (1) Support for mask ROM version, external ROM version and flash memory version (2) ROM capacity (3) Package 100P6S-A : Plastic molded QFP (mask ROM version and flash memory version) 100P6Q-A : Plastic molded QFP (mask ROM version and flash memory version) 144P6Q-A : Plastic molded QFP (mask ROM version and flash memory version) The M16C/80 group products currently supported are listed in Table 1.2. ROM Size (Byte) External ROM 128K Mask ROM version Flash memory version External ROM version 256K M30800MC-XXXFP/GP M30800FCFP/GP M30803FGFP/GPM30803MG-XXXFP/GP M30802MC-XXXGP M30802FCGP M30805FGGP M30802SGP M30805MG-XXXGP M30805SGP M30805SGP-BL M30803SFP/GP-BL M30800SFP/GP-BL M30802SGP-BL M30803SFP/GP M30800SFP/GP RAM capacityROM capacity Package type RemarksType No 10K bytes 100P6S-A Mask ROM versionM30800MC-XXXFP 128K bytes M30800MC-XXXGP M30800FCFP M30800FCGP Flash memory version 100P6Q-A 100P6S-A 100P6Q-A M30803FGFP M30803FGGP 100P6S-A 100P6Q-A 20K bytes256K bytes 20K bytes 100P6S-AM30803MG-XXXFP 256K bytes M30803MG-XXXGP 100P6Q-A 10K bytes128K bytes 10K bytes External ROM version with built-in boot loader 144P6Q-A M30800SFP-BL 10K bytes External ROM version 24K bytes M30805SGP 24K bytes M30802MC-XXXGP M30805MG-XXXGP M30802FCGP 144P6Q-A 144P6Q-AM30805FGGP M30800SFP M30800SGP M30802SGP M30803SGP M30803SFP M30800SGP-BL M30802SGP-BL M30803SFP-BL M30803SGP-BL M30805SGP-BL 144P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 144P6Q-A 144P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 144P6Q-A 144P6Q-A Table 1.2 M16C/80 group Figure 1.5 ROM expansion

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 8 1. OverviewpuorG08/C61M Package type: FP : Package 100P6S-A GP : Package 100P6Q-A, 144P6Q-A ROM No. Omitted for blank external ROM version and flash memory version ROM capacity: C : 128K bytes G : 256K bytes Memory type: M : Mask ROM version S : External ROM version F : Flash memory version Type No. M 3 0 8 0 2 M C – X X X G P – BL M16C/80 Group M16C Family Shows RAM capacity, pin count, etc (The value itself has no specific meaning) Boot loader Figure 1.6 Product Numbering System

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 9 1. OverviewpuorG08/C61M VCC , VSS CNV SS XIN XOUT BYTE AV CC AV SS VREF P00 to P07 D 0 to D7 P10 to P17 D 8 to D15 P20 to P27 A0 to A7 A0/D0 to A7/D7 P30 to P37 A8 to A15 A8/D8 to A15/D15 Signal name Power supply input CNV SS Reset input Clock input Clock output External data bus width select input Analog power supply input Reference voltage input I/O port P0 I/O port P1 I/O port P2 I/O port P3 Supply 4.2 (2.7) to 5.5 V to the V CC pin. Supply 0 V to the VSS pin. Function This pin switches between processor modes. Connect it to the VSS when operating in single-chip or memory expansion mode after reset. Connect it to the V CC when in microprocessor mode after reset. An “L” on this input resets the microcomputer. These pins are provided for the main clock generating circuit. Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. This pin selects the width of an data bus in the external area 3. A 16- -bit width is selected when this input is “L”; an 8-bit width is selected when this input is “H ”. This input must be fixed to either “H ” or “L”. When not using the external bus, connect this pin to VSS . This pin is a power supply input for the A/D converter. Connect this pin to VCC . This pin is a power supply input for the A/D converter. Connect this pin to VSS . This pin is a reference voltage input for the A/D converter. This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When set for input in single chip mode, the user can specify in units of four bits via software whether or not they are tied to a pull-up resistance. In memory expansion and microprocessor mode, an built-in pull-up resistance cannot be used. However, it is possible to select pull-up resistance presence to the usable port as I/ O port by setting. When set as a separate bus, these pins input and output data (D 0–D 7). This is an 8-bit I/O port equivalent to P0. P15 to P17 also function as external interrupt pins as selected by software. When set as a separate bus, these pins input and output data (D8–D 15). This is an 8-bit I/O port equivalent to P0. These pins output 8 low-order address bits (A0–A7). If a multiplexed bus is set, these pins input and output data (D0–D 7) and output 8 low-order address bits (A0–A7) separated in time by multiplexing. This is an 8-bit I/O port equivalent to P0. These pins output 8 middle-order address bits (A8–A15). If the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (D8–D 15) and output 8 middle-order address bits (A8–A15) separated in time by multiplexing. Pin name I I I O I I I/O I/O I/O I/O I/O type Analog power supply input I/O O I/O I/O O I/O RESET MA0 to MA7 If accessing to DRAM area, these pins output row address and column address separated in time by multiplexing. O

1.6 Pin Description (1)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 10 1. OverviewpuorG08/C61M Pin Description (2) Signal name FunctionPin name I/O type I/O port P5 I/O I/O I/O I/O I/O I/O I I/O I/O I/O port P6 I/O port P7 I/O port P8 I/O port P85 I/O port P9 I/O port P10 P50 to P57 P60 to P67 P70 to P77 P80 to P84, P86, P87, P85 P90 to P97 P100 to P107 This is an 8-bit I/O port equivalent to P0. P53 in this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of the same frequency as XCIN as selected by software. O O O O O I O I This is an 8-bit I/O port equivalent to P0. When set for input in single chip mode, microprocessor mode and memory expansion mode the user can specify in units of four bits via software whether or not they are tied to a pull-up resistance. Pins in this port also function as UART0 and UART1 I/O pins as selected by software. This is an 8-bit I/O port equivalent to P6 (P7 0 and P71 are N-channel open drain output). Pins in this port also function as timer A0–A3, timer B5 or UART2 I/O pins as selected by software. This is an 8-bit I/O port equivalent to P6. Pins in this port also function as UART3 and UART4 I/O pins, Timer B0–B4 input pins, D/A converter output pins, A/D converter extended input pins, or A/D trigger input pins as selected by software. This is an 8-bit I/O port equivalent to P6. Pins in this port also function as A/D converter input pins. Furthermore, P10 4–P107 also function as input pins for the key input interrupt function. WRL / WR, WRH / BHE, RD, BCLK, HLDA, HOLD, ALE, RDY Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE signals. WRL and WRH, and BHE and WR can be switched using software control. WRL, WRH, and RD selected With a 16-bit external data bus, data is written to even addresses when the WRL signal is “L” and to the odd addresses when the WRH signal is “L”. Data is read when RD is “L”. WR, BHE, and RD selected Data is written when WR is “L”. Data is read when RD is “L”. Odd addresses are accessed when BHE is “L”. Use this mode when using an 8-bit external data bus. While the input level at the HOLD pin is “L”, the microcomputer is placed in the hold state. While in the hold state, HLDA outputs an “L” level. ALE is used to latch the address. While the input level of the RDY pin is “L”, the bus of microcomputer is in the wait state. P80 to P84, P86, and P87 are I/O ports with the same functions as P6. Using software, they can be made to function as the I/O pins for timer A4 and the input pins for external interrupts. P8 6 and P87 can be set using software to function as the I/O pins for a sub clock generation circuit. In this case, connect a quartz oscillator between P8 6 (XCOUT pin) and P87 (XCIN pin). P85 is an input-only port that also functions for NMI. The NMI interrupt is generated when the input at this pin changes from “H ” to “L”. The NMI function cannot be canceled using software. The pull-up cannot be set for this pin. DW, CASL, CASH, RAS O O O O When accessing to DRAM area while DW signal is “L”, write to DRAM. CASL and CASH show timing when latching to line address. When CASL accesses to even address, and CASH to odd, these two pins become “L”. RAS signal shows timing when latching to row address. P40 to P47 I/O port P4 This is an 8-bit I/O port equivalent to P0.I/O O O CS 0 to CS3 These pins output CS0–CS 3 signals. CS0–CS 3 are chip select signals used to specify an access space. A16 to A22, A23 O These pins output 8 high-order address bits (A16–A22, A23). Highest address bit (A23) outputs inversely. MA8 to MA12 If accessing to DRAM area, these pins output row address and column address separated in time by multiplexing.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 11 1. OverviewpuorG08/C61M Signal name FunctionPin name I/O type II/OI/O port P11P110 to P114 This is an 5-bit I/O port equivalent to P6. II/OI/O port P12P120 to P127 This is an 8-bit I/O port equivalent to P6. II/OI/O port P13P130 to P137 This is an 8-bit I/O port equivalent to P6. II/OI/O port P14P140 to P146 This is an 7-bit I/O port equivalent to P6. II/OI/O port P15P150 to P157 This is an 8-bit I/O port equivalent to P6. (Note) (Note) (Note) (Note) (Note) Pin Description (3) Note : Port P11 to P15 exist in 144-pin version. Operation of Functional Blocks The M16C/80 group accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/logic opera- tions. Also included are peripheral units such as timers, serial I/O, D/A converter, DMAC, CRC calcu- lation circuit, A/D converter, DRAM controller and I/O ports. The following explains each unit.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 13 3. Central Processing Unit (CPU)puorG08/C61M 3. Central Processing Unit (CPU) The CPU has a total of 28 registers shown in Figure 3.1. Eight of these registers (R0, R1, R2, R3, A0, A1, SB and FB) come in two sets; therefore, these have two register banks. Figure 3.1 Central processing unit register b23 b7 b0 Flag register Address register (Note) Static base register (Note) Frame base register (Note) User stack pointer Interrupt stack pointer Interrupt table register Flag save register PC save register Vector register DMA mode register DMA transfer count register DMA transfer count reload register DMA memory address register DMA SFR address register DMA memory address reload register b15 b0 b15 b0 b23 b15 b23 Data register (Note) FLG R0H R1H SB FB USP ISP INTB PC SVF VCT DMD0 DMD1 DCT0 DCT1 DRC0 DRC1 DMA0 DMA1 DSA0 DSA1 DRA0 DRA1 SVP DMAC related register Program counter High-speed interrupt register General register b31 R0L R1L Note: These registers have two register banks.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 14 3. Central Processing Unit (CPU)puorG08/C61M (1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, R3, R2R0 and R3R1) Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and low-order bits as (R0L/R1L). Registers R2 and R0, as well as R3 and R1 can use as 32-bit data registers (R2R0/R3R1). (2) Address registers (A0 and A1) Address registers (A0 and A1) are configured with 24 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing. (3) Static base register (SB) Static base register (SB) is configured with 24 bits, and is used for SB relative addressing. (4) Frame base register (FB) Frame base register (FB) is configured with 24 bits, and is used for FB relative addressing. (5) Program counter (PC) Program counter (PC) is configured with 24 bits, indicating the address of an instruction to be executed. (6) Interrupt table register (INTB) Interrupt table register (INTB) is configured with 24 bits, indicating the start address of an interrupt vector table. (7) User stack pointer (USP), interrupt stack pointer (ISP) Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config- ured with 24 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG). Set USP and ISP to an even number so that execution efficiency is increased. (8) Save flag register (SVF) This register consists of 16 bits and is used to save the flag register when a high-speed interrupt is generated.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 15 3. Central Processing Unit (CPU)puorG08/C61M (9) Save PC register (SVP) This register consists of 24 bits and is used to save the program counter when a high-speed interrupt is generated. (10) Vector register (VCT) This register consists of 24 bits and is used to indicate the jump address when a high-speed interrupt is generated. (11) DMA mode registers (DMD0/DMD1) These registers consist of 8 bits and are used to set the transfer mode, etc. for DMA. (12) DMA transfer count registers (DCT0/DCT1) These registers consist of 16 bits and are used to set the number of DMA transfers performed. (13) DMA transfer count reload registers (DRC0/DRC1) These registers consist of 16 bits and are used to reload the DMA transfer count registers. (14) DMA memory address registers (DMA0/DMA1) These registers consist of 24 bits and are used to set a memory address at the source or destination of DMA transfer. (15) DMA SFR address registers (DSA0/DSA1) These registers consist of 24 bits and are used to set a fixed address at the source or destination of DMA transfer. (16) DMA memory address reload registers (DRA0/DRA1) These registers consist of 24 bits and are used to reload the DMA memory address registers.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 16 3. Central Processing Unit (CPU)puorG08/C61M (17) Flag register (FLG) Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 3.2 shows the flag register (FLG). The following explains the function of each flag:

Bit 0: Carry flag (C flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
Bit 1: Debug flag (D flag) This flag enables a single-step interrupt. When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is cleared to “0” when the interrupt is acknowledged.
Bit 2: Zero flag (Z flag) This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
Bit 3: Sign flag (S flag) This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”.
Bit 4: Register bank select flag (B flag) This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
Bit 5: Overflow flag (O flag) This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
Bit 6: Interrupt enable flag (I flag) This flag enables a maskable interrupt. An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0” when the interrupt is acknowledged.
Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected when this flag is “1”. This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos. 0 to 31 is executed.
Bits 8 to 11: Reserved area

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 17 3. Central Processing Unit (CPU)puorG08/C61M Figure 3.2 Flag register (FLG) Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area Flag register (FLG) /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines CDZSBOIUIPL b0b15

Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled.
Bit 15: Reserved area

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 19 4. ResetpuorG08/C61M Table 4.1 shows the statuses of the other pins while the RESET pin level is “L”. Figures 4.3 and 4.4 show the internal status of the microcomputer immediately after the reset is cancelled. Table 4.1 Pin status when RESET pin level is “L” Status CNV SS = VCC CNV SS = VSS BYTE = VSS BYTE = VCC Pin name P2, P3, P4 P50 P51 P52 P53 P54 P55 P56 P57 P6, P7, P80 to P84, P86, P87, P9, P10, Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) Data input (floating) Data input (floating) Address output (undefined) BCLK output RAS output WR output (“H ” level is output) RD output (“H ” level is output) RDY input (floating) Input port (floating) BCLK output BHE output (undefined) HLDA output (The output value depends on the input to the HOLD pin) HOLD input (floating) Data input (floating) Address output (undefined) Input port (floating) Input port (floating) RDY input (floating) RAS output HOLD input (floating) HLDA output (The output value depends on the input to the HOLD pin) RD output (“H ” level is output) BHE output (undefined) WR output (“H ” level is output) Note :Port P11 to P15 exist in 144-pin vrsion. P11, P12, P13, P14, P15 (Note) Input port (floating) Input port (floating) Input port (floating)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 20 4. ResetpuorG08/C61M Figure 4.3 Device's internal status after a reset is cleared x : Nothing is mapped to this bit ? : Undefined The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. Note 1: When the VCC level is applied to the CNVSS pin, it is 0316 at a reset. Note 2: When the BYTE pin is "L", the third bit is "1". When the BYTE pin is "H", the third bit is "0". (1) (0004 16)···Processor mode register 0 (Note1) 8016 (2) (0005 16)···Processor mode register 1 (3) (0006 16)···System clock control register 0 (4) (0007 16)···System clock control register 1 (5) (0008 16)···Wait control register (6) (0009 16)···Address match interrupt enable register 00 (7) Protect register (000A 16)··· 000 (10) (000F16)···Watchdog timer control register 0 0? 0? ? ? ? (12) (001416)···Address match interrupt register 1 (001816)··· 0016 0016 (004016)···DMAM control register ?? ?? ? DMA0 interrupt control register (21) (006B16)··· UART0 receive interrupt control register ? 0 0 0 (22) (006C16)··· ? 0 0 0 (23) (006D16)··· Key input interrupt control register ? 0 0 0 (20) (006A16)··· Bus collision detection(UART3) interrupt control register 0 0 0? (8) External data bus width control register (Note 2) (000B16)··· (001016)···Address match interrupt register 0 (001116)··· (001216)··· 0016 0016 (11) Timer B5 interrupt control register (15) DMA2 interrupt control register ?000 (16) UART2 receive/ACK interrupt control register ?000 (17) Timer A0 interrupt control register ?000 (18) (006816)··· UART3 receive/ACK interrupt control register (19) (006916)··· (24) A/D conversion interrupt control register (25) (26) (007416)··· (007616)··· ? 0 0 0 ? 0 0 0 0016 (27) (28) (29) (30) UART1 transmit interrupt control register (31) (32) (33) (34) (35) (36) (37) Timer B0 interrupt control register Timer B2 interrupt control register (38) Timer B3 interrupt control register (39) INT5 interrupt control register (40) INT3 interrupt control register (41) INT1 interrupt control register (45) Three-phase output buffer register 0 (46) Three-phase output buffer register 1 Three-phase PWM control register 0 (43) Three-phase PWM control register 1 (44) (42) Timer B3,4,5 count start flag (47) Timer B3 mode register (48) Timer B4 mode register (49) Timer B5 mode register (50) UART4 transmit/receive control register 1 UART4 transmit/receive control register 0 (56) UART4 transmit/receive mode register (54) (55) (52) (53) UART4 special mode register 2 (51) (9) (000C 16)···Main clock divided register 0816 (13)Address match interrupt register 2 (14)Address match interrupt register 3 (001516)··· 0016 (001616)··· 0016 (001916)··· 0016 (001A16)··· 0016 (001C16)··· 0016 (001D16)··· 0016 (001E16)··· 0016 Timer A2 interrupt control register UART4 receive/ACK interrupt control register Timer A4 interrupt control register UART1 receive interrupt control register Timer B1 interrupt control register Bus collision detection(UART2) interrupt control register DMA1 interrupt control register UART2 transmit/NACK interrupt control register UART3 transmit/NACK interrupt control register Timer A1 interrupt control register UART4 receive/NACK interrupt control register Timer A3 interrupt control register DMA3 interrupt control register Bus collision detection(UART4) interrupt control register UART0 transmit interrupt control register INT4 interrupt control register INT2 interrupt control register INT0 interrupt control register Exit priority register XY control register UART4 special mode register Timer B4 interrupt control register (006E 16)··· (006F16)··· (007016)··· (007116)··· (007216)··· 000 2016 FF16 00001 0016 ?000 ?000 ?000 ?000 (007816)··· (007A16)··· (007C16)··· (007E16)··· ? 0 0 0 ? 000 ? 000 ? 000 (008816)··· (008916)··· (008A16)··· (008B16)··· (008E16)··· (008F16)··· (009016)··· (009116)··· (009216)··· ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 000 ? 000 ? 000 00? 0000 00? 0000 (030916)··· (030A16)··· 3F16 (030B16)··· 3F16 (030816)··· 0016 (030016)··· (031B16)··· (031C16)··· (009316)··· (009416)··· (009616)··· (009C16)··· (009E16)··· (009F16)··· (02E016)··· (02F616)··· ? 0 0 0 ? 0 0 0 ? 0 0 0 (009A16)··· ? 000 ? 000 ? 000 0 000 0016 (02F716)··· 0016 (02F816)··· 0016 (02FC16)··· 0816 (02FD16)··· 0216 (62) (63) (60) (59) (61) (64) (65) (66) (57) (58) UART4 special mode register 3 (02F516)··· 0016 (67) 000 ?0000 000

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 21 4. ResetpuorG08/C61M Trigger select flag Up-down flag Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Timer A3 mode register Timer A4 mode register One-shot start flag UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 UART transmit/receive control register 2 DMA0 cause select register DMA1 cause select register UART0 transmit/receive mode register UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 UART1 transmit/receive mode register A/D control register 2 A/D control register 0 A/D control register 1 Count start flag Clock prescaler reset flag x : Nothing is mapped to this bit ? : Undefined The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. Port P0 direction register Port P1 direction register Port P2 direction register Port P3 direction register Port P4 direction register Port P5 direction register Port P6 direction register Port P7 direction register Port P8 direction register Port P9 direction register Port P10 direction register Pull-up control register 0 Pull-up control register 1 Pull-up control register 2 Port control register Frame base register (FB) Address registers (A0/A1) Interrupt table register (INTB) User stack pointer (USP) Interrupt stack pointer (ISP) Static base register (SB) Flag register (FLG) Data registers (R0/R1/R2/R3) (78) (77) (79) (80) (83) (84) (85) (86) (82) (76) (81) (90) (91) (92) (93) (94) (95) (87) (88) (89) (96) (74) (73) (71) (72) (68) (69) (70) (75) (97) (99) (98) (103) (104) (105) (100) (114) (115) (116) (117) (118) (119) (120) (121) (122) (123) (124) (125) (126) (127) (132) (130) (131) (128) (129) (132) (136) (137) (138) (133) (135) (142) (143) (139) (141) (140) (109) (112) (113) (106) (107) (033D 16)··· (034016)··· (034116)··· (034216)··· (035716)··· (035816)··· (035916)··· (034416)··· (035616)··· (033C16)··· 0216 0016 0016 (034316)··· 0016 0016 (035D16)··· (036016)··· (036416)··· (036516)··· (036816)··· (036C16)··· (035A16)··· 0016 0816 0216(036D16)··· 001 00 0 0 (033716)··· 0016 (032C16)··· (033616)··· (032D16)··· (032516)··· (032716)··· (032816)··· 0816 0016 0016 0016 (031F16)··· 000000 0216 0016 (033816)··· 0016 000 0?000 000 0?000 000 0?000 000 0?000 000 0?000 00? 0000 0016 0816 0216 (037016)··· 0 0000 0000000 000000 (037916)··· (037816)···0 00000(039616)··· (039716)··· 0016 (108) D/A control register (039C16)··· 0016 00000(039416)··· ??? 0000000 000000 (037B16)··· (037A16)···0 0016 0000 0 (03C216)··· (03C316)··· (03C616)··· (03C716)··· (03CA16)··· (03DA16)··· (03DB16)··· (03E216)··· (03E316)··· (03E616)··· (03E716)··· (03EA16)··· (03EB16)··· (03F016)··· 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 000016 00000016 00000016 (03F116)··· X016 0(03FF16)··· 00000016 00000016 00000016 000016 0016 00000016 000 0 0 0 (03AF16)··· (03B016)··· (03B216)··· (03B316)··· (03B416)··· (03B516)··· (03B616)··· 00000 0(03B116)··· 0 00 0 Interrupt cause select register UART3 transmit/receive control register 1 UART3 transmit/receive control register 0 UART3 transmit/receive mode register UART3 special mode register 3 UART3 special mode register UART2 transmit/receive control register 1 UART2 transmit/receive control register 0 UART2 transmit/receive mode register UART2 special mode register 2 UART2 special mode register DMA2 cause select register DMA3 cause select register Pull-up control register 3 (Note 2) DMA mode register (DMD0/DMD1) DMA transfer count register (DCT0/DCT1) DMA transfer count reload register (DRC0/DRC1) DMA memory address register (DMA0/DMA1) DMA SFR address register (DSA0/DSA1) DMA memory address reload register (DRA0/DRA1)Function select register C Function select register A0 Function select register B0 Function select register A1 Function select register A2 Function select register A3 Function select register B1 Function select register B2 (032616)··· 0016UART3 special mode register 2 (033516)···UART2 special mode register 3 (03B716)···Function select register B30 00 0000 (146) (147) (145) (144) Port P11 direction register (Note 2) (03CB16)··· Port P12 direction register (Note 2) (03CE16)··· 0016 Port P13 direction register (Note 2) (03CF16)··· 0016 Port P14 direction register (Note 2) (03D216)··· Port P15 direction register (Note 2) (03D316)··· 0016 0000 0 0000 000 (03DC16)··· X016Pull-up control register 4 (Note 2) (148) (152) (153) (149) (151) (150) (037716)···Flash memory control register 0 (Note 1) 00 0 0 10(102) (101) 0? ??? ?(037616)···Flash memory control register 1 (Note 1) ? Note 1:This register exists in the flash memory version. Note 2:This register exists in 144-pin version. (111) (110) (154) (155)00 0016 Figure 4.4 Device's internal status after a reset is cleared

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 22 5. SFRpuorG08/C61M 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C 16 001D 16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 004016 004116 004216 004316 004416 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C 16 006D 16 006E16 006F16 007016 007116 007216 007316 007416 007516 007616 007716 007816 007916 007A16 007B16 007C 16 007D 16 007E16 007F16 008016 008116 008216 008316 008416 008516 008616 008716 008816 008916 008A16 008B16 008C 16 008D 16 008E16 008F16 009016 009116 009216 009316 009416 009516 009616 009716 009816 009916 009A16 009B16 009C 16 009D 16 009E16 009F16 00A016 00A116 00A216 00A316 00A416 Watchdog timer start register (WDTS) Watchdog timer control register (WDC) Processor mode register 0 (PM0) Address match interrupt register 0 (RMAD0) Address match interrupt register 1 (RMAD1) Wait control register (WCR) System clock control register 0 (CM0) System clock control register 1 (CM1) Address match interrupt enable register (AIER) Protect register (PRCR) Processor mode register 1(PM1) External data bus width control register (DS) Main clock division register (MCD) Address match interrupt register 2 (RMAD2) Address match interrupt register 3 (RMAD3) Emulator interrupt vector table register (EIAD) Emulator interrupt detect register (EITD) Emulator protect register (EPRR) ROM areaset register (ROA) Debug monitor area set register (DBA) Expansion area set register 0 (EXA0) Expansion area set register 1 (EXA1) Expansion area set register 2 (EXA2) Expansion area set register 3 (EXA3) DRAM control register (DRAMCONT) DRAM refresh interval set register (REFCNT) Timer A1 interrupt control register (TA1IC) UART0 transmit interrupt control register (S0TIC) Timer A0 interrupt control register (TA0IC) Timer A2 interrupt control register (TA2IC) UART0 receive interrupt control register (S0RIC) UART2 transmit/NACK interrupt control register (S2TIC) UART1 receive interrupt control register (S1RIC) DMA2 interrupt control register (DM2IC) DMA0 interrupt control register (DM0IC) Key input interrupt control register (KUPIC) A/D conversion interrupt control register (ADIC) Bus collision detection(UART3) interrupt control register (BCN3IC) UART2 receive/ACK interrupt control register (S2RIC) INT1 interrupt control register (INT1IC) Timer B0 interrupt control register (TB0IC) Timer B2 interrupt control register (TB2IC) Timer A3 interrupt control register (TA3IC) INT2 interrupt control register (INT2IC) INT0 interrupt control register (INT0IC) Timer B1 interrupt control register (TB1IC) Timer A4 interrupt control register (TA4IC) INT3 interrupt control register (INT3IC) Timer B5 interrupt control register (TB5IC) Timer B4 interrupt control register (TB4IC) Timer B3 interrupt control register (TB3IC) INT5 interrupt control register (INT5IC) INT4 interrupt control register (INT4IC) UART3 receive/ACK interrupt control register (S3RIC) UART4 receive/ACK interrupt control register (S4RIC) UART3 transmit/NACK interrupt control register (S3TIC) UART4 transmit/NACK interrupt control register (S4TIC) Exit priority register (RLVL) UART1 transmit interrupt control register (S1TIC) DMA1 interrupt control register (DM1IC) DMA3 interrupt control register (DM3IC) Bus collision detection(UART2) interrupt control register (BCN2IC) Bus collision detection(UART4) interrupt control register (BCN4IC) * * As this register is used exclusively for debugger purposes, user cannot use this. Do not access to the register. (The blank area is reserved and cannot be used by user.) Figure 5.1 Location of peripheral unit control registers (1) 5. SFR

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 23 5. SFRpuorG08/C61M Figure 5.2 Location of peripheral unit control registers (2) 030016 030116 030216 030316 030416 030516 030616 030716 030816 030916 030A16 030B16 030C 16 030D 16 030E16 030F16 031016 031116 031216 031316 031416 031516 031616 031716 031816 031916 031A16 031B16 031C 16 031D 16 031E16 031F16 032016 032116 032216 032316 032416 032516 032616 032716 032816 032916 032A16 032B16 032C 16 032D 16 032E16 032F16 033016 033116 033216 033316 033416 033516 033616 033716 033816 033916 033A16 033B16 033C 16 033D 16 033E16 033F16 02C0 16 02C1 16 02C2 16 02C3 16 02C4 16 02C5 16 02C6 16 02C7 16 02C8 16 02C9 16 02CA 16 02CB 16 02CC 16 02CD 16 02CE 16 02CF 16 02D0 16 02D1 16 02D2 16 02D3 16 02D4 16 02D5 16 02D6 16 02D7 16 02D8 16 02D9 16 02DA 16 02DB 16 02DC 16 02DD 16 02DE 16 02DF 16 02E016 02E116 02E216 02E316 02E416 02E516 02E616 02E716 02E816 02E916 02EA 16 02EB 16 02EC 16 02ED 16 02EE 16 02EF 16 02F016 02F116 02F216 02F316 02F416 02F516 02F616 02F716 02F816 02F916 02FA 16 02FB 16 02FC 16 02FD 16 02FE 16 02FF16 X0 register (X0R) Y0 register (Y0R) X1 register (X1R) Y1 register (Y1R) X2 register (X2R) Y2 register (Y2R) X3 register (X3R) Y3 register (Y3R) X4 register (X4R) Y4 register (Y4R) X5 register (X5R) Y5 register (Y5R) X6 register (X6R) Y6 register (Y6R) X7 register (X7R) Y7 register (Y7R) X8 register (X8R) Y8 register (Y8R) X9 register (X9R) Y9 register (Y9R) X10 register (X10R) Y10 register (Y10R) X11 register (X11R) Y11 register (Y11R) X12 register (X12R) Y12 register (Y12R) X13 register (X13R) Y13 register (Y13R) X14 register (X14R) Y14 register (Y14R) X15 register (X15R) Y15 register (Y15R) XY control register (XYC) UART4 special mode register (U4SMR) UART4 receive buffer register (U4RB) UART4 transmit buffer register (U4TB) UART4 transmit/receive control register 0 (U4C0) UART4 transmit/receive mode register (U4MR) UART4 transmit/receive control register 1 (U4C1) UART4 bit rate generator (U4BRG) UART4 special mode register 2 (U4SMR2) Timer A1-1 register (TA11) Timer A2-1 register (TA21) Dead time timer(DTT) Timer B2 interrupt occurrence frequency set counter(ICTB2) Three-phase PWM control register 0(INVC0) Three-phase PWM control register 1(INVC1) Thrree-phase output buffer register 0(IDB0) Thrree-phase output buffer register 1(IDB1) Timer B3 register (TB3) Timer B4 register (TB4) Timer B5 register (TB5) Timer B3, 4, 5 count start flag (TBSR) Timer B3 mode register (TB3MR) Timer B4 mode register (TB4MR) Timer B5 mode register (TB5MR) Interrupt cause select register (IFSR) UART2 special mode register (U2SMR) UART2 receive buffer register (U2RB) UART2 transmit buffer register (U2TB) UART2 transmit/receive control register 0 (U2C0) UART2 transmit/receive mode register (U2MR) UART2 transmit/receive control register 1 (U2C1) UART2 bit rate generator (U2BRG) Timer A4-1 register (TA41) UART2 special mode register 2 (U2SMR2) UART3 special mode register (U3SMR) UART3 receive buffer register (U3RB) UART3 transmit buffer register (U3TB) UART3 transmit/receive control register 0 (U3C0) UART3 transmit/receive mode register (U3MR) UART3 transmit/receive control register 1 (U3C1) UART3 bit rate generator (U3BRG) UART3 special mode register 2 (U3SMR2) UART4 special mode register 3 (U4SMR3) UART2 special mode register 3 (U2SMR3) UART3 special mode register 3 (U3SMR3) (The blank area is reserved and cannot be used by user.)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 24 5. SFRpuorG08/C61M Figure 5.3 Location of peripheral unit control registers (3) 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C 16 034D 16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C 16 035D 16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C 16 036D 16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C 16 037D 16 037E16 037F16 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C 16 038D 16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C 16 039D 16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA 16 03AB 16 03AC 16 03AD 16 03AE 16 03AF 16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA 16 03BB 16 03BC 16 03BD 16 03BE 16 03BF 16 Timer A0 register (TA0) Timer A1 register (TA1) Timer A2 register (TA2) Timer B0 register (TB0) Timer B1 register (TB1) Timer B2 register (TB2) Count start flag (TABSR) One-shot start flag (ONSF) Timer A0 mode register (TA0MR) Timer A1 mode register (TA1MR) Timer A2 mode register (TA2MR) Timer B0 mode register (TB0MR) Timer B1 mode register (TB1MR) Timer B2 mode register (TB2MR) Up-down flag (UDF) Timer A3 register (TA3) Timer A4 register (TA4) Timer A3 mode register (TA3MR) Timer A4 mode register (TA4MR) Trigger select register (TRGSR) Clock prescaler reset flag (CPSRF) UART0 transmit/receive mode register (U0MR) UART0 transmit buffer register (U0TB) UART0 receive buffer register (U0RB) UART1 transmit/receive mode register (U1MR) UART1 transmit buffer register (U1TB) UART1 receive buffer register (U1RB) UART0 bit rate generator (U0BRG) UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1) UART1 bit rate generator (U1BRG) UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1) DMA1 request cause select register (DM1SL) DMA0 request cause select register (DM0SL) CRC data register (CRCD) CRC input register (CRCIN) UART transmit/receive control register 2 (UCON) A/D register 7 (AD7) A/D register 0 (AD0) A/D register 1 (AD1) A/D register 2 (AD2) A/D register 3 (AD3) A/D register 4 (AD4) A/D register 5 (AD5) A/D register 6 (AD6) Function select register C(PSC) Function select register A1 (PS1) Function select register A0 (PS0) Function select register B0 (PSL0) Function select register B1 (PSL1) Function select register A3 (PS3) Function select register A2 (PS2) Function select register B2 (PSL2) A/D control register 0 (ADCON0) A/D control register 1 (ADCON1) D/A register 0 (DA0) D/A register 1 (DA1) D/A control register (DACON) A/D control register 2 (ADCON2) DMA3 request cause select register (DM3SL) DMA2 request cause select register (DM2SL) Function select register B3 (PSL3)Flash memory control register 0 (FMR0) (Note) Flash memory control register 1 (FMR1) (Note) Note :This register exists in the flash memory version.(The blank area is reserved and cannot be used by user.)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 25 5. SFRpuorG08/C61M Figure 5.4 Location of peripheral unit control registers (4) 03C0 16 03C1 16 03C2 16 03C3 16 03C4 16 03C5 16 03C6 16 03C7 16 03C8 16 03C9 16 03CA 16 03CB 16 03CC 16 03CD 16 03CE 16 03CF 16 03D0 16 03D1 16 03D2 16 03D3 16 03D4 16 03D5 16 03D6 16 03D7 16 03D8 16 03D9 16 03DA 16 03DB 16 03DC 16 03DD 16 03DE 16 03DF 16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA 16 03EB 16 03EC 16 03ED 16 03EE 16 03EF 16 03F016 03F116 03F216 03F316 03FC 16 03FD 16 03FE 16 03FF16 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Note 1: Addresses 03C916, 03CB16 to 03D316 area is for future plan. Must set "FF16" to address 03CB16, 03CE16, 03CF16, 03D216, 03D316 at initial setting. Note 2: Address 03DC16 area is for future plan. Must set "0016" to address 03DC16 at initial setting. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 03C0 16 03C1 16 03C2 16 03C3 16 03C4 16 03C5 16 03C6 16 03C7 16 03C8 16 03C9 16 03CA 16 03CB 16 03CC 16 03CD 16 03CE 16 03CF 16 03D0 16 03D1 16 03D2 16 03D3 16 03D4 16 03D5 16 03D6 16 03D7 16 03D8 16 03D9 16 03DA 16 03DB 16 03DC 16 03DD 16 03DE 16 03DF 16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA 16 03EB 16 03EC 16 03ED 16 03EE 16 03EF 16 03F016 03F116 03F216 03F316 03FC 16 03FD 16 03FE 16 03FF16 Port P0 (P0) Port P0 direction register (PD0) Port P1 (P1) Port P1 direction register (PD1) Port P2 (P2) Port P2 direction register (PD2) Port P3 (P3) Port P3 direction register (PD3) Port P4 (P4) Port P4 direction register (PD4) Port P5 (P5) Port P5 direction register (PD5) Port P6 (P6) Port P6 direction register (PD6) Port P7 (P7) Port P7 direction register (PD7) Port P8 (P8) Port P8 direction register (PD8) Port P9 (P9) Port P9 direction register (PD9) Port P10 (P10) Port P10 direction register (PD10) Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) Pull-up control register 2 (PUR2) Port control register (PCR) Pull-up control register 3 (PUR3) Port P0 (P0) Port P0 direction register (PD0) Port P1 (P1) Port P1 direction register (PD1) Port P2 (P2) Port P2 direction register (PD2) Port P3 (P3) Port P3 direction register (PD3) Port P4 (P4) Port P4 direction register (PD4) Port P5 (P5) Port P5 direction register (PD5) Port P6 (P6) Port P6 direction register (PD6) Port P7 (P7) Port P7 direction register (PD7) Port P8 (P8) Port P8 direction register (PD8) Port P9 (P9) Port P9 direction register (PD9) Port P10 (P10) Port P10 direction register (PD10) Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) Pull-up control register 2 (PUR2) Port control register (PCR) Pull-up control register 3 (PUR3) Port P11 (P11) Port P11 direction register (PD11) Port P12 (P12) Port P12 direction register (PD12) Port P13 (P13) Port P13 direction register (PD13) Port P14 (P14) Port P14 direction register (PD14) Port P15 (P15) Port P15 direction register (PD15) Pull-up control register 4 (PUR4) (The blank area is reserved and cannot be used by user.) <100-pin version> <144-pin version>

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 26 6. Processor ModepuorG08/C61M Software Reset Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the microcomputer. A software reset has the same effect as a hardware reset. The contents of internal RAM are preserved. Carry out a software reset after oscillation of main clock is fully stable. 6. Processor Mode (1) Types of Processor Mode One of three processor modes can be selected: single-chip mode, memory expansion mode, and micro- processor mode. The functions of some pins, the memory map, and the access space differ according to the selected processor mode.

Single-chip mode In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be accessed. However, after the reset has been released and the operation of shifting from the micropro- cessor mode has started ("H" applied to the CNV SS pin), the internal ROM area cannot be accessed even if the CPU shifts to the single-chip mode. Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal peripheral functions.
Memory expansion mode In memory expansion mode, external memory can be accessed in addition to the internal memory space (SFR, internal RAM, and internal ROM). However, after the reset has been released and the operation of shifting from the microprocessor mode has started ("H" applied to the CNVSS pin), the internal ROM area cannot be accessed even if the CPU shifts to the memory expansion mode. In this mode, some of the pins function as the address bus, the data bus, and as control signals. The number of pins assigned to these functions depends on the bus and register settings. (See “Bus Settings” for details.)
Microprocessor mode In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. The internal ROM area cannot be accessed. In this mode, some of the pins function as the address bus, the data bus, and as control signals. The number of pins assigned to these functions depends on the bus and register settings. (See “Bus Settings” for details.) (2) Setting Processor Modes The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address 000416). Do not set the processor mode bits to “102”. Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. Therefore, never change the processor mode bits when changing the contents of other bits. Do not change the processor mode bits simultaneously with other bits when changing the processor mode bits "012" or "112". Change the processor mode bits after changeing the other bits. Also do not attempt to shift to or from the microprocessor mode within the program stored in the internal ROM area.
Applying VSS to CNVSS pin The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode is selected by writing “012” to the processor mode is selected bits.
Applying VCC to CNVSS pin The microcomputer starts to operate in microprocessor mode after being reset. Figures 6.1 and 6.2 show the processor mode register 0 and 1. Figure 6.3 shows the memory maps applicable for each processor modes.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 27 6. Processor ModepuorG08/C61M Figure 6.1 Processor mode register 0 Processor mode register 0 (Note 1) Symbol Address When reset PM0 0004 16 8016 (Note 2) Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0: Single-chip mode 0 1: Memory expansion mode 1 0: Must not be set 1 1: Microprocessor mode b1 b0 PM03 PM01 PM00 Processor mode bit PM02 R/W mode select bit (Note 7) 0 : RD,BHE,WR 1 : RD,WRH,WRL Software reset bit The device is reset when this bit is set to “1”. The value of this bit is “0” when read. PM04 0 0 : Multiplexed bus is not used 0 1 : Allocated to CS2 space 1 0 : Allocated to CS1 space 1 1 : Allocated to entire space (Note4) b5 b4 Multiplexed bus space select bit (Note 3) PM05 PM07 BCLK output disable bit (Note 5) 0 : BCLK is output (Note 6) 1 : Function set by bit 0,1 of system clock control register 0 Note 1: Set bit 1 of the protect register (address 000A 16) to “1” when writing new values to this register. Note 2: If the VCC voltage is applied to the CNVSS , the value of this register when reset is 0316. (PM00 is set to “1” and PM07 is set to “0”.) Note 3: Valid in microprocessor and memory expansion modes 1, 2 and 3. Do not use multiplex bus when mode 0 is selected. Do not set to allocated to CS2 space when mode 2 is selected. Note 4: After the reset has been released, the M16C/80 group MCU operates using the separate bus. As a result, in microprocessor mode, you cannot select the full CS space multiplex bus. When you select the full CS space multiplex bus in memory expansion mode, the address bus operates with 64 Kbytes boundaries for each chip select. Mode 0: Multiplexed bus cannot be used. Mode 1: CS0 to CS2 when you select full CS space. Mode 2: CS0 to CS1 when you select full CS space. Mode 3: CS0 to CS3 when you select full CS space. Note 5: No BCLK is output in single chip mode even when "0" is set in PM07. When stopping clock output in microprocessor or memory expansion mode, make the following settings: PM07="1", bit 0 (CM00) and bit 1 (CM01) of system clock control register 0 (address 0006 16) = "0". "L" is now output from P53. Note 6: When selecting BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0". Note 7: When using 16-bit bus width in DRAM controller, set this bit to "1". Note 8: Do not set the processor mode bits and other bits simultaneously when setting the processor mode bits to “012” or “112”. Set the other bits first, and then change the processor mode bits. WR /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Reserved bit Must always be set to “0” (Note 8)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 28 6. Processor ModepuorG08/C61M Figure 6.2 Processor mode register 1 Processor mode register 1 (Note 1) :Flash memory version Symbol Address When reset PM1 0005 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register. Note 2: When mode 3 is selected, DRAMC is not used. Note 3: Valid in memory expansion mode or in microprocessor mode. Note 4: When selecting P5 3/BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0". Note 5: Rewrite this bit when the main clock is in division by 8 mode. ALE pin select bit (Note 3)0 0 : No ALE 0 1 : P53/BCLK (Note 4) 1 0 : P56/RAS 1 1 : P54/HLDA b5 b4 PM15 PM14 Reserved bit Must always be set to “0” WR /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Reserved bit Must always be set to “1” (Note 5) PM12 Internal memory wait bit 0 : No wait state 1 : Wait state inserted External memory area mode bit (Note 3) 0 0 : Mode 0 (P4 4 to P47 : A20 to A23) 0 1 : Mode 1 (P44 : A20, P45 to P47 : CS2 to CS0) 1 0 : Mode 2 (P44, P45 : A20, A21, P46, P47 : CS1, CS0) 1 1 : Mode 3 (Note 2) (P44 to P47 : CS3 to CS0) b1 b0 PM11 PM10 /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Processor mode register 1 (Note 1) :Mask ROM version ROMless version (144-pin version) Symbol Address When reset PM1 0005 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register. Note 2: When mode 3 is selected, DRAMC is not used. Note 3: Valid in memory expansion mode or in microprocessor mode. Note 4: When selecting P5 3/BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0". ALE pin select bit (Note 3)0 0 : No ALE 0 1 : P53/BCLK (Note 4) 1 0 : P56/RAS 1 1 : P54/HLDA b5 b4 PM15 PM14 Reserved bit Must always be set to “0” WR /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Nothing is assinged. When read, the content is indeterminate. PM12 Internal memory wait bit 0 : No wait state 1 : Wait state inserted External memory area mode bit (Note 3) 0 0 : Mode 0 (P4 4 to P47 : A20 to A23) 0 1 : Mode 1 (P44 : A20, P45 to P47 : CS2 to CS0) 1 0 : Mode 2 (P44, P45 : A20, A21, P46, P47 : CS1, CS0) 1 1 : Mode 3 (Note 2) (P44 to P47 : CS3 to CS0) b1 b0 PM11 PM10 /LiteDiagLines/LiteDiagLines/LiteDiagLines

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 29 6. Processor ModepuorG08/C61M Single chip mode Memory expanded mode Microprocessor mode SFR area Internal RAM area Internal reserved area Internal ROM area No use External area 0 CS22Mbytes External area 1 CS02Mbytes External area 3 No use Internal ROM areaInternal reserved area Internal ROM areaInternal reserved area Internal ROM areaInternal reserved area CS03Mbytes External area 3 CS14Mbytes(Note2) External area 0 External area 3 No use CS02Mbytes External area 3 CS04Mbytes External area 3 000000 000400 000800 200000 400000 C00000 E00000 F00000 FFFFFF Each CS0 to CS3 can set 0 to 3 WAIT. Mode 0 Mode 1 Mode 2 Mode 0 Mode 1 Mode 2 SFR area Internal RAM area Internal reserved area SFR area Internal RAM area Internal reserved area SFR area Internal RAM area Internal reserved area SFR area Internal RAM area Internal reserved area SFR area Internal RAM area Internal reserved area SFR area Internal RAM area Mode 3 Internal reserved area SFR area Internal RAM area Internal ROM areaInternal reserved areaCS1, 1MbytesExternal area 0 Mode 3 Internal reserved area SFR area Internal RAM area No use CS2, 1MbytesExternal area 1 No use Connect with DRAM 0, 0.5 to 8MB(When not connect with DRAM, use as external area.) Connect with DRAM 0, 0.5 to 8MB(When open area is under 8MB, cannot use the rest of this area.) Connect with DRAM 0, 0.5 to 8MB(When open area is under 8MB, cannot use the rest of this area.) Connect with DRAM 0, 0.5 to 8MB(When open area is under 8MB, cannot use the rest of this area.) No use (Cannot use as DRAM area or external area.) Connect with DRAM 0, 0.5 to 8MB(When not connect with DRAM, use as external area.) Connect with DRAM 0, 0.5 to 8MB(When open area is under 8MB, cannot use the rest of this area.) No use (Cannot use as DRAM area or external area.) No useNo use No use CS12Mbytes(Note1) External area 0 No use Note 1: 200000 –008000 =2016 Kbytes. 32 K less than 2 MB. Note 2: 400000 –008000 =4064 Kbytes. 32 K less than 4 MB. External area 1 External area 0 CS22Mbytes External area 1 CS14Mbytes(Note2) External area 0 CS1, 1MbytesExternal area 0CS2, 1MbytesExternal area 1 CS12Mbytes(Note1) External area 0 External area 1 (External area 2) (External area 2) (External area 2) (External area 2) (External area 2) (External area 2) External area 3 CS3, 1MbytesExternal area 2 CS0, 1MbytesExternal area 3 CS3, 1MbytesExternal area 2CS0, 1MbytesExternal area 3 Figure 6.3 Memory maps in each processor mode

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 30 7. BuspuorG08/C61M 7. Bus

7.1 Bus Settings

The BYTE pin, bit 0 to 3 of the external data bus width control register (address 000B16), bits 4 and 5 of the processor mode register 0 (address 000416) and bit 0 and 1 of the processor mode register 1 (address 000516) are used to change the bus settings. Table 7.1 shows the factors used to change the bus settings, Figure 7.1 shows external data bus width control register and Table 7.2 shows external area 0 to 3 and external area mode. Bus setting Switching factor Switching external address bus width External data bus width control register Switching external data bus width BYTE pin (external area 3 only) Switching between separate and multiplex bus Bits 4 and 5 of processor mode register 0 (1) Selecting external address bus width You can select the width of the address bus output externally from the 16 Mbytes address space, the number of chip select signals, and the address area of the chip select signals. (Note, however, that when ____ you select “Full CS space multiplex bus”, addresses A0 to A15 are output.) The combination of bits 0 and 1 of the processor mode register 1 allow you to set the external area mode. When using DRAM controller, the DRAM area is output by multiplexing of the time splitting of the row and column addresses. (2) Selecting external data bus width You can select 8-bit or 16-bit for the width of the external data bus for external areas 0, 1, 2, and 3. When the data bus width bit of the external data bus width control register is “0”, the data bus width is 8 bits; when “1”, it is 16 bits. The width can be set for each of the external areas. The default bus width for external area 3 is 16 bits when the BYTE pin is “L” after a reset, or 8 bits when the BYTE pin is “H ” after a reset. The bus width selection is valid only for the external bus (the internal bus width is always 16 bits). During operation, fix the level of the BYTE pin to “H ” or “L”. (3) Selecting separate/multiplex bus The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0.

Separate bus In this bus configuration, input and output is performed on separate data and address buses. The data bus width can be set to 8 bits or 16 bits using the external data bus width control register. For all programmable external areas, P0 is the data bus when the external data bus is set to 8 bits, and P1 is a programmable IO port. When the external data bus width is set to 16 bits for any of the external areas, P0 and P1 (although P1 is undefined for any 8-bit bus areas) are the data bus. When accessing memory using the separate bus configuration, you can select a software wait using the wait control register.
Multiplex bus In this bus configuration, data and addresses are input and output on a time-sharing basis. For areas for which 8-bit has been selected using the external data bus width control register, the 8 bits D 0 to D7 are multiplexed with the 8 bits A0 to A7. For areas for which 16-bit has been selected using the external data bus width control register, the 16 bits D0 to D15 are multiplexed with the 16 bits A0 to A15. When accessing memory using the multiplex bus configuration, two waits are inserted regardless of whether you select “No wait” or “1 wait’ in the appropriate bit of the wait control register. Table 7.1 Factors for switching bus settings

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 31 7. BuspuorG08/C61M ____ The default after a reset is the separate bus configuration, and the full CS space multiplex bus configu- ____ ration cannot be selected in microprocessor mode. If you select “Full CS space multiplex bus”, the 16 bits from A0 to A15 are output for the address. External data bus width control register Symbol Address When reset DS 000B 16 XXXXX000 2 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 DS3 DS1 DS0 External area 0 data bus width bit DS2 External area 1 data bus width bit External area 2 data bus width bit External area 3 data bus width bit (Note) 0 : 8 bits data bus width 1 : 16 bits data bus width Note: The value after a reset is determined by the input via the BYTE pin. WR /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Nothing is assigned. When write, set "0". When read, their contents are indeterminate. 0 : 8 bits data bus width 1 : 16 bits data bus width 0 : 8 bits data bus width 1 : 16 bits data bus width 0 : 8 bits data bus width 1 : 16 bits data bus width Figure 7.1 External data bus width control register Note 1: DRAMC area when using DRAMC. Note 2: Set the external area mode (modes 0, 1, 2, and 3) using bits 0 and 1 of the processor mode register 1 (address 000516). External area mode (Note 2) Mode 0 Mode 1 Mode 2 Mode 3 External area 0 External area 1 External area 2 External area 3 Memory expansion mode Memory expansion mode, Microprocessor mode Microprocessor mode Memory expansion mode, Microprocessor mode 00800016 to 1FFFFF 16 20000016 to 3FFFFF 16 40000016 to BFFFFF 16 (Note 1) C00000 16 to EFFFFF 16 C00000 16 to FFFFFF 16 <CS1 area> 00800016 to 1FFFFF 16 <CS2 area> 20000016 to 3FFFFF 16 <DRAMC area> 40000016 to BFFFFF 16 <CS0 area> C00000 16 to EFFFFF 16 <CS0 area> E0000016 to FFFFFF 16 <CS1 area> 00800016 to 1FFFFF 16 <DRAMC area> 40000016 to BFFFFF 16 <CS0 area> C00000 16 to EFFFFF 16 <CS0 area> C00000 16 to FFFFFF 16 <CS1 area> 10000016 to 1FFFFF 16 <CS2 area> 20000016 to 2FFFFF 16 <CS3 area> C00000 16 to CFFFFF 16 <CS0 area> E0000016 to EFFFFF 16 <CS0 area> F0000016 to FFFFFF 16 Memory expansion mode, Microprocessor mode No area is selected. Table 7.2 External area 0 to 3 and external area mode

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 32 7. BuspuorG08/C61M P00 to P07 I/O port Data bus Data bus Data bus Data bus I/O port I/O port CS1 or CS2 : multiplexed bus, and the other : separate bus Separate bus All space multiplexed bus Single-chip mode Memory expansion mode/microprocessor modes Memory expansion mode Data bus width BYTE pin level All external area is 8 bits Some external area is 16 bits All external area is 8 bits Some external area is 16 bits Note 1:The default after a reset is the separate bus configuration, and "Full CS space multiplex bus" cannot be selected in microprocessor mode. When you select "Full CS space multiplex bus" in extended memory mode, the address bus operates with 64 Kbytes boundaries for each chip select. Note 2: Address bus in separate bus configuration. Note 3: The ALE output pin is selected using bits 4 and 5 of the processor mode register 1. Note 4: When you have selected use of the DRAM controller and you access the DRAM area, these are CASL, CASH, DW, and BCLK outputs. Note 5: The CS signal and address bus selection are set by the external area mode. Processor mode Multiplexed bus space select bit CS (chip select) or address bus (A23) (For details, refer to “Bus control”) (Note 5) Outputs RD, WRL, WRH and BCLK, or RD, BHE, WR and BCLK (For details, refer to “Bus control”) (Note 3,4) P10 to P17 I/O port I/O port Data bus I/O port Data bus I/O port I/O port P20 to P27 I/O port Address bus Address bus Address bus Address bus Address bus Address bus /data bus /data bus /data bus /data bus P40 to P43 I/O port Address bus Address bus Address bus Address bus I/O port I/O port P44 to P46 I/O port CS (chip select) or address bus (A20 to A22) (For details, refer to “Bus control”) (Note 5) P47 I/O port P50 to P53 I/O port P54 I/O port HLDA(Note 3) HLDA(Note 3) HLDA(Note 3) HLDA(Note 3) HLDA(Note 3) HLDA(Note 3) P55 I/O port HOLD HOLD HOLD HOLD HOLD HOLD P56 I/O port RAS (Note 3) RAS (Note 3) RAS (Note 3) RAS (Note 3) RAS (Note 3) RAS (Note 3) P57 I/O port RDY RDY RDY RDY RDY RDY P30 to P37 I/O port Address bus Address bus Address bus Address bus Address bus Address bus /data bus /data bus (Note 2) (Note 2) (Note 2) All external area is 8 bits Some external area is 16 bits Table 7.3 Each processor mode and port function

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 33 7. BuspuorG08/C61M

7.2 Bus Control

The following explains the signals required for accessing external devices and software waits. The signals required for accessing the external devices are valid when the processor mode is set to memory expansion mode and microprocessor mode. (1) Address bus/data bus There are 24 pins, A0 to A22 and A23 for the address bus for accessing the 16 Mbytes address space. A23 is an inverted output of the MSB of the address. The data bus consists of pins for data IO. The external data bus control register (address 000B16) selects the 8-bit data bus, D0 to D7 for each external area, or the 16-bit data bus, D0 to D15. After a reset, there is by default an 8-bit data bus for the external area 3 when the BYTE pin is “H ”, or a 16-bit data bus when the BYTE pin is “L”. When shifting from single-chip mode to extended memory mode, the value on the address bus is unde- fined until an external area is accessed. When accessing a DRAM area with DRAM control in use, a multiplexed signal consisting of row address and column address is output to A 8 to A20. (2) Chip select signals ____ The chip select signals share A0 to A22 and A23. You can use bits 0 and 1 of the processor mode register 1 (address 000516) to set the external area mode, then select the chip select area and number of address outputs. In microprocessor mode, external area mode 0 is selected after a reset. The external area can be split into a maximum of four using the chip select signals. Table 7.4 shows the external areas specified by the chip select signals. Table 7.4 External areas specified by the chip select signals Processor mode Memory space expansion mode Specified address range Memory expansion mode Mode 0 Chip select signal CS0 CS1 CS2 CS3 C00000 16 to DFFFFF 16 (2 Mbytes) Microprocessor mode Memory expansion mode 00800016 to 1FFFFF 16 (2016 Kbytes) 20000016 to 3FFFFF 16 (2 Mbytes) 00800016 to 3FFFFF 16 (4064 Kbytes) Microprocessor mode E0000016 to FFFFFF 16 (2 Mbytes) C00000 16 to EFFFFF 16 (3 Mbytes) C00000 16 to FFFFFF 16 (4 Mbytes) E0000016 to EFFFFF 16 (1 Mbytes) 10000016 to 1FFFFF 16 (1 Mbytes) Mode 1 Mode 2 Mode 3 Memory expansion mode Microprocessor mode F0000016 to FFFFFF 16 (1 Mbytes) 20000016 to 2FFFFF 16 (1 Mbytes) C00000 16 to CFFFFF 16 (1 Mbytes) (A21) (A20) (A20)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 34 7. BuspuorG08/C61M Figure 7.2 Example of address bus and chip select signal outputs (Separate bus) The chip select signal turns “L” (active) in synchronize with the address bus. However, its turning “H ” depends on the area accessed in the next cycle. Figure 7.2 shows the output examples of the address bus and chip select signals. (Example 1) After accessing the external area, the address bus and chip select signal both are changed in the next cycle. The following example shows the other chip select signal accessing area (j) in the cycle after having accessed external area (i). In this case, the address bus and chip select signal both change between the two cycles. Note: These examples show the address bus and chip select signal for two consecutive cycles. By combining these examples, chip select signal can be extended beyond two cycles. Data bus Address bus Chip select (CSi) Access to external area (i) Chip select (CSj) Access to external area (j) Address DataData (Example 2) After accessing the external area, only the chip select signal is changed in the next cycle. (The address bus does not change.) The following example shows the CPU accesses the internal ROM/RAM area in the cycle after having accessed external area. In this case, the chip select signal changes between the two cycles but the address bus does not. (Example 3) After accessing the external area, only the address bus is changed in the next cycle. (The chip select signal does not change.) The following example shows the same chip select signal accessing area (i) in the cycle after having accessed external area (i). In this case, the address bus changes between the two cycles, but the chip select signal does not. Data bus Address bus Chip select (CSi) Data Address Data bus Address bus Chip select Data Address Access to external area No access Access to external area (i) Access to external area (i) Data bus Address bus Chip select Data Address (Example 4) After accessing the external area, the address bus and chip select signal both are not changed in the next cycle. The following example shows CPU does not access any area in the cycle after having accessed external area (no instruction pre-fetch is occurred). In this case, the address bus and the chip select signal do not change between the two cycles. Data

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 35 7. BuspuorG08/C61M Table 7.6 Operation of RD, WR, and BHE signals Status of external data busRD BHEWR HLL LHL HLH LHH Write 1 byte of data to odd address Read 1 byte of data from odd address Write 1 byte of data to even address Read 1 byte of data from even address Data bus width A0 H H L L HLL L LHL L HL H / L LH H / L8-bit Write data to both even and odd addresses Read data from both even and odd addresses Write 1 byte of data Read 1 byte of data 16-bit Not used Not used Status of external data bus Read data Write 1 byte of data to even address Write 1 byte of data to odd address Write data to both even and odd addresses WRHWRLRDData bus width 16-bit H H H H L H L H H L L L H H (Note) L (Note) L Not used Write 1 byte of data Read 1 byte of dataNot used8-bit (3) Read/write signals With a 16-bit data bus, bit 2 of the processor mode register 0 (address 000416) select the combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With a 8-bit full space data bus, use the combination of RD, WR, and BHE signals as read/write signals. (Set "0" to bit 2 of the processor mode register 0 (address 000416).) When using both 8-bit and 16-bit data bus widths and you access an 8-bit data bus area, the RD, WR and BHE signals combination is selected regardless of the value of bit 2 of the processor mode register 0 (address 0004 16). Tables 7.5 and 7.6 show the operation of these signals. After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected. When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the processor mode register 0 (address 0004 16) has been set (Note). Note 1: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register (address 000A16) to “1”. Note 2: When using 16-bit data bus width for DRAM controller, select RD, WRL, and WRH signals. Table 7.5 Operation of RD, WRL, and WRH signals Note: It becomes WR signal.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 37 7. BuspuorG08/C61M Figure 7.4 Example of RD signal extended by RDY signal RDY received timing /LiteDiagLines/LiteDiagLines Separate bus (2 wait) Multiplexed bus (2 wait) BCLK RD CS i (i=0 to 3) RDY /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines BCLK RD CS i (i=0 to 3) RDY tsu(RDY - BCLK) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 1st cycle 2nd cycle 3rd cycle 4th cycle tsu(RDY - BCLK) RDY received timing RDY signal received timing for i wait(s): i + 1 cycles (i = 1 to 3) 1st cycle 2nd cycle 3rd cycle 4th cycle : Wait using RDY signal : Wait using software (Note) (Note) Note: Chip select may get longer by a state of CPU such as an instruction queue buffer.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 38 7. BuspuorG08/C61M Item Status Oscillation ON RD/WR signal, address bus, data bus, CS, BHE Floating Programmable I/O ports P0, P1, P2, P3, P4, P5 M aintains status when hold signal is received P6, P7, P8, P9, P10 P11, P12, P13, P14, P15 (Note) HLDA Output “L” Internal peripheral circuits ON (but watchdog timer stops) ALE signal Undefined (6) Hold signal The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L” to the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status is maintained and “L” is output from the HLDA pin as long as “L” is input to the HOLD pin. Table 7.8 shows the microcomputer status in the hold state. The bus is used in the following descending order of priority: HOLD, DMAC, CPU. Figure 7.5 Example of RD signal extended by RDY signal HOLD > DMAC > CPU Table 7.8 Microcomputer status in hold state Item SFR accessing status Internal ROM/RAM accessing status Address bus Remain address of external area accessed immediately before Data bus When read Floating When write Floating RD, WR, WRL, WRH Output "H" BHE Remain external area status accessed immediately before ____ CS Output "H" ALE ALE output (8) BCLK output BCLK output can be selected by bit 7 of the processor mode register 0 (address 000416 :PM07) and bit 1 and bit 0 of the system clock select register 0 (address 000616 :CM01, CM00). Setting PM07 to “0” and CM01 and CM00 to “00” outputs the BCLK signal from P53. However, in single chip mode, BCLK signal is not output. When setting PM07 to “1”, the function is as set by CM01 and CM00. Note: Ports P11 to P15 exist in 144-pin version. (7) External bus status when accessing to internal area Table 7.9 shows external bus status when accessing to internal area Table 7.9 External bus status when accessing to internal area

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 39 7. BuspuorG08/C61M (10) Software wait A software wait can be inserted by setting the wait control register (address 000816). Figure 7.6 shows wait control register You can use the external area I wait bits (where I = 0 to 3) of the wait control register to specify from “No wait” to “3 waits” for the external memory area. When you select “No wait”, the read cycle is executed in the BCLK1 cycle. The write cycle is executed in the BCLK2 cycle (which has 1 wait). When accessing external memory using the multiplex bus, access has two waits regardless of whether you specify “No wait” or “1 wait” in the appropriate external area i wait bits in the wait control register. Software waits in the internal memory (internal RAM and internal ROM) can be set using the internal memory wait bits of the processor mode register 1 (address 0005 16). Setting the internal memory wait bit = “0” sets “No wait”. Setting the internal memory wait bit = “1” specifies a wait. The SFR area is not affected by the setting of the internal memory wait bit and is always accessed in the BCLK2 cycle. Table 7.11 shows the software waits and bus cycles. Figures 7.7 and 7.8 show example bus timings when using software waits. Status of external data busRAS CASHCASL LLL LLL LHH LLL Read data from both even and odd addresses Read 1 byte of data from even address Read 1 byte of data from odd address Write data to both even and odd addresses Data bus width DW H H H L LLHL LHL L LL H LL L8-bit Write 1 byte of data to even address Write 1 byte of data to odd address Read 1 byte of data Write 1 byte of data 16-bit Not used Not used (9) DRAM controller signals (RAS, CASL, CASH, and DW) Bits 1, 2, and 3 of the DRAM control register (address 000416) select the DRAM space and enable the DRAM controller. The DRAM controller signals are then output when the DRAM area is accessed. Table 7.10 shows the operation of the respective signals. Table 7.10 Operation of RAS, CASL, CASH, and DW signals

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 40 7. BuspuorG08/C61M Area Bus status Internal memory wait bit External memory area i wait bit Bus cycle 1 2 BCLK cycles External memory area 002 Read :1 BCLK cycle Separate bus Write : 2 BCLK cycles

2 BCLK cycles

3 BCLK cycles

4 BCLK cycles

3 BCLK cycle

Table 7.11 Software waits and bus cycles Figure 7.6 Wait control register Wait control register Symbol Address When reset WCR 0008 16 FF16 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0: Without wait 0 1: With 1 wait 1 0: With 2 wait 1 1: With 3 wait b1 b0 WCR WCR1 WCR0 External area 0 wait bit WCR2 External area 1 wait bit External area 2 wait bitWCR4 External area 3 wait bit WCR5 WCR7 Note 1: When using the multiplex bus configuration, there are two waits regardless of whether you have specified "No wait" or "1 wait". However, you can specify "2 wait" or "3 wait". Note 2: When using the separate bus configuration, the read bus cycle is executed in the BCLK1 cycle, and the write cycle is executed in the BCLK2 cycle (with 1 wait). WR /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines WCR6 0 0: Without wait 0 1: With 1 wait 1 0: With 2 wait 1 1: With 3 wait b3 b2 0 0: Without wait 0 1: With 1 wait 1 0: With 2 wait 1 1: With 3 wait b5 b4 0 0: Without wait 0 1: With 1 wait 1 0: With 2 wait 1 1: With 3 wait b7 b6

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 41 7. BuspuorG08/C61M Figure 7.7 Typical bus timings using software wait Output Input Address Address Bus cycle (Note) < Separate bus (with wait) > BCLK Read signal Write signal Data bus Address bus (Note 2) Chip select (Note 2,3) BCLK Read signal Data bus Chip select (Note 2,3) Data output AddressAddress bus (Note 2) Address Input < Separate bus with 2 wait > Write signal BCLK Read signal Write signal Address bus (Note 2) Address Bus cycle (Note)< Separate bus (no wait) > OutputData bus Chip select (Note 2,3) Input Bus cycle (Note) Bus cycle (Note) Bus cycle (Note 1) Bus cycle (Note 1) Address Note 1: This timing example shows bus cycle length. Read cycle and write cycle may be continued after this bus cycle. Note 2: Address bus and chip select may get longer by a state of CPU such as an instruction queue buffer. Note 3: When accessing same external area (same CS area) continuously, chip select may output continuously.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 42 7. BuspuorG08/C61M Figure 7.8 Typical bus timings using software wait BCLK Read signal Write signal Address bus/Data bus (Note 2) Chip select (Note 2,3) Address AddressAddress Data output Address Address Input ALE Bus cycle (Note) < Multiplexed bus (with 2 wait) > Bus cycle (Note) BCLK Read signal Write signal Chip select (Note 2,3) Bus cycle (Note) < Separate bus (with 3 wait) > AddressAddress (Note 2) Address Bus cycle (Note) Data bus Data output Input BCLK Read signal Write signal Address bus /Data bus (Note 2) Chip select (Note 2,3) AddressAddress Data output Address Input Bus cycle (Note) < Multiplexed bus (with 3 wait) > Address Address ALE Bus cycle (Note) Note 1: This timing example shows bus cycle length. Read cycle and write cycle may be continued after this bus cycle. Note 2: Address bus and chip select may get longer by a state of CPU such as an instruction queue buffer. Note 3: When accessing same external area (same CS area) continuously, chip select may output continuously.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 43 8. Clock Generating CircuitpuorG08/C61M Figure 8.2 Examples of sub clock Table 8.1 Main clock and sub clock generating circuits 8. Clock Generating Circuit The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral units.

8.1 Example of oscillator circuit

Figure 8.1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Figure 8.2 shows some examples of sub clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Circuit constants in Figures 8.1 and 8.2 vary with each oscillator used. Use the values recommended by the manufacturer of your oscillator. Figure 8.1 Examples of main clock Main clock generating circuit Sub clock generating circuit Use of clock • CPU ’s operating clock source• CPU ’s operating clock source

Internal peripheral units’• Timer A/B’s count clock operating clock source source Usable oscillator Ceramic or crystal oscillator Crystal oscillator Pins to connect oscillator X IN, XOUT XC IN, XCOUT Oscillation stop/restart function Available Available Oscillator status immediately after resetOscillating Stopped Other Externally derived clock can be input Microcomputer (Built-in feedback resistance) XIN XOUT Externally derived clock Open Vcc Vss Microcomputer (Built-in feedback resistance) XIN XOUT R d C IN C OUT (Note) Note: Insert a damping resistance if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Insert a feedback resistance between X IN and XOUT when an oscillation manufacture required. Microcomputer (Built-in feedback resistance) XCIN XCOUT Externally derived clock Open Vcc Vss Note: Insert a damping resistance if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Insert a feedback resistance between X CIN and XCOUT when an oscillation manufacture required. Microcomputer (Built-in feedback resistance) XCIN XCOUT (Note) C CIN C COUT R Cd

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 44 8. Clock Generating CircuitpuorG08/C61M

8.2 Clock Control

Figure 8.3 shows the block diagram of the clock generating circuit. Sub clock CM04 fC32 CM0i : Bit i at address 000616 CM1i : Bit i at address 000716 WDCi : Bit i at address 000F16 XCIN CM10 “1” Write signal XCOUT QS R WAIT instruction XOUT Main clock CM05 fC CM02 QS R NMI Interrupt request level judgment output RESET Software reset fC CM07=0 CM07=1 fAD /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Divider 1a d 1/2 1/2 1/2 1/2a Details of divider 1 XIN f32 cb b c f32SIO2 f8SIO2 f1SIO2 BCLK /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Divider 2 1/N dividera Details of divider 2 e N is set by MCD4 to MCD0 as follow: N = 1, 2, 3, 4, 6, 8, 10, 12, 14 and 16 e Figure 8.3 Clock generating circuit

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 45 8. Clock Generating CircuitpuorG08/C61M The following paragraphs describes the clocks generated by the clock generating circuit. (1) Main clock The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Switching to the sub clock oscillation as CPU operating clock source before stopping the clock reduces the power dissipation. When the main clock is stoped (bit 5 at address 0006 16 =1) or the mode is shifted to stop mode (bit 0 at address 000716 =1), the main clock division register (address 000C16) is set to the division by 8 ("0816"). After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the X IN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit defaults to “1” when shifting from high-speed or middle-speed mode to stop mode and after a reset. This bit remains in low-speed and low power dissipation mode. (2) Sub clock The sub clock is generated by the sub clock oscillation circuit. No sub clock is generated after a reset. After oscillation is started using the port Xc select bit (bit 4 at address 0006 16), the sub clock can be selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the sub clock oscillation has fully stabilized before switching. After the oscillation of the sub clock oscillation circuit has stabilized, the drive capacity of the sub clock oscillation circuit can be reduced using the X CIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the drive capacity of the sub clock oscillation circuit reduces the power dissipation. This bit changes to “1” when shifting to stop mode and at a reset. When the sub clock is used, set ports P8 6 and P87 to no pull-up resistance with the input port. (3) BCLK The BCLK is the clock that drives the CPU, and is either fc or is derived by dividing the main clock by 1, 2, 3, 4, 6, 8, 10, 12, 14 or 16. The BCLK is derived by dividing the main clock by 8 after a reset. This signal is output from BCLK pin using CM01, CM00 and PM07 in memory expansion mode and microprocessor mode. When main clock is stoped or shifting to stop mode, the main clock division register (address 000C 16) is set to the division by 8 ("0816"). (4) Peripheral function clock

f1, f8, f32, f1SIO2, f8SIO2, f32SIO2 The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 0006 16) to “1” and then executing a WAIT instruction.
fAD This clock has the same frequency as the main clock and is used for A/D conversion. (5) fC32 This clock is derived by dividing the sub clock by 32. It is used for the timer A and timer B counts. (6) fC This clock has the same frequency as the sub clock. It is used for BCLK and for the watchdog timer. Figure 8.4 shows the system clock control registers 0 and 1 and Figure 8.5 shows main clock division register.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 46 8. Clock Generating CircuitpuorG08/C61M Figure 8.4 System clock control registers 0 and 1 S y s t e m c l o c k c o n t r o l r e g i s t e r 0 ( N o t e 1 ) S y m b o lA d d r e s sW h e n r e s e t C M 6 0 B i t n a m e FunctionB i t s y m b o l b 7 b 6 b 5 b 4 b3 b 2 b 1 b 0 0 0 : I/O port P53 0 1 : fC output (Note 3) 1 0 : f8 output (Note 3) 1 1 : f32 output (Note 3) b1 b0 C M 0 7 C M 0 5 C M 0 4 C M 0 3 C M 0 1 CM02 C M 0 0 Clock output function select bit (Note 2) WAIT peripheral function clock stop bit 0 : Do not stop peripheral clock in wait mode 1 : Stop peripheral clock in wait mode (Note 10) X C I N - X C O U T d r i v e c a p a c i t y s e l e c t b i t N o t e 0 : LOW 1 : HIGH Port XC select bit 0 : I/O port 1 : XCIN-XCOUT generation (Note 11) Main clock (XIN-XOUT) stop bit (Note 5, 6) 0 : On 1 : Off (Note 7) System clock select bit (Note 9) 0 : X IN, XOUT 1 : XCIN, XCOUT N o t e 1 : S e t b i t 0 o f t h e p r o t e c t r e g i s t e r ( a d d r e s s 0 0 0 A1 6) t o “ 1 ” b e f o r e w r i t i n g t o t h i s r e g i s t e r . N o t e W h e n o u t p u t t i n g B C L K b i t o f p r o c e s s o r m o d e r e g i s t e r i s s e t t h e s e b i t s t o W h e n o u t p u t t i n g A L E t o P b i t a n d o f p r o c e s s o r m o d e r e g i s t e r i s s e t t h e s e b i t s t o T h e p o r t P f u n c t i o n i s n o t s e l e c t e d e v e n w h e n y o u s e t i n m i c r o p r o c e s s o r o r m e m o r y e x p a n s i o n m o d e a n d b i t o f t h e p r o c e s s o r m o d e r e g i s t e r i s N o t e W h e n s e l e c t i n g fC , o r i n s i n g l e c h i p m o d e m u s t u s e P a s i n p u t p o r t N o t e C h a n g e s t o w h e n s h i f t i n g t o s t o p m o d e o r r e s e t N o t e W h e n e n t e r i n g t h e p o w e r s a v i n g m o d e t h e m a i n c l o c k i s s t o p p e d u s i n g t h i s b i t T o s t o p t h e m a i n c l o c k s e t s y s t e m c l o c k s t o p b i t C M t o w h i l e a n o s c i l l a t i o n o f s u b c l o c k i s s t a b l e T h e n s e t t h i s b i t t o N o t e W h e n t h i s b i t i s XO U T i s H A l s o t h e i n t e r n a l f e e d b a c k r e s i s t a n c e r e m a i n s O N s o XI N i s p u l l e d u p t o XO U T H l e v e l v i a t h e f e e d b a c k r e s i s t a n c e N o t e W h e n t h e m a i n c l o c k i s s t o p p e d t h e m a i n c l o c k d i v i s i o n r e g i s t e r a d d r e s s C 1 i s s e t t o t h e d i v i s i o n b y m o d e N o t e W h e n h a s b e e n s e t o n c e c a n n o t b e w r i t t e n b y s o f t w a r e N o t e T o s e t C M f r o m f i r s t s e t C M t o a n d a n o s c i l l a t i o n o f s u b c l o c k i s s t a b l e T h e n s e t C M A l s o t o s e t C M f r o m f i r s t s e t C M t o a n d a n o s c i l l a t i o n o f m a i n c l o c k i s s t a b l e T h e n s e t C M D o n o t r e w r i t e C M a n d C M s i m u l t a n e o u s l y N o t e f i s n o t i n c l u d e d N o t e W h e n X cI N - X cO U T i s u s e d s e t p o r t P a n d P t o n o p u l l u p r e s i s t a n c e w i t h t h e i n p u t p o r t S y s t e m c l o c k c o n t r o l r e g i s t e r 1 ( N o t e 1 ) S y m b o lA d d r e s sW h e n r e s e t C M 6 2 B i t n a m eF u n c t i o nB i t s y m b o l b7 b6 b5 b4 b3 b2 b1 b0 C M 1 0 A l l c l o c k s t o p c o n t r o l b i t N o t e 0 : Clock on 1 : All clocks off (stop mode) (Note 4) Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register. Note 2: Changes to “1” when shifting from high-speed or middle-speed mode to stop mode or reset. This bit is remained in low speed or low power dissipation mode. Note 3: When this bit is "1", XOUT is "H", and the internal feedback resistance is disabled. XCIN and XCOUT are high-inpedance. Note 4: When the main clock is stopped, the main clock division register (address 000C16) is set to the division by 8 mode. C M 1 5 XI N - XO U T d r i v e c a p a c i t y s e l e c t b i t N o t e WR WR Reserved bit Always set to “0” 00 00 Reserved bit Always set to “0” C M 0 6 W a t c h d o g t i m e r f u n c t i o n s e l e c t b i t 0 : W a t c h d o g t i m e r i n t e r r u p t R e s e t N o t e

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 47 8. Clock Generating CircuitpuorG08/C61M Figure 8.5 Main clock division register Main clock division register (Note 1) Symbol Address When reset MCD 000C 16 XXX01000 2 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 0 : No division mode 0 0 0 1 0 : Division by 2 mode 0 0 0 1 1 : Division by 3 mode 0 0 1 0 0 : Division by 4 mode 0 0 1 1 0 : Division by 6 mode 0 1 0 0 0 : Division by 8 mode 0 1 0 1 0 : Division by 10 mode 0 1 1 0 0 : Division by 12 mode 0 1 1 1 0 : Division by 14 mode 0 0 0 0 0 : Division by 16 mode b4 b3 b2 b1 b0 MCD4 MCD3 MCD1 MCD2 MCD0 Main clock division select bit (Note 2) Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register. Note 2: These bits are "010002" (8-division mode) when main clock is stopped or you shift to stop mode. Note 3: Do not attempt to set combinations of values other than those shown in this figure. WR /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Nothing is assigned. When write, set "0". When read, their contents are indeterminate.

8.3 Clock Output

In single chip mode, when the BCLK output function select bit (bit 7 at address 000416 :PM07) is “1”, you can output f8, f32, or fc from the P53/BCLK/ALE/CLKOUT pins by setting the clock output function select bits (bits 1 and 0 at address 000616 :CM01, CM00).(Note) Even when you set PM07 to “0” and CM01 and CM00 to “002”, no BCLK is output. In memory expansion mode or microprocessor mode, when the ALE pin select bits (bits 5 and 4 at ad- dress 0005 16 :PM15, PM14) are other than “012(P53/BCLK)” and PM07 is “1”, you can output f8, f32, or fc from the P53/BCLK/ALE/CLKOUT pins by setting CM01 and CM00. In memory expansion mode or microprocessor mode, when PM15 and PM14 are other than “012(P53/ BCLK) ” and PM07 is “0” and CM01 and CM00 to “002”, BCLK is output from the P53/BCLK/ALE/CLKOUT pins. When stopping clock output in memory expansion mode or microprocessor mode, set PM07 to “1” and CM01 and CM00 to “002” (IO port P53). The P53 function is not selected. When PM15 and PM14 are “012 (P53/BCLK)” and CM01 and CM00 are “002”, PM07 is ignored and the P53 pin is set for ALE output. When the WAIT peripheral function clock stop bit (bit 2 at address 000616) is set to “1”, f8 or f32 clock output is stopped when a WAIT command is executed. Table 8.2 shows clock output setting (single chip mode) and Table 8.3 shows clock output setting (memory expansion/microprocessor mode). Note :When outputting the f 8, f32 or fc from port P53/BCLK/ALE/CLKOUT pin in single chip mode, use port P57/RDY as an input only port.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 48 8. Clock Generating CircuitpuorG08/C61M Table 8.2 Clock output setting (single chip mode) Table 8.3 Clock output setting (memory expansion/microprocessor mode)

8.4 Stop Mode

Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcom- puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC re- mains above 2V. Because the oscillation of BCLK, f 1 to f32, f1SIO2 to f32SIO2, fc, fc32, and fAD stops in stop mode, peripheral functions such as the A/D converter and watchdog timer do not function. However, timer A and timer B operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2) functions provided an external clock is selected. Table 8.4 shows the status of the ports in stop mode. Stop mode is cancelled by a hardware reset or interrupt. When using an interrupt to exit stop mode, the relevant interrupt must have been enabled and set to a priority level above the level set by the interrupt priority set bits (bits 2, 1, and 0 at address 009F 16) for exiting a stop/wait state. Set the interrupt priority set bits for the exit from a stop/wait state to the same level as the flag register (FLG) processor interrupt level (IPL). Figure 8.6 shows the exit priority register. The priority level of the interrupt which is not used to cancel stop mode, must have been changed to 0. When exiting stop mode using an interrupt, the relevant interrupt routine is executed. If only a hardware reset or an NMI interrupt is used to cancel stop mode, change the priority level of all interrupt to 0, then shift to stop mode. When shifting to stop mode and reset, the main clock division register (000C 16) is set to “0816”. PM07 CM01 CM00 PM14 P53/BCLK/ALE/CLKOUT pin function Ignored Ignored Ignored Ignored Ignored Ignored Ignored Ignored PM15 P53 I/O port fc output f8 output f32 output BCLK output function select bit Clock output function select bit ALE pin select bit Note :Must use P5 7 as input port. (Note) (Note) (Note) 1 1 1 BCLK output "L" output (not P53) fc output f8 output 0 0 1 f32 output ALE output PM07 CM01 CM00 PM14 P53/BCLK/ALE/CLKOUT pin function Ignored PM15 BCLK output function select bit Clock output function select bit ALE pin select bit

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 49 8. Clock Generating CircuitpuorG08/C61M Pin Memory expansion mode Single-chip mode Microprocessor mode Address bus, data bus, CS0 to CS3, BHERetains status before stop mode RD, WR, WRL, WRH, DW, CASL, “H ” (Note) CASH RAS “H ” (Note) HLDA, BCLK “H ” ALE “H ” Port Retains status before stop modeRetains status before stop mode CLK OUT When fc selected “H ”“ H ” When f8, f32 selected Retains status before stop mode Retains status before stop mode Note :When self-refresh is done in operating DRAM control, CAS and RAS becomes “L”. Table 8.4 Port status during stop mode Figure 8.6 Exit priority register Exit priority register Symbol Address When reset RLVL 009F 16 XXXX0000 2 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 : Level 0 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 FSIT RLVL1 RLVL2 RLVL0 Interrupt priority set bit for exiting Stop/Wait state (Note 1,2) Note 1: Exits the Stop or Wait mode when the requested interrupt priority level is higher than that set in the exit priority register. Note 2: Set to the same value as the processor interrupt priority level (IPL) set in the flag register (FLG). Note 3: The high-speed interrupt can only be specified for interrupts with interrupt priority level 7. Specify interrupt priority level 7 for only one interrupt. WR Nothing is assigned. When write, set "0". When read, their contents are indeterminate. 0: Interrupt priority level 7 = normal interrupt 1: Interrupt priority level 7 = high-speed interrupt High-speed interrupt set bit (Note 3) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 50 8. Clock Generating CircuitpuorG08/C61M If only a hardware reset or an NMI interrupt is used to cancel stop mode, change the priority level of all interrupt to 0, then shift to wait mode. Table 8.5 Port status during wait mode Pin Memory expansion mode Single-chip mode Microprocessor mode Address bus, data bus, CS0 to CS3,Retains status before wait mode BHE RD, WR, WRL, WRH, DW, CASL, “H ” (Note) CASH RAS “H ” (Note) HLDA,BCLK “H ” ALE “L” Port Retains status before wait mode Retains status before wait mode CLK OUT When fC selected Does not stop When f8, f32 selected Does not stop when the WAIT peripheral function clock stop bit is “0”. When the WAIT peripheral function clock stop bit is “1”, the status immediately prior to entering wait mode is main- tained. Note :When self-refresh is done in operating DRAM control, CAS and RAS becomes “L”.

8.5 Wait Mode

When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but the BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. Table 8.5 shows the status of the ports in wait mode. Wait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, the microcomputer restarts using as BCLK the clock that had been selected when the WAIT instruction was executed. When using an interrupt to exit Wait mode, the relevant interrupt must have been enabled and set to a priority level above the level set by the interrupt priority set bits for exiting a stop/wait state (bits 2, 1, and 0 at address 009F 16). Set the interrupt priority set bits for the exit from a stop/wait state to the same level as the flag register (FLG) processor interrupt level (IPL). The priority level of the interrupt which is not used to cancel wait mode, must have been changed to 0. When using an interrupt to exit Wait mode, the microcomputer resumes operating the clock that was oper- ating when the WAIT command was executed as BCLK from the interrupt routine.

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8.6 Status Transition of BCLK

Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table 8.6 shows the operating modes corresponding to the settings of system clock control regis- ters 0 and main clock division register. After a reset, operation defaults to division by 8 mode. When shifting to stop mode, reset or stopping main clock, the main clock division register (address 000C 16) is set to “0816”. (1) Division by 2 mode The main clock is divided by 2 to obtain the BCLK. (2) Division by 3 mode The main clock is divided by 3 to obtain the BCLK. (3) Division by 4 mode The main clock is divided by 4 to obtain the BCLK. (4) Division by 6 mode The main clock is divided by 6 to obtain the BCLK. (5) Division by 8 mode The main clock is divided by 8 to obtain the BCLK. After reset, this mode is executed. Note that oscillation of the main clock must have stabilized before transferring from this mode to no-division, division by 2, 6, 10, 12, 14 and 16 mode. Oscillation of the sub clock must have stabilized before transferring to low-speed and low power dissipa- tion mode. (6) Division by 10 mode The main clock is divided by 10 to obtain the BCLK. (7) Division by 12 mode The main clock is divided by 12 to obtain the BCLK. (8) Division by 14 mode The main clock is divided by 14 to obtain the BCLK. (9) Division by 16 mode The main clock is divided by 16 to obtain the BCLK. (10) No-division mode The main clock is divided by 1 to obtain the BCLK. (11) Low-speed mode fC is used as BCLK. Note that oscillation of both the main and sub clocks must have stabilized before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled. (12) Low power dissipation mode fC is the BCLK and the main clock is stopped. When the main clock is stoped, the main clock division register (address 000C16) is set to the division by 8 mode.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 52 8. Clock Generating CircuitpuorG08/C61M 0 0 Invalid 1 0 0 1 0 No division 0 0 Invalid 0 0 0 1 0 Division by 2 mode 0 0 Invalid 0 0 0 1 1 Division by 3 mode 0 0 Invalid 0 0 1 0 0 Division by 4 mode 0 0 Invalid 0 0 1 1 0 Division by 6 mode 0 0 Invalid 0 1 0 0 0 Division by 8 mode 0 0 Invalid 0 1 0 1 0 Division by 10 mode 0 0 Invalid 0 1 1 0 0 Division by 12 mode 0 0 Invalid 0 1 1 1 0 Division by 14 mode 0 0 Invalid 0 0 0 0 0 Division by 16 mode 1 0 1 Invalid Invalid Invalid Invalid Invalid Low-speed mode 1 1 1 Invalid Invalid Invalid Invalid Invalid Low power dissipation mode CM07 CM05 CM04 MCD4 MCD3 MCD2 MCD1 MCD0 Operating mode of BCLK Table 8.6 Operating modes dictated by settings of system clock control register 0 and main clock division register Note: When count source of BCLK is changed from clock A to clock B (XIN to XCIN or XCIN to XIN), clock B needs to be stable before changing. Please wait to change modes until after oscillation has stabilized. CM0i: Clock control register 0 (address 000616) bit i MCDi: Main clock division register (address 000C16) bit i

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8.7 Power Saving

In Power Save modes, the CPU and oscillator stop and the operating clock is slowed to minimize power dissipation by the CPU. The following outlines the Power Save modes. There are three power save modes. (1) Normal operating mode

High-speed mode In this mode, one main clock cycle forms BCLK. The CPU operates on the selected internal clock. The peripheral functions operate on the clocks specified for each respective function.
Medium-speed mode In this mode, the main clock is divided into 2, 3, 4, 6, 8, 10, 12, 14, or 16 to form BCLK. The CPU operates on the selected internal clock. The peripheral functions operated on the clocks specified for each respective function.
Low-speed mode In this mode, fc forms BCLK. The CPU operates on the fc clock. fc is the clock supplied by the subclock. The peripheral functions operate on the clocks specified for each respective function.
Low power-dissipation mode This mode is selected when the main clock is stopped from low-speed mode. The CPU operates on the fc clock. fc is the clock supplied by the subclock. Only the peripheral functions for which the subclock was selected as the count source continue to run. (2) Wait mode CPU operation is halted in this mode. The oscillator continues to run. (3) Stop mode All oscillators stop in this mode. The CPU and internal peripheral functions all stop. Of all 3 power saving modes, power savings are greatest in this mode. Figure 8.7 shows the clock transition between each of the three modes, (1), (2), and (3).

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 54 8. Clock Generating CircuitpuorG08/C61M Figure 8.7 Clock transition Wait mode CPU operation stopped CM10= “1” Transition of stop mode, wait mode BCLK :f(XIN)/8 CM07= “0” MCD=“0816” Main clock is oscillating Sub clock is oscillating Main clock is oscillating Sub clock is stopped Note 1: Switch clocks after oscillation of main clock is fully stable. Note 2: Switch clocks after oscillation of sub clock is fully stable. Note 3: Set the desired division to the main clock division register (MCD). Note 4: When shifting to division by 8 mode, MCD is set to "08 16". Main clock is oscillating Sub clock is stopped CM04= “1” MCD= “XX 16” Note 1, 3 CM04= “0” BCLK :f(XIN)/division rate CM07= “0” MCD=“XX 16” Note 4 BCLK :f(XIN) CM07= “0” MCD=“1216” High-speed mode Medium-speed mode (divided-by-2, 3, 4, 6, 8, 10, 12, 14 and 16 mode) BCLK :f(XIN)/division rate CM07= “0” MCD=“XX 16” Note 4 BCLK :f(XIN) CM07= “0” MCD=“1216” High-speed mode Medium-speed mode (divided-by-2, 3, 4, 6, 10, 12, 14 and 16 mode) Medium-speed mode (divided-by-8 mode) Transition of normal mode Normal mode CM10= “1” Stop mode All oscillators stopped Wait mode CPU operation stopped CM04= “1” CM05= “0” Note 4 BCLK :f(XCIN) CM07= “1” Low-speed mode BCLK :f(XCIN) CM07= “1” Main clock is oscillating Sub clock is oscillating MCD= “XX 16” Note 1, 3 CM07= “0 Note 1 MCD= “XX 16” Note 3 CM07= “1” Note 2 CM10= “1” Stop mode All oscillators stopped Wait mode CPU operation stopped (Please see the following as transition of normal mode.) CM07= “0” Note 1 MCD= “XX 16” Note 3 CM04= “1” Interrupt WAIT instruction Interrupt WAIT instruction Interrupt WAIT instruction Interrupt Interrupt Interrupt Low power dissipation mode CM05= “1” High-speed/medium- speed mode Low-speed/low power dissipation mode Medium-speed mode (Divided-by-8 mode) Note 1 Note 2Note 1 Note 1: Switch clocks after oscillation of main clock is fully stable. After stop mode or when main clock oscillation is stopped, transferred to the middle speed mode. Note 2: Switch clocks after oscillation of sub clock is fully stable. Note 3: The main ckock devision register is set to the division by 8 mode (MCD="08 16"). Note 4: When shifting to low power dissipation mode, the main ckock devision register is set to the division by 8 mode (MCD="0816"). Please change according to a direction of an arrow. High-speed/medium-speed mode Low-speed/low power dissipation mode Main clock is stopped Sub clock is oscillating Reset Note 4 Note 3

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8.8 Protection

The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 8.8 shows the protect register. The values in the processor mode register 0 (address 0004 16), processor mode register 1 (address 000516), system clock control reg- ister 0 (address 000616), system clock control register 1 (address 000716), main clock division register (address 000C16), port P9 direction register (address 03C716) and function select register A3 (address 03B516) can only be changed when the respective bit in the protect register is set to “1”. Therefore, impor- tant outputs can be allocated to port P9. If, after “1” (write-enabled) has been written to the PRC2 (bit 2 at address 000A 16), a value is written to any address, the bit automatically reverts to “0” (write-inhibited). Change port P9 input/output and function select register A3 immediately after setting "1" to PRC2. Interrupt and DMA transfer should not be inserted between instructions. However, the PRC0 (bit 0 at address 000A 16) and PRC1 (bit 1 at address 000A16) do not automatically return to “0” after a value has been written to an address. The program must therefore be written to return these bits to “0”. Protect register Symbol Address When reset PRCR 000A 16 XXXXX000 2 Bit nameBit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : Write-inhibited 1 : Write-enabled PRC1 PRC0 PRC2 Enables writing to processor mode registers 0 and 1 (addresses 000416 and 000516) Function 0 : Write-inhibited 1 : Write-enabled Enables writing to system clock control registers 0 and 1 (addresses 0006 16 and 000716) and main clock division register (address 000C16) Enables writing to port P9 direction register (address 03C716) and function select register A3 (address 03B516) (Note) 0 : Write-inhibited 1 : Write-enabled WR Nothing is assigned. When write, set "0". When read, their contents are indeterminate. Note: Writing a value to an address after “1” is written to this bit returns the bit to “0”. Other bits do not automatically return to “0” and they must therefore be reset by the program. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Figure 8.8 Protect register

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 56 9. Interrupt OutlinepuorG08/C61M Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction BRK2 instruction INT instruction Software Hardware Interrupt NMI Watchdog timer Single step Address matched Special Peripheral I/O Figure 9.1 Classification of interrupts *1 Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system. High-speed interrupt can be used as highest priority in peripheral I/O interrupts. 9. Interrupt Outline

9.1 Types of Interrupts

Figure 9.1 lists the types of interrupts.

Maskable interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level.
Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level.

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9.2 Software Interrupts

Software interrupts are generated by some instruction that generates an interrupt request when ex- ecuted. Software interrupts are nonmaskable interrupts. (1) Undefined-instruction interrupt This interrupt occurs when the UND instruction is executed. (2) Overflow interrupt This interrupt occurs if the INTO instruction is executed when the O flag is 1. The following lists the instructions that cause the O flag to change: ABS, ADC, ADCF, ADD, ADDX, CMP, CMPX, DIV, DIVU, DIVX, NEG, RMPA, SBB, SCMPU, SHA, SUB, SUBX (3) BRK interrupt This interrupt occurs when the BRK instruction is executed. (4) BRK2 interrupt This interrupt occurs when the BRK2 instruction is executed. This interrupt is used exclusively for debugger purposes. You normally do not need to use this interrupt. (5) INT instruction interrupt This interrupt occurs when the INT instruction is executed after specifying a software interrupt number from 0 to 63. Note that software interrupt numbers 0 to 43 are assigned to peripheral I/O interrupts. This means that by executing the INT instruction, you can execute the same interrupt routine as used in peripheral I/O interrupts. The stack pointer used in INT instruction interrupt varies depending on the software interrupt number. For software interrupt numbers 0 to 31, the U flag is saved when an interrupt occurs and the U flag is cleared to 0 to choose the interrupt stack pointer (ISP) before executing the interrupt sequence. The previous U flag before the interrupt occurred is restored when control returns from the interrupt rou- tine. For software interrupt numbers 32 to 63, such stack pointer switchover does not occur. However, in peripheral I/O interrupts, the U flag is saved when an interrupt occurs and the U flag is cleared to 0 to choose ISP. Therefore movement of U flag is different by peripheral I/O interrupt or INT instruction in software interrupt number 32 to 43.

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9.3 Hardware Interrupts

There are Two types in hardware Interrupts; special interrupts and Peripheral I/O interrupts. (1) Special interrupts Special interrupts are nonmaskable interrupts.

Reset A reset occurs when the RESET pin is pulled low.
NMI interrupt This interrupt occurs when the NMI pin is pulled low.
Watchdog timer interrupt This interrupt is caused by the watchdog timer.
Address-match interrupt This interrupt occurs immediately before the instruction at the address indicated by the address match interrupt register is executed while the address match interrupt enable bit is set to “1”. This interrupt does not occur if any address other than the start address of an instruction is set in the address match register.
Single-step interrupt This interrupt is used exclusively for debugger purposes, do not use it in other circumstances. A single- step interrupt occurs when the D flag is set (= 1); in this case, an interrupt is generated after one instruction is executed. (2) Peripheral I/O interrupts A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func- tions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. The interrupt vector table is the same as the one for software interrupt numbers 0 through 43 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
Bus collision detection, start/stop condition detection interrupts (UART2, UART3, UART4), fault error interrupts (UART3, 4) This is an interrupt that the serial I/O bus collision detection generates. When I 2C mode is selected, start, stop condition interrupt is selected. When SS pin is selected, fault error interrupt is selected.
DMA0 through DMA3 interrupts These are interrupts that DMA generates.
Key-input interrupt ___ A key-input interrupt occurs if an “L” is input to the KI pin.
A/D conversion interrupt This is an interrupt that the A/D converter generates.
UART0, UART1, UART2/NACK, UART3/NACK and UART4/NACK transmission interrupt These are interrupts that the serial I/O transmission generates.
UART0, UART1, UART2/ACK, UART3/ACK and UART4/ACK reception interrupt These are interrupts that the serial I/O reception generates.
Timer A0 interrupt through timer A4 interrupt These are interrupts that timer A generates
Timer B0 interrupt through timer B5 interrupt These are interrupts that timer B generates.
INT0 interrupt through INT5 interrupt An INT interrupt selects a edge sense or a level sense. In edge sense, an INT interrupt occurs if either a rising edge or a falling edge or a both edge is input to the INT pin. In level sense, an INT interrupt occurs if either an "H" level or an "L" level is input to the INT pin.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 59 9. Interrupt OutlinepuorG08/C61M Figure 9.2 Format for specifying interrupt vector addresses /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Mid address /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Low address /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines High address /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 0 0 0 0 0 0 0 0 Vector address + 0 Vector address + 1 Vector address + 2 Vector address + 3 LSBMSB

9.4 High-speed interrupts

High-speed interrupts are interrupts in which the response is executed at 5 cycles and the return is 3 cycles. When a high-speed interrupt is received, the flag register (FLG) and program counter (PC) are saved to the save flag register (SVF) and save PC register (SVP) and the program is executed from the address shown in the vector register (VCT). Execute a FREIT instruction to return from the high-speed interrupt routine. High-speed interrupts can be set by setting “1” in the high-speed interrupt specification bit allocated to bit 3 of the exit priority register. Setting “1” in the high-speed interrupt specification bit makes the interrupt set to level 7 in the interrupt control register into a high-speed interrupt. You can only set one interrupt as a high-speed interrupt. When using a high-speed interrupt, do not set multiple interrupts as level 7 interrupts. The interrupt vector for a high-speed interrupt must be set in the vector register (VCT). When using a high-speed interrupt, you can use a maximum of two DMAC channels. The execution speed is improved when register bank 1 is used with high speed interrupt register selected by not saving registers to the stack but to the switching register bank. In this case, switch register bank mode for high-speed interrupt routine.

9.5 Interrupts and Interrupt Vector Tables

If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Figure 9.2 shows the format for specifying the address. Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 60 9. Interrupt OutlinepuorG08/C61M Interrupt source Vector table addresses Remarks Address (L) to address (H) Undefined instruction FFFFDC16 to FFFFDF16 Interrupt on UND instruction Overflow FFFFE0 16 to FFFFE316 Interrupt on INTO instruction BRK instruction FFFFE4 16 to FFFFE716 If content of FFFFE716 is filled with FF16, program execution starts from the address shown by the vector in the variable vector table Address match FFFFE8 16 to FFFFEB16 There is an address-matching interrupt enable bit Watchdog timer FFFFF0 16 to FFFFF316 NMI FFFFF8 16 to FFFFFB16 External interrupt by input to NMI pin Reset FFFFFC 16 to FFFFFF16 Table 9.1 Interrupt factors (fixed interrupt vector addresses) Interrupt source Vector table addresses Remarks Address (L) to address (H) BRK2 instruction Interrupt vector table register for emulator Interrupt for debugger 00002016 to 00002216 Single step Interrupt vector table register for emulator Interrupt for debugger 00002016 to 00002216 Table 9.2 Interrupt vector table register for emulator

Fixed vector tables The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFFDC 16 to FFFFFF16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table 9.1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables.
Vector table dedicated for emulator Table 9.2 shows interrupt vector address which is vector table register dedicated for emulator (ad- dress 000020 16 to 00002216). These instructions are not effected with interrupt enable flag (I flag) (non maskable interrupt). This interrupt is used exclusively for debugger purposes. You normally do not need to use this inter- rupt. Do not access to the interrupt vector table register dedicated for emulator (address 000020 16 to 00002216).
Variable vector tables The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the ad- dress the INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 9.3 shows the interrupts assigned to the variable vector tables and addresses of vector tables. Set an even address to the start address of vector table setting in INTB so that operating efficiency is increased.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 61 9. Interrupt OutlinepuorG08/C61M Table 9.3 Interrupt causes (variable interrupt vector addresses) Software interrupt number Interrupt sourceVector table address Address (L) to address (H) Remarks Cannot be masked I flag+0 to +3 (Note 1) BRK instructionSoftware interrupt number 0 +44 to +47 (Note 1) Software interrupt number 11 +48 to +51 (Note 1)Software interrupt number 12 +52 to +55 (Note 1)Software interrupt number 13 +56 to +59 (Note 1)Software interrupt number 14 +68 to +71 (Note 1)Software interrupt number 17 +72 to +75 (Note 1)Software interrupt number 18 +76 to +79 (Note 1)Software interrupt number 19 +80 to +83 (Note 1)Software interrupt number 20 +84 to +87 (Note 1)Software interrupt number 21 +88 to +91 (Note 1)Software interrupt number 22 +92 to +95 (Note 1)Software interrupt number 23 +96 to +99 (Note 1)Software interrupt number 24 +100 to +103 (Note 1)Software interrupt number 25 +104 to +107 (Note 1)Software interrupt number 26 +108 to +111 (Note 1)Software interrupt number 27 +112 to +115 (Note 1)Software interrupt number 28 +116 to +119 (Note 1)Software interrupt number 29 +120 to +123 (Note 1)Software interrupt number 30 +124 to +127 (Note 1)Software interrupt number 31 +128 to +131 (Note 1)Software interrupt number 32 +252 to +255 (Note 1)Software interrupt number 63 to Note 1: Address relative to address in interrupt table register (INTB). Note 2: When I C mode is selected, NACK/ACK, start/stop condition detection interrupts are selected. Note 3: The fault error interrupt is selected when SS pin is selected. Cannot be masked I flag +40 to +43 (Note 1)Software interrupt number 10 +60 to +63 (Note 1)Software interrupt number 15 +64 to +67 (Note 1)Software interrupt number 16 +32 to +35 (Note 1)Software interrupt number 8 +36 to +39 (Note 1)Software interrupt number 9 Timer B3 Timer B4 Timer B5 INT3 to DMA0 DMA1 Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 INT0 INT1 INT2 Software interrupt INT4 INT5 Bus collision detection, start/stop condition detection (UART2) (Note 2) UART0 transmit UART0 receive UART1 transmit UART1 receive Key input interrupt A/D UART2 transmit/NACK (Note 2) UART2 receive/ACK (Note 2) DMA2 DMA3 UART3 transmit/NACK (Note 2) UART3 receive/ACK (Note 2) UART4 transmit/NACK (Note 2) UART4 receive/ACK (Note 2) Bus collision detection, start/stop condition detection, fault error (UART3) (Note 2, 3) Bus collision detection, start/stop condition detection, fault error (UART4) (Note 2, 3) +132 to +135 (Note 1)Software interrupt number 33 +136 to +139 (Note 1)Software interrupt number 34 +140 to +143 (Note 1)Software interrupt number 35 +144 to +147 (Note 1)Software interrupt number 36 +148 to +151 (Note 1)Software interrupt number 37 +152 to +155 (Note 1)Software interrupt number 38 +156 to +159 (Note 1)Software interrupt number 39 +160 to +163 (Note 1)Software interrupt number 40 +164 to +167 (Note 1)Software interrupt number 41 +168 to +171 (Note 1)Software interrupt number 42 +172 to +175 (Note 1)Software interrupt number 43 +176 to +179 (Note 1)Software interrupt number 44

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9.6 Interrupt control registers

Peripheral I/O interrupts have their own interrupt control registers. Figure 9.3 shows the interrupt control registers. When using an interrupt to exit Stop mode or Wait mode, the relevant interrupt must have been enabled and set to a priority level above the level set by the interrupt priority set bits for exit a stop/wait state (bits 2, 1, and 0 at address 009F 16). Set the interrupt priority set bits for the exit from a stop/wait state to the same level as the flag register (FLG) processor interrupt level (IPL). Figure 9.4 shows the exit priority register.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 63 9. Interrupt OutlinepuorG08/C61M Figure 9.3 Interrupt control register Symbol Address When reset INTiIC(i=0 to 5) 009E16, 007E16, 009C16, 007C16, 009A16, 007A16 XX00X000 2 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines ILVL0 IR POL Nothing is assigned. When write, set "0". When read, their contents are indeterminate. Interrupt priority level select bit Interrupt request bit Polarity select bit Level sense/edge sense select bit 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge or L level 1 : Selects rising edge or H level ILVL1 ILVL2 Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: When INT3 to INT5 are used for data bus in microprocessor mode or memory expansion mode, set the interrupt disabled to INT3IC, INT4IC and INT5IC. Note 3: When level sense is selected, set related bit of interrupt cause select register ( address 031F16) to one edge. (Note 1) Interrupt control register b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Bit name FunctionBit symbol WR Symbol Address When reset ADIC 0073 16 XXXXX000 2 BCNiIC(i=2 to 4) 008F 16, 007116, 009116 XXXXX000 2 DMiIC(i=0 to 3) 0068 16, 008816, 006A16, 008A16 XXXXX000 2 KUPIC 0093 16 XXXXX000 2 TAiIC(i=0 to 4) 006C 16, 008C16, 006E16, 008E16, 007016 XXXXX000 2 TBiIC(i=0 to 5) 009416, 007616, 009616, 007816, 009816, 006916 XXXXX000 2 SiTIC(i=0 to 4) 0090 16, 009216, 008916, 008B16, 008D16 XXXXX000 2 SiRIC(i=0 to 4) 0072 16, 007416, 006B16, 006D16, 006F16 XXXXX000 2 ILVL0 IR Interrupt priority level select bit Interrupt request bit 0 : Interrupt not requested 1 : Interrupt requested ILVL1 ILVL2Nothing is assigned. When write, set "0". When read, their contents are indeterminate. (Note) Note: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 0 : Edge sense 1 : Level senseLVS (Note 2) (Note 3)

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9.7 Interrupt Enable Flag (I Flag)

The interrupt enable flag (I flag) is used to disable/enable maskable interrupts. When this flag is set (= 1), all maskable interrupts are enabled; when the flag is cleared to 0, they are disabled. This flag is automatically cleared to 0 after a reset is cleared.

9.8 Interrupt Request Bit

This bit is set (= 1) by hardware when an interrupt request is generated. The bit is cleared to 0 by hardware when the interrupt request is acknowledged and jump to the interrupt vector. This bit can be cleared to 0 (but cannot be set to 1) in software.

9.9 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)

Interrupt priority levels are set by the interrupt priority select bit in an interrupt control register. When an interrupt request is generated, the interrupt priority level of this interrupt is compared with the processor interrupt priority level (IPL). This interrupt is enabled only when its interrupt priority level is greater than the processor interrupt priority level (IPL). This means that you can disable any particu- lar interrupt by setting its interrupt priority level to 0. Figure 9.4 Exit priority register Exit priority register Symbol Address When reset RLVL 009F 16 XXXX0000 2 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 : Level 0 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 FSIT RLVL1 RLVL2 RLVL0 Interrupt priority set bit for exiting Stop/Wait state (Note 1,2) Note 1: Exits the Stop or Wait mode when the requested interrupt priority level is higher than that set in the exit priority register. Note 2: Set to the same value as the processor interrupt priority level (IPL) set in the flag register (FLG). Note 3: The high-speed interrupt can only be specified for interrupts with interrupt priority level 7. Specify interrupt priority level 7 for only one interrupt. WR Nothing is assigned. When write, set "0". When read, their contents are indeterminate. 0: Interrupt priority level 7 = normal interrupt 1: Interrupt priority level 7 = high-speed interrupt High-speed interrupt set bit (Note 3) /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 65 9. Interrupt OutlinepuorG08/C61M 0 1 0 0 1 1 1 1 0 1 1 1 0 0 1 0 0 0 Low High 1 0 1 1 1 0 1 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 1 Table 9.5 IPL and Interrupt Enable LevelsTable 9.4 Interrupt Priority Levels Interrupt priority level select bitInterrupt priority levelPriority order b0b1b2 1 0 0 1 0 1 Processor interrupt priority level (IPL) Enabled interrupt priority levels IPL1 IPL0 Interrupt levels 1 and above are enabled. Interrupt levels 2 and above are enabled. Interrupt levels 3 and above are enabled. Interrupt levels 4 and above are enabled. Interrupt levels 5 and above are enabled. Interrupt levels 6 and above are enabled. Interrupt levels 7 and above are enabled. All maskable interrupts are disabled. Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 IPL2 Table 9.4 shows how interrupt priority levels are set. Table 9.5 shows interrupt enable levels in relation to the processor interrupt priority level (IPL). The following lists the conditions under which an interrupt request is acknowledged:

Interrupt enable flag (I flag) = 1
Interrupt request bit = 1
Interrupt priority level > Processor interrupt priority level (IPL) The interrupt enable flag (I flag), interrupt request bit, interrupt priority level select bit, and the proces- sor interrupt priority level (IPL) all are independent of each other, so they do not affect any other bit.

9.10 Rewrite the interrupt control register

When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 66 9. Interrupt OutlinepuorG08/C61M Figure 9.5 Interrupt response time (a) The period from the occurrence of an interrupt to the completion of the instruction under execution. (b) The time required for executing the interrupt sequence. (a) (b) Time Instruction Interrupt response time Instruction in interrupt routineInterrupt sequence Interrupt request acknowledgedInterrupt request generated

9.11 Interrupt Sequence

An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SCMPU, SIN, SMOVB, SMOVF, SMOVU, SSTR, SOUT or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. In the interrupt sequence, the processor carries out the following in sequence given: (1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 000000 16 (address 00000216 when high-speed interrupt). After this, the related interrupt request bit is "0". (2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt se- quence in the temporary register (Note) within the CPU. (3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to “0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed) (4) Saves the content of the temporary register (Note 1) within the CPU in the stack area. Saves in the flag save register (SVF) in high-speed interrupt. (5) Saves the content of the program counter (PC) in the stack area. Saves in the PC save register (SVP) in high-speed interrupt. (6) Sets the interrupt priority level of the accepted instruction in the IPL. After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. Note: This register cannot be utilized by the user.

9.12 Interrupt Response Time

'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). Figure 9.5 shows the interrupt response time.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 67 9. Interrupt OutlinepuorG08/C61M Time (a) varies with each instruction being executed. The DIVX instruction requires a maximum time that consists of 24* cycles. Time (b) is shown in Table 9.6. * It is when the divisor is immediate or register. When the divisor is memory, the following value is added.

Normal addressing : 2 + X
Index addressing : 3 + X
Indirect addressing : 5 + X + 2Y
Indirect index addressing : 6 + X + 2Y X is number of wait of the divisor area. Y is number of wait of the indirect address stored area. When X and Y are in odd address or in 8 bits bus area, double the value of X and Y. Table 9.6 Interrupt Sequence Execution Time 8 bits data bus 16 cycles 16 cycles 14 cycles 14 cycles 15 cycles 16 cycles 19 cycles 19 cycles 21 cycles 16 bits data bus 14 cycles 16 cycles 12 cycles 14 cycles 13 cycles 14 cycles 17 cycles 19 cycles 19 cycles Interrupt vector address Even address Odd address (Note 1) Even address Odd address (Note 1) Even address (Note 2) Even address (Note 2) Even address Odd address (Note 1) Even address (Note 2) Vector table is internal register Note 1: Allocate interrupt vector addresses in even addresses, if possible. Note 2: The vector table is fixed to even address. Note 3: The high-speed interrupt is independent of these conditions. Interrupt Peripheral I/O INT instruction NMI Watchdog timer Undefined instruction Address match Overflow BRK instruction (Variable vector table) Single step BRK2 instruction BRK instruction (Fixed vector table) High-speed interrupt (Note 3) 5 cycles

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9.14 Saving Registers

In an interrupt sequence, only the contents of the flag register (FLG) and program counter (PC) are saved to the stack area. The order in which these contents are saved is as follows: First, the FLG register is saved to the stack area. Next, the 16 high-order bits and 16 low-order bits of the program counter expanded to 32-bit are saved. Figure 9.6 shows the stack status before an interrupt request is acknowledged and the stack status after an interrupt request is acknowledged. In a high-speed interrupt sequence, the contents of the flag register (FLG) is saved to the flag save register (SVF) and program counter (PC) is saved to PC save register (SVP). If there are any other registers you want to be saved, save them in software at the beginning of the interrupt routine. The PUSHM instruction allows you to save all registers except the stack pointer (SP) by a single instruction. The execution speed is improved when register bank 1 is used with high speed interrupt register selected by not saving registers to the stack but to the switching register bank. In this case, switch register bank mode for high-speed interrupt routine. Figure 9.6 Stack status before and after an interrupt request is acknowledged Value that is set to IPL Not changed

9.13 Changes of IPL When Interrupt Request Acknowledged

When an interrupt request is acknowledged, the interrupt priority level of the acknowledged interrupt is set to the processor interrupt priority level (IPL). If an interrupt request is acknowledged that does not have an interrupt priority level, the value shown in Table 9.7 is set to the IPL. Table 9.7 Relationship between Interrupts without Interrupt Priority Levels and IPL Interrupt sources without interrupt priority levels Watchdog timer, NMI Reset Other [SP] Stack pointer value before interrupt occurs Stack status before interrupt request is acknowledged Address Stack status after interrupt request is acknowledged m-6 m-5 m –4 m –3 m –2 m –1 m m+1 LSBMSBLSBMSB Address Stack area Stack area Flag register (FLG Program counter (PCH ) Flag register (FLG H ) Content of previous stack Content of previous stack Content of previous stack Content of previous stack Program counter (PCL) Program counter (PCM ) [SP] New stack pointer value m-6 m-5 m –4 m –3 m –2 m –1 m m+1 0 0

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9.16 Interrupt Priority

If two or more interrupt requests are sampled active at the same time, whichever interrupt request is acknowledged that has the highest priority. Maskable interrupts (Peripheral I/O interrupts) can be assigned any desired priority by setting the inter- rupt priority level select bit accordingly. If some maskable interrupts are assigned the same priority level, the priority between these interrupts is resolved by the priority that is set in hardware. Certain nonmaskable interrupts such as a reset (reset is given the highest priority) and watchdog timer interrupt have their priority levels set in hardware. Figure 9.7 lists the hardware priority levels of these interrupts. Software interrupts are not subjected to interrupt priority. They always cause control to branch to an interrupt routine whenever the relevant instruction is executed.

9.17 Interrupt Resolution Circuit

Interrupt resolution circuit selects the highest priority interrupt when two or more interrupt requests are sampled active at the same time. Figure 9.8 shows the interrupt resolution circuit. Reset > NMI > Watchdog > Peripheral I/O > Single step > Address match

9.15 Return from Interrupt Routine

As you execute the REIT instruction at the end of the interrupt routine, the contents of the flag register (FLG) and program counter (PC) that have been saved to the stack area immediately preceding the interrupt sequence are automatically restored. In high-speed interrupt, as you execute the FREIT instruc- tion at the end of the interrupt routine, the contents of the flag register (FLG) and program counter (PC) that have been saved to the save registers immediately preceding the interrupt sequence are automati- cally restored. Then control returns to the routine that was under execution before the interrupt request was acknowl- edged, and processing is resumed from where control left off. If there are any registers you saved via software in the interrupt routine, be sure to restore them using an instruction (e.g., POPM instruction) before executing the REIT or FREIT instruction. When switching the register bank before executing REIT and FREIT instruction, switched to the register bank immediately before the interrupt sequence. Figure 9.7 Interrupt priority that is set in hardware

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 70 9. Interrupt OutlinepuorG08/C61M Figure 9.8 Interrupt resolution circuit Timer B2 Timer B0 Timer A0 Timer A1 Timer B1 UART1 reception UART0 reception UART2 reception/ACK A/D conversion Bus collision/start, stop condition(UART2)UART1 transmission UART0 transmission UART2 transmission/NACK Key input interrupt Processor interrupt priority level (IPL) Interrupt enable flag (I flag) INT5 INT2 INT0 Watchdog timer Reset DBC NMI Interrupt request accepted. To CPU Level 0 (initial value) Priority level of each interruptHigh Low Priority of peripheral I/O interrupts (if priority levels are same) INT3 Address match Timer B4 Timer B3 DMA0 DMA1 DMA2 DMA3 Timer A2 Timer A3 Timer A4 INT4 INT1 Timer B5 UART3 reception/ACK UART3 transmission/NACK UART4 reception/ACK UART4 transmission/NACK Bus collision/start, stop condition/fault error (UART3) Bus collision/start, stop condition/fault error (UART4) Instruction fetch Stop/wait return interrupt level (RLVL) Interrupt request priority detection results output (to clock generation circuit)

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9.18 INT Interrupts

INT0 to INT5 are external input interrupts. The level sense/edge sense switching bits of the interrupt control register select the input signal level and edge at which the interrupt can be set to occur on input signal level and input signal edge. The polarity bit selects the polarity. With the external interrupt input edge sense, the interrupt can be set to occur on both rising and falling edges by setting the INTi interrupt polarity switch bit of the interrupt request select register (address 031F 16) to “1”. When you select both edges, set the polarity switch bit of the corresponding interrupt control register to the falling edge (“0”). When you select level sense, the INTi interrupt polarity switch bit of the interrupt request select register (address 031F 16) to “0”. Figure 9.9 shows the interrupt request select register. Figure 9.9 Interrupt request cause select register Interrupt request cause select register Bit name FumctionBit symbol WR Symbol Address When reset IFSR 031F 16 XX000000 2 IFSR0 b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines INT0 interrupt polarity swiching bit (Note) 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges INT1 interrupt polarity swiching bit (Note) INT2 interrupt polarity swiching bit (Note) INT3 interrupt polarity swiching bit (Note) INT4 interrupt polarity swiching bit (Note) INT5 interrupt polarity swiching bit (Note) 0 : One edge 1 : Two edges IFSR1 IFSR2 IFSR3 IFSR4 IFSR5 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines Nothing is assigned. When write, set "0". When read, their contents are indeterminate. Note :When level sense is selected, set this bit to "0".

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 72 9. Interrupt OutlinepuorG08/C61M Interrupt control circuit Key input interrupt control register (address 009316) Key input interrupt request P107/KI3 P106/KI2 P105/KI1 P104/KI0 Port P104-P107 pull-up select bit Port P107 direction register Port P107 direction register Port P106 direction register Port P105 direction register Port P104 direction register Pull-up transistor Pull-up transistor Pull-up transistor Pull-up transistor key input interrupt disable bit Figure 9.10 Block diagram of key input interrupt

9.19 NMI Interrupt

An NMI interrupt is generated when the input to the P85/NMI pin changes from “H ” to “L”. The NMI interrupt is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address 03C4 16). This pin cannot be used as a normal port input. Notes: When not intending to use the NMI function, be sure to connect the NMI pin to VCC (pulled-up). The NMI interrupt is non-maskable. Because it cannot be disabled, the pin must be pulled up.

9.20 Key Input Interrupt

If the direction register of any of P104 to P107 is set for input and a falling edge is input to that port, a key input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancel- ling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P10 4 to P107 as A/D input ports. Figure 9.10 shows the block diagram of the key input interrupt. Note that if an “L” level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an interrupt. Setting the key input interrupt disable bit (bit 7 at address 03AF 16) to “1” disables key input interrupts from occurring regardless of the setting in the interrupt control register. When “1” is set in the key input interrupt disable register, there is no input via the port pin even when the direction register is set to input.

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9.21 Address Match Interrupt

An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Four address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not affected by the inter- rupt enable flag (I flag) and processor interrupt priority level (IPL). Figure 9.11 shows the address match interrupt-related registers. Set the start address of an instruction to the address match interrupt register. Address match interrupt is not generated when address such as the middle of instruction or table data is set. Bit nameBit symbol Symbol Address When reset AIER 0009 16 XXXX0000 2 Address match interrupt enable register Function WR /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Address match interrupt 0 enable bit 0 : Interrupt disabled 1 : Interrupt enabled AIER0 Address match interrupt 1 enable bit AIER1 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Symbol Address When reset RMAD0 0012 16 to 001016 00000016 RMAD1 0016 16 to 001416 00000016 RMAD2 001A 16 to 001816 00000016 RMAD3 001E 16 to 001C16 00000016 Nothing is assigned. When write, set "0". When read, their contents are indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 WR Address setting register for address match interrupt Function Values that can be set Address match interrupt register i (i = 0 ot 3) 00000016 to FFFFFF16 0 : Interrupt disabled 1 : Interrupt enabled b0 b7 b0 (b16) b7 b0 (b15) (b8) (b23) /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Address match interrupt 2 enable bit 0 : Interrupt disabled 1 : Interrupt enabled AIER2 Address match interrupt 3 enable bit AIER3 0 : Interrupt disabled 1 : Interrupt enabled /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Figure 9.11 Address match interrupt-related registers

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9.22 Precautions for Interrupts

(1) Reading addresses 00000016 and 00000216

When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence from address 00000016. When high-speed interrupt is occurred, CPU read from address 00000216. The interrupt request bit of the certain interrupt will then be set to “0”. However, reading addresses 00000016 and 00000216 by software does not set request bit to “0”. (2) Setting the stack pointer
The value of the stack pointer immediately after reset is initialized to 00000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point at the beginning of a program. Any interrupt including the NMI interrupt is generated immediately after executing the first instruction after reset. Set an even address to the stack pointer so that the operating efficiency of accessign memory is increased. (3) The NMI interrupt
As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the Vcc pin via a resistance (pull-up) if unused. Be sure to work on it.
The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time when the NMI interrupt is input.
Signals input to the NMI pin require "L" level and "H" level of 2 clock + 300ns or more, from the operation clock of CPU. (4) External interrupt
Edge sense Either an “L” level or an “H ” level of at least 250 ns width is necessary for the signal input to pins INT0 to INT5 regardless of the CPU operation clock.
Level sense Either an “L” level or an “H ” level of 1 cycle of BCLK + at least 200 ns width is necessary for the signal input to pins INT0 to INT5 regardless of the CPU operation clock. (When XIN=20MHz and no division mode, at least 250 ns width is necessary.)
When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0". Figure 9.12 shows the procedure for changing the INT interrupt generate factor.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 75 9. Interrupt OutlinepuorG08/C61M Figure 9.12 Switching condition of INT interrupt request Set the polarity select bit Clear the interrupt request bit to “0” Set the interrupt priority level to level 1 to 7 (Enable the accepting of INT interrupt request) Set the interrupt priority level to level 0 (Disable INT interrupt) (5) Rewrite the interrupt control register

When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET
When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit is not cleared sometimes. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : MOV (6) Address match interrupt
Do not set the following addresses to the address match interrupt register. 1. The address of the starting instruction in an interrupt routine. 2. Any of the next 7 instructions addresses immediately after an instruction to clear an interrupt request bit of an interrupt control register or an instruction to rewrite an interrupt priority level to a smaller value. 3. Any of the next 3 instructions addresses immediately after an instruction to set the interrupt enable flag (I flag). 4. Any of the next 3 instructions addresses immediately after an instruction to rewrite a processor inter- rupt priority level (IPL) to a smaller value.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 76 9. Interrupt OutlinepuorG08/C61M

To return from an interrupt to the address set in an address match interrupt register using return instruction (reit or freit) To rewrite the interrupt control register within the interrupt routine, add the below processing to the end of the routine (immediately before the reit or freit instruction). Also, if multiple interrupts are enabled with other interrupts, add the below processing to the end of the interrupt that enables the multiple interrupts. If the interrupt control register is being rewritten within the non-maskable interrupt routine, add the below processing to the end of all interrupts. Additional process ; Execute after the register reset instruction (popm instruction) fclr U ; Select ISP (Unnecessary if the ISP has been selected) pushm R0 ; Store R0 register mov.w 6[SP],R0 ; Read FLG on stack (use "stc SVF,R0" when high-speed ; interrupt) ldc R0,FLG ; Set in FLG popm R0 ; Restore R0 register nop ; Dummy reit ; Interrupt completed (use freit when high-speed interrupt) Example 1) Interrupt_A: ; Interrupt A routine pushm R0,R1,R2,R3,A0,A1 ; <----
••• ; Example 2) mov.b #0,TA0IC ;Change TA0 interrupt priority level to a smaller value nop ; 1st instruction nop ; 2nd instruction nop ; 3rd instruction nop ; 4th instruction nop ; 5th instruction nop ; 6th instruction nop ; 7th instruction Example 3) fset I ; Set I flag ( interrupt enabled) nop ; 1st instruction nop ; 2nd instruction nop ; 3rd instruction Example 4) ldipl #0 ; Rewrite IPL to a smaller value nop ; 1st instruction nop ; 2nd instruction nop ; 3rd instruction Do not set address match interrupt during this period Do not set address match interrupt during this period Do not set address match interrupt during this period Do not set address match interrupt to the start address of an interrupt instruction

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 77 9. Interrupt OutlinepuorG08/C61M Example 5) If rewriting the interrupt control register for interrupt B with the interrupt A routine and enabling multiple interrupts with interrupt C, the above processing is required at the end of the interrupt A and interrupt C routines. Interrupt A routine Interrupt_A: pushm R0,R1,R2,R3,A0,A1 ; Store registers

••• bclr 3,TA0IC ; Rewrite interrupt control register of interrupt B
••• popm R0,R1,R2,R3,A0,A1 ; Restore registers fclr U ; Select ISP (Unnecessary if the ISP has been selected) pushm R0 ; Store R0 register mov.w 6[SP],R0 ; Read FLG on stack ldc R0,FLG ; Set in FLG popm R0 ; Restore R0 register nop ; Dummy reit ; Interrupt completed Interrupt C routine Interrupt_C: pushm R0,R1,R2,R3,A0,A1 ; Store registers fset I ; Multiple interrupt enabled
•••
••• popm R0,R1,R2,R3,A0,A1 ;Restore registers fclr U ; Select ISP (Unnecessary if the ISP has been selected) pushm R0 ; Store R0 register mov.w 6[SP],R0 ; Read FLG on stack ldc R0,FLG ; Set in FLG popm R0 ; Restore R0 register nop ; Dummy reit ; Interrupt completed

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 78 10. Watchdog TimerpuorG08/C61M 10. Watchdog Timer The watchdog timer has the function of detecting when the program is out of control. Therefore, we recom- mend using the watchdog timer to improve reliability of a system. The watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. Whether a watchdog timer interrupt is generated or reset is selected when an underflow occurs in the watchdog timer. Watchdog timer interrupt is selected when bit 6 of the system control register 0 (address 0008 16 :CM06) is "0" and reset is selected when CM06 is "1". No value other than "1" can be written in CM06. Once when reset is selected (CM06="1"), watchdog timer interrupt cannot be selected by software. When X IN is selected for the BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000F16). Therefore, the watchdog timer cycle can be calculated as follows. However, errors can arise in the watchdog timer cycle due to the prescaler. When X IN is selected in BCLK Watchdog timer cycle = When X CIN is selected in BCLK Watchdog timer cycle = For example, when BCLK is 20MHz and the prescaler division ratio is set to 16, the monitor timer cycle is approximately 26.2 ms. The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by writing to the watchdog timer start register (address 000E 16). CM06 is initialized only at reset. After reset, watchdog timer interrupt is selected. The watchdog timer and the prescaler stop in stop mode, wait mode and hold status. After exiting these modes and status, counting starts from the value remained before. In the stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is resumed from the held value when the modes or state are released. Figure 10.1 shows the block diagram of the watchdog timer. Figure 10.2 shows the watchdog timer-related registers. "CM06=0" Watchdog timer interrupt request "CM06=1" Reset BCLK Write to the watchdog timer start register (address 000E 16) RESET Watchdog timer Set to “7FFF 16” “CM07 = 0” “WDC7 = 1 ” “CM07 = 0” “WDC7 = 0 ” “CM07 = 1” HOLD Prescaler Prescaler division ratio (16 or 128) x watchdog timer count (32768) BCLK Prescaler division ratio (2) x watchdog timer count (32768) BCLK Figure 10.1 Block diagram of watchdog timer

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 79 10. Watchdog TimerpuorG08/C61M Watchdog timer control register Symbol Address When reset WDC 000F 16 000XXXXX 2 FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 High-order bit of watchdog timer WDC7 Bit name Prescaler select bit 0 : Divided by 16 1 : Divided by 128 Watchdog timer start register Symbol Address When reset WDTS 000E

16 Indeterminate

The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to “7FFF 16” regardless of whatever value is written. Reserved bit Must always be set to “0” /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Figure 10.2 Watchdog timer control and start registers S y s t e m c l o c k c o n t r o l r e g i s t e r 0 ( N o t e 1 ) S y m b o lA d d r e s sW h e n r e s e t C M 6 0 B i t n a m e FunctionB i t s y m b o l b 7 b 6 b 5 b4 b 3 b 2 b 1 b 0 0 0 : I/O port P53 0 1 : fC output (Note 3) 1 0 : f8 output (Note 3) 1 1 : f32 output (Note 3) b b C M 0 7 C M 0 5 C M 0 4 CM03 CM01 C M 0 2 C M 0 0 Clock output function select bit (Note 2) W A I T p e r i p h e r a l f u n c t i o n c l o c k s t o p b i t 0 : D o n o t s t o p p e r i p h e r a l c l o c k i n w a i t m o d e S t o p p e r i p h e r a l c l o c k i n w a i t m o d e N o t e XCIN-XCOUT drive capacity select bit (Note 4) 0 : L O W H I G H P o r t X C s e l e c t b i t0 : I / O p o r t XC I N - XC O U T g e n e r a t i o n N o t e Main clock (XIN-XOUT) stop bit (Note 5, 6) 0 : On 1 : Off (Note 7) S y s t e m c l o c k s e l e c t b i t N o t e 0 : XI N , XO U T XC I N , XC O U T N o t e S e t b i t o f t h e p r o t e c t r e g i s t e r a d d r e s s t o b e f o r e w r i t i n g t o t h i s r e g i s t e r N o t e W h e n o u t p u t t i n g B C L K b i t o f p r o c e s s o r m o d e r e g i s t e r i s s e t t h e s e b i t s t o W h e n o u t p u t t i n g A L E t o P b i t a n d o f p r o c e s s o r m o d e r e g i s t e r i s s e t t h e s e b i t s t o T h e p o r t P f u n c t i o n i s n o t s e l e c t e d e v e n w h e n y o u s e t i n m i c r o p r o c e s s o r o r m e m o r y e x p a n s i o n m o d e a n d b i t o f t h e p r o c e s s o r m o d e r e g i s t e r i s N o t e W h e n s e l e c t i n g fC , o r i n s i n g l e c h i p m o d e m u s t u s e P a s i n p u t p o r t N o t e C h a n g e s t o w h e n s h i f t i n g t o s t o p m o d e o r r e s e t N o t e W h e n e n t e r i n g t h e p o w e r s a v i n g m o d e t h e m a i n c l o c k i s s t o p p e d u s i n g t h i s b i t T o s t o p t h e m a i n c l o c k s e t s y s t e m c l o c k s t o p b i t C M t o w h i l e a n o s c i l l a t i o n o f s u b c l o c k i s s t a b l e T h e n s e t t h i s b i t t o N o t e W h e n t h i s b i t i s XO U T i s H A l s o t h e i n t e r n a l f e e d b a c k r e s i s t a n c e r e m a i n s O N s o XI N i s p u l l e d u p t o XO U T H l e v e l v i a t h e f e e d b a c k r e s i s t a n c e N o t e W h e n t h e m a i n c l o c k i s s t o p p e d t h e m a i n c l o c k d i v i s i o n r e g i s t e r a d d r e s s C 1 i s s e t t o t h e d i v i s i o n b y m o d e N o t e W h e n h a s b e e n s e t o n c e c a n n o t b e w r i t t e n b y s o f t w a r e N o t e T o s e t C M f r o m f i r s t s e t C M t o a n d a n o s c i l l a t i o n o f s u b c l o c k i s s t a b l e T h e n s e t C M A l s o t o s e t C M f r o m f i r s t s e t C M t o a n d a n o s c i l l a t i o n o f m a i n c l o c k i s s t a b l e T h e n s e t C M D o n o t r e w r i t e C M a n d C M s i m u l t a n e o u s l y N o t e f i s n o t i n c l u d e d N o t e W h e n X cI N - X cO U T i s u s e d s e t p o r t P a n d P t o n o p u l l u p r e s i s t a n c e w i t h t h e i n p u t p o r t WR C M 0 6 W a t c h d o g t i m e r f u n c t i o n s e l e c t b i t 0 : W a t c h d o g t i m e r i n t e r r u p t R e s e t N o t e

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 80 11. DMACpuorG08/C61M 11. DMAC This microcomputer has four DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. DMAC is a function that to transmit 1 data of a source address (8 bits / 16 bits) to a destination address when transmission request occurs. When using three or more DMAC channels, the register bank 1 register and high-speed interrupt register are used as DMAC registers. If you are using three or more DMAC channels, you cannot, therefore, use high-speed interrupts. The CPU and DMAC use the same data bus, but the DMAC has a higher bus access privilege than the CPU, and because of the use of cycle-steeling, operations are performed at high-speed from the occurrence of a transfer request until one word (16 bits) or 1 byte (8 bits) of data have been sent. Figure 11.1 shows the mapping of registers used by the DMAC. Table 11.1 shows DMAC specifications. Figures 11.2 to 11.5 show the structures of the registers used. As the registers shown in Figure 11.1 is allocated in CPU, use LDC instruction when writing. When writing to DCT2, DCT3, DRC2, DRC3, DMA2 and DMA3, set register bank select flag (B flag) to "1" and use MOV instruction to set R0 to R3, A0 and A1 registers. When writing to DSA2 and DSA3, set register bank select flag (B flag) to "1" and use LDC instruction to set SB and FB registers. DMA mode register 0, 1 DMA0, 1 transfer count register DMA0,1 transfer count reload register DMA0, 1 memory address register DMA0, 1 SFR address register DMA0, 1 memory address reload register DMD0 DMD1 DCT0 DCT1 DRC0 DRC1 DMA0 DMA1 DSA0 DSA1 DRA0 DRA1 DMAC related register When using three or more DMAC channels The high-speed interrupt register is used as a DMAC register DMA2 transfer count register DMA2 transfer count reload register DMA2 memory address register DMA2 SFR address register DCT2 (R0) DCT3 (R1) DRC2 (R2) DRC3 (R3) DMA2 (A0) DMA3 (A1) DSA2 (SB) DSA3 (FB) When using DMA2 and DMA3, use the CPU registers shown in parentheses. When using three or more DMAC channels The register bank 1 is used as a DMAC register DMA3 transfer count register DMA3 transfer count reload register DMA3 memory address register DMA3 SFR address register SVF DMA2 memory address reload registerDRA2 (SVP) DRA1 (VCT) Flag save register DMA3 memory address reload register Figure 11.1 Register map using DMAC In addition to writing to the software DMA request bit to start DMAC transfer, the interrupt request signals output from the functions specified in the DMA request factor select bits are also used. However, in contrast to the interrupt requests, repeated DMA requests can be received, regardless of the interrupt flag. (Note, however, that the number of actual transfers may not match the number of transfer requests if the DMA request cycle is shorter than the DMR transfer cycle. For details, see the description of the DMAC request bit.)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 81 11. DMACpuorG08/C61M Item Specification No. of channels 4 (cycle steal method) Transfer memory space • From any address in the 16 Mbytes space to a fixed address (16 Mbytes space)

From a fixed address (16 Mbytes space) to any address in the 16 M bytes space Maximum No. of bytes transferred128 Kbytes (with 16-bit transfers) or 64 Kbytes (with 8-bit transfers) DMA request factors (Note) Falling edge of INT0 to INT3 or both edge Timer A0 to timer A4 interrupt requests Timer B0 to timer B5 interrupt requests UART0 to UART4 transmission and reception interrupt requests A/D conversion interrupt requests Software triggers Channel priority DMA0 > DMA1 > DMA2 > DMA3 (DMA0 is the first priority) Transfer unit 8 bits or 16 bits Transfer address direction forward/fixed (forward direction cannot be specified for both source and destination simultaneously) Transfer mode • Single transfer Transfer ends when the transfer count register is "000016".
Repeat transfer When the transfer counter is "000016", the value in the transfer counter reload register is reloaded into the transfer counter and the DMA transfer is continued DMA interrupt request generation timingWhen the transfer counter register changes from "000116" to "000016". DMA startup • Single transfer Transfer starts when DMA transfer count register is more than "0001 16" and the DMA is requested after “012” is written to the channel i transfer mode select bits
Repeat transfer Transfer starts when the DMA is requested after “112” is written to the channel i transfer mode select bits DMA shutdown • Single transfer When “002” is written to the channel i transfer mode select bits and DMA transfer count register becomes "000016" by DMA transfer or write
Repeat transfer When “002” is written to the channel i transfer mode select bits Reload timing When the transfer counter register changes from "0001 16" to "000016" in repeat transfer mode. Reading / writing the register Registers are always read/write enabled. Number of DMA transfer cycles Between SFR and internal RAM : 3 cycles Between external I/O and external memory : minimum 3 cycles Table 11.1 DMAC specifications Note: DMA transfer is not effective to any interrupt.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 82 11. DMACpuorG08/C61M DMAi request cause select register (i = 0 to 3)(Note 1) Symbol Address When reset DMiSL 0378 16 to 037B16 0X0000002 FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 DMA request cause select bitDSEL0 RW DSEL1 DSEL2 DSEL3 Nothing is assigned. When write, set "0". When read, its content is indeterminate. Software DMA request bit (Note 5) If software trigger is selected, a DMA request is generated by setting this bit to “1” (When read, the value of this bit is always “0”) DSR b4 b3 b2 b1 b0 0 0 0 0 0 : Software trigger 0 0 0 0 1 : Falling edge of INTi pin (Note 3) 0 0 0 1 0 : Two edges of INTi pin (Note 3) 0 0 0 1 1 : Timer A0 0 0 1 0 0 : Timer A1 0 0 1 0 1 : Timer A2 0 0 1 1 0 : Timer A3 0 0 1 1 1 : Timer A4 0 1 0 0 0 : Timer B0 0 1 0 0 1 : Timer B1 0 1 0 1 0 : Timer B2 0 1 0 1 1 : Timer B3 0 1 1 0 0 : Timer B4 0 1 1 0 1 : Timer B5 0 1 1 1 0 : UART0 transmit 0 1 1 1 1 : UART0 receive 1 0 0 0 0 : UART1 transmit 1 0 0 0 1 : UART1 receive 1 0 0 1 0 : UART2 transmit 1 0 0 1 1 : UART2 receive/ACK (Note 4) 1 0 1 0 0 : UART3 transmit 1 0 1 0 1 : UART3 receive/ACK (Note 4) 1 0 1 1 0 : UART4 transmit 1 0 1 1 1 : UART4 receive/ACK (Note 4) 1 1 0 0 0 : A/D conversion 1 1 0 0 1 to 1 1 1 1 1 : Inhibit /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Bit name DMA request bitDRQ 0 : Not requested 1 : Requested /LiteDiagLines /LiteDiagLines Note 1: Please refer to DMAC precautions. Note 2: Set DMA inhibit before changing the DMA request cause. Set DRQ to "1" simultaneously. e.g.) MOV.B #083h, DMiSL ; Set timer A0 Note 3: DMA0-INT0, DMA1-INT1, DMA2-INT2, and DMA3-INT3 correspond to DMAi and INTi. However, when INT3 pin becomes data bus in microprocessor mode, DMA3- INT3 cannot be used. Note 4: UARTi reception and ACK switching are effected using the UARTi special mode register and UARTi special mode register 2. Note 5: When setting DSR to "1", set DRQ to "1" using OR instruction etc. simultaneously. e.g.) OR.B #0A0h, DMiSL Note 6: Do not write "0" to this bit. There is no need to clear the DMA request bit. (Note 5,6) (Note 2) DSEL4 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Figure 11.2 DMAC register (1)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 83 11. DMACpuorG08/C61M DMA mode register 0 (CPU internal register) Symbol When reset DMD0 00 16 FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 Channel 0 transfer mode select bit MD00 RW MD01 BW0 RW0 MD11 b1 b0 0 0 : DMA inhibit 0 1 : Single transfer 1 0 : Reserved 1 1 : Repeat transfer /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Bit name MD10 Channel 0 transfer unit select bit 0 : 8 bits 1 : 16 bits Channel 0 transfer direction select bit 0 : Fixed address to memory (forward direction) 1 : Memory (forward direction) to fixed address Channel 1 transfer mode select bit BW1 RW1 b5 b4 0 0 : DMA inhibit 0 1 : Single transfer 1 0 : Reserved 1 1 : Repeat transfer /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Channel 1 transfer unit select bit 0 : 8 bits 1 : 16 bits Channel 1 transfer direction select bit DMA mode register 1 (CPU internal register) Symbol When reset DMD1 00 16 FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 Channel 2 transfer mode select bit MD20 RW MD21 BW2 RW2 MD31 b1 b0 0 0 : DMA inhibit 0 1 : Single transfer 1 0 : Reserved 1 1 : Repeat transfer /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Bit name MD30 Channel 2 transfer unit select bit 0 : 8 bits 1 : 16 bits Channel 2 transfer direction select bit Channel 3 transfer mode select bit BW3 RW3 b5 b4 0 0 : DMA inhibit 0 1 : Single transfer 1 0 : Reserved 1 1 : Repeat transfer /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Channel 3 transfer unit select bit 0 : 8 bits 1 : 16 bits Channel 3 transfer direction select bit 0 : Fixed address to memory (forward direction) 1 : Memory (forward direction) to fixed address 0 : Fixed address to memory (forward direction) 1 : Memory (forward direction) to fixed address 0 : Fixed address to memory (forward direction) 1 : Memory (forward direction) to fixed address Figure 11.3 DMAC register (2)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 84 11. DMACpuorG08/C61M Figure 11.4 DMAC register (3) Function RW

Transfer counter Set transfer number Symbol When reset DCT0 XXXX 16 DCT1 XXXX 16 DCT2 (bank 1;R0) (Note 1) 0000 16 DCT3 (bank 1;R1) (Note 1) 0000 16 DMAi transfer count register (i = 0 to 3) (CPU internal register) Transfer count specification 000016 to FFFF16 /LiteDiagLines/LiteDiagLines/LiteDiagLines Note 1: When setting DCT2 and DCT3, set "1" to the register bank select flag (B flag) of flag register (FLG), and then set desired value to R0 and R1 of register bank 1. Note 2: When "0" is set to this register, data transfer is not done even if DMA is requested. b15 b0 Function RW
Transfer count register reload value Set transfer number Symbol When reset DRC0 XXXX 16 DRC1 XXXX 16 DRC2 (bank 1;R2) (Note 1) 0000 16 DRC3 (bank 1;R3) (Note 1) 0000 16 DMAi transfer count reload register (i = 0 to 3) (CPU internal register) Transfer count specification 000016 to FFFF16 /LiteDiagLines/LiteDiagLines/LiteDiagLines Note: When setting DRC2 and DRC3, set "1" to the register bank select flag (B flag) of flag register (FLG), and then set desired value to R2 and R3 of register bank 1. b15 b0

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 85 11. DMACpuorG08/C61M Figure 11.5 DMAC register (4) b23 b0 Function RW

Memory address (Note 2) Set source or destination memory address Symbol When reset DMA0 XXXXXX 16 DMA1 XXXXXX 16 DMA2 (bank 1;A0) (Note 1) 000000 16 DMA3 (bank 1;A1) (Note 1) 000000 16 DMAi memory address register (i = 0 to 3) (CPU internal register) Transfer address specification area 00000016 to FFFFFF16 (16 Mbytes area)/LiteDiagLines/LiteDiagLines /LiteDiagLines Note 1: When setting DMA2 and DMA3, set "1" to the register bank select flag (B flag) of flag register (FLG), and set desired value to A0 and A1 of register bank 1. Note 2: When the transfer direction select bit is "0" (fixed address to memory), this register is destination memory address. When the transfer direction select bit is "1" (memory to fixed address), this register is source memory address. Function RW
SFR address (Note 2) Set source or destination fixed address Symbol When reset DSA0 XXXXXX 16 DSA1 XXXXXX 16 DSA2 (bank 1;SB) (Note 1) 000000 16 DSA3 (bank 1;FB) (Note 1) 000000 16 DMAi SFR address register (i = 0 to 3) (CPU internal register) Transfer address specification area 00000016 to FFFFFF16 (16 Mbytes area)/LiteDiagLines/LiteDiagLines /LiteDiagLines Note 1: When setting DSA2, set "1" to the register bank select flag (B flag) of flag register (FLG), and set desired value to SB of register bank 1. When setting DSA3, set "1" to the register bank select flag (B flag) of flag register (FLG), and set desired value to FB of register bank 1. Note 2: When the transfer direction select bit is "0" (fixed address to memory), this register is source fixed address. When the transfer direction select bit is "1" (memory to fixed address), this register is destination fixed address. Function RW
Memory address register reload value Set source or destination memory address Symbol When reset DRA0 XXXXXX 16 DRA1 XXXXXX 16 DRA2 (SVP) (Note) XXXXXX 16 DRA3 (VCT) (Note) XXXXXX 16 DMAi memory address reload register (i = 0 to 3) (CPU internal register) Transfer address specification area 00000016 to FFFFFF16 (16 Mbytes area) /LiteDiagLines/LiteDiagLines /LiteDiagLines Note: When setting DRA2, set desired value to save PC register (SVP). When setting DRA3, set desired value to vector register (VCT). b23 b23

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 86 11. DMACpuorG08/C61M (1) Transfer cycle The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) and the bus cycle in which the data is written to memory or to the SFR area (destination write). The number of read and write bus cycles depends on the source and destination addresses. In memory expansion mode and microprocessor mode, the number of read and write bus cycles also de- pends on the level of the BYTE pin. Also, the bus cycle itself is longer when software waits are inserted. (a) Effect of source and destination addresses When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there are one more source read cycle and destination write cycle than when the source and destination both start at even addresses. (b) Effect of external data bus width control register When in memory expansion mode or microprocessor mode, the transfer cycle changes according to the data bus width at the source and destination. 1. When transferring 16 bits of data and the data bus width at the source and at the destination is 8 bits (data bus width bit = “0”), there are two 8-bit data transfers. Therefore, two bus cycles are required for reading and two cycles for writing. 2. When transferring 16 bits of data and the data bus width at the source is 8 bits (data bus width bit = “0”) and the data bus width at the destination is 16 bits (data bus width bit = “1”), the data is read in two 8-bit blocks and written as 16-bit data. Therefore, two bus cycles are required for reading and one cycle for writing. 3. When transferring 16 bits of data and the data bus width at the source is 16 bits (data bus width bit = “1”) and the data bus width at the destination is 8 bits (data bus width bit = “0”), 16 bits of data are read and written as two 8-bit blocks. Therefore, one bus cycle is required for reading and two cycles for writing. (c) Effect of software wait When the SFR area or a memory area with a software wait is accessed, the number of cycles is increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK. Figure 11.6 shows the example of the transfer cycles for a source read. Figure 11.6 shows the destination is external area, the destination write cycle is shown as two cycle (one bus cycle) and the source read cycles for the different conditions. In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respective conditions to both the destination write cycle and the source read cycle. For example (2) in Figure 11.6, if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the source read cycle and the destination write cycle.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 87 11. DMACpuorG08/C61M BCLK Address bus RD signal WR signal Data bus CPU use CPU use CPU use CPU useSource Source Destination (1) •When 8-bit data is transferred

When 16-bit data is transferred on a 16-bit data bus and the source address is even BCLK Address bus RD signal WR signal Data bus CPU use CPU use CPU use CPU useSource Source (3) •When one wait is inserted into the source read under the conditions in (1) BCLK Address bus RD signal WR signal Data bus CPU use CPU use CPU use CPU useSource Source Source + 1 Source + 1 (2) •When 16-bit data is transferred and the source address is odd
When 16-bit data is transferred and the width of data bus at the source is 8-bit (When the width of data bus at the destination is 8-bit, there are also two destination write cycles). BCLK Address bus RD signal WR signal Data bus CPU use CPU use CPU use CPU useSource Source Source + 1 Source + 1 (4) •When one wait is inserted into the source read under the conditions in (2) (When 16-bit data is transferred and the width of data but at the destination is 8-bit, there are two destination write cycles). Note: The same timing changes occur with the respective conditions at the destination as at the source. Destination Destination Destination Destination Destination Destination Destination Figure 11.6 Example of the transfer cycles for a source read

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 88 11. DMACpuorG08/C61M Transfer unit Bus width Access address No. of read No. of write No. of read No. of write cycles cycles cycles cycles 16-bit Even 1111 8-bit transfers (DSi = “1”) O d d 1111 (BWi = “0”) 8-bit Even —— 11 (DSi = “0”) Odd —— 11 16-bit Even 1111 16-bit transfers (DSi = “1”) O d d 2222 (BWi = “1”) 8-bit Even —— 22 (DSi = “0”) Odd —— 22 Table 11.2 No. of DMAC transfer cycles Coefficient j, k (2) DMAC transfer cycles Any combination of even or odd transfer read and write addresses is possible. Table 11.2 shows the number of DMAC transfer cycles. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k Internal ROM/RAM SFR area Separate bus Multiplex bus No wait With wait No wait One wait Two waits Three waits Two waits Three waits j=1 j=2 j=2 j=1 j=2 j=3 j=4 j=3 j=4 k=1 k=2 k=2 k=2 k=2 k=3 k=4 k=3 k=4 Internal Memory External Memory DMA Request Bit The DMAC can issue DMA requests using preselected DMA request factors for each channel as trig- gers. The DMA transfer request factors include the reception of DMA request signals from the internal periph- eral functions, software DMA factors generated by the program, and external factors using input from external interrupt signals. See the description of the DMAi factor selection register for details of how to select DMA request factors. DMA requests are received as DMA requests when the DMAi request bit is set to “1” and the channel i transfer mode select bits are “01” or “11”. Therefore, even if the DMAi request bit is “1”, no DMA request is received if the channel i transfer mode select bit is “00”. In this case, DMAi request bit is cleared. Because the channel i transfer mode select bits default to “00” after a reset, remember to set the channel i transfer mode select bit for the channel to be activated after setting the DMAC related registers. This enables receipt of the DMA requests for that channel, and DMA transfers are then performed when the DMAi request bit is set. The following describes when the DMAi request bit is set and cleared. Memory expansion mode Microprocessor modeSingle-chip mode

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 90 11. DMACpuorG08/C61M Precautions for DMAC (1) Do not clear the DMA request bit of the DMAi request cause select register. In M16C/80, when a DMA request is generated while the channel is disabled (Note), the DMA transfer is not executed and the DMA request bit is cleared automatically. Note :The DMA is disabled or the transfer count register is "0". (2) When DMA transfer is done by a software trigger, set DSR and DRQ of the DMAi request cause select register to "1" simultaneously using the OR instruction. e.g.) OR.B #0A0h, DMiSL ; DMiSL is DMAi request cause select register (3) When changing the DMAi request cause select bit of the DMAi request cause select register, set "1" to the DMA request bit, simultaneously. In this case, set the corresponding DMA channel to disabled before changing the DMAi request cause select bit. At least 26 cycles are needed from the instruction to write to the DMAi request cause select register to enable DMA. Example) When DMA request cause is changed to timer A0 and using DMA0 in single transfer after DMA initial setting push.w R0 ; Store R0 register stc DMD0, R0 ; Read DMA mode register 0 and.b #11111100b, R0L ; Clear DMA0 transfer mode select bit to "00" ldc R0, DMD0 ; DMA0 disabled mov.b #10000011b, DM0SL ; Select timer A0 ; (Write "1" to DMA request bit simultaneously) push.w R0 ; Store R0 register mov.w #6,R0 ; dummy_loop: sbjnz.w #1,R0,dummy_loop ; Dummy cycle pop.w R0 ; Restore R0 register or.b #00000001b, R0L ; Set DMA0 single transfer ldc R0, DMD0 ; DMA0 enabled pop.w R0 ; Restore R0 register At least 26 cycles are needed until DMA enabled. (4) Recommended procedure for starting DMA transfer

When writing to the DMAi request cause register including overwriting the same value to the DMAi request cause register; 1. Disable the corresponding channel i DMA in DMA mode registers 0 and 1. 2. Set up the peripheral used as the source of the DMA transfer. However, the peripheral should remain disabled at this time. For example, when using UART0 transmit, disable UART0 transmit. 3. Set the DMAi request cause select register. At this time, write a '1' to the DMA request bit (bit 7)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 91 11. DMACpuorG08/C61M 4. Set the following SFR registers:

DMAiSFR address register
DMAI memory address reload register
DMAi memory address register
DMAi transfer count reload register
DMAi transfer count register 5. At this point, if the number of elapsed cycles are less than 26, add code (NOP's or other processing) to make up some time. 6. Enable the corresponding channel i DMA in the DMA mode registers 0 and 1. 7. Enable the peripheral used as the source of the DMA transfer. For example, when using UART0 transmit, enable UART0 transmit.
When not writing to the DMAi request cause register; 1. Disable the corresponding channel i DMA in the DMA mode registers 0 and 1. 2. Set up the peripheral used as the source of the DMA transfer. However, the peripheral should remain disabled at this time. For example, when using UART0 transmit, disable UART0 transmit. 3. Set up the following SFR registers:
DMAiSFR address register
DMAI memory address reload register
DMAi memory address register
DMAi transfer count reload register
DMAi transfer count register 4. Enable the corresponding channel i DMA in the DMA mode registers 0 and 1. 5. Enable the peripheral used as the source of the DMA transfer. For example, when using UART0 transmit, enable UART0 transmit. (5) Recommended procedure after completing DMA transfer
Disable the peripheral used as source of the DMA transfer to prevent generating a DMA request.
Disable the corresponding channel i DMA in the DMA mode registers 0 and 1.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 92 12. TimerpuorG08/C61M 12. Timer There are eleven 16-bit timers. These timers can be classified by function into timers A (five) and timers B (six). All these timers function independently. Count source for each timer becomes an operation clock for timer operation as counting and reloading, etc. Figures 12.1 and 12.2 show the block diagram of timers.• Timer mode

One-shot timer mode
PWM mode
Timer mode
One-shot timer mode
PWM mode
Timer mode
One-shot timer mode
PWM mode
Timer mode
One-shot timer mode
PWM mode
Timer mode
One-shot timer mode
PWM mode
Event counter mode
Event counter mode
Event counter mode
Event counter mode
Event counter mode TA0 IN TA1 IN TA2 IN TA3 IN TA4 IN Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 f1 f8 f32 fC32 Timer A0 interrupt Timer A1 interrupt Timer A2 interrupt Timer A3 interrupt Timer A4 interrupt Noise filter Noise filter Noise filter Noise filter Noise filter 1/32 fC32 f32 XIN XCIN Clock prescaler reset flag (bit 7 at address 034116) set to “1” Reset Clock prescaler Timer B2 overflow Figure 12.1 Timer A block diagram

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 93 12. TimerpuorG08/C61M Figure 12.2 Timer B block diagram

Event counter mode
Event counter mode
Event counter mode
Timer mode
Pulse width measuring mode
Timer mode
Pulse width measuring mode
Timer mode
Pulse width measuring mode TB0 IN TB1 IN TB2 IN Timer B0 Timer B1 Timer B2 f1 f8 f32 fC32 Timer B0 interruptNoise filter Noise filter Noise filter 1/32 fC32 f32 XIN XCIN Clock prescaler reset flag (bit 7 at address 034116) set to “1” Reset Clock prescaler Timer B2 overflow (to timer A count source)
Event counter mode
Event counter mode
Event counter mode
Timer mode
Pulse width measuring mode
Timer mode
Pulse width measuring mode
Timer mode
Pulse width measuring mode TB3 IN TB4 IN TB5 IN Timer B3 Timer B4 Timer B5 Timer B3 interruptNoise filter Noise filter Noise filter Timer B1 interrupt Timer B2 interrupt Timer B4 interrupt Timer B5 interrupt

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 95 13. Timer ApuorG08/C61M Figure 13.3 Timer A-related registers (2) Timer A4 up/down flag Timer A3 up/down flag Timer A2 up/down flag Timer A1 up/down flag Timer A0 up/down flag Timer A2 two-phase pulse signal processing select bit Timer A3 two-phase pulse signal processing select bit Timer A4 two-phase pulse signal processing select bit Symbol Address When reset UDF 0344 16 0016 TA4P TA3P TA2P Up/down flag (Note 1) Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 TA4UD TA3UD TA2UD TA1UD TA0UD 0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled (Note 2) When not using the two-phase pulse signal processing function, set the select bit to “0” Symbol Address When reset TABSR 0340 16 0016 Count start flag Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Timer B2 count start flag Timer B1 count start flag Timer B0 count start flag Timer A4 count start flag Timer A3 count start flag Timer A2 count start flag Timer A1 count start flag Timer A0 count start flag0 : Stops counting 1 : Starts counting TB2S TB1S TB0S TA4S TA3S TA2S TA1S TA0S Symbol Address When reset TA0 0347 16,034616 Indeterminate TA1 0349 16,034816 Indeterminate TA2 034B 16,034A16 Indeterminate TA3 034D 16,034C16 Indeterminate TA4 034F 16,034E16 Indeterminate b7 b0b7 b0 (b15) (b8) Timer Ai register (Note 1) WR

Timer mode 0000 16 to FFFF16 Counts an internal count source Function Values that can be set
Event counter mode 0000 16 to FFFF16 Counts pulses from an external source or timer overflow
One-shot timer mode (Note 2, 3) 0000 16 to FFFF16 Counts a one shot width
Pulse width modulation mode (16-bit PWM) (Note 2, 4) Functions as a 16-bit pulse width modulator
Pulse width modulation mode (8-bit PWM) (Note 2, 4) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 16 to FE16 (High-order address) 0016 to FF16 (Low-order address) 000016 to FFFE16 Note 1: Read and write data in 16-bit units. Note 2: Use MOV instruction to write to this register. Note 3: When the timer Ai register is set to "000016", the counter does not operate and the timer Ai interrupt request is not generated. When the pulse is set to output, the pulse does not output from the TAi OUT pin. Note 4: When the timer Ai register is set to "000016", the pulse width modulator does not operate and the output level of the TAiOUT pin remains "L" level, therefore the timer Ai interrupt request is not generated. This also occurs in the 8-bit pulse width modulator mode when the significant 8 high-order bits in the timer Ai register are set to "00 16". /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Note 1: Use MOV instruction to write to this register. Note 2: Set the corresponding port function select register A to I/O port, and port direction register to "0".

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 96 13. Timer ApuorG08/C61M Symbol Address When reset CPSRF 0341 16 0XXXXXXX 2 Clock prescaler reset flag Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Clock prescaler reset flag0 : No effect 1 : Prescaler is reset (When read, the value is “0”) CPSR WR Nothing is assigned. When write, set "0". When read, their contents are indeterminate. TA1TGL Symbol Address When reset TRGSR 0343 16 0016 Timer A1 event/trigger select bit 0 0 : Input on TA1IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected Trigger select register Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : Input on TA2IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA1 overflow is selected 1 1 : TA3 overflow is selected 0 0 : Input on TA3IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA2 overflow is selected 1 1 : TA4 overflow is selected 0 0 : Input on TA4IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA3 overflow is selected 1 1 : TA0 overflow is selected Timer A2 event/trigger select bit Timer A3 event/trigger select bit Timer A4 event/trigger select bit WR TA1TGH TA2TGL TA2TGH TA3TGL TA3TGH TA4TGL TA4TGH b1 b0 b3 b2 b5 b4 b7 b6 TA1OS TA2OS TA0OS One-shot start flag Symbol Address When reset ONSF 0342 16 0016 Timer A0 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag TA3OS TA4OS Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 TA0TGL TA0TGH 0 0 : Input on TA0IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA4 overflow is selected 1 1 : TA1 overflow is selected Timer A0 event/trigger select bit b7 b6 Note: Set the corresponding function select register A to I/O port, and port direction register to “0”. WR 1 : Timer start When read, the value is “0” /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Z phase input enable bitTAZIE 0 : Invalid 1 : Valid Note: Set the corresponding function select register A to I/O port, and port direction register to “0”. /LiteDiagLines /LiteDiagLines Figure 13.4 Timer A-related registers (3)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 97 13. Timer ApuorG08/C61M Item Specification Count source f 1, f8, f32, fc32 Count operation • Down count

When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingWhen the timer underflows TAiIN pin function Programmable I/O port or gate input TAiOUT pin function Programmable I/O port or pulse output (Setting by the corresponding function select registers A and B) Read from timer Count value can be read out by reading timer Ai register Write to timer • When not counting Value written to timer Ai register is written to both reload register and counter
When counting Value written to timer Ai register is written to only reload register (Transferred to counter at next reload time) Select function • Gate function Counting can be started and stopped by the TAiIN pin’s input signal
Pulse output function Each time the timer underflows, the TAiOUT pin’s polarity is reversed (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 13.1) Figure 13.5 shows the timer Ai mode register in timer mode. Table 13.1 Specifications of timer mode Note 1: The bit can be “0” or “1”. Note 2: Set the corresponding port function select register to I/O port, and port direction register to “0”. Timer Ai mode register Symbol Address When reset TAiMR(i=0 to 4) 035616 to 035A16 00000X002 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 Operation mode select bit 0 0 : Timer mode b1 b0 TMOD1 TMOD0 MR0 Gate function select bit0 X (Note 1): Gate function not available (TAiIN pin is a normal port pin) 1 0 : Timer counts only when TAiIN pin is held “L” (Note 2) 1 1 : Timer counts only when TAiIN pin is held “H ” (Note 2) b4 b3 MR2 MR1 MR3 0 (Set to “0” in timer mode) 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 TCK1 TCK0 Count source select bit 000 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines This bit is invalid in M16C/80 series. Port output control is set by the function select registers A and B.– – Figure 13.5 Timer Ai mode register in timer mode

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 99 13. Timer ApuorG08/C61M Item Specification Count source •Two-phase pulse signals input to TAiIN or TAiOUT pins (i=2 to 4) Count operation •Up count or down count can be selected by two-phase pulse signal

When the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (Note) Divide ratio •1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingTimer overflows or underflows TAiIN pin function Two-phase pulse input (Set the corresponding function select registers A to I/ O port, and port direction register to "0") TAiOUT pin function Two-phase pulse input (Set the corresponding function select registers A to I/ O port, and port direction register to "0") Read from timer Count value can be read out by reading timer A2, A3, or A4 register Write to timer • When not counting Value written to timer Ai register is written to both reload register and counter
When counting Value written to timer Ai register is written to only reload register (Transferred to counter at next reload time) Select function (Note 2)•Normal processing operation (TimerA2 and timer A3) The timer counts up rising edges or counts down falling edges on the TAiIN pin when input signal on the TAiOUT pin is “H ”
Multiply-by-4 processing operation (TimerA3 and timer A4) If the phase relationship is such that the TAiIN pin goes “H ” when the input signal on the TAiOUT pin is “H ”, the timer counts up rising and falling edges on the TAiOUT and TAiIN pins. If the phase relationship is such that the TAiIN pin goes “L” when the input signal on the TAiOUT pin is “H ”, the timer counts down rising and falling edges on the TAiOUT and TAiIN pins. Table 13.3 Timer specifications in event counter mode TAiOUT Up count Up count Up count Down count Down count Down count TAiIN (i=2,3) TAiOUT TAiIN (i=3,4) Count up all edges Count up all edges Count down all edges Count down all edges (when processing two-phase pulse signal with timers A2, A3, and A4) Note 1: This does not apply when the free-run function is selected. Note 2: Timer A3 is selectable. Timer A2 is fixed to normal processing operation and timer A4 is fixed to multiply-by-4 operation.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 100 13. Timer ApuorG08/C61M Note 1: Set the corresponding function select register A to I/O port. Note 2: This bit is valid for timer A3 mode register. Timer A2 is fixed to normal processing operation and timer A4 is fixed to multiply-by-4 processing operation. Note 3: When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 0344 16) is set to “1”. Also, always be sure to set the event/trigger select bit (addresses 034316) to “00”. Timer Ai mode register (When using two-phase pulse signal processing) Symbol Address When reset TAiMR(i=2 to 4) 035816 to 035A16 00000X002 b7 b6 b5 b4 b3 b2 b1 b0 Operation mode select bit0 1 : Event counter mode b1 b0 TMOD1 TMOD0 MR0 0 (Set to “0” when using two-phase pulse signal processing) MR2 MR1 MR3 0 (Set to “0” when using two-phase pulse signal processing) TCK1 TCK0 010 1 (Set to “1” when using two-phase pulse signal processing) Bit symbol Bit name Function WR Count operation type select bit Two-phase pulse processing operation select bit (Note 2)(Note 3) 0 : Reload type 1 : Free-run type 0 : Normal processing operation 1 : Multiply-by-4 processing operation /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines This bit is invalid in M16C/80 series. Port output control is set by the function select registers A and B. (Note 1)– – Figure 13.7 Timer Ai mode register in event counter mode

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 101 13. Timer ApuorG08/C61M

Counter Resetting by Two-Phase Pulse Signal Processing This function resets the timer counter to “0” when the Z-phase (counter reset) is input during two- phase pulse signal processing. This function can only be used in timer A3 event counter mode, two-phase pulse signal processing, free-run type, and multiply-by-4 processing. The Z phase is input to the INT2 pin. When the Z-phase input enable bit (bit 5 at address 0342 16) is set to “1”, the counter can be reset by Z-phase input. For the counter to be reset to “0” by Z-phase input, you must first write “000016” to the timer A3 register (address 034D16 and 034C16). The Z-phase is input when the INT2 input edge is detected. The edge polarity is selected by the INT2 polarity switch bit (bit 4 at address 009C 16). The Z-phase must have a pulse width greater than 1 cycle of the timer A3 count source. Figure 13.8 shows the relationship between the two-phase pulse (A phase and B phase) and the Z phase. The counter is reset at the count source following Z-phase input. Figure 13.9 shows the timing at which the counter is reset to “0”. The pulse must be wider than this width. Note: When the rising edge of INT2 is selected TA3 OUT (A phase) Count source TA3 IN (B phase) INT2 (Note) (Z phase) Figure 13.8 The relationship between the two-phase pulse (A phase and B phase) and the Z phase

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 102 13. Timer ApuorG08/C61M Figure 13.9 The counter reset timing Note that timer A3 interrupt requests occur successively two times when timer A3 underflow and INT2 input reload are happened at the same timing. Do not use timer A3 interrupt request when this function is used. TA3 OUT (A phase) Count source TA3 IN (B phase) Becoming "0" at this timing. Count value mm + 1 1 2 3 4 5 INT2 (Z phase) (Note) Note: When the rising edge of INT2 is selected

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 103 13. Timer ApuorG08/C61M Item Specification Count source f 1, f8, f32, fC32 Count operation •The timer counts down

When the count reaches 000016, the timer stops counting after reloading a new count
If a trigger occurs when counting, the timer reloads a new count and restarts counting Divide ratio 1/n n : Set value Count start condition • An external trigger is input
The timer overflows
The one-shot start flag is set (= 1) Count stop condition • A new count is reloaded after the count has reached 000016
The count start flag is reset (= 0) Interrupt request generation timingThe count reaches 000016 TAiIN pin function Programmable I/O port or trigger input TAiOUT pin function Programmable I/O port or pulse output (Setting by the corresponding function select registers A and B) Read from timer When timer Ai register is read, it indicates an indeterminate value Write to timer • When not counting Value written to timer Ai register is written to both reload register and counter
When counting Value written to timer Ai register is written to only reload register (Transferred to counter at next reload time) Table 13.4 Timer specifications in one-shot timer mode Figure 13.10 Timer Ai mode register in one-shot timer mode (3) One-shot timer mode In this mode, the timer operates only once. (See Table 13.4) When a trigger occurs, the timer starts up and continues operating for a given period. Figure 13.10 shows the timer Ai mode register in one-shot timer mode. Bit name Timer Ai mode register Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 Operation mode select bit1 0 : One-shot timer mode b1 b0 TMOD1 TMOD0 MR0 MR2 MR1 MR3 0 (Set to “0” in one-shot timer mode) 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 TCK1 TCK0 Count source select bit 100 0 : One-shot start flag is valid 1 : Selected by event/trigger select bit Trigger select bit External trigger select bit (Note 1) 0 : Falling edge of TAiIN pin's input signal (Note 2) 1 : Rising edge of TAiIN pin's input signal (Note 2) Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses 034216 and 034316). If timer overflow is selected, this bit can be “1” or “0”. Note 2: Set the corresponding port function select register to I/O port, and port direction register to “0”. WR /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Symbol Address When reset TAiMR(i=0 to 4) 035616 to 035A16 00000X002 This bit is invalid in M16C/80 series. Port output control is set by the function select registers A and B. – –

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 104 13. Timer ApuorG08/C61M Item Specification Count source f 1, f8, f32, fC32 Count operation •The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)

The timer reloads a new count at a rising edge of PWM pulse and continues counting
The timer is not affected by a trigger that occurs when counting 16-bit PWM •High level width n / fi n : Set value
Cycle time (2 16-1) / fi fixed 8-bit PWM •High level width n (m+1) / fi n : values set to timer Ai register’s high-order address
Cycle time (28-1) (m+1) / fi m:values set to timer Ai register’s low-order address Count start condition •External trigger is input
The timer overflows
The count start flag is set (= 1) Count stop condition •The count start flag is reset (= 0) Interrupt request generation timingPWM pulse goes “L” TAiIN pin function Programmable I/O port or trigger input TAiOUT pin function Pulse output (TAiOUT output is selected by the corresponding function select registers A and B) Read from timer When timer Ai register is read, it indicates an indeterminate value Write to timer • When not counting Value written to timer Ai register is written to both reload register and counter
When counting Value written to timer Ai register is written to only reload register (Transferred to counter at next reload time) (4) Pulse width modulation (PWM) mode In this mode, the timer outputs pulses of a given width in succession. (See Table 13.5) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 13.11 shows the timer Ai mode register in pulse width modulation mode. Figure 13.12 shows the example of how a 16-bit pulse width modulator operates. Figure 13.13 shows the example of how an 8-bit pulse width modulator operates. Figure 13.11 Timer Ai mode register in pulse width modulation mode Table 13.5 Timer specifications in pulse width modulation mode Bit name Timer Ai mode register FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 Operation mode select bit 1 1 : Pulse width modulaten (PWM) mode b1 b0 TMOD1 TMOD0 MR0 MR2 MR1 MR3 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 TCK1 TCK0 Count source select bit WR 16/8-bit PWM mode select bit 0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator Trigger select bit External trigger select bit (Note 1) 0: Falling edge of TAiIN pin's input signal (Note 2) 1: Rising edge of TAiIN pin's input signal (Note 2) 0: Count start flag is valid 1: Selected by event/trigger select bit Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses 034216 and 034316). If timer overflow is selected, this bit can be “1” or “0”. Note 2: Set the corresponding function select register A to I/O port, and port direction register to “0”. /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Symbol Address When reset TAiMR(i=0 to 4) 035616 to 035A16 00000X002 This bit is invalid in M16C/80 series. Port output control is set by the function select registers A and B.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 107 14. Timer BpuorG08/C61M Symbol Address When reset TABSR 0340 16 0016 Count start flag Bit nameBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Timer B2 count start flag Timer B1 count start flag Timer B0 count start flag Timer A4 count start flag Timer A3 count start flag Timer A2 count start flag Timer A1 count start flag Timer A0 count start flag0 : Stops counting 1 : Starts counting TB2S TB1S TB0S TA4S TA3S TA2S TA1S TA0S Function /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Symbol Address When reset CPSRF 0341 16 0XXXXXXX 2 Clock prescaler reset flag Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Clock prescaler reset flag0 : No effect 1 : Prescaler is reset (When read, the value is “0”) CPSR /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Symbol Address When reset TB0 0351 16, 035016 Indeterminate TB1 0353 16, 035216 Indeterminate TB2 0355 16, 035416 Indeterminate TB3 0311 16, 031016 Indeterminate TB4 0313 16, 031216 Indeterminate TB5 0315 16, 031416 Indeterminate b7 b0 b7 b0 (b15) (b8) Timer Bi register (Note) WR

Pulse period / pulse width measurement mode Measures a pulse period or width
Timer mode 0000 16 to FFFF16 Counts the timer's period Function Values that can be set
Event counter mode 0000 16 to FFFF16 Counts external pulses input or a timer overflow Note: Read and write data in 16-bit units. /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines Symbol Address When reset TBSR 0300 16 000XXXXX 2 Timer B3, 4, 5 count start flag Bit nameBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Timer B5 count start flag Timer B4 count start flag Timer B3 count start flag0 : Stops counting 1 : Starts counting TB5S TB4S TB3S Nothing is assigned. When write, set "0". When read, the value of these bits is indeterminate. Function /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Nothing is assigned. When write, set "0". When read, the value of these bits is indeterminate. Figure 14.3 Timer B-related registers (2)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 108 14. Timer BpuorG08/C61M Item Specification Count source f1, f8, f32, fC32 Count operation •Counts down

When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingThe timer underflows TBiIN pin function Programmable I/O port Read from timer Count value is read out by reading timer Bi register Write to timer • When not counting Value written to timer Bi register is written to both reload register and counter
When counting Value written to timer Bi register is written to only reload register (Transferred to counter at next reload time) (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 14.1) Figure 14.4 shows the timer Bi mode register in timer mode. Table 14.1 Timer specifications in timer mode Note 1: Timer B0, timer B3. Note 2: Timer B1, timer B2, timer B4, timer B5. Timer Bi mode register Symbol Address When reset TBiMR(i = 0 to 5) 035B 16 to 035D16 00XX0000 2 031B16 to 031D16 00XX0000 2 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Operation mode select bit0 0 : Timer mode b1 b0 TMOD1 TMOD0 MR0 Invalid in timer mode Can be “0” or “1” MR2 MR1 MR3 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 TCK1 TCK0 Count source select bit Invalid in timer mode. When write, set "0". When read in timer mode, its content is indeterminate. 0 (Set to “0” in timer mode ; i = 0, 3) Nothing is assiigned (i = 1, 2, 4, 5). When write, set "0". When read, its content is indeterminate. (Note 1) (Note 2) b7 b6 /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Figure 14.4 Timer Bi mode register in timer mode

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 109 14. Timer BpuorG08/C61M Item Specification Count source •External signals input to TBiIN pin Effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software

TBi overflows or underflows Count operation •Counts down
When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingThe timer underflows TBiIN pin function Programable I/O port or Count source input (Set the corresponding function select register A to I/O port.) Read from timer Count value can be read out by reading timer Bi register Write to timer • When not counting Value written to timer Bi register is written to both reload register and counter
When counting Value written to timer Bi register is written to only reload register (Transferred to counter at next reload time) (2) Event counter mode In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 14.2) Figure 14.5 shows the timer Bi mode register in event counter mode. Table 14.2 Timer specifications in event counter mode Figure 14.5 Timer Bi mode register in event counter mode Timer Bi mode register Symbol Address When reset TBiMR(i = 0 to 5) 035B16 to 035D16 00XX0000 2 031B16 to 031D16 00XX0000 2 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Operation mode select bit 0 1 : Event counter mode b1 b0 TMOD1 TMOD0 MR0 Count polarity select bit (Note 1) MR2 MR1 MR3 Invalid in event counter mode. When write, set "0". When read in event counter mode, its content is indeterminate. TCK1 TCK0 0 0 : Counts external signal's falling edges 0 1 : Counts external signal's rising edges 1 0 : Counts external signal's falling and rising edges 1 1 : Must not be set b3 b2 Nothing is assigned (i = 1, 2, 4, 5). When write, set "0". When read, its content is indeterminate. Note 1: Valid only when input from the TBiIN pin is selected as the event clock. If timer's overflow is selected, this bit can be “0” or “1”. Note 2: Timer B0, timer B3. Note 3: Timer B1, timer B2, timer B4, timer B5. Note 4: Set the corresponding function select register A to I/O port, and port direction register to “0”. Invalid in event counter mode. Can be “0” or “1”. Event clock select 0 : Input from TBiIN pin (Note 4) 1 : TBj overflow (j = i – 1; however, j = 2 when i = 0, j = 5 when i = 3) 0 (Set to “0” in event counter mode; i = 0, 3) (Note 2) (Note 3) /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 112 15. Three-phase motor control timers’ functionspuorG08/C61M 15. Three-phase motor control timers’ functions Use of more than one built-in timer A and timer B provides the means of outputting three-phase motor driving waveforms. Figures 15.1 through 15.3 show registers related to timers for three-phase motor control. No value other than “0” can be written. Selecting three-phase PWM output mode causes the dead time timer, the U, V, W phase output control circuits, and the timer B2 interrupt occurrences frequency set circuit works. For U, U, V, V, W and W output from P8 0, P81, and P72 through P75, setting of function select registers A, B and C is required. In triangular wave modulation mode: The dead time timer starts in synchronization with the falling edge of timer Ai output. The data transfer from the three-phase buffer register to the three-phase output shift register is made only once in synchronization with the transfer trigger signal after writing to the three-phase output buffer register. In sawtooth wave modulation mode: The dead time timer starts in synchronization with the falling edge of timer A output and with the transfer trigger signal. The data transfer from the three-phase output buffer register to the three- phase output shift register is made with respect to every transfer trigger. Set bit 1 of this register to "1" after setting timer B2 interrupt frequency set counter. Rewrite the INV00 to INV02 and INV06 bits when the timers A1,A2,A4 and B stop. Three-phase PWM control register 0 (Note 5) Symbol Address When reset INVC0 0308 16 0016 b7 b6 b5 b4 b3 b2 b1 b0 Effective interrupt output polarity select bitINV00 Bit symbol Bit name Description RW INV01 Effective interrupt output specification bit INV02 Mode select bit (Note 2) INV04 Positive and negative phases concurrent L output disable function enable bit INV0

7 Software trigger bit

INV06 Modulation mode select bit (Note 3) INV05 Positive and negative phases concurrent L output detect flag INV0

3 Output control bit

0: A timer B2 interrupt occurs when the timer A1 reload control signal is “0”. 1: A timer B2 interrupt occurs when the timer A1 reload control signal is “1”. Effective only in three-phase mode 1 0: Not specified. 1: Selected by the effective interrupt output polarity selection bit. Effective only in three-phase mode 1 0: Normal mode 1: Three-phase PWM output mode 0: Output disabled 1: Output enabled 0: Feature disabled 1: Feature enabled 0: Not detected yet 1: Already detected 0: Triangular wave modulation mode 1: Sawtooth wave modulation mode 1: Trigger generated The value, when read, is “0”. (Note 1) Three-phase PWM control register 1 Symbol Address When reset INVC1 0309 16 XXX0X000 2 Bit name DescriptionBit symbol WR INV10 INV11 INV12 Timer Ai start trigger signal select bit Timer A1-1, A2-1, A4-1 control bit Dead time timer count source select bit 0: Timer B2 overflow signal 1: Timer B2 overflow signal, signal for writing to timer B2 0: Three-phase mode 0 1: Three-phase mode 1 0 : f1 1 : f1/2 b7 b6 b5 b4 b3 b2 b1 b0 Noting is assigned. When write, set "0". When read, their contents are "0". Note 1: Note 2: Note 3: Note 4: Note 5: Note : INV13 is valid when INV06 = 0 and INV11 = 1. INV13 INV14 Carrier wave detect flag (Note) Output porality control bit 0: Rising edge of triangular waveform 1: Falling edge of triangular waveform 0 : Low active 1 : High active X (Note 4) Figure 15.1 Registers related to timers for three-phase motor control

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 113 15. Three-phase motor control timers’ functionspuorG08/C61M Three-phase output buffer register 0 Symbol Address When reset IDB0 030A 16 3F16 Bit name FunctionBit Symbol WR b7 b6 b5 b4 b3 b2 b1 b0 Nothing is assigned. When write, set "0". When read, its content is "0". DU0 DUB0 DV0 DW0 DVB0 DWB0 U phase output buffer 0 Setting in U phase output buffer 0 V phase output buffer 0 W phase output buffer 0 U phase output buffer 0 V phase output buffer 0 W phase output buffer 0 Setting in V phase output buffer 0 Setting in W phase output buffer 0 Setting in W phase output buffer 0 Setting in V phase output buffer 0 Setting in U phase output buffer 0 Three-phase output buffer register 1 Symbol Address When reset IDB1 030B 16 3F16 Bit name FunctionBit Symbol WR b7 b6 b5 b4 b3 b2 b1 b0 Nothing is assigned. When write, set "0". When read, its content is "0". DU1 DUB1 DV1 DW1 DVB1 DWB1 U phase output buffer 1 Setting in U phase output buffer 1 V phase output buffer 1 W phase output buffer 1 U phase output buffer 1 V phase output buffer 1 W phase output buffer 1 Setting in V phase output buffer 1 Setting in W phase output buffer 1 Setting in W phase output buffer 1 Setting in V phase output buffer 1 Setting in U phase output buffer 1 Dead time timer (Note) Symbol Address When reset DTT 030C 16 Indeterminate Function Values that can be set WR b7 b0 Set dead time timer 1 to 255 Timer B2 interrupt occurrences frequency set counter (Note 1 to 4) Symbol Address When reset ICTB2 030D 16 Indeterminate Function Values that can be set WR b3 b0 Set occurrence frequency of timer B2 interrupt request 1 to 15 Note: When executing read instruction of this register, the contents of three-phase shift register is read out. Note: When executing read instruction of this register, the contents of three-phase shift register is read out. Note 1: When the effective interrupt output specification bit (INV01: bit 1 at 030816) is set to "1" and three-phase motor control timer is operating, do not rewrite to this register. Note 2: Do not write to this register at the timing of timer B2 overflow. Note 3: Use MOV instruction to write to this register. Note 4: Setting of this register is valid only when bit 2(INV02) of three-phase PWM control register 0 is set to "1". Note: Use MOV instruction to write to this register. Note Note Note Note Note Note Note Note Note Note Note Note Figure 15.2 Registers related to timers for three-phase motor control

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 114 15. Three-phase motor control timers’ functionspuorG08/C61M Figure 15.3 Registers related to timers for three-phase motor control Symbol Address When reset TA11 0303 16,030216 Indeterminate TA21 0305 16,030416 Indeterminate TA41 0307 16,030616 Indeterminate b7 b0 b7 b0 (b15) (b8) WR Counts an internal count source 0000 16 to FFFF16 Function Values that can be set Timer Ai-1 register (Note 1 to 2) Note 1: Read and write data in 16-bit units. Note 2: Do not write to these register at the timing of timer B2 overflow. /LiteDiagLines/LiteDiagLines Symbol Address When reset TA1 0349 16,034816 Indeterminate TA2 034B 16,034A16 Indeterminate TA4 034F 16,034E16 Indeterminate TB2 0355 16,035416 Indeterminate b7 b0 b7 b0(b15) (b8) WR

Timer mode 0000 16 to FFFF16 Counts an internal count source Function Values that can be set
One-shot timer mode 0000 16 to FFFF16 Counts a one shot width Note 1: Read and write data in 16-bit units. Note 2: When the timer Ai register is set to "000016", the counter does not operate and a timer Ai interrupt does not occur. Note 3: When writing to this register, use MOV instruction. Timer Ai register (Note1) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines TA1TGL Symbol Address When reset TRGSR 0343 16 0016 Timer A1 event/trigger select bit 0 0 : Input on TA1IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected Trigger select register Bit name FunctionBit symbol 0 0 : Input on TA2IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA1 overflow is selected 1 1 : TA3 overflow is selected 0 0 : Input on TA3IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA2 overflow is selected 1 1 : TA4 overflow is selected 0 0 : Input on TA4IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA3 overflow is selected 1 1 : TA0 overflow is selected Timer A2 event/trigger select bit Timer A3 event/trigger select bit Timer A4 event/trigger select bit WR TA1TGH TA2TGL TA2TGH TA3TGL TA3TGH TA4TGL TA4TGH b1 b0 b3 b2 b5 b4 b7 b6 Note: Set the corresponding port function select register to I/O port, and port direction register to "0". /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines b7 b6 b5 b4 b3 b2 b1 Symbol Address When reset TABSR 0340 16 0016 Count start flag Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Timer B2 count start flag Timer B1 count start flag Timer B0 count start flag Timer A4 count start flag Timer A3 count start flag Timer A2 count start flag Timer A1 count start flag Timer A0 count start flag0 : Stops counting 1 : Starts counting TB2S TB1S TB0S TA4S TA3S TA2S TA1S TA0S /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines (Note 2, 3)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 115 15. Three-phase motor control timers’ functionspuorG08/C61M Bit name Timer Ai mode register Symbol Address When reset TA1MR 0357 16 00000X00 2 TA2MR 0358 16 00000X002 TA3MR 035A 16 00000X002 Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 Operation mode select bit 1 0 : One-shot timer mode b1 b0 TMOD1 TMOD0 MR0 MR2 MR1 MR3 0 (Set to “0” in one-shot timer mode) 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 TCK1 TCK0 Count source select bit 100 1 : Selected by event/trigger select register Trigger select bit External trigger select bit Invalid in three-phase PWM output mode. WR /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Timer B2 mode register Symbol Address When reset TB2MR 035D 16 00XX0000 2 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Operation mode select bit0 0 : Timer mode b1 b0 TMOD1 TMOD0 MR0 Invalid in timer mode Can be “0” or “1” MR2 MR1 MR3 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 TCK1 TCK0 Count source select bit Invalid in timer mode. When write, set "0". When read in timer mode, its content is indeterminate. 0 (Set to “0” in timer mode) b7 b6 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines This bit is invalid in M16C/80 series. Port output control is set by the function select registers A and B.–– Figure 15.4 Timer mode registers in three-phase PWM output mode Three-phase motor driving waveform output mode (three-phase PWM output mode) Setting “1” in the mode select bit (bit 2 at 030816) shown in Figure 15.1 causes three-phase PWM output mode that uses four timers A1, A2, A4, and B2 to be selected. As shown in Figure 15.4, set timers A1, A2, and A4 in one-shot timer mode, set the trigger in timer B2, and set timer B2 in timer mode using the respective timer mode registers.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 116 15. Three-phase motor control timers’ functionspuorG08/C61M Figure 15.5 shows the block diagram for three-phase waveform mode. In “L” active output polarity in three-phase waveform mode, the positive-phase waveforms (U phase, V phase, and W phase) and negative waveforms (U phase, V phase, and W phase), six waveforms in total, are output from P80, P81, P72, P73, P74, and P75 as active on the “L” level. Of the timers used in this mode, timer A4 controls the U phase and U phase, timer A1 controls the V phase and V phase, and timer A2 controls the W phase and ___ W phase respectively; timer B2 controls the periods of one-shot pulse output from timers A4, A1, and A2. In outputting a waveform, dead time can be set so as to cause the “L” level of the positive waveform ___ output (U phase, V phase, and W phase) not to lap over the “L” level of the negative waveform output (U phase, V phase, and W phase). To set short circuit time, use three 8-bit timers sharing the reload register for setting dead time. A value from 1 through 255 can be set as the count of the timer for setting dead time. The timer for setting dead time works as a one-shot timer. If a value is written to the dead timer (030C 16), the value is written to the reload register shared by the three timers for setting dead time. Any of the timers for setting dead time takes the value of the reload register into its counter, if a start trigger comes from its corresponding timer, and performs a down count in line with the clock source selected by the dead time timer count source select bit (bit 2 at 0309 16). The timer can receive another trigger again before the workings due to the previous trigger are completed. In this instance, the timer performs a down count from the reload register’s content after its transfer, provoked by the trigger, to the timer for setting dead time. Since the timer for setting dead time works as a one-shot timer, it starts outputting pulses if a trigger comes; it stops outputting pulses as soon as its content becomes 00 16, and waits for the next trigger to come. The positive waveforms (U phase, V phase, and W phase) and the negative waveforms (U phase, V ___ phase, and W phase) in three-phase waveform mode are output from respective ports by means of setting “1” in the output control bit (bit 3 at 0308 16). Setting “0” in this bit causes the ports to be the high- impedance state. This bit can be set to “0” not only by use of the applicable instruction, but by entering a falling edge in the NMI terminal or by resetting. Also, if “1” is set in the positive and negative phases ___ concurrent L output disable function enable bit (bit 4 at 030816) causes one of the pairs of U phase and U phase, V phase and V phase, and W phase and W phase concurrently go to “L”, as a result, the output control bit becomes the high-impedance state.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 117 15. Three-phase motor control timers’ functionspuorG08/C61M Timer B2(Timer mode) Overflow Interrupt occurrence frequency set counter Interrupt request bit U(P8 U(P8 V(P7 V(P7 W(P7 W(P7 NMI RESET RD D T Q D T Q D T Q D T Q For short circuit prevention D T Q D T Q Q INV0 INV0 Diagram for switching to P8 0, P8 1 and P7 2 - P7 5 is not shown. INV0 Timer A4 counter (One-shot timer mode) (One-shot timer mode) (One-shot timer mode) Trigger Timer A4 Reload Timer A4-1 Timer A1 counter TriggerTimer A1 Reload Timer A1-1 Timer A2 counter Trigger Timer A2 Reload Timer A2-1INV0 T Q INV1 Dead time timer setting (8) INV0 1 0 INV0 INV1 DU0 DU1 T DQ T DQ DUB0 DUB1 T DQ T DQ U phase output control circuit U phase output signalU phase output signal V phase output control circuit To be set to “0” when timer A4 stops T Q INV1 To be set to “0” when timer A1 stops T Q INV1 To be set to “0” when timer A2 stops W phase output control circuit V phase output signal W phase output signal V phase output signal W phase output signal Signal to be written to B2 Trigger signal for timer Ai start Trigger signal for transfer INV1 Circuit foriInterrupt occurrence frequency set counter Bit 0 at 030B Bit 0 at 030A Three-phase output shift register (U phase) /LiteDiagLines 0 1 n = 1 to 15 Reload register n = 1 to 255 Dead time timer setting (8) n = 1 to 255 Dead time timer setting (8) n = 1 to 255 n = 1 to 255 Trigger INV0 Trigger TriggerTrigger TriggerTrigger INV0 INV0 INV1 INV1 Figure 15.5 Block diagram for three-phase waveform mode

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 118 15. Three-phase motor control timers’ functionspuorG08/C61M Triangular wave modulation To generate a PWM waveform of triangular wave modulation, set “0” in the modulation mode select bit (bit 6 at 030816). Also, set “1” in the timers A4-1, A1-1, A2-1 control bit (bit 1 at 030916). In this mode, each of timers A4, A1, and A2 has two timer registers, and alternately reloads the timer register’s content to the counter every time timer B2 counter’s content becomes 000016. If “0” is set to the effective interrupt output specification bit (bit 1 at 030816), the frequency of interrupt requests that occur every time the timer B2 counter’s value becomes 000016 can be set by use of the timer B2 counter (030D16) for setting the frequency of interrupt occurrences. The frequency of occurrences is given by (setting; setting π 0). Setting “1” in the effective interrupt output specification bit (bit 1 at 030816) provides the means to choose which value of the timer A1 reload control signal to use, “0” or “1”, to cause timer B2’s interrupt request to occur. To make this selection, use the effective interrupt output polarity selection bit (bit 0 at 030816). An example of U phase waveform is shown in Figure 15.6, and the description of waveform output work- ings is given below. Set “1” in DU0 (bit 0 at 030A 16). And set “0” in DUB0 (bit 1 at 030A16). In addition, set “0” in DU1 (bit 0 at 030B16) and set “1” in DUB1 (bit 1 at 030B16). Also, set “0” in the effective interrupt output specification bit (bit 1 at 030816) to set a value in the timer B2 interrupt occurrence frequency set counter. By this setting, a timer B2 interrupt occurs when the timer B2 counter’s content becomes 000016 as many as (setting) times. Furthermore, set “1” in the effective interrupt output specification bit (bit 1 at 030816), set in the effective interrupt polarity select bit (bit 0 at 030816) and set "1" in the interrupt occur- rence frequency set counter (030D16). These settings cause a timer B2 interrupt to occur every other interval when the U phase output goes to “H ”. When the timer B2 counter’s content becomes 000016, timer A4 starts outputting one-shot pulses. In this instance, the content of DU1 (bit 0 at 030B16) and that of DU0 (bit 0 at 030A16) are set in the three-phase output shift register (U phase), the content of DUB1 (bit 1 at 030B16) and that of DUB0 (bit 1 at 030A16) ___ are set in the three-phase shift register (U phase). After triangular wave modulation mode is selected, however, no setting is made in the shift register even though the timer B2 counter’s content becomes 0000 16. ___ The value of DU0 and that of DUB0 are output to the U terminal (P80) and to the U terminal (P81) respectively. When the timer A4 counter counts the value written to timer A4 (034F16, 034E16) and when timer A4 finishes outputting one-shot pulses, the three-phase shift register’s content is shifted one posi- ___ tion, and the value of DU1 and that of DUB1 are output to the U phase output signal and to U phase output signal respectively. At this time, one-shot pulses are output from the timer for setting dead time used for ___ setting the time over which the “L” level of the U phase waveform doesn’t lap over the “L” level of the U phase waveform, which has the opposite phase of the former. The U phase waveform output that started from the “H ” level keeps its level until the timer for setting dead time finishes outputting one-shot pulses even though the three-phase output shift register’s content changes from “1” to “0” by the effect of the one-shot pulses. When the timer for setting dead time finishes outputting one-shot pulses, "0" already shifted in the three-phase shift register goes effective, and the U phase waveform changes to the "L" level. When the timer B2 counter’s content becomes 0000 16, the timer A4 counter starts counting the value written to timer A4-1 (030716, 030616), and starts outputting one-shot pulses. When timer A4 fin- ishes outputting one-shot pulses, the three-phase shift register’s content is shifted one position, but if the three-phase output shift register’s content changes from “0” to “1” as a result of the shift, the output level changes from “L” to “H ” without waiting for the timer for setting dead time to finish outputting one-shot pulses. A U phase waveform is generated by these workings repeatedly. With the exception that the three-phase output shift register on the U phase side is used, the workings in generating a U phase waveform, which has the opposite phase of the U phase waveform, are the same as in generating a U

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 119 15. Three-phase motor control timers’ functionspuorG08/C61M Timer A4 output Trigger signal for timer Ai start (timer B2 overflow signal) Timer B2 U phase A carrier wave of triangular waveform Carrier wave Signal wave U phase output signal Control signal for timer A4 reload U phase U phase output signal mn n m p o Note 1: When INV14="0" (output wave Low active) Note 2: When INV14="1" (output wave High active) Note 3: Set to trian gular wave modulation mode and to three-phase mode 1. m INV13(Triangular wave modulation detect flag) (Note 1) (Note 2) (Note 3) U phase U phase Dead time Dead time Timber B2 interrupt occurres Rewriting timer A4 and timer A4-1. Possible to set the number of overflows to generate an interrupt by use of the interrupt occurrences frequency set circuit The three-phase shift register shifts in synchronization with the falling edge of the A4 output. Figure 15.6 Timing chart of operation (1) phase waveform. In this way, a waveform can be picked up from the applicable terminal in a manner in which the "L" level of the U phase waveform doesn’t lap over that of the U phase waveform, which has the opposite phase of the U phase waveform. The width of the “L” level too can be adjusted by varying the values of timer B2, timer A4, and timer A4-1. In dealing with the V and W phases, and V and W phases, the latter are of opposite phase of the former, have the corresponding timers work similarly to dealing with ___ the U and U phases to generate an intended waveform.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 120 15. Three-phase motor control timers’ functionspuorG08/C61M Figure 15.7 Timing chart of operation (2) Timer A4 output Trigger signal for timer Ai start (timer B2 overflow signal) Timer B2 U phase Dead time A carrier wave of triangular waveform Carrier wave Signal wave Rewriting timer A4 every timer B2 interrupt occurres. U phase output signal m nn mp o Note: Set to triangular wave modulation mode and to three-phase mode 1. Control signal for timer A4 reload m U phase U phase output signal Timer B2 interrupt occurres. Rewriting three-phase buffer register. Assigning certain values to DU0 (bit 0 at 030A16) and DUB0 (bit 1 at 030A16), and to DU1 (bit 0 at 030B16) and DUB1 (bit 1 at 030B16) allows you to output the waveforms as shown in Figure 15.7, that is, to output the U phase alone, to fix U phase to “H ”, to fix the U phase to “H,” or to output the U phase alone.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 121 15. Three-phase motor control timers’ functionspuorG08/C61M Sawtooth modulation To generate a PWM waveform of sawtooth wave modulation, set “1” in the modulation mode select bit (bit 6 at 030816). Also, set “0” in the timers A4, A1, and A2-1 control bit (bit 1 at 030916). In this mode, the timer registers of timers A4, A1, and of A2 comprise conventional timers A4, A1, and A2 alone, and reload the corresponding timer register’s content to the counter every time the timer B2 counter’s content be- comes 0000 16. The effective interrupt output specification bit (bit 1 at 030816) and the effective interrupt output polarity select bit (bit 0 at 030816) go nullified. An example of U phase waveform is shown in Figure 15.8, and the description of waveform output work- ings is given below. Set “1” in DU0 (bit 0 at 030A 16), and set “0” in DUB0 (bit 1 at 030A16). In addition, set “0” in DU1 (bit 0 at 030B16) and set “1” in DUB1 (bit 1 at 030B16). When the timber B2 counter’s content becomes 000016, timer B2 generates an interrupt, and timer A4 starts outputting one-shot pulses at the same time. In this instance, the contents of the three-phase buffer registers DU1 and DU0 are set in the three-phase output shift register (U phase), and the contents of DUB1 and DUB0 are set in the three-phase output register (U phase). After this, the three-phase buffer register’s content is set in the three-phase shift register every time the timer B2 counter’s content be- comes 0000 16. ___ The value of DU0 and that of DUB0 are output to the U terminal (P80) and to the U terminal (P81) respectively. When the timer A4 counter counts the value written to timer A4 (034F16, 034E16) and when timer A4 finishes outputting one-shot pulses, the three-phase output shift register’s content is shifted one ___ position, and the value of DU1 and that of DUB1 are output to the U phase output signal and to the U output signal respectively. At this time, one-shot pulses are output from the timer for setting dead time used for setting the time over which the “L” level of the U phase waveform doesn’t lap over the “L” level of ___ the U phase waveform, which has the opposite phase of the former. The U phase waveform output that started from the “H ” level keeps its level until the timer for setting dead time finishes outputting one-shot pulses even though the three-phase output shift register’s content changes from “1” to “0 ”by the effect of the one-shot pulses. When the timer for setting dead time finishes outputting one-shot pulses, 0 already shifted in the three-phase shift register goes effective, and the U phase waveform changes to the “L” level. When the timer B2 counter’s content becomes 0000 16, the contents of the three-phase buffer registers DU1 and DU0 are set in the three-phase shift register (U phase), and the contents of DUB1 and ___ DUB0 are set in the three-phase shift register (U phase) again. A U phase waveform is generated by these workings repeatedly. With the exception that the three-phase output shift register on the U phase side is used, the workings in generating a U phase waveform, which has the opposite phase of the U phase waveform, are the same as in generating a U phase waveform. In this way, a waveform can be picked up from the applicable terminal in a manner in which the “L” level of the U phase waveform doesn’t lap over that of the U phase waveform, which has the opposite phase of the U phase waveform. The width of the “L” level too can be adjusted by varying the values of timer B2 and timer A4. In dealing with the V and W phases, and V and W phases, the latter are of opposite phase ___ of the former, have the corresponding timers work similarly to dealing with the U and U phases to gener- ate an intended waveform.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 122 15. Three-phase motor control timers’ functionspuorG08/C61M Timer B2 Timer A4 output U phase U phase Dead time Carrier wave Signal wave A carrier wave of sawtooth waveform m n o p Note: Set to sawtooth modulation mode and to three-phase mode 0. Interrupt occurres. Rewriting the value of timer A4. U phase output signal U phase output signal The three-phase shift register shifts in synchronization with the falling edge of timer A4. Data transfer is made from the three- phase buffer register to the three- phase shift register in step with the timing of the timer B overflow. Trigger signal for timer Ai start (timer B2 overflow signal) Figure 15.8 Timing chart of operation (3)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 123 15. Three-phase motor control timers’ functionspuorG08/C61M Timer B2 Timer A4 output U phase U phase Dead time Carrier wave Signal wave A carrier wave of sawtooth waveform mn p Note: Set to sawtooth modulation mode and to three-phase mode 0. U phase output signal U phase output signal The three-phase shift register shifts in synchronization with the falling edge of timer A4. Trigger signal for timer Ai start (timer B2 overflow signal) Interrupt occurres. Rewriting the value of timer A4. Rewriting three-phase output buffer register Data transfer is made from the three- phase buffer register to the three- phase shift register in step with the timing of the timer B overflow. Interrupt occurres. Rewriting the value of timer A4. Figure 15.9 Timing chart of operation (4) ___ Setting “1” both in DUB0 and in DUB1 provides a means to output the U phase alone and to fix the U phase output to “H ” as shown in Figure 15.9.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 124 16. Serial I/OpuorG08/C61M 16. Serial I/O Serial I/O is configured as five channels: UART0 to UART4. UART0 to 4 UART0 to UART4 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. diagram of the transmit/receive unit. UARTi has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 0360 16, 036816, 033816, 032816 and 02F816) determine whether UARTi is used as a clock synchronous serial I/O or as a UART. Although a few functions are different, UART0 to UART4 have almost the same functions. UART2 to UART4, in particular, are compliant with the SIM interface with some extra settings added in clock-asynchronous serial I/O mode (Note). It also has the bus collision detection function that generates an interrupt request if the TxD pin and the RxD pin are different in level. Table 16.1 shows the comparison of functions of UART0 to UART4, and Figures 16.5 through 16.11 show the registers related to UARTi. Note: SIM : Subscriber Identity Module Note 1: Only when clock synchronous serial I/O mode. Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode. Note 3: Only when UART mode. Note 4: Using for SIM interface. UART0 UART1 UART2Function CLK polarity selection Continuous receive mode selection LSB first / MSB first selection ImpossibleTransfer clock output from multiple pins selection Impossible Impossible Impossible ImpossibleSerial data logic switch Impossible Sleep mode selection Impossible ImpossibleTxD, RxD I/O polarity switch Impossible Possible CMOS outputTxD, RxD port output format CMOS output N-channel open drain output ImpossibleParity error signal output Impossible ImpossibleBus collision detection Impossible Possible Possible(Note 1) Separate CTS/RTS pins Possible(Note 1) Possible(Note 1) Possible(Note 3) Possible(Note 1) Possible(Note 1) Possible(Note 1) Possible(Note 1) Possible(Note 3) Possible Possible(Note 1) Possible(Note 2) Possible(Note 1) Possible(Note 4) Possible(Note 4) UART3 Impossible Impossible Impossible Possible Possible Possible(Note 1) Possible(Note 2) Possible(Note 1) Possible(Note 4) Possible(Note 4) UART4 Impossible Impossible Impossible Possible Possible Possible(Note 1) Possible(Note 2) Possible(Note 1) Possible(Note 4) Possible(Note 4) CMOS output CMOS output Table 16.1 Comparison of functions of UART0 to UART4

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 125 16. Serial I/OpuorG08/C61M Figure 16.1 Block diagram of UARTi (i = 0 to 2) n0 : Values set to UART0 bit rate generator (BRG0) n1 : Values set to UART1 bit rate generator (BRG1) n2 : Values set to UART2 bit rate generator (BRG2) RxD2 Reception control circuit Transmission control circuit 1 / (n2+1) Bit rate generator Clock synchronous type (when internal clock is selected) UART reception Clock synchronous type UART transmission Clock synchronous type Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) Receive clock Transmit clock CLK2 CTS2 / RTS2 f32 Vss RTS 2 CTS 2 TxD2 (UART2) RxD polarity reversing circuit TxD polarity reversing circuit RxD0 1 / (n0+1) Clock synchronous type (when internal clock is selected) UART reception Clock synchronous type UART transmission Clock synchronous type Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) Receive clock Transmit clock CLK0 Clock source selection CTS0 / RTS0 f32 Reception control circuit Transmission control circuit Internal External Vss RTS 0 CTS 0 TxD0 Transmit/ receive unit RxD1 1 / (n1+1) Clock synchronous type (when internal clock is selected) UART reception Clock synchronous type UART transmission Clock synchronous type Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) Receive clock Transmit clock CLK1 Clock source selection f32 Reception control circuit Transmission control circuit Internal External RTS 1 CTS 1 TxD1 (UART1) (UART0) CLK polarity reversing circuit CLK polarity reversing circuit CTS/RTS disabled CTS/RTS separated Clock output pin select switch CTS1 / RTS1 / CTS0 / CLKS1 CTS/RTS disabled CTS0 from UART1 CTS/RTS selected CTS/RTS disabled VSS CTS0 to UART0CTS 0 CTS/RTS disabled CTS/RTS separated CTS/RTS disabled CTS/RTS disabled CTS/RTS selected CLK polarity reversing circuit Internal External Clock source selection Transmit/ receive unit Transmit/ receive unit Bit rate generator Bit rate generator

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 126 16. Serial I/OpuorG08/C61M RxD3 Reception control circuit Transmission control circuit 1 / (n2+1) Bit rate generator Clock synchronous type (when internal clock is selected) UART reception Clock synchronous type UART transmission Clock synchronous type Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) Receive clock Transmit clock CLK3 CTS3 / RTS3 f32 Vss RTS 3 CTS 3 TxD3 (UART3) RxD polarity reversing circuit TxD polarity reversing circuit CTS/RTS disabled CTS/RTS disabled CTS/RTS selected CLK polarity reversing circuit Internal External Clock source selection Transmit/ receive unit n3 : Values set to UART3 bit rate generator (BRG3) n4 : Values set to UART4 bit rate generator (BRG4) RxD4 Reception control circuit Transmission control circuit 1 / (n2+1) Bit rate generator Clock synchronous type (when internal clock is selected) UART reception Clock synchronous type UART transmission Clock synchronous type Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) Receive clock Transmit clock CLK4 CTS4 / RTS4 f32 Vss RTS 4 CTS 4 TxD4 (UART4) RxD polarity reversing circuit TxD polarity reversing circuit CTS/RTS disabled CTS/RTS disabled CTS/RTS selected CLK polarity reversing circuit Internal External Clock source selection Transmit/ receive unit Figure 16.2 Block diagram of UARTi (i = 3, 4)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 127 16. Serial I/OpuorG08/C61M Figure 16.3 Block diagram of UARTi (i = 0, 1) transmit/receive unit SP SP PAR 2SP 1SP UART UART (7 bits) UART (8 bits) UART (7 bits) UART (9 bits) Clock synchronous type Clock synchronous type TxDi UARTi transmit register PAR enabled PAR disabled D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 SP: Stop bit PAR: Parity bit UARTi transmit buffer register MSB/LSB conversion circuit UART (8 bits) UART (9 bits) Clock synchronous type UARTi receive buffer register UARTi receive register 2SP 1SP PAR enabled PAR disabled UART UART (7 bits) UART (9 bits) Clock synchronous type Clock synchronous type UART (7 bits) UART (8 bits) RxDi Clock synchronous type UART (8 bits) UART (9 bits) Address 036616 Address 036716 Address 036E16 Address 036F16 Address 036216 Address 036316 Address 036A16 Address 036B16 Data bus low-order bits MSB/LSB conversion circuit D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0D 80000000 SP SP PAR “0” Data bus high-order bits

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 128 16. Serial I/OpuorG08/C61M SP SP PAR 2SP 1SP UART UART (7 bits) UART (8 bits) UART(7 bits) UART (9 bits) Clock synchronous type Clock synchronous type Data bus low-order bits TxDi UARTi transmit registerPAR disabled PAR enabled D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 UART2 transmit buffer register UART (8 bits) UART (9 bits) Clock synchronous type UARTi receive buffer register UARTi receive register 2SP 1SP UART (7 bits) UART (8 bits) UART(7 bits) UART (9 bits) Clock synchronous type Clock synchronous type RxDi UART (8 bits) UART (9 bits) Address 033E Address 033F16 Address 032E16 Address 032F16 Address 02FE16 Address 02FF16 Address 033A16 Address 033B16 Address 032A16 Address 032B16 Address 02FA16 Address 02FB16 Data bus high-order bits D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0D 80000000 SP SP PAR “0” Reverse No reverse Error signal output circuit RxD data reverse circuit Error signal output enable Error signal output disable Reverse No reverse Logic reverse circuit + MSB/LSB conversion circuit Logic reverse circuit + MSB/LSB conversion circuit PAR enabled PAR disabled UART Clock synchronous type TxD data reverse circuit SP : Stop bit PAR : Parity bit i: 2 t o 4 Figure 16.4 Block diagram of UARTi (i = 2 to 4) transmit/receive unit

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 129 16. Serial I/OpuorG08/C61M Figure 16.5 Serial I/O-related registers (1) UARTi bit rate generator (Note 1, 2) Symbol Address When reset U0BRG 0361 16 Indeterminate U1BRG 0369 16 Indeterminate U2BRG 0339 16 Indeterminate U3BRG 0329 16 Indeterminate U4BRG 02F9 16 Indeterminate Function Assuming that set value = n, BRGi divides the count source by n + 1 0016 to FF16 Values that can be set WR /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines b7 b0 (b15) (b8) b7 b0 UARTi transmit buffer register (Note) Function Transmit data Nothing is assigned. When write, set "0". When read, their contents are indeterminate. Symbol Address When reset U0TB 0363 16, 036216 Indeterminate U1TB 036B 16, 036A16 Indeterminate U2TB 033B 16, 033A16 Indeterminate U3TB 032B 16, 032A16 Indeterminate U4TB 02FB 16, 02FA16 Indeterminate WR /LiteDiagLines (b15) Symbol Address When reset U0RB 0367 16, 036616 Indeterminate U1RB 036F 16, 036E16 Indeterminate U2RB 033F 16, 033E16 Indeterminate U3RB 032F 16, 032E16 Indeterminate U4RB 02FF 16, 02FE16 Indeterminate b7 b0 (b8) b7 b0 UARTi receive buffer register OER FER SUM Function (During UART mode) Function (During clock synchronous serial I/O mode) Bit nameBit symbol 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found Note 1: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses 036016, 036816, 033816, 032816 and 02F816) are set to “0002” or the receive enable bit is set to “0”. (Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the lower byte of the UARTi receive buffer register (addresses 036616, 036E16, 033E16, 032E16 and 02FE16) is read out. Note 2: Arbitration lost detecting flag is allocated to U2RB, U3RB and U4RB and nothing but “0” may be written. Nothing is assigned in bit 11 of U0RB and U1RB. When write, set "0". When read, the value of this bit is “0”. Invalid Invalid InvalidPER Overrun error flag (Note 1) Framing error flag (Note 1) Parity error flag (Note 1) Error sum flag (Note 1) 0 : No overrun error 1 : Overrun error found 0 : No overrun error 1 : Overrun error found Nothing is assigned. When write, set "0". When read, the value of these bits is “0”. Receive data WR Receive data /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines ABT Arbitration lost detecting flag (Note 2) Invalid0 : Not detected 1 : Detected /LiteDiagLines/LiteDiagLines/LiteDiagLines Note 1: Use MOV instruction to write to this register. Note 2: Write a value to this register while transmit/receive halts. Note: Use MOV instruction to write to this register.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 130 16. Serial I/OpuorG08/C61M UARTi transmit/receive mode register Symbol Address When reset UiMR(i=0,1) 0360 16, 036816 0016 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol WR Must be fixed to 001 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set 0 1 1 : Must not be set 1 1 1 : Must not be set b2 b1 b0 CKDIR SMD1 SMD0 Serial I/O mode select bit SMD2 Internal/external clock select bit STPS PRY PRYE SLEP Parity enable bit 0 : Internal clock (Note 1) 1 : External clock (Note 2) Stop bit length select bit Odd/even parity select bit Sleep select bit 0 : One stop bit 1 : Two stop bits 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set 0 1 1 : Must not be set 1 1 1 : Must not be set b2 b1 b0 0 : Internal clock 1 : External clock (Note 2) Invalid Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity Invalid Invalid Set to “0” Function (During UART mode) Function (During clock synchronous serial I/O mode) UARTi transmit/receive mode register Symbol Address When reset UiMR (i=2 to 4) 0338 16, 032816, 02F816 0016 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol WR Must be fixed to 001 0 0 0 : Serial I/O invalid 0 1 0 : (Note) 0 1 1 : Must not be set 1 1 1 : Must not be set b2 b1 b0 CKDIR SMD1 SMD0 Serial I/O mode select bit SMD2 Internal/external clock select bit STPS PRY PRYE IOPOL Parity enable bit 0 : Internal clock (Note 2) 1 : External clock (Note 3) Stop bit length select bit Odd/even parity select bit TxD, RxD I/O polarity reverse bit 0 : One stop bit 1 : Two stop bits 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse Usually set to “0” 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set 0 1 1 : Must not be set 1 1 1 : Must not be set b2 b1 b0 0 : Internal clock 1 : External clock (Note 3) Invalid Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity Invalid Invalid 0 : No reverse 1 : Reverse Usually set to “0” Function (During UART mode) Function (During clock synchronous serial I/O mode) /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Note 1: Bit 2 to bit 0 are set to “0102” when I2C mode is used. Note 2: Select CLK output by the corresponding function select registers A, B and C. Note 3: Set the corresponding function select register A to the I/O port. Note 1: Select CLK output by the corresponding function select registers A, B and C. Note 2: Set the corresponding function select register A to the I/O port. Figure 16.6 Serial I/O-related registers (2)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 131 16. Serial I/OpuorG08/C61M Function (During UART mode) WR Function (During clock synchronous serial I/O mode) TXEPT CLK1 CLK0 CRS CRD NCH CKPOL BRG count source select bit Transmit register empty flag 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge CLK polarity select bit CTS/RTS function select bit CTS/RTS disable bit Data output select bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set b1 b0 0 : LSB first 1 : MSB first 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open drain output UFORM Transfer format select bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set b1 b0 Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open drain output Set to “0” Bit nameBit symbol Set to “0” Note 1: Set the corresponding function select register A to I/O port, and port direction register to “0”. Note 2: Select RTS output using the corresponding function select registers A and B. 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines Function (During UART mode) WR Function (During clock synchronous serial I/O mode) TXEPT CLK1 CLK0 CRS CRD CKPOL BRG count source select bit Transmit register empty flag 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge CLK polarity select bit CTS/RTS function select bit CTS/RTS disable bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set b1 b0 0 : LSB first 1 : MSB first 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open-drain output UFORM Transfer format select bit (Note 3) 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set b1 b0 Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output Set to “0” Bit nameBit symbol Note 1: Set the corresponding function select register A to I/O port, and port direction register to “0”. Note 2: Select RTS output using the corresponding function select registers A and B. Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid. 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled Nothing is assigned. When write, set “0”. When read, the value of this bit is “0”. 0 : LSB first 1 : MSB first /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines UART2 transmit/receive control register 0 Symbol Address When reset U2C0 033C 16 0816 b7 b6 b5 b4 b3 b2 b1 b0 UARTi transmit/receive control register 0 Symbol Address When reset UiC0(i=0,1) 0364 16, 036C16 0816 b7 b6 b5 b4 b3 b2 b1 b0 Figure 16.7 Serial I/O-related registers (3)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 132 16. Serial I/OpuorG08/C61M Figure 16.8 Serial I/O-related registers (4) Function (During UART mode) WR Function (During clock synchronous serial I/O mode) TXEPT CLK1 CLK0 CRS CRD NCH CKPOL BRG count source select bit Transmit register empty flag 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge CLK polarity select bit CTS/RTS function select bit CTS/RTS disable bit Data output select bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set b1 b0 0 : LSB first 1 : MSB first 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open drain output UFORM Transfer format select bit (Note 3) 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set b1 b0 Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open drain output Set to “0” Bit nameBit symbol Note 1: Set the corresponding function select register A to I/O port, and port direction register to “0”. Note 2: Select RTS output using the corresponding function select registers A and B. Note 3: Valid only in clock syncronous serial I/O mode and 8 bits UART mode. 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines UARTi transmit/receive control register 0 Symbol Address When reset UiC0(i=3,4) 032C 16, 02FC16 0816 b7 b6 b5 b4 b3 b2 b1 b0 0 : LSB first 1 : MSB first

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 133 16. Serial I/OpuorG08/C61M Figure 16.9 Serial I/O-related registers (5) UARTi transmit/receive control register 1 Symbol Address When reset UiC1(i=0,1) 0365 16,036D 16 0216 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol WRFunction (During UART mode) Function (During clock synchronous serial I/O mode) TE TI RE RI Transmit enable bit Receive enable bit Receive complete flag Transmit buffer empty flag 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : No data present in receive buffer register 1 : Data present in receive buffer register Nothing is assigned. When write, set "0". When read, the value of these bits is “0”.UARTi transmit/receive control register 1 Symbol Address When reset UiC1 (i=2 to 4) 033D 16, 032D16, 02FD16 0216 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol WRFunction (During UART mode) Function (During clock synchronous serial I/O mode) TE TI RE RI Transmit enable bit Receive enable bit Receive complete flag Transmit buffer empty flag 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : No data present in receive buffer register 1 : Data present in receive buffer register UiIRS UARTi transmit interrupt cause select bit 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) UiRRM UARTi continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Data logic select bit 0 : No reverse 1 : Reverse 0 : No reverse 1 : Reverse UiLCH UiERE Error signal output enable bit Set to “0” 0 : Output disabled 1 : Output enabled /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Set to “0”

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 134 16. Serial I/OpuorG08/C61M UART transmit/receive control register 2 Symbol Address When reset UCON 0370 16 X0XX0000 2 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol WRFunction (During UART mode) Function (During clock synchronous serial I/O mode) RCSP UART0 transmit interrupt cause select bit UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enable UART1 continuous receive mode enable bit UART1 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Nothing is assigned. When write, set "0". When read, its content is indeterminate. 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) U0IRS U1IRS U0RRM U1RRM 0 : CTS/RTS shared pin 1 : CTS/RTS separated 0 : CTS/RTS shared pin 1 : CTS/RTS separated Separate CTS/RTS bit /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines UARTi special mode register Symbol Address When reset UiSMR (i=2 to 4) 0337 16, 032716, 02F716 0016 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol WRFunction (During UART mode) Function (During clock synchronous serial I/O mode) ABSCS ACSE SSS IIC mode select bit Bus busy flag 0 : STOP condition detected 1 : START condition detected SCLL sync output enable bit Bus collision detect sampling clock select bit Arbitration lost detecting flag control bit 0 : Normal mode 1 : IIC mode 0 : Update per bit 1 : Update per byte IICM ABC BBS LSYN 0 : Ordinary 1 : Falling edge of RxDi 0 : Disabled 1 : Enabled Transmit start condition select bit Set to “0” 0 : Rising edge of transfer clock 1 : Underflow signal of timer Ai (Note 2) Auto clear function select bit of transmit enable bit /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines 0 : No auto clear function 1 : Auto clear at occurrence of bus collision Set to “0” Set to “0” Set to “0” Set to “0” Set to “0” Set to “0” Nothing is assigned. When write, set "0". When read, its content is indeterminate. Note 1: Nothing but "0" may be written. Note 2: UART2 : timer A0 underflow signal, UART3 : timer A3 underflow signal, UART4 : timer A4 underflow signal. (Note1) Nothing is assigned. When write, set "0". When read, its content is indeterminate. Set to “0” Set to “0” Figure 16.10 Serial I/O-related registers (6)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 135 16. Serial I/OpuorG08/C61M Figure 16.11 Serial I/O-related registers (7) UARTi special mode register 2 Symbol Address When reset UiSMR2 (i=2 to 4) 0336 16, 032616, 02F616 0016 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol WRFunction IICM2 CSC SWC ALS IIC mode select bit 2 SCL wait output bit SDA output stop flag Clock synchronous bit 0 : NACK/ACK interrupt DMA source - ACK Transfer to receive buffer at the rising edge of last bit of receive clock Receive interrupt is occurred at the rising edge of last bit of receive clock 1 : UART transfer/receive interrupt DMA source - UART receive Transfer to receive buffer at the falling edge of last bit of receive clock Receive interrupt is occurred at the falling edge of last bit of receive clock 0 : Disabled 1 : Enabled STC UARTi initialize bit SWC2 SCL wait output bit 2 SDA output inhibit bitSDHI SHTC Start/stop condition control bit /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : UARTi clock 1 : 0 output 0 : Enabled 1 : Disabled (high impedance) Must set to "1" in selecting IIC mode. /LiteDiagLines /LiteDiagLines

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 136 16. Serial I/OpuorG08/C61M Figure 16.12 Serial I/O-related registers (8) Symbol Address When reset U2SMR3 0335 16 000XXXXX 2 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset U3SMR3 0325 16 000000002 U4SMR3 02F5 16 000000002 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 SSE SS port function enable bit0: SS function disable 1: SS function enable 0: Without fault error 1: With fault error CKPH DINC NODC ERR Clock phase set bit Serial input port set bit Clock output select bit 0: Select TxDi and RxDi (master mode) (Note 5) 1: Select STxDi and SRxDi (slave mode) (Note 6) 0: CLKi is CMOS output 1: CLKi is N-channel open drain output Fault error flag (Note 3) (Note 4) 0: Without clock delay 1: With clock delay 000:Without delay 001:1 to 2 cycles of 1/f(XIN) 010:2 to 3 cycles of 1/f(XIN) 011:3 to 4 cycles of 1/f(XIN) 100:4 to 5 cycles of 1/f(XIN) 101:5 to 6 cycles of 1/f(XIN) 110:6 to 7 cycles of 1/f(XIN) 111:7 to 8 cycles of 1/f(XIN) SDA 2(TxD2) digital delay time set bit (Note 1,2) DL0 DL1 DL2 UART2 special mode register 3 Note 1: These bits are used for SDA2(TxD2) output digital delay when using UART2 for IIC interface. Otherwise, must set to "000". Note 2: When external clock is selected, delay is increased approx. 100ns. UARTi special mode register 3 (i=3,4) 000 :Without delay 001 :1 to 2 cycles of 1/f(X IN) 010 :2 to 3 cycles of 1/f(XIN) 011 :3 to 4 cycles of 1/f(XIN) 100 :4 to 5 cycles of 1/f(XIN) 101 :5 to 6 cycles of 1/f(XIN) 110 :6 to 7 cycles of 1/f(XIN) 111 :7 to 8 cycles of 1/f(XIN) SDAi(TxD2) digital delay time set bit (Note 1,2) DL0 DL1 DL2 Note 1: These bits are used for SDAi(TxDi) output digital delay when using UARTi for IIC interface. Otherwise, must set to "000". Note 2: When external clock is selected, delay is increased approx. 100ns. Note 3: Set SS function after setting CTS/RTS disable bit (bit 4 of UARTi transfer/receive control register 0) to "1". Note 4: Nothing but "0" may be written. Note 5: Set CLKi and TxDi both for output using the CLKi and TxDi function select register A. Set the RxDi function select register A for input/output port and the port direction register to "0". Note 6: Set STxDi for output using the STxDi function select registers A and B. Set the CLKi and SRxDi function select register A for input/output port and the port direction register to "0". b7 b6 b5 b7 b6 b5 Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 137 17. Clock synchronous serial I/O modepuorG08/C61M 17. Clock synchronous serial I/O mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 17.1 and 17.2 list the specifications of the clock synchronous serial I/O mode. Figure 17.1 shows the UARTi transmit/receive mode register. Table 17.1 Specifications of clock synchronous serial I/O mode (1) Item Specification Transfer data format • Transfer data length: 8 bits Transfer clock • When internal clock is selected (bit 3 at addresses 036016, 036816, 033816, _ CLK is selected by the corresponding port function select register, periph- eral function select register and peripheral subfunction select register.

When external clock is selected (bit 3 at addresses 036016, 036816, 033816 , 032816, 02F816= “1”) : Input from CLKi pin _ Set the corresponding function select register A to I/O port Transmission/reception control
CTS function/RTS function/CTS, RTS function chosen to be invalid Transmission start condition• To start transmission, the following requirements must be met: _ Transmit enable bit (bit 0 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = “1” _ Transmit buffer empty flag (bit 1 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = “0” _ When CTS function selected, CTS input level = “L” _ TxD output selected by the corresponding function select register A, B and C.
Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 036416, 036C16, 033C16, 032C 16, 02FC16) = “0”: CLKi input level = “H ” _ CLKi polarity select bit (bit 6 at addresses 036416, 036C16, 033C16, 032C 16, 02FC16) = “1”: CLKi input level = “L” Reception start condition• To start reception, the following requirements must be met: _ Receive enable bit (bit 2 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = “1” _ Transmit enable bit (bit 0 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = “1” _ Transmit buffer empty flag (bit 1 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = “0”
Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 036416, 036C16, 033C16, 032C 16, 02FC16) = “0”: CLKi input level = “H ” _ CLKi polarity select bit (bit 6 at addresses 036416, 036C16, 033C16, 032C 16, 02FC16) = “1”: CLKi input level = “L”
When transmitting _ Transmit interrupt cause select bit (bits 0, 1 at address 037016, bit 4 at address 033D 16, 032D16, 02FD16) = “0”: Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed _ Transmit interrupt cause select bit (bits 0, 1 at address 037016, bit 4 at address 033D16, 032D16, 02FD16) = “1”: Interrupts requested when data transmission from UARTi transfer register is completed
When receiving _ Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed Interrupt request generation timing Note : “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 138 17. Clock synchronous serial I/O modepuorG08/C61M Item Specification Error detection • Overrun error (Note 1) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out Select function • CLK polarity selection Whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected

LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected
Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register
Transfer clock output from multiple pins selection (UART1) (Note 2) UART1 transfer clock can be chosen by software to be output from one of the two pins set
Separate CTS/RTS pins (UART0) (Note 2) UART0 CTS and RTS pins each can be assigned to separate pins
Switching serial data logic (UART2 to UART4) Whether to reverse data in writing to the transmission buffer register or reading the reception buffer register can be selected.
TxD, RxD I/O polarity reverse (UART2 to UART4) This function is reversing TxD port output and RxD port input. All I/O data level is reversed. Table 17.2 Specifications of clock synchronous serial I/O mode (2) Note 1: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit will not change. Note 2: The transfer clock output from multiple pins and the separate CTS/RTS pins functions cannot be selected simultaneously.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 139 17. Clock synchronous serial I/O modepuorG08/C61M Figure 17.1 UARTi transmit/receive mode register in clock synchronous serial I/O mode Symbol Address When reset UiMR(i=0,1) 0360 16, 036816 0016 CKDIR UARTi transmit/receive mode registers Internal/external clock select bit STPS PRY PRYE SLEP 0 : Internal clock (Note 1) 1 : External clock (Note 2) Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 0 (Set to “0” in clock synchronous serial I/O mode) 010 SMD0 SMD1 SMD2 Serial I/O mode select bit 0 0 1 : Clock synchronous serial I/O mode b2 b1 b0 Invalid in clock synchronous serial I/O mode CKDIR UART2 transmit/receive mode register Internal/external clock select bit STPS PRY PRYE IOPOL 0 : Internal clock (Note 2) 1 : External clock (Note 3) Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 010 SMD0 SMD1 SMD2 Serial I/O mode select bit0 0 1 : Clock synchronous serial I/O mode b2 b1 b0 Invalid in clock synchronous serial I/O mode TxD, RxD I/O polarity reverse bit (Note 1) 0 : No reverse 1 : Reverse /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Note 1: Usually set to “0”. Note 2: Select CLK output by the corresponding function select registers A, B and C. Note 3: Set the corres ponding function select register A to the I/O port. Note 1: Select CLK output by the corresponding function select registers A, B and C. Note 2: Set the corresponding function select register A to the I/O port. Symbol Address When reset UiMR (i=2 to 4) 0338 16, 032816, 02F816 0016

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 140 17. Clock synchronous serial I/O modepuorG08/C61M Table 17.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. This table shows the pin functions when the transfer clock output from multiple pins and the separate CTS/ RTS pins functions are not selected. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H ”. (If the N-channel open drain is selected, this pin is in floating state.) Table 17.3 Input/output pin functions in clock synchronous serial I/O mode Pin name Function Method of selection TxDi (P63, P67, P70, P92, P96) Serial data output (Note 1) Serial data input (Note 2) Transfer clock output (Note 1) Transfer clock input (Note 2) Programmable I/O port (Note 2) (Outputs dummy data when performing reception only) RxDi (P6 2, P66, P71, P91, P97) CLKi (P61, P65, P72, P90, P95) Internal/external clock select bit (bit 3 at addresses 036016, 036816, 033816, 032816, 02F816) = “0” Internal/external clock select bit (bit 3 at addresses 036016, 036816, 033816, 032816, 02F816) = “1” Port P61, P65, P72, P90 and P95 direction register (bits 1 and 5 at address 03C2 16, bit 2 at address 03C316, bit 0 and 5 at address 03C716) = “0” Port P62, P66, P71, P91 and P97 direction register (bits 2 and 6 at address 03C2 16, bit 1 at address 03C316, bit 1 and 7 at address 03C716)= “0” (Can be used as an input port when performing transmission only) CTS/RTS disable bit (bit 4 at addresses 036416, 036C16, 033C16, 032C16, 02FC 16) =“0” CTS/RTS function select bit (bit 2 at addresses 036416, 036C16, 033C16, 032C 16, 02FC16) = “0” Port P60, P64, P73, P93 and P94 direction register (bits 0 and 4 at address 03C2 16, bit 3 at address 03C316, bits 3 and 4 at address 03C716) = “0” CTS/RTS disable bit (bit 4 at addresses 036416, 036C16, 033C16, 032C 16, 02FC16) = “0” CTS/RTS function select bit (bit 2 at addresses 036416, 036C16, 033C16, 032C 16, 02FC16) = “1” CTS/RTS disable bit (bit 4 at addresses 036416, 036C16, 033C16, 032C 16, 02FC16) = “1” CTS input (Note 2) RTS output (Note 1) CTSi/RTSi (P6 0, P64, P73, P93, P94) (when transfer clock output from multiple pins and separate CTS/RTS pins functions are not selected) Note 1: Select TxD output, CLK output and RTS output by the corresponding function select registers A, B and C. Note 2: Select I/O port by the corresponding function select register A.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 141 17. Clock synchronous serial I/O modepuorG08/C61M Figure 17.2 Typical transmit/receive timings in clock synchronous serial I/O mode

Example of transmit timing (when internal clock is selected) D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Tc TCLK Stopped pulsing because transfer enable bit = “0” Data is set in UARTi transmit buffer register Tc = TCLK = 2(n + 1) / fi fi: frequency of BRGi count source (f1, f8, f32) n: value set to BRGi Transfer clock Transmit enable bit (TE) Transmit buffer empty flag (Tl) CLKi TxDi Transmit register empty flag (TXEPT) “H ” “L” “0” “1” “0” “1” “0” “1” CTSi The above timing applies to the following settings:
Internal clock is selected.
CTS function is selected.
CLK polarity select bit = “0”.
Transmit interrupt cause select bit = “0”. Transmit interrupt request bit (IR)“0” “1” Stopped pulsing because CTS = “H ” Transferred from UARTi transmit buffer register to UARTi transmit register Shown in ( ) are bit symbols. Cleared to “0” when interrupt request is accepted, or cleared by software 1 / fEXT Dummy data is set in UARTi transmit buffer register Transmit enable bit (TE) Transmit buffer empty flag (Tl) CLKi RxDi Receive complete flag (Rl) RTSi “H ” “L” “0” “1” “0” “1” “0” “1” Receive enable bit (RE) “0” “1” Receive data is taken in Transferred from UARTi transmit buffer register to UARTi transmit register Read out from UARTi receive buffer register The above timing applies to the following settings:
External clock is selected.
RTS function is selected.
CLK polarity select bit = “0”. fEXT : frequency of external clock Transferred from UARTi receive register to UARTi receive buffer register Receive interrupt request bit (IR)“0” “1” D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 Shown in ( ) are bit symbols. Meet the following conditions are met when the CLKi input before data reception = “H ”
Transmit enable bit “1”
Receive enable bit “1”
Dummy data write to UARTi transmit buffer register Cleared to “0” when interrupt request is accepted, or cleared by software
Example of receive timing (when external clock is selected)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 144 18. Clock asynchronous serial I/O (UART) modepuorG08/C61M Item Specification Transfer data format • Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected

Start bit: 1 bit
Parity bit: Odd, even, or nothing as selected
Stop bit: 1 bit or 2 bits as selected Transfer clock • When internal clock is selected (bit 3 at addresses 036016, 036816, 033816, 032816, 02F816 = “0”) : fi/16(n+1) (Note 1) fi = f1, f8, f32
When external clock is selected (bit 3 at addresses 036016, 036816, 033816, 032816, 02F816 =“1”) : fEXT /16(n+1)(Note 1) (Note 2) Transmission/reception control
CTS function/RTS function/CTS, RTS function chosen to be invalid Transmission start condition• To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = “1” - Transmit buffer empty flag (bit 1 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = “0” - When CTS function selected, CTS input level = “L” - TxD output is selected by the corresponding function select register A, B and C. Reception start condition• To start reception, the following requirements must be met: - Receive enable bit (bit 2 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = “1” - Start bit detection Interrupt request • When transmitting generation timing - Transmit interrupt cause select bits (bits 0,1 at address 037016, bit 4 at address 033D16, 032D16, 02FD16) = “0”: Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed - Transmit interrupt cause select bits (bits 0, 1 at address 037016, bit 4 at address 033D16, 032D16, 02FD16) = “1”: Interrupts requested when data transmission from UARTi transfer register is completed
When receiving - Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed 18. Clock asynchronous serial I/O (UART) mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer UARTi transmit/receive mode register. Table 18.1 Specifications of UART Mode (1) Note 1: ‘n’ denotes the value 00 16 to FF16 that is set to the UARTi bit rate generator. Note 2: fEXT is input from the CLKi pin.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 145 puorG08/C61M 18. Clock asynchronous serial I/O (UART) mode Table 18.2 Specifications of UART Mode (2) Note: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit will not change. Item Specification Error detection • Overrun error (Note) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out

Framing error This error occurs when the number of stop bits set is not detected
Parity error This error occurs when if parity is enabled, the number of 1’s in parity and character bits does not match the number of 1’s set
Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered Select function
Separate CTS/RTS pins (UART0) UART0 CTS and RTS pins each can be assigned to separate pins
Sleep mode selection (UART0, UART1) This mode is used to transfer data to and from one of multiple slave micro- computers
Serial data logic switch (UART2 to UART4) This function is reversing logic value of transferring data. Start bit, parity bit and stop bit are not reversed.
TxD, RxD I/O polarity switch (UART2 to UART4) This function is reversing TxD port output and RxD port input. All I/O data level is reversed.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 146 18. Clock asynchronous serial I/O (UART) modepuorG08/C61M Figure 18.1 UARTi transmit/receive mode register in UART mode Symbol Address When reset UiMR(i=0,1) 0360 16, 036816 0016 CKDIR UARTi transmit / receive mode registers Internal / external clock select bit STPS PRY PRYE SLEP 0 : Internal clock 1 : External clock (Note) Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 SMD0 SMD1 SMD2 Serial I/O mode select bit b2 b1 b0 0 : One stop bit 1 : Two stop bits 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity Stop bit length select bit Odd / even parity select bit Parity enable bit Sleep select bit CKDIR UARTi transmit / receive mode register Internal / external clock select bit STPS PRY PRYE IOPOL 0 : Internal clock 1 : External clock (Note 2) Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 SMD0 SMD1 SMD2 Serial I/O mode select bit b2 b1 b0 0 : One stop bit 1 : Two stop bits 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity Stop bit length select bit Odd / even parity select bit Parity enable bit TxD, RxD I/O polarity reverse bit (Note 1) /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Note 1: Usually set to “0”. Note 2: Set the corresponding port function select register A to I/O port. Symbol Address When reset UiMR (i=2 to 4) 0338 16, 032816, 02F816 0016 0 : Internal clock 1 : External clock (Note) Note: Set the corresponding port function select register A to I/O port.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 147 puorG08/C61M 18. Clock asynchronous serial I/O (UART) mode Table 18.3 lists the functions of the input/output pins during UART mode. This table shows the pin functions when the separate CTS/RTS pins function is not selected. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H ”. (If the N-channel open drain is selected, this pin is in floating state.) Table 18.3 Input/output pin functions in UART mode Note 1: Select TxD output, CLK output and RTS output by the corresponding function select registers A, B and C. Note 2: Select I/O port by the corresponding function select register A. Pin name Function Method of selection Serial data output (Note 1) Serial data input (Note 2) Programmable I/O port (Note 2) Transfer clock input (Note 2) Programmable I/O port Internal/external clock select bit (bit 3 at addresses 036016, 036816, 033816, 032816, 02F816) = “0” Internal/external clock select bit (bit 3 at addresses 036016, 036816, 033816, 032816, 02F816) = “1” Port P61, P65, P72, P90 and P95 direction register (bits 1 and 5 at address 03C2 16, bit 2 at address 03C316, bits 0 and 5 at address 03C716) = “0” Port P62, P66, P71, P91 and P97 direction register (bits 2 and 6 at address 03C2 16, bit 1 at address 03C316, bit 1 and 7 at address 03C716)= “0” (Can be used as an input port when performing transmission only) CTS/RTS disable bit (bit 4 at addresses 036416, 036C16, 033C16, 032C 16, 02FC16) =“0” CTS/RTS function select bit (bit 2 at addresses 036416, 036C16, 033C16, 032C 16, 02FC16) = “0” Port P60, P64, P73, P93 and P94 direction register (bits 0 and 4 at address 03C2 16, bit 3 at address 03C316, bits 3 and 4 at address 03C716) = “0” CTS input (Note 2) RTS output TxDi (P6 3, P67, P70, P92, P96) RxDi (P62, P66, P71, P91, P97) CLKi (P61, P65, P72, P90, P95) CTSi/RTSi (P60, P64, P73, P93, P94) CTS/RTS disable bit (bit 4 at addresses 036416, 036C16, 033C16, 032C16, 02FC 16) = “0” CTS/RTS function select bit (bit 2 at addresses 036416, 036C16, 033C16, 032C 16, 02FC16) = “1” CTS/RTS disable bit (bit 4 at addresses 036416, 036C16, 033C16, 032C16, 02FC 16) = “1” (Note 1) (Note 2) (When separate CTS/RTS pins function is not selected)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 148 18. Clock asynchronous serial I/O (UART) modepuorG08/C61M Transmit enable bit(TE) Transmit buffer empty flag(TI) Transmit register empty flag (TXEPT) Start bit Parity bit TxDi CTSi The above timing applies to the following settings :

Parity is enabled.
One stop bit.
CTS function is selected.
Transmit interrupt cause select bit = “1”. “1” “0” “1” “L” “H ” “0” “1” Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Transmit interrupt request bit (IR) “0” “1” Cleared to “0” when interrupt request is accepted, or cleared by software Transmit enable bit(TE) Transmit buffer empty flag(TI) TxDi Transmit register empty flag (TXEPT) “0” “1” “0” “1” “0” “1” The above timing applies to the following settings :
Parity is disabled.
Two stop bits.
CTS function is disabled.
Transmit interrupt cause select bit = “0”. Transfer clock Tc Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Transmit interrupt request bit (IR) “0” “1” Shown in ( ) are bit symbols. Shown in ( ) are bit symbols. Tc Transfer clock D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7SP ST P SP D 0 D 1ST Stopped pulsing because transmit enable bit = “0”Stop bit Transferred from UARTi transmit buffer register to UARTi transmit register Start bit The transfer clock stops momentarily as CTS is “H ” when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTS changes to “L”. Data is set in UARTi transmit buffer register D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST SPD 8 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST D 8 D 0 D 1STSP SP Transferred from UARTi transmit buffer register to UARTi transmit register Stop bit Stop bit Data is set in UARTi transmit buffer register.“0” SP Cleared to “0” when interrupt request is accepted, or cleared by software
Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) Figure 18.2 Typical transmit timings in UART mode

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 151 19. Clock-asynchronous serial I/O mode (compliant with the SIM interface)puorG08/C61M Item Specification Transfer data format • Transfer data 8-bit UART mode (bit 2 to 0 of addresses 033816, 032816, 02F816 = “1012”)

One stop bit (bit 4 of addresses 033816, 032816, 02F816 = “0”)
With the direct format chosen Set parity to “even” (bit 5 and 6 of addresses 033816, 032816, 02F816 = “1” and “1” respectively) Set data logic to “direct” (bit 6 of address 033D16, 032D16, 02FD 16 = “0”). Set transfer format to LSB (bit 7 of address 033C16, 032C16, 02FC 16 = “0”).
With the inverse format chosen Set parity to “odd” (bit 5 and 6 of addresses 033816, 032816, 02F816 = “0” and “1” respectively) Set data logic to “inverse” (bit 6 of address 033D16, 032D16, 02FD 16 = “1”) Set transfer format to MSB (bit 7 of address 033C16, 032C16, 02FC 16 = “1”) Transfer clock • With the internal clock chosen (bit 3 of addresses 033816, 032816, 02F816 = “0”) : fi / 16 (n + 1) (Note 1) : fi=f1, f8, f32
With an external clock chosen (bit 3 of addresses 033816, 032816, 02F816 = “1”) : fEXT / 16 (n+1) (Note 1) (Note 2) Transmission / reception control
Disable the CTS and RTS function (bit 4 of address 033C16, 032C16, 02FC16 = “1”) Other settings • The sleep mode select function is not available for UART2 and UART3
Set transmission interrupt factor to “transmission completed” (bit 4 of address 033D16, 032D 16, 02FD16 = “1”)
Set N-channel open drain output to TxD and RxD pins in UART3 and 4 (bit 5 of address 032C16, 02FC16 = “1”) Transmission start condition• To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 of address 033D16, 032D16, 02FD16) = “1” - Transmit buffer empty flag (bit 1 of address 033D16, 032D16, 02FD16) = “0” Reception start condition• To start reception, the following requirements must be met: - Reception enable bit (bit 2 of address 033D16, 032D16, 02FD16) = “1” - Detection of a start bit
When transmitting When data transmission from the UART2 to UART4 transfer register is completed (bit 4 of address 033D16, 032D16, 02FD16 = “1”)
When receiving When data transfer from the UART2 to UART4 receive register to the UART2 to UART4 receive buffer register is completed Error detection • Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 3)
Framing error (see the specifications of clock-asynchronous serial I/O)
Parity error (see the specifications of clock-asynchronous serial I/O) - On the reception side, an “L” level is output from the TxDi pin by use of the parity error signal output function (bit 7 of address 033D16, 032D16, 02FD16 = “1”) when a parity error is detected - On the transmission side, a parity error is detected by the level of input to the RxDi pin when a transmission interrupt occurs
The error sum flag (see the specifications of clock-asynchronous serial I/O) 19. Clock-asynchronous serial I/O mode (compliant with the SIM interface) The SIM interface is used for connecting the microcomputer with a memory card I/C or the like; adding some extra settings in UART2 to UART4 clock-asynchronous serial I/O mode allows the user to effect this function. Table 19.1 shows the specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface). Interrupt request generation timing Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: fEXT is input from the CLKi pin. Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit will not change. Table 19.1 Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 152 puorG08/C61M 19. Clock-asynchronous serial I/O mode (compliant with the SIM interface) Figure 19.1 Typical transmit/receive timing in UART mode (compliant with the SIM interface) D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST PSP D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST PSP D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SPSP D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SPSP Start bit Parity bit "0" "1" "0" "1" "0" "1" Cleared to "0" when interrupt request is accepted, or cleared by software Tc Transfer Clock Stop bit Data is set in the UARTi transmit buffer register An "L" level returns from SIM card due to the occurrence of a parity error The level is detected by the interrupt routine TxDi Transfer Clock Read to receive buffer TxDi Signal conductor level (Note 2) Note 1: After writing to the transfer buffer at above timing, transmission starts at the timing of BRG overflow. Note 2: Equal in waveform because TxDi and RxDi are connected. Transferred from the UARTi transmit buffer register to the UARTi transmit register (Note 1) Receive enable bit (RE) Transmit rnable bit (TE) Transmit enable empty flag (TI) Transmit register empty flag (TXEPT) Transmit interrupt request bit (IR) Shown in () are bit symbols. The above timing applies to the following settings :

Parity is enabled.
One stop bit
Transmit interrupt cause select bit = "1". Tc = 16 ( n + 1 ) / fi or 16 ( n + 1 ) / f EXT fi : frequency of BRGi rcount source (f1, f8, f32) fEXT : frequency of BRGi rcount source (external clock) n : value set to BRGi Start bit Stop bit Parity bit "1" "0" "0" "1" RxDi RxDi "1" SP The level is detected by the interrupt routine SP Tc Signal conductor level (Note 2) Transmit register empty flag (TXEPT) Transmit interrupt request bit (IR) An "L" level returns from TxDi due to the occurrence of a parity error Read to receive buffer Cleared to "0" when interrupt request is accepted, or cleared by software Shown in () are bit symbols. The above timing applies to the following settings :
Parity is enabled.
One stop bit
Transmit interrupt cause select bit = "0". Tc = 16 ( n + 1 ) / fi or 16 ( n + 1 ) / f EXT fi : frequency of BRGi rcount source (f1, f8, f32) fEXT : frequency of BRGi rcount source (external clock) n : value set to BRGi

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 155 20. UARTi Special Mode Register (i = 2 to 4)puorG08/C61M 20. UARTi Special Mode Register (i = 2 to 4) UART2 to UART4 operate the IIC bus interface (simple IIC bus) using the UARTi special mode register (addresses 033616, 032616 and 02F616 [i = 2 to 4]) and UARTi special mode register 2 (addresses 033616, 032616 and 02F616 [i = 2 to 4]). UART3 and UART4 add special functions using UARTi special mode resister 3 (addresses 032516 and 02F516 [i = 3 or 4]). (1) IIC Bus Interface Mode The I2C bus interface mode is provided with UART2 to UART4. Table 20.1 shows the construction of the UARTi special mode register and UARTi special mode register When the I 2C mode select bit (bit 0 in addresses 033716, 032716 and 02F716) is set to “1”, the I2C bus (simple I2C bus) interface circuit is enabled. To use the I2C bus, set the SCLi and the SDAi of both master and slave to output with the function select register. In UART3 and 4, set the data output select bit (bit 5 in address 032C16 and 02FC16) to N-channel open drain output. Table 20.1 shows the relationship of the IIC mode select bit to control. To use the chip in the clock synchronized serial I/O mode or clock asynchronized serial I/O mode, always set this bit to “0”. Function Normal mode I2C mode (Note 1) Factor of interrupt number 33, 35, 37 (Note 2) UARTi transmission No acknowledgment detection (NACK) Factor of interrupt number 34, 36, 38 (Note 2) UARTi reception Start condition detection or stop condition detection UARTi transmission output delay Not delayed Delayed P70, P92, P96 at the time when UARTi is in use TxDi (output) SDAi (input/output) (Note 3) P71, P91, P97 at the time when UARTi is in use RxDi (input) SCLi (input/output) P72, P90, P95 at the time when UARTi is in use CLKi P7 2, P90, P95 DMA1 factor at the time when 1 1 0 1 is assigned to the DMA request factor selection bits UARTi reception Acknowledgment detection (ACK) Noise filter width 15ns 50ns Reading P71, P91, P97 Reading the terminal when 0 is assigned to the direction register Reading the terminal regardless of the value of the direction register Note 1: Make the settings given below when I2C mode is in use. Set 0 1 0 in bits 2, 1, 0 of the UARTi transmission/reception mode register. Disable the RTS/CTS function. Choose the MSB First function. Note 2: Follow the steps given below to switch from a factor to another. 1. Disable the interrupt of the corresponding number. 2. Switch from a factor to another. 3. Reset the interrupt request flag of the corresponding number. 4. Set an interrupt level of the corresponding number. Note 3: Set an initial value of SDA transmission output when IIC mode (IIC mode select bit = "1") is valid and serial I/O is invalid. Factor of interrupt number 39 to 41 (Note 2)Bus collision detection Acknowledgment detection (ACK) Initial value of UARTi output H level (when 0 is assigned to the CLK polarity select bit) The value set in latch P7 0, P92, P96 when the port is selected (Note 3) Table 20.1 Features in I2C mode

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 156 20. UARTi Special Mode Register (i = 2 to 4)puorG08/C61M UARTi special mode register b7 b6 b5 b4 b3 b2 b1 b0 Bit name Bit symbol WRFunction (During UART mode) Function (During clock synchronous serial I/O mode) ABSCS ACSE SSS I C mode select bit Bus busy flag 0 : STOP condition detected 1 : START condition detected SCLL sync output enable bit Bus collision detect sampling clock select bit Arbitration lost detecting flag control bit 0 : Normal mode 1 : I C mode 0 : Update per bit 1 : Update per byte IICM ABC BBS LSYN 0 : Ordinary 1 : Falling edge of RxDi 0 : Disabled 1 : Enabled Transmit start condition select bit Set to “0” 0 : Rising edge of transfer clock 1 : Underflow signal of timer Ai Auto clear function select bit of transmit enable bit /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 0 : No auto clear function 1 : Auto clear at occurrence of bus collision Set to “0” Set to “0” Set to “0” Set to “0” Set to “0” Set to “0” Nothing is assigned. When write, set "0". When read, the content is "0". Note 1: Nothing but "0" may be written. Note 2: UART2 : timer A0 underflow signal, UART3 : timer A3 underflow signal, UART4 : timer A4 underflow signal. (Note 1) (Note 2) Symbol Address When reset UiSMR (i=2 to 4) 0337 16, 032716, 02F716 0016 UARTi special mode register 2 Symbol Address When reset UiSMR2 (i=2 to 4) 0336 16, 032616, 02F616 0016 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol WRFunction IICM2 CSC SWC ALS IIC mode select bit 2 SCL wait output bit SDA output stop flag Clock synchronous bit Refer to Table 20.2 0 : Disabled 1 : Enabled STC UARTi initialize bit SWC2 SCL wait output bit 2 SDA output inhibit bitSDHI SHTC Start/stop condition control bit /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : UARTi clock 1 : 0 output 0 : Enabled 1 : Disabled (high impedance) Set to "1" in selecting IIC mode. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Figure 20.1 UART2 special mode register

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 158 20. UARTi Special Mode Register (i = 2 to 4)puorG08/C61M The start condition detection interrupt is generated when the fall at the SDA2 pin (P70) is detected while the SCL2 pin (P71) is in the H state. The stop condition detection interrupt is generated when the rise at the SDA2 pin (P70) is detected while the SCL2 pin (P71) is in the H state. The acknowledge non-detection interrupt is generated when the H level at the SDA2 pin is detected at the 9th rise of the transmission clock. The acknowledge detection interrupt is generated when the L level at the SDA2 pin is detected at the 9th rise of the transmission clock. Also, DMA transfer can be started when the acknowledge is de- tected if UART2 transmission is selected as the DMAi request factor. Bit 2 is the bus busy flag. It is set to “1” when the start condition is detected, and reset to “0” when the stop condition is detected. Bit 1 is the arbitration lost detection flag control bit. Arbitration detects a conflict between data trans- mitted at SCL2 rise and data at the SDA2 pin. This detection flag is allocated to bit 11 in UART2 transmission buffer register (address 033E 16). It is set to “1” when a conflict is detected. With the arbitration lost detection flag control bit, it can be selected to update the flag in units of bits or bytes. When this bit is set to “1”, update is set to units of byte. If a conflict is then detected, the arbitration lost detection flag control bit will be set to “1” at the 9th rise of the clock. When updating in units of byte, always clear (“0” interrupt) the arbitration lost detection flag control bit after the 1st byte has been acknowledged but before the next byte starts transmitting. Bit 3 is the SCL2 L synchronization output enable bit. When this bit is set to “1”, the P71 data register is set to “0” in sync with the L level at the SCL2 pin. Bit 4 is the bus collision detection sampling clock select bit. The bus collision detection interrupt is generated when RxDi and TxDi level do not conflict with one another. When this bit is “0”, a conflict is detected in sync with the rise of the transfer clock. When this bit is “1”, detection is made when timer Ai (timer A0 with UART2, timer A3 with UART3 and timer A4 with UART4) underflows. Operation is shown in Figure 20.3. Bit 5 is the transmission enable bit automatic clear select bit. By setting this bit to “1”, the transmission bit is automatically reset to “0” when the bus collision detection interrupt factor bit is “1” (when a conflict is detected). Bit 6 is the transmission start condition select bit. By setting this bit to “1”, TxDi transmission starts in sync with the falling at the RxDi pin.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 159 20. UARTi Special Mode Register (i = 2 to 4)puorG08/C61M 1. Bus collision detect sampling clock select bit (Bit 4 of the UARTi special mode register) 0: Rising edges of the transfer clock CLKi Timer Ai 1: Timer A0 underflow 2. Auto clear function select bit of transmit enable bit (Bit 5 of the UARTi special mode register) CLKi TxDi/RxDi Bus collision detect interrupt request bit Transmit enable bit 3. Transmit start condition select bit (Bit 6 of the UARTi special mode register) CLKi TxDi Enabling transmission CLKi TxDi RxDi With "1: falling edge of RxDi" selected 0: In normal state TxDi/RxDi Figure 20.3 Some other functions added

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 160 20. UARTi Special Mode Register (i = 2 to 4)puorG08/C61M UARTi Special Mode Register 2(i=2 to 4) (Address 033616,032616,02F616) Bit 0 is the IIC mode select bit 2. Table 20.2 gives control changes by bit when the IIC mode select bit is “1”. Start and stop condition detection timing characteristics are shown in Figure 20.4. Always set bit 7 (start/stop condition control bit) to “1”. Bit 1 is the clock synchronization bit. When this bit is set to “1”, if the rise edge is detected at pin SCLi while the internal SCL is H level, the internal SCL is changed to L level, the UARTi bit rate generator value is reloaded and the L sector count starts. Also, while the SCLi pin is L level, if the internal SCL changes from L level to H, the count stops. If the SCLi pin is H level, counting restarts. Because of this function, the UARTi transmission-reception clock takes the AND condition for the internal SCL and SCLi pin signals. This function operates from the clock half period before the 1st rise of the UARTi clock to the 9th rise. To use this function, select the internal clock as the transfer clock. Bit 2 is the SCL wait output bit. When this bit is set to “1”, output from the SCLi pin is fixed to L level at the clock’s 9th rise. When set to “0”, the L output lock is released. Bit 3 is the SDA output stop bit. When this bit is set to “1”, an arbitration lost is generated. If the arbitration lost detection flag is “1”, the SDAi pin simultaneously becomes high impedance. Bit 4 is the UARTi initialize bit. While this bit is set to “1”, the following operations are performed when the start condition is detected. 1. The transmission shift register is initialized and the content of the transmission register is trans- mitted to the transmission shift register. As such, transmission starts with the 1st bit of the next input clock. However, the UARTi output value remains the same as when the start condition was detected, without changing from when the clock is input to when the 1st bit of data is output. 2. The reception shift register is initialized and reception starts with the 1st bit of the next input clock. 3. The SCL wait output bit is set to “1”. As such, the SCLi pin becomes L level at the rise of the 9th bit of the clock. When UART transmission-reception has been started using this function, the content of the transmis- sion buffer available flag does not change. Also, to use this function, select an external clock as the transfer clock. Bit 5 is SCL wait output bit 2. When this bit is set to “1” and serial I/O has been selected, an L level can be forcefully output from the SCLi pin even during UART operation. When this bit is set to “0', the L output from the SCLi pin is canceled and the UARTi clock is input and output. Bit 6 is the SDA output disable bit. When this bit is set to “1”, the SDAi pin is forcefully made high impedance. To overwrite this bit, do so at the rise of the UARTi transfer clock. The arbitration lost detection flag may be set.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 161 20. UARTi Special Mode Register (i = 2 to 4)puorG08/C61M Table 20.2 Functions changed by I2C mode select bit 2 IICM2 = 0 Acknowrege not detect (NACK) Acknowrege detect (ACK) Acknowrege detect (ACK) Rising edge of the last bit of re- ceive clock Rising edge of the last bit of re- ceive clock Function Interrupt no. 33, 35, 37 factor Interrupt no. 34, 36, 38 factor DMA factor Data transfer timing from UARTi (i = 2 to 4) receive shift register to re- ceive buffer UARTi(i = 2 to 4) receive / ACK in- terrupt request generation timing IICM2 = 1 UART2 transfer (rising edge of ) Acknowrege detect (ACK) Acknowrege detect (ACK) Rising edge of the last bit of re- ceive clock Rising edge of the last bit of re- ceive clock Set up time Hold time SCL SDA (Start condition) SDA (Stop condition) Figure 20.4 Start/stop condition detect timing characteristics 3 to 6 cycles < set up time (Note) 3 to 6 cycles < hold time (Note) Note : Cycle number shows main clock input oscillation frequency f(XIN) cycle number. UARTi Special Mode Register 3(i=2 to 4 )(Address 033516,032516,02F516) Bits 5 to 7 are the SDAi digital delay setting bits. By setting these bits, it is possible to turn the SDAi delay OFF or set the f(X IN) delay to 2 to 8 cycles.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 162 20. UARTi Special Mode Register (i = 2 to 4)puorG08/C61M P13 P12 IC1 P93(SS 3) P92(TxD 3) P90(CLK 3) P91(RxD 3) IC2 P93(SS 3) P92(SRxD 3) P90(CLK 3) P91(STxD 3) IC3 P93(SS 3) P92(SRxD 3) P90(CLK 3) P91(STxD 3) M16C/80 (M) M16C/80 (S) M16C/80 (S) M :Master S :Slave (2) Serial Interface Special Function UART 3 and UART4 can control communications on the serial bus using the SSi input pins (Figure 20.5). The master outputting the transfer clock transfers data to the slave inputting the transfer clock. In this case, in order to prevent a data collision on the bus, the master floats the output pin of other slaves/ masters using the SSi input pins. Figure 20.6 shows the structure of UARTi special mode register 3 (addresses 0325 16 and 02F516 [i = 3 or 4]) which controls this mode. SSi input pins function between the master and slave are as follows. Figure 20.5 Serial bus communication control example using the SSi input pins < Slave Mode (STxDi and SRxDi are selected, DINC = 1) > When an H level signal is input to an SSi input pin, the STxDi and SRxDi pins both become high impedance, hence clock input is ignored. When an "L" level signal is input to an SSi input pin, clock input becomes effective and serial communications are enabled. (i = 3 or 4) < Master Mode (TxDi and RxDi are selected, DINC = 0) > The SSi input pins are used with a multiple master system. When an SSi input pin is H level, transmis- sion has priority and serial communications are enabled. When an L signal is input to an SSi input pin, another master exists, and the TxDi, RxDi and CLKi pins all become high impedance. Moreover, the trouble error interrupt request bit becomes “1”. Communications do not stop even when a trouble error is generated during communications. To stop communications, set bits 0, 1 and 2 of the UARTi trans- mission-reception mode register (address 0328 16 and 02F816 [i = 3 or 4]) to “0”. The trouble error interrupt is used by both the bus collision interrupt and start/stop condition detection interrupts, but the trouble error interrupt itself can be selected by setting bit 0 of UARTi special mode register 3 (address 0325 16 and 02F516 [i = 3 or 4]) to “1”. When the trouble error flag is set to “0”, output is restored to the clock output and data output pins. In the master mode, if an SSi input pin is H level, “0” can be written for the trouble error flag. When an SSi input pin is L level, “0” cannot be written for the trouble error flag. In the slave mode, the “0” can be written for the trouble error flag regardless of the input to the SSi input pins.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 163 20. UARTi Special Mode Register (i = 2 to 4)puorG08/C61M Symbol Address When reset U3SMR3 0325 16 000000002 U4SMR3 02F5 16 000000002 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 SSE SS port function enable bit0: SS function disable 1: SS function enable 0: Without fault error 1: With fault error CKPH DINC NODC ERR Clock phase set bit Serial input port set bit Clock output select bit 0: Select TxDi and RxDi (master mode) (Note 5) 1: Select STxDi and SRxDi (slave mode) (Note 6) 0: CLKi is CMOS output 1: CLKi is N-channel open drain output Fault error flag (Note 3) (Note 4) 0: Without clock delay 1: With clock delay UARTi special mode register 3 (i=3,4) 000 :Without delay 001 :1 to 2 cycles of 1/f(XIN) 010 :2 to 3 cycles of 1/f(XIN) 011 :3 to 4 cycles of 1/f(XIN) 100 :4 to 5 cycles of 1/f(XIN) 101 :5 to 6 cycles of 1/f(XIN) 110 :6 to 7 cycles of 1/f(XIN) 111 :7 to 8 cycles of 1/f(XIN) SDAi(TxD2) digital delay time set bit (Note 1,2) DL0 DL1 DL2 Note 1: These bits are used for SDAi(TxDi) output digital delay when using UARTi for IIC interface. Otherwise, must set to "000". Note 2: When external clock is selected, delay is increased approx. 100ns. Note 3: Set SS function after setting CTS/RTS disable bit (bit 4 of UARTi transfer/receive control register 0) to "1". Note 4: Nothing but "0" may be written. Note 5: Set CLKi and TxDi both for output using the CLKi and TxDi function select register A. Set the RxDi function select register A for input/output port and the port direction register to "0". Note 6: Set STxDi for output using the STxDi function select registers A and B. Set the CLKi and SRxDi function select register A for input/output port and the port direction register to "0". b7 b6 b5 Figure 20.6 UARTi special mode register 3 (i=3,4)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 166 21. A/D ConverterpuorG08/C61M Item Performance Method of A/D conversion Successive approximation (capacitive coupling amplifier) Analog input voltage (Note 1)0V to AVCC (VCC ) Operating clock fAD (Note 2) VCC = 5V f AD , fAD /2, fAD /4 fAD =f(XIN) VCC = 3V f AD /2, fAD /4 fAD =f(XIN) Resolution 8-bit or 10-bit (selectable) Absolute precision V CC = 5V

8-bit resolution ±2LSB
10-bit resolution ±3LSB However, when using AN0 to AN7 in the mode which external operation amp is connected : ±7LSB VCC = 3V
Without sample and hold function (8-bit resolution) ±2LSB Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 Analog input pins 8 pins (AN 0 to AN7) + 2 pins (ANEX0 and ANEX1) A/D conversion start condition• Software trigger A/D conversion starts when the A/D conversion start flag changes to “1”
External trigger (can be retriggered) A/D conversion starts when the A/D conversion start flag is “1” and the AD TRG /P97 input changes from “H ” to “L” Conversion speed per pin• Without sample and hold function 8-bit resolution: 49 fAD cycles, 10-bit resolution: 59 fAD cycles
With sample and hold function 8-bit resolution: 28 fAD cycles, 10-bit resolution: 33 fAD cycles 21. A/D Converter The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling amplifier. Pins P100 to P107, P95, and P96 also function as the analog signal input pins. The direction registers of these pins for A/D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 0397 16) can be used to isolate the resistance ladder of the A/D converter from the reference voltage input pin (VREF ) when the A/D converter is not used. Doing so stops any current flowing into the resistance ladder from VREF , reducing the power dissipation. When using the A/D converter, start A/D conversion only after setting bit 5 of 039716 to connect VREF . The result of A/D conversion is stored in the A/D registers of the selected pins. When set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses. Table 21.1 shows the performance of the A/D converter. Figure 21.1 shows the block diagram of the A/D converter, and Figures 21.2 and 21.3 show the A/D converter-related registers. Note 1: Does not depend on use of sample and hold function. Note 2: When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing. Without sample and hold function, set the fAD frequency to 250kHz min. With the sample and hold function, set the fAD frequency to 1MHz min. Table 21.1 Performance of A/D converter

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 167 21. A/D ConverterpuorG08/C61M Figure 21.1 Block diagram of A/D converter φAD fAD A/D conversion rate selection (038116, 038016) (038316, 038216) (038516, 038416) (038716, 038616) (038916, 038816) (038B16, 038A16) (038D16, 038C16) (038F16, 038E16) CKS1=1 CKS0=0 0 0 : Normal operation 0 1 : ANEX0 1 0 : ANEX1 1 1 : External op-amp mode A/D register 0(16) A/D register 1(16) A/D register 2(16) A/D register 3(16) A/D register 4(16) A/D register 5(16) A/D register 6(16) A/D register 7(16) Resistance ladder ANEX1 ANEX0 Successive conversion register OPA1,OPA0=0,1 OPA0=1 OPA1=1 OPA1,OPA0=1,1 AN 0 AN 1 AN 2 AN 3 AN 5 AN 6 AN 7 A/D control register 0 (address 039616) A/D control register 1 (address 039716) Vref VIN Data bus high-order Data bus low-order V REF AN 4 OPA1,OPA0=0,0 VCUT=0 AV SS VCUT=1 CKS0=1 CKS1=0 CH2,CH1,CH0=000 CH2,CH1,CH0=001 CH2,CH1,CH0=010 CH2,CH1,CH0=011 CH2,CH1,CH0=100 CH2,CH1,CH0=101 CH2,CH1,CH0=110 CH2,CH1,CH0=111 Decoder Comparator OPA1, OPA0 Addresses

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 168 21. A/D ConverterpuorG08/C61M Figure 21.2 A/D converter-related registers (1) A/D control register 0 (Note 1) Symbol Address When reset ADCON0 0396 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bit0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected (Note 2) CH0 Bit symbol Bit name Function CH1 CH2 A/D operation mode select bit 0 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 (Note 2) Repeat sweep mode 1 MD0 MD1 Trigger select bit 0 : Software trigger 1 : ADTRG triggerTRG ADST A/D conversion start flag 0 : A/D conversion disabled 1 : A/D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selectedCKS0 WR A/D control register 1 (Note 1) Symbol Address When reset ADCON1 0397 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 A/D sweep pin select bitSCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT OPA0 Vref connect bit OPA1 A/D operation mode select bit 1 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 0 : Vref not connected 1 : Vref connected External op-amp connection mode bit WR b2 b1 b0 b4 b3 When single sweep and repeat sweep mode 0 are selected 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) b1 b0 When repeat sweep mode 1 is selected 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) b1 b0 0 0 : ANEX0 and ANEX1 are not used(Note 3) 0 1 : ANEX0 input is A/D converted(Note 4) 1 0 : ANEX1 input is A/D converted(Note 5) 1 1 : External op-amp connection mode(Note 6) b7 b6 Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. Note 2: When changing A/D operation mode, set analog input pin again. Frequency select bit 1 (Note 2) 0 : f AD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. Note 2: When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing. Note 3: Set "0" to PSL3_5 and PSL3_6 of the function select register B3. Note 4: Set "1" to PSL3_5 of the function select register B3. Note 5: Set "1" to PSL3_6 of the function select register B3. Note 6: Set "1" to PSL3_5 and PSL3_6 of the function select register B3. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 169 21. A/D ConverterpuorG08/C61M Figure 21.3 A/D converter-related registers (2) A/D control register 2 (Note) Symbol Address When reset ADCON2 0394 16 XXXXXXX0 2 b7 b6 b5 b4 b3 b2 b1 b0 A/D conversion method select bit 0 : Without sample and hold 1 : With sample and hold Bit symbol Bit name Function R W Note: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Nothing is assigned. When write, set "0". When read, their content is "0". A/D register i Symbol Address When reset ADi(i=0 to 7) 038016 to 038F16 Indeterminate Eight low-order bits of A/D conversion result Function R W (b15) b7b7 b0 b0 (b8)

During 10-bit mode Two high-order bits of A/D conversion result Nothing is assigned. When write, set "0". When read, their content is "0".
During 8-bit mode When read, the content is indeterminate /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines SMP Reserved bit Must always set to “0” /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines 000

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 170 21. A/D ConverterpuorG08/C61M (1) One-shot mode In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A/D conver- sion. Table 21.2 shows the specifications of one-shot mode. Figure 21.4 shows the A/D control register in one-shot mode. Table 21.2 One-shot mode specifications A/D control register 0 (Note 1) Symbol Address When reset ADCON0 0396 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bit Bit symbol Bit name Function CH1 CH2 A/D operation mode select bit 0 MD0 MD1 Trigger select bit 0 : Software trigger 1 : ADTRG triggerTRG ADST A/D conversion start flag 0 : A/D conversion disabled 1 : A/D conversion started Frequency select bit 00: fAD /4 is selected 1: fAD /2 is selected CKS0 WR A/D control register 1 (Note) Symbol Address When reset ADCON1 0397 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 A/D sweep pin select bitSCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT OPA0 Vref connect bit OPA1 A/D operation mode select bit 1 0 : Any mode other than repeat sweep mode 1 1 : Vref connected External op-amp connection mode bit WR Invalid in one-shot mode 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected (Note 2) b2 b1 b0 0 0 : One-shot mode (Note 2) b4 b3 CH0 b7 b6 Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. Note 2: When changing A/D operation mode, set analog input pin again. 0 : fAD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Frequency select bit 1 (Note 2) 0 0 : ANEX0 and ANEX1 are not used(Note 3) 0 1 : ANEX0 input is A/D converted(Note 4) 1 0 : ANEX1 input is A/D converted(Note 5) 1 1 : External op-amp connection mode(Note 6) Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. Note 2: When f(X IN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing. Note 3: Set "0" to PSL3_5 and PSL3_6 of the function select register B3. Note 4: Set "1" to PSL3_5 of the function select register B3. Note 5: Set "1" to PSL3_6 of the function select register B3. Note 6: Set "1" to PSL3_5 and PSL3_6 of the function select register B3. Item Specification Function The pin selected by the analog input pin select bit is used for one A/D conversion Start condition Writing “1” to A/D conversion start flag Stop condition •End of A/D conversion (A/D conversion start flag changes to “0”, except when external trigger is selected)

Writing “0” to A/D conversion start flag Interrupt request generation timingEnd of A/D conversion Input pin One of AN 0 to AN7, as selected Reading of result of A/D converterRead A/D register corresponding to selected pin Figure 21.4 A/D conversion register in one-shot mode

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 171 21. A/D ConverterpuorG08/C61M (2) Repeat mode In repeat mode, the pin selected using the analog input pin select bit is used for repeated A/D conversion. Table 21.3 shows the specifications of repeat mode. Figure 21.5 shows the A/D control register in repeat mode. A/D control register 0 (Note 1) Symbol Address When reset ADCON0 0396 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bitCH0 Bit symbol Bit name Function CH1 CH2 A/D operation mode select bit 0 MD0 MD1 Trigger select bit 0 : Software trigger 1 : ADTRG triggerTRG ADST A/D conversion start flag 0 : A/D conversion disabled 1 : A/D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selectedCKS0 WR A/D control register 1 (Note) Symbol Address When reset ADCON1 0397 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 A/D sweep pin select bit SCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT OPA0 Vref connect bit OPA1 A/D operation mode select bit 1 1 : Vref connected External op-amp connection mode bit WR Invalid in repeat mode 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected (Note 2) b2 b1 b0 0 1 : Repeat mode (Note 2) b4 b3 b7 b6 0 : fAD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 0 : Any mode other than repeat sweep mode 1 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Frequency select bit 1 (Note 2) 0 0 : ANEX0 and ANEX1 are not used(Note 3) 0 1 : ANEX0 input is A/D converted(Note 4) 1 0 : ANEX1 input is A/D converted(Note 5) 1 1 : External op-amp connection mode(Note 6) Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. Note 2: When f(X IN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing. Note 3: Set "0" to PSL3_5 and PSL3_6 of the function select register B3. Note 4: Set "1" to PSL3_5 of the function select register B3. Note 5: Set "1" to PSL3_6 of the function select register B3. Note 6: Set "1" to PSL3_5 and PSL3_6 of the function select register B3. Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. Note 2: When changing A/D operation mode, set analog input pin again. Figure 21.5 A/D conversion register in repeat mode Item Specification Function The pin selected by the analog input pin select bit is used for repeated A/D conversion Star condition Writing “1” to A/D conversion start flag Stop condition Writing “0” to A/D conversion start flag Interrupt request generation timingNone generated Input pin One of AN 0 to AN7, as selected Reading of result of A/D converterRead A/D register corresponding to selected pin (at any time) Table 21.3 Repeat mode specifications

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 172 21. A/D ConverterpuorG08/C61M (3) Single sweep mode In single sweep mode, the pins selected using the A/D sweep pin select bit are used for one-by-one A/D conversion. Table 21.4 shows the specifications of single sweep mode. Figure 21.6 shows the A/D con- trol register in single sweep mode. Table 21.4 Single sweep mode specifications Figure 21.6 A/D conversion register in single sweep mode A/D control register 0 (Note) Symbol Address When reset ADCON0 0396 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bit CH0 Bit symbol Bit name Function CH1 CH2 A/D operation mode select bit 0 1 0 : Single sweep modeMD0 MD1 Trigger select bit 0 : Software trigger 1 : ADTRG trigger TRG ADST A/D conversion start flag 0 : A/D conversion disabled 1 : A/D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selected CKS0 WR A/D control register 1 (Note 1) Symbol Address When reset ADCON1 0397 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 A/D sweep pin select bitSCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT OPA0 Vref connect bit 0 : Any mode other than repeat sweep mode 1 OPA1 A/D operation mode select bit 1 1 : Vref connected External op-amp connection mode bit (Note 2) WR 1 0 Invalid in single sweep mode Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. Note 2: Neither ‘01’ nor ‘10’ can be selected with the external op-amp connection mode bit. Note 3: When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing. Note 4: Set "0" to PSL3_5 and PSL3_6 of the function select register B3. Note 5: Set "1" to PSL3_5 of the function select register B3. Note 6: Set "1" to PSL3_6 of the function select register B3. Note 7: Set "1" to PSL3_5 and PSL3_6 of the function select re gister B3. b4 b3 When single sweep and repeat sweep mode 0 are selected 0 0 : AN 0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) b1 b0 b7 b6 Note: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. 0 : fAD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Frequency select bit 1 (Note 3) 0 0 : ANEX0 and ANEX1 are not used(Note 4) 0 1 : ANEX0 input is A/D converted(Note 5) 1 0 : ANEX1 input is A/D converted(Note 6) 1 1 : External op-amp connection mode(Note 7) Item Specification Function The pins selected by the A/D sweep pin select bit are used for one-by-one A/D conversion Start condition Writing “1” to A/D converter start flag Stop condition •End of A/D conversion (A/D conversion start flag changes to “0”, except when external trigger is selected)

Writing “0” to A/D conversion start flag Interrupt request generation timingEnd of A/D conversion Input pin AN 0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Reading of result of A/D converterRead A/D register corresponding to selected pin

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 173 21. A/D ConverterpuorG08/C61M (4) Repeat sweep mode 0 In repeat sweep mode 0, the pins selected using the A/D sweep pin select bit are used for repeat sweep A/D conversion. Table 21.5 shows the specifications of repeat sweep mode 0. Figure 21.7 shows the A/ D control register in repeat sweep mode 0. Figure 21.7 A/D conversion register in repeat sweep mode 0 A/D control register 0 (Note) Symbol Address When reset ADCON0 0396 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bit CH0 Bit symbol Bit name Function CH1 CH2 A/D operation mode select bit 0 1 1 : Repeat sweep mode 0MD0 MD1 Trigger select bit 0 : Software trigger 1 : ADTRG trigger TRG ADST A/D conversion start flag 0 : A/D conversion disabled 1 : A/D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selectedCKS0 WR A/D control register 1 (Note 1) Symbol Address When reset ADCON1 0397 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 A/D sweep pin select bitSCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit0 : 8-bit mode 1 : 10-bit mode VCUT OPA0 Vref connect bit 0 : Any mode other than repeat sweep mode 1 OPA1 A/D operation mode select bit 1 1 : Vref connected External op-amp connection mode bit (Note 2) WR 1 1 Invalid in repeat sweep mode 0 b4 b3 When single sweep and repeat sweep mode 0 are selected 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) b1 b0 b7 b6 0 : fAD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Frequency select bit 1 (Note 3) Note: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. Note 2: Neither ‘01’ nor ‘10’ can be selected with the external op-amp connection mode bit. Note 3: When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing. Note 4: Set "0" to PSL3_5 and PSL3_6 of the function select register B3. Note 5: Set "1" to PSL3_5 of the function select register B3. Note 6: Set "1" to PSL3_6 of the function select register B3. Note 7: Set "1" to PSL3_5 and PSL3_6 of the function select re gister B3. 0 0 : ANEX0 and ANEX1 are not used(Note 4) 0 1 : ANEX0 input is A/D converted(Note 5) 1 0 : ANEX1 input is A/D converted(Note 6) 1 1 : External op-amp connection mode(Note 7) Item Specification Function The pins selected by the A/D sweep pin select bit are used for repeat sweep A/D conversion Start condition Writing “1” to A/D conversion start flag Stop condition Writing “0” to A/D conversion start flag Interrupt request generation timingNone generated Input pin AN 0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Reading of result of A/D converterRead A/D register corresponding to selected pin (at any time) Table 21.5 Repeat sweep mode 0 specifications

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 174 21. A/D ConverterpuorG08/C61M Item Specification Function All pins perform repeat sweep A/D conversion, with emphasis on the pin or pins selected by the A/D sweep pin select bit Example : AN0 selected AN0 AN1 AN0 AN2 AN0 AN3, etc Start condition Writing “1” to A/D conversion start flag Stop condition Writing “0” to A/D conversion start flag Interrupt request generation timingNone generated Input pin AN 0 to AN7 With emphasis on the pin AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins) Reading of result of A/D converterRead A/D register corresponding to selected pin (at any time) (5) Repeat sweep mode 1 In repeat sweep mode 1, all pins are used for A/D conversion with emphasis on the pin or pins selected using the A/D sweep pin select bit. Table 21.6 shows the specifications of repeat sweep mode 1. Figure 21.8 shows the A/D control register in repeat sweep mode 1. A/D control register 0 (Note) Symbol Address When reset ADCON0 0396 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bit CH0 Bit symbol Bit name Function CH1 CH2 A/D operation mode select bit 0 1 1 : Repeat sweep mode 1MD0 MD1 Trigger select bit 0 : Software trigger 1 : ADTRG trigger TRG ADST A/D conversion start flag 0 : A/D conversion disabled 1 : A/D conversion started Frequency select bit 00 : fAD /4 is selected 1 : fAD /2 is selectedCKS0 WR A/D control register 1 (Note 1) Symbol Address When reset ADCON1 0397 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 A/D sweep pin select bitSCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT OPA0 Vref connect bit 1 : Repeat sweep mode 1 OPA1 A/D operation mode select bit 1 1 : Vref connected External op-amp connection mode bit (Note 2) WR 1 1 Invalid in repeat sweep mode 1 b4 b3 When repeat sweep mode 1 is selected 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) b1 b0 b7 b6 Note: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. 0 : fAD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Frequency select bit 1 (Note 3) Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. Note 2: Neither ‘01’ nor ‘10’ can be selected with the external op-amp connection mode bit. Note 3: When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing. Note 4: Set "0" to PSL3_5 and PSL3_6 of the function select register B3. Note 5: Set "1" to PSL3_5 of the function select register B3. Note 6: Set "1" to PSL3_6 of the function select register B3. Note 7: Set "1" to PSL3_5 and PSL3_6 of the function select register B3. 0 0 : ANEX0 and ANEX1 are not used(Note 4) 0 1 : ANEX0 input is A/D converted(Note 5) 1 0 : ANEX1 input is A/D converted(Note 6) 1 1 : External op-amp connection mode(Note 7) Figure 21.8 A/D conversion register in repeat sweep mode 1 Table 21.6 Repeat sweep mode 1 specifications

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 175 21. A/D ConverterpuorG08/C61M (a) Sample and hold Sample and hold is selected by setting bit 0 of the A/D control register 2 (address 039416) to “1”. When sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 fAD cycle is achieved with 8-bit resolution and 33 fAD with 10-bit resolution. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before starting A/D conversion whether sample and hold is to be used. (b) Extended analog input pins In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can also be converted from analog to digital. When bit 6 of the A/D control register 1 (address 0397 16) is “1” and bit 7 is “0”, input via ANEX0 is converted from analog to digital. The result of conversion is stored in A/D register 0. When bit 6 of the A/D control register 1 (address 0397 16) is “0” and bit 7 is “1”, input via ANEX1 is converted from analog to digital. The result of conversion is stored in A/D register 1. Set the related input peripheral function of the function select register B3 to disabled. (c) External operation amp connection mode In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1, can be amplified together by just one operation amp and used as the input for A/D conversion. When bit 6 of the A/D control register 1 (address 0397 16) is “1” and bit 7 is “1”, input via AN0 to AN7 is output from ANEX0. The input from ANEX1 is converted from analog to digital and the result stored in the corresponding A/D register. The speed of A/D conversion depends on the response of the external op- eration amp. Do not connect the ANEX 0 and ANEX1 pins directly. Figure 21.9 is an example of how to connect the pins in external operation amp mode. Set the related input peripheral function of the function select register B3 to disabled. Analog input External op-amp AN 0 AN 7 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 ANEX1 ANEX0 Resistance ladder Successive conversion register Comparator Figure 21.9 Example of external op-amp connection mode

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 176 22. D/A ConverterpuorG08/C61M 22. D/A Converter This is an 8-bit, R-2R type D/A converter. The microcomputer contains two independent D/A converters of this type. D/A conversion is performed when a value is written to the corresponding D/A register. Bits 0 and 1 (D/A output enable bits) of the D/A control register decide if the result of conversion is to be output. Set the function select register A3 to I/O port, the related input peripheral function of the function select register B3 to disabled and the direction register to input mode. When the D/A output is enabled, the pull-up function of the corresponding port is automatically disabled. Output analog voltage (V) is determined by a set value (n : decimal) in the D/A register. V = V REF X n/ 256 (n = 0 to 255) VREF : reference voltage Table 22.1 lists the performance of the D/A converter. Figure 22.1 shows the block diagram of the D/A converter. Figure 22.2 shows the D/A control register. Item Performance Conversion method R-2R method Resolution 8 bits Analog output pin 2 channels Table 22.1 Performance of D/A converter D/A register i (8) (i = 0, 1) R-2R resistance ladder (Address 039816, 039A16) D/Ai output enable bit (i = 0, 1) /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines P93 / DA0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines P94 / DA1 Data bus low-order bits Figure 22.1 Block diagram of D/A converter

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 178 23. CRC Calculation CircuitpuorG08/C61M 23. CRC Calculation Circuit The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcom- puter uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code. The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC code is set in a CRC data register each time one byte of data is transferred to a CRC input register after writing an initial value into the CRC data register. Generation of CRC code for one byte of data is com- pleted in two machine cycles. Figure 23.1 shows the block diagram of the CRC circuit. Figure 23.2 shows the CRC-related registers. Figure 23.2 CRC-related registers Symbol Address When reset CRCD 037D 16, 037C16 Indeterminate b7 b0 b7 b0 (b15) (b8) CRC data register WR CRC calculation result output register Function Values that can be set 000016 to FFFF16 Symbo Address When reset CRCIN 037E /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Eight low-order bits /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Eight high-order bits Data bus high-order bits Data bus low-order bits /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines CRC data register (16) CRC input register (8) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines CRC code generating circuit x16 + x12 + x5 + 1 (Addresses 037D16, 037C16) (Address 037E16) Figure 23.1 Block diagram of CRC circuit

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 179 23. CRC Calculation CircuitpuorG08/C61M b15 b0 (1) Setting 000016 CRC data register CRCD [037D16, 037C16] b0b7 b15 b0 (2) Setting 0116 CRC input register CRCIN [037E16] 2 cycles After CRC calculation is complete CRC data register CRCD [037D16, 037C16] 118916 Stores CRC code b0b7 b15 b0 (3) Setting 2316 CRC input register CRCIN [037E16] After CRC calculation is complete CRC data register CRCD [037D16, 037C16]0A4116 Stores CRC code The code resulting from sending 0116 in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial, (X16 + X12 + X5 + 1), becomes the remainder resulting from dividing (1000 0000) X16 by (1 0001 0000 0010 0001) in conformity with the modulo-2 operation. Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000) corresponds to 118916 in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC operation. Also switch between the MSB and LSB of the result as stored in CRC data. 1 0001 0000 0010 00011000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 1000 1000 LSB MSB LSB MSB 98 1 1 Modulo-2 operation is operation that complies with the law given below. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 -1 = 1 Figure 23.3 CRC example

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 180 24. XY ConverterpuorG08/C61M 24. XY Converter XY conversion rotates the 16 x 16 matrix data by 90 degrees. It can also be used to invert the top and bottom of the 16-bit data. Figure 24.1 shows the XY control register. The Xi and the Yi registers are 16-bit registers. There are 16 of each (where i= 0 to 15). The Xi and Yi registers are mapped to the same address. The Xi register is a write-only register, while the Yi register is a read-only register. Be sure to access the Xi and Yi registers in 16-bit units from an even address. Operation cannot be guaranteed if you attempt to access these registers in 8-bit units. Figure 24.1 XY control register XY control register Symbol Address When reset XYC 02E0 16 XXXXXX00 2 b7 b6 b5 b4 b3 b2 b1 b0 Read-mode set bit XYC0 Bit symbol Bit name Function R W 0 : Data conversion 1 : No data conversion Write-mode set bit 0 : No bit mapping conversion 1 : Bit mapping conversion XYC1 Nothing is assigned. When write, set "0". When read, the value of these bits is indeterminate. /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 183 25. DRAM ControllerpuorG08/C61M 25. DRAM Controller There is a built in DRAM controller to which it is possible to connect between 512 Kbytes and 8 Mbytes of DRAM. Table 25.1 shows the functions of the DRAM controller. Table 25.1 DRAM Controller Functions DRAM space 512KB, 1MB, 2MB, 4MB, 8MB Bus control 2CAS/1W Refresh CAS before RAS refresh Self refresh-compatible Function modes EDO-compatible, fast page mode-compatible Waits 1 wait or 2 waits, programmable To use the DRAM controller, use the DRAM space select bit of the DRAM control register (address 0040 16) to specify the DRAM size. Figure 25.1 shows the DRAM control register. The DRAM controller cannot be used in external memory mode 3 (bits 1 and 2 at address 0005 16 are “112”). Always use the DRAM controller in external memory modes 0, 1, or 2. When the data bus width is 16-bit in DRAM area, set "1" to R/W mode select bit (bit 2 at address 0004 16). Set wait time between after DRAM power ON and before memory processing, and processing necessary for dummy cycle to refresh DRAM by software. DRAM control register Symbol Address When reset DRAMCONT 00040 16 Indeterminate (Note 4) Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 AR1 WT AR0 AR2 0 0 0 : DRAM ignored 0 0 1 : Inhibit 0 1 0 : 0.5MB 0 1 1 : 1MB 1 0 0 : 2MB 1 0 1 : 4MB 1 1 0 : 8MB 1 1 1 : Inhibit b3 b2 b1 DRAM space select bit Wait select bit (Note 1) Self-refresh mode bit (Note 2) SREF 0 : Two wait 1 : One wait 0: Self-refresh OFF 1: Self-refresh ON Nothing is assigned. When write, set "0". When read, the value of these bits is indeterminate. Note 1: The number of cycles with 2 waits is 3-2-2. With 1 wait, it is 2-1-1. Note 2: When you set "1", both RAS and CAS change to "L". When you set "0", RAS and CAS change to "H" and then normal operation (read/write, refresh) is resumed. In Stop mode, there is no control. Note 3: Set the bus width using the external data bus width control register (address 000B 16). When selecting 8-bit bus width, CASH is indeterminate. Note 4: After reset, the content of this register is indeterminate. DRAM controller starts the operation after writing to this register. Figure 25.1 DRAM control register

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 184 25. DRAM ControllerpuorG08/C61M

DRAM Controller Multiplex Address Output The DRAM controller outputs the row addresses and column addresses as a multiplexed signal to the address bus A8 to A20. Figure 25.2 shows the output format for multiplexed addresses. A9(A20) (A19) A18 A17 A16 A15 A14 A13 A12 A11 A10 A0(A22) (A22) A8 A7 A6 A5 A4 A3 A2 A1 8-bit bus mode 512KB, 1MB 2MB, 4MB 8MB MA1MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 A9(A20) A18 A17 A16 A15 A14 A13 A12 A11 A10 A0(A22) A8 A7 A6 A5 A4 A3 A2 A1 A19 A19 A20A21 A9A18 A17 A16 A15 A14 A13 A12 A11 A10 A0(A22) A8 A7 A6 A5 A4 A3 A2 A1 A19 A21A22 A20 (A9)(A20) (A19) A18 A17 A16 A15 A14 A13 A12 A11 A10 (A0)(A22) (A20) A8 A7 A6 A5 A4 A3 A2 A1 16-bit bus mode (A9)(A20) (A19) (A18) (A17) (A16) (A15) (A14) (A13) (A12) (A11) (A10)Pin function 512KB 1MB, 2MB 4MB, 8MB (Note 2) MA1MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 (A9)(A20) A18 A17 A16 A15 A14 A13 A12 A11 A10 (A0)(A22) A8 A7 A6 A5 A4 A3 A2 A1 A19 A9A20 (A9)A18 A17 A16 A15 A14 A13 A12 A11 A10 (A0)A8 A7 A6 A5 A4 A3 A2 A1 Row address A19 A9A21 A20 A22 Note 1: ( ) invalid bit: bits that change according to selected mode (8-bit/16-bit bus mode, DRAM space). Note 2: The figure is for 4Mx1 or 4Mx4 memory configuration. If you are using a 4Mx16 configuration, use combinations of the following: For row addresses, MA0 to MA12; for column addresses MA2 to MA8, MA11, and MA12. Or for row addresses MA1 to MA12; for column addresses MA2 to MA9, MA11, MA12. Note 3: "–" is indeterminate. (A8) MA0 (A8) MA0 Row address Row address Pin function Row address Row address Row address Column address Column address Column address Column address Column address Column address Figure 25.2 Output format for multiplexed addresses

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 185 25. DRAM ControllerpuorG08/C61M Figure 25.3 DRAM refresh interval set register

Refresh The refresh method is CAS before RAS. The refresh interval is set by the DRAM refresh interval set register (address 004116). The refresh signal is not output in HOLD state. Figure 25.3 shows the DRAM refresh interval set register. Use the following formula to determine the value to set in the refresh interval set register. Refresh interval set register value (0 to 255) = refresh interval time / (BCLK frequency X 32) - 1 DRAM refresh interval set register Symbol Address When reset REFCNT 00041 16 Indeterminate WR b7 b6 b5 b4 b3 b2 b1 b0 Refresh interval set bit 0 0 0 0 0 0 0 0 : 1.6 µs 0 0 0 0 0 0 0 1 : 3.2 µs 0 0 0 0 0 0 1 0 : 4.8 µs 1 1 1 1 1 1 1 1 : 409.6 µs b7 b6 b5 b4 b3 b2 b1 b0 (Note) Note: Refresh interval at 20 MHz operating (no division) Refresh interval = BCLK frequency X (refresh interval set bit + 1) X 32 REFCNT0 REFCNT1 REFCNT2 REFCNT3 REFCNT4 REFCNT5 REFCNT6 REFCNT7 Bit name FunctionBit symbol

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 186 25. DRAM ControllerpuorG08/C61M The DRAM self-refresh operates in STOP mode, etc. When shifting to self-refresh, select DRAM ignored by the DRAM space select bit. In the next instruction, simultaneously set the DRAM space select bit and self-refresh ON by self-refresh mode bit. Also, insert two NOPs after the instruction that sets the self-refresh mode bit to "1". Do not access external memory while operating in self-refresh. (All external memory space access is inhibited. ) When disabling self-refresh, simultaneously select DRAM ignored by the DRAM space select bit and self- refresh OFF by self-refresh mode bit. In the next instruction, set the DRAM space select bit. Do not access the DRAM space immediately after setting the DRAM space select bit. Example) One wait is selected by the wait select bit and 4MB is selected by the DRAM space select bit Shifting to self-refresh

•• mov.b #00000001b,DRAMCONT ;DRAM ignored, one wait is selected mov.b #10001011b,DRAMCONT ;Set self-refresh, select 4MB and one wait nop ;Two nops are needed nop ;
•• Disable self-refresh
•• mov.b #00000001b,DRAMCONT ;Disable self-refresh, DRAM ignored, one wait is ;selected mov.b #00001011b,DRAMCONT ;Select 4MB and one wait nop ;Inhibit instruction to access DRAM area nop
•• Figures 25.4 to 25.6 show the bus timing during DRAM access.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 187 25. DRAM ControllerpuorG08/C61M Figure 25.4 The bus timing during DRAM access (1) BCLK MA0 to MA12 RAS CASH CASL DW D 0 to D15 (EDO mode) BCLK MA0 to MA12 RAS CASH CASL DW D 0 to D15 'H' < Read cycle (wait control bit = 0) > < Write cycle (wait control bit = 0) > Row address Row address Note : Only CASL is operating in 8-bit data bus width. Note : Only CASL is operating in 8-bit data bus width. Column address 1 Column address 2 Column address 3 Column address 1 Column address 2 Column address 3

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 188 25. DRAM ControllerpuorG08/C61M Figure 25.5 The bus timing during DRAM access (2) BCLK MA0 to MA12 RAS CASH CASL DW D 0 to D15 (EDO mode) BCLK MA0 to MA12 RAS CASH CASL DW D 0 to D15 < Read cycle (wait control bit = 1) > < Write cycle (wait control bit = 1) > Row address Row address 'H' Note : Only CASL is operating in 8-bit data bus width. Note : Only CASL is operating in 8-bit data bus width. Column address 1 Column address 2 Column address 3 Column address 4 Column address 1 Column address 2 Column address 3 Column address 4

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 189 25. DRAM ControllerpuorG08/C61M Figure 25.6 The bus timing during DRAM access (3) BCLK RAS CASH CASL BCLK RAS < Self refresh cycle > Note : Only CASL is operating in 8-bit data bus width. "H" DW < CAS before RAS refresh cycle > CASH CASL "H" DW Note : Only CASL is operating in 8-bit data bus width.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 190 26. Programmable I/O PortspuorG08/C61M 26. Programmable I/O Ports There are 87 programmable I/O ports for 100-pin version: P0 to P10 (excluding P85). There are 123 pro- grammable I/O ports for 144-pin version: P0 to P15 (excluding P85). Each port can be set independently for input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P85 is an input-only port and has no built-in pull-up resistance. Figures 26.1 to 26.3 show the programmable I/O ports. Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices. To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D/A con- verter), set the corresponding function select registers A, B and C. When pins are to be used as the outputs for the D/A converter, set the function select register of each pin to I/O port, and set the direction registers to input mode. Table 26.1 lists each port and peripheral function. See the descriptions of the respective functions for how to set up the built-in peripheral devices. (1) Direction registers Figures 26.4 and 26.5 show the direction registers. These registers are used to choose the direction of the programmable I/O ports. Each bit in these regis- ters corresponds one for one to each I/O pin. In memory expansion and microprocessor mode, the contents of corresponding direction register of pins A0 to A22, A23, D0 to D15, MA0 to MA12, CS0 to CS 3, WRL/WR/CASL, WRH/BHE/CASH, RD/DW, BCLK/ALE/CLK OUT , HLDA/ALE, HOLD, ALE/RAS, and RDY are not changed. Note: There is no direction register bit for P85. (2) Port registers Figures 26.6 and 26.7 show the port registers. These registers are used to write and read data for input and output to and from an external device. A port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit in port registers corresponds one for one to each I/O pin. In memory expansion and microprocessor mode, the contents of corresponding port register of pins A 0 to A22, A23, D0 to D15, MA0 to MA12, CS0 to CS 3, WRL/WR/CASL, WRH/BHE/CASH, RD/DW, BCLK/ALE/ CLK OUT , HLDA/ALE, HOLD, ALE/RAS, and RDY are not changed. (3) Function select register A Figures 26.8 and 26.9 show the function select registers A. The register is used to select port output and peripheral function output when the port functions for both port output and peripheral function output. Each bit of this register corresponds to each pin that functions for both port output and peripheral function output.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 192 26. Programmable I/O PortspuorG08/C61M Figure 26.1 Programmable I/O ports (1) P00 to P07, P20 to P27, P30 to P37, P40 to P47, P50 to P52, P54 to P57, P110 to P114, P120 to P127, P130 to P137, P140 to P146, P150 to P157 P10 to P14 P15 to P17 P62, P66, P77, P87 Data bus Direction register Pull-up selection Pull-up selection Pull-up selection Pull-up selection Direction register Port latch Port P1 control register bit 0 Direction register Port latch Port latch Port latch Direction register Port P1 control register bit 0 Data bus Data bus Data bus Input to respective peripheral functions Input to respective peripheral functions (Note) Note: Port P11 to P15 exist in 144-pin version.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 193 26. Programmable I/O PortspuorG08/C61M P85 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines Note Function select register A Port latch Pull-up selection P82 to P84 P60, P61, P64, P65, P72, P73 P74, P75, P76, P80, P81, P90, P91 P92, P97 (inside dotted-line included) 3, P63, P67, P86 (inside dotted-line not included) Note : P53 is connected to clock output function select bit. P70, P71 Direction register Input to respective peripheral functions Direction register Direction register Port latch Port latch Pull-up selection Input to respective peripheral functions Input to respective peripheral functions Function select register A Data bus Data bus Data bus Data bus Output from respective peripheral functions Output from respective peripheral functions NMI interrupt input Figure 26.2 Programmable I/O ports (2)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 194 26. Programmable I/O PortspuorG08/C61M Figure 26.3 Programmable I/O ports (3) P100 to P103 P93, P94 D/A output enabled P95 (inside dotted-line included) P96 (inside dotted-line not included) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines P104 to P107 Port latch Pull-up selection Direction register Input to respective peripheral functions Data bus Port latch Direction register Port latch Direction register Port latch Direction register Pull-up selection Pull-up selection Pull-up selection Data bus Data bus Data bus Input to respective peripheral functions Input to respective peripheral functions Analog input Analog input Analog input Analog input Function select register A Function select register A Output from respective peripheral functions Output from respective peripheral functions

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 195 26. Programmable I/O PortspuorG08/C61M Figure 26.4 Direction register (1) Port Pi direction register (Note 1,2, 3) Symbol Address When reset PDi (i = 0 to 15, 03E2 16, 03E316, 03E616, 03E716, 0016 except 8, 11 and 14) 03EA16, 03EB16, 03C216, 03C316, 03C7 16, 03CA16, 03CE16, 03CF16, 03D3 16 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 PDi_0 Port Pi 0 direction register PDi_1 Port Pi 1 direction register PDi_2 Port Pi 2 direction register PDi_3 Port Pi 3 direction register PDi_4 Port Pi 4 direction register PDi_5 Port Pi 5 direction register PDi_6 Port Pi 6 direction register PDi_7 Port Pi 7 direction register 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) (i = 0 to 15 except 8, 11 and 14) Port P8 direction register Symbol Address When reset PD8 03C6 16 00X000002 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 PD8_0 Port P8 0 direction register PD8_1 Port P8 1 direction register PD8_2 Port P8 2 direction register PD8_3 Port P8 3 direction register PD8_4 Port P8 4 direction register Nothing is assigned. When write, set "0". When read, its content is indeterminate. PD8_6 Port P8 6 direction register PD8_7 Port P8 7 direction register 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) Note 1: Set bit 2 of protect register (address 000A16) to “1” before rewriting to the port P9 direction register. Note 2: In memory expansion and microprocessor mode, the contents of corresponding port direction register of pins A0 to A22, A23, D0 to D15, MA0 to MA 12, CS0 to CS 3, WRL/WR/CASL, WRH/BHE/CASH, RD/DW, BCLK/ALE/ CLK OUT , HLDA/ALE, HOLD, ALE/RAS, and RDY are not changed. Note 3: Port P12, P13 and P15 direction registers exist in 144-pin version. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 196 26. Programmable I/O PortspuorG08/C61M Figure 26.5 Direction register (2) Port P11 direction register (Note) Symbol Address When reset PD11 03CB 16, XXX00000 2 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 PD11_0 Port P11 0 direction register PD11_1 Port P11 1 direction register PD11_2 Port P11 2 direction register PD11_3 Port P11 3 direction register PD11_4 Port P11 4 direction register 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) Port P14 direction register (Note) Symbol Address When reset PD14 03D2 16 X00000002 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 PD14_0 Port P14 0 direction register PD14_1 Port P14 1 direction register PD14_2 Port P14 2 direction register PD14_3 Port P14 3 direction register PD14_4 Port P14 4 direction register Nothing is assigned. When write, set "0". When read, its content is indeterminate. 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Nothing is assigned. When write, set "0". When read, its content is indeterminate. PD14_5 Port P14 5 direction register PD14_6 Port P14 6 direction register /LiteDiagLines/LiteDiagLines/LiteDiagLines Note: This register exists in 144-pin version. Note: This register exists in 144-pin version.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 197 26. Programmable I/O PortspuorG08/C61M Port Pi register (Note 1, 3) Symbol Address When reset Pi (i = 0 to 15, 03E0 16, 03E116, 03E416, 03E516, Indeterminate except 8, 11 and 14) 03E816, 03E916, 03C016, 03C116, 03C516, 03C816, 03CC16, 03CD16, 03D116 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 PDi_0 Port Pi 0 register PDi_1 Port Pi 1 register PDi_2 Port Pi 2 register PDi_3 Port Pi 3 register PDi_4 Port Pi 4 register PDi_5 Port Pi 5 register PDi_6 Port Pi 6 register PDi_7 Port Pi 7 register Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : “L” level data 1 : “H ” level data (Note 2) (i = 0 to 15 except 8, 11 and 14) Port P8 register Symbol Address When reset P8 03C4 16 Indeterminate Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 PD8_0 Port P80 register PD8_1 Port P81 register PD8_2 Port P82 register PD8_3 Port P83 register PD8_4 Port P84 register PD8_5 Port P85 register PD8_6 Port P86 register PD8_7 Port P87 register Data is input and output to and from each pin by reading and writing to and from each corresponding bit (except for P8 0 : “L” level data 1 : “H ” level data /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Note 1: In memory expansion and microprocessor mode, the contents of corresponding port Pi direction register of pins A0 to A22, A23, D0 to D15, MA0 to MA12, CS0 to CS 3, WRL/WR/CASL, WRH/BHE/CASH, RD/DW, BCLK/ ALE/CLK OUT , HLDA/ALE, HOLD, ALE/RAS, and RDY are not changed. Note 2: P70 and P71 are N-channel open drain ports and high inpedance outputs. Note 3: Port P12, P13 and P15 registers exist in 144-pin version. Figure 26.6 Port register (1)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 198 26. Programmable I/O PortspuorG08/C61M Figure 26.7 Port register (2) Port P11 register (Note) Symbol Address When reset P11 03C9 16 Indeterminate Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 P11_0 Port P11 0 register P11_1 Port P11 1 register P11_2 Port P11 2 register P11_3 Port P11 3 register P11_4 Port P11 4 register Port P14 register (Note) Symbol Address When reset P14 03D0 16 Indeterminate Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 P14_0 Port P14 0 register P14_1 Port P14 1 register P14_2 Port P14 2 register P14_3 Port P14 3 register P14_4 Port P14 4 register Nothing is assigned. When set, write "0". When read, its content is indeterminate. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Nothing is assigned. When write, set "0". When read, its content is indeterminate. P14_5 Port P14 5 register P14_6 Port P14 6 register /LiteDiagLines/LiteDiagLines Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : “L” level data 1 : “H ” level data Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : “L” level data 1 : “H ” level data Note: This register exists in 144-pin version. Note: This register exists in 144-pin version.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 199 26. Programmable I/O PortspuorG08/C61M P60 P61 P62 P63 P64 P65 P66 P67 P70 P71 P72 P73 P74 P75 P76 P77 P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 CLK 0 output TXD 0 output CLK 1 output TXD 1 output TXD 2(SDA 2) output SCL 2 output CLK 2 output TA2 OUT output TA3 OUT output TA4 OUT output CLK 3 output SCL 3 output TXD 3(SDA 3) output CLK 4 output TXD 4(SDA 4) output SCL 3 output Port Periphral output function 1 Periphraloutput function 2 Periphral output function 3 CLKS 1 output TA0 OUT output TA1 OUT output W phase output U phase output V phase output RTS 0 output RTS 1 output RTS 2 output W phase output U phase output RTS 3 output RTS 4 output V phase output ST XD 4 output ST XD 3 output Table 26.1 Each port and peripheral output function (Note 1) Note 1: When using peripheral input function, set the corresponding function select register A to "0" (I/O port). Note 2: N-channel open drain output. (Note 2) (Note 2)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 200 26. Programmable I/O PortspuorG08/C61M Figure 26.8 Function select register A (1) Function select register A0 Symbol Address When reset PS0 03B0 16 0X000X00 2 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 Port P60 function select bitPS0_0 0 : I/O port 1 : RTS0 output Port P61 function select bitPS0_1 0 : I/O port 1 : CLK0 output Port P63 function select bitPS0_3 0 : I/O port 1 : TXD0 output Port P64 function select bitPS0_4 0 : I/O port 1 : Peripheral function output (PSL0_4 enabled) Port P6 5 function select bitPS0_5 0 : I/O port 1 : CLK1 output Port P67 function select bitPS0_7 0 : I/O port 1 : TXD1 output Function select register A1 Symbol Address When reset PS1 03B1 16 X00000002 WR b7 b6 b5 b4 b3 b2 b1 b0 Port P70 function select bit (Note) PS1_0 0 : I/O port 1 : Peripheral function output (PSL1_0 enabled)Port P73 function select bitPS1_3 0 : I/O port 1 : Peripheral function output (PSL1_3 enabled) Port P7 4 function select bitPS1_4 0 : I/O port 1 : Peripheral function output (PSL1_4 enabled) Port P7 5 function select bitPS1_5 Port P72 function select bitPS1_2 0 : I/O port 1 : Peripheral function output (PSL1_2, PSC_0 enabled) 0 : I/O port 1 : W phase output Port P76 function select bitPS1_6 0 : I/O port 1 : TA3OUT output Port P71 function select bit (Note) PS1_1 0 : I/O port 1 : SCL2 output Nothing is assigned. When write, set "0". When read, the content is indeterminate. Nothing is assigned. When write, set "0". When read, the content is indeterminate. Nothing is assigned. When write, set "0". When read, the content is indeterminate. Bit name FunctionBit symbol /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Note: This port is N-channel open drain output.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 201 26. Programmable I/O PortspuorG08/C61M Figure 26.9 Function select register A (2) Function select register A2 Symbol Address When reset PS2 03B4 16 XXXXXX00 2 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 Port P80 function select bitPS2_0 0 : I/O port 1 : Peripheral function output (PSL2_0 enabled) Port P81 function select bitPS2_1 0 : I/O port 1 : U phase output Function select register A3 (Note) Symbol Address When reset PS3 03B5 16 0016 WR b7 b6 b5 b4 b3 b2 b1 b0 Port P90 function select bitPS3_0 0 : I/O port 1 : CLK3 output Port P93 function select bitPS3_3 0 : I/O port 1 : RTS3 output Port P94 function select bitPS3_4 0 : I/O port 1 : RTS4 output Port P95 function select bitPS3_5 Port P92 function select bitPS3_2 0 : I/O port 1 : TxD3(SDA 3) output 0 : I/O port 1 : CLK4 output Port P96 function select bitPS3_6 0 : I/O port 1 : TxD4(SDA 4) output Port P91 function select bitPS3_1 0 : I/O port 1 : Peripheral function output (PSL3_1 enabled) Nothing is assigned. When write, set "0". When read, the content is indeterminate. Bit name FunctionBit symbol Port P97 function select bitPS3_7 0 : I/O port 1 : Peripheral function output (PSL3_7 enabled) Note: Set bit 2 of protect register (address 000A 16) to “1” before rewriting to this register. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 202 26. Programmable I/O PortspuorG08/C61M Figure 26.10 Function select register B (1) Function select register B0 Symbol Address When reset PSL0 03B2 16 XXX0XXXX 2 Bit nameBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 Port P64 peripheral function select bit (Enabled when PS0_4 = 1) PSL0_4Function select register B1 Symbol Address When reset PSL1 03B3 16 XXX000X0 2 WR b7 b6 b5 b4 b3 b2 b1 b0 Port P70 peripheral function select bit (Enabled when PS1_0 = 1) (Note 2) PSL1_0 PSL1_3 PSL1_4 PSL1_2 0 : Port P72 peripheral subfunction select bit (PSC_0) is enabled 1 : TA1 OUT output (Note 1) Nothing is assigned. When write, set "0". When read, the content is indeterminate. Bit nameBit symbol Function 0 : RTS1 output 1 : CLKS1 output 0 : TxD2(SDA 2) port 1 : TA0OUT output 0 : RTS2 port 1 : V phase output 0 : TA2OUT port 1 : W phase output Function Note 1: Set PSC_0 to “1”. Note 2: This port is N-channel open drain output. Nothing is assigned. When write, set "0". When read, the content is indeterminate. Port P72 peripheral function select bit (Enabled when PS1_2 = 1) Port P7 4 peripheral function select bit (Enabled when PS1_4 = 1) Port P7 3 peripheral function select bit (Enabled when PS1_3 = 1) Nothing is assigned. When write, set "0". When read, the content is indeterminate. Nothing is assigned. When write, set "0". When read, the content is indeterminate. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Function select register B2 Symbol Address When reset PSL2 03B6 16 XXXXXXX0 2 WR b7 b6 b5 b4 b3 b2 b1 b0 Port P80 peripheral function select bit (Enabled when PS2_0 = 1) PSL2_0 Bit nameBit symbol 0 : TA4OUT output 1 : U phase output Function Nothing is assigned. When write, set "0". When read, the content is indeterminate. /LiteDiagLines/LiteDiagLines /LiteDiagLines

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 204 26. Programmable I/O PortspuorG08/C61M Figure 26.13 Pull-up control register (1) Pull-up control register 0 (Note) Symbol Address When reset PUR0 03F0 16 0016 Bit name Function Bit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 PU00 P0 0 to P03 pull-up PU01 P0 4 to P07 pull-up PU02 P1 0 to P13 pull-up PU03 P1 4 to P17 pull-up PU04 P2 0 to P23 pull-up PU05 P2 4 to P27 pull-up PU06 P3 0 to P33 pull-up PU07 P3 4 to P37 pull-up The corresponding port is pulled high with a pull-up resistance 0 : Not pulled high 1 : Pulled high /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Pull-up control register 1 (Note) Symbol Address When reset PUR1 03F1 16 X016 Bit name Function Bit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 PU10 P4 0 to P43 pull-up PU11 P4 4 to P47 pull-up PU12 P5 0 to P53 pull-up PU13 P5 4 to P57 pull-up The corresponding port is pulled high with a pull-up resistance 0 : Not pulled high 1 : Pulled high Note 1: Since P7 0 and P71 are N-channel open drain ports, pull-up is not available for them. Note 2: Except port P85. /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Pull-up control register 2 Symbol Address When reset PUR2 03DA 16 0016 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 PU24 P8 0 to P83 pull-up PU25 P8 4 to P87 pull-up (Note 2) PU26 P9 0 to P93 pull-up PU27 P9 4 to P97 pull-up The corresponding port is pulled high with a pull-up resistance 0 : Not pulled high 1 : Pulled high /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Nothing is assigned. When write, set "0". When read, their contents are indeterminate. PU20 P6 0 to P63 pull-up PU21 P6 4 to P67 pull-up PU22 P7 0 to P73 pull-up (Note 1) PU23 P7 4 to P77 pull-up /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Note: Since P0 to P5 operate as the bus in memory expansion mode and microprocessor mode, do not set the pull-up control register. However, it is possible to select pull- up resistance presence to the usable port as I/O port by setting. Note: Since P0 to P5 operate as the bus in memory expansion mode and microprocessor mode, do not set the pull-up control register. However, it is possible to select pull- up resistance presence to the usable port as I/O port by setting.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 205 26. Programmable I/O PortspuorG08/C61M Figure 26.14 Pull-up control register (2) Pull-up control register 3 Symbol Address When reset PUR3 03DB 16 0016 Bit name Function Bit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 PU30 P10 0 to P103 pull-up PU31 P10 4 to P107 pull-up PU32 P11 0 to P113 pull-up PU33 P11 4 pull-up PU34 P12 0 to P123 pull-up PU35 P12 4 to P127 pull-up PU36 P13 0 to P133 pull-up PU37 P13 4 to P137 pull-up The corresponding port is pulled high with a pull-up resistance 0 : Not pulled high 1 : Pulled high /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Pull-up control register 4 (Note) Symbol Address When reset PUR4 03DC 16 XXXX0000 2 Bit name Function Bit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 PU40 P14 0 to P143 pull-up PU41 P14 4 to P146 pull-up PU42 P15 0 to P153 pull-up PU43 P15 4 to P157 pull-up The corresponding port is pulled high with a pull-up resistance 0 : Not pulled high 1 : Pulled high /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Nothing is assigned. When write, set "0". When read, their contents are “0”. Note: This register exists in 144-pin version. Pull-up control register 3 Symbol Address When reset PUR3 03DB 16 0016 Bit name Function Bit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 PU30 P10 0 to P103 pull-up PU31 P10 4 to P107 pull-up Reserved bit The corresponding port is pulled high with a pull-up resistance 0 : Not pulled high 1 : Pulled high /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 00 00 0 0 Must always be set to "0" 100-pin version 144-pin version

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 206 26. Programmable I/O PortspuorG08/C61M Figure 26.15 Port control register Port control register (Note 1) Symbpl Address When reset PCR 03FF 16 XXXXXXX0 2 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 PCR0 Port P1 control register 0 : Function as common CMOS port 1 : Function as N-ch open drain port (Note 2) Nothing is assigned. When write, set "0". When read, their contents are indeterminate. /LiteDiagLines /LiteDiagLines Note 1: Since P1 operates as the data bus in memory expansion mode and microprocessor mode, do not set the port control register. However, it is possible to select the CMOS port or N-channel open drain to the usable port as I/O port by setting. Note 2: This function is designed to permanently turn OFF the Pch of the CMOS port. It does not make port 1 a full open drain. Therefore, the absolute maximum input voltage rating is [-3 to Vcc + 0.3V].

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 207 26. Programmable I/O PortspuorG08/C61M Pin name Connection Ports P0 to P15 (excluding P85) ( Note 1) XOUT (Note 2) AV SS , VREF , BYTE AV CC After setting for input mode, connect every pin to VSS via a resistance (pull-down); or after setting for output mode, leave these pins open. Open Connect to VCC Connect to VSS Note 1: Port P11 to P15 exist in 144-pin version. Note 2: With external clock input to XIN pin. NMI Connect via resistance to VCC (pull-up) Table 26.2 Example connection of unused pins in single-chip mode Pin name Connection Ports P6 to P15(excluding P85) ( Note 1) AV SS , VREF AV CC Open Connect to VCC Connect to VSS Note 1: Port P11 to P15 exist in 144-pin version. Note 2: With external clock input to XIN pin. HOLD, RDY, NMI Connect via resistance to VCC (pull-up) BHE, ALE, HLDA, XOUT (Note 2), BCLK After setting for input mode, connect every pin to VSS via a resistance (pull-down); or after setting for output mode, leave these pins open. Figure 26.16 Example connection of unused pins Port P0 to P15 (except for P85) (Input mode)··

(Input mode) (Output mode) NMI XOUT AV CC BYTE AV SS VREF Microcomputer VCC VSS In single-chip mode Port P6 to P15 (except for P85) (Input mode)··
(Input mode) (Output mode) NMI XOUT AV CC AV SS VREF Open Microcomputer VCC VSS In memory expansion mode or in microprocessor mode HOLD RDY ALE BCLK BHE HLDA Open Open Open
··
·· Note: Port P11 to P15 exist in 144-pin version. (Note) (Note) Table 26.3 Example connection of unused pins in memory expansion mode and microprocessor mode

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 208 27. Usage PrecautionpuorG08/C61M 27. Usage Precaution SFR (100-pin version) (1) Addresses 03C916, 03CB16 to 03D316 , 03DC16 area is for future plan. Must set "FF16" to address 03CB 16, 03CE16, 03CF16, 03D216, 03D316 and "0016" to address 03DC16 at initial setting. Timer (1) A timer Ai register and a timer Bi register are unstable after MCU resetting. Please start a count after setting a value as the timer Ai register or timer Bi register to be used, when using a timer. Timer A (timer mode) (1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing gets “FFFF 16”. Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a proper value. Timer A (event counter mode) (1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing gets “FFFF 16” by under- flow or “000016” by overflow. Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a proper value. (2) When stop counting in free run type, set timer again. (3) In the case of using as “Free-Run type”, the timer register contents may be unknown when count- ing begins. If the timer register is set before counting has started, then the starting value will be unknown.

In the case where the up/down count will not be changed. Enable the “Reload” function and write to the timer register before counting begins. Re- write the value to the timer register immediately after counting has started. If counting up, rewrite “0000 16” to the timer register. If counting down, rewrite “FFFF 16” to the timer register. This will cause the same operation as “Free-Run type” mode.
In the case where the up/down count has changed. First set to “Reload type” operation. Once the first counting pulse has occurred, the timer may be changed to “Free-Run type”.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 209 27. Usage PrecautionpuorG08/C61M Timer A (one-shot timer mode) (1) Setting the count start flag to “0” while a count is in progress causes as follows:

The counter stops counting and a content of reload register is reloaded.
The TAiOUT pin outputs “L” level.
The interrupt request generated and the timer Ai interrupt request bit goes to “1”. (2) The output from the one-shot timer synchronizes with the count source generated internally. There- fore, when an external trigger has been selected, a delay of one cycle of count source as maximum occurs between the trigger input to the TAi IN pin and the one-shot timer output. (3) The timer Ai interrupt request bit goes to “1” if the timer's operation mode is set using any of the following procedures:
Selecting one-shot timer mode after reset.
Changing operation mode from timer mode to one-shot timer mode.
Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after the above listed changes have been made. (4) If a trigger occurs while a count is in progress, after the counter performs one down count following the reoccurrence of a trigger, the reload register contents are reloaded, and the count continues. To generate a trigger while a count is in progress, generate the second trigger after an elapse longer than one cycle of the timer's count source after the previous trigger occurred. (5) If an external trigger input is used to start counting, the next external trigger input must be avoided within 300ns before the timer A reaches "0000h". Timer A (pulse width modulation mode) (1) The timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compliance with any of the following procedures:
Selecting PWM mode after reset.
Changing operation mode from timer mode to PWM mode.
Changing operation mode from event counter mode to PWM mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after the above listed changes have been made. (2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop counting. If the TAiOUT pin is outputting an “H ” level in this instance, the output level goes to “L”, and the timer Ai interrupt request bit goes to “1”. If the TAiOUT pin is outputting an “L” level in this instance, the level does not change, and the timer Ai interrupt request bit does not becomes “1”.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 210 27. Usage PrecautionpuorG08/C61M Timer B (timer mode, event counter mode) (1) The TBi (i=0 to 5) register indicates the countervalue during counting at any given time. However, the counter is "FFFF16" when reloading. The setting value can be read after setting the TBi register while the counter stops and before the counter starts counting. Timer B (pulse period/pulse width measurement mode) (1) If the measurement mode select bit setting is changed after counting is started, the timer Bi interrupt request bit is set to "1". (2) Indeterminate values are transferred to the reload register during the first valid edge input after count- ing is started. The timer Bi interrupt request is not generated at this time. (3) The counter value is indeterminate when counting is started. Therefore, the timer Bi overflow flag setting may change to "1" and causes the timer Bi interrupt requests to be generated until a valid edge is input after counting is started. (4) The timer Bi overflow flag is set to "0" by writting to the timer Bi mode register at or after counting timing of the next count source, after the count start flag is set to "1" and the timer Bi overflow flag is set to "1". Stop Mode and Wait Mode (1) To exit stop mode by hardware reset, provide an "L" signal input to the RESET pin until main clock oscillation is stable. (2) When entering wait mode, the instruction queue reads ahead to instructions following the WAIT in- struction, and the program stops. Write at least 4 NOP instructions after the WAIT instruction. (3) When entering stop mode, the instruction lined in the instruction queue is executed before the inter- rupt for recovery is done. Write the JMP.B instruction, as follows, after the instruction setting the all clock stop control bit to "1". bset 0,prcr ; protection removed bset 0,cm1 ; all clocks stopped (entering stop mode) jmp.b LABEL_001 ; JMP.B instruction executed (Jump to the next instruction soon LABEL_001: ; with no instruction between JMP.B and LABEL.) nop ; nop(1) nop ; nop(2) nop ; nop(3) nop ; nop(4) mov.b #0,prcr ; protection set

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 211 27. Usage PrecautionpuorG08/C61M (4) Use the following procedure to enter stop mode.

Initial Setting Set each interrupt priority level after setting the interrupt priority level required to exit stop mode, controlled by the RLVL2 to RLVL0 bits in the RLVL register, to "7".
Before Entering Stop Mode [1] Set the interrupt priority level of the interrupt being used to exit stop mode [2] Set the interrupt priority levels of the interrupts, not being used to exit stop mode, to "0". [3] Set the IPL in the FLG register. Then set the exit priority level to the same level as the IPL. (Interrupt priority level of the interrupt used to exit stop mode > exit priority level ≥ interrupt priority level of the interrupts not used to exit stop mode) [4] Set the I flag to "1" [5] Set the CM10 bit in the CM1 register to "1" (all clocks stop) after setting the PRC0 bit in the PRCR register to "1" (write enabled)
After Exiting Stop Mode Set the exit priority level to "7" as soon as exiting stop mode. (5) When microcomputer enters stop mode again after exiting from stop mode using the NMI interrupt, use the following procedure to set the CM10 bit to "1". [1] Exit stop mode using the NMI interrupt [2] Generate a dummy interrupt [3] Set the CM10 bit to "1" Example: INT #63 ; Dummy interrupt BSET CM1 ; All clocks stopped (in stop mode) ; /*for dummy interrupt* / DUMMY: REIT (6) Use the following procedure to enter wait mode.
Initial Setting Set each interrupt priority level after setting the interrupt priority level required to exit wait mode, controlled by the RLVL2 to RLVL0 bits in the RLVL register, to "7".
Before Entering Wait Mode [1] Set the interrupt priority level of the interrupt being used to exit wait mode [2] Set the interrupt priority levels of the interrupts, not being used to exit wait mode, to "0". [3] Set the IPL in the FLG register. Then set the exit priority level to the same level as the IPL. (Interrupt priority level of the interrupt used to exit wait mode > exit priority level ≥ interrupt priority level of the interrupts not used to exit wait mode) [4] Set the I flag to "1" [5] Execute the WAIT instruction
After Exiting Wait Mode Set the exit priority level to "7" as soon as exiting wait mode.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 212 27. Usage PrecautionpuorG08/C61M A/D Converter (1) Write to each bit (except bit 6) of A/D control register 0, to each bit of A/D control register 1, and to bit 0 of A/D control register 2 when A/D conversion is stopped (before a trigger occurs). In particular, when the Vref connection bit is changed from “0” to “1”, start A/D conversion after an elapse of 1 µs or longer. (2) When changing A/D operation mode, select analog input pin again. (3) Using one-shot mode or single sweep mode Read the correspondence A/D register after confirming A/D conversion is finished. (It is known by A/ D conversion interrupt request bit.) Use the undivided main clock as the internal CPU clock. (4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1 (5) When f(X IN) is faster than 10 MHz, make the frequency 10 MHz or less by dividing. (6) If A/D conversion is stopped by program while in progress of A/D conversion, the conversion result of A/D converter becomes indeterminate. The contents of A/D registers irrelevant to A/D conversion may become indeterminate. If A/D conversion is stopped by program while in progress of A/D conver- sion, ignore the values of all A/D registers. (7) Output impedance of sensor at A/D conversion (Reference value) To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 27.1 has to be completed within a specified period of time T. Let output impedance of sensor equivalent circuit be R0, microcomputer’s internal resistance be R, precision (error) of the A/D converter be X, and the A/ D converter’s resolution be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode). Vc is generally V C = VIN {1 – e} And when t = T, VC =VIN – VIN=VIN(1 – ) e = – =ln Hence, R0 = –– R C (R0 +R) T C (R0 + R) T C (R0 + R) t Y X Y X Y X Y X C • ln T Y X

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 213 27. Usage PrecautionpuorG08/C61M VC C (3.0pF)VIN Microcomputer Sensor Equivalent Circuit R (7.8k )R 0 With the model shown in Figure 27.1 as an example, when the difference between VIN and VC becomes 0.1LSB, we find impedance R0 when voltage between pins VC changes from 0 to VIN-(0.1/1024) VIN in time T. (0.1/1024) means that A/D precision drop due to insufficient capacitor charge is held to 0.1LSB at time of A/D conversion in the 10-bit mode. Actual error however is the value of absolute precision added to 0.1LSB. When f(X IN) = 10 MHz, T = 0.3 us in the A/D conversion mode with sample & hold. Output impedance R0 for sufficiently charging capacitor C within time T is determined as follows. T = 0.3 µs, R = 7.8 kΩ , C = 3 pF, X = 0.1, and Y = 1024 . Hence, R0 = –– 7.8 X103 3.0 X 103 Thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the A/D con- verter turns out to be approximately 3.0 kΩ . Tables 27.1 and 27.2 show output impedance values based on the LSB values.

3.0 X 10 –12 • ln

0.1

0.3 X 10-6

Figure 27.1 Anolog Input Pin and External Sensor Equivalent Circuit

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 214 27. Usage PrecautionpuorG08/C61M Tables 27.1 Output impedance values based on the LSB values (10-bit mode) Reference value Tables 27.2 Output impedance values based on the LSB values (8-bit mode) Reference value f(XIN) (MHz) Cycle (µs) Sampling time (µs) R (Kohm) C (pF) Resolution (LSB) R0max (Kohm) 10 0.1 0.3 (3 X cycle, Sample & hold bit is enabled) 7.8 3.0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 3.0 4.5 5.3 5.9 6.4 6.8 7.2 7.5 7.8 8.1 0.4 0.9 1.3 1.7 2.0 2.2 2.4 2.6 2.8 10 0.1 0.2 (2 X cycle, Sample & hold bit is enabled) 7.8 3.0 f(XIN) (MHz) Cycle (µs) Sampling time (µs) R (Kohm) C (pF) Resolution (LSB) R0max (Kohm) 10 0.1 0.3 (3 X cycle, Sample & hold bit is enabled) 7.8 3.0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 4.9 7.0 8.2 9.1 9.9 10.5 11.1 11.7 12.1 12.6 0.7 2.1 2.9 3.5 4.0 4.4 4.8 5.2 5.5 5.8 10 0.1 0.2 (2 X cycle, Sample & hold bit is enabled) 7.8 3.0

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 215 27. Usage PrecautionpuorG08/C61M Do not set address match interrupt during this period Interrupts (1) Setting the stack pointer

The value of the stack pointer is initialized to 00000016 immediately after reset. Accepting an interrupt before setting a value in the stack pointer may cause runaway. Be sure to set a value in the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack pointer at the beginning of a program. Regard- ing the first instruction immediately after reset, generating any interrupts including the NMI inter- rupt is prohibited. Set an even address to the stack pointer so that operating efficiency is increased. (2) The NMI interrupt
As for the NMI interrupt pin, an interrupt cannot be prohibited. Connect it to the VCC pin via a resistance (pulled-up) if unused.
The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time when the NMI interrupt is input.
Signals input to NMI pin require "L" level and "H" level of 2 clock + 300ns or more, from the operation clock of CPU. (3) Address match interrupt
Do not set the following addresses to the address match interrupt register. 1. The address of the starting instruction in an interrupt routine. 2. Any of the next 7 instructions addresses immediately after an instruction to clear an interrupt request bit of an interrupt control register or an instruction to rewrite an interrupt priority level to a smaller value. 3. Any of the next 3 instructions addresses immediately after an instruction to set the interrupt enable flag (I flag). 4. Any of the next 3 instructions addresses immediately after an instruction to rewrite a processor interrupt priority level (IPL) to a smaller value. Example 1) Interrupt_A: ; Interrupt A routine pushm R0,R1,R2,R3,A0,A1 ; <----
••• ; Example 2) mov.b #0,TA0IC ;Change TA0 interrupt priority level to a smaller value nop ; 1st instruction nop ; 2nd instruction nop ; 3rd instruction nop ; 4th instruction nop ; 5th instruction nop ; 6th instruction nop ; 7th instruction Example 3) fset I ; Set I flag ( interrupt enabled) nop ; 1st instruction nop ; 2nd instruction nop ; 3rd instruction Do not set address match interrupt to the start address of an interrupt instruction Do not set address match interrupt during this period

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 216 27. Usage PrecautionpuorG08/C61M Example 4) ldipl #0 ; Rewrite IPL to a smaller value nop ; 1st instruction nop ; 2nd instruction nop ; 3rd instruction

To return from an interrupt to the address set in an address match interrupt register using return instruction (reit or freit) To rewrite the interrupt control register within the interrupt routine, add the below processing to the end of the routine (immediately before the reit or freit instruction). Also, if multiple interrupts are enabled with other interrupts, add the below processing to the end of the interrupt that enables the multiple interrupts. If the interrupt control register is being rewritten within the non-maskable interrupt routine, add the below processing to the end of all interrupts. Additional process ; Execute after the register reset instruction (popm instruction) fclr U ; Select ISP (Unnecessary if the ISP has been selected) pushm R0 ; Store R0 register mov.w 6[SP],R0 ; Read FLG on stack (use "stc SVF,R0" when high-speed ; interrupt) ldc R0,FLG ; Set in FLG popm R0 ; Restore R0 register nop ; Dummy reit ; Interrupt completed (use freit when high-speed interrupt) Example 5) If rewriting the interrupt control register for interrupt B with the interrupt A routine and enabling multiple interrupts with interrupt C, the above processing is required at the end of the interrupt A and interrupt C routines. Interrupt A routine Interrupt_A: pushm R0,R1,R2,R3,A0,A1 ; Store registers
••• bclr 3,TA0IC ; Rewrite interrupt control register of interrupt B
••• popm R0,R1,R2,R3,A0,A1 ; Restore registers fclr U ; Select ISP (Unnecessary if the ISP has been selected) pushm R0 ; Store R0 register mov.w 6[SP],R0 ; Read FLG on stack ldc R0,FLG ; Set in FLG popm R0 ; Restore R0 register nop ; Dummy reit ; Interrupt completed Do not set address match interrupt during this period

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 217 27. Usage PrecautionpuorG08/C61M (4) External interrupt

Edge sense Either an “L” level or an “H ” level of at least 250 ns width is necessary for the signal input to pins INT0 to INT5 regardless of the CPU operation clock.
Level sense Either an “L” level or an “H ” level of 1 cycle of BCLK + at least 200 ns width is necessary for the signal input to pins INT0 to INT5 regardless of the CPU operation clock. (When XIN=20MHz and no division mode, at least 250 ns width is necessary.)
When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0". Figure 27.2 shows the procedure for changing the INT interrupt generate factor. Figure 27.2 Switching condition of INT interrupt request Set the polarity select bit Clear the interrupt request bit to “0” Set the interrupt priority level to level 1 to 7 (Enable the accepting of INT interrupt request) Set the interrupt priority level to level 0 (Disable INT interrupt) Interrupt C routine Interrupt_C: pushm R0,R1,R2,R3,A0,A1 ; Store registers fset I ; Multiple interrupt enabled
•••
••• popm R0,R1,R2,R3,A0,A1 ;Restore registers fclr U ; Select ISP (Unnecessary if the ISP has been selected) pushm R0 ; Store R0 register mov.w 6[SP],R0 ; Read FLG on stack ldc R0,FLG ; Set in FLG popm R0 ; Restore R0 register nop ; Dummy reit ; Interrupt completed

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 218 27. Usage PrecautionpuorG08/C61M (5) Rewrite the interrupt control register

When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET
When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit is not cleared sometimes. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : MOV DMAC (1) Do not clear the DMA request bit of the DMAi request cause select register. In M16C/80, when a DMA request is generated while the channel is disabled (Note), the DMA transfer is not executed and the DMA request bit is cleared automatically. Note :The DMA is disabled or the transfer count register is "0". (2) When DMA transfer is done by a software trigger, set DSR and DRQ of the DMAi request cause select register to "1" simultaneously using the OR instruction. e.g.) OR.B #0A0h, DMiSL ; DMiSL is DMAi request cause select register (3) When changing the DMAi request cause select bit of the DMAi request cause select register, set "1" to the DMA request bit, simultaneously. In this case, set the corresponding DMA channel to disabled before changing the DMAi request cause select bit. At least 26 cycles are needed from the instruction to write to the DMAi request cause select register to enable DMA. Example) When DMA request cause is changed to timer A0 and using DMA0 in single transfer after DMA initial setting push.w R0 ; Store R0 register stc DMD0, R0 ; Read DMA mode register 0 and.b #11111100b, R0L ; Clear DMA0 transfer mode select bit to "00" ldc R0, DMD0 ; DMA0 disabled mov.b #10000011b, DM0SL ; Select timer A0 ; (Write "1" to DMA request bit simultaneously) push.w R0 ; Sotre R0 register mov.w #6,R0 ; dummy_loop: sbjnz.w #1,R0,dummy_loop ; Dummy cycle pop.w R0 ; Restore R0 register or.b #00000001b, R0L ; Set DMA0 single transfer ldc R0, DMD0 ; DMA0 enabled pop.w R0 ; Restore R0 register At least 26 cycles are needed until DMA enabled.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 219 27. Usage PrecautionpuorG08/C61M (4) Recommended procedure for starting DMA transfer

When writing to the DMAi request cause register including overwriting the same value to the DMAi request cause register; 1. Disable the corresponding channel i DMA in DMA mode registers 0 and 1. 2. Set up the peripheral used as the source of the DMA transfer. However, the peripheral should remain disabled at this time. For example, when using UART0 transmit, disable UART0 transmit. 3. Set the DMAi request cause select register. At this time, write a '1' to the DMA request bit (bit 7) 4. Set the following SFR registers:
DMAiSFR address register
DMAI memory address reload register
DMAi memory address register
DMAi transfer count reload register
DMAi transfer count register 5. At this point, if the number of elapsed cycles are less than 26, add code (NOP's or other processing) to make up some time. 6. Enable the corresponding channel i DMA in the DMA mode registers 0 and 1. 7. Enable the peripheral used as the source of the DMA transfer. For example, when using UART0 transmit, enable UART0 transmit.
When not writing to the DMAi request cause register; 1. Disable the corresponding channel i DMA in the DMA mode registers 0 and 1. 2. Set up the peripheral used as the source of the DMA transfer. However, the peripheral should remain disabled at this time. For example, when using UART0 transmit, disable UART0 transmit. 3. Set up the following SFR registers:
DMAiSFR address register
DMAI memory address reload register
DMAi memory address register
DMAi transfer count reload register
DMAi transfer count register 4. Enable the corresponding channel i DMA in the DMA mode registers 0 and 1. 5. Enable the peripheral used as the source of the DMA transfer. For example, when using UART0 transmit, enable UART0 transmit. (5) Recommended procedure after completing DMA transfer
Disable the peripheral used as source of the DMA transfer to prevent generating a DMA request.
Disable the corresponding channel i DMA in the DMA mode registers 0 and 1.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 220 27. Usage PrecautionpuorG08/C61M Noise (1) A bypass capacitor should be inserted between Vcc-Vss line for reducing noise and latch-up Connect a bypass capacitor (approx. 0.1µF) between the Vcc and Vss pins using short wiring and thicker circuit traces. Precautions for using CLKOUT pin When using the Clock Output function of P53/CLKOUT pin (f8, f32 or fc output) in single chip mode, use port P57 as an input only port (port P57 direction register is "0"). Although port P57 may be set as an output port, it will become high impedance and will not output "H" or "L" levels. HOLD signal When P40 to P47 and P50 to P52 are set to output port (the direction register is "1") in single-chip mode, then the MCU is changed to microprocessor mode or memory expansion mode. Although the HOLD pin may be held "L", P40 to P47 (A16 to A23, CS0 to CS3, MA8 to MA12) and P50 to P52 (RD/WR/BHE, RD/WRL/WRH, CASL/CASH/DW) will not become high-impedance ports. When using the HOLD input while P40 to P47 and P50 to P52 are set as output ports in single-chip mode, you must first set all pins for P40 to P47 and P50 to P52 as input ports, then shift to microprocessor mode or memory expansion mode.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 221 27. Usage PrecautionpuorG08/C61M Reducing power consumption (1) When A/D conversion is not performed, select the Vref not connected with the Vref connect bit of A/D control register 1. When A/D conversion is performed, start the A/D conversion at least 1 µs or longer after connecting Vref. (2) When using AN4 (P104) to AN7 (P107), select the input disable of the key input interrupt signal with the key input interrupt disable bit of the function select register C . When selecting the input disable of the key input interrupt signal, the key input interrupt cannot be used. Also, the port cannot be input even if the direction register of P104 to P107 is set to input (the input result becomes undefined). When the input disable of the key input interrupt signal is selected, use all AN4 to AN7 as A/D inputs. (3) When ANEX0 and ANEX1 are used, select the input peripheral function disable with port P9 5 and P96 input peripheral function select bit of the function select register B3. When the input peripheral function disable is selected, the port cannot be input even if the port direc- tion register is set to input (the input result becomes undefined). Also, it is not possible to input a peripheral function except ANEX0 and ANEX1. (4) When D/A converter is not used, set output disabled with the D/A output enable bit of D/A control register and set the D/A register to "0016". (5) When D/A conversion is used, select the input peripheral function disabled with port P93 and P94 input peripheral function select bit of the function select register B3. When the input peripheral function disabled is selected, the port cannot be input even if the port direction register is set to input (the input result becomes undefined). Also, it is not possible to input a peripheral function. DRAM controller When shifting to self-refresh, select DRAM ignored by the DRAM space select bit. In the next instruction, simultaneously set the DRAM space select bit and self-refresh ON by self-refresh mode bit. Also, insert two NOPs after the instruction that sets the self-refresh mode bit to "1". Do not access external memory while operating in self-refresh. (All external memory space access is inhibited. ) When disabling self-refresh, simultaneously select DRAM ignored by the DRAM space select bit and self- refresh OFF by self-refresh mode bit. In the next instruction, set the DRAM space select bit. Do not access the DRAM space immediately after setting the DRAM space select bit. Example) One wait is selected by the wait select bit and 4MB is selected by the DRAM space select bit Shifting to self-refresh

•• mov.b #00000001b,DRAMCONT ;DRAM ignored, one wait is selected mov.b #10001011b,DRAMCONT ;Set self-refresh, select 4MB and one wait nop ;Two nops are needed nop ;
•• Disable self-refresh
•• mov.b #00000001b,DRAMCONT ;Disable self-refresh, DRAM ignored, one wait is ;selected mov.b #00001011b,DRAMCONT ;Select 4MB and one wait nop ;Inhibit instruction to access DRAM area nop
••

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 222 27. Usage PrecautionpuorG08/C61M Setting the registers The registers shown in Table 27.3 include indeterminate bit when read. Set immidiate to these registers. Store the content of the frequently used register to RAM, change the content of RAM, then transfer to the register. Table 27.3 The object registers Register name Symbol Address UART4 bit rate generator U4BRG 02F9 16 UART4 transfer buffer register U4TB 02FB 16, 02FA16 Dead time timer DTT 030C 16 Timer B2 interrupt occurrence frequency set counter ICTB2 030D 16 UART3 bit rate generator U3BRG 0329 16 UART3 transfer buffer register U3TB 032B 16, 032A16 UART2 bit rate generator U2BRG 0339 16 UART2 transfer buffer register U2TB 033B 16, 033A16 Up-down flag UDF 0344 16 Timer A0 register (Note) TA0 0347 16, 034616 Timer A1 register (Note) TA1 0349 16, 034816 Timer A2 register (Note) TA2 034B 16, 034A16 Timer A3 register (Note) TA3 034D 16, 034C16 Timer A4 register (Note) TA4 034F 16, 034E16 UART0 bit rate generator U0BRG 0361 16 UART0 transfer buffer register U0TB 0363 16, 036216 UART1 bit rate generator U1BRG 0369 16 UART1 transfer buffer register U1TB 036B 16, 036A16 Note: In one-shot timer mode and pulse widt modulation mode. External ROM version (144-pin version) The external ROM version is operated only in microprocessor mode, so be sure to perform the following:

Connect CNVss pin to Vcc. Notes on CNVSS pin reset at "H" level When the CNVSS pin is reset at "H" level, the contents of internal ROM cannot be read out.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 223 27. Usage PrecautionpuorG08/C61M Microprocesser mode or Memory expansion mode When the MCU enters wait mode while operating in memory expansion mode or microprocessor mode, a pin functioning as part of the address or data bus retains it's state on the bus before wait mode is entered. Shift to single-chip mode and output an arbitrary value in order to reduce current consumption. By shifting to single-chip mode, a pin which was functioning as part of the bus becomes a general- purpose port and can output an arbitrary value. Set the port registers and direction registers after shifting to single-chip mode (this implies that any control pins (CS,WR,RD,etc.. ) being used for access of an external device be changed as well). If the port registers and direction registers are set while in memory expansion mode or microprocessor mode, the operation will be ignored. This is similar when entering stop mode. Setting procedure is following. Operate in memory expansion mode or microprocessor mode Shift to single-chip mode Set the port register Set the direction register Enter the wait mode or stop mode Note . This program does not work in external area. Transfer a program to internal RAM and work on internal RAM. Note Figure 27.3 Setting procedure of the port register and direction register. Microprocessor If the software reset is executed when the CNVss pin is connected to Vcc to start up in microprocessor mode, write at least three NOP instructions following the writing instruction to the PM0 Register. example: mov.b #02H,PRCR bset 3,PM0 ; or "mov.b #8BH,PM0" (instruction to execute software reset) nop ; write at least three NOP instructions nop nop nop

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 224 27. Usage PrecautionpuorG08/C61M Flash memory version Bit 7 and bit 6 of the processor mode register 1 (address 000516) must be set to "112" and this setting should be done when the main clock is divided by 8. Rewrite program of external ROM version with built-in boot loader

Do not use interrupts in rewrite program.
Do not use absolute address jump instructions (JMP.A, JMPI.A) and absolute address subroutine call instructions (JSR.A, JSRI.A) in rewrite program.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 225 28. Electrical characteristicspuorG08/C61M Table 28.1 Absolute maximum ratings Note 1: Port P11 to P15 exist in 144-pin version. Note 2: Specify a product of -40 to 85°C to use it. VREF , XIN XOUT VO -0.3 to Vcc+0.3 -0.3 to Vcc+0.3 Pd Topr=25 -0.3 to 6.5 -0.3 to 6.5 V V VVI AVcc Vcc Tstg Topr mW V -65 to 150 500 -20 to 85 / -40 to 85 (Note 2) P30-P37, P40-P47, P50-P57, P60-P67, P72-P77, P80-P87, P00-P07, P10-P17, P20-P27, P30-P37,P40-P47, P50-P57, P60-P67,P72-P77, P80-P84, P00-P07, P10-P17, P20-P27, RESET, P90-P97, P100-P107, P110-P114, P120-P127, P130-P137, P140-P146, P150-P157, P86, P87, P90-P97, P100-P107, P110-P114, P120-P127, P130-P137, P140-P146, P150-P157, P70, P71 P70, P71 -0.3 to 6.5 -0.3 to 6.5 V V (maskROM : CNVSS , BYTE), VCC =AV CC VCC =AV CC C C C Symbol Parameter Condition Rated value Unit Supply voltage Analog supply voltage Input voltage Output voltage Power dissipation Operating ambient temperature Storage temperature (Note 1) (Note 1) 28. Electrical characteristics

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 226 28. Electrical characteristicspuorG08/C61M Note 1: The mean output current is the mean value within 100ms. Note 2: The total IOL (peak) for ports P0, P1, P2, P86, P87, P9, P10, P11, P14 and P15 must be 80mA max. The total IOH (peak) for ports P0, P1, P2, P86, P87, P9, P10, P11, P14 and P15 must be -80mA max. The total IOL (peak) for ports P3, P4, P5, P6, P7,P80 to P84, P12 and P13 must be 80mA max. The total IOH (peak) for ports P3, P4, P5, P6, P72 to P77, P80 to P84, P12 and P13 must be -80mA max. Note 3: Specify a product of -40 to 85°C to use it. Note 4: The specification of VIH and VIL of P87 is not when using as XCIN but when using programmable input port. Note 5: Port P11 to P15 exist in 144-pin version. Table 28.2 Recommended operating conditions (referenced to VCC = 2.7V to 5.5V at Topr = – 20 to 85oC / – 40 to 85oC(Note3) unless otherwise specified) P110-P114, P120-P127,P130-P137, P140-P146, P150-P157 (Note 5), P110-P114, P120-P127,P130-P137, P140-P146, P150-P157 (Note 5), Vcc VccAVcc V VIH IOH (avg) mA mA Vss AVss 0.8Vcc V V V V V V V 0.8Vcc 0.5Vcc Vcc Vcc Vcc 0.2Vcc 0.2Vcc (data input function during memory expansion and microprocessor modes) 0.16Vcc IOH (peak) P72-P77, P80-P87, P90-P97, P100-P107, -5.0 -10.0 P00-P07, P10-P17, P20-P27, P30-P37 (during single-chip mode) P00-P07, P10-P17, P20-P27, P30-P37 P00-P07, P10-P17, P20-P27, P30-P37 P40-P47, P50-P57, P60-P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107, P40-P47, P50-P57, P60-P67, 10.0 5.0 mA f (XIN) MHz IOL (peak) mA IOL (avg) f (XcIN) kHz5032.768 XIN, RESET, CNVSS , BYTE P70-P77, P80-P87, P90-P97, P100-P107, P40-P47, P50-P57, P60-P67, XIN, RESET, CNVSS , BYTE (data input function during memory expansion and microprocessor modes) P00-P07, P10-P17, P20-P27, P30-P37 (during single-chip mode) P00-P07, P10-P17, P20-P27, P30-P37 Vcc=4.2V to 5.5V P70 , 0.8Vcc 6.5 VP71 VIL Vcc=2.7V to 4.2V 0 MHz 10 Symbol Parameter Unit Standard Min Typ. Max. Supply voltage Analog supply voltage Supply voltage Analog supply voltage HIGH input voltage LOW input voltage HIGH peak output current HIGH average output current LOW peak output current LOW average output current Main clock input oscillation frequency Subclock oscillation frequency No wait 2.7 5.55.0 V P110-P114, P120-P127,P130-P137, P140-P146, P150-P157 (Note 5) P00-P07, P10-P17, P20-P27, P30-P37 P40-P47, P50-P57, P60-P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110-P114, P120-P127,P130-P137, P140-P146, P150-P157 (Note 5) P00-P07, P10-P17, P20-P27, P30-P37 P40-P47, P50-P57, P60-P67, P70-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110-P114, P120-P127,P130-P137, P140-P146, P150-P157 (Note 5) P00-P07, P10-P17, P20-P27, P30-P37 P40-P47, P50-P57, P60-P67, P70-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110-P114, P120-P127,P130-P137, P140-P146, P150-P157 (Note 5)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 227 28. Electrical characteristicspuorG08/C61M Table 28.3 A/D conversion characteristics (referenced to VCC = AVCC = VREF = 5V, Vss = AVSS = 0V at Topr = 25oC , f(XIN)=20MH Z unless otherwise specified) Table 28.4 D/A conversion characteristics (referenced to VCC = VREF = 5V, Vss = AVSS = 0V at Topr = 25oC , f(XIN)=20MH Z unless otherwise specified) kΩ Min. Typ. Max. tsu R O Resolution Absolute accuracy Setup time Output resistance Reference power supply input current Bits mA IVREF 1.0 1.5 Symbol Parameter Measuring condition Unit 20104 µs VREF = VCC = 5V(Note 1) Standard Note 1: DO f(XIN) in range of main clock input oscillation frequency prescribed with recommended operating conditions of table 28.2. Divide the fAD if f(XIN) exceeds 10 MHz, and make AD operation clock frequency (ØAD) equal to or lower than 10 MHz. And divide the fAD if VCC is less than 4.2V, and make AD operation clock frequency (ØAD) equal to or lower than fAD /2. Note 2 :A case without sample & hold function turn AD operation clock frequency (ØAD) into 250 kHz or more in addition to a limit of Note 1. Note 3 :Connect AVCC pin to VCC pin and apply the same electric potential. Note 1: This applies when using one D/A converter, with the D/A register for the unused D/A converter set to "0016". The A/D converter's ladder resistance is not included. Also, when D/A register contents are not "00 16" the current IVREF always flows even though Vref may have been set to be unconnected by the A/D control register. mA1.0VREF = VCC = 3V(Note 1) lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU .niM. pyT. xaM -n oituloseRV FER V= CC 01s tiB - )stib01(ycaruccaetulosbA V FER V= CC V5= NA 0 NAot 7 tupni tupni1XENA,0XENA 3±B SL pma-polanretxE edomnoitcennoc 7±B SL )stib8(ycaruccaetulosbAV FER V= CC V5=2 ±B SL ycaruccaetulosbA )stib8( dloh&elpmaS elbaliavatonnoitcnuf V FER V= CC ,V3= ∅ f=DA DA 2/2 ±B SL R REDDAL ecnatsisetreddaLV =FER V CC 010 4k Ω t VNOC emitnoisrevnoC )stib01( dloh&elpmaS elbaliavanoitcnuf V FER V= CC ,V5= ∅ zHM01=DA3 .3 µs t VNOC emitnoisrevnoC )stib8( dloh&elpmaS elbaliavanoitcnuf V FER V= CC ,V5= ∅ zHM01=DA8 .2 µs t VNOC emitnoisrevnoC )stib8( dloh&elpmaS elbaliavatonnoitcnuf V FER V= CC ,V3= ∅ f=DA DA zHM5=2/8 .9 µs t PMAS emitgnilpmaS 3.0 µs V FER egatlovecnerefeR V FER V= CC V5.5ot2.4=0 .2V V FER V= CC V5.5ot7.2=7 .2V V AI egatlovtupnigolanA 0V FER V

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 228 28. Electrical characteristicspuorG08/C61M Table 28.5 Electrical characteristics (referenced to VCC =5V, VSS =0V at Topr=25oC, f(XIN)=20MH Z unless otherwise specified) VCC = 5V XOUT XOUT IOH = - 5mA, VCC =5.0V IOH = - 1mA, VCC =5.0V IOH = - 200µA, VCC =5.0V IOH = - 0.5mA, VCC =5.0V IOL =5mA, VCC =5.0V IOL =1mA, VCC =5.0V IOL =200µA, VCC =5.0V IOL =0.5mA, VCC =5.0V HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER XCOUT TA0 OUT -TA4OUT ,NMI, INT0-INT5,AD TRG , CTS0-CTS4, CLK0-CLK4, HOLD, RDY, TA0IN-TA4IN, TB0IN-TB5IN, XCOUT HIGHPOWER LOWPOWER KI0-KI3,RxD0-RxD4, VOH VOH VOH VOL VOL VOL VT+-VT- Symbol HIGH output voltage HIGH output voltage HIGH output voltage HIGH output voltage LOW output voltage LOW output voltage LOW output voltage LOW output voltage Hysteresis With no load applied, VCC =5.0V With no load applied, VCC =5.0V With no load applied, VCC =5.0V With no load applied, VCC =5.0V Parameter Measuring condition RESET P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, P90-P97,P100-P107, P110-P114, P120-P127,P130-P137, P140-P146, P150-P157, XIN, RESET, CNVss, BYTE (Note 1) VI=5V, VCC =5.0V VI=0V, VCC =5.0V P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, P90-P97,P100-P107, P110-P114, P120-P127,P130-P137, P140-P146, P150-P157, XIN, RESET, CNVss, BYTE (Note 1) P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P72-P77, P80-P84, P86, P87, P90-P97,P100-P107, P110-P114, P120-P127, P130-P137, P140-P146, P150-P157 (Note 1) VI=0V, VCC =5.0V IIH IIL V RAM Icc VT+-VT- R fXIN R fXCIN R PULLUP Hysteresis HIGH input current LOW input current Pull-up resistance XIN XCIN Feedback resistance Feedback resistance RAM retention voltage f(XIN)=20MHz f(XCIN)=32kHz Power supply current When clock is stopped In single-chip mode, the output pins are open and other pins are V SS Square wave, no division Square wave f(XCIN)=32kHz Topr=85°C when clock is stopped Topr=25°C when clock is stopped When a WAIT instruction is executed P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110-P114, P120-P127, P130-P137, P140-P146, P150-P157 (Note 1) P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110-P114, P120-P127, P130-P137, P140-P146, P150-P157 (Note 1) P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110-P114, P120-P127, P130-P137, P140-P146, P150-P157 (Note 1) P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110-P114, P120-P127, P130-P137, P140-P146, P150-P157 (Note 1) SCL 2-SCL4, SDA 2-SDA 4 Mask ROM 128 KB version ROMless RAM 10 KB version(Note 2) Flash memory version Mask ROM 256 KB version ROMless RAM 24 KB version (Note 2) Mask ROM 128 KB version ROMless RAM 10 KB version(Note 2) Flash memory version Mask ROM 256 KB version ROMless RAM 24 KB version (Note 2) Mask ROM 128 KB version ROMless RAM 10KB version (Note 2) Flash memory version Mask ROM 256 KB version ROMless RAM 24KB version (Note 2) V V4.7 V 3.0 3.0 V2.0 0.45 V V 2.0 2.0 3.0 3.0 1.6 V 0.2 1.0 V V UnitStandard Min Typ. Max. 0.2 1.8 V 5.0 2.0 V mA 20.0 - 5.0 45.0 72.0 4.0 100.0 6.0

1.0 M Ω

M Ω 50.0 kΩ30.0 167.0 µA µA µA µA 50.0 80.0 7.0 mA 50.0 80.0 90.0 µA1.0 2.0 1.0 Measuring condition: VCC =5.0V VCC =5.0V Note 1: Port P11 to P15 exist in 144-pin version. Note 2: ROMless version exists in 144-pin version.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 229 28. Electrical characteristicspuorG08/C61M Timing requirements (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise specified) Table 28.6 External clock input (Note) (Note) (Note) Max. External clock rise time nstr Min. External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock fall time ns ns ns ns tc tw(H) tw(L) tf ParameterSymbol UnitStandard Min. Data input setup time nstsu(DB-BCLK) tsu(RDY-BCLK ) ParameterSymbol UnitMax. Standard nsRDY input setup time Data input hold time nsth(RD-DB) th(BCLK -RDY) nsRDY input hold time nsHOLD input setup timetsu(HOLD-BCLK ) nsHOLD input hold timeth(BCLK-HOLD ) Data input access time (RD standard, no wait) nstac1(RD-DB) ns ns tac2(RD-DB) tac3(RD-DB) Data input access time (RD standard, with wait) Data input access time (RD standard, when accessing multiplex bus area) nstd(BCLK-HLDA ) HLDA output delay time tac1(RD – DB) = f(BCLK) X 2 – 35109 [ns] tac2(RD – DB) = f(BCLK) X 2 – 3510 X m [ns] (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively) (Note)Data input access time (AD standard, CS standard, no wait) nstac1(AD-DB) (Note) nstac2(AD-DB) Data input access time (AD standard, CS standard, with wait) (Note) nstac3(AD-DB) Data input access time (AD standard, CS standard, when accessing multiplex bus area) tac1(AD – DB) = f(BCLK) – 3510 9 [ns] tac2(AD – DB) = – 3510 X n [ns] (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively) tac3(RD – DB) = f(BCLK) X 2 – 3510 X m [ns] (m=3 and 5 when 2 wait and 3 wait, respectively) tac3(AD – DB) = f(BCLK) X 2 – 3510 X n [ns] (n=5 and 7 when 2 wait and 3 wait, respectively) Note: Calculated according to the BCLK frequency as follows: Note that inserting wait or using lower operation frequency f(BCLK) is needed when calculated value is negative. (Note) nstac4(CAS-DB) Data input access time (CAS standard, DRAM access) (Note) nstac4(RAS-DB) Data input access time (RAS standard, DRAM access) (Note) nstac4(CAD-DB) Data input access time (CAD standard, DRAM access) tac4(RAS – DB) = f(BCLK) X 2 – 3510 X m [ns] (m=3 and 5 when 1 wait and 2 wait, respectively) tac4(CAS – DB) = – 3510 X n [ns] (n=1 and 3 when 1 wait and 2 wait, respectively) tac4(CAD – DB) = f(BCLK) – 3510 X l [ns] (l=1 and 2 when 1 wait and 2 wait, respectively) f(BCLK) f(BCLK) X 2 ns0th(CAS -DB) Data input hold time VCC = 5V Table 28.7 Memory expansion and microprocessor modes

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 230 puorG08/C61M 28. Electrical characteristics Standard Max. nsTAiIN input LOW pulse widthtw(TAL) Min. ns ns Unit Standard Max.Min. ns ns ns Unit Standard Max.Min. ns ns ns Unit Standard Max.Min. ns ns Unit Standard Max.Min. ns ns ns Unit ns ns TAiIN input HIGH pulse widthtw(TAH) ParameterSymbol TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width tc(TA) tw(TAH) tw(TAL) Symbol Parameter TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width tc(TA) tw(TAH) tw(TAL) Symbol Parameter tw(TAH) tw(TAL) Symbol Parameter TAiIN input HIGH pulse width TAiIN input LOW pulse width Symbol Parameter tc(TA) TAiIN input cycle time TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) 100 400 200 200 200 100 100 100 100 2000 1000 1000 400 400 Timing requirements (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise specified) Table 28.8 Timer A input (counter input in event counter mode) Table 28.9 Timer A input (gating input in timer mode) Table 28.10 Timer A input (external trigger input in one-shot timer mode) Table 28.11 Timer A input (external trigger input in pulse width modulation mode) Table 28.12 Timer A input (up/down input in event counter mode) VCC = 5V

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 231 28. Electrical characteristicspuorG08/C61M ns ns ns ns ns ns ns Standard Max.Min. TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) ns ns ns tc(TB) tw(TBH) tw(TBL) ParameterSymbol Unit tc(TB) tw(TBL) tw(TBH) ns ns ns TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges) TBiIN input cycle time (counted on both edges) Standard Max.Min. ns ns tc(TB) tw(TBH) Symbol Parameter Unit tw(TBL) ns TBiIN input HIGH pulse width TBiIN input cycle time TBiIN input LOW pulse width Standard Max.Min. ns ns tc(TB) Symbol Parameter Unit tw(TBL) ns tw(TBH) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Standard Max.Min. ns ns tc(AD) tw(ADL) Symbol Parameter Unit AD TRG input cycle time (trigger able minimum) AD TRG input LOW pulse width Standard Max.Min. ns ns tw(INH) tw(INL) Symbol Parameter Unit INTi input LOW pulse width INTi input HIGH pulse width Standard Max.Min. CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width tc(CK) tw(CKH) tw(CKL) ParameterSymbol Unit td(C-Q) tsu(D-C) th(C-Q) TxDi hold time RxDi input setup time TxDi output delay time th(C-D) RxDi input hold time 100 200 400 200 200 400 200 200 1000 125 250 250 200 100 100 Timing requirements (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise specified) Table 28.13 Timer B input (counter input in event counter mode) Table 28.14 Timer B input (pulse period measurement mode) Table 28.15 Timer B input (pulse width measurement mode) Table 28.16 A/D trigger input Table 28.17 Serial I/O VCC = 5V Table 28.18 External interrupt INTi inputs

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 232 puorG08/C61M 28. Electrical characteristics Symbol StandardMeasuring condition Max.Min.Parameter Unit td(BCLK-AD) Address output delay time 18 ns th(BCLK-AD) Address output hold time (BCLK standard) -3 ns th(BCLK-CS) Chip select output hold time (BCLK standard) -3 ns td(BCLK-ALE) ALE signal output delay time 18 ns th(BCLK-ALE) ALE signal output hold time – 2 ns td(BCLK-RD) RD signal output delay time 10 ns th(BCLK-RD) RD signal output hold time -5 ns td(BCLK-WR) WR signal output delay time 18 ns th(BCLK-WR) WR signal output hold time -3 ns th(WR-DB) Data output hold time (WR standard) (Note 1) ns td(DB-WR) Data output delay time (WR standard) ns (Note 1) Note 1: Calculated according to the BCLK frequency as follows: td(DB – WR) = f(BCLK) 10 9 – 20 [ns] td(BCLK-CS) Chip select output delay time 18 ns th(RD-AD) Address output hold time (RD standard) 0 ns th(WR-AD) Address output hold time (WR standard) (Note 1) ns th(RD-CS) Chip select output hold time (RD standard) 0 ns th(WR-CS) Chip select output hold time (WR standard) (Note 1) ns th(WR – DB) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] tw(WR) WR signal width ns(Note 1) tw(WR) = f(BCLK) X 2 10 9 – 15 [ns] Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise specified) VCC = 5V Figure 28.1 Table 28.19 Memory expansion mode and microprocessor mode (no wait)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 233 28. Electrical characteristicspuorG08/C61M Symbol StandardMeasuring condition Max.Min.Parameter Unit td(BCLK-AD) Address output delay time 18 ns th(BCLK-AD) Address output hold time (BCLK standard) – 3 ns th(BCLK-CS) Chip select output hold time (BCLK standard) – 3 ns td(BCLK-ALE) ALE signal output delay time 18 ns th(BCLK-ALE) ALE signal output hold time – 2 ns td(BCLK-RD) RD signal output delay time 10 ns th(BCLK-RD) RD signal output hold time – 5 ns td(BCLK-WR) WR signal output delay time 18 ns th(BCLK-WR) WR signal output hold time – 3 ns th(WR-DB) Data output hold time (WR standard) (Note 1) ns td(DB-WR) Data output delay time (WR standard) ns(Note 1) Note 1: Calculated according to the BCLK frequency as follows: [ns] (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively) td(BCLK-CS) Chip select output delay time 18 ns th(RD-AD) Address output hold time (RD standard) 0 ns th(WR-AD) Address output hold time (WR standard) (Note 1) ns th(RD-CS) Chip select output hold time (RD standard) 0 ns th(WR-CS) Chip select output hold time (WR standard) (Note 1) ns td(DB – WR) = f(BCLK)

10 X n9

– 20 th(WR – DB) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] tw(WR) WR signal width (Note 1) ns [ns] (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively)tw( WR) = 10 X n9 – 15f(BCLK ) X 2 Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise specified) VCC = 5V Figure 28.1 Table 28.20 Memory expansion mode and microprocessor mode (with wait, accessing external memory)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 234 puorG08/C61M 28. Electrical characteristics Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise specified) VCC = 5V Table 28.21 Memory expansion mode and microprocessor mode (with wait, accessing external memory, multiplex bus area selected) Figure 28.1 Symbol StandardMeasuring condition Max.Min.Parameter Unit td(BCLK-AD) Address output delay time 18 ns th(BCLK-AD) Address output hold time (BCLK standard) -3 ns th(BCLK-CS) Chip select output hold time (BCLK standard) -3 ns td(BCLK-ALE) ALE signal output delay time (BCLK standard) 18 ns th(BCLK-ALE) ALE signal output hold time (BCLK standard) – 2 ns td(BCLK-RD) RD signal output delay time 18 ns th(BCLK-RD) RD signal output hold time -5 ns td(BCLK-WR) WR signal output delay time 18 ns th(BCLK-WR) WR signal output hold time -3 ns th(WR-DB) Data output hold time (WR standard) (Note 1) ns td(DB-WR) Data output delay time (WR standard) ns(Note 1) Note 1: Calculated according to the BCLK frequency as follows: td(DB – WR) = 10 X m – 25 [ns] (m=3 and 5 when 2 wait and 3 wait, respectively) td(BCLK-CS) Chip select output delay time 18 ns th(RD-AD) Address output hold time (RD standard) (Note 1) ns th(WR-AD) Address output hold time (WR standard) (Note 1) ns th(RD-CS) Chip select output hold time (RD standard) ns th(WR-CS) Chip select output hold time (WR standard) (Note 1) ns th(RD – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(RD – CS) = f(BCLK) X 2 10 9 – 10 [ns] td(AD-ALE) ALE signal output delay time (address standard) ns th(ALE-AD) ALE signal output hold time (address standard) ns tdz(RD-AD) Address output flowting start time ns (Note 1) (Note 1) th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – DB) = f(BCLK) X 2 10 9 – 10 [ns] td(AD – ALE) = f(BCLK) X 2 10 9 – 23 [ns] th(ALE – AD) = f(BCLK) X 2 10 9 – 10 [ns] f(BCLK) X 2 (Note 1) th(BCLK-DB) Data output hold time (BCLK standard) -5 ns

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 235 28. Electrical characteristicspuorG08/C61M Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = 25oC unless otherwise specified) VCC = 5V Table 28.22 Memory expansion mode and microprocessor mode (with wait, accessing external memory, DRAM area selected) Figure 28.1 Symbol StandardMeasuring condition Max.Min.Parameter Unit td(BCLK-RAD) Row address output delay time 18 ns th(BCLK-RAD) Row address output hold time (BCLK standard) -3 ns td(BCLK-RAS) RAS output delay time (BCLK standard) ns tsu(DB-CAS) CAS after DB output setup time ns th(BCLK-DB) DB signal output hold time (BCLK standard) (Note 1) ns td(BCLK-CAS) CAS output delay time (BCLK standard) ns th(BCLK-CAS) CAS output hold time (BCLK standard) (Note 1) ns td(BCLK-DW) Data output delay time (BCLK standard) ns Note 1: Calculated according to the BCLK frequency as follows: tsu(CAS – RAS) = f(BCLK ) X 2 – 13 [ns] th(RAS-RAD) Row address output hold time after RAS output ns td(BCLK-CAD) String address output delay time ns th(BCLK-CAD) String address output hold time (BCLK standard) (Note 1) ns th(BCLK-RAS) RAS output hold time (BCLK standard) ns tRP RAS "H" hold time ns th(RAS – RAD) = f(BCLK) X 2 10 9 – 13 [ns] tRP = f(BCLK) X 2

10 X 39

– 20 [ns] tsu(CAS-RAS) CAS before RAS setup time (refresh) ns (Note 1) tsu(DB – CAS) = f(BCLK) 10 9 – 20 [ns] th(BCLK-DW) Data output hold time (BCLK standard) ns-5

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 236 puorG08/C61M 28. Electrical characteristics Figure 28.1 Port P0 to P15 measurement circuit P10 30pF P14 P13 P12 P15 P11 Note: Port P11 to P15 exist in 144-pin version. (Note)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 237 28. Electrical characteristicspuorG08/C61M BCLK ALE -2ns.min RD 10ns.max -5ns.min Hi-ZDB 0ns.min 0ns.min td(BCLK-ALE) th(BCLK-ALE) tsu(DB-BCLK) td(BCLK-RD) 26ns.min*1 CSi td(BCLK-CS) 18ns.max*1 ADi th(BCLK-AD) -3ns.min th(BCLK-CS) -3ns.min BHE tcyc td(BCLK-AD) 0ns.min tac1(AD-DB)*2 tac1(RD-DB)=(tcyc/2-35)ns.max tac1(AD-DB)=(tcyc-35)ns.max WR,WRL, WRH 18ns.max -3ns.min BCLK CSi td(BCLK-CS) 18ns.max ADi td(BCLK-AD) 18ns.max td(BCLK-ALE) -3ns.min -3ns.min tcyc BHE DBi td(BCLK-WR) ALE 18ns.max -2ns.min th(WR-DB) *3 td(DB-WR) =(tcyc-20)ns.min th(WR-DB) =(tcyc/2-10)ns.min th(WR-AD) =(tcyc/2-10)ns.min th(WR-CS) =(tcyc/2-10)ns.min tw(WR) =(tcyc/2-15)ns.min Vcc=5V th(BCLK-RD) th(RD-DB) th(RD-AD) th(RD-CS) th(BCLK-WR) th(BCLK-ALE) th(BCLK-AD) th(BCLK-CS) th(WR-CS) *3 th(WR-AD) *3 tw(WR) *3 tac1(RD-DB)*2 18ns.max*1 Read Timing Write Timing ( Written by 2 cycles in selecting no wait) *3:It depends on operation frequency. Measuring conditions

VCC =5V±10%
Input timing voltage :Determined with VIH=2.5V, VIL=0.8V
Output timing voltage :Determined with VOH =2.0V, VOL =0.8V Memory expansion Mode and Microprocessor Mode (without wait) *1:It is a guarantee value with being alone. 35ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK). *2:It depends on operation frequency. 18ns.max td(DB-WR) *3 Figure 28.2 VCC =5V timing diagram (1)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 238 28. Electrical characteristicspuorG08/C61M BCLK ALE 18ns.max -2ns.min RD 10ns.max -5ns.min Hi-ZDB 0ns.min 0ns.min td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) 26ns.min*1 tac2(RD-DB)*2 CSi td(BCLK-CS) 18ns.max*1 ADi 18ns.max*1 th(BCLK-AD) -3ns.min th(BCLK-CS) -3ns.min BHE tcyc td(BCLK-AD) tac2(AD-DB)*2 tac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.) tac2(AD-DB)=(tcyc x n-35)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.) WR,WRL, WRH 18ns.max -3ns.min BCLK CSi 18ns.max ADi 18ns.max -3ns.min -3ns.min tcyc BHE DBi td(BCLK-WR) ALE 18ns.max -2ns.min Vcc=5V th(BCLK-RD) th(RD-DB)tsu(DB-BCLK) th(RD-CS) 0ns.min td(BCLK-CS) td(BCLK-AD) td(BCLK-ALE) th(BCLK-AD) th(BCLK-CS) th(WR-CS)*3 td(DB-WR)*3 th(WR-DB)*3 th(WR-AD)*3 td(DB-WR) =(tcyc x n-20)ns.min (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.) t h(WR-DB) =(tcyc/2-10)ns.min th(WR-AD) =(tcyc/2-10)ns.min th(WR-CS) =(tcyc/2-10)ns.min tw(WR) =(tcyc/2 x n-15)ns.min (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.) *3:It depends on operation frequency. Measuring conditions

VCC =5V±10%
Input timing voltage :Determined with VIH=2.5V, VIL=0.8V
Output timing voltage :Determined with VOH =2.0V, VOL =0.8V *1:It is a guarantee value with being alone. 35ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK). *2:It depends on operation frequency. th(BCLK-ALE) Read Timing Write Timing Memory expansion Mode and Microprocessor Mode (with 1 wait) th(RD-AD) tw(WR)*3 th(BCLK-WR) Figure 28.3 VCC =5V timing diagram (2)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 239 28. Electrical characteristicspuorG08/C61M BCLK ALE 18ns.max -2ns.min RD 10ns.max -5ns.min Hi-ZDB 0ns.min 0ns.min td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) 26ns.min*1 tac2(RD-DB)*2 CSi td(BCLK-CS) 18ns.max*1 ADi 18ns.max*1 th(BCLK-AD) -3ns.min th(BCLK-CS) -3ns.min BHE tcyc td(BCLK-AD) tac2(AD-DB)*2 tac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.) tac2(AD-DB)=(tcyc x n-35)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.) WR,WRL, WRH 18ns.max -3ns.min BCLK CSi 18ns.max ADi 18ns.max -3ns.min -3ns.min tcyc BHE DBi td(BCLK-WR) ALE 18ns.max -2ns.min Vcc=5V th(BCLK-RD) th(RD-DB) th(RD-AD) tsu(DB-BCLK) th(RD-CS) 0ns.min th(BCLK-WR) td(BCLK-CS) td(BCLK-AD) td(BCLK-ALE) th(BCLK-AD) th(BCLK-CS) th(WR-CS)*3 td(DB-WR)*3 th(WR-DB)*3 th(WR-AD)*3 td(DB-WR) =(tcyc x n-20)ns.min (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.) t h(WR-DB) =(tcyc/2-10)ns.min th(WR-AD) =(tcyc/2-10)ns.min th(WR-CS) =(tcyc/2-10)ns.min tw(WR) =(tcyc/2 x n-15)ns.min (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.) *3:It depends on operation frequency. Measuring conditions

VCC =5V±10%
Input timing voltage :Determined with VIH=2.5V, VIL=0.8V
Output timing voltage :Determined with VOH =2.0V, VOL =0.8V *1:It is a guarantee value with being alone. 35ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK). *2:It depends on operation frequency. th(BCLK-ALE) Read Timing Write Timing Memory expansion Mode and Microprocessor Mode (with 2 wait) tw(WR)*3 Figure 28.4 VCC =5V timing diagram (3)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 240 28. Electrical characteristicspuorG08/C61M Figure 28.5 VCC =5V timing diagram (4) BCLK ALE 18ns.max -2ns.min RD 10ns.max -5ns.min Hi-ZDB 0ns.min 0ns.min td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) 26ns.min*1 tac2(RD-DB)*2 CSi td(BCLK-CS) 18ns.max*1 ADi 18ns.max*1 th(BCLK-AD) -3ns.min th(BCLK-CS) -3ns.min BHE tcyc td(BCLK-AD) tac2(AD-DB)*2 WR,WRL, WRH 18ns.max -3ns.min BCLK CSi 18ns.max ADi 18ns.max -3ns.min -3ns.min tcyc BHE DBi td(BCLK-WR) ALE 18ns.max -2ns.min Vcc=5V th(BCLK-RD) th(RD-DB) th(RD-AD) tsu(DB-BCLK) th(RD-CS) 0ns.min th(BCLK-WR) td(BCLK-CS) td(BCLK-AD) td(BCLK-ALE) th(BCLK-AD) th(BCLK-CS) th(WR-CS) *3 tw(WR) *3 td(DB-WR) *3 th(WR-DB) *3 th(WR-AD) *3 th(BCLK-ALE) Read Timing Write Timing Memory expansion Mode and Microprocessor Mode (with 3 wait) *1:It is a guarantee value with being alone. 35ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK). *2:It depends on operation frequency. tac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.) tac2(AD-DB)=(tcyc x n-35)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.) *3:It depends on operation frequency. td(DB-WR) =(tcyc x n-20)ns.min (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.) t h(WR-DB) =(tcyc/2-10)ns.min th(WR-AD) =(tcyc/2-10)ns.min th(WR-CS) =(tcyc/2-10)ns.min tw(WR) =(tcyc/2 x n-15)ns.min (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.) Measuring conditions

VCC =5V ±10%
Input timing voltage :Determined with VIH=2.5V, VIL=0.8V
Output timing voltage :Determined with VOH =2.0V, VOL =0.8V

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 241 28. Electrical characteristicspuorG08/C61M BCLK CSi 18ns.max ADi 18ns.max RD 18ns.max -5ns.min th(BCLK-AD) -3ns.min -3ns.min BHE ADi /DBi 0ns.min 18ns.max -3ns.min BCLK CSi 18ns.max ADi 18ns.max -3ns.min -3ns.mintcyc BHE -5ns.min ADi /DBi Data output WR,WRL, WRH Address AddressData input 26ns.min td(BCLK-RD) th(WR-CS) *2 Address td(AD-ALE)*2 Address tsu(DB-BCLK) tac3(RD-DB)*1 tdz(RD-AD) 8ns.max ALE -2ns.min td(BCLK-ALE) 18ns.max td(AD-ALE)=(tcyc/2-23)ns.min th(ALE-AD)=(tcyc/2-10)ns.min, th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min tac3(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 and 5 when 2 wait and 3 wait, respectively.) tac3(AD-DB)=(tcyc/2 x n-35)ns.max (n=5 and 7 when 2 wait and 3 wait, respectively.) ALE 18ns.max -2ns.mintd(BCLK-ALE) th(ALE-AD)*2 td(AD-ALE)=(tcyc/2-23)ns.min th(ALE-AD)=(tcyc/2-10)ns.min, th(WR-AD) =(tcyc/2-10)ns.min th(WR-CS) =(tcyc/2-10)ns.min, th(WR-DB) =(tcyc/2-10)ns.min td(DB-WR) =(tcyc/2 x m-25)ns.min (m=3 and 5 when 2 wait and 3 wait, respectively.) Vcc=5V td(BCLK-CS) td(AD-ALE)*1 th(ALE-AD)*1 th(BCLK-RD) th(RD-AD)*1 th(RD-DB) td(BCLK-AD) th(BCLK-CS) th(RD-CS)*1 td(BCLK-WR) th(BCLK-WR) td(BCLK-CS) td(BCLK-AD) th(BCLK-AD) th(BCLK-CS) th(WR-AD) *2 th(BCLK-DB) td(DB-WR) *2 th(WR-DB) *2 th(BCLK-ALE) th(BCLK-ALE) tcyc *2:It depends on operation frequency. Measuring conditions

VCC =5V±10%
Input timing voltage :Determined with VIH=2.5V, VIL=0.8V
Output timing voltage :Determined with VOH =2.0V, VOL =0.8V *1:It depends on operation frequency. Read Timing Write Timing Memory expansion Mode and Microprocessor Mode (When accessing external memory area with 2 wait, and select multiplexed bus)) tac3(AD-DB)*1 Figure 28.6 VCC =5V timing diagram (5)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 242 28. Electrical characteristicspuorG08/C61M BCLK CSi 18ns.max ADi 18ns.max RD 18ns.max -5ns.min th(BCLK-AD) -3ns.min -3ns.min BHE ADi /DBi 0ns.min 18ns.max -3ns.min BCLK CSi 18ns.max ADi 18ns.max -3ns.min -3ns.mintcyc BHE -5ns.min ADi /DBi Data output WR,WRL, WRH Address AddressData input 26ns.min td(BCLK-RD) th(WR-CS) *2 Address td(AD-ALE)*2 Address tsu(DB-BCLK) tac3(RD-DB)*1 tdz(RD-AD) 8ns.max ALE -2ns.min td(BCLK-ALE) 18ns.max td(AD-ALE)=(tcyc/2-23)ns.min th(ALE-AD)=(tcyc/2-10)ns.min, th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min tac3(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 and 5 when 2 wait and 3 wait, respectively.) tac3(AD-DB)=(tcyc/2 x n-35)ns.max (n=5 and 7 when 2 wait and 3 wait, respectively.) ALE 18ns.max -2ns.min td(BCLK-ALE) th(ALE-AD)*2 td(AD-ALE)=(tcyc/2-23)ns.min th(ALE-AD)=(tcyc/2-10)ns.min, th(WR-AD) =(tcyc/2-10)ns.min th(WR-CS) =(tcyc/2-10)ns.min, th(WR-DB) =(tcyc/2-10)ns.min td(DB-WR) =(tcyc/2 x m-25)ns.min (m=3 and 5 when 2 wait and 3 wait, respectively.) Vcc=5V td(BCLK-CS) td(AD-ALE)*1 th(ALE-AD)*1 th(BCLK-RD) th(RD-AD)*1 th(RD-DB) td(BCLK-AD) th(BCLK-CS) th(RD-CS)*1 td(BCLK-WR) th(BCLK-WR) td(BCLK-CS) td(BCLK-AD) th(BCLK-AD) th(BCLK-CS) th(WR-AD) *2 th(BCLK-DB) td(DB-WR) *2 th(WR-DB) *2 th(BCLK-ALE) th(BCLK-ALE) tcyc *2:It depends on operation frequency. Measuring conditions

VCC =5V±10%
Input timing voltage :Determined with VIH=2.5V, VIL=0.8V
Output timing voltage :Determined with VOH =2.0V, VOL =0.8V *1:It depends on operation frequency. Read Timing Write Timing Memory expansion Mode and Microprocessor Mode (When accessing external memory area with 3 wait, and select multiplexed bus)) tac3(AD-DB)*1 Figure 28.7 VCC =5V timing diagram (6)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 243 28. Electrical characteristicspuorG08/C61M Figure 28.8 VCC =5V timing diagram (7) BCLK DW DB MAi td(BCLK-RAS) + tsu(DB-BCLK) td(BCLK-CAS) + tsu(DB-BCLK) td(BCLK-CAD) + tsu(DB-BCLK) tac4(RAS-DB)=(tcyc/2 x m-35)ns.max (m=3 and 5 when 1 wait and 2 wait, respectively.) tac4(CAS-DB)=(tcyc/2 x n-35)ns.max (n=1 and 3 when 1 wait and 2 wait, respectively.) tac4(CAD-DB)=(tcyc x l-35)ns.max (l=1 and 2 when 1 wait and 2 wait, respectively.) th(RAS-RAD) =(tcyc/2-13)ns.min tRP =(tcyc/2 x 3-20)ns.min Vcc=5V RAS CASL CASH Hi-Z tac4(CAS-DB)*2 18ns.max th(BCLK-CAD) -3ns.min tcyc td(BCLK-RAD) tac4(RAS-DB)*2 Row address String address th(BCLK-RAD) -3ns.min 18ns.max*1 td(BCLK-CAD) 18ns.max*1 td(BCLK-RAS) 18ns.max*1 td(BCLK-CAS) th(RAS-RAD)*2 tRP*2 tac4(CAD-DB)*2 th(BCLK-RAS) -3ns.min th(BCLK-CAS) -3ns.min 0ns.min tsu(DB-BCLK) 26ns.min*1 th(CAS-DB) *2:It depends on operation frequency. Measuring conditions

VCC =5V±10%
Input timing voltage :Determined with VIH=2.5V, VIL=0.8V
Output timing voltage :Determined with VOH =2.0V, VOL =0.8V Read Timing Memory expansion Mode and Microprocessor Mode (When accessing DRAM area with 1 wait) *1:It is a guarantee value with being alone. 35ns.max garantees as follows:

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 244 28. Electrical characteristicspuorG08/C61M Figure 28.9 VCC =5V timing diagram (8) BCLK DW DB MAi th(RAS-RAD) =(tcyc/2-13)ns.min tRP =(tcyc/2 x 3-20)ns.min tsu(DB-CAS)=(tcyc-20)ns.min Vcc=5V RAS CASL CASH Hi-Z th(BCLK-DB) -7ns.min 18ns.max th(BCLK-CAD) -3ns.min tcyc td(BCLK-RAD) th(BCLK-RAD) -3ns.min 18ns.max td(BCLK-CAD) 18ns.max td(BCLK-RAS) 18ns.max td(BCLK-CAS) th(RAS-RAD) *1 tRP *1 18ns.max td(BCLK-DW) tsu(DB-CAS)*1 th(BCLK-RAS) -3ns.min th(BCLK-CAS) -3ns.min th(BCLK-DW) -5ns.min Row address String address *1:It depends on operation frequency. Measuring conditions

VCC =5V±10%
Input timing voltage :Determined with VIH=2.5V, VIL=0.8V
Output timing voltage :Determined with VOH =2.0V, VOL =0.8V Write Timing Memory expansion Mode and Microprocessor Mode (When accessing DRAM area with 1 wait)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 245 28. Electrical characteristicspuorG08/C61M Figure 28.10 VCC =5V timing diagram (9) BCLK DW DB MAi td(BCLK-RAS) + tsu(DB-BCLK) td(BCLK-CAS) + tsu(DB-BCLK) td(BCLK-CAD) + tsu(DB-BCLK) tac4(RAS-DB)=(tcyc/2 x m-35)ns.max (m=3 and 5 when 1 wait and 2 wait, respectively.) tac4(CAS-DB)=(tcyc/2 x n-35)ns.max (n=1 and 3 when 1 wait and 2 wait, respectively.) tac4(CAD-DB)=(tcyc x l-35)ns.max (l=1 and 2 when 1 wait and 2 wait, respectively.) th(RAS-RAD) =(tcyc/2-13)ns.min tRP =(tcyc/2 x 3-20)ns.min Vcc=5V RAS CASL CASH Hi-Z tac4(CAS-DB)*2 18ns.max th(BCLK-CAD) -3ns.min tcyc td(BCLK-RAD) tac4(RAS-DB)*2 Row address String address th(BCLK-RAD) -3ns.min 18ns.max*1 td(BCLK-CAD) 18ns.max*1 td(BCLK-RAS) 18ns.max*1 td(BCLK-CAS) th(RAS-RAD)*2 tRP*2 tac4(CAD-DB)*2 th(BCLK-RAS) -3ns.min th(BCLK-CAS) -3ns.min 0ns.min tsu(DB-BCLK) 26ns.min*1 th(CAS-DB) *2:It depends on operation frequency. Measuring conditions

VCC =5V±10%
Input timing voltage :Determined with VIH=2.5V, VIL=0.8V
Output timing voltage :Determined with VOH =2.0V, VOL =0.8V Read Timing Memory expansion Mode and Microprocessor Mode (When accessing DRAM area with 2 wait) *1:It is a guarantee value with being alone. 35ns.max garantees as follows:

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 246 28. Electrical characteristicspuorG08/C61M Figure 28.11 VCC =5V timing diagram (10) BCLK DW DB MAi th(RAS-RAD) =(tcyc/2-13)ns.min tRP =(tcyc/2 x 3-20)ns.min tsu(DB-CAS)=(tcyc-20)ns.min Vcc=5V RAS CASL CASH Hi-Z th(BCLK-DB) -7ns.min 18ns.max th(BCLK-CAD) -3ns.min tcyc td(BCLK-RAD) th(BCLK-RAD) -3ns.min 18ns.max td(BCLK-CAD) 18ns.max td(BCLK-RAS) 18ns.max td(BCLK-CAS) th(RAS-RAD)*1 tRP*1 18ns.max td(BCLK-DW) tsu(DB-CAS)*1 th(BCLK-RAS) -3ns.min th(BCLK-CAS) -3ns.min th(BCLK-DW) -5ns.min Row address String address *1:It depends on operation frequency. Measuring conditions

VCC =5V±10%
Input timing voltage :Determined with VIH=2.5V, VIL=0.8V
Output timing voltage :Determined with VOH =2.0V, VOL =0.8V Write Timing Memory expansion Mode and Microprocessor Mode (When accessing DRAM area with 2 wait)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 247 28. Electrical characteristicspuorG08/C61M Figure 28.12 VCC =5V timing diagram (11) tcyc 18ns.max td(BCLK-RAS) 18ns.max td(BCLK-CAS) th(BCLK-RAS) -3ns.min th(BCLK-CAS) -3ns.min tsu(CAS-RAS)*1 18ns.max tcyc td(BCLK-CAS) tsu(CAS-RAS)*1 th(BCLK-RAS) -3ns.min th(BCLK-CAS) -3ns.min 18ns.max td(BCLK-RAS) BCLK DW tsu(CAS-RAS)=(tcyc/2-13)ns.min Vcc=5V RAS CASL CASH BCLK DW tsu(CAS-RAS)=(tcyc/2-13)ns.min RAS CASL CASH *1:It depends on operation frequency. Measuring conditions

VCC =5V±10%
Input timing voltage :Determined with VIH=2.5V, VIL=0.8V
Output timing voltage :Determined with VOH =2.0V, VOL =0.8V Refresh Timing (CAS before RAS refresh) Memory expansion Mode and Microprocessor Mode *1:It depends on operation frequency. Refresh Timing (Self-refresh)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 248 28. Electrical characteristicspuorG08/C61M Figure 28.13 VCC =5V timing diagram (12) VCC = 5V tsu(D–C) TAiIN input TAiOUT input During event counter mode TBiIN input CLKi TxDi RxDi tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C–Q) th(C–D) th(C–Q) th(TIN–UP) tsu(UP–TIN) TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) TAiOUT input (Up/down input) INTi input AD TRG input

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 249 28. Electrical characteristicspuorG08/C61M VCC = 5V Figure 28.14 VCC =5V timing diagram (13) th(BCLK –HOLD)tsu(HOLD –BCLK) td(BCLK –HLDA)td(BCLK –HLDA) Hi–Z Measuring conditions :

VCC =5V±10%
Input timing voltage : Determined with VIL=1.0V, VIH=4.0V
Output timing voltage : Determined with VOL =2.5V, VOH =2.5V Memory Expansion Mode and Microprocessor Mode BCLK HOLD input HLDA output P0, P1, P2, P3, P4, 0 to P52 (Valid with or without wait) (Valid only with wait) RDY input tsu(RDY –BCLK) th(BCLK –RDY) BCLK RD (Multiplexed bus) (Multiplexed bus) WR, WRL, WRH WR, WRL, WRH (Separate bus) RD (Separate bus)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 250 28. Electrical characteristicspuorG08/C61M VCC = 3V Table 28.23 Electrical characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25oC, f(XIN) = 10MH Z unless otherwise specified) Electrical characteristics (Vcc = 3V) Note 1: Ports P11 to P15 exist in 144-pin version. Note 2: ROMless version exists in 144-pin version. V2.5IOH = - 1mA , VCC = 3.0V P00-P07,P10-P17,P20-P27, P30-P37,P40-P47,P50-P57, P60-P67,P72-P77,P80-P84, P86,P87,P90-P97,P100-P107, VOH Symbol HIGH output voltage Parameter UnitStandard Min Typ. Max.Measuring condition VXOUT 2.5 2.5 V0.5 IOH = - 0.1 mA , VCC = 3.0V IOH = - 50 µA , VCC = 3.0V IOL =1mA , VCC = 3.0V P00-P07,P10-P17,P20-P27, P30-P37,P40-P47,P50-P57, HIGHPOWER LOWPOWER P60-P67,P70-P77,P80-P84, P86,P87,P90-P97,P100-P107 HIGHPOWER LOWPOWER XCOUT 3.0 1.6 V VOH VOL HIGH output voltage HIGH output voltage LOW output voltage With no load applied , VCC = 3.0V With no load applied , VCC = 3.0V VXOUT 0.5 0.5 IOL =0.1mA , VCC = 3.0V IOL =50µA , VCC = 3.0V HIGHPOWER LOWPOWER NMI, KI0-KI3, RxD0-RxD4, 0.2 1.0 V 0.2 1.8 V 4.0 2.0 V µA mA RESET 20.0 TB0 IN-TB2IN, INT0-INT5, ADTRG , CTS 0-CTS4,CLK0-CLK4,TA2OUT -TA4OUT , HOLD, RDY, TA0IN-TA4IN, VI=3V , VCC = 3.0V VI=0V , VCC = 3.0V - 4.0 12.0 20.0 P00-P07,P10-P17,P20-P27, P30-P37,P40-P47,P50-P57, P60-P67,P70-P77,P80-P87, P90-P97,P100-P107, P110-P114, P120-P127,P130-P137, P140-P146, P150-P157 (Note 1) XIN, RESET, CNVss, BYTE 1.5 10.0

3.0 M Ω

M Ω 120.0 kΩ P00-P07,P10-P17,P20-P27, P30-P37,P40-P47,P50-P57, P60-P67,P72-P77,P80-P84, P86,P87,P90-P97,P100-P107 VXCOUT HIGHPOWER LOWPOWER VI=0V , VCC = 3.0V 66.0 500.0 VOL VT+-VT- LOW output voltage LOW output voltage Hysteresis IIH IIL V RAM Icc VT+-VT- R fXIN R fXCIN R PULLUP Hysteresis HIGH input current LOW input current Pull-up resistance XIN XCIN Feedback resistance Feedback resistance RAM retention voltage f(XIN)=10MHz f(XCIN)=32kHzPower supply current When clock is stopped In single-chip mode, the output pins are open and other pins are V SS Square wave, no division Square wave f(XCIN)=32kHz Topr=85°C, when clock is stopped Topr=25°C, when clock is stopped When a WAIT instruction is executed. Oscillation drive capacity is Low. µA µA µA µA With no load applied , VCC = 3.0V With no load applied , VCC = 3.0V 3.0f(XCIN)=32kHz When a WAIT instruction is executed. Oscillation drive capacity is High. µA SCL2-SCL4, SDA 2-SDA 4 Mask ROM 128 KB version ROMless RAM 10 KB version (Note 2) Mask ROM 256 KB version ROMless RAM 24 KB version (Note 2) Flash memory version 14.0 23.0 14.0 23.0 45.0Mask ROM 128 KB version ROMless RAM 10 KB version (Note 2) Mask ROM 256 KB version ROMless RAM 24 KB version (Note 2) Flash memory version 60.0 mA3.5 1.0 Mask ROM 128 KB version ROMless RAM 10 KB version (Note 2) Mask ROM 256 KB version ROMless RAM 24 KB version (Note 2) Flash memory version 1.0 1.0 P110-P114, P120-P127,P130-P137, P140-P146, P150-P157 (Note 1) P110-P114, P120-P127,P130-P137, P140-P146, P150-P157 (Note 1) P00-P07,P10-P17,P20-P27, P30-P37,P40-P47,P50-P57, P60-P67,P70-P77,P80-P87, P90-P97,P100-P107, P110-P114, P120-P127,P130-P137, P140-P146, P150-P157 (Note 1) XIN, RESET, CNVss, BYTE P110-P114, P120-P127,P130-P137, P140-P146, P150-P157 (Note 1) VCC = 3.0V VCC = 3.0V

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 251 28. Electrical characteristicspuorG08/C61M Timing requirements (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise specified) Table 28.24 External clock input (Note) (Note) (Note) 100 Max. External clock rise time nstr Min. External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock fall time ns ns ns ns tc tw(H) tw(L) tf ParameterSymbol UnitStandard 100 Min. Data input setup time nstsu(DB-BCLK) tsu(RDY-BCLK ) ParameterSymbol UnitMax. Standard nsRDY input setup time Data input hold time nsth(RD-DB) th(BCLK -RDY) nsRDY input hold time nsHOLD input setup timetsu(HOLD-BCLK ) nsHOLD input hold timeth(BCLK-HOLD ) Data input access time (RD standard, no wait) nstac1(RD-DB) ns ns tac2(RD-DB) tac3(RD-DB) Data input access time (RD standard, with wait) Data input access time (RD standard, when accessing multiplex bus area) nstd(BCLK-HLDA ) HLDA output delay time tac1(RD – DB) = f(BCLK) X 2 – 42109 [ns] tac2(RD – DB) = f(BCLK) X 2 – 4210 X m9 [ns] (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively) (Note)Data input access time (AD standard, CS standard, no wait) nstac1(AD-DB) (Note) nstac2(AD-DB) Data input access time (AD standard, CS standard, with wait) (Note) nstac3(AD-DB) Data input access time (AD standard, CS standard, when accessing multiplex bus area) tac1(AD – DB) = f(BCLK) – 55109 [ns] tac2(AD – DB) = – 5510 X n9 [ns] (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively) tac3(RD – DB) = f(BCLK) X 2 – 5510 X m9 [ns] (m=3 and 5 when 2 wait and 3 wait, respectively) tac3(AD – DB) = f(BCLK) X 2 – 5510 X n [ns] (n=5 and 7 when 2 wait and 3 wait, respectively) Note: Calculated according to the BCLK frequency as follows: Note that inserting wait or using lower operation frequency f(BCLK) is needed when calculated value is negative. (Note) nstac4(CAS-DB) Data input access time (CAS standard, DRAM access) (Note) nstac4(RAS-DB) Data input access time (RAS standard, DRAM access) (Note) nstac4(CAD-DB) Data input access time (CAD standard, DRAM access) tac4(RAS – DB) = f(BCLK) X 2 – 5510 X m [ns] (m=3 and 5 when 1 wait and 2 wait, respectively) tac4(CAS – DB) = – 5510 X n [ns] (n=1 and 3 when 1 wait and 2 wait, respectively) tac4(CAD – DB) = f(BCLK) – 5510 X l [ns] (l=1 and 2 when 1 wait and 2 wait, respectively) f(BCLK) f(BCLK) X 2 0Data input hold time nsth(CAS-DB) VCC = 3V Table 28.25 Memory expansion and microprocessor modes

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 252 28. Electrical characteristicspuorG08/C61M VCC = 3V Timing requirements (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise specified) Table 28.26 Timer A input (counter input in event counter mode) Standard Max.Min. UnitParameterSymbol nstw(TAL) TAiIN input LOW pulse width 60 nstc(TA) TAiIN input cycle time 150 nstw(TAH) TAiIN input HIGH pulse width 60 Standard Max.Min. UnitParameterSymbol nstc(TA) TAiIN input cycle time 600 nstw(TAH) TAiIN input HIGH pulse width 300 nstw(TAL) TAiIN input LOW pulse width 300 Standard Max.Min. UnitParameterSymbol nstc(TA) TAiIN input cycle time 300 nstw(TAH) TAiIN input HIGH pulse width 150 nstw(TAL) TAiIN input LOW pulse width 150 Standard Max.Min. UnitParameterSymbol nstw(TAH) TAiIN input HIGH pulse width 150 nstw(TAL) TAiIN input LOW pulse width 150 Standard Max.Min. UnitParameterSymbol nstc(UP) TAiOUT input cycle time 3000 nstw(UPH) TAiOUT input HIGH pulse width 1500 nstw(UPL) TAiOUT input LOW pulse width 1500 nstsu(UP-TIN) TAiOUT input setup time 600 nsth(TIN-UP) TAiOUT input hold time 600 Table 28.27 Timer A input (gating input in timer mode) Table 28.28 Timer A input (external trigger input in one-shot timer mode) Table 28.29 Timer A input (external trigger input in pulse width modulation mode) Table 28.30 Timer A input (up/down input in event counter mode)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 253 28. Electrical characteristicspuorG08/C61M Timing requirements (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise specified) Table 28.31 Timer B input (counter input in event counter mode) VCC = 3V Standard Max.Min.ParameterSymbol Unit nstc(TB) TBiIN input cycle time (counted on one edge) 150 nstw(TBH) TBiIN input HIGH pulse width (counted on one edge) 60 nstw(TBL) TBiIN input LOW pulse width (counted on one edge) 60 tw(TBH) nsTBiIN input HIGH pulse width (counted on both edges) 160 tw(TBL) nsTBiIN input LOW pulse width (counted on both edges) 160 tc(TB) nsTBiIN input cycle time (counted on both edges) 300 Standard Max.Min. ParameterSymbol Unit nstc(TB) TBiIN input cycle time 600 nstw(TBH) TBiIN input HIGH pulse width 300 tw(TBL) nsTBiIN input LOW pulse width 300 Standard Max.Min.ParameterSymbol Unit nstc(TB) TBiIN input cycle time 600 nstw(TBH) TBiIN input HIGH pulse width 300 tw(TBL) nsTBiIN input LOW pulse width 300 Standard Max.Min. ParameterSymbol Unit nstc(AD) AD TRG input cycle time (trigger able minimum) 1500 nstw(ADL) AD TRG input LOW pulse width 200 Standard Max.Min. ParameterSymbol Unit nstw(INH) INTi input HIGH pulse width 380 nstw(INL) INTi input LOW pulse width 380 Standard Max.Min. ParameterSymbol Unit nstc(CK) CLKi input cycle time 300 nstw(CKH) CLKi input HIGH pulse width 150 nstw(CKL) CLKi input LOW pulse width 150 th(C-Q) nsTxDi hold time 0 tsu(D-C) nsRxDi input setup time 50 th(C-D) nsRxDi input hold time 90 td(C-Q) nsTxDi output delay time 160 Table 28.32 Timer B input (pulse period measurement mode) Table 28.33 Timer B input (pulse width measurement mode) Table 28.34 A/D trigger input Table 28.35 Serial I/O Table 28.36 External interrupt INTi inputs

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 254 28. Electrical characteristicspuorG08/C61M Symbol StandardMeasuring condition Max.Min.Parameter Unit td(BCLK-AD) Address output delay time 25 ns th(BCLK-AD) Address output hold time (BCLK standard) 0 ns th(BCLK-CS) Chip select output hold time (BCLK standard) 0 ns td(BCLK-ALE) ALE signal output delay time 25 ns th(BCLK-ALE) ALE signal output hold time – 2 ns td(BCLK-RD) RD signal output delay time 10 ns th(BCLK-RD) RD signal output hold time – 3 ns td(BCLK-WR) WR signal output delay time 25 ns th(BCLK-WR) WR signal output hold time 0 ns (Note 1) ns td(DB-WR) Data output delay time (WR standard) ns(Note 1) Note 1: Calculated according to the BCLK frequency as follows: td(DB – WR) = f(BCLK) 10 9 – 40 [ns] td(BCLK-CS) Chip select output delay time 25 ns th(RD-AD) Address output hold time (RD standard) 0 ns th(WR-AD) Address output hold time (WR standard) (Note 1) ns th(RD-CS) Chip select output hold time (RD standard) 0 ns th(WR-CS) Chip select output hold time (WR standard) (Note 1) ns th(WR – DB) = f(BCLK) X 2 10 9 – 20 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 20 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 20 [ns] tw(WR) WR signal width tw(WR) = f(BCLK) X2 10 9 – 20 [ns] th(WR-DB) Data output hold time (WR standard) ns (Note 1) Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise specified) VCC = 3V Figure 28.1 Table 28.37 Memory expansion and microprocessor modes (with no wait)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 255 28. Electrical characteristicspuorG08/C61M Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise specified) VCC = 3V Figure 28.1 Table 28.38 Memory expansion and microprocessor modes (with wait, accessing external memory) Symbol StandardMeasuring condition Max.Min.Parameter Unit td(BCLK-AD) Address output delay time 25 ns th(BCLK-AD) Address output hold time (BCLK standard) 0 ns th(BCLK-CS) Chip select output hold time (BCLK standard) 0 ns td(BCLK-ALE) ALE signal output delay time 25 ns th(BCLK-ALE) ALE signal output hold time – 2 ns td(BCLK-RD) RD signal output delay time 10 ns th(BCLK-RD) RD signal output hold time – 3 ns td(BCLK-WR) WR signal output delay time 25 ns th(BCLK-WR) WR signal output hold time 0 ns th(WR-DB) Data output hold time (WR standard) (Note 1) ns td(DB-WR) Data output delay time (WR standard) ns(Note 1) Note 1: Calculated according to the BCLK frequency as follows: [ns] (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively) td(BCLK-CS) Chip select output delay time 25 ns th(RD-AD) Address output hold time (RD standard) 0 ns th(WR-AD) Address output hold time (WR standard) (Note 1) ns th(RD-CS) Chip select output hold time (RD standard) 0 ns th(WR-CS) Chip select output hold time (WR standard) (Note 1) ns td(DB – WR) = f(BCLK) – 40 th(WR – DB) = f(BCLK) X 2 10 9 – 20 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 20 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 20 [ns] tw(WR) WR signal width [ns] (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively)tw( WR) = 10 X n9 – 20 (Note 1) ns f(BCLK ) X 2

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 256 28. Electrical characteristicspuorG08/C61M VCC = 3V Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise specified) Table 28.39 Memory expansion and microprocessor modes (with wait, accessing external memory, multiplex bus area selected) Symbol Standard Measuring condition Max.Min.Parameter Unit td(BCLK-AD) Address output delay time 25 ns th(BCLK-AD) Address output hold time (BCLK standard) 0 ns th(BCLK-CS) Chip select output hold time (BCLK standard) 0 ns td(BCLK-ALE) ALE signal output delay time (BCLK standard) 25 ns th(BCLK-ALE) ALE signal output hold time (BCLK standard) – 2n s td(BCLK-RD) RD signal output delay time 25 ns th(BCLK-RD) RD signal output hold time ns td(BCLK-WR) WR signal output delay time 25 ns th(BCLK-WR) WR signal output hold time 0 ns th(WR-DB) Data output hold time (WR standard) (Note 1) ns td(DB-WR) Data output delay time (WR standard) ns (Note 1) Note 1: Calculated according to the BCLK frequency as follows: td(DB – WR) = 10 X m9 – 40 [ns] (m=3 and 5 when 2 wait and 3 wait, respectively) td(BCLK-CS) Chip select output delay time 25 ns th(RD-AD) Address output hold time (RD standard) (Note 1) ns th(WR-AD) Address output hold time (WR standard) (Note 1) ns th(RD-CS) Chip select output hold time (RD standard) ns th(WR-CS) Chip select output hold time (WR standard) (Note 1) ns th(RD – AD) = f(BCLK) X 2 10 9 – 20 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 20 [ns] th(RD – CS) = f(BCLK) X 2 10 9 – 20 [ns] td(AD-ALE) ALE signal output delay time (address standard) ns th(ALE-AD) ALE signal output hold time (address standard) ns tdz(RD-AD) Address output flowting start time ns (Note 1) (Note 1) th(WR – CS) = f(BCLK) X 2 10 9 – 20 [ns] th(WR – DB) = f(BCLK) X 2 10 9 – 20 [ns] td(AD – ALE) = f(BCLK) X 2 10 9 – 27 [ns] th(ALE – AD) = f(BCLK) X 2 10 9 – 20 [ns] f(BCLK) X 2 (Note 1) th(BCLK-DB) DB signal output hold time (BCLK standard) ns 0 – 3 Figure 28.1

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 257 28. Electrical characteristicspuorG08/C61M VCC = 3V Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25oC unless otherwise specified) Table 28.40 Memory expansion and microprocessor modes (with wait, accessing external memory, DRAM area selected) Symbol StandardMeasuring condition Max.Min.Parameter Unit td(BCLK-RAD) Row address output delay time 25 ns th(BCLK-RAD) Row address output hold time (BCLK standard) 0 ns td(BCLK-RAS) RAS output delay time (BCLK standard) ns tsu(DB-CAS) CAS after DB output setup time ns th(BCLK-DB) DB signal output hold time (BCLK standard) (Note 1) ns td(BCLK-CAS) CAS output delay time (BCLK standard) – 3 ns th(BCLK-CAS) CAS output hold time (BCLK standard) (Note 1) ns td(BCLK-DW) Data output delay time (BCLK standard) ns – 7 Note 1: Calculated according to the BCLK frequency as follows: tsu(CAS – RAS) = f(BCLK ) X 2 – 25 [ns] th(RAS-RAD) Row address output hold time after RAS output ns td(BCLK-CAD) String address output delay time ns th(BCLK-CAD) String address output hold time (BCLK standard) (Note 1) ns th(BCLK-RAS) RAS output hold time (BCLK standard) ns tRP RAS "H" hold time ns th(RAS – RAD) = f(BCLK) X 2 10 9 – 25 [ns] tRP = f(BCLK) X 2 – 40 [ns] tsu(CAS-RAS) CAS before RAS setup time (refresh) ns (Note 1) tsu(DB – CAS) = f(BCLK) 10 9 – 40 [ns] th(BCLK-DW) Data output hold time (BCLK standard) ns Figure 28.1

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 258 28. Electrical characteristicspuorG08/C61M Figure 28.15 VCC =3V timing diagram (1) BCLK ALE -2ns.min RD 10ns.max -3ns.min Hi-ZDB 0ns.min 0ns.min td(BCLK-ALE) th(BCLK-ALE) tsu(DB-BCLK) td(BCLK-RD) 40ns.min*1 CSi td(BCLK-CS) 25ns.max*1 ADi th(BCLK-AD) 0ns.min th(BCLK-CS) 0ns.min BHE tcyc td(BCLK-AD) 0ns.min tac1(AD-DB)*2 tac1(RD-DB)=(tcyc/2-42)ns.max tac1(AD-DB)=(tcyc-55)ns.max WR,WRL, WRH 25ns.max 0ns.min BCLK CSi td(BCLK-CS) 25ns.max ADi td(BCLK-AD) 25ns.max td(BCLK-ALE) 0ns.min 0ns.min tcyc BHE td(DB-WR) *3 DBi td(BCLK-WR) ALE -2ns.min th(WR-DB) *3 td(DB-WR) =(tcyc-40)ns.min th(WR-DB) =(tcyc/2-20)ns.min th(WR-AD) =(tcyc/2-20)ns.min th(WR-CS) =(tcyc/2-20)ns.min tw(WR) =(tcyc/2-20)ns.min Vcc=3V th(BCLK-RD) th(RD-DB) th(RD-AD) th(RD-CS) th(BCLK-WR) th(BCLK-ALE) th(BCLK-AD) th(BCLK-CS) th(WR-CS) *3 th(WR-AD) *3 tac1(RD-DB)*2 25ns.max*1 Read Timing Write Timing ( Written by 2 cycles in selecting no wait) *3:It depends on operation frequency. Measuring conditions

VCC =3V±10%
Input timing voltage :Determined with VIH=1.5V, VIL=0.5V
Output timing voltage :Determined with VOH =1.5V, VOL =1.5V Memory expansion Mode and Microprocessor Mode (without wait) *1:It is a guarantee value with being alone. 55ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK). *2:It depends on operation frequency. 25ns.max tw(WR)*3 25ns.max

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 259 28. Electrical characteristicspuorG08/C61M Figure 28.16 VCC =3V timing diagram (2) BCLK ALE 25ns.max -2ns.min RD 10ns.max -3ns.min Hi-ZDB 0ns.min 0ns.min td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) 40ns.min*1 tac2(RD-DB)*2 CSi td(BCLK-CS) 25ns.max*1 ADi 25ns.max*1 th(BCLK-AD) 0ns.min th(BCLK-CS) 0ns.min BHE tcyc td(BCLK-AD) tac2(AD-DB)*2 tac2(RD-DB)=(tcyc/2 x m-42)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.) tac2(AD-DB)=(tcyc x n-55)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.) WR,WRL, WRH 25ns.max 0ns.min BCLK CSi 25ns.max ADi 25ns.max 0ns.min 0ns.min tcyc BHE DBi td(BCLK-WR) ALE 25ns.max -2ns.min Vcc=3V th(BCLK-RD) th(RD-DB) th(RD-AD) tsu(DB-BCLK) th(RD-CS) 0ns.min th(BCLK-WR) td(BCLK-CS) td(BCLK-AD) td(BCLK-ALE) th(BCLK-AD) th(BCLK-CS) th(WR-CS) *3 td(DB-WR) *3 th(WR-DB) *3 th(WR-AD) *3 td(DB-WR) =(tcyc x n-40)ns.min (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.) t h(WR-DB) =(tcyc/2-20)ns.min th(WR-AD) =(tcyc/2-20)ns.min th(WR-CS) =(tcyc/2-20)ns.min tw(WR) =(tcyc/2 x n-20)ns.min (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.) *3:It depends on operation frequency. Measuring conditions

VCC =3V±10%
Input timing voltage :Determined with VIH=1.5V, VIL=0.5V
Output timing voltage :Determined with VOH =1.5V, VOL =1.5V *1:It is a guarantee value with being alone. 55ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK). *2:It depends on operation frequency. th(BCLK-ALE) Read Timing Write Timing Memory expansion Mode and Microprocessor Mode (with 1 wait) tw(WR) *3

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 260 28. Electrical characteristicspuorG08/C61M Figure 28.17 VCC =3V timing diagram (3) BCLK ALE 25ns.max -2ns.min RD 10ns.max -3ns.min Hi-ZDB 0ns.min 0ns.min td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) 40ns.min*1 tac2(RD-DB)*2 CSi td(BCLK-CS) 25ns.max*1 ADi 25ns.max*1 th(BCLK-AD) 0ns.min th(BCLK-CS) 0ns.min BHE tcyc td(BCLK-AD) tac2(AD-DB)*2 tac2(RD-DB)=(tcyc/2 x m-42)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.) tac2(AD-DB)=(tcyc x n-55)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.) WR,WRL, WRH 25ns.max 0ns.min BCLK CSi 25ns.max ADi 25ns.max 0ns.min 0ns.min tcyc BHE DBi td(BCLK-WR) ALE 25ns.max -2ns.min Vcc=3V th(BCLK-RD) th(RD-DB) th(RD-AD) tsu(DB-BCLK) th(RD-CS) 0ns.min th(BCLK-WR) td(BCLK-CS) td(BCLK-AD) td(BCLK-ALE) th(BCLK-AD) th(BCLK-CS) th(WR-CS) *3 td(DB-WR) *3 th(WR-DB) *3 th(WR-AD) *3 td(DB-WR) =(tcyc x n-40)ns.min (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.) t h(WR-DB) =(tcyc/2-20)ns.min th(WR-AD) =(tcyc/2-20)ns.min th(WR-CS) =(tcyc/2-20)ns.min tw(WR) =(tcyc/2 x n-20)ns.min (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.) *3:It depends on operation frequency. Measuring conditions

VCC =3V±10%
Input timing voltage :Determined with VIH=1.5V, VIL=0.5V
Output timing voltage :Determined with VOH =1.5V, VOL =1.5V *1:It is a guarantee value with being alone. 55ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK). *2:It depends on operation frequency. th(BCLK-ALE) Read Timing Write Timing Memory expansion Mode and Microprocessor Mode (with 2 wait) tw(WR) *3

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 261 28. Electrical characteristicspuorG08/C61M Figure 28.18 VCC =3V timing diagram (4) BCLK ALE 25ns.max -2ns.min RD 10ns.max -3ns.min Hi-ZDB 0ns.min 0ns.min td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) 40ns.min*1 tac2(RD-DB)*2 CSi td(BCLK-CS) 25ns.max*1 ADi 25ns.max*1 th(BCLK-AD) 0ns.min th(BCLK-CS) 0ns.min BHE tcyc td(BCLK-AD) tac2(AD-DB)*2 WR,WRL, WRH 25ns.max 0ns.min BCLK CSi 25ns.max ADi 25ns.max 0ns.min 0ns.min tcyc BHE DBi td(BCLK-WR) ALE 25ns.max -2ns.min Vcc=3V th(BCLK-RD) th(RD-DB) th(RD-AD) tsu(DB-BCLK) th(RD-CS) 0ns.min th(BCLK-WR) td(BCLK-CS) td(BCLK-AD) td(BCLK-ALE) th(BCLK-AD) th(BCLK-CS) th(WR-CS) *3 td(DB-WR) *3 th(WR-DB) *3 th(WR-AD) *3 th(BCLK-ALE) Read Timing Write Timing Memory expansion Mode and Microprocessor Mode (with 3 wait) tw(WR) *3 *1:It is a guarantee value with being alone. 55ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK). *2:It depends on operation frequency. tac2(RD-DB)=(tcyc/2 x m-42)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.) tac2(AD-DB)=(tcyc x n-55)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.) *3:It depends on operation frequency. td(DB-WR) =(tcyc x n-40)ns.min (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.) t h(WR-DB) =(tcyc/2-20)ns.min th(WR-AD) =(tcyc/2-20)ns.min th(WR-CS) =(tcyc/2-20)ns.min tw(WR) =(tcyc/2 x n-20)ns.min (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.) Measuring conditions

VCC =3V ±10%
Input timing voltage :Determined with VIH=1.5V, VIL=0.5V
Output timing voltage :Determined with VOH =1.5V, VOL =1.5V

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 262 28. Electrical characteristicspuorG08/C61M Figure 28.19 VCC =3V timing diagram (5) BCLK CSi 25ns.max ADi 25ns.max RD 25ns.max -3ns.min th(BCLK-AD) 0ns.min 0ns.min BHE ADi /DBi 0ns.min 25ns.max 0ns.min BCLK CSi 25ns.max ADi 25ns.max 0ns.min 0ns.mintcyc BHE 0ns.min ADi /DBi Data output WR,WRL, WRH Address AddressData input 40ns.min td(BCLK-RD) th(WR-CS) *2 Address td(AD-ALE)*2 Address tsu(DB-BCLK) tac3(RD-DB)*1 tdz(RD-AD) 8ns.max ALE -2ns.min td(BCLK-ALE) 25ns.max td(AD-ALE)=(tcyc/2-27)ns.min th(ALE-AD)=(tcyc/2-20)ns.min, th(RD-AD)=(tcyc/2-20)ns.min, th(RD-CS)=(tcyc/2-20)ns.min tac3(RD-DB)=(tcyc/2 x m-55)ns.max (m=3 and 5 when 2 wait and 3 wait, respectively.) tac3(AD-DB)=(tcyc/2 x n-55)ns.max (n=5 and 7 when 2 wait and 3 wait, respectively.) ALE -2ns.min td(BCLK-ALE) th(ALE-AD)*2 td(AD-ALE)=(tcyc/2-27)ns.min th(ALE-AD)=(tcyc/2-20)ns.min, th(WR-AD) =(tcyc/2-20)ns.min th(WR-CS) =(tcyc/2-20)ns.min, th(WR-DB) =(tcyc/2-20)ns.min td(DB-WR) =(tcyc/2 x m-40)ns.min (m=3 and 5 when 2 wait and 3 wait, respectively.) Vcc=3V td(BCLK-CS) td(AD-ALE)*1 th(ALE-AD)*1 th(BCLK-RD) th(RD-AD)*1 th(RD-DB) td(BCLK-AD) th(BCLK-CS) th(RD-CS)*1 td(BCLK-WR) th(BCLK-WR) td(BCLK-CS) td(BCLK-AD) th(BCLK-AD) th(BCLK-CS) th(WR-AD) *2 th(BCLK-DB) td(DB-WR) *2 th(WR-DB) *2 th(BCLK-ALE) th(BCLK-ALE) tcyc *2:It depends on operation frequency. Measuring conditions

VCC =3V±10%
Input timing voltage :Determined with VIH=1.5V, VIL=0.5V
Output timing voltage :Determined with VOH =1.5V, VOL =1.5V *1:It depends on operation frequency. Read Timing Write Timing Memory expansion Mode and Microprocessor Mode (When accessing external memory area with 2 wait, and select multiplexed bus) 25ns.max tac3(AD-DB)*1

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 263 28. Electrical characteristicspuorG08/C61M Figure 28.20 VCC =3V timing diagram (6) BCLK CSi 25ns.max ADi 25ns.max RD 25ns.max -3ns.min th(BCLK-AD) 0ns.min 0ns.min BHE ADi /DBi 0ns.min 25ns.max 0ns.min BCLK CSi 25ns.max ADi 25ns.max 0ns.min 0ns.mintcyc BHE 0ns.min ADi /DBi Data output WR,WRL, WRH Address AddressData input 40ns.min td(BCLK-RD) th(WR-CS) *2 Address td(AD-ALE)*2 Address tsu(DB-BCLK) tac3(RD-DB)*1 tdz(RD-AD) 8ns.max ALE -2ns.min td(BCLK-ALE) 25ns.max td(AD-ALE)=(tcyc/2-27)ns.min th(ALE-AD)=(tcyc/2-20)ns.min, th(RD-AD)=(tcyc/2-20)ns.min, th(RD-CS)=(tcyc/2-20)ns.min tac3(RD-DB)=(tcyc/2 x m-55)ns.max (m=3 and 5 when 2 wait and 3 wait, respectively.) tac3(AD-DB)=(tcyc/2 x n-55)ns.max (n=5 and 7 when 2 wait and 3 wait, respectively.) ALE -2ns.min td(BCLK-ALE) th(ALE-AD)*2 td(AD-ALE)=(tcyc/2-27)ns.min th(ALE-AD)=(tcyc/2-20)ns.min, th(WR-AD) =(tcyc/2-20)ns.min th(WR-CS) =(tcyc/2-20)ns.min, th(WR-DB) =(tcyc/2-20)ns.min td(DB-WR) =(tcyc/2 x m-40)ns.min (m=3 and 5 when 2 wait and 3 wait, respectively.) Vcc=3V td(BCLK-CS) td(AD-ALE)*1 th(ALE-AD)*1 th(BCLK-RD) th(RD-AD)*1 th(RD-DB) td(BCLK-AD) th(BCLK-CS) th(RD-CS)*1 td(BCLK-WR) th(BCLK-WR) td(BCLK-CS) td(BCLK-AD) th(BCLK-AD) th(BCLK-CS) th(WR-AD) *2 th(BCLK-DB) td(DB-WR) *2 th(WR-DB) *2 th(BCLK-ALE) th(BCLK-ALE) tcyc *2:It depends on operation frequency. Measuring conditions

VCC =3V±10%
Input timing voltage :Determined with VIH=1.5V, VIL=0.5V
Output timing voltage :Determined with VOH =1.5V, VOL =1.5V *1:It depends on operation frequency. Read Timing Write Timing Memory expansion Mode and Microprocessor Mode (When accessing external memory area with 3 wait, and select multiplexed bus) 25ns.max tac3(AD-DB)*1

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 264 28. Electrical characteristicspuorG08/C61M Figure 28.21 VCC =3V timing diagram (7) BCLK DW DB MAi td(BCLK-RAS) + tsu(DB-BCLK) td(BCLK-CAS) + tsu(DB-BCLK) td(BCLK-CAD) + tsu(DB-BCLK) tac4(RAS-DB)=(tcyc/2 x m-55)ns.max (m=3 and 5 when 1 wait and 2 wait, respectively.) tac4(CAS-DB)=(tcyc/2 x n-55)ns.max (n=1 and 3 when 1 wait and 2 wait, respectively.) tac4(CAD-DB)=(tcyc x l-55)ns.max (l=1 and 2 when 1 wait and 2 wait, respectively.) th(RAS-RAD) =(tcyc/2-25)ns.min tRP =(tcyc/2 x 3-40)ns.min Vcc=3V RAS CASL CASH Hi-Z tac4(CAS-DB)*2 25ns.max*1 th(BCLK-CAD) 0ns.min tcyc td(BCLK-RAD) tac4(RAS-DB)*2 Row address String address th(BCLK-RAD) 0ns.min 25ns.max*1 td(BCLK-CAD) 25ns.max*1 td(BCLK-RAS) 25ns.max*1 td(BCLK-CAS) th(RAS-RAD)*2 tRP*2 tac4(CAD-DB)*2 th(BCLK-RAS) 0ns.min th(BCLK-CAS) 0ns.min 0ns.min tsu(DB-BCLK) 40ns.min*1 th(CAS-DB) *2:It depends on operation frequency. Measuring conditions

VCC =3V±10%
Input timing voltage :Determined with VIH=1.5V, VIL=0.5V
Output timing voltage :Determined with VOH =1.5V, VOL =1.5V Read Timing Memory expansion Mode and Microprocessor Mode (When accessing DRAM area with 1 wait) *1:It is a guarantee value with being alone. 55ns.max garantees as follows:

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 265 28. Electrical characteristicspuorG08/C61M Figure 28.22 VCC =3V timing diagram (8) BCLK DW DB MAi th(RAS-RAD) =(tcyc/2-25)ns.min tRP =(tcyc/2 x 3-40)ns.min tsu(DB-CAS)=(tcyc-40)ns.min Vcc=3V RAS CASL CASH Hi-Z th(BCLK-DB) -7ns.min 25ns.max th(BCLK-CAD) 0ns.min tcyc td(BCLK-RAD) th(BCLK-RAD) 0ns.min 25ns.max td(BCLK-CAD) 25ns.max td(BCLK-RAS) 25ns.max td(BCLK-CAS) tRP*1 25ns.max td(BCLK-DW) tsu(DB-CAS)*1 th(BCLK-RAS) 0ns.min th(BCLK-CAS) -3ns.min th(BCLK-DW) 0ns.min Row address String address *1:It depends on operation frequency. Measuring conditions

VCC =3V±10%
Input timing voltage :Determined with VIH=1.5V, VIL=0.5V
Output timing voltage :Determined with VOH =1.5V, VOL =1.5V Write Timing Memory expansion Mode and Microprocessor Mode (When accessing DRAM area with 1 wait) th(RAS-RAD)*1

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 266 28. Electrical characteristicspuorG08/C61M Figure 28.23 VCC =3V timing diagram (9) BCLK DW DB MAi td(BCLK-RAS) + tsu(DB-BCLK) td(BCLK-CAS) + tsu(DB-BCLK) td(BCLK-CAD) + tsu(DB-BCLK) tac4(RAS-DB)=(tcyc/2 x m-55)ns.max (m=3 and 5 when 1 wait and 2 wait, respectively.) tac4(CAS-DB)=(tcyc/2 x n-55)ns.max (n=1 and 3 when 1 wait and 2 wait, respectively.) tac4(CAD-DB)=(tcyc x l-55)ns.max (l=1 and 2 when 1 wait and 2 wait, respectively.) th(RAS-RAD) =(tcyc/2-25)ns.min tRP =(tcyc/2 x 3-40)ns.min Vcc=3V RAS CASL CASH Hi-Z tac4(CAS-DB)*2 25ns.max*1 th(BCLK-CAD) 0ns.min tcyc td(BCLK-RAD) tac4(RAS-DB)*2 Row address String address th(BCLK-RAD) 0ns.min 25ns.max*1 td(BCLK-CAD) 25ns.max*1 td(BCLK-RAS) 25ns.max*1 td(BCLK-CAS) th(RAS-RAD)*2 tRP*2 tac4(CAD-DB)*2 th(BCLK-RAS) 0ns.min th(BCLK-CAS) 0ns.min 0ns.min tsu(DB-BCLK) 40ns.min*1 th(CAS-DB) *2:It depends on operation frequency. Measuring conditions

VCC =3V±10%
Input timing voltage :Determined with VIH=1.5V, VIL=0.5V
Output timing voltage :Determined with VOH =1.5V, VOL =1.5V Read Timing Memory expansion Mode and Microprocessor Mode (When accessing DRAM area with 2 wait) *1:It is a guarantee value with being alone. 55ns.max garantees as follows:

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 267 28. Electrical characteristicspuorG08/C61M Figure 28.24 VCC =3V timing diagram (10) BCLK DW DB MAi th(RAS-RAD) =(tcyc/2-25)ns.min tRP =(tcyc/2 x 3-40)ns.min tsu(DB-CAS)=(tcyc-40)ns.min Vcc=3V RAS CASL CASH Hi-Z th(BCLK-DB) -7ns.min 25ns.max th(BCLK-CAD) 0ns.min tcyc td(BCLK-RAD) th(BCLK-RAD) 0ns.min 25ns.max td(BCLK-CAD) 25ns.max td(BCLK-RAS) 25ns.max td(BCLK-CAS) tRP*1 25ns.max td(BCLK-DW) tsu(DB-CAS)*1 th(BCLK-RAS) 0ns.min th(BCLK-CAS) -3ns.min th(BCLK-DW) 0ns.min Row address String address *1:It depends on operation frequency. Measuring conditions

VCC =3V±10%
Input timing voltage :Determined with VIH=1.5V, VIL=0.5V
Output timing voltage :Determined with VOH =1.5V, VOL =1.5V Write Timing Memory expansion Mode and Microprocessor Mode (When accessing DRAM area with 2 wait) th(RAS-RAD)*1

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 268 28. Electrical characteristicspuorG08/C61M Figure 28.25 VCC =3V timing diagram (11) tcyc 25ns.max td(BCLK-RAS) 25ns.max td(BCLK-CAS) th(BCLK-RAS) 0ns.min th(BCLK-CAS) 0ns.min tsu(CAS-RAS)*1 25ns.max tcyc td(BCLK-CAS) tsu(CAS-RAS)*1 th(BCLK-RAS) 0ns.min th(BCLK-CAS) 0ns.min 25ns.max td(BCLK-RAS) BCLK DW tsu(CAS-RAS)=(tcyc/2-25)ns.min Vcc=3V RAS CASL CASH BCLK DW tsu(CAS-RAS)=(tcyc/2-25)ns.min RAS CASL CASH *1:It depends on operation frequency. Measuring conditions

VCC =3V±10%
Input timing voltage :Determined with VIH=1.5V, VIL=0.5V
Output timing voltage :Determined with VOH =1.5V, VOL =1.5V Refresh Timing (CAS before RAS refresh) Memory expansion Mode and Microprocessor Mode *1:It depends on operation frequency. Refresh Timing (Self-refresh)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 269 28. Electrical characteristicspuorG08/C61M Figure 28.26 VCC =3V timing diagram (12) tsu(D–C) TAiIN input TAiOUT input During event counter mode TBiIN input CLKi TxDi RxDi tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C–Q) th(C–D) th(C–Q) th(TIN–UP) tsu(UP–TIN) TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) TAiOUT input (Up/down input) INTi input AD TRG input VCC = 3V

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 270 28. Electrical characteristicspuorG08/C61M Figure 28.27 VCC =3V timing diagram (13) VCC = 3V Measuring conditions :

VCC =3V±10%
Input timing voltage : Determined with VIH=2.4V, VIL=0.6V
Output timing voltage : Determined with VOH =1.5V, VOL =1.5V Memory Expansion Mode and Microprocessor Mode BCLK HOLD input HLDA output P0, P1, P2, P3, P4, 0 to P52 (Valid with or without wait) (Valid only with wait) RDY input tsu(RDY –BCLK) th(BCLK –RDY) BCLK RD (Multiplexed bus) (Multiplexed bus) WR, WRL, WRH WR, WRL, WRH (Separate bus) RD (Separate bus) Hi–Z th(BCLK –HOLD)tsu(HOLD –BCLK) td(BCLK –HLDA)td(BCLK –HLDA)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 271 29. Flash Memory VersionpuorG08/C61M Item Power supply voltage Program/erase voltage Flash memory operation mode Erase block division Program method Erase method Program/erase control method Protect method Number of commands Program/erase count ROM code protect Performance 5V version: f(XIN)=20MHz, without wait, 4.2V to 5.5V f(X IN)=10MHz, without wait, 2.7V to 5.5V 5V version: 4.2V to 5.5 V f(BCLK )=12.5MHz, with one wait f( BCLK )=6.25MHz, without wait Three modes (parallel I/O, standard serial I/O, CPU rewrite) See Figure 29.3 One division (8 Kbytes) (Note 1) In units of pages (in units of 256 bytes) Collective erase/block erase Program/erase control by software command Protected for each block by lock bit 8 commands 100 times Parallel I/O and standard serial modes are supported. Note: The boot ROM area contains a standard serial I/O mode control program which is stored in it when shipped from the factory. This area can be erased and programmed in only parallel I/O mode. User ROM area Boot ROM area Data holding 10 years Table 29.1 Outline Performance of the M16C/80 (flash memory version) Outline Performance Table 29.1 shows the outline performance of the M16C/80 (flash memory version). 29. Flash Memory Version

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 272 29. Flash Memory VersionpuorG08/C61M M30800FCFP M30800FCGP M30803FGFP M30803FGGP

10 Kbytes128 Kbytes 100P6S-A

20 Kbytes256 Kbytes

RAM capacityROM capacity Package type RemarksType No M30802FCGP M30805FGGP 20 Kbytes256 Kbytes 144P6Q-A10 Kbytes128 Kbytes The following shows Renesas plans to develop a line of M16C/80 products (flash memory version). (1) ROM capacity (2) Package 100P6S-A ... Plastic molded QFP 100P6Q-A ... Plastic molded QFP 144P6Q-A ... Plastic molded QFP Figure 29.1 ROM Expansion The following lists the M16C/80 products to be supported in the future. ROM size (Bytes) M30805FGGP M30803FGFP/GP Flash memory version External ROM 256K 128K 96K 64K M30802FCGP M30800FCFP/GP Table 29.2 Product List Figure 29.2 Type No., memory size, and package Package type: FP : Package 100P6S-A GP : Package 100P6Q-A, 144P6Q-A ROM No. Omitted for blank external ROM version and flash memory version ROM capacity: C : 128K bytes G : 256K bytes Memory type: M : Mask ROM version S : External ROM version F : Flash memory version Type No. M 3 0 8 0 0 M C – X X X F P M16C/80 Group M16C Family Shows RAM capacity, pin count, etc (The value itself has no specific meaning)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 273 29. Flash Memory VersionpuorG08/C61M Flash Memory The M16C/80 (flash memory version) contains the flash memory that can be rewritten with a single voltage of 5 V. For this flash memory, three flash memory modes are available in which to read, program, and erase: parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a programmer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Pro- cessing Unit (CPU). Each mode is detailed in the pages to follow. The flash memory is divided into several blocks as shown in Figure 29.3, so that memory can be erased one block at a time. Each block has a lock bit to enable or disable execution of an erase or program operation, allowing for data in each block to be protected. In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user’s application system. This boot ROM area can be rewritten in only parallel I/O mode. Figure 29.3 Block diagram of flash memory version 0FC0000 16 0FD0000 16 Block 6 : 64K byte Block 5 : 64K byte 0FE0000 16 Block 4 : 64K byte 0FF000016 Block 3 : 32K byte 0FF800016 Block 2 : 8K byte 0FFA000 16 Block 1 : 8K byte Block 0 : 16K byte0FFC000 16 User ROM area 8K byte0FFE000 16 0FFFFFF 16 0FFFFFF 16 Boot ROM area Flash memory start address 0FE0000 16 0FC0000 16 Note 1: The boot ROM area can be rewritten in only parallel input/output mode. (Access to any other areas is inhibited.) Note 2: To specify a block, use the maximum address in the block that is an even address. Flash memory size 256Kbytes 128Kbytes

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 274 30. CPU Rewrite ModepuorG08/C61M 30. CPU Rewrite Mode In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). In CPU rewrite mode, only the user ROM area shown in Figure 29.3 can be rewritten; the boot ROM area cannot be rewritten. Make sure the program and block erase commands are issued for only the user ROM area and each block area. The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to any area other than the internal flash memory before it can be executed. Microcomputer Mode and Boot Mode The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard serial I/O mode becomes unusable.) See Figure 29.3 for details about the boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNV SS pin low. In this case, the CPU starts operating using the control program in the user ROM area. When the microcomputer is reset by pulling the P5 5 pin low, the CNVSS pin high, and the P50 pin high, the CPU starts operating using the control program in the boot ROM area. This mode is called the “boot” mode. The control program in the boot ROM area can also be used to rewrite the user ROM area. Block Address Block addresses refer to the maximum even address of each block. These addresses are used in the block erase command, lock bit program command, and read lock status command.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 275 30. CPU Rewrite ModepuorG08/C61M Outline Performance (CPU Rewrite Mode) In the CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by software commands. Operations must be executed from a memory other than the internal flash memory, such as the internal RAM. When the CPU rewrite mode select bit (bit 1 at address 0377 16) is set to “1”, transition to CPU rewrite mode occurs and software commands can be accepted. In the CPU rewrite mode, write to and read from software commands and data into even-numbered ad- dress (“0” for byte address A0) in 16-bit units. Always write 8-bit software commands into even-numbered address. Commands are ignored with odd-numbered addresses. Use software commands to control program and erase operations. Whether a program or erase operation has terminated normally or in error can be verified by reading the status register. Read data from an even address in the user ROM area when reading the status register. Figure 30.1 shows the flash memory control register 0 and the flash memory control register 1. Bit 0 of the flash memory control register 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming and erase operations, it is “0”. Otherwise, it is “1”. Bit 1 of the flash memory control register 0 is the CPU rewrite mode select bit. The CPU rewrite mode is entered by setting this bit to “1”, so that software commands become acceptable. In CPU rewrite mode, the CPU becomes unable to access the internal flash memory directly. Therefore, write bit 1 in an area other than the internal flash memory. To set this bit to “1”, it is necessary to write “0” and then write “1” in succession when NMI pin is "H" level. The bit can be set to “0” by only writing a “0” . Bit 2 of the flash memory control register 0 is a lock bit disable bit. By setting this bit to “1”, it is possible to disable erase and write protect (block lock) effectuated by the lock bit data. The lock bit disable select bit only disables the lock bit function; it does not change the lock data bit value. However, if an erase operation is performed when this bit =“1”, the lock bit data that is “0” (locked) is set to “1” (unlocked) after erasure. To set this bit to “1”, it is necessary to write “0” and then write “1” in succession. This bit can be manipulated only when the CPU rewrite mode select bit = “1”. Bit 3 of the flash memory control register 0 is the flash memory reset bit used to reset the control circuit of the internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access has failed. When the CPU rewrite mode select bit is “1”, writing “1” for this bit resets the control circuit. To release the reset, it is necessary to set this bit to “0”. Bit 5 of the flash memory control register 0 is a user ROM area select bit which is effective in only boot mode. If this bit is set to “1” in boot mode, the area to be accessed is switched from the boot ROM area to the user ROM area. When the CPU rewrite mode needs to be used in boot mode, set this bit to “1”. Note that if the microcomputer is booted from the user ROM area, it is always the user ROM area that can be accessed and this bit has no effect. When in boot mode, the function of this bit is effective regardless of whether the CPU rewrite mode is on or off. Use the control program except in the internal flash memory to rewrite this bit. Bit 3 of the flash memory control register 1 turns power supply to the internal flash memory on/off. When this bit is set to “1”, power is not supplied to the internal flash memory, thus power consumption can be reduced. However, in this state, the internal flash memory cannot be accessed. To set this bit to “1”, it is necessary to write “0” and then write “1” in succession. Use this bit mainly in the low speed mode (when X CIN is the block count source of BCLK). When the CPU is shifted to the stop or wait modes, power to the internal flash memory is automatically shut off. It is reconnected automatically when CPU operation is restored. Therefore, it is not particularly neces- sary to set flash memory control register 1.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 277 30. CPU Rewrite ModepuorG08/C61M End Start Execute read array command or reset flash memory by setting flash memory reset bit (by writing “1” and then “0” in succession) (Note 3) Single-chip mode, memory expansion mode, or boot mode Set processor mode register (Note 1) Using software command execute erase, program, or other operation (Set lock bit disable bit as required) Jump to transferred control program in RAM (Subsequent operations are executed by control program in this RAM) Transfer CPU rewrite mode control program to internal RAM Note 1: During CPU rewrite mode, set the main clock frequency as shown below using the main clock division register (address 000C 16):

6.25 MHz or less when wait bit (bit 2 at address 000516) = “0” (without internal access wait state)

12.5 MHz or less when wait bit (bit 2 at address 000516) = “1” (with internal access wait state)

Note 2: For CPU rewrite mode select bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Use the program except in the internal flash memory for write to this bit. Also write to this bit when NMI pin is "H" level. Note 3: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute a read array command or reset the flash memory. Note 4: “1” can be set. However, when this bit is “1”, user ROM area is accessed. (Boot mode only) Write “0” to user ROM area select bit (Note 4) Write “0” to CPU rewrite mode select bit (Boot mode only) Set user ROM area select bit to “1” Set CPU rewrite mode select bit to “1” (by writing “0” and then “1” in succession)(Note 2) Program in ROM Program in RAM Figure 30.2 CPU rewrite mode set/reset flowchart

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 278 30. CPU Rewrite ModepuorG08/C61M Figure 30.3 Shifting to the low speed mode flowchart End Start XIN oscillating Transfer the program to be executed in the low speed mode, to the internal RAM. Switch the count source of BCLK. XIN stop. (Note 2) Jump to transferred control program in RAM (Subsequent operations are executed by control program in this RAM) Note 1: For flash memory power supply-OFF bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Note 2: Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which the count source is going to be switched must be oscillating stably. Wait time until the internal circuit stabilizes (Set NOP instruction about twice) Set flash memory power supply-OFF bit to “0” Set flash memory power supply-OFF bit to “1” (by writing “0” and then “1” in succession)(Note 1) Program in ROM Program in RAM Process of low speed mode Wait until the XIN has stabilized Switch the count source of BCLK (Note 2)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 279 30. CPU Rewrite ModepuorG08/C61M Precautions on CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During CPU rewrite mode, set the BCLK as shown below using the main clock division register (ad- dress 000C 16):

6.25 MHz or less when wait bit (bit 2 at address 000516) = 0 (without internal access wait state)

12.5 MHz or less when wait bit (bit 2 at address 000516) = 1 (with internal access wait state)

(2) Instructions inhibited against use The instructions listed below cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction (3) Interrupts inhibited against use The address match interrupt cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory. If interrupts have their vector in the variable vector table, they can be used by transferring the vector into the RAM area. The NMI and watchdog timer interrupts each can be used to change the CPU rewrite mode select bit forcibly to normal mode (FMR01="0") upon occur- rence of the interrupt. Since the rewrite operation is halted when the NMI and watchdog timer inter- rupts occur, set the CPU rewite mode select bit to "1" and the erase/program operation needs to be performed over again. (4) Reset Reset input is always accepted. (5) Access disable Write CPU rewrite mode select bit, flash memory power supply-OFF bit and user ROM area select bit in an area other than the internal flash memory. (6) How to access For CPU rewrite mode select bit, lock bit disable bit, and flash memory power supply-OFF bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Write to the CPU rewrite mode select bit when NMI pin is "H" level. (7)Writing in the user ROM area If power is lost while rewriting blocks that contain the flash rewrite program with the CPU rewrite mode, those blocks may not be correctly rewritten and it is possible that the flash memory can no longer be rewritten after that. Therefore, it is recommended to use the standard serial I/O mode or parallel I/O mode to rewrite these blocks. (8)Using the lock bit To use the CPU rewrite mode, use a boot program that can set and cancel the lock command.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 280 30. CPU Rewrite ModepuorG08/C61M Command Page program Clear status register Read array Read status register X X X X(Note 3) First bus cycle Second bus cycle Third bus cycle FF16 7016 5016 4116 Write Write Write Write XS R DRead Write Lock bit program X 7716Write BA D0 16Write Erase all unlock block X A716Write X D0 16Write WA1 WD1Write (Note 2) WA0 (Note 3)WD0 (Note 3) Block erase X 2016Write D0 16Write BA (Note 4) Read lock bit status X 7116Write BA D 6Read (Note 5) Mode Address Mode Address Mode AddressData (D0 to D7) Data (D0 to D7) Data (D0 to D7) (Note 6) Note 1: When a software command is input, the high-order byte of data (D8 to D15) is ignored. Note 2: SRD = Status Register Data Note 3: WA = Write Address, WD = Write Data WA and WD must be set sequentially from 00 16 to FE16 (byte address; however, an even address). The page size is 256 bytes. Note 4: BA = Block Address (Enter the maximum address of each block that is an even address.) Note 5: D 6 corresponds to the block lock status. Block not locked when D6 = 1, block locked when D6 = 0. Note 6: X denotes a given address in the user ROM area (that is an even address). (Note 6) Software Commands Table 30.1 lists the software commands available with the M16C/62A (flash memory version). After setting the CPU rewrite mode select bit to 1, write a software command to specify an erase or program operation. Note that when entering a software command, the upper byte (D 8 to D15) is ignored. The content of each software command is explained below. Table 30.1 List of software commands (CPU rewrite mode) Read Array Command (FF16) The read array mode is entered by writing the command code “FF16” in the first bus cycle. When an even address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data bus (D 0–D 15), 16 bits at a time. The read array mode is retained intact until another command is written. Read Status Register Command (7016) When the command code “7016” is written in the first bus cycle, the content of the status register is read out at the data bus (D0–D 7) by a read in the second bus cycle. (Set an address to even address in the user ROM area). The status register is explained in the next section. Clear Status Register Command (50 16) This command is used to clear the bits SR3 to 5 of the status register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code “50 16” in the first bus cycle.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 285 30. CPU Rewrite ModepuorG08/C61M Data Protect Function (Block Lock) Each block in Figure 29.3 has a nonvolatile lock bit to specify that the block be protected (locked) against erase/write. The lock bit program command is used to set the lock bit to 0 (locked). The lock bit of each block can be read out using the read lock bit status command. Whether block lock is enabled or disabled is determined by the status of the lock bit and how the flash memory control register 0’s lock bit disable bit is set. (1) When the lock bit disable bit = 0, a specified block can be locked or unlocked by the lock bit status (lock bit data). Blocks whose lock bit data = 0 are locked, so they are disabled against erase/write. On the other hand, the blocks whose lock bit data = 1 are not locked, so they are enabled for erase/ write. (2) When the lock bit disable bit = 1, all blocks are nonlocked regardless of the lock bit data, so they are enabled for erase/write. In this case, the lock bit data that is 0 (locked) is set to 1 (nonlocked) after erasure, so that the lock bit-actuated lock is removed. Status Register The status register indicates the operating status of the flash memory and whether an erase or program operation has terminated normally or in an error. The content of this register can be read out by only writing the read status register command (70 16). Table 30.2 details the status register. The status register is cleared by writing the Clear Status Register command (5016). After a reset, the status register is set to “8016.” Each bit in this register is explained below. Write state machine (WSM) status (SR7) After power-on, the write state machine (WSM) status is set to 1. The write state machine (WSM) status indicates the operating status of the device, as for output on the ____ RY/BY pin. This status bit is set to 0 during auto write or auto erase operation and is set to 1 upon completion of these operations. Erase status (SR5) The erase status informs the operating status of auto erase operation to the CPU. When an erase error occurs, it is set to 1. The erase status is reset to 0 when cleared.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 286 30. CPU Rewrite ModepuorG08/C61M Each bit of SRD SR4 (bit4) SR5 (bit5) SR7 (bit7) SR6 (bit6) Status name Definition SR1 (bit1) SR2 (bit2) SR3 (bit3) SR0 (bit0) "1" "0" Program status Erase status Write state machine (WSM) status Reserved Reserved Reserved Block status after program Reserved Ready Busy Terminated in error Terminated in error Terminated in error Terminated normally Terminated normally Terminated normally Program status (SR4) The program status informs the operating status of auto write operation to the CPU. When a write error occurs, it is set to 1. The program status is reset to 0 when cleared. When an erase command is in error (which occurs if the command entered after the block erase command (20 16) is not the confirmation command (D016), both the program status and erase status (SR5) are set to 1. When the program status or erase status = 1, the following commands entered by command write are not accepted. Also, in one of the following cases, both SR4 and SR5 are set to 1 (command sequence error): (1) When the valid command is not entered correctly (2) When the data entered in the second bus cycle of lock bit program (77 16/D016), block erase (2016/D016), or erase all unlock blocks (A716/D016) is not the D016 or FF16. However, if FF16 is entered, read array is assumed and the command that has been set up in the first bus cycle is canceled. Block status after program (SR3) If excessive data is written (phenomenon whereby the memory cell becomes depressed which results in data not being read correctly), “1” is set for the program status after-program at the end of the page write operation. In other words, when writing ends successfully, “80 16” is output; when writing fails, “9016” is output; and when excessive data is written, “8816” is output. Table 30.2 Definition of each bit in status register

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 287 30. CPU Rewrite ModepuorG08/C61M Read status register SR4=1 and SR5 =1 ? NO Command sequence error YES SR5=0? YES Block erase errorNO SR4=0? YES Program error (page or lock bit) NO SR3=0? YES Program error (block) NO End (block erase, program) Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should a block erase error occur, the block in error cannot be used. Execute the read lock bit status command (71 16) to see if the block is locked. After removing lock, execute write operation in the same way. If the error still occurs, the page in error cannot be used. After erasing the block in error, execute write operation one more time. If the same error still occurs, the block in error cannot be used. Note: When one of SR5 to SR3 is set to 1, none of the page program, block erase, erase all unlock blocks and lock bit program commands is accepted. Execute the clear status register command (50 16) before executing these commands. (When reading the status register, set an even number address in the user ROM area). Full Status Check By performing full status check, it is possible to know the execution results of erase and program operations. Figure 30.8 shows a full status check flowchart and the action to be taken when each error occurs. Figure 30.8 Full status check flowchart and remedial procedure for errors

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 288 30. CPU Rewrite ModepuorG08/C61M Functions To Prevent the Flash Memory from Rewriting To prevent the contents of the flash memory version from being read out or rewritten easily, the device incorporates a ROM code protect function for use in parallel I/O mode and an ID code verify function for use in standard serial I/O mode. ROM code protect function The ROM code protect function reading out or modifying the contents of the flash memory version by using the ROM code protect control address (0FFFFFF 16) during parallel I/O mode. Figure 30.9 shows the ROM code protect control address (0FFFFFF16). (This address exists in the user ROM area.) If one of the pair of ROM code protect bits is set to 0, ROM code protect is turned on, so that the contents of the flash memory version are protected against readout and modification. If both of the two ROM code protect reset bits are set to “00,” ROM code protect is turned off, so that the contents of the flash memory version can be read out or modified. Once ROM code protect is turned on, the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/ O or some other mode to rewrite the contents of the ROM code protect reset bits. Figure 30.9 ROM code protect control address ROM Code Protect Control Address(5) Symbol Address Factory Setting ROMCP FFFFFF 16 FF 16(4) RW RW RW Bit Name FunctionBit Symbol NOTES: 1. When the ROM code protection is active by the ROMCP1 bit setting, the flash memory is protected against reading or rewriting in parallel I/O mode. 2. Set the bit 5 to bit 0 to "1111112" when the ROMCP1 bit is set to a value other than "112". If the bit 5 to bit 0 are set to values other than "1111112", the ROM code protection may not become active by setting the ROMCP1 bit to a value other than "112". 3. To make the ROM code protection inactive, erase a block including the ROMCP address in standard serial I/O mode or CPU rewrite mode. 4. The ROMCP address is set to "FF16" when a block, including the ROMCP address, is erased. 5. When a value of the ROMCP address is "0016" or "FF16", the ROM code protect function is disabled. b7 b6 b5 b4 b3 b2 b1 b0 (b5 - b0) ROMCP1 ROM Code Protect Level 1 Set Bit(1, 2, 3, 4) b7 b6 Reserved Bit Set to "1" 0 0 : ROM code protection active 0 1 : ROM code protection active 1 0 : ROM code protection active 1 1 : ROM code protection inactive 111 111

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 289 30. CPU Rewrite ModepuorG08/C61M ID Code Verify Function Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the peripheral unit is compared with the ID code written in the flash memory to see if they match. If the ID codes do not match, the commands sent from the peripheral unit are not accepted. The ID code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFFDF 16, 0FFFFE316, 0FFFFEB 16, 0FFFFEF16, 0FFFFF316, 0FFFFF716, and 0FFFFFB16. Write a program which has had the ID code preset at these addresses to the flash memory. Figure 30.10 ID code store addresses Reset vector Watchdog timer vector Address match vector BRK instruction vector Overflow vector Undefined instruction vector ID7 ID6 ID5 ID4 ID3 ID2 ID1 NMI vector 0FFFFFC 16 to 0FFFFFF16 0FFFFF8 16 to 0FFFFFB16 0FFFFF4 16 to 0FFFFF716 0FFFFF0 16 to 0FFFFF316 0FFFFEC 16 to 0FFFFEF16 0FFFFE8 16 to 0FFFFEB16 0FFFFE4 16 to 0FFFFE716 0FFFFE0 16 to 0FFFFE316 0FFFFDC 16 to 0FFFFDF16 4 bytes Address

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 290 31. Parallel I/O ModepuorG08/C61M 31. Parallel I/O Mode Use an exclusive programer supporting M16C/80 (flash memory version). Refer to the instruction manual of each programer maker for the details of use. User ROM and Boot ROM Areas In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 29.3 can be rewritten. Both areas of flash memory can be operated on in the same way. Program and block erase operations can be performed in the user ROM area. The user ROM area and its blocks are shown in Figure 29.3. The boot ROM area is 8 Kbytes in size. In parallel I/O mode, it is located at addresses 0FFE000 16 through 0FFFFFF 16. Make sure program and block erase operations are always performed within this address range. (Access to any location outside this address range is prohibited.) In the boot ROM area, an erase block operation is applied to only one 8 Kbyte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. Therefore, using the device in standard serial input/output mode, you do not need to write to the boot ROM area.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 291 31. Parallel I/O ModepuorG08/C61M Pin Description VCC ,VSS Apply 4.2V to 5.5V to Vcc pin and 0 V to Vss pin. CNV SS Connect to Vcc pin. RESET Reset input pin. While reset is "L" level, a 20 cycle or longer clock must be input to XIN pin. XIN Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin.XOUT BYTE Connect this pin to Vcc or Vss. AV CC , AVSS VREF Connect AVSS to Vss and AVcc to Vcc, respectively. Enter the reference voltage for A/D converter from this pin. P00 to P07 Input "H" or "L" level signal or open. P10 to P17 Input "H" or "L" level signal or open. P20 to P27 Input "H" or "L" level signal or open. P30 to P37 Input "H" or "L" level signal or open. P40 to P47 Input "H" or "L" level signal or open. P51 to P54, P56, P57 Input "H" or "L" level signal or open. P50 Input "H" level signal. P55 Input "L" level signal. P60 to P63 Input "H" or "L" level signal or open. P64 P65 P66 Serial data input pin P67 Serial data output pin P70 to P77 Input "H" or "L" level signal or open. P80 to P84, P86, P87 Input "H" or "L" level signal or open. P90 to P97 Input "H" or "L" level signal or open. P100 to P107 Input "H" or "L" level signal or open. Name Power input CNV SS Reset input Clock input Clock output BYTE Analog power supply input Reference voltage input Input port P0 Input port P1 Input port P2 Input port P3 Input port P4 Input port P5 CE input EPM input Input port P6 BUSY output SCLK input RxD input TxD output Input port P7 Input port P8 Input port P9 Input port P10 I/O I I I O I I I I I I I I I I I O I I O I I I I P85 NMI input I Connect this pin to Vcc. I Standard serial mode 1: BUSY signal output pin Standard serial mode 2: Monitors the program operation check Standard serial mode 1: Serial clock input pin Standard serial mode 2: Input "L" level signal. P110 to P114 Input "H" or "L" level signal or open. (Note)Input port P11 I P120 to P127 Input "H" or "L" level signal or open. (Note)Input port P12 I P130 to P137 Input "H" or "L" level signal or open. (Note)Input port P13 I P140 to P146 Input "H" or "L" level signal or open. (Note)Input port P14 I P150 to P157 Input "H" or "L" level signal or open. (Note)Input port P15 I Pin functions (Flash memory standard serial I/O mode) Note: Port P11 to P15 exist in 144-pin version.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 292 31. Parallel I/O ModepuorG08/C61M Figure 31.1 Pin connections for standard serial I/O mode (1) 10 11 13 14 17 18 20 21 24 25 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 81828384858687888990919293949596979899100 0/D 1/D 2/D 3/D 4/D 5/D 6/D 7/D P10/D8 P11/D9 P12/D10 P13/D11 P14/D12 V REF AV SS VCC XIN XOUT VSS RESET CNVss P87/XCIN P86/XCOUT BYTE P20/A0(/D0) P21/A1(/D1) P22/A2(/D2) P23/A3(/D3) P24/A4(/D4) P25/A5(/D5) P26/A6(/D6) P27/A7(/D7) P30/A8(MA0)(/D8) P31/A9(MA1)(/D9) P32/A10(MA2)(/D10) P33/A11(MA3)(/D11) P34/A12(MA4)(/D12) P35/A13(MA5)(/D13) P36/A14(MA6)(/D14) P37/A15(MA7)(/D15) P40/A16(MA8) P41/A17(MA9) P42/A18(MA10) P43/A19(MA11) P74/TA2OUT /W P76/TA3OUT P77/TA3IN 5/HOLD 4/HLDA/ALE 3/BCLK/ALE/CLK OUT Vcc Vss 7/RDY 5/CS2/A 6/CS1/A AVcc 3/T XD 5/CLK 6/RxD 7/T XD 1/CLK 2/RxD P10 0/AN P10 1/AN P10 2/AN P10 3/AN P95/ANEX0/CLK 4 P96/ANEX1/TXD 4/SDA4/SRxD4 P91/TB1IN/RXD 3/SCL3/STxD3 P92/TB2IN/TXD 3/SDA3/SRxD3 P80/TA4OUT /U 0/CTS 0/RTS 4/CTS 1/RTS 1/CTS 0/CLKS P72/CLK2/TA1OUT /V P82/INT0 P71/RxD2/SCL2/TA0IN/TB5IN P83/INT1 P85/NMI 7/AD TRG XD 4/SCL 4/STxD 4/CS3/A (MA12) P90/TB0IN/CLK3 P70/TXD 2/SDA2/TA0OUT P84/INT2 P81/TA4IN/U P73/CTS2/RTS2/TA1IN/V P75/TA2IN/W P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 P10 7/AN 7/KI P10 6/AN 6/KI P10 5/AN 5/KI P10 4/AN KI 2/RD/DW 1/WRH/BHE/CASH 0/WRL/WR/CASL 7/CS0/A P94/DA1/TB4IN/CTS4/RTS4/SS4 P93/DA0/TB3IN/CTS3/RTS3/SS3 6/ALE/RAS Signal Value CNVss Vcc EPM Vss RESET Vss >> Vcc CE Vcc Mode setting Vcc Vss TxD RxD SCLK Connect oscillation circuit CNVss CEEPMBUSY RESET M16C/80(100-pin) Group Flash Memory Version (100P6S)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 293 31. Parallel I/O ModepuorG08/C61M Figure 31.2 Pin connections for standard serial I/O mode (2) 4/CTS 1/RTS 1/CTS 0/CLKS 1/RxD 2/SCL 2/TA0 IN /TB5 IN P93/DA0/TB3IN/CTS3/RTS3/SS3 7/AD TRG /RxD 4/SCL 4/STxD 6/ANEX1/TxD 4/SDA 4/SRxD 0/T XD 2/SDA 2/TA0 OUT 1/WRH/BHE/CASH 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 0/D 1/D 2/D 3/D 4/D 5/D 6/D 7/D 0/D 1/D 2/D P13/D11 P14/D12 V REF AV SS VCC XIN XOUT VSS RESET CNVss P87/XCIN P86/XCOUT BYTE P20/A0(/D0) P21/A1(/D1) P22/A2(/D2) P23/A3(/D3) P24/A4(/D4) P25/A5(/D5) P26/A6(/D6) P27/A7(/D7) P30/A8(MA0)(/D8) P31/A9(MA1)(/D9) P32/A10(MA2)(/D10) P33/A11(MA3)(/D11) P34/A12(MA4)(/D12) P35/A13(MA5)(/D13) P36/A14(MA6)(/D14) P37/A15(MA7)(/D15) P40/A16(MA8) P41/A17(MA9) 2/A /(MA10) 3/A /(MA11) P74/TA2OUT /W P76/TA3OUT P77/TA3IN 5/HOLD 3/BCLK/ALE/CLK OUT Vcc Vss 7/RDY 5/CS2/A 6/CS1/A 7/CS0/A AVcc 3/T XD 5/CLK 6/RxD 7/T XD 1/CLK 2/RxD P10 0/AN P10 1/AN P10 2/AN P10 3/AN 5/ANEX0/CLK P91/TB1IN/RxD3/SCL3/STxD3 P92/TB2IN/TxD3/SDA3/SRxD3 P80/TA4OUT /U 0/CTS 0/RTS P82/INT0 P83/INT1 P85/NMI 4/CS3/A (MA12) P90/TB0IN/CLK3 P84/INT2 2/CLK 2/TA1 OUT P75/TA2IN/W P73/CTS2/RTS2/TA1IN/V P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 P10 7/AN 7/KI P10 6/AN 6/KI P10 5/AN 5/KI P10 4/AN KI P81/TA4IN/U P94/DA1/TB4IN/CTS4/RTS4/SS4 6/ALE/RAS 4/HLDA/ALE 2/RD/DW 0/WRL/WR/CASL CNV SS RESET V SS V CC CEBUSY EPMSCLK R XD TXD Connect oscillation circuit Signal Value CNVss Vcc EPM Vss RESET Vss >> Vcc CE Vcc Mode setting M16C/80(100-pin) Group Flash Memory Version (100P6Q)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 294 31. Parallel I/O ModepuorG08/C61M Figure 31.3 Pin connections for standard serial I/O mode (3) 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 P14 P14 P14 P14 P14 P14 P14 BYTECNV SS 7/X CIN 6/X COUT X OUT V SS X IN V CC 0/TA 4OUT 7/TA 3IN 6/TA 3OUT 4/TA 2OUT 2/CLK 2/TA 1OUT 1/R XD 2/SCL 2/TA 0IN /TB 5IN RESET P8 5/NMI 4/INT 3/INT 2/INT 1/TA 4IN 5/TA 2IN 3/CTS 2/RTS 2/TA 1IN P70/TXD2/SDA2/TA0OUT P67/TXD1 VCC P66/RXD1 VSS P65/CLK1 P63/TXD0 P62/RXD0 P61/CLK0 P137 P136 P135 P134 P133 VSS P132 VCC P131 P130 P53/BCLK/ALE/CLKOUT P127 P126 P125 P64/CTS1/RTS1/CTS0/CLKS1 P60/CTS0/RTS0 P56/ALE/RAS P55/HOLD P54/HLDA/ALE P52/RD/DW P51/WRH/BHE/CASH P50/WRL/WR/CASL P47/CS0/A23 P46/CS1/A22 P45/CS2/A21 P44/CS3/A20(MA12) 3/A (MA11) V CC 2/A (MA10) V SS 1/A (MA9) 0/A (MA8) 7/A (MA7)(/D 6/A (MA6)(/D 5/A (MA5)(/D 4/A (MA4)(/D 3/A (MA3)(/D 2/A (MA2)(/D 1/A 9(MA1)(/D P12 P12 P12 P12 P12 V CC 0/A 8(MA0)(/D 7/A 7(/D 6/A 6(/D 5/A 5(/D 4/A 4(/D 3/A 3(/D 2/A 2(/D 1/A 1(/D 0/A 0(/D V SS 4/D 3/D 2/D 1/D 5/D /INT3 6/D /INT4 7/D /INT5 P10/D8 P07/D7 P06/D6 P05/D5 P04/D4 P114 P113 P112 P111 P110 P03/D3 P02/D2 P01/D1 P00/D0 P157 P156 P155 P154 P153 P152 P151 VSS P150 VCC P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVCC P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P97/ADTRG /RXD4/ SCL4/STxD4 7374757677798081828384858687888990919293949596979899100101102103104105106107108 78 P57/RDY 123 4 7 6 8 9 1 0 1 1 1 21 3 1 41 5 1 61 7 1 81 92 02 1 2 22 3 2 42 52 6 2 7 2 82 93 05 31 32 33 34 35 36 M16C/80(144-pin) Group Flash Memory Version (144P6Q) CNV SS RESET EPM CE VCC VSS TxD RxD SCLK BUSY Signal Value CNVss Vcc EPM Vss RESET Vss >> Vcc CE Vcc Mode setting Connect oscillation circuit 6/ANEX 1/T XD 4/SDA 4/SRxD 5/ANEX 0/CLK 2/TB 2IN XD 3/SDA 3/SRxD 1/TB 1IN XD 3/SCL 3/STxD 0/TB 0IN /CLK3 4/DA 1/TB 4IN /CTS 4/RTS 4/SS 3/DA 0/TB 3IN /CTS 3/RTS 3/SS

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 295 32. Standard serial I/O modepuorG08/C61M 32. Standard serial I/O mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is serial. There are actually two standard serial I/O modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. Both modes require a purpose-specific peripheral unit. The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory rewrite (uses the CPU's rewrite mode), rewrite data input and so forth. It is started when the reset is re- leased, which is done when the P50 (CE) pin is "H" level, the P55 (EPM) pin "L" level and the CNVss pin "H" level. (In the ordinary command mode, set CNVss pin to "L" level.) This control program is written in the boot ROM area when the product is shipped from the factory. Accord- ingly, make note of the fact that the standard serial I/O mode cannot be used if the boot ROM area is rewritten in the parallel I/O mode. Figures 31.1 and 31.3 show the pin connections for the standard serial I/ O mode. Serial data I/O uses UART1 and transfers the data serially in 8-bit units. Standard serial I/O switches between mode 1 (clock synchronized) and mode 2 (clock asynchronized) according to the level of CLK 1 pin when the reset is released. To use standard serial I/O mode 1 (clock synchronized), set the CLK1 pin to "H" level and release the reset. The operation uses the four UART1 pins CLK1, RxD1, TxD1 and RTS1 (BUSY). The CLK1 pin is the transfer clock input pin through which an external transfer clock is input. The TxD1 pin is for CMOS output. The RTS 1 (BUSY) pin outputs an "L" level when ready for reception and an "H" level when reception starts. To use standard serial I/O mode 2 (clock asynchronized), set the CLK1 pin to "L" level and release the reset. The operation uses the two UART1 pins RxD1 and TxD1. In the standard serial I/O mode, only the user ROM area indicated in Figure 32.17can be rewritten. The boot ROM cannot. In the standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, com- mands sent from the peripheral unit (programmer) are not accepted unless the ID code matches.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 296 32. Standard serial I/O modepuorG08/C61M

32.1 Overview of standard serial I/O mode 1 (clock synchronized)

In standard serial I/O mode 1, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial I/O (UART1). Standard serial I/O mode 1 is engaged by releasing the reset with the P6 5 (CLK1) pin "H" level. In reception, software commands, addresses and program data are synchronized with the rise of the trans- fer clock that is input to the CLK 1 pin, and are then input to the MCU via the RxD1 pin. In transmission, the read data and status are synchronized with the fall of the transfer clock, and output from the TxD1 pin. The TxD1 pin is for CMOS output. Transfer is in 8-bit units with LSB first. When busy, such as during transmission, reception, erasing or program execution, the RTS1 (BUSY) pin is "H" level. Accordingly, always start the next transfer after the RST1 (BUSY) pin is "L" level. Also, data and status registers in memory can be read after inputting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following are explained software commands, status registers, etc.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 297 32. Standard serial I/O modepuorG08/C61M Software Commands Table 31.1 lists software commands. In the standard serial I/O mode 1, erase operations, programs and reading are controlled by transferring software commands via the RxD1 pin. Software commands are explained here below. Table 32.1 Software commands (Standard serial I/O mode 1) Control command 2nd byte 3rd byte 4th byte 5th byte 6th byte

1 Page read

2 Page program

3 Block erase

4 Erase all unlocked blocks

5 Read status register

6 Clear status register

7 Read lock bit status

8 Lock bit program

9 Lock bit enable

10 Lock bit disable

11 Code processing function

12 Download function

13 Version data output function

14 Boot ROM area output

15 Read check data

(middle) Address (middle) Address (middle) D0 16 SRD output Address (middle) Address (middle) Address (low) Size (low) Version data output Address (middle) Check data (low) Address (high) Address (high) Address (high) SRD1 output Address (high) Address (high) Address (middle) Size (high) Version data output Address (high) Check data (high) Data output Data input D0 16 Lock bit data output D0 16 Address (high) Check- sum Version data output Data output Data output Data input ID size Data input Version data output Data output Data output Data input ID1 To required number of times Version data output Data output Data output to 259th byte Data input to 259th byte To ID7 Version data output to 9th byte Data output to 259th byte FF 16 4116 2016 A7 16 7016 5016 7116 7716 7A 16 7516 F516 FA 16 FB 16 FC 16 FD 16 When ID is not verified Not acceptable Not acceptable Not acceptable Not acceptable Acceptable Not acceptable Not acceptable Not acceptable Not acceptable Not acceptable Acceptable Not acceptable Acceptable Not acceptable Not acceptable 1st byte transfer Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is trans- ferred from the peripheral unit to the flash memory microcomputer. Note 2: SRD refers to status register data. SRD1 refers to status register data1 . Note 3: All commands can be accepted when the flash memory is totally blank.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 300 32. Standard serial I/O modepuorG08/C61M Block Erase Command This command erases the data in the specified block. Execute the block erase command as explained here following. (1) Transfer the “20 16” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code “D0 16” with the 4th byte. With the verify command code, the erase operation will start for the specified block in the flash memory. Write the highest address of the specified block for addresses A 16 to A23. When block erasing ends, the RTS1 (BUSY) signal changes from the “H ” to the “L” level. After block erase ends, the result of the block erase operation can be known by reading the status register. For more information, see the section on the status register. Each block can be erase-protected with the lock bit. For more information, see the section on the data protection function. Figure 32.5 Timing for block erasing A8 to A15 A16 to A232016 D0 16 CLK1 RxD1 TxD1 RTS1(BUSY) (M16C reception data) (M16C transmit data)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 306 32. Standard serial I/O modepuorG08/C61M Read Check Data This command reads the check data that confirms that the write data, which was sent with the page program command, was successfully received. (1) Transfer the "FD 16" command code with the 1st byte. (2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd. To use this read check data command, first execute the command and then initialize the check data. Next, execute the page program command the required number of times. After that, when the read check command is executed again, the check data for all of the read data that was sent with the page program command during this time is read. The check data is the result of CRC operation of write data. Figure 32.16 Timing for the read check data Check data (low) CLK1 RxD1 TxD1 RTS1(BUSY) FD 16 (M16C reception data) (M16C transmit data) Check data (high)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 307 32. Standard serial I/O modepuorG08/C61M Data Protection (Block Lock) Each of the blocks in Figure 32.17 have a nonvolatile lock bit that specifies protection (block lock) against erasing/writing. A block is locked (writing “0” for the lock bit) with the lock bit program command. Also, the lock bit of any block can be read with the read lock bit status command. Block lock disable/enable is determined by the status of the lock bit itself and execution status of the lock bit disable and lock enable bit commands. (1) After the reset has been cancelled and the lock bit enable command executed, the specified block can be locked/unlocked using the lock bit (lock bit data). Blocks with a “0” lock bit data are locked and cannot be erased or written in. On the other hand, blocks with a “1” lock bit data are unlocked and can be erased or written in. (2) After the lock bit enable command has been executed, all blocks are unlocked regardless of lock bit data status and can be erased or written in. In this case, lock bit data that was “0” before the block was erased is set to “1” (unlocked) after erasing, therefore the block is actually unlocked with the lock bit. Figure 32.17 Blocks in the user area 0FC0000 16 0FD0000 16 Block 6 : 64K byte Block 5 : 64K byte 0FE0000 16 Block 4 : 64K byte 0FF000016 Block 3 : 32K byte 0FF800016 Block 2 : 8K byte 0FFA000 16 Block 1 : 8K byte Block 0 : 16K byte0FFC000 16 User ROM area 0FFFFFF 16 Flash memory size Flash memory start address

128 Kbytes 0FE0000 16

256 Kbytes 0FC0000 16

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 308 32. Standard serial I/O modepuorG08/C61M Status Register (SRD) The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read status register command (70 16). Also, the status register is cleared by writing the clear status register command (5016). Table 32.2 gives the definition of each status register bit. After clearing the reset, the status register outputs “80 16”. Table 32.2 Status register (SRD) Write State Machine (WSM) Status (SR7) The write state machine (WSM) status indicates the operating status of the flash memory. When power is turned on, “1” (ready) is set for it. The bit is set to “0” (busy) during an auto write or auto erase operation, but it is set back to “1” when the operation ends. Erase Status (SR5) The erase status reports the operating status of the auto erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is set to “0”. Program Status (SR4) The program status reports the operating status of the auto write operation. If a write error occurs, it is set to “1”. When the program status is cleared, it is set to “0”. Program Status After Program (SR3) If excessive data is written (phenomenon whereby the memory cell becomes depressed which results in data not being read correctly), “1” is set for the program status after-program at the end of the page write operation. In other words, when writing ends successfully, “80 16” is output; when writing fails, “9016” is output; and when excessive data is written, “8816” is output. If “1” is written for any of the SR5, SR4 or SR3 bits, the page program, block erase, erase all unlocked blocks and lock bit program commands are not accepted. Before executing these commands, execute the clear status register command (50 16) and clear the status register. SRD0 bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Status name Write state machine (WSM) status Reserved Erase status Program status Block status after program Reserved Reserved Reserved Definition "1" "0" Ready Terminated in error Terminated in error Terminated in error Busy Terminated normally Terminated normally Terminated normally

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 309 32. Standard serial I/O modepuorG08/C61M Status Register 1 (SRD1) Status register 1 indicates the status of serial communications, results from ID checks and results from check sum comparisons. It can be read after the SRD by writing the read status register command (7016). Also, status register 1 is cleared by writing the clear status register command (5016). Table 31.3 gives the definition of each status register 1 bit. “0016” is output when power is turned ON and the flag status is maintained even after the reset. Table 32.3 Status register 1 (SRD1) Boot Update Completed Bit (SR15) This flag indicates whether the control program was downloaded to the RAM or not, using the down- load function. Check Sum Consistency Bit (SR12) This flag indicates whether the check sum matches or not when a program, is downloaded for execu- tion using the download function. ID Check Completed Bits (SR11 and SR10) These flags indicate the result of ID checks. Some commands cannot be accepted without an ID check. Data Reception Time Out (SR9) This flag indicates when a time out error is generated during data reception. If this flag is attached during data reception, the received data is discarded and the microcomputer returns to the command wait state. SRD1 bits SR15 (bit7) SR14 (bit6) SR13 (bit5) SR12 (bit4) SR11 (bit3) SR10 (bit2) SR9 (bit1) SR8 (bit0) Status name Boot update completed bit Reserved Reserved Checksum match bit ID check completed bits Data receive time out Reserved Definition "1" "0" Update completed Match Not update Mismatch Normal operation Not verified Verification mismatch Reserved Verified Time out

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 311 32. Standard serial I/O modepuorG08/C61M

32.2 Overview of standard serial I/O mode 2 (clock asynchronized)

In standard serial I/O mode 2, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using 2-wire clock-asynchronized serial I/O (UART1). Standard serial I/O mode 2 is engaged by releasing the reset with the P6 5 (CLK1) pin "L" level. The TxD1 pin is for CMOS output. Data transfer is in 8-bit units with LSB first, 1 stop bit and parity OFF. After the reset is released, connections can be established at 9,600 bps when initial communications (Fig- ure 32.20) are made with a peripheral unit. However, this requires a main clock with a minimum 2 MHz input oscillation frequency. Baud rate can also be changed from 9,600 bps to 19,200, 38,400, 57,600 or 115,200 bps by executing software commands. However, communication errors may occur because of the oscilla- tion frequency of the main clock. If errors occur, change the main clock's oscillation frequency and the baud rate. After executing commands from a peripheral unit that requires time to erase and write data, as with erase and program commands, allow a sufficient time interval or execute the read status command and check how processing ended, before executing the next command. Data and status registers in memory can be read after transmitting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following are explained initial communications with peripheral units, how frequency is identified and software commands. Initial communications with peripheral units After the reset is released, the bit rate generator is adjusted to 9,600 bps to match the oscillation fre- quency of the main clock, by sending the code as prescribed by the protocol for initial communications with peripheral units (Figure 32.20). (1) Transmit "00 16" from a peripheral unit 16 times. (The MCU with internal flash memory sets the bit rate generator so that "0016" can be successfully received.) (2) The MCU with internal flash memory outputs the "B016" check code and initial communications end successfully *1. Initial communications must be transmitted at a speed of 9,600 bps and a transfer interval of a minimum 15 ms. Also, the baud rate at the end of initial communications is 9,600 bps. *1. If the peripheral unit cannot receive "B016" successfully, change the oscillation frequency of the main clock. Figure 32.20 Peripheral unit and initial communication MCU with internal flash memory Peripheral unit (1) Transfer "0016" 16 times At least 15ms transfer interval 1st 2nd 15 th 16th (2) Transfer check code "B016" "0016" "0016" "0016" "B016" "0016" Reset The bit rate generator setting completes (9600bps)

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 312 32. Standard serial I/O modepuorG08/C61M How frequency is identified When "0016" data is received 16 times from a peripheral unit at a baud rate of 9,600 bps, the value of the bit rate generator is set to match the operating frequency (2 - 20 MHz). The highest speed is taken from the first 8 transmissions and the lowest from the last 8. These values are then used to calculate the bit rate generator value for a baud rate of 9,600 bps. Baud rate cannot be attained with some operating frequencies. Table 32.4 gives the operation frequency and the baud rate that can be attained for. Table 32.4 Operation frequency and the baud rate Operation frequency (MH Z) Baud rate 9,600bps Baud rate 19,200bps Baud rate 38,400bps Baud rate 57,600bps 20MHz 16MH Z 12MH Z 11MH Z 10MH Z 8MH Z 7.3728MH Z 6MH Z 5MH Z 4.5MH Z 4.194304MH Z 4MH Z 3.58MH Z 3MH Z 2MH Z : Communications possible – : Communications not possible Baud rate 115,200bps

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 313 32. Standard serial I/O modepuorG08/C61M Software Commands Table 32.5 lists software commands. In the standard serial I/O mode 2, erase operations, programs and reading are controlled by transferring software commands via the RxD1 pin. Standard serial I/O mode 2 adds five transmission speed commands - 9,600, 19,200, 38,400, 57,600 and 115,200 bps - to the soft- ware commands of standard serial I/O mode 1. Software commands are explained here below. Table 32.5 Software commands (Standard serial I/O mode 2) Control command 2nd byte 3rd byte 4th byte 5th byte 6th byte

16 Baud rate 9600

17 Baud rate 19200

18 Baud rate 38400

19 Baud rate 57600

20 Baud rate 115200

(middle) Address (middle) Address (middle) D0 16 SRD output Address (middle) Address (middle) Address (low) Size (low) Version data output Address (middle) Check data (low) B0 16 B1 16 B2 16 B3 16 B4 16 Address (high) Address (high) Address (high) SRD1 output Address (high) Address (high) Address (middle) Size (high) Version data output Address (high) Check data (high) Data output Data input D0 16 Lock bit data output D0 16 Address (high) Check- sum Version data output Data output Data output Data input ID size Data input Version data output Data output Data output Data input ID1 To required number of times Version data output Data output Data output to 259th byte Data input to 259th byte To ID7 Version data output to 9th byte Data output to 259th byte FF 16 4116 2016 A7 16 7016 5016 7116 7716 7A 16 7516 F516 FA 16 FB 16 FC 16 FD 16 B0 16 B1 16 B2 16 B3 16 B4 16 When ID is not verified Not acceptable Not acceptable Not acceptable Not acceptable Acceptable Not acceptable Not acceptable Not acceptable Not acceptable Not acceptable Acceptable Not acceptable Acceptable Not acceptable Not acceptable Acceptable Acceptable Acceptable Acceptable Acceptable 1st byte transfer Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is trans- ferred from the peripheral unit to the flash memory microcomputer. Note 2: SRD refers to status register data. SRD1 refers to status register data 1. Note 3: All commands can be accepted when the flash memory is totally blank.

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 324 33. Appendix External ROM version with built-in boot loaderpuorG08/C61M M30800SFP-BL M30800SGP-BL M30802SGP-BL M30803SFP-BL

10 Kbytes 100P6S-A

RAM capacityROM capacity Package type RemarksType No M30803SGP-BL M30805SGP-BL

24 Kbytes

Appendix External ROM version with built-in boot loader External ROM version of M16C/80 is available with built-in boot loader (firmware). By using the boot loader, users can download their rewrite program of Flash memory to the internal RAM. When using the following Flash memory*, reprogramming of the external Flash memory can be done without downloading the rewrite program. For more detail, please refer to the "Volume Boot Loader" in the application note of M16C/80 external ROM version. *: M5M29GB/T160BVP, M5M29GB/T320BVP and the equivalent of these. The following shows Renesas plans to develop a line of M16C/80 products with built-in boot loader. (1) ROM capacity (2) Package 100P6S-A ... Plastic molded QFP 100P6Q-A ... Plastic molded QFP 144P6Q-A ... Plastic molded QFP Figure 33.1 ROM Expansion The following lists the M16C/80 products to be supported in the future. ROM size (Bytes) M30805SGP-BL M30803SFP/GP-BL External ROM version External ROM 256K 128K M30802SGP-BL M30800SFP/GP-BL Table 33.1 Product List

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 325 33. Appendix External ROM version with built-in boot loaderpuorG08/C61M Figure 33.2 Type No., memory size, and package Package type: FP : Package 100P6S-A GP : Package 100P6Q-A, 144P6Q-A ROM No. Omitted for blank external ROM version and flash memory version ROM capacity: C : 128K bytes G : 256K bytes Memory type: M : Mask ROM version S : External ROM version F : Flash memory version Type No. M 3 0 8 0 2 M C – X X X G P – BL M16C/80 Group M16C Family Shows RAM capacity, pin count, etc (The value itself has no specific meaning) Boot loader

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 326 Package DimensionspuorG08/C61M QFP100-P-1420-0.65 1.58 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Alloy 42 100P6S-A Plastic 100pin 14✕ 20mm body QFP 0.1 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.35 ––I2 1.3 ––M D 14.6 ––M E 20.6 10°0° 0.1 1.4 0.80.60.4 23.122.822.5 17.116.816.5 0.65 20.220.019.8 14.214.013.8 0.20.150.13 0.40.30.25 2.8 3.05 e e e E c H E H D D M D M E A F A1 A2 L y Recommended Mount Pad Detail F 100 x – – 0.13 b x M Recommended LQFP100-P-1414-0.50 Weight(g) – 0.63 JEDEC CodeEIAJ Package Code Lead Material Cu Alloy 100P6Q-A Plastic 100pin 14✕ 14mm body LQFP 0.1 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.225 ––I2 0.9 ––M D 14.4 ––M E 14.4 10°0° 0.1 1.0 0.70.50.3 16.216.015.8 16.216.015.8 0.5 14.114.013.9 14.114.013.9 0.1750.1250.105 0.280.180.13 1.4 1.7 e e E H E 5026 H D D A F y 100 Lp 0.45 0.6 0.25 0.75 0.08 x b x M A1 A2 L Detail F Lp c M D l2 b2 M E e Recommended Mount Pad Recommended Package Dimension

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 327 puorG08/C61M Package Dimensions LQFP144-P-2020-0.50 Weight(g) – 1.23 JEDEC CodeEIAJ Package Code Lead Material Cu Alloy 144P6Q-A Plastic 144pin 20✕ 20mm body LQFP 0.125 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.225 ––I2 0.95 ––M D 20.4 ––M E 20.4 8°0° 0.1 1.0 0.650.50.35 22.222.021.8 22.222.021.8 0.5 20.120.019.9 20.120.019.9 0.1750.1250.105 0.270.220.17 1.4 0.05 1.7 e A H D D H E E 37 72 108 109144 F e Lp 0.45 0.6 0.25 0.75 0.08 x M D l2 b2 M E e Recommended Mount Pad y b x M A1 A2 L Detail F Lp c Recommended

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 328 Register IndexpuorG08/C61M Register Index A AD0 to AD7 169 ADCON0 168, 170, 171, 172, 173, 174 ADCON1 168, 170, 171, 172, 173, 174 ADCON2 169 ADIC 63 AIER 73 B BCN2IC to BCN4IC 63 C CM0 46, 79 CM1 46 CPSRF 96, 107 CRCD 178 CRCIN 178 D DA0 to DA1 177 DACON 177 DCT0 to DCT3 84 DM0IC to DM3IC 63 DM0SL to DM3SL 82 DMA0 to DMA3 85 DMD0 to DMD1 83 DRA0 to DRA3 85 DRAMCONT 183 DRC0 to DRC3 84 DS 31 DSA0 to DSA3 85 DTT 113 F FMR0 to FMR1 276 I ICTB2 113 IDB0 to IDB1 113 IFSR 71 INT0IC to INT5IC 63 INVC0 to INVC1 112 K KUPIC 63 M MCD 47 O ONSF 96 P P0 to P10 197 P11 198 P12 to P13 197 P14 198 P15 197 PCR 206 PD0 to PD10 195 PD11 196 PD12 to P13 195 PD14 196 PD15 195 PM0 27 PM1 28 PRCR 55 PS0 to PS1 200 PS2 to PS3 201 PSC 203 PSL0 PSL2 202 PSL3 203 PUR0 to PUR2 204 PUR3 to PUR4 205 R REFCNT 185 RLVL 49, 64 RMAD0 to RMAD3 73 ROMCP 288 S S0RIC to S4RIC 63 S0TIC to S4TIC 63

923fo5002,20.guA00.1.veR 0010-7810B90JER Page 329 Register IndexpuorG08/C61M T TA0,TA3 95 TA0IC to TA4IC 63 TA0MR to TA4MR 94, 97, 98, 103, 104 TA1,TA2,TA4 95, 114 TA11,TA21,TA41 114 TA1MR,TA2MR,TA4MR 115 TA2MR to TA4MR 100 TABSR 95, 107, 114 TB0,TB1,TB3,TB4,TB5 107 TB0IC to TB5IC 63 TB0MR to TB5MR 106, 108, 109, 110 TB2 107, 114 TB2MR 115 TBSR 107 TRGSR 96, 114 U U0BRG to U4BRG 129 U0C0 to U2C0 131 U0C1 to U4C1 133 U0MR to U4MR 130, 139, 146 U0RB to U4RB 129 U0TB to U4TB 129 U2SMR to U4SMR 134, 156 U2SMR2 to U4SMR2 135, 156 U2SMR3 136 U3C0 to U4C0 132 U3SMR3 to U4SMR3 136, 163 UCON 134 UDF 95 W WCR 40 WDC 79 WDTS 79 X X0R to X15R 181 XYC 180 Y Y0R to Y15R 181

RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER HARDWARE MANUAL M16C/80 Group Publication Data : Rev.B Oct. 19, 1998 Rev.1.00 Aug. 02, 2005 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.

2-6-2, Ote-machi, Chiyoda-ku, Tokyo,100-0004, Japan

Product Information

M30802SGP-BL specifications and overview.

Summary

RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

Description

RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

Source title M30802SGP-BL Datasheet(PDF) - Renesas Technology Corp

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