M30800SAFP

32C80 RENESAS | Alldatasheet

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SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER page 1 65fo5002,10.voN01.1.veR 0110-8300B30JER REJ03B0038-0110 Rev.1.10 Nov. 01, 2005 1. Overview The M32C/80 Group microcomputer is a single-chip control unit that utilizes high-performance silicon gate CMOS technology with the M32C/80 series CPU core. The M32C/80 Group is available in 100-pin plastic molded LQFP/QFP package. With a 16-Mbyte address space, this microcomputer combines advanced instruction manipulation capabili- ties to process complex instructions by less bytes and execute instructions at higher speed. It incorporates a multiplier and DMAC adequate for office automation, communication devices and industrial equipments and other high-speed processing applications. The M32C/80 Group is ROMless device. Use the M32C/80 Group in microprocessor mode after reset.

1.1 Applications

Audio, cameras, office equipment, communications equipment, portable equipment, etc.

65fo5002,10.voN01.1.veR 0110-8300B30JER 1. Overview page 2 puorG08/C23M

1.2 Performance Overview

Table 1.1 lists performance overview of the M32C/80 Group. Table 1.1 M32C/80 Group Performance Item Performance CPU Basic Instructions 108 instructions Minimum Instruction Execution Time 31.3 ns ( f(BCLK)=32 MHz, VCC1 =4.2 to 5.5 V ) 41.7 ns ( f(BCLK)=24 MHz, VCC1 =3.0 to 5.5 V ) Operating Mode Single-chip mode, Memory expansion mode, Microprocessor mode Memory Space 16 Mbytes Memory Capacity See Table 1.2 PeripheralI/O Port 47 I/O pins (when using 16-bit bus) and 1 input pin function Multifunction Timer Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels Three-phase motor control circuit Intelligent I/O Communication Function 2 channels Serial I/O 5 channels Clock synchronous serial I/O, Clock asynchronous serial I/O, IEBus(1), I2C Bus(2) A/D Converter 10-bit A/D converter: 1 circuit, 10 channels D/A Converter 8 bits x 2 channels DMAC 4 channels DMAC II Can be activated by all peripheral function interrupt sources Immediate transfer, operation and chain transfer function CRC Calculation Circuit CRC-CCITT X/Y Converter 16 bits x 16 bits Watchdog Timer 15 bits x 1 channel (with prescaler) Interrupt 34 internal sources and 8 external sources, 5 software sources Interrupt priority level: 7 Clock Generation Circuit 4 circuits Main Clock oscillation circuit (*), Sub clock oscillation circuit (*), On-chip oscillator, PLL frequency synthesizer (*)Equipped with a built-in feedback resistor Oscillation Stop Detect Function Main clock oscillation stop detect circuit Charact- V CC1 =3.0 to 5.5 V, VCC2 =3.0 to VCC1 (f(BCLK)=24 MHz) eristicsPower Consumption 22 mA (V CC1 =V CC2 =5 V, f(BCLK)=32 MHz) 17 mA (VCC1 =V CC2 =3.3 V, f(BCLK)=24 MHz) 10 µA (VCC1 =V CC2 =3.3 V, f(BCLK)=32 kHz, in wait mode) Operating AmbientTemperature –20 to 85 oC, –40 to 85oC(optional) Package 100-pin plastic molded LQFP/QFP NOTES: 1. IEBus is a trademark of NEC Electronics Corporation. 2. I2C bus is a trademark of Koninklijke Philips Electronics N. V. All options are on a request basis.

65fo5002,10.voN01.1.veR 0110-8300B30JER 1. Overview page 3 puorG08/C23M

1.3 Block Diagram

Figure 1.1 shows a block diagram of the M32C/80 Group microcomputer. Figure 1.1 M32C/80 Group Block Diagram R0H R0L R1H R1L FB SB FLG INTB ISP USP PC SVF SVP VCT Multiplier M32C/80 series CPU core Clock Generating Circuit XIN - XOUT XCIN - XCOUT On-chip Oscillator PLL Frequency Synthesizer A/D Converter 1 circuit Standard: 8 inputs Maximum: 10 inputs UART/ Clock Synchronous Serial I/O 5 channels X/Y converter 16 bits X 16 bits CRC Calcilation Circuit (CCITT) X16+X12+X5+1 Timer (16 bits) Timer A: 5 channels Timer B: 6 channels Three-phase Motor Control Circuit Watchdog Timer (15 bits) D/A Converter 8 bits X 2 channels Peripheral Functions RAM Memory Port P0 Port P6 Port P7 8DMAC DMACII Intelligent I/O Communication Function 2 channels <VCC2 > Port P8 P85Port P9 Port P10 <VCC1> Port P1 Port P2 Port P3 Port P4 Port P5 NOTES: 1. Ports P0 to P5 function as bus control pins when using memory expansion mode or microprocessor mode. 2. Port P1 functions as I/O port when the microcomputer is placed in memory expansion mode or microprocessor mode and all external data buses are selected as 8-bit buses.

65fo5002,10.voN01.1.veR 0110-8300B30JER 1. Overview page 4 puorG08/C23M Figure 1.2 Product Numbering System

1.4 Product Information

Table 1.2 lists the product information. Figure 1.2 shows the product numbering system. Table 1.2 M32C/80 Group As of November, 2005 Package type: FP = Package PRQP0100JB-A (100P6S-A) GP = Package PLQP0100KB-A (100P6Q-A) Memory type: S = ROMless version M 3 0 8 0 0 S A G P - B L M32C/80 Group M16C Family RAM capacity, pin count, etc On-chip boot loader rebmuNepyTe pyTegakcaP MOR yticapaC MAR yticapaC skrameR 03MA S008P G) A-Q6P001(A-BK0010PQLP − K8 sselMOR 03MA S008P F) A-S6P001(A-BJ0010PQRP 03MA S008P GL B-) A-Q6P001(A-BK0010PQLP htiwsselMOR redaoltoobpihc-no03MA S008P FL B-) A-S6P001(A-BJ0010PQRP

65fo5002,10.voN01.1.veR 0110-8300B30JER 1. Overview page 5 puorG08/C23M

1.5 Pin Assignment

Figures 1.3 and 1.4 show pin assignments (top view). Figure 1.3 Pin Assignment 100 M32C/80 GROUP SRxD4 / SDA4 / TxD4 / ANEX1 / P96 CLK4 / ANEX0 / P95 SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94 SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93 SRxD3 / SDA3 / TxD3 / TB2IN / P92 STxD3 / SCL3 / RxD3 / TB1IN / P91 CLK3 / TB0IN / P90 BYTE CNVss XCIN / P87 XCOUT / P86 RESET XOUT Vss XIN Vcc1 NMI / P85 INT2 / P84 INT1 / P83 INT0 / P82 U / TA4IN / P81 ISRxD0 / U / TA4OUT / P80 ISCLK0 / TA3IN / P77 ISTxD0 / TA3OUT / P76 ISRxD1 / W / TA2IN / P75 ISCLK1 / W / TA2OUT / P74 ISTxD1 / SS2 / RTS2 / CTS2 / V / TA1IN / P73 CLK2 / V / TA1OUT / P72 STxD2 / SCL2 / RxD2 / TA0IN / TB5IN / P71 SRxD2 / SDA2 / TxD2 / TA0OUT / P70 P44 / CS3 / A20 P45 / CS2 / A21 P46 / CS1 / A22 P47 / CS0 / A23 P50 / WRL / WR P51 / WRH / BHE P52 / RD P53 / CLKOUT / BCLK / ALE P54 / HLDA / ALE P55 / HOLD P56 / ALE P57 / RDY P60 / CTS0 / RTS0 / SS0 P61 / CLK0 P62 / RxD0 / SCL0 / STxD0 P63 / TxD0 / SDA0 / SRxD0 P64 / CTS1 / RTS1 / SS1 P65 / CLK1 P66 / RxD1 / SCL1 / STxD1 P67 / TxD1 / SDA1 / SRxD1 P10 / D8 P11 / D9 P12 / D10 P13 / D11 P14 / D12 P15 / D13 / INT3 P16 / D14 / INT4 P17 / D15 / INT5 P20 / A0 ( / D0 ) P21 / A1 ( / D1 ) P22 / A2 ( / D2 ) P23 / A3 ( / D3 ) P24 / A4 ( / D4 ) P25 / A5 ( / D5 ) P26 / A6 ( / D6 ) P27 / A7 ( / D7 ) Vss 0 / A8 ( / D8 ) Vcc2 1 / A9 ( / D9 ) P32 / A10 ( / D10 ) P33 / A11 ( / D11 ) P34 / A12 ( / D12 ) P35 / A13 ( / D13 ) P36 / A14 ( / D14 ) P37 / A15 ( / D15 ) P40 / A16 P41 / A17 P42 / A18 P43 / A19 D 7 / P07 D 6 / P06 D 5 / P05 D 4 / P04 D 3 / P03 D 2 / P02 D 1 / P01 D 0 / P00 KI3 / AN7 / P107 KI2 / AN6 / P106 KI1 / AN5 / P105 KI0 / AN4 / P104 AN 3 / P103 AN 2 / P102 AN 1 / P101 AVss AN 0 / P100 VREF AVcc RxD4 / ADTRG / P97 STxD4 / SCL4 / <VCC2 > <VCC1 > NOTE: 1. P7 0 and P71 are ports for the N-channel open drain output. PRQP0100JB-A (100P6S-A)

65fo5002,10.voN01.1.veR 0110-8300B30JER 1. Overview page 6 puorG08/C23M Figure 1.4 Pin Assignment 100 M32C/80 GROUP SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94 SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93 SRxD3 / SDA3 / TxD3 / TB2IN / P92 STxD3 / SCL3 / RxD3 / TB1IN / P91 CLK3 / TB0IN / P90 BYTE CNVss XCIN / P87 XCOUT / P86 RESET XOUT Vss XIN Vcc1 NMI / P85 INT2 / P84 INT1 / P83 INT0 / P82 U / TA4IN / P81 ISRxD0 / U / TA4OUT / P80 ISCLK0 / TA3IN / P77 ISTxD0 / TA3OUT / P76 ISRxD1 / W / TA2IN / P75 ISCLK1 / W / TA2OUT / P74 ISTxD1 / SS2 / RTS2 / CTS2 / V / TA1IN / P73 P42 / A18 P43 / A19 P44 / CS3 / A20 P45 / CS2 / A21 P46 / CS1 / A22 P47 / CS0 / A23 P50 / WRL / WR P51 / WRH / BHE P52 / RD P53 / CLKOUT / BCLK / ALE P54 / HLDA / ALE P55 / HOLD P56 / ALE P57 / RDY P60 / CTS0 / RTS0 / SS0 P61 / CLK0 P62 / RxD0 / SCL0 / STxD0 P63 / TxD0 / SDA0 / SRxD0 P64 / CTS1 / RTS1 / SS1 P65 / CLK1 P66 / RxD1 / SCL1 / STxD1 P67 / TxD1 / SDA1 / SRxD1 P70 / TA0OUT / TxD2 / SDA2 / SRxD2 P71 / TA0IN / TB5IN / RxD2 / SCL2 / STxD2 P72 / TA1OUT / V / CLK2 P13 / D11 P14 / D12 P15 / D13 / INT3 P16 / D14 / INT4 P17 / D15 / INT5 P20 / A0 ( / D0 ) P21 / A1 ( / D1 ) P22 / A2 ( / D2 ) P23 / A3 ( / D3 ) P24 / A4 ( / D4 ) P25 / A5 ( / D5 ) P26 / A6 ( / D6 ) P27 / A7 ( / D7 ) Vss 0 / A8 ( / D8 ) Vcc2 1 / A9 ( / D9 ) P32 / A10 ( / D10 ) P33 / A11 ( / D11 ) P34 / A12 ( / D12 ) P35 / A13 ( / D13 ) P36 / A14 ( / D14 ) P37 / A15 ( / D15 ) P40 / A16 P41 / A17 D 10 / P12 D 9 / P11 D 8 / P10 D 7 / P07 D 6 / P06 D 5 / P05 D 4 / P04 D 3 / P03 D 2 / P02 D 1 / P01 D 0 / P00 KI3 / AN7 / P107 KI2 / AN6 / P106 KI1 / AN5 / P105 KI0 / AN4 / P104 AN 3 / P103 AN 2 / P102 AN 1 / P101 AVss AN 0 / P100 VREF AVcc STxD4 / SCL4 / RxD4 / ADTRG / P97 SRxD4 / SDA4 / TxD4 / ANEX1 / P96 CLK4 / ANEX0 / P95 <VCC2 ><VCC2 > <VCC1 ><VCC1 > NOTE: 1. P7 0 and P71 are ports for the N-channel open drain output. PLQP0100KB-A (100P6Q-A)

65fo5002,10.voN01.1.veR 0110-8300B30JER 1. Overview page 7 puorG08/C23M BYTE CNV SS XCIN XCOUT RESET X OUT VSS XIN VCC1 P96 P95 P94 P93 P92 P91 P90 P87 P86 P85 P84 P83 P82 P81 P80 P77 P76 P75 P74 P73 P72 P71 P70 P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55 P54 P53 P52 P51 P50 P47 P46 P45 P44 NMI INT2 INT1 INT0 TB4 IN TB3 IN TB2 IN TB1 IN TB0 IN TA4IN/U TA4OUT /U TA3IN TA3OUT TA2IN/W TA2OUT /W TA1IN/V TA1OUT /V TB5 IN/TA0IN TA0OUT TxD4/SDA4/SRxD4 CLK4 CTS4/RTS4/SS4 CTS3/RTS3/SS3 TxD3/SDA3/SRxD3 RxD3/SCL3/STxD3 CLK3 CTS2/RTS2/SS2 CLK2 RxD2/SCL2/STxD2 TxD2/SDA2/SRxD2 TxD1/SDA1/SRxD1 RxD1/SCL1/STxD1 CLK1 CTS1/RTS1/SS1 TxD0/SDA0/SRxD0 RxD0/SCL0/STxD0 CLK0 CTS0/RTS0/SS0 ANEX1 ANEX0 DA1 DA0 100 RDY ALE HOLD HLDA/ALE CLK OUT /BCLK/ALE RD WRH/BHE WRL/WR CS0/A CS1/A22 CS2/A21 CS3/A20 Package Pin No FP GP Control pins Port Timer pins UART pins Bus control pins Analog pins Interrupt pins Intelligent I/O pins ISRxD0 ISCLK0 ISTxD0 ISRxD1 ISCLK1 ISTxD1 Table 1.3 Pin Characteristics

65fo5002,10.voN01.1.veR 0110-8300B30JER 1. Overview page 8 puorG08/C23M Table 1.3 Pin Characteristics (Continued) 100 VCC2 VSS AV SS AV CC P43 P42 P41 P40 P37 P36 P35 P34 P33 P32 P31 P30 P27 P26 P25 P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06 P05 P04 P03 P02 P01 P00 P107 P106 P105 P104 P103 P102 P101 P100 P97 AN 7 AN 6 AN 5 AN 4 AN 3 AN 2 AN 1 AN 0 VREF AD TRG A19 A18 A17 A16 A15(/D15) A14(/D14) A13(/D13) A12(/D12) A11(/D11) A10(/D10) A9(/D9) A8(/D8) A7(/D7) A6(/D6) A5(/D5) A4(/D4) A3(/D3) A2(/D2) A1(/D1) A0(/D0) D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 INT5 INT4 INT3 KI KI2 KI1 KI0 RxD4/SCL4/STxD4 FP GP Package pin No Control pins Port Timer pins UART pins Bus control pins Analog pins Interrupt pins Intelligent I/O pins

65fo5002,10.voN01.1.veR 0110-8300B30JER 1. Overview page 9 puorG08/C23M Apply 3.0 to 5.5 V to both VCC1 and VCC2 pins. Apply 0 V to the VSS pin. VCC1 ≥ VCC2 (1) Supplies power for the A/D converter. Connect the AVCC pin to VCC1 and the AVSS pin to VSS The microcomputer is in a reset state when "L" is applied to the RESET pin Connect this pin to VCC1 Switches the data bus in external memory space 3. The data bus is 16 bits long when the this pin is held "L" and 8 bits long when the this pin is held "H". Set it to either one. Inputs and outputs data (D 0 to D7) while accessing an external memory space with separate bus Inputs and outputs data (D 8 to D15) while accessing an external memory space with 16-bit separate bus Outputs address bits (A0 to A22) Outputs inversed address bit A23 Inputs and outputs data (D 0 to D7) and outputs 8 low-order address bits (A0 to A7) by time-sharing while accessing an external memory space with multiplexed bus Inputs and outputs data (D 8 to D15) and outputs 8 middle-order address bits (A8 to A15) by time-sharing while accessing an external memory space with multiplexed bus Output CS0 to CS3 that are chip-select signals specifying an external space Outputs WRL, WRH, (WR, BHE) and RD signals. WRL and WRH can be switched with WR and BHE by program WRL, WRH and RD are selected: If external data bus is 16 bits wide, data is writtenn to an even address when WRL is held "L". Data is written to an odd address when WRH is held "L". Data is read when RD is held "L". WR, BHE and RD are selected Data is written to external memory space when WR is held "L". Data is read when RD is held "L". An odd address is accessed when BHE is held "L". Select WR, BHE and RD for an external 8-bit data bus ALE is a signal latching address The microcomputer is placed in a hold state while the HOLD pin is held "L" Outputs an "L" siganl while the microcomputer is placed in a hold state Bus is placed in a wait state while the RDY pin is held "L" VCC1, VCC2 VSS AV CC AV SS RESET CNV SS BYTE D 0 to D7 D 8 to D15 A0 to A22 A23 A0/D0 to A7/D7 A8/D8 to A15/D15 CS0 to CS3 WRL/WR WRH/BHE RD ALE HOLD HLDA RDY Power supply Analog power supply input Reset input CNV SS External data bus width select input Bus control pins I I I I I I/O I/O O O I/O I/O O O O I O I VCC1 VCC1 VCC1 VCC1 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 Supply Signal name Pin name I/O type Descriptionvoltage

1.6 Pin Description

Table 1.4 Pin Description I: Input O: Output I/O: Input and output NOTE: 1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.

65fo5002,10.voN01.1.veR 0110-8300B30JER 1. Overview page 10 puorG08/C23M XIN XOUT XCIN XCOUT BCLK CLK OUT INT0 to INT2 INT3 to INT5 NMI KI0 to KI3 TA0 OUT to TA4 OUT TA0 IN to TA4 IN TB0 IN to TB5 IN __ __ U, U, V, V, W, W CTS0 to CTS4 RTS0 to RTS4 CLK0 to CLK4 RxD0 to RxD4 TxD0 to TxD4 SDA0 to SDA4 SCL0 to SCL4 STxD0 to STxD4 SRxD0 to SRxD4 SS0 to SS4 Main clock input Main clock output Sub clock input Sub clock output BCLK output Clock output INT interrupt input NMI interrupt input Key input interrupt Timer A Timer B Three-phase motor control output Serial I/O I2C mode Serial I/O special function VCC1 VCC1 VCC1 VCC1 VCC2 VCC2 VCC1 VCC2 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 I O I O O O I I I I/O I I O I O I/O I O I/O I/O I I I I/O pins for the main clock generation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT . To apply external clock, input the clock from XIN and leave XOUT open I/O pins for a sub clock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT. To apply external clock, input the clock from XCIN and leave XCOUT open Outputs BCLK signal Outputs clock having thesame frequency as fC , f8, or f32 Input pins for the INT interrupt Input pin for the NMI interrupt Input pins for the key input interrupt I/O pins for the timer A0 to A4 (TA0OUT is a pin for the N-channel open drain output.) Input pins for the timer A0 to A4 Input pins for the timer B0 to B5 output pins for the three-phase motor control timer Input pins for data transmission control Output pins for data reception control Inputs and outputs the transfer clock Inputs serial data Outputs serial data (TxD2 is a pin for the N-channel open drain output.) Inputs and outputs serial data (SDA2 is a pin for for the N- channel open drain output.) Inputs and outputs the transfer clock (SCL2 is a pin for the N- channel open drain output.) Outputs serial data when slave mode is selected (SDA2 is a pin for the N-channel open drain output.) Inputs serial data when slave mode is selected Input pins to control serial I/O special function Supply Signal name Pin name I/O type Descriptionvoltage Table 1.4 Pin Description (Continued) I: Input O: Output I/O: Input and output

65fo5002,10.voN01.1.veR 0110-8300B30JER 1. Overview page 11 puorG08/C23M VREF AN 0 to AN7 AD TRG ANEX0 ANEX1 DA0, DA1 ISCLK0 ISCLK1 ISTxD0 ISTxD1 ISRxD0 ISRxD1 P00 to P07(1) P10 to P17(2) P20 to P27(1) P30 to P37(1) P40 to P47(1) P50 to P57(1) P60 to P67 P70 to P77 P90 to P97 P100 to P107 P80 to P84, P86, P87 P85 Reference voltage input A/D converter D/A converter Intelligent I/O communication function I/O port VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC2 VCC1 VCC1 VCC1 Applies reference voltage for the A/D converter and D/A converter Analog input pins for the A/D converter Input pin for an external A/D trigger Extended analog input pin for the A/D converter and output pin in external op-amp connection mode Extended analog input pin for the A/D converter Output pin for the D/A converter Inputs and outputs clock for the intelligent I/O communication fucntion Outputs data for the intelligent I/O communication fucntion Inputs data for the intelligent I/O communication fucntion I/O ports fro CMOS. Each port can be programmed for nput or output under the control of the direction register. An input port can be set, by program, for a pull-up resistor available or for no pull-up resistor available in 4-bit units I/O ports having equivalent functions to P0 (P7 0 and P71 are ports for the N-channel open drain output.) I/O ports having equivalent functions to P0 Shares a pin with NMI. NMI input state can be got by reading P85 I I I I/O I O I/O O I I/O I/O I/O I Supply Signal name Pin name I/O type Descriptionvoltage Table 1.5 Pin Description (Continued) I: Input O: Output I/O: Input and output NOTES: 1. Ports P0 to P5 function as bus control pins when using memory expansion mode or microprocessor mode. They cannot be used as I/O ports. 2. Port P1 functions as I/O port when the microcomputer is placed in memory expansion mode or microprocessor mode and all external data buses are selected as 8-bit buses.

Page 13 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M 2. Central Processing Unit (CPU)

2.1 General Registers

2.1.1 Data Registers (R0, R1, R2 and R3)

R0, R1, R2 and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R0 can be combined with R2 to be used as a 32-bit data register (R2R0). The same applies to R1 and R3.

2.1.2 Address Registers (A0 and A1)

A0 and A1 are 24-bit registers for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer, arith- metic and logic operations.

2.1.3 Static Base Register (SB)

SB is a 24-bit register for SB-relative addressing.

2.1.4 Frame Base Register (FB)

FB is a 24-bit register for FB-relative addressing.

2.1.5 Program Counter (PC)

PC, 24 bits wide, indicates the address of an instruction to be executed.

2.1.6 Interrupt Table Register (INTB)

INTB is a 24-bit register indicating the starting address of an relocatable interrupt vector table.

2.1.7 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)

The stack pointers (SP), USP and ISP, are 24 bits wide each. The U flag is used to switch between USP and ISP. Refer to 2.1.8 Flag Register (FLG) for details on the U flag. Set USP and ISP to even addresses to execute an interrupt sequence efficiently.

2.1.8 Flag Register (FLG)

FLG is a 16-bit register indicating a CPU state.

2.1.8.1 Carry Flag (C)

The C flag indicates whether carry or borrow has occurred after executing an instruction.

2.1.8.2 Debug Flag (D)

The D flag is for debug only. Set to "0".

2.1.8.3 Zero Flag (Z)

The Z flag is set to "1" when the value of zero is obtained from an arithmetic operation; otherwise "0".

2.1.8.4 Sign Flag (S)

The S flag is set to "1" when a negative value is obtained from an arithmetic operation; otherwise "0".

Page 14 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M 2. Central Processing Unit (CPU)

2.1.8.5 Register Bank Select Flag (B)

The register bank 0 is selected when the B flag is set to "0". The register bank 1 is selected when this flag is set to "1".

2.1.8.6 Overflow Flag (O)

The O flag is set to "1" when the result of an arithmetic operation overflows; otherwise "0".

2.1.8.7 Interrupt Enable Flag (I)

The I flag enables a maskable interrupt. Interrupt is disabled when the I flag is set to "0" and enabled when the I flag is set to "1". The I flag is set to "0" when an interrupt is acknowledged.

2.1.8.8 Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to "0". USP is selected when this flag is set to "1". The U flag is set to "0" when a hardware interrupt is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed.

2.1.8.9 Processor Interrupt Priority Level (IPL)

IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has greater priority than IPL, the interrupt is enabled.

2.1.8.10 Reserved Space

When writing to a reserved space, set to "0". When reading, its content is indeterminate.

2.2 High-Speed Interrupt Registers

Registers associated with the high-speed interrupt are as follows: - Flag save register (SVF) - PC save register (SVP) - Vector register (VCT)

2.3 DMAC-Associated Registers

Registers associated with DMAC are as follows: - DMA mode register (DMD0, DMD1) - DMA transfer count register (DCT0, DCT1) - DMA transfer count reload register (DRC0, DRC1) - DMA memory address register (DMA0, DMA1) - DMA SFR address register (DSA0, DSA1) - DMA memory address reload register (DRA0, DRA1)

1. Special Function Registers (SFRs) 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M Address Register Symbol Value after RESET 000016 000116 000216 000316

000416 Processor Mode Register(1) PM0 0000 00112(CNVss pin ="H")

000516 Processor Mode Register 1 PM1 00 16

000616 System Clock Control Register 0 CM0 0000 1000 2

000716 System Clock Control Register 1 CM1 0010 0000 2

000916 Address Match Interrupt Enable Register AIER 00 16

000A 16 Protect Register PRCR XXXX 0000 2 XXXX 10002(BYTE pin ="L") 000B 16 External Data Bus Width Control Register DS XXXX 00002(BYTE pin ="H") 000C 16 Main Clock Division Register MCD XXX0 1000 2 000D 16 Oscillation Stop Detection Register CM2 00 16 000E 16 Watchdog Timer Start Register WDTS XX 16 000F16 Watchdog Timer Control Register WDC 000X XXXX 2 001016

001116 Address Match Interrupt Register 0 RMAD0 000000 16

001316 Processor Mode Register 2 PM2 00 16

001516 Address Match Interrupt Register 1 RMAD1 000000 16

001916 Address Match Interrupt Register 2 RMAD2 000000 16

001D 16 Address Match Interrupt Register 3 RMAD3 000000 16 001E 16 001F16 002016 002116 002216 002316 002416 002516

002616 PLL Control Register 0 PLC0 0001 X010 2

002716 PLL Control Register 1 PLC1 000X 0000 2

002916 Address Match Interrupt Register 4 RMAD4 000000 16

002D 16 Address Match Interrupt Register 5 RMAD5 000000 16 002E 16 002F16 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTE: 1. The PM01 and PM00 bits in the PM0 register maintain values set before reset, even after software reset or watch- dog timer reset has been performed. 4. Special Function Registers (SFRs)

1. Special Function Registers (SFRs) 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M Address Register Symbol Value after RESET 003016 003116 003216 003316 003416 003516 003616 003716 003816

003916 Address Match Interrupt Register 6 RMAD6 00000016

003D 16 Address Match Interrupt Register 7 RMAD7 00000016 003E 16 003F16 004016 004116 004216 004316 004416 004516 004616 004716

004816 External Space Wait Control Register 0 EWCR0 X0X0 00112

004916 External Space Wait Control Register 1 EWCR1 X0X0 00112

004A 16 External Space Wait Control Register 2 EWCR2 X0X0 00112 004B 16 External Space Wait Control Register 3 EWCR3 X0X0 00112 004C 16 004D 16 004E 16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A 16 005B 16 005C 16 005D 16 005E 16 005F16 X: Indeterminate Blank spaces are reserved. No access is allowed.

1. Special Function Registers (SFRs) 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M Address Register Symbol Value after RESET 006016 006116 006216 006316 006416 006516 006616 006716

006816 DMA0 Interrupt Control Register DM0IC XXXX X000 2

006916 Timer B5 Interrupt Control Register TB5IC XXXX X000 2

006A 16 DMA2 Interrupt Control Register DM2IC XXXX X000 2 006B 16 UART2 Receive /ACK Interrupt Control Register S2RIC XXXX X000 2 006C 16 Timer A0 Interrupt Control Register TA0IC XXXX X000 2 006D 16 UART3 Receive /ACK Interrupt Control Register S3RIC XXXX X000 2 006E 16 Timer A2 Interrupt Control Register TA2IC XXXX X000 2 006F16 UART4 Receive /ACK Interrupt Control Register S4RIC XXXX X000 2

007016 Timer A4 Interrupt Control Register TA4IC XXXX X000 2

007116 UART0/UART3 Bus Conflict Detect Interrupt Control Register BCN0IC/BCN3IC XXXX X000 2

007216 UART0 Receive/ACK Interrupt Control Register S0RIC XXXX X000 2

007316 A/D0 Conversion Interrupt Control Register AD0IC XXXX X000 2

007416 UART1 Receive/ACK Interrupt Control Register S1RIC XXXX X000 2

007516 Intelligent I/O Interrupt Control Register 0 IIO0IC XXXX X000 2

007616 Timer B1 Interrupt Control Register TB1IC XXXX X000 2

007716 Intelligent I/O Interrupt Control Register 2 IIO2IC XXXX X000 2

007816 Timer B3 Interrupt Control Register TB3IC XXXX X000 2

007916 Intelligent I/O Interrupt Control Register 4 IIO4IC XXXX X000 2

007A 16 INT5 Interrupt Control Register INT5IC XX00 X000 2 007B 16 007C 16 INT3 Interrupt Control Register INT3IC XX00 X000 2 007D 16 007E 16 INT1 Interrupt Control Register INT1IC XX00 X000 2 007F16 008016 008116 008216 008316 008416 008516 008616 008716

008816 DMA1 Interrupt Control Register DM1IC XXXX X000 2

008916 UART2 Transmit /NACK Interrupt Control Register S2TIC XXXX X000 2

008A 16 DMA3 Interrupt Control Register DM3IC XXXX X000 2 008B 16 UART3 Transmit /NACK Interrupt Control Register S3TIC XXXX X000 2 008C 16 Timer A1 Interrupt Control Register TA1IC XXXX X000 2 008D 16 UART4 Transmit /NACK Interrupt Control Register S4TIC XXXX X000 2 008E 16 Timer A3 Interrupt Control Register TA3IC XXXX X000 2 008F16 UART2 Bus Conflict Detect Interrupt Control Register BCN2IC XXXX X000 2 X: Indeterminate Blank spaces are reserved. No access is allowed.

1. Special Function Registers (SFRs) 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M Address Register Symbol Value after RESET

009016 UART0 Transmit /NACK Interrupt Control Register S0TIC XXXX X000 2

009116 UART1/UART4 Bus Conflict Detect Interrupt Control Register BCN1IC/BCN4IC XXXX X000 2

009216 UART1 Transmit/NACK Interrupt Control Register S1TIC XXXX X000 2

009316 Key Input Interrupt Control Register KUPIC XXXX X000 2

009416 Timer B0 Interrupt Control Register TB0IC XXXX X000 2

009516 Intelligent I/O Interrupt Control Register 1 IIO1IC XXXX X000 2

009616 Timer B2 Interrupt Control Register TB2IC XXXX X000 2

009716 Intelligent I/O Interrupt Control Register 3 IIO3IC XXXX X000 2

009816 Timer B4 Interrupt Control Register TB4IC XXXX X000 2

009A 16 INT4 Interrupt Control Register INT4IC XX00 X000 2 009B 16 009C 16 INT2 Interrupt Control Register INT2IC XX00 X000 2 009D 16 009E 16 INT0 Interrupt Control Register INT0IC XX00 X000 2 009F16 Exit Priority Control Register RLVL XXXX 0000 2 00A0 16 Interrupt Request Register 0 IIO0IR 0000 000X 2 00A1 16 Interrupt Request Register 1 IIO1IR 0000 000X 2 00A2 16 Interrupt Request Register 2 IIO2IR 0000 000X 2 00A3 16 Interrupt Request Register 3 IIO3IR 0000 000X 2 00A4 16 Interrupt Request Register 4 IIO4IR 0000 000X 2 00A5 16 00A6 16 00A7 16 00A8 16 00A9 16 00AA 16 00AB 16 00AC 16 00AD 16 00AE 16 00AF 16 00B0 16 Interrupt Enable Register 0 IIO0IE 00 16 00B1 16 Interrupt Enable Register 1 IIO1IE 00 16 00B2 16 Interrupt Enable Register 2 IIO2IE 00 16 00B3 16 Interrupt Enable Register 3 IIO3IE 00 16 00B4 16 Interrupt Enable Register 4 IIO4IE 00 16 00B5 16 00B6 16 00B7 16 00B8 16 00B9 16 00BA 16 00BB 16 00BC 16 00BD 16 00BE 16 00BF 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

1. Special Function Registers (SFRs) 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M Address Register Symbol Value after RESET 00C0 16 00C1 16 00C2 16 00C3 16 00C4 16 00C5 16 00C6 16 00C7 16 00C8 16 00C9 16 00CA 16 00CB 16 00CC 16 00CD 16 00CE 16 00CF 16 00D0 16 00D1 16 00D2 16 00D3 16 00D4 16 00D5 16 00D6 16 00D7 16 00D8 16 00D9 16 00DA 16 00DB 16 00DC 16 00DD 16 00DE 16 00DF 16 00E0 16 00E1 16 00E2 16 00E3 16 00E4 16 00E5 16 00E6 16 00E7 16 00E8 16 XXXX XXXX 2 SI/O Receive Buffer Register 0 G0RB00E9 16 XXX0 XXXX 2 00EA 16 Transmit Buffer/Receive Data Register 0 G0TB/G0DR XX 16 00EB 16 00EC 16 Receive Input Register 0 G0RI XX 16 00ED 16 SI/O Communication Mode Register 0 G0MR 00 16 00EE 16 Transmit Output Register 0 G0TO XX 16 00EF 16 SI/O Communication Control Register 0 G0CR 0000 X011 2 X: Indeterminate Blank spaces are reserved. No access is allowed.

1. Special Function Registers (SFRs) 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M Address Register Symbol Value after RESET 00F016 Data Compare Register 00 G0CMP0 XX 16 00F116 Data Compare Register 01 G0CMP1 XX 16 00F216 Data Compare Register 02 G0CMP2 XX 16 00F316 Data Compare Register 03 G0CMP3 XX 16 00F416 Data Mask Register 00 G0MSK0 XX 16 00F516 Data Mask Register 01 G0MSK1 XX 16 00F616 Communication Clock Select Register CCS XXXX 0000 2 00F716 00F816 XX 16 Receive CRC Code Register 0 G0RCRC00F916 XX 16 00FA 16 0016 Transmit CRC Code Register 0 G0TCRC00FB 16 0016 00FC 16 SI/O Expansion Mode Register 0 G0EMR 00 16 00FD 16 SI/O Expansion Receive Control Register 0 G0ERC 00 16 00FE 16 SI/O Special Communication Interrupt Detect Register 0 G0IRF 00 16 00FF 16 SI/O Expansion Transmit Control Register 0 G0ETC 0000 0XXX 2 010016 010116 010216 010316 010416 010516 010616 010716 010816 010916 010A 16 010B 16 010C 16 010D 16 010E 16 010F16 011016 011116 011216 011316 011416 011516 011616 011716 011816 011916 011A 16 011B 16 011C 16 011D 16 011E 16 011F16 X: Indeterminate Blank spaces are reserved. No access is allowed.

1. Special Function Registers (SFRs) 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M Address Register Symbol Value after RESET 012016 012116 012216 012316 012416 012516 012616 012716

012816 XXXX XXXX 2

SI/O Receive Buffer Register 1 G1RB012916 XXX0 XXXX 2 012A 16 Transmit Buffer/Receive Data Register 1 G1TB/G1DR XX 16 012B 16 012C 16 Receive Input Register 1 G1RI XX 16 012D 16 SI/O Communication Mode Register 1 G1MR 00 16 012E 16 Transmit Output Register 1 G1TO XX 16 012F16 SI/O Communication Control Register 1 G1CR 0000 X011 2

013016 Data Compare Register 10 G1CMP0 XX 16

013116 Data Compare Register 11 G1CMP1 XX 16

013216 Data Compare Register 12 G1CMP2 XX 16

013316 Data Compare Register 13 G1CMP3 XX 16

013416 Data Mask Register 10 G1MSK0 XX 16

013516 Data Mask Register 11 G1MSK1 XX 16

013816 XX 16

Receive CRC Code Register 1 G1RCRC013916 XX 16 013A 16 0016 Transmit CRC Code Register 1 G1TCRC013B 16 0016 013C 16 SI/O Expansion Mode Register 1 G1EMR 00 16 013D 16 SI/O Expansion Receive Control Register 1 G1ERC 00 16 013E 16 SI/O Special Communication Interrupt Detection Register 1 G1IRF 00 16 013F16 SI/O Expansion Transmit Control Register 1 G1ETC 0000 0XXX 2 014016 014116 014216 014316 014416 014516 014616 014716 014816 014916 014A 16 014B 16 014C 16 014D 16 to 02AF 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

1. Special Function Registers (SFRs) 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M Address Register Symbol Value after RESET 02B1 16 02B2 16 02B3 16 02B4 16 02B5 16 02B6 16 02B7 16 02B8 16 02B9 16 02BA 16 02BB 16 02BC 16 02BD 16 02BE 16 02BF 16 02C0 16 XX 16 X0 Register Y0 Register X0R,Y0R02C1 16 XX 16 02C2 16 XX 16 X1 Register Y1 Register X1R,Y1R02C3 16 XX 16 02C4 16 XX 16 X2 Register Y2 Register X2R,Y2R02C5 16 XX 16 02C6 16 XX 16 X3 Register Y3 Register X3R,Y3R02C7 16 XX 16 02C8 16 XX 16 X4 Register Y4 Register X4R,Y4R02C9 16 XX 16 02CA 16 XX 16 X5 Register Y5 Register X5R,Y5R02CB 16 XX 16 02CC 16 XX 16 X6 Register Y6 Register X6R,Y6R02CD 16 XX 16 02CE 16 XX 16 X7 Register Y7 Register X7R,Y7R02CF 16 XX 16 02D0 16 XX 16 X8 Register Y8 Register X8R,Y8R02D1 16 XX 16 02D2 16 XX 16 X9 Register Y9 Register X9R,Y9R02D3 16 XX 16 02D4 16 XX 16 X10 Register Y10 Register X10R,Y10R02D5 16 XX 16 02D6 16 XX 16 X11 Register Y11 Register X11R,Y11R02D7 16 XX 16 02D8 16 XX 16 X12 Register Y12 Register X12R,Y12R02D9 16 XX 16 02DA 16 XX 16 X13 Register Y13 Register X13R,Y13R02DB 16 XX 16 02DC 16 XX 16 X14 Register Y14 Register X14R,Y14R02DD 16 XX 16 02DE 16 XX 16 X15 Register Y15 Register X15R,Y15R02DF 16 XX 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

1. Special Function Registers (SFRs) 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M Address Register Symbol Value after RESET 02E0 16 X/Y Control Register XYC XXXX XX00 2 02E1 16 02E2 16 02E3 16 02E4 16 UART1 Special Mode Register 4 U1SMR4 00 16 02E5 16 UART1 Special Mode Register 3 U1SMR3 00 16 02E6 16 UART1 Special Mode Register 2 U1SMR2 00 16 02E7 16 UART1 Special Mode Register U1SMR 00 16 02E8 16 UART1 Transmit/Receive Mode Register U1MR 00 16 02E9 16 UART1 Bit Rate Register U1BRG XX 16 02EA 16 XX 16 UART1 Transmit Buffer Register U1TB02EB 16 XX 16 02EC 16 UART1 Transmit/Receive Control Register 0 U1C0 0000 1000 2 02ED 16 UART1 Transmit/Receive Control Register 1 U1C1 0000 0010 2 02EE 16 XX 16 UART1 Receive Buffer Register U1RB02EF 16 XX 16 02F016 02F116 02F216 02F316 02F416 UART4 Special Mode Register 4 U4SMR4 00 16 02F516 UART4 Special Mode Register 3 U4SMR3 00 16 02F616 UART4 Special Mode Register 2 U4SMR2 00 16 02F716 UART4 Special Mode Register U4SMR 00 16 02F816 UART4 Transmit/Receive Mode Register U4MR 00 16 02F916 UART4 Bit Rate Register U4BRG XX 16 02FA 16 XX 16 UART4 Transmit Buffer Register U4TB02FB 16 XX 16 02FC 16 UART4 Transmit/Receive Control Register 0 U4C0 0000 1000 2 02FD 16 UART4 Transmit/Receive Control Register 1 U4C1 0000 0010 2 02FE 16 XX 16 UART4 Receive Buffer Register U4RB02FF 16 XX 16

030016 Timer B3, B4, B5 Count Start Flag TBSR 000X XXXX 2

030216 XX 16

Timer A1-1 Register TA11030316 XX 16

030416 XX 16

Timer A2-1 Register TA21030516 XX 16

030616 XX 16

Timer A4-1 Register TA41030716 XX 16

030816 Three-Phase PWM Control Register 0 INVC0 00 16

030916 Three-Phase PWM Control Register 1 INVC1 00 16

030A 16 Three-Phase Output Buffer Register 0 IDB0 XX11 1111 2 030B 16 Three-Phase Output Buffer Register 1 IDB1 XX11 1111 2 030C 16 Dead Time Timer DTT XX 16 030D 16 Timer B2 Interrupt Generation Frequency Set Counter ICTB2 XX 16 030E 16 030F16 X: Indeterminate Blank spaces are reserved. No access is allowed.

1. Special Function Registers (SFRs) 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M Address Register Symbol Value after RESET

031016 XX 16

Timer B3 Register TB3031116 XX 16

031216 XX 16

Timer B4 Register TB4031316 XX 16

031416 XX 16

Timer B5 Register TB5031516 XX 16 031616 031716 031816 031916 031A 16 031B 16 Timer B3 Mode Register TB3MR 00XX 0000 2 031C 16 Timer B4 Mode Register TB4MR 00XX 0000 2 031D 16 Timer B5 Mode Register TB5MR 00XX 0000 2 031E 16 031F16 External Interrupt Request Source Select Register IFSR 00 16 032016 032116 032216 032316

032416 UART3 Special Mode Register 4 U3SMR4 00 16

032516 UART3 Special Mode Register 3 U3SMR3 00 16

032616 UART3 Special Mode Register 2 U3SMR2 00 16

032716 UART3 Special Mode Register U3SMR 00 16

032816 UART3 Transmit/Receive Mode Register U3MR 00 16

032916 UART3 Bit Rate Register U3BRG XX 16

UART3 Transmit Buffer Register U3TB032B 16 XX 16 032C 16 UART3 Transmit/Receive Control Register 0 U3C0 0000 1000 2 032D 16 UART3 Transmit/Receive Control Register 1 U3C1 0000 0010 2 032E 16 XX 16 UART3 Receive Buffer Register U3RB032F16 XX 16 033016 033116 033216 033316

033416 UART2 Special Mode Register 4 U2SMR4 00 16

033516 UART2 Special Mode Register 3 U2SMR3 00 16

033616 UART2 Special Mode Register 2 U2SMR2 00 16

033716 UART2 Special Mode Register U2SMR 00 16

033816 UART2 Transmit/Receive Mode Register U2MR 00 16

033916 UART2 Bit Rate Register U2BRG XX 16

UART2 Transmit Buffer Register U2TB033B 16 XX 16 033C 16 UART2 Transmit/Receive Control Register 0 U2C0 0000 1000 2 033D 16 UART2 Transmit/Receive Control Register 1 U2C1 0000 0010 2 033E 16 XX 16 UART2 Receive Buffer Register U2RB033F16 XX 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

1. Special Function Registers (SFRs) 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M X: Indeterminate Blank spaces are reserved. No access is allowed. NOTE: 1. The TCSPR register maintains values set before reset, even after software reset or watchdog timer reset has been performed. Address Register Symbol Value after RESET

034016 Count Start Flag TABSR 00 16

034116 Clock Prescaler Reset Flag CPSRF 0XXX XXXX 2

034216 One-Shot Start Flag ONSF 00 16

034316 Trigger Select Register TRGSR 00 16

034416 Up/Down Flag UDF 00 16

034616 XX 16

Timer A0 Register TA0034716 XX 16

034816 XX 16

Timer A1 Register TA1034916 XX 16 034A 16 XX 16 Timer A2 Register TA2034B 16 XX 16 034C 16 XX 16 Timer A3 Register TA3034D 16 XX 16 034E 16 XX 16 Timer A4 Register TA4034F16 XX 16

035016 XX 16

Timer B0 Register TB0035116 XX 16

035216 XX 16

Timer B1 Register TB1035316 XX 16

035416 XX 16

Timer B2 Register TB2035516 XX 16

035616 Timer A0 Mode Register TA0MR 00 16

035716 Timer A1 Mode Register TA1MR 00 16

035816 Timer A2 Mode Register TA2MR 00 16

035916 Timer A3 Mode Register TA3MR 00 16

035A 16 Timer A4 Mode Register TA4MR 00 16 035B 16 Timer B0 Mode Register TB0MR 00XX 0000 2 035C 16 Timer B1 Mode Register TB1MR 00XX 0000 2 035D 16 Timer B2 Mode Register TB2MR 00XX 0000 2 035E 16 Timer B2 Special Mode Register TB2SC XXXX XXX0 2 035F16 Count Source Prescaler Register(1) TCSPR 0XXX 0000 2 036016 036116 036216 036316

036416 UART0 Special Mode Register 4 U0SMR4 00 16

036516 UART0 Special Mode Register 3 U0SMR3 00 16

036616 UART0 Special Mode Register 2 U0SMR2 00 16

036716 UART0 Special Mode Register U0SMR 00 16

036816 UART0 Transmit/Receive Mode Register U0MR 00 16

036916 UART0 Bit Rate Register U0BRG XX 16

UART0 Transmit Buffer Register U0TB036B 16 XX 16 036C 16 UART0 Transmit/Receive Control Register 0 U0C0 0000 1000 2 036D 16 UART0 Transmit/Receive Control Register 1 U0C1 0000 0010 2 036E 16 XX 16 UART0 Receive Buffer Register U0RB036F16 XX 16

1. Special Function Registers (SFRs) 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M Address Register Symbol Value after RESET 037016 037116 037216 037316 037416 037516 037616 037716

037816 DMA0 Request Source Select Register DM0SL 0X00 0000 2

037916 DMA1 Request Source Select Register DM1SL 0X00 0000 2

037A 16 DMA2 Request Source Select Register DM2SL 0X00 0000 2 037B 16 DMA3 Request Source Select Register DM3SL 0X00 0000 2 037C 16 XX 16 CRC Data Register CRCD037D 16 XX 16 037E 16 CRC Input Register CRCIN XX 16 037F16

038016 XXXX XXXX 2

A/D0 Register 0 AD00038116 0000 00002

038216 XX 16

A/D0 Register 1 AD01038316 XX 16

038416 XX 16

A/D0 Register 2 AD02038516 XX 16

038616 XX 16

A/D0 Register 3 AD03038716 XX 16

038816 XX 16

A/D0 Register 4 AD04038916 XX 16 038A 16 XX 16 A/D0 Register 5 AD05038B 16 XX 16 038C 16 XX 16 A/D0 Register 6 AD06038D 16 XX 16 038E 16 XX 16 A/D0 Register 7 AD07038F16 XX 16 039016 039116 039216 039316

039416 A/D0 Control Register 2 AD0CON2 XX0X XXX0 2

039516 A/D0 Control Register 3 AD0CON3 XXXX X000 2

039616 A/D0 Control Register 0 AD0CON0 00 16

039716 A/D0 Control Register 1 AD0CON1 00 16

039816 D/A Register 0 DA0 XX 16

039A 16 D/A Register 1 DA1 XX 16 039B 16 039C 16 D/A Control Register DACON XXXX XX00 2 039D 16 039E 16 039F16 X: Indeterminate Blank spaces are reserved. No access is allowed.

1. Special Function Registers (SFRs) 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M Address Register Symbol Value after RESET 03A0 16 03A1 16 03A2 16 03A3 16 03A4 16 03A5 16 03A6 16 03A7 16 Function Select Register D1 PSD1 X0XX XX00 2 03A8 16 03A9 16 03AA 16 03AB 16 03AC 16 03AD 16 Function Select Register C3 PSC3 X0XX XXXX 2 03AE 16 03AF 16 Function Select Register C PSC 00X0 0000 2 03B0 16 Function Select Register A0 PS0 00 16 03B1 16 Function Select Register A1 PS1 00 16 03B2 16 Function Select Register B0 PSL0 00 16 03B3 16 Function Select Register B1 PSL1 00 16 03B4 16 Function Select Register A2 PS2 00X0 0000 2 03B5 16 Function Select Register A3 PS3 00 16 03B6 16 Function Select Register B2 PSL2 00X0 0000 2 03B7 16 Function Select Register B3 PSL3 00 16 03B8 16 03B9 16 03BA 16 03BB 16 03BC 16 03BD 16 03BE 16 03BF 16 03C0 16 Port P6 Register P6 XX 16 03C1 16 Port P7 Register P7 XX 16 03C2 16 Port P6 Direction Register PD6 00 16 03C3 16 Port P7 Direction Register PD7 00 16 03C4 16 Port P8 Register P8 XX 16 03C5 16 Port P9 Register P9 XX 16 03C6 16 Port P8 Direction Register PD8 00X0 0000 2 03C7 16 Port P9 Direction Register PD9 00 16 03C8 16 Port P10 Register P10 XX 16 03C9 16 03CA 16 Port P10 Direction Register PD10 00 16 03CB 16 03CC 16 03CD 16 03CE 16 03CF 16 X: Indeterminate Blank spaces are reserved. No access is allowed.

1. Special Function Registers (SFRs) 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M Address Register Symbol Value after RESET 03D0 16 03D1 16 03D2 16 03D3 16 03D4 16 03D5 16 03D6 16 03D7 16 03D8 16 03D9 16 03DA 16 Pull-Up Control Register 2 PUR2 00 16 03DB 16 Pull-Up Control Register 3 PUR3 00 16 03DC 16 03DD 16 03DE 16 03DF 16 03E0 16 Port P0 Register(1) P0 XX 16 03E1 16 Port P1 Register(1) P1 XX 16 03E2 16 Port P0 Direction Register(1) PD0 00 16 03E3 16 Port P1 Direction Register(1) PD1 00 16 03E4 16 Port P2 Register(1) P2 XX 16 03E5 16 Port P3 Register(1) P3 XX 16 03E6 16 Port P2 Direction Register(1) PD2 00 16 03E7 16 Port P3 Direction Register(1) PD3 00 16 03E8 16 Port P4 Register(1) P4 XX 16 03E9 16 Port P5 Register(1) P5 XX 16 03EA 16 Port P4 Direction Register(1) PD4 00 16 03EB 16 Port P5 Direction Register(1) PD5 00 16 03EC 16 03ED 16 03EE 16 03EF 16 03F016 Pull-up Control Register 0 PUR0 00 16 03F116 Pull-up Control Register 1 PUR1 XXXX 0000 2 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA 16 03FB 16 03FC 16 03FD 16 03FE 16 03FF 16 Port Control Register PCR XXXX XXX0 2 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTE: 1. Pins, functioning as bus control pins, cannot be selected as I/O ports.

Page 30 65fo5002,10.voN01.1.veR 0110-8300B30JER 5. Electrical CharacteristicspuorG08/C23M 5. Electrical Characteristics Table 5.1 Absolute Maximum Ratings lobmySr etemaraPn oitidnoCe ulaVt inU V 1CC V, 2CC egatloVylppuSV 1CC VA= CC 0.6ot3.0- V V 2CC egatloVylppuS- V ot3.0- 1CC V VA CC egatloVylppuSgolanAV 1CC VA= CC 0.6ot3.0- V VI egatloVtupnIV NC,TESER SS 6P,ETYB, 0 6P- 7 7P, 2 7P- 7, 8P 0 8P- 7 9P, 0 9P- 7 01P, 0 01P- 7 V, FER X, NI Vot3.0- 1CC 3.0+V 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7, 4P 0 4P- 7 5P, 0 5P- 7 Vot3.0- 2CC 3.0+ 7P 0 7P, 1 0.6ot3.0- VO egatloVtuptuO6 P 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7, 9P 0 9P- 7 01P, 0 01P- 7 X, TUO Vot3.0- 1CC 3.0+V 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7, 4P 0 4P- 7 5P, 0 5P- 7 Vot3.0- 2CC 3.0+ 7P 0 7P, 1 0.6ot3.0- dPn oitapissiDrewoP C°52=rpoT0 05W m rpoTe rutarepmeTtneibmAgnitarepO /58ot02- 58ot04- )1( gtsTe rutarepmeTegarotS 051ot56-C ° :ETON 58ot04-foegnarerutarepmetfieciffoselasruotcatnoC.1 .deriuqersiC°

Page 31 65fo5002,10.voN01.1.veR 0110-8300B30JER 5. Electrical CharacteristicspuorG08/C23M Table 5.2 Recommended Operating Conditions (VCC1 = VCC2 =3.0V to 5.5V at Topr=– 20 to 85oC unless otherwise specified) lobmySr etemaraP dradnatS tinU.niM. pyT. xaM V 1CC V, 2CC V(egatloVylppuS 1CC V 2CC )0 .30 .55 .5V VA CC egatloVylppuSgolanA V 1CC V V SS egatloVylppuS 0V VA SS egatloVylppuSgolanA 0V V HI )"H"(hgiHtupnI egatloV 2P 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 V8.0 2CC V 2CC V 6P 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 7 )3( 9P, 0 9P- 7 01P, 0 01P- 7 X, NI , VNC,TESER SS ETYB, V8.0 1CC V 1CC 7P 0 7P, 1 V8.0 1CC 0.6 0P 0 0P- 7 1P, 0 1P- 7 )edompihc-elgnisni(V 8.0 2CC V 2CC 0P 0 0P- 7 1P, 0 1P- 7 )edomrosecorporcimdnaedomnoisnapxeyromemni( V5.0 2CC V 2CC V LI )"L"(woLtupnI egatloV P20 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7 0V 2.0 2CC V 6P 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7 )3( 9P, 0 9P- 7 01P, 0 01P- 7 X, NI , VNC,TESER SS ETYB, 0V 2.0 1CC 0P 0 0P- 7 1P, 0 1P- 7 )edompihc-elgnisni(0 V 2.0 2CC 0P 0 0P- 7 1P, 0 1P- 7 )edomrosecorporcimdnaedomnoisnapxeyromemni( 0V 61.0 2CC I )kaep(HO hgiHtuptuOkaeP tnerruC)"H"( )2( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7, 6P 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7, 01P 0 01P- 7 0.01-A m I )gva(HO tuptuOegarevA tnerruC)"H"(hgiH )1( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7, 6P 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7, 01P 0 01P- 7 0.5-A m I )kaep(LO woLtuptuOkaeP tnerruC)"L"( )2( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7, 6P 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7, 01P 0 01P- 7 0.01A m I )gva(LO woLtuptuOegarevA tnerruC)"L"( )1( 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7 5P, 0 5P- 7, 6P 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0 9P- 7, 01P 0 01P- 7 0.5A m :SETON .sm001sitnerructuptuoegarevanehwseulavlacipyT.1 IlatoT.2 )kaep(LO 8P,2P,1P,0Prof 6 8P, 7 .sselroAm08ebtsum01Pdna,9P, IlatoT )kaep(LO 8Pdna,7P,6P,5P,4P,3Prof 0 8Pot 4 .sselroAm08ebtsum IlatoT )kaep(HO .sselroAm04-ebtsum2Pdna,1P,0Prof IlatoT )kaep(HO 8Prof 6 8P, 7 .sselroAm04-ebtsum01Pdna,9P, IlatoT )kaep(HO .sselroAm04-ebtsum5Pdna,4P,3Prof IlatoT )kaep(HO 8Pdna,7P,6Prof 0 8Pot 4 .sselroAm04-ebtsum .3V HI Vdna LI 8Profecnerefer 7 8Pnehwseilppa 7 .troptupnielbammargorpasadesusi 8PnehwylppatonseodtI 7 Xsadesusi NIC .

Page 32 65fo5002,10.voN01.1.veR 0110-8300B30JER 5. Electrical CharacteristicspuorG08/C23M Table 5.2 Recommended Operating Conditions (Continued) (VCC1 =V CC2 =3.0V to 5.5V at Topr=–20 to 85oC unless otherwise specified) lobmySr etemaraP dradnatS tinU .niM. pyT. xaM (f KLCB )y cneuqerFnoitarepOUPCV 1CC V5.5ot2.4=0 2 3z HM V 1CC V5.5ot0.3=0 4 2z HM X(f NI )y cneuqerFtupnIkcolCniaMV 1CC V5.5ot2.4=0 2 3z HM V 1CC V5.5ot0.3=0 4 2z HM X(f NIC )y cneuqerFkcolCbuS 867.230 5z Hk (f gniR ) (ycneuqerFrotallicsOpihc-nO5 2=rpoT) C° 5.01 2 z HM (f LLP )y cneuqerFkcolCLLPV 1CC V5.5ot2.4=0 12 3z HM V 1CC V5.5ot0.3=0 14 2z HM t )LLP(US rezisehtnySycneuqerFLLPezilibatSotemiTtiaWV 1CC V0.5=5 s m V 1CC V3.3=0 1s m

Page 33 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M 5. Electrical Characteristics VCC1 =VCC2 =5V Table 5.3 Electrical Characteristics (VCC1 =VCC2 =4.2 to 5.5V, VSS =0V at Topr= –20 to 85oC, f(BCLK)=32MHZ unless otherwise specified) lobmySr etemaraPn oitidnoC dradnatS tinU.niM. pyT. xaM V HO )"H"(hgiHtuptuO egatloV 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 I HO Am5-= V CC -2 0.2 V CC 2 V 6P 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0- 9P 7 01P, 0 01P- 7 I HO Am5-= V CC -1 0.2 V CC 1 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 I HO 002-= µA V CC -2 3.0 V CC 2 V 6P 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0- 9P 7 01P, 0 01P- 7 I HO 002-= µA V CC -1 3.0 V CC 1 X TUO I HO Am1-=0 .3V CC 1 V X TUOC rewoPhgiH deilppadaoloN5 .2V rewoPwoL deilppadaoloN6 .1 V LO )"L"(woLtuptuO egatloV 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 I LO Am5=0 .2V 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 I LO 002= µA5 4.0V X TUO I LO Am1=0 .2V X TUOC rewoPhgiH deilppadaoloN0 V rewoPwoL deilppadaoloN0 V +T V- -T siseretsyH 0AT,YDR,DLOH NI 4AT- NI 0BT, NI 5BT- NI , DA,5TNI-0TNI GRT ,4KLC-0KLC,4STC-0STC, 0AT TUO 4AT- TUO ,4DxR-0DxR,3IK-0IK,IMN, 4ADS-0ADS,4LCS-0LCS 2.00 .1V TESER2 .08 .1V IHI )"H"(hgiHtupnI tnerruC 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7 9P, 0 9P- 7, 01P 0 01P- 7 X, NI VNC,TESER, SS ETYB, VI V5=0 .5 µA ILI )"L"(woLtupnI tnerruC 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7 9P, 0 9P- 7, 01P 0 01P- 7 X, NI VNC,TESER, SS ETYB, VI V0=0 .5- µA R PULLUP ecnatsiseRpu-lluP 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 VI V0=0 20 47 61k Ω fR NIX ecnatsiseRkcabdeeFX NI 5.1M Ω fR NICX ecnatsiseRkcabdeeFX NIC 51M Ω V MAR egatloVybdnatSMARe dompotsnI0 .2V I CC tnerruCylppuSrewoP, edompihc-elgnisnI tfelerasniptuptuo sniprehtodnanepo Votdetcennocera SS . ,evawerauqS,zHM23=)KLCB(f noisividoN 220 6A m ,edomtiawnI,zHk23=)KLCB(f C°52=rpoT 01 µA ,spotskcolcelihW5 2=rpoTC ° 8.05 µA ,spotskcolcelihW5 8=rpoTC ° 02 µA

Page 34 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M 5. Electrical Characteristics VCC1 =VCC2 =5V lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU .niM. pyT. xaM -n oituloseRV FER V= 1CC 01s tiB LNIr orrEytiraenilnoNlargetnIV FER V= 1CC V= 2CC V5= NA 0 NAot 7,, 0XENA 1XENA 3± BSL BSL pma-polanretxE edomnoitcennoc 7± BSL BSL LNDr orrEytiraenilnoNlaitnereffiD 1±B SL -r orrEtesffO 3±B SL -r orrEniaG 3±B SL R REDDAL reddaLrotsiseRV =FER V 1CC 80 4k Ω t VNOC emiTnoisrevnoCtib-01 )2,1( 60.2 µs t VNOC emiTnoisrevnoCtib-8 )2,1( 57.1 µs t PMAS emiTgnilpmaS )1( 881.0 µs V FER egatloVecnerefeR 2V 1CC V V AI egatloVtupnIgolanA 0V FER V :SETON X(fediviD.1 NI peekot,zHM61gnideecxefi,) φ .sselrozHM61taycneuqerfDA .noitcnufdlohdnaelpmasehtgnisuhtiW.2 lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU .niM. pyT. xaM -n oituloseR 8s tiB -y caruccAetulosbA 0.1% t US emiTputeS 3 µs R O ecnatsiseRtuptuO 40 10 2k Ω I FERV tnerruCtupnIylppuSrewoPecnerefeR) 1etoN(5 .1A m :ETON gniebton,retrevnocA/Dehtfo)1,0=i(retsigeriADehT.retrevnocA/DenognisunehwtnemerusaeM.1 00"ottessi,desu 61 .dedulcxesiretrevnocD/AehtnireddalrotsiserehT." I FERV Von("0"ottessiretsiger1NOC0DAehtnitibTUCVehtfineveswolf FER .)noitcennoc Table 5.4 A/D Conversion Characteristics (VCC1 =V CC2 =AV CC =V REF =4.2 to 5.5V, Vss= AVSS = 0V at Topr=–20 to 85oC, f(BCLK) = 32MHZ unless otherwise specified) Table 5.5 D/A Conversion Characteristics (VCC1 =V CC2 =V REF =4.2 to 5.5V, VSS =AV SS= 0V at Topr=–20 to 85oC, f(BCLK) = 32MHZ unless otherwise specified)

Page 35 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M 5. Electrical Characteristics VCC1 =VCC2 =5V lobmySr etemaraP dradnatS tinU .niM. xaM 1cat )BD-DR( )dradnatsDR(emiTsseccAtupnIataD )1etoN(s n 1cat )BD-DA( )dradnatsSC,dradnatsDA(emiTsseccAtupnIataD )1etoN(s n 2cat )BD-DR( )subdrxelpitlumehthtiwecapsagnisseccanehw,dradnatsDR(emiTsseccAtupnIataD )1etoN(s n 2cat )BD-DA( )subdexelpitlumehthtiwecapsagnisseccanehw,dradnatsDA(emiTsseccAtupnIataD )1etoN(s n ust )KLCB-BD( emiTputeStupnIataD 62s n ust )KLCB-YDR( emiTputeStupnIYDR 62s n ust )KLCB-DLOH( emiTputeStupnIDLOH 03s n ht )BD-DR( emiTdloHtupnIataD 0s n ht )YDR-KLCB( emiTdloHtupnIYDR 0s n ht )DLOH-KLCB( emiTdloHtupnIDLOH 0s n dt )ADLH-KLCB( emiTyaleDtuptuOADLH 52s n :ETON atresnI.selcycsublanretxednaycnceuqerfKLCBotgnidrocca,snoitauqegniwollofehtmorfdeniatboebnacseulaV.1 (f,ycneuqerfnoitarepoehtrewolroetatstiaw KLCB .evitagensieulavdetaluclacehtfi,) lobmySr etemaraP dradnatS tinU .niM. xaM cte miTelcyCtupnIkcolClanretxE 52.13s n wt )H( htdiW)"H"(hgiHtupnIkcolClanretxE 57.31s n wt )L( htdiW)"L"(woLtupnIkcolClanretxE 57.31s n rte miTesiRkcolClanretxE 5s n fte miTllaFkcolClanretxE 5s n Timing Requirements (VCC1 =V CC2 =4.2 to 5.5V, VSS =0V at Topr=–20 to 85oC unless otherwise specified) Table 5.6 External Clock Input Table 5.7 Memory Expansion Mode and Microprocessor Mode tac1(RD – DB) = f(BCLK) X 2 – 3510 X m [ns] (if external bus cycle is aφ + bφ, m=(bx2)+1) tac2(AD – DB) = f(BCLK) X 2 – 3510 X p9 [ns] (if external bus cycle is aφ + bφ, p={(a+b-1)x2}+1) – 3510 X n9 [ns] (if external bus cycle is aφ + bφ, n=a+b)f(BCLK) tac1(AD – DB) = tac2(RD – DB) = f(BCLK) X 2 – 3510 X m9 [ns] (if external bus cycle is aφ + bφ, m=(bx2)-1)

Page 36 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M 5. Electrical Characteristics VCC1 =VCC2 =5V lobmySr etemaraP dradnatS tinU .niM. xaM ct )AT( iAT NI emiTelcyCtupnI 001s n wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 04s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 04s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )AT( iAT NI emiTelcyCtupnI 004s n wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 002s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )AT( iAT NI emiTelcyCtupnI 002s n wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 001s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 001s n lobmySr etemaraP dradnatS tinU .niM. xaM wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 001s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 001s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )PU( iAT TUO emiTelcyCtupnI 0002s n wt )HPU( iAT TUO htdiW)"H"(hgiHtupnI 0001s n wt )LPU( iAT TUO htdiW)"L"(woLtupnI 0001s n ust )NIT-PU( iAT TUO emiTputeStupnI 004s n ht )PU-NIT( iAT TUO emiTdloHtupnI 004s n Timing Requirements (VCC1 =V CC2 =4.2 to 5.5V, VSS =0V at Topr=–20 to 85oC unless otherwise specified) Table 5.8 Timer A Input (Count Source Input in Event Counter Mode) Table 5.9 Timer A Input (Gate Input in Timer Mode) Table 5.10 Timer A Input (External Trigger Input in One-Shot Timer Mode) Table 5.11 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Table 5.12 Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)

Page 37 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M 5. Electrical Characteristics VCC1 =VCC2 =5V lobmySr etemaraP dradnatS tinU .niM. xaM ct )BT( iBT NI )egdeenonodetnuoc(emiTelcyCtupnI 001s n wt )HBT( iBT NI )egdeenonodetnuoc(htdiW)"H"(hgiHtupnI 04s n wt )LBT( iBT NI )egdeenonodetnuoc(htdiW)"L"(woLtupnI 04s n ct )BT( iBT NI )segdehtobnodetnuoc(emiTelcyCtupnI 002s n wt )HBT( iBT NI )segdehtobnodetnuoc(htdiW)"H"(hgiHtupnI 08s n wt )LBT( iBT NI )segdehtobnodetnuoc(htdiW)"L"(woLtupnI 08s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )BT( iBT NI emiTelcyCtupnI 004s n wt )HBT( iBT NI htdiW)"H"(hgiHtupnI 002s n wt )LBT( iBT NI htdiW)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )BT( iBT NI emiTelcyCtupnI 004s n wt )HBT( iBT NI htdiW)"H"(hgiHtupnI 002s n wt )LBT( iBT NI htdiW)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU .niMx aM ct )DA( DA GRT )reggirtrofderiuqer(emiTelcyCtupnI 0001s n wt )LDA( DA GRT htdiW)"L"(woLtupnI 521s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )KC( emiTelcyCtupnIiKLC 002s n wt )HKC( htdiW)"H"(hgiHtupnIiKLC 001s n wt )LKC( htdiW)"L"(woLtupnIiKLC 001s n dt )Q-C( emiTyaleDtuptuOiDxT 08s n ht )Q-C( emiTdloHiDxT 0s n ust )C-D( emiTputeStupnIiDxR 03s n ht )Q-C( emiTdloHtupnIiDxR 09s n lobmySr etemaraP dradnatS tinU .niM. xaM wt )HNI( htdiW)"H"(hgiHtupnIiTNI 052s n wt )LNI( htdiW)"L"(woLtupnIiTNI 052s n Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.13 Timer B Input (Count Source Input in Event Counter Mode) Table 5.14 Timer B Input (Pulse Period Measurement Mode) Table 5.15 Timer B Input (Pulse Width Measurement Mode) Table 5.16 A/D Trigger Input Table 5.17 Serial I/O Table 5.18 External Interrupt INTi Input

Page 38 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M 5. Electrical Characteristics VCC1 =VCC2 =5V lobmySr etemaraP tnemerusaeM noitidnoC dradnatS tinU .niM. xaM dt )DA-KLCB( emiTyaleDtuptuOsserddA 81s n ht )DA-KLCB( )dradnatsKLCB(emiTdloHtuptuOsserddA 3-s n ht )DA-DR( )dradnatsDR(emiTdloHtuptuOsserddA 0s n ht )DA-RW( )dradnatsRW(emiTdloHtuptuOsserddA )1etoN(s n dt )SC-KLCB( emiTyaleDtuptuOlangiStceleS-pihC 81s n ht )SC-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiStceleS-pihC 3-s n ht )SC-DR( )dradnatsDR(emiTdloHtuptuOlangiStceleS-pihC 0s n ht )SC-RW( )dradnatsRW(emiTdloHtuptuOlangiStceleS-pihC )1etoN(s n dt )DR-KLCB( emiTyaleDtuptuOlangiSDR 81s n ht )DR-KLCB( emiTdloHtuptuOlangiSDR 5-s n dt )RW-KLCB( emiTyaleDtuptuOlangiSRW 81s n ht )RW-KLCB( emiTdloHtuptuOlangiSRW 5-s n dt )RW-BD( )dradnatsRW(emiTyaleDtuptuOataD )2etoN(s n ht )BD-RW( )dradnatsRW(emiTdloHtuptuOataD )1etoN(s n wt )RW( htdiWtuptuORW )2etoN(s n td(DB – WR) = f(BCLK) – 20 [ns] th(WR – DB) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] tw(WR) = f(BCLK) X 2

10 X n

– 15 [ns] 1. Values can be obtained from the following equations, according to BCLK frequency. 2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycles. (if external bus cycle is aφ + bφ, n=(bx2)-1)

10 X m

(if external bus cycle is aφ + bφ, m= b) NOTES: See Figure 5.1 Switching Characteristics (VCC1 = VCC2 = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.19 Memory Expansion Mode and Microprocessor Mode (when accessing external memory space)

Page 39 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M 5. Electrical Characteristics VCC1 =VCC2 =5V lobmySr etemaraP tnemerusaeM noitidnoC dradnatS tinU .niM. xaM dt )DA-KLCB( emiTyaleDtuptuOsserddA 81s n ht )DA-KLCB( )dradnatsKLCB(emiTdloHtuptuOsserddA 3-s n ht )DA-DR( )dradnatsDR(emiTdloHtuptuOsserddA )1etoN(s n ht )DA-RW( )dradnatsRW(emiTdloHtuptuOsserddA )1etoN(s n dt )SC-KLCB( emiTyaleDtuptuOlangiStceleS-pihC 81s n ht )SC-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiStceleS-pihC 3-s n ht )SC-DR( )dradnatsDR(emiTdloHtuptuOlangiStceleS-pihC )1etoN(s n ht )SC-RW( )dradnatsRW(emiTdloHtuptuOlangiStceleS-pihC )1etoN(s n dt )DR-KLCB( emiTyaleDtuptuOlangiSDR 81s n ht )DR-KLCB( emiTdloHtuptuOlangiSDR 5-s n dt )RW-KLCB( emiTyaleDtuptuOlangiSRW 81s n ht )RW-KLCB( emiTdloHtuptuOlangiSRW 5-s n dt )RW-BD( )dradnatsRW(emiTyaleDtuptuOataD )2etoN(s n ht (- RW) BD )dradnatsRW(emiTdloHtuptuOataD )1etoN(s n dt )ELA-KLCB( )dradnatsKLCB(emiTyaleDtuptuOlangiSELA 81s n ht )ELA-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiSELA 5-s n dt )ELA-DA( )dradnatssserdda(emiTyaleDtuptuOlangiSELA )3etoN(s n ht )DA-ELA( )dradnatssserdda(emiTdloHtuptuOlangiSELA )4etoN(s n zdt )DA-DR( emiTtratStaolFtuptuOsserddA 8s n td(DB – WR) = 10 X m – 25 [ns] (if external bus cycle is aφ + bφ, m= (bx2)-1) th(RD – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(RD – CS) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – DB) = f(BCLK) X 2 10 9 – 10 [ns] td(AD – ALE) = f(BCLK) X 2 – 20 [ns] (if external bus cycle is aφ + bφ, n= a) th(ALE – AD) = f(BCLK ) X 2 – 10 [ns] (if external bus cycle is aφ + bφ, n= a) f(BCLK) X 2 1. Values can be obtained from the following equations, according to BCLK frequency. 2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle. 3. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle.

1. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle.

NOTES: See Figure 5.1 Switching Characteristics (VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.20 Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space with the multiplexed bus)

Page 40 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M 5. Electrical Characteristics VCC1 =VCC2 =5V P10 30pF Figure 5.1 P0 to P10 Measurement Circuit

Page 41 65fo5002,10.voN01.1.veR 0110-8300B30JER 5. Electrical CharacteristicspuorG08/C23M Figure 5.2 VCC1 =V CC2 =5V Timing Diagram (1) BCLK RD 18ns.max -5ns.min Hi-ZDB 0ns.min 0ns.min tsu(DB-BCLK) td(BCLK-RD) 26ns.min(1) CSi td(BCLK-CS) 18ns.max(1) ADi th(BCLK-AD) -3ns.min th(BCLK-CS) -3ns.min BHE tcyc td(BCLK-AD) 0ns.min tac1(AD-DB)(2) WR,WRL, WRH 18ns.max -5ns.min BCLK CSi td(BCLK-CS) 18ns.max ADi td(BCLK-AD) 18ns.max -3ns.min -3ns.min tcyc BHE DBi td(BCLK-WR) th(WR-DB) (3) td(DB-WR) =(tcyc x m-20)ns.min (if external bus cycle is aφ+bφ, m=b) th(WR-DB) =(tcyc/2-10)ns.min th(WR-AD) =(tcyc/2-10)ns.min th(WR-CS) =(tcyc/2-10)ns.min tw(WR) =(tcyc/2 x n-15)ns.min (if external bus cycle is aφ+bφ , n=(bx2)-1) Vcc1=Vcc2=5V th(BCLK-RD) th(RD-DB) th(RD-AD) th(RD-CS) th(BCLK-WR) th(BCLK-AD) th(BCLK-CS) th(WR-CS) (3) th(WR-AD) (3) tw(WR) (3) tac1(RD-DB)(2) 18ns.max(1) [ Read Timing ] (1φ +1φ Bus Cycle) [ Write timing ] (1φ +1φ Bus Cycle) NOTE: 3. Varies with operation frequency: Measurement Conditions:

• VCC1 =VCC2 =4.2 to 5.5V
• Input high and low voltage: VIH=2.5V, VIL=0.8V
• Output high and low voltage: VOH =2.0V, VOL =0.8V Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space) NOTES: 1. Values guaranteed only when the microcomputer is used independently. A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK). 2. Varies with operation frequency: tac1(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2)+1) tac1(AD-DB)=(tcyc x n-35)ns.max (if external bus cycle is aφ + bφ, n=a+b) td(DB-WR) (3) tcyc= 10 f(BCLK)

Page 42 65fo5002,10.voN01.1.veR 0110-8300B30JER 5. Electrical CharacteristicspuorG08/C23M Figure 5.3 VCC1 =V CC2 =5V Timing Diagram (2) BCLK CSi ADi RD -5ns.min BHE ADi /DBi 26ns.min td(BCLK-RD) tsu(DB-BCLK) tac2(RD-DB) tdz(RD-AD) 8ns.max ALE td(BCLK-ALE) 18ns.max td(BCLK-CS) td(AD-ALE) th(ALE-AD) th(BCLK-RD) th(RD-AD) th(RD-DB)td(BCLK-AD) th(BCLK-CS) th(RD-CS) th(BCLK-ALE) tcyc Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space with the multiplexed bus) -5ns.min BCLK CSi ADi BHE ADi /DBiWR,WRL, WRH th(WR-CS) ALE th(BCLK-WR) td(DB-WR) 18ns.max tac2(AD-DB) [ Read Timing ] (2φ +2φ Bus Cycle) Address (1) (1) (1) td(AD-ALE)=(tcyc/2 x n-20)ns.min (if external bus cycle is aφ + bφ, n=a) th(ALE-AD)=(tcyc/2 x n-10)ns.min (if external bus cycle is aφ + bφ, n=a) th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min tac2(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2)-1) tac2(AD-DB)=(tcyc/2 x p-35)ns.max (if external bus cycle is aφ + bφ, p={(a+b-1) x 2}+1) NOTE: 1. Varies with operation frequency: Data input Address (1) [ Write Timing ] (2φ +2φ Bus Cycle) Address Data output Address (2) (2) td(AD-ALE)=(tcyc/2 x n - 20)ns.min (if external bus cycle is aφ + bφ, n=a) th(ALE-AD)=(tcyc/2 x n -10)ns.min (if external bus cycle is aφ + bφ, n=a) th(WR-AD) =(tcyc/2-10)ns.min, th(WR-CS) =(tcyc/2-10)ns.min, th(WR-DB) =(tcyc/2-10)ns.min td(DB-WR) =(tcyc/2 x m-25)ns.min (if external bus cycle is aφ + bφ, m=(b x 2)-1) NOTE: 2. Varies with operation frequency: Measurement Conditions:

• V CC1 =V CC2 =4.2 to 5.5V
• Input high and low voltage: VIH=2.5V, VIL=0.8V
• Output high and low voltage: VOH =2.0V, VOL =0.8V Vcc1=Vcc2=5V -3ns.min (1) th(BCLK-AD) -3ns.min0ns.min (1) 18ns.max -5ns.min 18ns.max 18ns.max th(WR-DB) (2) th(BCLK-AD) -3ns.min th(WR-AD) 18ns.max td(BCLK-WR) 18ns.max td(BCLK-AD) td(AD-ALE) (2) td(BCLK-CS) 18ns.max td(BCLK-ALE) -5ns.min th(BCLK-ALE) tcyc (2) th(BCLK-CS) -3ns.min th(ALE-AD) (2) tcyc= 10 f(BCLK)

Page 43 65fo5002,10.voN01.1.veR 0110-8300B30JER 5. Electrical CharacteristicspuorG08/C23M tsu(D–C) TAiIN Input TAiOUT Input In event counter mode TBiIN Input CLKi TxDi RxDi tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C–Q) th(C–D) th(C–Q) th(TIN–UP) tsu(UP–TIN)TAiIN Input (When counting on the falling edge) TAiIN Input (When counting on the rising edge) TAiOUT Input (Counter increment/ decrement input) INTi Input AD TRG Input Vcc1=Vcc2=5V NMI input

2 CPU clock cycles +

("L" width) Figure 5.4 VCC1 =V CC2 =5V Timing Diagram (3)

Page 44 65fo5002,10.voN01.1.veR 0110-8300B30JER 5. Electrical CharacteristicspuorG08/C23M th(BCLK –HOLD)tsu(HOLD –BCLK) td(BCLK –HLDA)td(BCLK –HLDA) Hi–Z Measurement Conditions

• VCC1 =VCC2 =4.2 to 5.5V
• Input high and low voltage: VIH=4.0V, VIL=1.0V
• Output high and low voltage: VOH =2.5V, VOL =2.5V Memory Expansion Mode and Microprocessor Mode BCLK HOLD Input HLDA Output P0, P1, P2, P3, P4, 0 to P52 RDY input tsu(RDY –BCLK) th(BCLK –RDY) BCLK RD (Multiplexed bus) (Multiplexed bus) WR, WRL, WRH WR, WRL, WRH (Separate bus) RD (Separate bus) Vcc1=Vcc2=5V Figure 5.5 VCC1 =V CC2 =5V Timing Diagram (4)

Page 45 65fo5002,10.voN01.1.veR 0110-8300B30JER 5. Electrical Characteristics VCC1 =VCC2 =3.3V puorG08/C23M Table 5.21 Electrical Characteristics (VCC1 =V CC2 =3.0 to 3.6V, VSS =0V at Topr = –20 to 85oC, f(BCLK)=24MHZ unless otherwise specified) lobmySr etemaraPn oitidnoC dradnatS tinU.niM. pyT. xaM V HO )"H"(hgiHtuptuO egatloV 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 I HO Am1-=V 2CC 6.0-V 2CC V 6P 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6 8P, 7 9P, 0- 9P 7 01P, 0 01P- 7 V 1CC 6.0-V 1CC V X TUO I HO Am1.0-=7 .2V 1CC V X TUOC rewoPhgiH deilppadaoloN5 .2V rewoPwoL deilppadaoloN6 .1V V LO )"L"(woLtuptuO egatloV 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0- 4P 7 5P, 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 4, 8P 6 8P, 7 9P, 0 9P- 7 01P, 0 01P- 7 I LO Am1=5 .0V X TUO I LO Am1.0=5 .0V X TUOC rewoPhgiH deilppadaoloN0 V rewoPwoL deilppadaoloN0 V V +T V- -T siseretsyH 0AT,YDR,DLOH NI 4AT- NI 0BT, NI 5BT- NI , DA,5TNI-0TNI GRT -0KLC,4STC-0STC, 0AT,4KLC TUO 4AT- TUO -0DxR,3IK-0IK,IMN, 4ADS-0ADS,4LCS-0LCS,4DxR 2.00 .1V TESER2 .08 .1V IHI )"H"(hgiHtupnI tnerruC 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0- 4P 7 5P, 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7, 9P 0 9P- 7 01P, 0 01P- 7 X, NI VNC,TESER, SS , ETYB VI V3=0 .4 µA ILI )"L"(woLtupnI tnerruC 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0- 4P 7 5P, 0 5P- 7 6P, 0 6P- 7 7P, 0 7P- 7 8P, 0 8P- 7, 9P 0 9P- 7 01P, 0 01P- 7 X, NI VNC,TESER, SS , ETYB VI V0=0 .4- µA R PULLUP ecnatsiseRpu-lluP 0P 0 0P- 7 1P, 0 1P- 7 2P, 0 2P- 7 3P, 0 3P- 7 4P, 0 4P- 7, 5P 0 5P- 7 6P, 0 6P- 7 7P, 2 7P- 7 8P, 0 8P- 4 8P, 6, 8P 7 9P, 0 9P- 7 01P, 0 01P- 7 VI V0=0 40 70 05k Ω fR NIX ecnatsiseRkcabdeeFX NI 0.3M Ω fR NICX ecnatsiseRkcabdeeFX NIC 0.03M Ω V MAR egatloVybdnatSMARe dompotsni0 .2V I CC ylppuSrewoP tnerruC :noitidnoctnemerusaeM ,edompihc-elgnisnI nepotfelerasniptuptuo erasniprehtodna Votdetcennoc SS . ,evawerauqS,zHM42=)KLCB(f noisividoN 715 3A m ,edomtiawnI,zHk23=)KLCB(f 52=rpoTC ° 01 µA ,spotskcolcelihW5 2=rpoTC ° 8.05 µA ,spotskcolcelihW5 8=rpoTC ° 05 µA

Page 46 65fo5002,10.voN01.1.veR 0110-8300B30JER 5. Electrical Characteristics VCC1 =VCC2 =3.3V puorG08/C23M Table 5.22 A/D Conversion Characteristics (VCC1 =V CC2 =AV CC =V REF = 3.0 to 3.6V, VSS =AV SS =0V at Topr = –20 to 85oC, f(BCLK) = 24MHZ unless otherwise specified) Table 5.23 D/A Conversion Characteristics (VCC1 =V CC2 =VREF =3.0 to 3.6V, VSS =AV SS =0V at Topr = –20 to 85oC, f(BCLK) = 24MHZ unless otherwise specified) lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU .niM. pyT. xaM -n oituloseRV FER V= 1CC 01s tiB LNIr orrEytiraenilnoNlargetnI) tib-8(H&SoNV 1CC V= 2CC V= FER V3.3=2 ±B SL LNDr orrEytiraenilnoNlaitnereffiD) tib-8(H&SoN1 ±B SL -r orrEtesffO) tib-8(H&SoN2 ±B SL -r orrEniaG) tib-8(H&SoN2 ±B SL R REDDAL reddaLrotsiseRV FER V= 1CC 0.80 4k Ω t VNOC emiTnoisrevnoCtib-8 )2,1( 1.6 µs V FER egatloVecnerefeR 3.3V 1CC V V AI egatloVtupnIgolanA 0V FER V dloHdnaelpmaS:H&S :SETON X(fediviD.1 NI peekot,zHM01gnideecxefi,) φ .sselrozHM01taycneuqerfDA .elbaliavatonH&S.2 lobmySr etemaraPn oitidnoCtnemerusaeM dradnatS tinU .niM. pyT. xaM -n oituloseR 8s tiB -y caruccAetulosbA 0.1% t US emiTputeS 3 µs R O ecnatsiseRtuptuO 40 10 2k Ω I FERV tnerruCtupnIylppuSrewoPecnerefeR) 1etoN(0 .1A m :ETON gniebton,retrevnocA/Dehtfo)1,0=i(retsigeriADehT.retrevnocA/DenognisunehwstlusertnemerusaeM.1 00"ottessi,desu 61 .dedulcxesiretrevnocD/AehtnireddalrotsiserehT." I FERV Von("0"ottessiretsiger1NOC0DAehtnitibTUCVehtfineveswolf FER .)noitcennoc

Page 47 65fo5002,10.voN01.1.veR 0110-8300B30JER 5. Electrical Characteristics VCC1 =VCC2 =3.3V puorG08/C23M Timing Requirements (VCC1 =V CC2 = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.24 External Clock Input Table 5.25 Memory Expansion Mode and Microprocessor Mode lobmySr etemaraP dradnatS tinU .niM. xaM cte miTelcyCtupnIkcolClanretxE 14s n wt )H( htdiW)"H"(hgiHtupnIkcolClanretxE 81s n wt )L( htdiW)"L"(woLtupnIkcolClanretxE 81s n rte miTesiRkcolClanretxE 5s n fte miTllaFkcolClanretxE 5s n lobmySr etemaraP dradnatS tinU .niM. xaM 1cat )BD-DR( )dradnatsDR(emiTsseccAtupnIataD )1etoN(s n 1cat )BD-DA( )dradnatsSC,dradnatsDA(emiTsseccAtupnIataD )1etoN(s n 2cat )BD-DR( )subdexelpitlumehthtiwecapsagnisseccanehw,dradnatsDR(emiTsseccAtupnIataD )1etoN(s n 2cat )BD-DA( )subdexelpitlumehthtiwecapsagnisseccanehw,dradnatsDA(emiTsseccAtupnIataD )1etoN(s n ust )KLCB-BD( emiTputeStupnIataD 03s n ust )KLCB-YDR( emiTputeStupnIYDR 04s n ust )KLCB-DLOH( emiTputeStupnIDLOH 06s n ht )BD-DR( emiTdloHtupnIataD 0s n ht )YDR-KLCB( emiTdloHtupnIYDR 0s n ht )DLOH-KLCB( emiTdloHtupnIDLOH 0s n dt )ADLH-KLCB( emiTyaleDtuptuOADLH 52s n :ETON atresnI.selcycsublanretxednaycnceuqerfKLCBotgnidrocca,snoitauqegniwollofehtmorfdeniatboebnacseulaV.1 (f,ycneuqerfnoitarepoehtrewolroetatstiaw KLCB .evitagensieulavdetaluclacehtfi,) tac1(RD – DB) = f(BCLK) X 2 – 3510 X m [ns] (if external bus cycle is aφ + bφ, m=(bx2)+1) tac2(AD – DB) = f(BCLK) X 2 – 3510 X p9 [ns] (if external bus cycle is aφ + bφ, p={(a+b-1)x2}+1) – 3510 X n9 [ns] (if external bus cycle is aφ + bφ, n=a+b)f(BCLK) tac1(AD – DB) = tac2(RD – DB) = f(BCLK) X 2 – 3510 X m9 [ns] (if external bus cycle is aφ + bφ, m=(bx2)-1)

Page 48 65fo5002,10.voN01.1.veR 0110-8300B30JER 5. Electrical Characteristics VCC1 =VCC2 =3.3V puorG08/C23M Timing Requirements (VCC1 =VCC2 = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.26 Timer A Input (Count Source Input in Event Counter Mode) Table 5.27 Timer A Input (Gate Input in Timer Mode) Table 5.28 Timer A Input (External Trigger Input in One-Shot Timer Mode) Table 5.29 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Table 5.30 Timer A Input (Counter Increment/decrement Input in Event Counter Mode) lobmySr etemaraP dradnatS tinU .niM. xaM ct )AT( iAT NI emiTelcyCtupnI 001s n wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 04s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 04s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )AT( iAT NI emiTelcyCtupnI 004s n wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 002s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )AT( iAT NI emiTelcyCtupnI 002s n wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 001s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 001s n lobmySr etemaraP dradnatS tinU .niM. xaM wt )HAT( iAT NI htdiW)"H"(hgiHtupnI 001s n wt )LAT( iAT NI htdiW)"L"(woLtupnI 001s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )PU( iAT TUO emiTelcyCtupnI 0002s n wt )HPU( iAT TUO htdiW)"H"(hgiHtupnI 0001s n wt )LPU( iAT TUO htdiW)"L"(woLtupnI 0001s n ust )NIT-PU( iAT TUO emiTputeStupnI 004s n ht )PU-NIT( iAT TUO emiTdloHtupnI 004s n

Page 49 65fo5002,10.voN01.1.veR 0110-8300B30JER 5. Electrical Characteristics VCC1 =VCC2 =3.3V puorG08/C23M Timing Requirements (VCC1 =VCC 2= 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.31 Timer B Input (Count Source Input in Event Counter Mode) Table 5.32 Timer B Input (Pulse Period Measurement Mode) Table 5.33 Timer B Input (Pulse Width Measurement Mode) Table 5.34 A/D Trigger Input Table 5.35 Serial I/O Table 5.36 External Interrupt INTi Input lobmySr etemaraP dradnatS tinU .niM. xaM ct )BT( iBT NI )egdeenonodetnuoc(emiTelcyCtupnI 001s n wt )HBT( iBT NI )egdeenonodetnuoc(htdiW)"H"(hgiHtupnI 04s n wt )LBT( iBT NI )egdeenonodetnuoc(htdiW)"L"(woLtupnI 04s n ct )BT( iBT NI )segdehtobnodetnuoc(emiTelcyCtupnI 002s n wt )HBT( iBT NI )segdehtobnodetnuoc(htdiW)"H"(hgiHtupnI 08s n wt )LBT( iBT NI )segdehtobnodetnuoc(htdiW)"L"(woLtupnI 08s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )BT( iBT NI emiTelcyCtupnI 004s n wt )HBT( iBT NI htdW)"H"(hgiHtupnI 002s n wt )LBT( iBT NI htdiW)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )BT( iBT NI emiTelcyCtupnI 004s n wt )HBT( iBT NI htdiW)"H"(hgiHtupnI 002s n wt )LBT( iBT NI htdiW)"L"(woLtupnI 002s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )DA( DA GRT )reggirtrofderiuqer(emiTelcyCtupnI 0001s n wt )LDA( DA GRT htdiW)"L"(woLtupnI 521s n lobmySr etemaraP dradnatS tinU .niM. xaM ct )KC( emiTelcyCtupnIiKLC 002s n wt )HKC( htdiW)"H"(hgiHtupnIiKLC 001s n wt )LKC( htdiW)"L"(woLtupnIiKLC 001s n dt )Q-C( emiTyaleDtuptuOiDxT 08s n ht )Q-C( emiTdloHiDxT 0s n ust )C-D( emiTputeStupnIiDxR 03s n ht )Q-C( emiTdloHtupnIiDxR 09s n lobmySr etemaraP dradnatS tinU .niM. xaM wt )HNI( htdiW)"H"(hgiHtupnIiTNI 052s n wt )LNI( htdiW)"L"(woLtupnIiTNI 052s n

Page 50 65fo5002,10.voN01.1.veR 0110-8300B30JER 5. Electrical Characteristics VCC1 =VCC2 =3.3V puorG08/C23M lobmySr etemaraP tnemerusaeM noitidnoC dradnatS tinU .niM. xaM dt )DA-KLCB( emiTyaleDtuptuOsserddA 81s n ht )DA-KLCB( )dradnatsKLCB(emiTdloHtuptuOsserddA 0s n ht )DA-DR( )dradnatsDR(emiTdloHtuptuOsserddA 0s n ht )DA-RW( )dradnatsRW(emiTdloHtuptuOsserddA )1etoN(s n dt )SC-KLCB( emiTyaleDtuptuOlangiStceleS-pihC 81s n ht )SC-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiStceleS-pihC 0s n ht )SC-DR( )dradnatsDR(emiTdloHtuptuOlangiStceleS-pihC 0s n ht )SC-RW( )dradnatsRW(emiTdloHtuptuOlangiStceleS-pihC )1etoN(s n dt )DR-KLCB( emiTyaleDtuptuOlangiSDR 81s n ht )DR-KLCB( emiTdloHtuptuOlangiSDR 3-s n dt )RW-KLCB( emiTyaleDtuptuOlangiSRW 81s n ht )RW-KLCB( emiTdloHtuptuOlangiSRW 0s n dt )RW-BD( )dradnatsRW(emiTyaleDtuptuOataD )2etoN(s n ht )BD-RW( )dradnatsRW(emiTdloHtuptuOataD )1etoN(s n wt )RW( htdiWtuptuORW )2etoN(s n td(DB – WR) = f(BCLK) 10 x m – 20 [ns] (if external bus cycle is aφ + bφ, m=b) th(WR – DB) = f(BCLK) X 2 10 9 – 20 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] tw(WR) = f(BCLK) X 2 10 x n9 – 15 [ns] (if external bus cycle is aφ + bφ, n=(b x 2)-1) NOTES: 1. Values can be obtained from the following equations, according to BCLK frequency. 2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycles. See Figure 5.1 Switching Characteristics (VCC1 =V CC2 =3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.37 Memory Expansion Mode and Microprocessor Mode (when accessing external memory space)

Page 51 65fo5002,10.voN01.1.veR 0110-8300B30JER 5. Electrical Characteristics VCC1 =VCC2 =3.3V puorG08/C23M Switching Characteristics (VCC1 = VCC2 = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.38 Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space with the multiplexed bus) lobmySr etemaraP tnemerusaeM noitidnoC dradnatS tinU .niM. xaM dt )DA-KLCB( emiTyaleDtuptuOsserddA 81s n ht )DA-KLCB( )dradnatsKLCB(emiTdloHtuptuOsserddA 0s n ht )DA-DR( )dradnatsDR(emiTdloHtuptuOsserddA )1etoN(s n ht )DA-RW( )dradnatsRW(emiTdloHtuptuOsserddA )1etoN(s n dt )SC-KLCB( emiTyaleDtuptuOlangiStceleS-pihC 81s n ht )SC-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiStceleS-pihC 0s n ht )SC-DR( )dradnatsDR(emiTdloHtuptuOlangiStceleS-pihC )1etoN(s n ht )SC-RW( )dradnatsRW(emiTdloHtuptuOlangiStceleS-pihC )1etoN(s n dt )DR-KLCB( emiTyaleDtuptuOlangiSDR 81s n ht )DR-KLCB( emiTdloHtuptuOlangiSDR 3-s n dt )RW-KLCB( emiTyaleDtuptuOlangiSRW 81s n ht )RW-KLCB( emiTdloHtuptuOlangiSRW 0s n dt )RW-BD( )dradnatsRW(emiTyaledtuptuOataD )2etoN(s n ht )BD-RW( )dradnatsRW(emiTdloHtuptuOataD )1etoN(s n dt )ELA-KLCB( )dradnatsKLCB(emiTyaleDtuptuOlangiSELA 81s n ht )ELA-KLCB( )dradnatsKLCB(emiTdloHtuptuOlangiSELA 2-s n dt )ELA-DA( )dradnatssserdda(emiTyaleDtuptuOlangiSELA )3etoN(s n ht )DA-ELA( )dradnatssserdda(emiTdloHtuptuOlangiSELA )4etoN(s n zdt )DA-DR( emiTtratStaolFtuptuOsserddA 8s n td(DB – WR) = 10 X m9 – 25 [ns] (if external bus cycle is aφ + bφ, m=(b+2)-1) th(RD – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – AD) = f(BCLK) X 2 10 9 – 10 [ns] th(RD – CS) = f(BCLK) X 2 10 9 –10 [ns] th(WR – CS) = f(BCLK) X 2 10 9 – 10 [ns] th(WR – DB) = f(BCLK) X 2 10 9 – 20 [ns] td(AD – ALE) = f(BCLK) X 2 10 x n – 20 [ns] (if external bus cycle is aφ + bφ, n=a) th(ALE – AD) = f(BCLK) X 2 10 x n9 – 10 [ns] (if external bus cycle is aφ + bφ, n=a) f(BCLK) X 2 NOTES: 1. Values can be obtained by the following equations, according to BLCK frequency. 2. Values can be obtained by the following equations, according to BLCK frequency and external bus cycles. 3. Values can be obtained by the following equations, according to BLCK frequency and external bus cycles. 4. Values can be obtained by the following equations, according to BLCK frequency and external bus cycles. See Figure 5.1

Page 52 65fo5002,10.voN01.1.veR 0110-8300B30JER 5. Electrical CharacteristicspuorG08/C23M Figure 5.6 VCC1 =V CC2 =3.3V Timing Diagram (1) BCLK RD 18ns.max -3ns.min Hi-ZDB 0ns.min 0ns.min td(BCLK-RD) 30ns.min(1) tac1(RD-DB)(2) CSi td(BCLK-CS) 18ns.max(1) ADi 18ns.max(1) th(BCLK-AD) 0ns.min th(BCLK-CS) 0ns.min BHE tcyc td(BCLK-AD) tac1(AD-DB)(2) WR,WRL, WRH 18ns.max 0ns.min BCLK CSi 18ns.max ADi 18ns.max 0ns.min 0ns.min tcyc BHE DBi td(BCLK-WR) th(BCLK-RD) th(RD-DB) th(RD-AD) tsu(DB-BCLK) th(RD-CS) 0ns.min th(BCLK-WR) td(BCLK-CS) td(BCLK-AD) th(BCLK-AD) th(BCLK-CS) th(WR-CS) (3) td(DB-WR) (3) th(WR-DB) (3) th(WR-AD) (3) [Read Timing] (1φ + 1φ Bus Cycles) [Write Timing] (1φ + 1φ Bus Cycles) Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space) tw(WR) (3) Vcc1=Vcc2=3.3V NOTES: 1. Values guaranteed only when the microcomputer is used independently. A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK). 2. Varies with operation frequency. tac1(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2) + 1) tac1(AD-DB)=(tcyc x n-35)ns.max (if external bus cycle is aφ + bφ, n = a + b) td(DB-WR) =(tcyc x m-20)ns.min (if external bus cycle is aφ + bφ, m=b) th(WR-DB) =(tcyc/2-20)ns.min th(WR-AD) =(tcyc/2-10)ns.min th(WR-CS) =(tcyc/2-10)ns.min tw(WR) =(tcyc/2 x n-15)ns.min (if external bus cycle is aφ + bφ, n=(bx2)-1) NOTE: 3. Varies with operation frequency. Measurement Conditions

• VCC 1=V CC 2=3.0 to 3.6V
• Input high and low voltage: VIH=1.5V, VIL=0.5V
• Output high and low voltage: VOH =1.5V, VOL =1.5V tcyc= 10 f(BCLK)

Page 53 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M 5. Electrical Characteristics BCLK CSi ADi RD -3ns.min BHE ADi /DBi 30ns.min td(BCLK-RD) tsu(DB-BCLK) tdz(RD-AD) 8ns.max ALE td(BCLK-ALE) 18ns.max td(AD-ALE) th(ALE-AD) th(BCLK-RD) th(RD-AD) td(BCLK-AD) th(BCLK-CS) th(RD-CS) th(BCLK-ALE) tcyc Memory Expansion Mode and Microprocessor Mode (when accessing external memory space and using the multiplexed bus) 0ns.min BCLK CSi ADi BHE ADi /DBiWR,WRL, WRH ALE th(BCLK-WR) 18ns.max tac2(AD-DB) [ Read Timing ] (2φ +2φ Bus Cycles) Address (1) (1) (1) (1) (1) td(AD-ALE)=(tcyc/2 x n-20)ns.min (if external bus cycle is aφ + bφ, n=a) th(ALE-AD)=(tcyc/2 x n-10)ns.min (if external bus cycle is aφ + bφ, n=a) th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min tac2(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is aφ + bφ, m=(b x 2)-1) tac2(AD-DB)=(tcyc/2 x p-35)ns.max (if external bus cycle is aφ + bφ, p={(a+b-1) x 2}+1) NOTE: 1. Varies with operation frequency: (1) [ Write Timing ] (2φ +2φ Bus Cycles) Address Address td(AD-ALE)=(tcyc/2 x n - 20)ns.min (if external bus cycle is aφ + bφ, n=a) th(ALE-AD)=(tcyc/2 x n -10)ns.min (if external bus cycle is aφ + bφ, n=a) th(WR-AD) =(tcyc/2-10)ns.min, th(WR-CS) =(tcyc/2-10)ns.min, th(WR-DB) =(tcyc/2-20)ns.min td(DB-WR) =(tcyc/2 x m-25)ns.min (if external bus cycle is aφ + bφ, m=(b x 2)-1) NOTE: 2. Varies with operation frequency: Measurement Conditions:

• VCC 1=V CC 2=3.0 to 3.6V
• Input high and low voltage: VIH=1.5V, VIL=0.5V
• Output high and low voltage: VOH =1.5V, VOL =1.5V Vcc1=Vcc2=3.3V 18ns.max td(BCLK-WR) th(WR-AD) (2) th(BCLK-AD) 0ns.min Data output th(ALE-AD) -2ns.min td(BCLK-ALE) th(BCLK-ALE) 18ns.max 18ns.max 0ns.minth(WR-CS) td(AD-ALE) td(BCLK-CS) td(BCLK-AD) th(BCLK-CS) td(DB-WR) th(WR-DB) tcyc (2) (2) (2) (2) (2) 18ns.max 18ns.max 18ns.max 0ns.min 0ns.mintac2(RD-DB) -2ns.min td(BCLK-CS) th(RD-DB) th(BCLK-AD) 0ns.min Data input Address tcyc= 10 f(BCLK) Figure 5.7 VCC1 =V CC2 =3.3V Timing Diagram (2)

Page 54 65fo5002,10.voN01.1.veR 0110-8300B30JER 5. Electrical CharacteristicspuorG08/C23M Figure 5.8 VCC1 =V CC2 =3.3V Timing Diagram (3) tsu(D–C) TAiIN Input TAiOUT Input In event counter mode TBiIN Input CLKi TxDi RxDi tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C–Q) th(C–D) th(C–Q) th(TIN–UP) tsu(UP–TIN)TAiIN Input (When counting on falling edge) TAiIN Input (When counting on rising edge) TAiOUT Input (Counter increment/ decrement input) INTi Input AD TRG Input Vcc1=Vcc2=3.3V NMI input ("L" width)

Page 55 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M 5. Electrical Characteristics Figure 5.9 VCC1 =V CC2 =3.3V Timing Diagram (4) Measurement Conditions:

• VCC1 =V CC2 =3.0 to 3.6V
• Input high and low voltage: VIH=2.4V, VIL=0.6V
• Output high and low voltage: VOH =1.5V, VOL =1.5V Memory Expansion Mode and Microprocessor Mode BCLK HOLD input HLDA output P0, P1, P2, P3, P4, 0 to P52 RDY input tsu(RDY –BCLK) th(BCLK –RDY) BCLK RD (Multiplexed bus) (Multiplexed bus) WR, WRL, WRH WR, WRL, WRH (Separate bus) RD (Separate bus) Hi–Z th(BCLK –HOLD)tsu(HOLD –BCLK) td(BCLK –HLDA)td(BCLK –HLDA) Vcc1=Vcc2=3.3V

Page 56 65fo5002,10.voN01.1.veR 0110-8300B30JER puorG08/C23M Package Dimensions Terminal cross section bp c DO NOT INCLUDE MOLD FLASH. NOTE) DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. y Index mark x 12 5 5175 100 F ZE ZD E D HD HE bp Detail F A2A1 L A c ZE ZD bp HE HD y 0.08 e 0.5 c 0° 8° x L 0.35 0.5 0.65 0.05 0.1 0.15 A 1.7 15.8 16.0 16.2 15.8 16.0 16.2 A2 1.4 E 13.9 14.0 14.1 D 13.9 14.0 14.1 Reference Symbol Dimension in Millimeters Min Nom Max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 Previous CodeJEITA Package Code RENESAS Code PLQP0100KB-A 100P6Q-A / FP-100U / FP-100UV MASS[Typ.] 0.6gP-LQFP100-14x14-0.50 e Package Dimensions 0.80.5 0.825 0.575 ZE ZD bp HE HD y 0.10 e 0.65 c 0° 10° L 0.4 0.6 0.8 0 0.1 0.2 A 3.05 16.5 16.8 17.1 22.5 22.8 23.1 A 2 2.8 E 13.8 14.0 14.2 D 19.8 20.0 20.2 Reference Symbol Dimension in Millimeters Min Nom Max 0.25 0.3 0.4 0.13 0.15 0.2 P-QFP100-14x20-0.65 1.6g MASS[Typ.] 100P6S-APRQP0100JB-A RENESAS CodeJEITA Package Code Previous Code y Index mark 100 80 51 301 F ZE ZD e bp A HD D E HE c Detail F A1 A2 L INCLUDE TRIM OFFSET. DIMENSION "*3" DOES NOT NOTE) DO NOT INCLUDE MOLD FLASH.

REVISION HISTORY

Rev. Date Description Page Summary M32C/80 Group Datasheet A-1 0.10 Sep., 02 New Document – 0.11 Sep., 02 Table 1.1.1 “CAN ” deleted 3 0.12 Nov., 02 Table 1.1.1 "3.0 to 3.6V (f(XIN)=20MHz without software wait)" deleted "26mA (f(XIN)=20MHz without software wait,Vcc=3.3V)" deleted 1. Overview changed

1.2 Performance Outline changed

1.3 Block Diagram added

1.5 Pin Assignments changed

Table 1.3 Pin Characteristics for 100-Pin Package changed

1.6 Pin Description added

1. Central Processing Unit (CPU) added 3. Memory added 4. Special Function Registers (SFR) added 0.30 Aug., 02 – All pages Words standardized: On-chip oscillator, A/D converter and D/A converter Overview 2, 3 • Table 1.1 and 1.2 M32C/80 Group Performance "When using 16-bit bus" added to I/O ports "Option" deleted from Serial I/O, I2C bus, and IEBus "Voltage Detection Circuit" added Value added to "Power Consumption" "Flash Memory" added 4 • 1.3 Block Diagram Description deleted 5 • Figure 1.2 ROM/RAM Capacity deleted

• Table 1.3 M32C/85 Group Note1 deleted 11 • Table 1.5 Pin Description Note 1 added to I/O ports Memory 23 • Chapter Description modified
• Figure 3.1 Memory Map modified SFR 16- • "X: Nothing is assigned" modified to "X: Indeterminate"
• "?: Indeterminate” modified to "X: Indeterminate"
• "Users cannot use any symbols with *" deleted
• Register names, symbols, value after RESET of addresses 001716, 001B16, 001F16, 002B16, 002F16, 004C16, and 004D16 deleted
• Value after RESET in the PM0 register revised 16 • Note 3 deleted 29 • Note 1 added to addresses 03E016 to 03EB16 0.40 Jun., 04 1.00 Nov., 04

Rev. Date Description Page Summary M32C/80 Group Datasheet A-2

Electrical Characteristics

30- • This capter added All pagesPackage code chnaged: 100P6Q-A to PLQP0100KB-A and 100P6S-A to PRQP0100JB-A Overview 1 • Note that the M32C/80 Group is ROMless device added 2 • Table 1.1 M32C/80 Group Performance Item "HDLC Data Processing" changed to "Intelligent I/O Communication Function"; item "Flash Memory" deleted 3 • Figure 1.1 M32C/80 Group Block Diagram Notes 1 and 2 added 9 • Table 1.4 Pin Description Supply voltage for analog power supply input modi- fied "-" to "VCC1 "; description for CNVSS changed; supply voltage for INT inter- rupt input modified; note for I/O ports added Memory 15 • Figure 3.1 Memory Map Disgram changed; note added Special Function Registers (SFRs) 16 • Note 2 deleted 17 • Values after RESET in the RMAD6 and RMAD7 registers modified 19 • Value after RESET in the RLVL register modified 20 • Value after RESET in the G0RB register modified 21 • Values after RESET in the G0EMR, G0ERC, and G0IRF registers modified 26 • Value after RESET in the TCSPR register modified; note 1 added 27, 28 • Register names, symbols, and value after RESET of addresses 039216 and 03AC 16 deleted 28 • Value after RESET in the PSC register modified 30- • Ports P11 to P15 deleted 32 • Table 5.2 Recpmmended Operating Conditions f(BCLK) standard added 33 • Table 5.3 Electrical Characteristics Max. standard for ICC modified 34 • Table 5.4 A/D Conversion Characteristics AN00 to AN07 deleted from "INL" row 35 • Table 5.7 Memory Expansion Mode and Microprocessor Mode Expressions on note 1 corrected 41 • Figure 5.2 VCC1 =VCC2 =5V Timing Diagram (1) Expression for tcyc added; note 3 corrected 42 • Figure 5.3 VCC1 =VCC2 =5V Timing Diagram (2) Expression for tcyc added; notes 1 and 2 corrected 46 • Table 5.22 A/D Conversion Characteristics Min. standard for VREF modified 47 • Table 5.25 Memory Expansion Mode and Microprocessor Mode Expres- sions on note 1 corrected 52 • Figure 5.6 VCC1 =VCC2 =3.3V Timing Diagram (1) Expression for tcyc added; note 3 corrected 1.10 Nov., 05

Rev. Date Description Page Summary M32C/80 Group Datasheet A-3 53 • Figure 5.7 VCC1 =V CC2 =3.3V Timing Diagram (2) Expression for tcyc added; notes 1 and 2 corrected

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