M30245M8GP

M30245 RENESAS | Alldatasheet

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Features

3.25K programmable FIFO, 9 endpoints Integrated transceiver Conforms to USB V 2.0 Specification 128K ROM / 10K RAM (M30245MC-XXXGP) 128K Flash /10K RAM (M30245FCGP) 4 software interrupt sources 7 levels (including key input interrupt X 8) Configurable for synchronous or asynchronous mode, Serial Sound Interface, I 2C Bus (built-in feedback resistor, and external ceramic or quartz oscillator)

Rev.2.00 Oct 16, 2006 page 2 of 264 M30245 Group Description REJ03B0005-0200 Table of Contents

Rev.2.00 Oct 16, 2006 page 4 of 264 M30245 Group Description REJ03B0005-0200 Performance outline Table 1.1 is a performance outline of the M30245 group. Table 1.1. M30245 Group performance outline Parameters Function Description Number of basic Instructions 91 Shortest Instruction execution time 62.5 ns f(Xin)= 16 MHz, Vcc = 3V Memory size ROM 128/64 Kbytes RAM 10/5 Kbytes Input/Output ports P0 to P8, P10 (excl P85) I/O 8 bits x 10 P85 I 1 bit x 1 Multifunction timer TA0, TA1, TA2, TA3, TA4 16 bits x 5 Serial I/O UART0 to 1 UART (or clock synchronous or Serial Sound Interface) x 2 UART2 to 3 UART (or clock synchronous) x 2 A/D converter 10 bits x 8 channels DMAC 4 channels (31 trigger sources) CRC calculation circuits CRC-CCITT and CRC-16 Watchdog timer 15 bits x 1 (with prescaler) Interrupts 31 internal, 4 external sources, 4 software, 7 levels Clock-generating circuit 2 built-in clock generating circuits (built in feedback resistor, and external ceramic or quartz oscillator) Supply voltage 3.0 ~ 3.6, f(X IN)=16MHz Power consumption 25mA (Vcc=3.3V, f(X IN)=16MHz no division, USB ON) Operating temperature -20 to 85 °C Package 100-pin plastic mold LQFP P9 I/O 4 bits x 1 16mA (Vcc=3.3V, f(XIN)=16MHz no division, USB OFF) AND flash control circuit Communicate with external AND type flash memory

Rev.2.00 Oct 16, 2006 page 6 of 264 M30245 Group Description REJ03B0005-0200 Table 1.2. Pin cross reference Pin No. Control Port Interrupt Timer UART/ USB SPI I2C Serial Sound Interface Analog/ Other Bus Control

1 Vbus DTCT

10 RESET

11 X OUT

12 Vss

14 Vcc

5 NMI

16 P8 4 INT2

17 P8 3 INT1

18 P8 2 INT0

19 P8 1 TA4IN

20 P8 0 TA4OUT

21 P7 7 TA3IN CTS3/RTS3 SS3 LED7

22 P7 6 TA3OUT CLK3 SCK3 LED6

23 P7 5 TA2IN RxD3 STxD3 SCL3 LED5

24 P7 4 TA2OUT TxD3 SRxD3 SDA3 LED4

25 P7 3 TA1IN CTS2/RTS2 SS2 LED3

26 P7 2 TA1OUT CLK2 SCK2 LED2

27 P7 1 TA0IN RxD2 STxD2 SCL2 LED1

28 P7 0 TA0OUT TxD2 SRxD2 SDA2 LED0

29 P6 7 TxD1 SRxD1 SDA1 XMT 1

30 P6 6 RxD1 STxD1 SCL1 RX 1

31 P6 5 CLK1 SCK1 SCK1

32 P6 4 CTS1/RTS1 SS1 WS1

33 P6 3 TxD0 SRxD0 SDA0 XMT 0

34 P6 2 RxD0 STxD0 SCL0 RX 0

35 P6 1 CLK0 SCK0 SCK0

36 P6 0 CTS0/RTS0 SS0 WS0

37 P5 7 RDY

38 P5 6 ALE

39 P5 5 HOLD

40 P5 4 HLDA

41 P5 3 BCLK

42 P5 2 RD

43 P5 1 WRH/BHE

44 P5 0 WRL/WR

45 P4 7 CS3

46 P4 6 CS2

47 P4 5 CS1

48 P4 4 CS0

49 P4 3 A19

50 P4 2 A18

51 P4 1 A17

Rev.2.00 Oct 16, 2006 page 7 of 264 M30245 Group Description REJ03B0005-0200 Table 1.2 Pin cross reference

52 P4 0 A16

53 P3 7 A15

54 P3 6 A14

55 P3 5 A13

56 P3 4 A12

57 P3 3 A11

58 P3 2 A10

59 P3 1 A9

60 Vcc

61 P3 0 A8

62 Vss

63 P2 7 A7

64 P2 6 A6

65 P2 5 A5

66 P2 4 A4

67 P2 3 A3

68 P2 2 A2

69 P2 1 A1

70 P2 0 A0

71 P1 7 D15

72 P1 6 D14

73 P1 5 D13

74 P1 4 D12

75 P1 3 D11

76 P1 2 D10

77 P1 1 D9

78 P1 0 D8

79 P0 7 D7

80 P0 6 D6

81 P0 5 D5

82 P0 4 D4

83 P0 3 D3

84 P0 2 D2

85 P0 1 D1

86 P0 0 D0

87 P10 7 KI7 AN7

88 P10 6 KI6 AN6

89 P10 5 KI5 AN5

90 P10 4 KI4 AN4

91 P10 3 KI3 AN3

92 P10 2 KI2 AN2

93 P10 1 KI1 AN1

94 AVss

95 LPF

96 VREF

97 AVcc

98 P10 0 KI0 AN0

99 P9 3 ADTRG

100 P9 2 SOF

No. Control Port Interrupt Timer UART/ USB SPI I2C Serial Sound Interface Analog/ Other Bus Control AND_SC AND_WE AND_OE AND_DATA7 AND_DATA6 AND_DATA5 AND_DATA4 AND_DATA3 AND_DATA2 AND_DATA1 AND_DATA0

Rev.2.00 Oct 16, 2006 page 8 of 264 M30245 Group Description REJ03B0005-0200 Table 1.3 Pin description With a 16-bit external data bus, data is written to even addresses when the WRL signal is "L", and to the odd addresses when the WRH signal is "L". Data is read when RD is "L". Port Function Pin Name I/O Description Power supply input Vcc 3.0 to 3.6V Vss 0V CPU mode switch CNVss I Connect to Vss: single-chip or memory expansion mode Connect to Vcc: Microprocessor mode only External data bus width select input BYTE I Selects external memory data bus width. Connect to Vss: 16-bit. Connect to Vcc: 8-bit. Reset input RESET I "L" resets the microcomputer. Clock input X IN I These pins support the main clock generating circuit. Connect a crystal between the XIN and XOUT pins. To use an external clock, input it to the XIN pin and leave the XOUT pin open. Clock output X OUT O Analog power supply input AVcc Connect to Vcc. AVss Connect to Vss. Reference voltage input V REF I This is a reference voltage for A/D converter. Low pass filter LPF O Loop filter for the frequency synthesizer circuit. USB power supply input UVcc Power pin for USB Vbus detect VbusDTCT I Detects USB host power USB D+ USB D+ I/O USB D+ voltage line interface USB D- USB D- I/O USB D- voltage line interface P0 I/O port P0 0 to P07 I/O This is an 8-bit CMOS I/O port. The input/output port direction register allows each pin to be set individually. When used for input, the port can be set to include internal pull-up resistors in 4-pin blocks. Data bus D 0 to D7 I/O These pins input and output 8 low-order data bits when set as a separate bus. P1 I/O port P1 0 to P17 I/O This is an 8-bit I/O port equivalent to P0. Data bus D 8 to D15 I/O These pins input and output 8 high-order data bits when set as a separate bus. P2 I/O port P2 0 to P27 I/O This is an 8-bit I/O port equivalent to P0. Address bus A 0 to A7 O These pins output 8 low-order address bits. P3 I/O port P3 0 to P37 I/O This is an 8-bit I/O port equivalent to P0. Address bus A 8 to A15 O These pins output 8 middle-order address bits. P4 I/O port P4 0 to P47 I/O This is an 8-bit I/O port equivalent to P0. Address bus A 16 to A19 O These pins output 4 high-order address bits. Chip select CS0 to CS3 OP 4 4 to P47 are chip select output pins that specify access areas. P5 I/O port P5 0 to P57 I/O This is an 8-bit I/O port equivalent to P0. Bus control WRL/WR O Ouput WRL, WRH (WR, BHE), and RD bus control signals. Using WRL and WRH or WR and BHE can be switched using software control. WRL, WRH, and RD selected. WR, BHE, and RD selected. Data is written when WR is "L". Data is read when RD is "L". Odd addresses are accessed when BHE is "L". Use this mode when using an 8-bit external data bus. WRH/BHE O RD O BCLK O Output operation clock for the CPU. HOLD I While the HOLD pin input is "L", the MCU is placed in the Hold state. HLDA O The HLDA pin output is "L" while the MCU is in the hold state. ALE O The ALE pin can be used to latch the address. RDY I While the RDY pin input is "L", the MCU is in the ready state. AND Flash control AND_SC AND_WE AND_OE O Control signal pins for communicating with AND type flash memory devices AND Flash control AND_DATA0 to 7 I/O Data pins for communicating with AND type flash memory devices

Rev.2.00 Oct 16, 2006 page 9 of 264 M30245 Group Description REJ03B0005-0200 Table 1.3 Pin description P6 I/O port P6 0 to P67 I/O This is an 8-bit I/O port equivalent to P0. UART/SSI CTS/RTS/SS/WS CLK/SCK RxD/SCL/STxD/RX TxD/SDA/SRxD/XMT I/O P6 0 to P63 are I/O ports for UART0. P64 to P67 are I/O ports for UART1. These pins can be used for Serial Sound Interface, I 2C and SPI communication. P7 I/ P7 0 to P77 I/O This is an 8-bit I/O port equivalent to P0. P7 0 and P71 are N-channel open drain output. Timer A TA IN IP 7 0 to P77 are I/O ports for Timer A0 to A3. TAOUT O UART CTS/RTS/SS/WS CLK/SCK RxD/SCL/STxD TxD/SDA/SRxD 0 to P73 are I/O ports for UART2. P74 to P77 are I/O ports for UART3. These pins can be used for I 2C and SPI communication. LED drive LED 0 to LED 7 O These pins are capable of sinking 20mA for driving LEDs. External interrupt input INT0 to INT2 IP 8 2 to P84 are external interrupt input ports. Input P85/NMI I Input port for NMI interrupt. P9 I/O port P9 0, P 92, P 93 I/O This is a 3-bit I/O port equivalent to P0. A/D AD TRG IP 9 3 is an A/D trigger input port. USB-ATTACH ATTACH O P9 0 can be used to attach or detach from the USB host without disconnecting the USB cable. USB SOF SOF O P92 is an output for the USB start of frame signal pulse. P10 I/O port P10 0 to P107 I/O This is an 8-bit I/O port equivalent to P0. Key-input interrupt KI 0 to KI7 I P10 0 to P107 are key-input interrupt ports. Analog input AN 0 to AN7 I P10 0 to P107 are analog input ports for A/D converter. Port Function Pin Name I/O Description I/OI/O port P80 to P84, P 86, P87 This is a 7-bit I/O port equivalent to P0. XCIN, XCOUT P86 and P87 , connect an oscillator between these pins for sub-clock generation. I/O I, OSub-Clock O port

Rev.2.00 Oct 16, 2006 page 11 of 264 M30245 Group Description REJ03B0005-0200 USB Overview The M30245 group is a single-chip PC peripheral microcontroller that is compliant with the Universal Serial Bus (USB) Version 2.0 specification for full-speed USB operation (12Mbps). This device provides an interface between a USB- equipped host computer and PC peripherals such as telephones, audio systems, and digital cameras. The M30245 architectural overview is shown in Figure 1.4. The USB function control unit of the M30245 group supports full-speed operation and all four data transfer types listed in the USB specification. Each transfer type is used for controlling a different set of PC peripherals.

• Isochronous transfers provide guaranteed bus access, a constant data rate, and error tolerance for devices such as computer-telephone integration (CTI) and audio systems.
• Interrupt transfers are designed to support human input devices (HID) that communicate small amounts of data infrequently.
• Bulk transfers are necessary for devices such as digital cameras and scanners that communicate large amounts of data to the PC as bus bandwidth becomes free.
• Control transfers are supported and are useful for bursty, host-initiated type communication where bus manage- ment is the primary concern. Figure 1.4. M30245 architectural overview frequency RAM DMAC x 4 M16C CPU UART x 4 Timers x 5 Watchdog CRC Circuit I/O Ports (P0 to P10) FIFOs USB Function Control Unit Transceiver (Normal MCU or DMA Transfer) 1 - 16MHz

48 MHzsynthesizer

(X 8) A/D Converter Timer ROM

M30245 Group Central Processing Unit Rev.2.00 Oct 16, 2006 page 13 of 264 REJ03B0005-0200 Central Processing Unit The CPU has a total of 13 registers shown in Figure 1.6. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks. Figure 1.6. Central processing unit register Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3) Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32-bit data registers (R2R0/R3R1). Address registers (A0 and A1) Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). Frame base register (FB) Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing. H L b15 b8 b7 b0 R0(Note) H L b15 b8 b7 b0 R1(Note) R2(Note) b15 b0 R3(Note) b15 b0 A0(Note) b15 b0 A1(Note) b15 b0 FB(Note) b15 b0 Data registers Address registers Frame base registers b15 b0 b15 b0 b15 b0 b15 b0 b0 b19 b0 b19 HL Program counter Interrupt table register User stack pointer Interrupt stack pointer Static base register Flag register PC INTB USP ISP SB FLG Note: These registers consist of two register banks. CDZSBOIUIPL

M30245 Group Central Processing Unit Rev.2.00 Oct 16, 2006 page 14 of 264 REJ03B0005-0200 Program counter (PC) Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed. Interrupt table register (INTB) Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table. Stack pointer (USP/ISP) The stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits. The desired type of stack pointer (USP or ISP) can be selected by the stack pointer select flag (U flag). This flag is located at bit 7 of the flag register (FLG). Static base register (SB) Static base register (SB) is configured with 16 bits, and is used for SB relative addressing. Flag register (FLG) Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.7 shows the flag register (FLG). The following explains the function of each flag:

• Bit 0: Carry flag (C flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag) This flag enables a single-step interrupt. When this flag is "1", a single-step interrupt is generated after instruction execution. This flag is cleared to "0" when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag) This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, cleared to "0".
• Bit 3: Sign flag (S flag) This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, cleared to "0".
• Bit 4: Register bank select flag (B flag) This flag chooses a register bank. Register bank 0 is selected when this flag is "0"; register bank 1 is selected when this flag is "1".
• Bit 5: Overflow flag (O flag) This flag is set to "1" when an arithmetic operation resulted in overflow; otherwise, cleared to "0".
• Bit 6: Interrupt enable flag (I flag) This flag enables all maskable interrupts. Interrupts are disabled when this flag is "0", and are enabled when this flag is "1". This flag is cleared to "0" when an interrupt is acknowledged.

M30245 Group Central Processing Unit Rev.2.00 Oct 16, 2006 page 15 of 264 REJ03B0005-0200

• Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is "0"; user stack pointer (USP) is selected when this flag is "1". This flag is cleared to "0" when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight proces- sor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled.
• Bit 15: Reserved area The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details. Figure 1.7. Flag register Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority Flag register (FLG)CDZSBOIUIPL b0b15 Reserved area

Rev.2.00 Oct 16, 2006 page 17 of 264 REJ03B0005-0200 Figure 1.9. Reset sequence Table 1.5. Pin status when RESET pin level is "L" BCLK Address Address Address Microprocessor mode BYTE = “H” Microprocessor mode BYTE = “L” Content of reset vectorSingle chip mode BCLK 24cycles FFFFC16 FFFFD16 FFFFE16 Content of reset vector FFFFC16 FFFFE16 Content of reset vector FFFFE16 XIN RESET RD WR CS0 RD WR CS0 FFFFC16 More than 20 cycles are needed Pin name Status CNVss=Vss CNVss=Vcc BYTE=Vss BYTE=Vcc P0 Input port (floating) Data input (floating) Data input (floating) P1 Input port (floating) Data input (floating) Input port (floating) P2, P3, P40 to P43 Input port (floating) Address output (undefined) Address output (undefined) P44 Input port (floating) CS0 output (“H” level is output) CS0 output (“H” level is output) P45 to P47 Input port (floating) Input port (floating) (pull-up resistor is on) Input port (floating) (pull-up resistor is on)

0 Input port (floating) WR output (”H” level is output) WR output (”H” level is output)

P51 Input port (floating) BHE output (undefined) BHE output (undefined) P52 Input port (floating) RD output (“H” level is output) RD output (“H” level is output) P53 Input port (floating) BCLK output BCLK output P54 Input port (floating) HLDA output (The output value depends on the input to the HOLD pin) HLDA output (The output value depends on the input to the HOLD pin) P55 Input port (floating) HOLD input (floating) HOLD input (floating) P56 Input port (floating) ALE output (“L” level is output) ALE output (“L” level is output) P57 Input port (floating) RDY input (floating) RDY input (floating) P6, P7, P80 to P84, P86, P87, P9, P10 Input port (floating) Input port (floating) Input port (floating)

M30245 Group S pecial Function Registers Rev.2.00 Oct 16, 2006 page 18 of 264 REJ03B0005-0200 Special Function Registers Tables 1.6 to 1.13 show the peripheral control registers, their addresses, names, acronyms, and values after reset. Table 1.6. SFR Map (1) Address Register name Acronym Value after reset 000016 000116 000216 000316

000416 Processor mode register 0 (Note 3) PM0 0016

000516 Processor mode register 1 PM1 0 0 0

000616 System clock control register 0 CM0 4816

000716 System clock control register 1 CM1 2016

000816 C S R 00000001

000916 Address match interrupt enable register AIER 00

000A16 Protect register PRCR 000 000B16 000C16 USB control register USBC 0016 000D16 000E16 Watchdog timer start register WDTS 000F16 Watchdog timer control register WDC 000????? 001016 Address match interrupt register 0 RMAD0 0016 001116 0016 001216 0000 001316 001416 Address match interrupt register 1 RMAD1 0016 001516 0016 001616 0000 001716 001816 001916 001A16 001B16 Chip select expansion register CSE 0016 001C16 001D16 001E16 Reserved 001F16 USB Attach/Detach register USBAD 0016 002016 DMA0 source pointer SAR0002116 002216 002316 002416 DMA0 destination pointer DAR0002516 002616 002716

002816 DMA0 transfer counter TCR0002916

002C16 DM0CON 00000?00 002D16 002E16 002F16 003016 DMA1 source pointer SAR1003116 003216 003316 003416 DMA1 destination pointer DAR1003516 003616 003716

003816 DMA1 transfer counter TCR1003916

003C16 DM1CON 00000?00 Chip select control register DMA0 control register DMA1 control register Note 1: The contents of other registers and RAM is undefined when the microcomputer is reset. The initial value must therefore be set. Note 2: Locations in the SFR area where nothing is assigned are reserved areas. Do not access these areas for read or write. Note 3: For hardware reset, when Vcc is applied to the CNVss pin, it is 0316 at reset. For software reset, the contents of bit 0 and 1 are preserved as before the reset. ? : Undefined : Nothing is mapped to this bit

M30245 Group S pecial Function Registers Rev.2.00 Oct 16, 2006 page 19 of 264 REJ03B0005-0200 Table 1.7. SFR Map (2) Address Register name Acronym Value after reset 004016 004116 Key input interrupt control register KUPIC ?000 004216 UART2 receive/ACK interrupt control register S2RIC ?000 004316 UART1/3 Bus collision interrupt control register S13BCNIC ?000 004416 INT1 interrupt control register INT1IC 00?000 Polarity 004516 Timer A1 interrupt control register TA1IC ?000 004616 USB Endpoint 0 interrupt control register EP0IC ?000 004716 Timer A2 interrupt control register TA2IC ?000 004816 UART1 receive/ACK/SSI1 interrupt control register S1RIC 00?000 Polarity 004916 UART0/2 Bus collision interrupt control register S02BCNIC 00?000 Polarity 004A16 UART0 receive/ACK/SSI0 interrupt control register S0RIC ?000 004B16 AD conversion interrupt control register ADIC ?000 004C16 DMA0 interrupt conrol register DM0IC ?000 004D16 UART3 transmit/NACK interrupt control register S3TIC ?000 004E16 DMA1 interrupt control register DM1IC ?000 004F16 UART2 transmit/NACK interrupt control register S2TIC ?000 005016 DMA2 interrupt control register DM2IC ?000 005116 UART1 transmit/NACK/SSI1 interrupt control register S1TIC ?000 005216 DMA3 interrupt control register DM3IC ?000 005316 UART0 transmit/NACK/SSI0 interrupt control register S0TIC ?000 005416 Timer A0 interrupt control register TA0IC ?000 005516 UART3 receive/ACK interrupt control register S3RIC ?000 005616 USB suspend interrupt control register SUSPIC ?000 005716 Timer A3 interrupt control register TA3IC ?000 005816 USB resume interrupt control register RSMIC ?000 005916 Timer A4 interrupt control register TA4IC ?000 005A16 USB reset interrupt control register RSTIC ?000 005B16 USB SOF interrupt control register SOFIC ?000 005C16 USB Vbus detect interrupt control register VBDIC ?000 005D16 USB function interrupt control register USBFIC ?000 005E16 INT2 interrupt control register INT2IC 00?000 Polarity 005F16 INT0 interrupt control register INT0IC 00?000 Polarity 018016 DMA2 source pointer SAR2018116 018216 018316 018416 DMA2 destination pointer DAR2018516 018616 018716

018816 DMA2 transfer counter TCR2018916

018C16 DM2CON 00000?00 018D16 018E16 018F16 019016 DMA3 source pointer SAR3019116 019216 019316 019416 DMA3 destination pointer DAR3019516 019616 019716

019816 DMA3 transfer counter TCR3019916

019C16 DM3CON 00000?00 019D16 019E16 019F16 DMA2 control register DMA3 control register Note 1: The contents of other registers and RAM is undefined when the microcomputer is reset. The initial value must therefore be set. Note 2: Locations in the SFR area where nothing is assigned are reserved areas. Do not access these areas for read or write. ? : Undefined : Nothing is mapped to this bit

M30245 Group S pecial Function Registers Rev.2.00 Oct 16, 2006 page 20 of 264 REJ03B0005-0200 Table 1.8. SFR Map (3) Address Register name Acronym Value after reset

028016 USB address register USBA 000016028116

028216 USB power management register USBPM 000016028316

028416 USB interrupt status register USBIS 000016028516

028616 USB interrupt clear register USBIC 000016028716

028816 USB interrupt enable register USBIE 01FF16028916

028A16 USB frame number register USBFN 000016028B16 028C16 USB ISO control register USBISOC 000016028D16 028E16 USB endpoint enable register USBEPEN 000016028F16

029016 USB DMA0 request register USBDMA0 000016029116

029216 USB DMA1 request register USBDMA1 000016029316

029416 USB DMA2 request register USBDMA2 000016029516

029616 USB DMA3 request register USBDMA3 000016029716

029816 USB EP0 control/status register EP0CS 200016029916

029A16 USB EP0 max packet size register EP0MP 000816029B16 029C16 USB EP0 write count register EP0WC 000016029D16 029E16 USB EP1 IN control/status register EP1ICS 000316029F16 02A016 USB EP1 IN max packet size register EP1IMP 00001602A116 02A216 USB EP1 IN FIFO configuration register EP1IFC 00001602A316 02A416 USB EP2 IN control/status register EP2ICS 00031602A516 02A616 USB EP2 IN max packet size register EP2IMP 00001602A716 02A816 USB EP2 IN FIFO configuration register EP2IFC 00001602A916 02AA16 USB EP3 IN control/status register EP3ICS 00031602AB16 02AC16 USB EP3 IN max packet size register EP3IMP 00001602AD16 02AE16 USB EP3 IN FIFO configuration register EP3IFC 00001602AF16 02B016 USB EP4 IN control/status register EP4ICS 00031602B116 02B216 USB EP4 IN max packet size register EP4IMP 00001602B316 02B416 USB EP4 IN FIFO configuration register EP4IFC 00001602B516 02B616 USB EP1 OUT control/status register EP1OCS 00001602B716 02B816 USB EP1 OUT max packet size register EP1OMP 00001602B916 02BA16 USB EP1 OUT write count register EP1WC 00001602BB16 02BC16 USB EP1 OUT FIFO configuration register EP1OFC 00001602BD16 02BE16 USB EP2 OUT control /status register EP2OCS 00001602BF16 Note 1: The contents of other registers and RAM is undefined when the microcomputer is reset. The initial value must therefore be set. Note 2: Locations in the SFR area where nothing is assigned are reserved areas. Do not access these areas for read or write.

M30245 Group S pecial Function Registers Rev.2.00 Oct 16, 2006 page 21 of 264 REJ03B0005-0200 Table 1.9. SFR Map (4) Address Register name Acronym Value after reset 02C016 USB EP2 OUT max packet size register EP2OMP 00001602C116 02C216 USB EP2 OUT write count register EP2WC 00001602C316 02C416 USB EP2 OUT FIFO configuration register EP2OFC 00001602C516 02C616 USB EP3 OUT control/status register EP3OCS 00001602C716 02C816 USB EP3 OUT max packet size register EP3OMP 00001602C916 02CA16 USB EP3 OUT write count register EP3WC 00001602CB16 02CC16 USB EP3 OUT FIFO configuration register EP3OFC 00001602CD16 02CE16 USB EP4 OUT control/status register EP4OCS 00001602CF16 02D016 USB EP4 OUT max packet size register EP4OMP 00001602D116 02D216 USB EP4 OUT write count register EP4WC 00001602D316 02D416 USB EP4 OUT FIFO configuration register EP4OFC 00001602D516 02D616 02D716 02D816 USB reserved 02D916 USB reserved 02DA16 USB reserved 02DB16 USB reserved 02DC16 USB reserved 02DD16 USB reserved 02DE16 USB reserved 02DF16 USB reserved 02E016 USB EP0 IN FIFO EP0I02E116 02E216 USB EP0 OUT FIFO EP0O02E316 02E416 USB EP1 IN FIFO EP1I02E516 02E616 USB EP1 OUT FIFO EP1O02E716 02E816 USB EP2 IN FIFO EP2I02E916 02EA16 USB EP2 OUT FIFO EP2O02EB16 02EC16 USB EP3 IN FIFO EP3I02ED16 02EE16 USB EP3 OUT FIFO EP3O02EF16 02F016 USB EP4 IN FIFO EP4I02F116 02F216 USB EP4 OUT FIFO EP4O02F316 02F416 02F516 02F616 02F716 Flash memory control register 0 (Note 3) FMR0 0116 02F816 02F916 02FA16 02FB16 02FC16 02FD16 02FE16 02FF16 Note 1: The contents of other registers and RAM is undefined when the microcomputer is reset. The initial value must therefore be set. Note 2: Locations in the SFR area where nothing is assigned are reserved areas. Do not access these areas for read or write. Note 3: This register exists only in the flash memory version. Reserved Reserved

M30245 Group S pecial Function Registers Rev.2.00 Oct 16, 2006 page 22 of 264 REJ03B0005-0200 Table 1.10. SFR Map (5) Address Register name Acronym Value after reset 030016 030116 030216 030316 030416 030516 030616 030716 030816 030916 030A16 030B16 030C16 030D16 030E16 030F16

031016 Serial Sound Interface 0 mode register 0 SSI0MR0 0016

031116 Serial Sound Interface 0 mode register 1 SSI0MR1 0016

031216 Reserved

031316 Reserved

031416 Serial Sound Interface 0 transmit buffer register SSI0TXB 000016031516

031616 Serial Sound Interface 0 receive buffer register SSI0RXB 000016031716

031816 Serial Sound Interface 0 rate feedback register SSI0RF 000016031916

032416 UART3 special mode register 4 U3SMR4 0016

032516 UART3 special mode register 3 U3SMR3 0016

032616 UART3 special mode register 2 U3SMR2 0016

032716 UART3 special mode register U3SMR 0016

032816 UART3 transmit / receive mode register U3MR 0016

032916 UART3 bit rate generator U3BRG

032A16 UART3 transmit buffer register U3TB032B16 032C16 UART3 transmit / receive control register 0 U3C0 0816 032D16 UART3 transmit / receive control register 1 U3C1 0216 032E16 UART3 receive buffer register U3RB032F16 033016 033116 033216 033316

033416 UART2 special mode register 4 U2SMR4 0016

033516 UART2 special mode register 3 U2SMR3 0016

033616 UART2 special mode register 2 U2SMR2 0016

033716 UART2 special mode register U2SMR 0016

033816 UART2 transmit / receive mode register U2MR 0016

033916 UART2 bit rate generator U2BRG

033A16 UART2 transmit buffer register U2TB033B16 033C16 UART2 transmit / receive control register 0 U2C0 0816 033D16 UART2 transmit / receive control register 1 U2C1 0216 033E16 UART2 receive buffer register U2RB033F16 Note 1: The contents of other registers and RAM is undefined when the microcomputer is reset. The initial value must therefore be set. Note 2: Locations in the SFR area where nothing is assigned are reserved areas. Do not access these areas for read or write.

M30245 Group S pecial Function Registers Rev.2.00 Oct 16, 2006 page 23 of 264 REJ03B0005-0200 Table 1.11. SFR Map (6) Address Register name Acronym Value after reset 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 Interrupt cause select register IFSR 0016 036016 036116 036216 036316

036416 UART1 special mode register 4 U1SMR4 0016

036516 UART1 special mode register 3 U1SMR3 0016

036616 UART1 special mode register 2 U1SMR2 0016

036716 UART1 special mode register U1SMR 0016

036816 UART1 transmit / receive mode register U1MR 0016

036916 UART1 bit rate generator U1BRG

036A16 UART1 transmit buffer register U1TB036B16 036C16 UART1 transmit / receive control register 0 U1C0 0816 036D16 UART1 transmit / receive control register 1 U1C1 0216 036E16 UART1 receive buffer register U1RB036F16

037016 Serial Sound Interface 1 mode register 0 SSI1MR0 0016

037116 Serial Sound Interface 1 mode register 1 SSI1MR1 0016

037216 Reserved

037316 Reserved

037416 Serial Sound Interface 1 transmit buffer register SSI1TXB 000016037516

037616 Serial Sound Interface 1 receive buffer register SSI1RXB 000016037716

037816 Serial Sound Interface 1 rate feedback register SSI1RF‘ 000016037916

Note 1: The contents of other registers and RAM is undefined when the microcomputer is reset. The initial value must therefore be set. Note 2: Locations in the SFR area where nothing is assigned are reserved areas. Do not access these areas for read or write.

M30245 Group S pecial Function Registers Rev.2.00 Oct 16, 2006 page 24 of 264 REJ03B0005-0200 Table 1.12. SFR Map (7) Address Register name Acronym Value after reset

038016 Count start flag TABSR 00000

038116 Clock prescaler reset flag CPSRF 0

038216 One-shot start flag ONSF 0 0 00000

038316 Trigger select register TRGSR 0016

038416 Up-down flag UDF 0016

038616 Timer A0 TA0038716

038816 Timer A1 TA1038916

039616 Timer A0 mode register TA0MR 0016

039716 Timer A1 mode register TA1MR 0016

039816 Timer A2 mode register TA2MR 0016

039916 Timer A3 mode register TA3MR 0016

039A16 Timer A4 mode register TA4MR 0016 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 UART0 special mode register 4 U0SMR4 0016 03A516 UART0 special mode register 3 U0SMR3 0016 03A616 UART0 special mode register 2 U0SMR2 0016 03A716 UART0 special mode register U0SMR 0016 03A816 UART0 transmit / receive mode register U0MR 0016 03A916 UART0 bit rate generator U0BRG 03AA16 UART0 transmit buffer register U0TB03AB16 03AC16 UART0 transmit / receive control register 0 U0C0 0816 03AD16 UART0 transmit / receive control register 1 U0C1 0216 03AE16 UART0 receive buffer register U0RB03AF16 03B016 DMA2 cause select register DM2SL 0016 03B116 03B216 DMA3 cause select register DM3SL 0016 03B316 03B416 CRC snoop address register CRCSAR03B516 03B616 CRC mode register CRCMR 0 0 03B716 03B816 DMA0 cause select register DM0SL 0016 03B916 03BA16 DMA1 cause select register DM1SL 0016 03BB16 03BC16 CRC data register CRCD03BD16 03BE16 CRC input register CRCIN 03BF16 Note 1: The contents of other registers and RAM is undefined when the microcomputer is reset. The initial value must therefore be set. Note 2: Locations in the SFR area where nothing is assigned are reserved areas. Do not access these areas for read or write. ? : Undefined : Nothing is mapped to this bit ??00

M30245 Group S pecial Function Registers Rev.2.00 Oct 16, 2006 page 25 of 264 REJ03B0005-0200 Table 1.13. SFR Map (8) Address Register name Acronym Value after reset 03C016 AD register 0 AD003C116 03C216 AD register 1 AD103C316 03C416 AD register 2 AD203C516 03C616 AD register 3 AD303C716 03C816 AD register 4 AD403C916 03CA16 AD register 5 AD503CB16 03CC16 AD register 6 AD603CD16 03CE16 AD register 7 AD703CF16 03D016 03D116 03D216 03D316 03D416 AD control register 2 ADCON2 0 03D516 03D616 A D C O N 0 00000??? 03D716 AD conrol register 1 ADCON1 0016 03D816 03D916 03DA16 03DB16 Frequency synthesizer clock control FSCCR 0016 03DC16 Frequency synthesizer control FSC 6016 03DD16 Frequency synthesizer multiplier control FSM FF16 03DE16 Frequency synthesizer prescaler control FSP FF16 03DF16 Frequency synthesizer divider FSD FF16 03E016 Port P0 P0 03E116 Port P1 P1 03E216 Port P0 direction register PD0 0016 03E316 Port P1 direction register PD1 0016 03E416 Port P2 P2 03E516 Port P3 P3 03E616 Port P2 direction register PD2 0016 03E716 Port P3 direction register PD3 0016 03E816 Port P4 P4 03E916 Port P5 P5 03EA16 Port P4 direction register PD4 0016 03EB16 Port P5 direction register PD5 0016 03EC16 Port P6 P6 03ED16 Port P7 P7 03EE16 Port P6 direction register PD6 0016 03EF16 Port P7 direction register PD7 0016 03F016 Port P8 P8 03F116 Port P9 P9 00 0 03F216 Port P8 direction register PD8 0 0 00000 03F316 Port P9 direction register PD9 00 0 03F416 Port P10 P10 03F516 03F616 Port P10 direction register PD10 0016 03F716 03F816 03F916 Key-input mode register KUPM 0016 03FA16 P7 drive capacity P7DR 0016 03FB16 03FC16 Pull-up control register 0 PUR0 0016 03FD16 Pull-up control register 1 (Note 3) PUR1 0016 03FE16 Pull-up control register 2 PUR2 00 000 03FF16 Port control register PCR 0 AD conrol register 0 Note 1: The contents of other registers and RAM is undefined when the microcomputer is reset. The initial value must therefore be set. Note 2: Locations in the SFR area where nothing is assigned are reserved areas. Do not access these areas for read or write. Note 3: For hardware reset, when Vcc is applied to the CNVss pin, it is 0216 at reset. For a software reset, if bit 1 and bit 0 of the processor mode register 0 (address 000416) are [102] or [112], then it becomes 0216 at a reset. ? : Undefined : Nothing is mapped to this bit

M30245 Group Processor Mode Rev.2.00 Oct 16, 2006 page 26 of 264 REJ03B0005-0200 Processor Modes One of three processor modes can be selected: single-chip mode, memory expansion mode, and microprocessor mode. The functions of some pins, the memory map, and the access space differ according to the selected processor mode. Figure 1.10 shows the processor mode register 0 and 1.

• Single-chip mode In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be accessed. However, if microprocessor mode is set ("H" applied to the CNVss pin) when coming out of reset, the internal ROM cannot be accessed even if the CPU shifts to single-chip mode. Ports P0 to P10 can be used as programmable I/O ports or I/O ports for the internal peripheral functions.
• Memory expansion mode In memory expansion mode, external memory can be accessed in addition to the internal memory space (SFR, internal RAM, and internal ROM). However, if microprocessor mode is set ("H" applied to CNVss pin) when coming out of a reset, the internal ROM cannot be accessed even if the CPU shifts to memory expansion mode. In memory expansion mode, some of the pins function as the address bus, the data bus, and as control signals. The number of pins assigned to these functions depends on the bus and register settings. (See "Bus Settings"for details.)
• Microprocessor mode In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. However, the internal ROM area cannot be accessed. In this mode, some of the pins function as the address bus, the data bus, and as control signals. The number of pins assigned to these functions depends on the bus and register settings. (See "Bus Settings" for details). Setting Processor Modes The processor mode is set using the CNVss pin and the processor mode bits (bits 1 and 0 at address 0004 16). Do not set the processor mode bits t o "10 2". Regardless of the level of the CNVss pin, changing the processor mode bits selects the mode. However, the processor mode bits cannot be changed to "01 2" (memory expansion mode) or "11 2" (microprocessor mode) at the same time the PM07-PM02 bits are rewritten. Also do not attempt to change to or from microprocessor mode within the program stored in the internal ROM area.
• Applying Vss to CNVss pin The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode is selected by writing "01 2" to the processor mode bits in the Processor Mode register 0 (0004 16).
• Applying Vcc to CNVss pin The microcomputer starts to operate in microprocessor mode after being reset. Figure 1.11 shows the applicable memory maps for each mode. Figure 1.12 shows the memory maps and chip-select areas in normal mode.

M30245 Group Processor Mode Rev.2.00 Oct 16, 2006 page 27 of 264 REJ03B0005-0200 Figure 1.10. Processor mode register 0 and 1 Processor mode register 0 (Note 1) Symbol Address When reset PM0 0004 16 0016 (Note 2) Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 0 0: Single-chip mode 0 1: Memory expansion mode 1 0: Inhibited 1 1: Microprocessor mode b1 b0 PM03 PM01 PM00 Processor mode bit PM02 R/W mode select bit 0: RD,BHE,WR 1: RD,WRH,WRL Software reset bit The device is reset when this bit is set to "1". The value of this bit is "0" when read. PM04 PM05 PM06 PM07 Port P40 to P43 function select bit (Note 3) 0 : Address output 1 : Port function (Address is not output) BCLK output disable bit 0 : BCLK is output 1 : BCLK is not output (Pin is left floating) Note 1: Set bit 1 of the protect register (address 000A 16) to "1" before writing new values to this register. Note 2: For hardware reset: If VCC voltage is applied to the CNVSS pin, the value of this register when reset is 0316. (PM00 and PM01 are both set to "1".) For software reset: the value of PM00 and PM01 are preserved as before the reset. Note 3: Valid in microprocessor and memory expansion modes. Processor mode register 1 (Note 1) Symbol Address When reset PM1 0005 16 00000XX02 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 Reserved bit Must always be set to "0" Note 1: Set bit 1 of the protect register (address 000A16) to "1" before writing new values to this register. Reserved bit Must always be set to "0" Reserved bit Must always be set to "0" 000 O O O O O O Nothing is assigned. Write "0" when writing to these bits. The value is indeterminate if read. Reserved Must always be set to "0" 0 0 PM16 WR length control bit 0 : Normal 1 : Extended O O

M30245 Group Processor Mode Rev.2.00 Oct 16, 2006 page 29 of 264 REJ03B0005-0200 Selecting external address bus width The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K bytes address space) or 20 bits (1M bytes address space). When bit 6 of the processor mode register 0 is set to "1", the external address bus width is set to 16 bits, and P2 and P3 become part of the address bus. P4 0 to P43 can be used as programmable I/O ports. When bit 6 of processor mode register 0 is set to "0", the external address bus width is set to 20 bits, and P2, P3, and P4 0 to P43 become part of the address bus. Selecting external data bus width The external data bus width can be set to 8 or 16 bits. When the BYTE pin is "L", the bus width is set to 16 bits; when "H", it is set to 8 bits. (The internal bus width is permanently set to 16 bits.) While operating, fix the BYTE pin either to "H" or to "L". When the BYTE pin is "H", the data bus is set to 8 bits and P0 functions as the data bus and P1 as a programmable I/O port. When the BYTE pin is "L", the data bus is set to 16 bits and P0 and P1 are both used for the data bus. A software wait can also be added. Table 1.15. Pin functions for each processor mode Processor mode Single-chip mode Memory expansion mode/microprocessor mode Data bus width BYTE = "H" 16 bits BYTE = "L" P00 to P07 I/O port Data bus Data bus P10 to P17 I/O port I/O port Data bus P20 I/O port Address bus Address bus P21 to P27 I/O port Address bus Address bus P30 I/O port Address bus Address bus P31 to P37 I/O port Address bus Address bus P40 to P43 (function select bit =1) I/O port I/O port I/O port P40 to P43 (function select bit =0) I/O port Address bus Address bus P44 to P47 I/O port CS (chip select) or programmable I/O port (Refer to "Bus control" for details) P50 to P53 I/O port Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR and BCLK (Refer to "Bus control" for details) P54 I/O port HLDA HLDA P55 I/O port HOLD HOLD P56 I/O port ALE ALE P57 I/O port RDY RDY

M30245 Group Processor Mode Rev.2.00 Oct 16, 2006 page 31 of 264 REJ03B0005-0200 Table 1.16. External areas specified by the chip select signals Read/write signals With a 16-bit data bus (BYTE pin ="L"), bit 2 of the processor mode register 0 (address 0004 16) selects the combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus (BYTE pin = "H"), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0 (address 000416) to "0".) Tables 1.17 and 1.18 show the operation of these signals. After a reset, the combination of RD, WRR, and BHE signals is automatically selected. When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the processor mode register 0 (address 0004 16) has been set . Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register (address 000A 16) to "1". Table 1.17. Operation of RD, WRL, and WRH signals Table 1.18. Operation of RD, WR, and BHE signals Processor mode Chip-select signal CS0 CS1 CS2 CS3 Memory expansion mode 3000016 to CFFFF16 (640 Kbytes) 2800016 to 2FFFF16 (32 Kbytes) 0800016 to 27FFF16 (128 Kbytes) 0400016 to 07FFF16 (16 Kbytes)Microprocessor mode 30000 16 to FFFFF16 (832 Kbytes) Data bus wid th RD WRL WRH External data bus status 16-bit (BYTE = "L") L H H Read data H L H Write 1 byte of data to even address H H L Write 1 byte of data to odd address H L L Write data to both even and odd addresses Data bus wid th RD WRL BHE A0 External data bus status 16-bit (BYTE = “L”) H L L H Write 1 byte of data to odd address L H L H Read 1 byte of data from odd address H L H L Write 1 byte of data to even address L H H L Read 1 byte of data from even address H L L L Write data from both even and odd addresses L H L L Read data from both even and odd addresses 8-bit (BYTE = “H”) H L Not used H/L Write 1 byte of data L H Not used H/L Read 1 byte of data

M30245 Group Processor Mode Rev.2.00 Oct 16, 2006 page 32 of 264 REJ03B0005-0200 The ALE signal The ALE signal can be used by an external device to latch the address from the address bus. This signal indicates when the address on the bus is valid. Latch the address when the ALE signal falls. The RDY signal RDY is a signal that facilitates access to an external device that requires long access time. As shown in Figure 1.14, if an "L" is input to the RDY at the BCLK falling edge, the bus turns to the wait state. If an "H" is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state. Table 1.19 shows the state of the microcomputer with the bus in the wait state. Figure 1.15 is an example of the RD signal prolonged by the RDY signal. The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of the chip select control register (address 0008 16) are set to "0". The RDY signal is invalid when setting "1" to all bits 4 to 7 of the chip select control register (address 0008 16), but the RDY pin should still be connected properly as it is when not used. Table 1.19. Microcomputer status in ready state (Note) Figure 1.14. Example of RD signal extended by RDY signal Note: The RDY signal cannot be received immediately before a software wait. Item Status Oscillation On R/W signal, address bus, data bus, CS ALE signal, HLDA, programmable I/O ports Maintain status when RDY signal received Internal peripheral circuits On BCLK RD CSi (i=0 to 3) RDY tsu(RDY - BCLK) : Wait using RDY signal : Wait using software Accept timing of RDY signal

M30245 Group Processor Mode Rev.2.00 Oct 16, 2006 page 33 of 264 REJ03B0005-0200 HOLD signal The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting "L" to the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status is maintained and "L" is output from the HLDA pin as long as "L" is input to the HOLD pin. Table 1.20 shows the microcomputer status in the hold state. Bus priorities listed in descending order are: HOLD, DMAC, and CPU. Table 1.20. Microcomputer status in HOLD state External bus status when the internal area is accessed Table 1.21 shows the external bus status when the internal area is accessed. Table 1.21. External bus status when the internal area is accessed BCLK output The user can choose to output BCLK on P53 by use of bit 7 of processor mode register 0 (000416) (Note). When set to "1", the output is left floating. Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register (address 000A16) to "1". Item SFR accessed Internal ROM/RAM accessed Address bus Address output Maintain status before accessing address of external area Data When read Floating Floating When write Output data Undefined RD, WR, WRL, WRH RD, WR, WRL, WRH output Output "H" BHE BHE output Maintain status before accessing status of external area CS Output "H" Output "H" ALE Output "L" Output "L" Item Status Oscillation On R/W signal, address bus, data bus, CS, BHE Floating Programmable I/O ports P0, P1, P2, P3, P4, P5 Floating P6, P7, P8, P9, P10 Maintains status when hold signal is received HLDA Output "L" Internal peripheral circuits On (Watchdog timer is stopped) ALE signal Undefined

M30245 Group Processor Mode Rev.2.00 Oct 16, 2006 page 34 of 264 REJ03B0005-0200 Software wait A software wait of one to three BCLK cycles can be inserted by setting bits 4 to 7 of the chip select control register (address 0008 16) and the bits in the chip select expansion register (address 001B 16). Software waits can be set independently for each of the 4 chip select memory areas. Bits 4 to 7 of the chip select control register correspond to chip selects CS0 to CS3. When one of these bits is set to "1", the read bus cycle is executed in one BCLK cycle and the write bus cycle is executed in two BCLK cycles. When set to "0", the read and write bus cycles are executed in two, three or four BCLK cycles, depending on the settings in the chip select expansion register. The bits in the chip select expansion register are only valid when the corresponding bit in the chip select control register is set to "0". When the bits in the chip select control register are set to "1", the corresponding bits in the chip select expansion register must be set to "00 2". The bits in the chip select control register and chip select expansion register default to "0" after the microcomputer has been reset. When the user is using the RDY signal, the relevant bit in the chip select control register’s bits 4 to 7 must be set to "0". The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Table 1.22 shows the software waits and bus cycles. Figures 1.15 and 1.16 show example bus timing when using software waits. Table 1.22. Software waits and bus cycles Note 1: When using the RDY signal, always set this bit to "0". Note 2: Set the CSxW bit to 0 before setting these bits. Also, when setting the CSxW bit to 1, be sure to reset these bits to '002' first. Area CSxW (Note 1) CSExW (Note 2) Bus Cycles Read Write SFR Invalid Invalid 2 BCLK cycles 2 BCLK cycles Internal ROM/RAM Invalid Invalid 1 BCLK cycle 1 BCLK cycle External memory area 0 00 2 BCLK cycles 2 BCLK cycles 0 01 3 BCLK cycles 3 BCLK cycles 0 10 4 BCLK cycles 4 BCLK cycles 0 11 Inhibited Inhibited 1 00 1 BCLK cycle 2 BCLK cycles

M30245 Group Processor Mode Rev.2.00 Oct 16, 2006 page 35 of 264 REJ03B0005-0200 Figure 1.15. Typical bus timings using software wait (1) Output Input Address Address Bus cycle(Note) With 1 Wait BCLK Read signal Write signal Data bus Address bus Chip select BCLK Read signal Write signal Address bus Address Address Bus cycle(Note) No Wait Data bus Chip select Bus cycle(Note) Bus cycle(Note) Note : These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in succession. InputOutput PM16=0 Write signal PM16=1 PM16=0 Data bus InputOutput PM16=1 PM16=0 PM16=0 Input Write signal Data bus PM16=1 PM16=1 Output

M30245 Group Processor Mode Rev.2.00 Oct 16, 2006 page 36 of 264 REJ03B0005-0200 Figure 1.16. Typical bus timings using software wait (2) BCLK Read signal Write signal Address bus Address Address Bus cycle(Note) With 2 Waits Data bus Chip select Bus cycle(Note) Note : These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in succession. Input PM16=0 Write signal PM16=1 PM16=0 Data bus InputPM16=1 Output Output Address BCLK Read signal Write signal Address bus Address Bus cycle(Note) With 3 Waits Data bus Chip select Bus cycle(Note) Input PM16=0 Write signal PM16=1 PM16=0 Data bus InputPM16=1 Output Output Address

M30245 Group Processor Mode Rev.2.00 Oct 16, 2006 page 37 of 264 REJ03B0005-0200 Protect register Symbol Address W hen reset PRCR 000A16 XXXXX0002 Bit nameBit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : Write-inhibited 1 : Write-enabled PRC1 PRC0 Enables writing to processor mode registers 0 and 1 (addresses 000416 and 000516) Function 0 : Write-inhibited 1 : Write-enabled Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) and frequency synthesizer registers (addresses 03DB16 to 03DF16) WR Nothing is assigned. Write "0" when writing to these bits. The values are indeterminate when read. Reserved Must always be set to "0" Protection The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 1.17 shows the protect register. The values in the processor mode register 0 (address 0004 16), processor mode register 1 (address 0005 16), system clock control register 0 (address 0006 16) and system clock control register 1 (address 0007 16) can only be changed when the respective bit in the protect register is set to "1". Setting the respective bits in the protect register to "0" will write protect these registers and not allow them to be changed. Figure 1.17. Protect register

Rev.2.00 Oct 16, 2006 page 38 of 264 REJ03B0005-0200 System Clock Clock-generating Circuit The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral units. Figure 1.18 shows the block diagram of the clock-generating circuit. Table 1.23 lists the main clock-generating circuits. Table 1.23. Main clock-generating circuits CM0i : Bit i at address 000616 CM1i : Bit i at address 000716 FSCCRi: Bit i at address 03DB16 WAIT instruction CM02 QS R NMI Interrupt request level judgment output RESET Software reset fAD Dividera d 1/2 1/2 1/2 1/2 CM06=0 CM17,CM16=00 CM06=0 CM17,CM16=01 CM06=0 CM17,CM16=10 CM06=1 CM06=0 CM17,CM16=11 d a Details of divider cb b c f32SIO2 f8SIO2 f1SIO2 f32 XOUT Main clock CM10 "1" Write signal QS R XIN Frequency Synthesizer Circuit fusb (48MHz) FSCCR0=1 FSCCR0=0 BCLK fsyn 1/32 fc32 fc XcoutXcin Sub clock CM04 CM05 CM07=0 fc CM07=1 Figure 1.18. Block diagram of the clock-generating circuit Microcomputer Externally derived clock Open Vcc Vss Microcomputer (Built-in feedback resistor) Rd CIN COUT (Note) Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. XIN XOUTXIN XOUT

Rev.2.00 Oct 16, 2006 page 40 of 264 REJ03B0005-0200 Clock Control Main clock The main clock is generated by the main clock oscillation circuit. After a reset, this clock is divided by 8 to produce the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 0006 16). Stopping the clock, after switching the operating clock source of CPU to the subclock, reduces the power dissipation. After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the main clock oscillation circuit reduces power dissipation. This bit changes to "1" when shifting from high-speed/ medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Subclock The subclock is generated by the subclock oscillation circuit. No subclock is generated after a reset. After oscillation is started using the port Xc select bit (bit 4 at address 0006 16), the subclock can be selected as the BCLK by using the system clock select bit (bit 7 at address 0006 16). However, be sure that the subclock oscillation has fully stabilized before switching. After the oscillation of the subclock oscillation circuit has stabilized, the drive capacity of the subclock oscillation circui t can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 0006 16). Reducing the drive capacity of the subclock oscillation circuit reduces the power dissipation. This bit changes to "1" when changing to stop mode and at a reset. BCLK The BCLK is the clock that drives the CPU, and is equal to fc or the clock that is derived by dividing the main clock by 1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK signal can be output from the BCLK pin (P5 3) by use of the BCLK output disable bit (bit 7 at address 0004 16) in the memory expansion and the microprocessor modes. The main clock division select bit 0 (bit 6 at address 0006 16) changes to "1" when shifting from high-speed/medium- speed to stop mode and at reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Peripheral function clock (f 1, f8, f32, f1SIO2, f8SIO2, f32SIO2, fAD) The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 0006 16) to "1" and then executing a WAIT instruction. fc This clock is derived by dividing the subclock by 32. It is used for the Timer A counts. fc This clock has the same frequency as the subclock. It is used for the BCLK and for the watchdog timer. fUSB This clock provides a 48 MHz signal required for USB operation. It is derived from the Frequency Synthesizer circuit.

Rev.2.00 Oct 16, 2006 page 42 of 264 REJ03B0005-0200 Stop Mode Writing "1" to the all-clock stop control bit (bit 0 at address 0007 16) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that Vcc remains above 2V. Because the oscillation of BCLK, f 1 to f32, f1SIO2 to f32SIO2, fc, fc 32 and f AD stops in stop mode, peripheral functions such as the A/D converter and watchdog timer do not function. However, timer A operates, provided that the event counter mode is set to an external pulse, and UARTi (i = 0 to 3) functions provided an external clock is selected. Table 1.24 shows the status of the ports in stop mode. Stop mode is cancelled by a hardware reset or interrupt. If an interrupt is to be used to cancel stop mode, that interrupt must first be enabled and the interrupt priority of any interrupts not used to cancel stop mode should be set to "0". The I flag must also be set prior to stopping for an interrupt to cancel it. When returning by an interrupt, that interrupt routine is executed. If only a hardware reset or an NMI interrupt is used to cancel stop mode, change the priority level of all interrupts to "0", then change to stop mode. After coming out of stop mode, it is recommended that four "NOP" instructions be executed to clear the instruction queue. When changing from high-speed/medium speed mode to stop mode and at reset, the main clock division select bit 0 (bit 6 at 0006 16) is set to "1". When changing from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Table 1.24. Port status during stop mode Pin Memory expansion mode Microprocessor mode Single-chip mode Address bus, data bus, CS0 to CS3, Retains status before stop mode RD, WR BHE , WRL, WRH "H" HLDA, BCLK "H" ALE "H" Port Retains status before stop mode Retains status before stop mode

Rev.2.00 Oct 16, 2006 page 43 of 264 REJ03B0005-0200 BCLK Status transition Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table 1.26 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. When reset, the device starts in division by 8 mode. The main clock division select bit 0 (bit 6 at address 0006 16) changes to "1" when shifting from high-speed/medium-speed to stop mode and at a reset. When shifting from low- speed/low power dissipation mode to stop mode, the value before stop mode is retained. The following shows the operational modes of BCLK. Wait Mode When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but the BCLK and watchdog timer stop. Writing "1" to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. However, the peripherial function clock f C32 does not stop during wait mode and thus does not contribute to any power savings. When the MCU is running in low-speed or low power dissipiation mode, do not enter WAIT mode with this bit set to "1". Table 1.25 shows the status of the ports in wait mode. Wait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, that interrupt must first be enabled and the interrupt priority levels of all other interrupts that are not used to cancel wait mode must be set to "0". When returning from an interrupt, the microcomputer restarts using as BCLK the clock that had been selected when the WAIT instruction was executed, and the program continues from the interrupt routine. If only a hardware reset or NMI interrupt is used to cancel wait mode, change the priority level of all interrupts to "0", then shift to wait mode. Table 1.25. Port status during wait mode Pin Memory expansion mode Microprocessor mode Single-chip mode Address bus, data bus, CS0 to CS3 Retains sta tus before wait mode RD, WR, BHE, WRL, WRH “H” HLDA, BCLK “H” ALE “H” Port Retains sta tus before wait mode Retains status before wait mode

Rev.2.00 Oct 16, 2006 page 44 of 264 REJ03B0005-0200 Table 1.26. System clock control registers 0 and 1 operating mode settings

• Divide by 2 mode The main clock is divided by 2 to obtain the BCLK.
• Divide by 4 mode The main clock is divided by 4 to obtain the BCLK.
• Divide by 8 mode The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4 mode, the main clock oscillator must be stable. When going to low-speed or lower power consumption mode, make sure the subclock's oscillator is stable.
• Divide by 16 mode The main clock is divided by 16 to obtain the BCLK.
• No-division mode The main clock is divided by 1 to obtain the BCLK.
• Low-speed mode fc is used as the BCLK. Note: Oscillation of both the main and sub-clocks must have stabilized before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the subclock starts. Therefore, write the program to wait until this clock has stabilized after powering up and after returning from stop mode.
• Low power dissipation mode fc is the BCLK and the main clock is stopped. Note: Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the new count source's oscillator must first be stable. Allow some wait time in software for the oscillation to stabilize before switching the clock over. CM17 CM16 CM07 CM06 CM05 CM04 BCLK operating mode 01000 10000 Invalid Invalid 0 1 0 Invalid

11000 I n v a l i d

00000 I n v a l i d

Invalid Invalid 1 Invalid 0 1 Low-speed mode Invalid Invalid 1 Invalid 1 1 Low power dissipation mode Invalid Invalid Divide-by-2 mode Divide-by-4 mode Divide-by-8 mode Divide-by-16 mode No division mode

M30245 Group Power Control Rev.2.00 Oct 16, 2006 page 45 of 264 REJ03B0005-0200 Power control The following is a description of the three available power control modes. Figure 1.22 shows the state transition diagram for these modes. Normal operation mode

• High-speed mode Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the internal clock selected. Each peripheral function operates according to its assigned clock.
• Medium-speed mode Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the BCLK. The CPU operates according to the internal clock selected. Each peripheral function operates according to its assigned clock.
• Low-speed mode fc becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the secondary clock. Each peripheral function operates according to its assigned clock.
• Low power consumption mode The main clock operating in low-speed mode is stopped. The CPU operates according to the fc clock. The fc clock is supplied by the secondary clock. The only peripheral functions that operate are those with the subclock selected as the count source. Wait mode The CPU operation is stopped. The oscillators do not stop. Stop mode All oscillators stop. The CPU and all built-in peripheral functions stop. Of the three modes discusses, the stop mode is the most effective in decreasing power consumption.

M30245 Group Power Control Rev.2.00 Oct 16, 2006 page 46 of 264 REJ03B0005-0200 Figure 1.22. Power control mode state transition diagram All oscillators stopped Stop Mode Medium-speed mode (divided-by-8 mode) RESET Normal Mode WAIT instruction Interrupt WAIT instruction Interrupt CM10 = "1" CM10 = "1" Interrupt Interrupt State Transitions for Stop and Wait modes Main clock is oscillating Sub clock is stopped Medium-speed mode (divided-by-8 mode) BCLK: f(Xin)/8 High-speed mode BCLK ; f(Xin) Medium-s peed mode (divided-by-4 mode) BCLK : f(X in)/4 BCLK ; f(Xin)/2 Medium-speed mode (divided-by-2 mode) Medium-s peed mode (divided-by-16 mode) BCLK : f(Xin)/4 Medium-speed mode (divided-by-8 mode) BCLK : f(Xin)/8 CM07 = "0" CM06 = "1" High-speed mode BCLK ; f(Xin) Medium-speed mode (divided-by-4 mode) BCLK : f(Xin)/4 BCLK ; f(Xin)/2 Medium-speed mode (divided-by-2 mode) Medium-speed mode (divided-by-16 mode) BCLK : f(Xin)/4 CM04 = "0" Main clock is oscillating Sub clock is stopped CM04 = "1" Main clock is oscillating Sub clock is oscillating CM06 = "0" (Notes 1, 3) CM07 = "0" (Note 1) CM06 = "0" (Note 3) CM07 = "1" (Note 2) CM05 = "1" CM05 = "0" CM04 = "1" (Notes 1, 3)CM04 = "0" CM06 = "1" CM07 = "0" (Note 1, 3) CM07 = "1" (Note 2) CM07 = "0" (Note 1) CM06 = "1" All oscillators stopped Stop Mode All oscillators stopped Stop Mode High speed / Medium-speed mode Low-speed / Low power dissipation mode CPU operation stopped Wait mode CPU operation stopped Wait mode CPU operation stopped Wait mode CM10 = "1" WAIT instruction Interrupt Main clock is oscillating Sub clock is oscillating Low-speed mode BCLK : f(X cin) CM07 = "1" BCLK: f(Xcin) CM07 = "1" Main clock is stopped Sub clock is oscillating Low-power dissipation mode CM05 = "1" Note 1: Switch clock after oscillation of main clock is sufficiently stable. Note 2: Switch clock after oscillation of sub clock is sufficiently stable. Note 3: Change CM06 after changing CM17 and CM16. Note 4: Transit in accordance with arrow. State Transitions for normal mode Interrupt

M30245 Group Frequency Synthesizer Circuit Rev.2.00 Oct 16, 2006 page 47 of 264 REJ03B0005-0200 Frequency synthesizer circuit The frequency synthesizer circuit generates a 48MHz clock (fUSB) needed by the USB block and a clock fSYN that are a multiple of the external input reference clock f(X IN). A block diagram of the circuit is shown in Figure 1.23. Figure 1.23. Frequency Synthesizer Circuit The frequency synthesizer consists of a prescaler, frequency multiplier, a frequency divider, and five registers: FSP; FSM; FSC; FSD; and FSCCR. Clock f(XIN) is prescaled down using FSP to generate fPIN. fPIN is multiplied by FSM to generate an f VCO clock, which is then divided by FSD to produce the clock f SYN. The fVCO clock is optimized for 48 MHz operation and is buffered and sent out of the frequency synthesizer block as signal fUSB. This signal is used by the USB block. The FSC0 bit in the FSC Control Register enables the frequency synthesizer block. When disabled (FSC0 = "0"), f VCO is held at either a high or low state. When the frequency synthesizer control bit is active (FSC0 = "1"), a lock status (LS ="1") indicates that fSYN and fVCO are the correct frequency. The LS and FSCO control bits in the FSC Control register are shown in Figure 1.24. When using the frequency synthesizer, a low-pass filter must be connected to the LPF pin. Once the frequency synthesizer is enabled, a delay of 2-5ms is recommended before the output of the frequency synthesizer is used. This is done to allow the output to stabilize. It is also recommended that none of the registers be modified once the frequency synthesizer is enabled as it will cause the output to be temporarily (2-5ms) unstable. The MCU clock source is selected via the Frequency Synthesizer Clock Control register (FSCCR). See Figure 1.25. Note: None of the registers must be written to once the frequency synthesizer is enabled and used as the system clock source (FSCCR register, address 03DB 16, bit '0' set to '1') because it will cause the output of the PLL to freeze. Switch system back to f(X IN) and disable before modifying PLL registers. FSP Data Bus FSM FSC FSD 03DE 03DD 03DC 03DF Frequency Multiplier Frequency Divider

8 Bit LS

8 Bit

f(Xin) fVCO fSYN fUSB Prescaler

Rev.2.00 Oct 16, 2006 page 51 of 264 REJ03B0005-0200 Hardware Interrupts Hardware interrupts are classified into two types - special interrupts and peripheral I/O interrupts. Special interrupts Special interrupts are non-maskable interrupts.

• Reset Reset occurs if an "L" is input to the RESET pin.
• NMI interrupt An NMI interrupt occurs if an "L" is input to the NMI pin.
• DBC interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt Generated by the watchdog timer.
• Single-step interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag) set to "1", a single-step interrupt occurs after one instruction is executed.
• Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to "1". If an address other than the first address of the instruction in the address match interrupt register is set, Peripheral I/O interrupts A peripheral I/O interrupt is generated by one of the built-in peripheral functions. Built-in peripheral functions are dependent on classes of products, so the interrupt factors are also dependent on classes of products. The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/ O interrupts are maskable interrupts.
• Bus collision detection interrupt This is an interrupt that the serial I/O bus collision detection generates.
• DMA0 through DMA3 interrupt These are interrupts the DMA generates.
• Key-input interrupt A key-input interrupt occurs if an "L" is input to any of the KI1 to KI7 pins.
• A/D conversion interrupt This is an interrupt that the A/D converter generates.
• UART0, UART1, UART2, UART3 transmit / NACK / SSI0, SSI1 transmit interrupt These are interrupts that the serial I/O, I 2C, and SSI generate.
• UART0, UART1, UART2, UART3 receive / ACK / SSI0, SSI1 receive interrupt These are interrupts that the serial I/O, I 2C, and SSI generate.
• Timer A0 interrupt through Timer A4 interrupt These are interrupts that Timer A generates
• INT0 through INT2 interrupt An INT interrupt occurs if either a rising edge or a falling edge or both edges are input to one of the INT pins.
• USB interrupts (EP0, Suspend, Resume, SOF, Reset, USB Function) These are interrupts that are generated from USB.
• VBus Detect interrupt This interrupt is generated from the USB VBus detection circuitry.

Rev.2.00 Oct 16, 2006 page 52 of 264 REJ03B0005-0200 Interrupt Routine Interrupt vector tables 1If an interrupt request is accepted, program execution branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Figure 1.30 shows the format for specifying the address. Two types of interrupt vector tables are available - fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting. Figure 1.30. Format for specifying interrupt vector addresses Fixed vector tables The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFDC 16 to FFFFF 16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table 1.27 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. Interrupt source Vector table addresses Address(L) to Address(H) Remarks Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction Overflow FFFE016 to FFFE316 Interrupt on INTO instruction BRK instruction FFFE416 to FFFE716 If the vector is filled with FF16, program execution starts from the address shown by the vector in the variable vector table Address Match FFFE816 to FFFEB16 There is an address-matching interrupt enable bit Single Step (Note) FFFEC16 to FFFEF16 Do not use Watchdog timer FFFF016 to FFFF316 DBC (Note) FFFF416 to FFFF716 Do not use NMI FFFF816 to FFFFB16 External interrupt by NMI pin Reset FFFFC16 to FFFFF16 Note: Interrupts used for debugging purposes only. Vector address + 0 Vector address + 1 Vector address + 2 Vector address + 3 Low address Mid address 0 0 0 0 High address 0 0 0 0 0 0 0 0 MSB LSB Table 1.27. Interrupt vectors with fixed addresses

Rev.2.00 Oct 16, 2006 page 53 of 264 REJ03B0005-0200 Variable vector tables The addresses in the variable vector table can be modified, according to the user’s settings. Before enabling interrupts, the user must load the INTB register with the address of the first entry in the table. The 256-byte area subsequent to the address the INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 1.28. Interrupt vectors with variable addresses Note 2: When I2C mode is selected, NACK/ACK, start/stop condition detection interrupts are selected. Software interrupt number Vector table addresses Address(L) to Address(H) Interrupt source Remarks 0 +0 to +3 (Note 1) BRK instruction Cannot be masked by I flag 1 +4 to +7 Key input 2 +8 to +11 UART2 receive / ACK 3 +12 to +15 UART1/UART3 Bus collision, Start/stop condition 4 +16 to +19 INT1 5 +20 to +23 Timer A1 6 +24 to +27 USB EP0 7 +28 to +31 Timer A2 8 +32 to +35 UART1 receive / ACK / SSI1 receive 9 +36 to +39 UART0/UART2 Bus collision, Start/stop condition 10 +40 to +43 UART0 receive / ACK / SSI0 receive 11 +44 to +47 A/D 12 +48 to +51 DMA0 13 +52 to +55 UART3 transmit / NACK 14 +56 to +59 DMA1 15 +60 to +63 UART2 transmit / NACK 16 +64 to +67 DMA2 17 +68 to +71 UART1 transmit / NACK / SSI1 transmit 18 +72 to +75 DMA3 19 +76 to +79 UART0 transmit / NACK / SSI0 transmit 20 +80 to +83 Timer A0 21 +84 to +87 UART3 receive / ACK 22 +88 to +91 USB suspend 23 +92 to +95 Timer A3 24 +96 to +99 USB resume 25 +100 to +103 Timer A4 26 +104 to +107 USB Reset 27 +108 to +111 USB SOF 28 +112 to +115 USB Vbus Detect 29 +116 to +119 USB Function 30 +120 to +123 INT2 31 +124 to +127 INT0 32 t o 63 +252 to +255 Software interrupt Cannot be masked by I flag (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) Note 1: Address relative to address in interrupt table base address register (INTB). (Note 2) (Note 2) (Note 2)

Rev.2.00 Oct 16, 2006 page 54 of 264 REJ03B0005-0200 Interrupt control The interrupt request bit is set by hardware to "0" when an interrupt request is received. The interrupt request bit can also be set by software to "0". (Do not set to "1".) INT0, INT1, and INT2 are triggered by the edges of external inputs. The edge polarity is selected using the polarity select bit. (Other interrupts are described elsewhere.) An interrupt must first be enabled before it can be used to cancel stop mode. Peripheral I/O interrupts have their own interrupt control registers. Figure 1.31 shows the interrupt control registers. Table 1.29 shows the addresses of the interrupt control registers. Figure 1.31. Interrupt control registers control registers b7 b6 b5 b4 b3 b2 b1 b0 Bit name FunctionBit symbol WR IL VL0 IR Interrupt priority level select bit Interrupt request bit 0 : Interrupt not requested 1 : Interrupt requested IL VL1 IL VL2 Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate. (Note) Note: This bit can only be reset (= 0), but cannot be set ( = 1). 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 IL VL0 IR POL Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate. Interrupt priority level select bit Interrupt request bit Polarity select bit (Note 2) Reserved bit 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Always set to "0" IL VL1 IL VL2 (Note 1) 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 Note 1: This bit can only be reset (=0), but cannot be set (=1). Note 2: For S1RIC( 004816) and S02BCNIC ( 004916), "0" should always be written. Symbol KUPIC S2RIC S13BCNIC T A1IC EP0IC T A2IC S0RIC ADIC DMOIC S3TIC DM1IC S2TIC DM2IC Address 0041 004216 004316 004516 004616 004716 004A16 004B16 004C16 004D16 004E16 004F16 005016 When reset XXXXX000 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 Symbol S1TIC DM3IC S0TIC T A0IC S3RIC SUSPIC T A3IC RSMIC T A4IC RSTIC SOFIC VBDIC USBFIC Address 0051 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 When reset XXXXX000 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 Interrupt control register Symbol INT1IC S1RIC S02BCNIC INT2IC INT0IC Address 0044 004816 004916 005E16 005F16 When reset XX00X000 XX00X0002 XX00X0002 XX00X0002 XX00X0002

Rev.2.00 Oct 16, 2006 page 55 of 264 REJ03B0005-0200 Table 1.29. Addresses in interrupt control register Interrupt control register Symbol name Address Interrupt control register Symbol name Address Key input KUPIC 004116 DMA2 DM2IC 005016 UART2 receive / ACK S2RIC 004216 UART1 transmit / NACK / Serial Sound Interface 1 transmit SITIC 005116 UART1 / UART3 Bus collision S13BCNIC 004316 DMA3 DM3IC 005216 INT1 INT1IC 004416 UART0 transmit / NACK / Serial Sound Interface 0 transmit S0TIC 0053 Timer A1 TA1IC 004516 Timer A0 TA0IC 005416 USB EP0 EP0IC 004616 UART3 receive / ACK S3RIC 005516 Timer A2 TA2IC 004716 USB Suspend SUSPIC 005616 UART1 receive / ACK / Serial Sound Interface 1 receive S1RIC 0048

16 Timer A3 TA3IC 005716

UART0 / UART2 Bus collision S02BCNIC 004916 USB Resume RSMIC 005816 UART0 receive / ACK / Serial Sound Interface 0 receive S0RIC 004A

16 Timer A4 TA4IC 005916

A/D ADIC 004B16 USB Reset RSTIC 005A16 DMA0 DM0IC 004C16 USB SOF SOFIC 005B16 UART3 transmit / NACK S3TIC 004D16 USB Vbus Detect VBDIC 005C16 DMA1 DM1IC 004E16 USB Function USBFIC 005D16 UART2 transmit / NACK S2TIC 004F16 INT2 INT2IC 005E16 INT0 INT0IC 005F16 Rewrite the Interrupt Control Register (a) The interrupt control register for any interrupt should be modified in places where no requests for that interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register. (b) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the instruction to be used.

• Changing any bit other than the IR bit
• Changing the IR bit Depending on the instruction used, the IR bit may not always be cleared to “0” (interrupt not requested). Therefore, be sure to use the MOV instruction to clear the IR bit. (c) When using the I flag to disable an interrupt, refer to the sample program fragments shown below as you set the I flag. (Refer to (b) for details about rewrite the interrupt control registers in the sample program frag- ments.) Examples 1 through 3 show how to prevent the I flag from being set to “1” (interrupts enabled) before the interrupt control register is rewrited, owing to the effects of the internal bus and the instruction queue buffer.

Rev.2.00 Oct 16, 2006 page 56 of 264 REJ03B0005-0200 Example 1:Using the NOP instruction to keep the program waiting until the interrupt control register is modified INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Set the TA0IC register to “00h”. NOP ; NOP FSET I ; Enable interrupts. The number of NOP instruction is as follows. PM20=1(1 wait) : 2, PM20=0(2 wait) : 3, when using HOLD function : 4. Example 2:Using the dummy read to keep the FSET instruction waiting INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Set the TA0IC register to “00h”. MOV.W M EM, R0 ; Dummy read. FSET I ; Enable interrupts. Example 3:Using the POPC instruction to changing the I flag INT_SWITCH3: PUSHC FLG FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Set the TA0IC register to “00h”. POPC FLG ; Enable interrupts. Interrupt Enable Flag (I flag) The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to "1" enables all maskable interrupts; setting it to "0" disables all maskable interrupts. This flag is set to "0" after reset. Interrupt Request Bit The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The interrupt request bit can also be set to "0" by software. (Do not set this bit to "1"). Interrupt Sequence The interrupt sequence, described below, is performed during the period from when an interrupt is accepted to when the interrupt routine is executed. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. The processor carries out the following in sequence after an interrupt request: (1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 00000 16. (2) Saves the contents of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU. (3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to "0" (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed). (4) Saves the contents of the temporary register (Note) within the CPU in the stack area. (5) Saves the contents of the program counter (PC) in the stack area. (6) Sets the interrupt priority level of the accepted instruction in the IPL. After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. Note: This register cannot be utilized by the user.

Rev.2.00 Oct 16, 2006 page 58 of 264 REJ03B0005-0200 Figure 1.34. Interrupt sequence timing Returning from an Interrupt Routine Executing the REIT instruction at the end of an interrupt routine restores the contents of the flag register (FLG) as it was immediately before the start of the interrupt sequence and the contents of the program counter (PC), both of which were saved in the stack area. Then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process resumes. Return the other registers that were saved by software within the interrupt routine using the POPM instruction or a similar instruction before executing the REIT instruction. Interrupt priority The order of priority when two or more interrupts are generated simultaneously is determined by both hardware and software. The interrupt priority levels determined by hardware are: RESET > NMI > DBC > Watchdog Timer > Peripheral I/O > Single step > Address match The interrupt priority levels determined by software are set in the interrupt control registers. When two or more interrupts are generated simultaneously, the interrupt with the higher software priority is selected. However, if the interrupts have the same software priority level, the interrupt is selected according to the hardware priority set in the circuit. The selected interrupt is accepted only when the priority level is higher than the processor interrupt priority level (IPL) in the flag register (FLG) and the interrupt enable flag (I flag) is "1" Note that the reset, NMI, DBC, watchdog timer, single- step, address-match, BRK instruction, overflow, and undefined instruction interrupts are accepted regardless of the interrupt enable flag (I flag). Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL) Set the interrupt priority level using the interrupt priority level select bits, which consists of three interrupt control register bits. When an interrupt request occurs, the interrupt priority level is compared with the IPL of the CPU flag register. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt priority level to "0" disables the interrupt. 1 23456789 1 0 1 1 12 The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs. Indeterminate SP-2 contents SP-4 contents Interrupt information Address 0000 Indeterminate SP-2 SP-4 PC BCLK Internal Address bus Internal Data bus R Indeterminate vec vec + 2 vec + 2

contents

W

Rev.2.00 Oct 16, 2006 page 59 of 264 REJ03B0005-0200 Table 1.31 shows the settings of interrupt priority levels and Table 1.32 shows the interrupt levels enabled, according to the contents of the IPL. The following are conditions under which an interrupt is accepted:

• interrupt enable flag (I flag) = 1
• interrupt request bit = 1 (set by hardware)
• interrupt priority level > IPL The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are independent, and they are not affected by one another. Table 1.31. Interrupt priority level settings Interrupt priority level select bit Interrupt priority level Priority order b2 b1 b0 0 0 0 Lev el 0 (interrupt disabled) 0 0 1 Le vel 1 Low 0 1 0 Le vel 2 0 1 1 Le vel 3 1 0 0 Le vel 4 1 0 1 Le vel 5 1 1 0 Le vel 6 1 1 1 Le vel 7 High Table 1.32. Interrupt levels enabled according to the contents of the IPL IPL Enabled interrupt priority levels IPL2 IPL1 IPL0 0 0 0 Interrupt levels 1 and above are enabled 0 0 1 Interrupt levels 2 and above are enabled 0 1 0 Interrupt levels 3 and above are enabled 0 1 1 Interrupt levels 4 and above are enabled 1 0 0 Interrupt levels 5 and above are enabled 1 0 1 Interrupt levels 6 and above are enabled 1 1 0 Interrupt levels 7 and above are enabled 1 1 1 All maskable interrupts are disabled

Rev.2.00 Oct 16, 2006 page 61 of 264 REJ03B0005-0200 Flag changes When an interrupt request is received, the stack pointer select flag (U flag) changes to "0" and the flag register (FLG) and program counter (PC) are saved to the stack area indicated by the interrupt stack pointer (ISP). Thereafter, the interrupt enable flag (I flag) and debug flag (D flag) change to "0" and the processor interrupt priority level (IPL) at the flag register (FLG) is replaced by the priority level of the received interrupt. However, when interrupt requests are received for software interrupts 32 to 63, the flag register (FLG) and program counter (PC) are saved to the stack shown by the stack pointer select flag (U flag) at the time the interrupt was received. The stack pointer select flag (U flag) does not change. The value of the processor interrupt priority level (IPL) in the flag register (FLG) differs in the case of reset, NMI, DBC, watchdog timer, single-step, address-match, BRK instruction, overflow, and undefined instruction interrupts. Table 1.34 shows how the IPL changes when interrupt requests are received. Table 1.34. Change of IPL state when interrupt request are accepted Interrupt Change of IPL Reset Le vel 0 ( 0002), is set NMI Le vel 7 ( 1112), i s set DBC Does not change Watchdog timer Le vel 7 ( 1112), i s set Single step Does not change Address match Does not ch ange Software interrupt Does not change

Rev.2.00 Oct 16, 2006 page 64 of 264 REJ03B0005-0200 Occurrence timing of the key-input interrupt With the Key-input interrupt enabled, Port 10 pins that are enabled in the Key-input mode register are set to input mode and become Key-input interrupt pins (KI 0 through KI7). A Key-input interrupt occurs when the selected edge is input to a Key-input interrupt pin. At this moment, the level of other key-input interrupt pins must be "H" No interrupt occurs when the level of any other key-input interrupt pins is "L". Determining a key-input interrupt A key-input interrupt occurs when the selected edge is input to one of 8 pins, (if they are all enabled in the Key-input mode register) but each pin has the same vector address. Therefore, read the input level of Port P10 in the key-input interrupt routine to determine the interrupted pin. Related registers Figure 1.39 shows the memory map of key-input interrupt-related registers. Figure 1.39. Memory map of Key-input interrupt-related registers Address Register name Acronym 004016

004116 Key input interrupt register KUPIC

03F616 Port 10 direction register PD10 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 Pull-up control register 2 PUR2 03FF16 Key-input mode register KUPM

Rev.2.00 Oct 16, 2006 page 66 of 264 REJ03B0005-0200 The NMI interrupt The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc with a pull-up resistor if unused. Do not go into stop mode when the NMI pin set to "L". The NMI pin also serves as P8 5, which is exclusively an input. Reading the contents of the P8 register allows the pin value to be read. Reading this pin is only to be used for establishing the pin level when the NMI interrupt is input. Do not reset the CPU with the input to the NMI pin in the "L" state. Do not attempt to go into stop mode when the input to the NMI pin is in "L" state. When the input to the NMI is in "L" state, CM10 is fixed to "0" thereby refusing to go into stop mode. Do not attempt to go into wait mode when the input to the NMI pin is in "L" state. When the input to the NMI pin is in"L" state, the CPU stops but the oscillation does not. This action does not save power. When this occurs, the CPU is returned to the normal state by a later interrupt. Signals input to the NMI pin require an "L" level of (2 clocks + 300nS) or more from the operation clock of the CPU. External interrupt Either an "H" or "L" level of at least 250 ns width is necessary for the signal input to pins INT0 to INT2 regardless of the CPU operation clock. When the polarity of the INT0 to INT2 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, reset the interrupt request bit to "0". Figure 1.41 shows the procedure for changing the INT interrupt generate factor. Figure 1.41. Switching condition of INT interrupt request Set the polarity select bit Clear the interrupt request bit to "0" Set the interrupt priority level 1 to 7 (Enable the INTi interrupt requests) Set the interrupt priority level to level 0 (Disable INTi interrupt) Clear the interrupt enable flag to "0" (Disable interrupt) Set the interrupt enable flag to "1" (Enable interrupt) Note: Execute the settings individually. Do not execute two or more settings simultaneously.

Rev.2.00 Oct 16, 2006 page 67 of 264 REJ03B0005-0200 Clearing the Interrupt request bit Even when the IR bit (bit 3 of the interrupt control register) is cleared to "0" (interrupt not requested), it may not actually get cleared to "0" depending on the instruction used to clear it. Therefore, use the MOV instruction to clear the IR bit. Rewriting the interrupt control register Rewrite the interrupt control register so that it does not generate an interrupt request for that register. If an interrupt request occurs, rewrite the interrupt control register after the interrupt is disabled. Some program examples are de- scribed below. When an instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not always set even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the instructions below to change the register. Instructions: AND, OR, BCLR, BSET Examples 1 through 3 show how to prevent the I flag from being set to "1" (interrupts enabled) before the interrupt control register is rewritting, due to the effects of the internal bus and the instruction queue buffer. Example 1: INT_SWITCH1: FCLR I :Disable interrupts. AND.B #00h, 0054h ;Clear TA0IC int. priority level and int. request bit. NOP ;Four NOP instructions are required when using the HOLD function . NOP FSET I ;Enable interrupts. Example 2: INT_SWITCH2: FCLR I :Disable interrupts. AND.B #00h, 0054h ;Clear TA0IC int. priority level and int. request bit. MOV.W MEM, R0 ;Dummy read. FSET I ;Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG ;Push Flag register onto stack FCLR I ;Diable interrupts. AND.B #00h, 0054h ;Clear TA0IC int. priority level and int. request bit.‘ POPC FLG ;Enable interrupts. The reason why two NOP instructions (four using the HOLD function) or a dummy read is inserted before "FSET I" in Examples 1 and 2, is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to the effects of the instruction queue.

M30245 Group Watchdog Timer Rev.2.00 Oct 16, 2006 page 68 of 264 REJ03B0005-0200 Watchdog Timer The watchdog timer can detect a runaway program. It is a 15-bit counter that decrements using the clock derived from dividing the BCLK by the prescaler. A watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. The watchdog timer interrupt is a non-maskable interrupt. When X IN is selected for BCLK, bit 7 (WDC7) of the watchdog timer control register (address 000F 16) selects the prescaler divide ratio to be either 16 or 128. When X CIN is selected for BCLK, the prescaler divide ratio is set to 2 regardless of WDC7. The watchdog timer cycle can be calculated as follows: When XIN chosen for BCLK: Watchdog timer period = prescaler dividing ratio (16 or 128) X Watchdog timer count (32768) BCLK When XCIN chosen for BCLK: Watchdog timer period = prescaler dividing ratio (2) X Watchdog timer count (32768) BCLK Example: When BCLK is 12 MHz and the prescaler divide ratio is set to 16, the monitor timer cycle is approximately 43.69 ms. The watchdog timer is initialized by writing to the watchdog timer start register (address 000E 16), and when a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is reset. After a reset, the watchdog timer and prescaler are both stopped. The count is started by writing to the watchdog timer start register (address 000E 16). The watchdog timer and the prescaler stop in stop mode, wait mode, and hold state. After exiting these modes, counting starts from the remaining value. Figure 1.42 shows the block diagram of the watchdog timer. Figure 1.43 shows the watchdog timer-related registers.

Rev.2.00 Oct 16, 2006 page 70 of 264 M30245 Group Universal Serial Bus REJ03B0005-0200 Universal Serial Bus

• USB Specification Revision 2.0 compliant
• Support of full-speed operation (12 Mbps)
• 9 endpoints - control endpoint (EP0 - bidirectional) plus four IN and four OUT endpoints
• Control endpoint (EP0) continuous transfer mode
• Programmability of transfer type and buffer size for 8 of the 9 endpoints (EP1 - EP4 IN & OUT) Single or double buffer selectable When in double buffer mode, effective maximum buffer size up to 2 x 1K bytes
• Bulk endpoints continuous transfer mode
• SOF output and interrupt generation with artificial SOF capability (in the event of corrupt SOF packet)
• 8- or 16-bit CPU access to the FIFO and registers USB Interrupts There are six USB interrupts in this device:
• EP0 Interrupt (multiple-trigger events)
• USB Function Interrupt (multiple sources)
• USB Reset Interrupt
• USB Resume Interrupt
• USB Suspend Interrupt
• USB Start-of-Frame (SOF) Interrupt The first five interrupts are used to control the data flow and USB power consumption. The SOF interrupt is used to monitor the transfer of isochronous (ISO) data. Setting the corresponding bit in the Interrupt Control Register for each interrupt enables each of the six USB interrupts.

Rev.2.00 Oct 16, 2006 page 71 of 264 M30245 Group Universal Serial Bus REJ03B0005-0200 The USB Function Interrupt has multiple interrupt sources that can be enabled within the USB Function Interrupt Enable Register (USBIE). EP0 Interrupt The EP0 interrupt is generated when one of the following events occur:

• A data set is successfully received
• A data set is successfully sent
• EP0CSR3 (DATA_END) flag is cleared. This event is maskable and the default is masked.
• A control transfer ends prematurely (i.e., the USB FCU sets the SETUP_END bit). USB Function Interrupt The USB Function interrupt can be triggered by:
• The interrupts from eight endpoints (EP1-EP4 IN/OUT). The interrupts indicate if a data set was either sent or received.
• A data flow error from any of the nine endpoints (including EP0)
• The enabling of any IN endpoint (EP1-EP4 IN).
• The corruption of the final ACK of a Control Read transfer's Data Stage. Each endpoint interrupt is enabled by setting the corresponding bit in the USB Interrupt Enable register (USBIE). Interrupt status flags associated with each source are contained in USB Interrupt Status register (USBIS). USB Reset Interrupt A USB Reset Interrupt is generated when the USB Function Control Unit (USB FCU) sees a SE0 present on D+/D- for at least 2.5us. When a reset signal is detected by the USB FCU, an internal reset pulse is also generated to reset all USB internal registers to the default values. When the CPU recognizes a USB Reset Interrupt, it re-initializes the USB FCU to ensure that the USB operation functions properly. The USB Reset Interrupt Control register (RSTIC) contains the USB Reset Interrupt request bit and interrupt priority select bits used to enable the interrupt and set the software priority level. USB Resume Interrupt A USB Resume Interrupt is generated when the USB FCU is in the suspend state and detects non-idle signaling on the D+/D-. The USB Resume Interrupt Control register (RSMIC) contains the USB Resume Interrupt request bit and interrupt priority select bits used to enable the interrupt and set its software priority level. USB SOF Interrupt The USB SOF (Start-Of-Frame) Interrupt is used to control the transfer of isochronous data. The USB FCU generates a USB SOF Interrupt request when a start-of-frame packet is received. Because the start-of-frame packet could be corrupted, a new frame might start without successful reception of the SOF packet. For this reason, an artificial SOF is provided. The frame timer signals a time out when a SOF packet is not received within the allotted time. The device generates an SOF interrupt once every frame. Setting bit 2 of the USB ISO Control Register to a "1" enables the artificial SOF function. Register SOFIC contains the USB SOF Interrupt’s request bit and interrupt priority select bits that are used to enable the interrupt and set its software priority level.

Rev.2.00 Oct 16, 2006 page 72 of 264 M30245 Group Universal Serial Bus REJ03B0005-0200 USB Suspend Interrupt A USB Suspend Interrupt is generated when the USB FCU does not detect any bus activity on D+/D- (in J-state) for at least 3ms. The USB Suspend Interrupt Control register (SUSPIC) contains the USB Suspend Interrupt request bit and interrupt priority select bits that are used to enable the interrupt and set its software priority level. USB Endpoint FIFOs The USB FCU has a built-in 3.25 K bytes FIFO as an endpoint buffer. The EP0 (control endpoint) FIFO occupies a fixed location (from 3K - 3.25K) with fixed buffer sizes (128 bytes each) for its IN and OUT data transfers. The other 8 endpoints (EP1 to EP4 IN and OUT) share a 3K bytes buffer. Each endpoint’s FIFO size and starting location (64 bytes) are programmable by the user. The sum of the 8 endpoint FIFOs can not exceed 3K bytes (3072 bytes). Note: Throughout the USB Block specification, "data packet" is generally used when continuous mode is disabled; "data set" (one or more data packets) is generally used when continuous mode is enabled. If a description applies for both noncontinuous mode and continuous mode, "data set" is used. Throughout the whole USB Block Specification, "FIFO" and "Buffer" are generally interchangeable terms. EP0 FIFO Operation The CPU writes data to the EP0 IN FIFO Data Register. The write pointer automatically increments by 2 in word accessing mode or by 1 in byte accessing mode after a write. The CPU must only write data to the EP0 IN FIFO Data Register and "1" to the SET_IN_BUF_RDY bit of the EP0 CSR when the IN_BUF_RDY flag is a "0". When a NULL packet is required to complete a control read request, the CPU must write "1" to the SET_IN_BUF_RDY bit of EP0_CSR without writing data to the EP0 IN FIFO Data Register. Continuous transfer modes are available for EP0 Control Transfers. EP0 IN FIFO with control read continuous transfer mode disabled The CPU writes "1" to the SET_IN_BUF_RDY bit of the EP0 CSR after the CPU finishes writing a data packet to the FIFO, this updates the IN_BUF_RDY flag to "1". The USB FCU updates the IN_BUF_RDY flag to "0" after the packet has been successfully transmitted to the host. EP0 IN FIFO with control read continuous transfer mode enabled The CPU writes "1" to the SET_IN_BUF_RDY bit of the EP0 CSR after the CPU finishes writing a data set (up to 128 bytes) to the FIFO. This updates the IN_BUF_RDY flag to "1". The USB FCU sends out data packets equal to the EP0 MAXP size one at a time, except for the last packet if the data set in the FIFO is not a multiple of EP0 MAXP. In this case the USB FCU sends a short packet. The USB FCU updates the IN_BUF_RDY flag to "0" after the data set has been successfully transmitted to the host. The CPU reads data from EP0 OUT FIFO Data Register. The read pointer automatically increments by 2 in word accessing mode or by 1 in byte accessing mode after a read. The CPU must only read data from the EP0 OUT FIFO when the OUT_BUF_RDY flag of the EP0_CSR is "1". When a SETUP packet is received, an EP0 interrupt is generated (both OUT_BUF_RDY and SETUP flags are set) regardless of the continuous transfer mode bit setting. EP0 OUT FIFO with control write continuous transfer mode disabled The USB FCU updates the OUT_BUF_RDY flag to "1" after it has successfully received a data packet from the host. The CPU writes "1" to CLR_OUT_BUF_RDY after the data packet has been unloaded from the FIFO by the CPU (updates the OUT_BUF_RDY flag to a "0").

Rev.2.00 Oct 16, 2006 page 73 of 264 M30245 Group Universal Serial Bus REJ03B0005-0200 EP0 OUT FIFO with control write continuous transfer mode enabled The USB FCU updates the OUT_BUF_RDY flag to "1" after:

• It has successfully received a data set equal to 128 bytes or a short packet from the host OR
• A control write status phase has started but there are pending OUT data packets in the buffer. The CPU writes "1" to CLR_OUT_BUF_RDY after the data set has been unloaded from the FIFO by the CPU (updates the OUT_BUF_RDY flag to "0"). Special note when using continuous transfer mode in control read request In continuous transfer mode, the CPU can write multiple data packets to the data buffer before setting the SET_IN_BUF_RDY to "1". The CPU must write the last data packet separately to the data buffer and sets the SET_DATA_END bit. For example, if the buffer size=128 bytes, MAXP= 8 bytes, and the CPU sends 64 bytes of data to the host, the CPU does the following:
• Writes 7x8=56 bytes to the buffer;
• Sets SET_IN_BUF_RDY=1;
• After the 7 packets are successfully sent to host, the IN_BUF_RDY flag changes from "1" to "0";
• Writes the last 8 bytes of data to the buffer;
• Sets SET_IN_BUF_RDY="1" and SET_DATA_END to "1"; The CPU should not write all 64 bytes of data, and set the SET_IN_BUF_RDY and SET_DATA_END bits to "1" at the same time. Special note when using continuous transfer mode in control write request Because the buffer can hold multiple data packets before generating an interrupt, two special cases should be taken into consideration: 1. The SETUP_END flag usually indicates a premature completion of a control transfer. However, if the data field of a control write is a multiple of MAXP but not a multiple of the buffer size, the SETUP_END flag may be set without causing a premature completion of transfer. For example, if MAXP =8, buffer size = 128, wLength = 192 (a multiple of MAXP but not the buffer size), the following occurs in continuous mode: After receiving 16 8-byte packets, (128 bytes) from the host, an EP0 interrupt is generated to indicate to the CPU that data unloading can start. When the host completes sending the remainder of the data field (eight 8-byte packets) an EP0 interrupt is not gener- ated because the buffer is not full and there is no short packet. When the status phase starts (the host sends an IN token), OUT_BUF_RDY and SETUP_END are set. The SETUP_END is set because the CPU is unaware of the end of the data phase, thus DATA_END is not set. Whenever DATA_END is not set and the status stage starts, the protocol state machine will treat it as a premature completion (data field is less than wLength) and sets the SETUP_END bit. It is the users responsibility to determine the difference between a premature completion and a normal completion (data field equals the wLength) when the CPU acknowledges a SETUP_END flag in continuous mode. 2. The device usually returns a stall handshake when the host sends more data than specified in the wLength field. However, if a host sends more data than specified in wLength in the middle of a continuous transfer burst, the USB FCU returns ACK to every packet it receives if there are no errors. In this case, when the firmware detects this kind of protocol error, it must set CLR_OUT_PKT_RDY to "1" and set SEND_STALL to "1" so that the USB FCU returns STALL in the subsequent data or status phase. For example, if MAXP = 8, buffer size = 128, wLength = 26, the following may occur:

Rev.2.00 Oct 16, 2006 page 74 of 264 M30245 Group Universal Serial Bus REJ03B0005-0200 CASE 1: The host sends three 8-byte packets and one 2-byte packet. When the core receives the last 2-byte packet, the OUT_BUF_RDY flag is set (because of a short packet) indicating the CPU can unload the data. At the end of unloading, the CPU should clear the OUT_BUF_RDY flag and set the DATA_END. If the host sends more data after this point, the core returns STALL automatically. CASE 2: The host sends 6 8-byte packets (anything greater than 3 for this example) and one 2-byte packet (host may erroneously send 50 bytes instead of 26). The host ACKs each received packet however, it does not automatically return a STALL because the DATA_END flag is not set when the excessive packets are received. When the CPU retrieves the data and detects that the data field is greater than the wLength, it sets the SEND_STALL bit for the core to return STALL. EP1-4 IN (Transmit) FIFO Operation The CPU writes data to the endpoint's FIFO Data Register. The write pointer automatically increments by 2 in word accessing mode or increments by 1 in byte accessing mode after a write. The CPU must only write data to the FIFO Data Register when the IN_BUF_STS1 flag of the corresponding EPx IN CSR is "0". The IN_BUF_STS0 & IN_BUF_STS1 flags are both "1" after a hardware reset or a USB reset, and become "0" when the corresponding endpoint is first enabled (Endpoints 1-4 IN & OUT are disabled at reset). The user can program the buffer size and starting location of each IN Endpoint. Users can assign a buffer size up to 1024 bytes in units of 64 bytes to an endpoint. If double buffer mode is selected, the effective buffer size is 2 x buffer size specified. Continuous transfer mode is available for IN EP1-4 for Bulk Transfers only. When the continuous transfer mode is enabled, it is the user’s responsibility to ensure the buffer size is a multiple of the MAXP value. AUTO_SET function is available for IN EP1-4 for both noncontinuous and continuous modes. When this function is enabled, if a short packet or a less than buffer size data set is to be transmitted to the host, the CPU must write a "1" to the SET_IN_BUF_RDY bit to signify the packet (data set) is ready to send. AUTO_SET and continuous transfer mode are disabled: Single Buffer Mode: The CPU writes a "1" to the SET_IN_BUF_RDY bit of the corresponding EPx IN CSR after the CPU finishes writing a data packet to the buffer (updates the IN_BUF_STS1 & IN_BUF_STS0 flags from 00 2 to 112). The USB FCU updates the buffer status flags from 11 2 to 002 after the data packet has been successfully transmitted to the host. Double Buffer Mode: The CPU writes "1" to the SET_IN_BUF_RDY bit of the corresponding EPx IN CSR after the CPU finishes writing a data packet to the buffer (updates the IN_BUF_STS1 & IN_BUF_STS0 flags).

• If the buffer is immediately available to accept another data packet, the buffer status flags transition from 00 2 to 012.
• If the buffer is not available to accept another data packet, the buffer status flags transition from 01 2 to 112. The USB FCU updates the buffers status flags after a data packet has been successfully transmitted to the host.
• If the buffer has one more data packet in it, the buffer status flags transition from 11 2 to 012.
• If the buffer has no more data packet in it, the buffer status flags transition from 01 2 to 002. AUTO_SET is disabled and continuous transfer mode enabled: Single Buffer Mode: The CPU writes a "1" to the SET_IN_BUF_RDY bit of the corresponding EPx IN CSR after the CPU finishes writing a data set up to its buffer size to the buffer (updates the IN_BUF_STS1 & IN_BUF_STS0 flags from 00 2 to 112). The USB FCU sends out data packets equal to the MAXP size one at a time, except for the last packet, if the data set in the buffer is not a multiple of the MAXP, the USB FCU sends a short packet. The USB FCU updates the buffer status flags from 11 2 to 002 after the data set has been successfully transmitted to the host.

Rev.2.00 Oct 16, 2006 page 75 of 264 M30245 Group Universal Serial Bus REJ03B0005-0200 Double Buffer Mode: The CPU writes a "1" to the SET_IN_BUF_RDY bit of the corresponding EPx IN CSR after the CPU finishes writing a data set up to its buffer size to the buffer (updates the IN_BUF_STS1 & IN_BUF_STS0 flags). The USB FCU sends out data packets equal to the MAXP size one at a time, except for the last packet if the data in the buffer is not a multiple of the MAXP, the USB FCU sends a short packet.

• If the buffer is immediately available to accept another data set, the buffer status flags transition from 00 2 to 012.
• If the buffer is not available to accept another data set, the buffer status flags transition from 01 2 to 112. The USB FCU updates the buffers status flags after a data set has been successfully transmitted to the host.
• If the buffer has one more data set in it, the buffer status flags transition from 11 2 to 012.
• If the buffer has no more data set in it, the buffer status flags transition from 01 2 to 002. AUTO_SET is enabled and continuous transfer mode disabled: Single Buffer Mode: After the CPU writes a data packet equal to the MAXP size to the buffer, the USB FCU updates the corresponding EPx IN CSR’s IN_BUF_STS1 & IN_BUF_STS0 flags from 00 2 to 11 2 automatically without the CPU writing "1" to the SET_IN_BUF_RDY bit. The USB FCU updates the buffer status flags from 11 2 to 002 after the data packet has been successfully transmitted to the host. If the data packet is less than the MAXP size, the CPU must write "1" to the SET_IN_BUF_RDY bit to signify the data packet is ready to send. Double Buffer Mode: After the CPU writes a data packet equal to its MAXP size to the buffer, the USB FCU updates the corresponding EPx IN CSR’s IN_BUF_STS1 & IN_BUF_STS0 flags.
• If the buffer is immediately available to accept another data packet, the buffer status flags transition from 00 2 to 012.
• If the buffer is not available to accept another data packet, the buffer status flags transition from 01 2 to 112. The USB FCU updates the buffers status flags after a data packet has been successfully transmitted to the host.
• If the buffer has one more data packet in it, the buffer status flags transition from 11 2 to 012.
• If the buffer has no more data packet in it, the buffer status flags transition from 01 2 to 002.
• If the data packet is less than the MAXP size, the CPU must write "1" to the SET_IN_BUF_RDY bit to signify the data packet is ready to send. AUTO_SET and continuous transfer mode are enabled: Single Buffer Mode: After the CPU writes a data set equal to the buffer size to the buffer, the USB FCU updates the corresponding EPx IN CSR's IN_BUF_STS1 & IN_BUF_STS0 flags from 00 2 to 11 2 automatically without the CPU writing "1" to the SET_IN_BUF_RDY bit. The USB FCU sends out data packets equal to the MAXP size one at a time, except for the last packet if the data set in the buffer is not a multiple of its MAXP, the USB FCU sends a short packet. The USB FCU updates the buffer status flags from 11 2 to 00 2 after the data set has been successfully transmitted to the host. If the data set is less than the buffer size, the CPU must write “1” to the SET_IN_BUF_RDY bit to signify the data set is ready to send.

Rev.2.00 Oct 16, 2006 page 76 of 264 M30245 Group Universal Serial Bus REJ03B0005-0200 Double Buffer Mode: After the CPU writes a data set equal to its buffer size to the buffer, the USB FCU updates the IN_BUF_STS1 & IN_BUF_STS0 flags.

• If the buffer is immediately available to accept another data set, the buffer status flags transition from 00 2 to 012.
• If the buffer is not available to accept another data set, the buffer status flags transition from 01 2 to 112. The USB FCU sends out data packets equal to the MAXP size one at a time, except for the last packet.
• If the data in the buffer is not a multiple of the MAXP, the USB FCU sends a short packet. The USB FCU updates the buffers status flags after a data set has been successfully transmitted to the host.
• If the buffer has one more data set in it, the buffer status flags transition from 11 2 to 012.
• If the buffer has no more data set in it, the buffer status flags transition from 01 2 to 002.
• If the data set is less than the buffer size, the CPU must write "1" to the SET_IN_BUF_RDY bit to signify the data set is ready to send. IN Endpoint FIFO Flush A software or a hardware flush causes the USB FCU to act (in both continuous and noncontinuous transfer modes) as if a data set has been successfully transmitted out to the host. When there is one data set in the buffer, a flush causes the buffer to be empty. When there are two data sets in the buffer, a flush causes the older data set to be flushed out from the buffer. A flush also updates the buffer status flags of the corresponding EPx IN CSR. The Endpoint 1-4 IN buffer status can be obtained from the two status bits of the EPx IN CSR of the corresponding endpoint as shown in Table 1.35. Table 1.35. Endpoint 1-4 IN buffer status IN_BUF_STS1 IN_BUF_STS0 Buffer Status 0 0 No data set in the IN buffer Single buffer mode: N/A Double buffer mode: One data set in the IN Buffer Single buffer mode: N/A Double buffer mode: N/A Single buffer mode: One data set in the IN buffer Double buffer mode: Two data sets in the IN buffer

Rev.2.00 Oct 16, 2006 page 77 of 264 M30245 Group Universal Serial Bus REJ03B0005-0200 EP1-4 OUT (Receive) FIFOs The CPU reads data from the endpoint’s FIFO Data Register. The read pointer automatically increments by 2 in word accessing mode or by 1 in byte accessing mode after a read. The CPU must only read data from the FIFO Data Register when the OUT_BUF_STS1 flag of the corresponding EPx OUT CSR is a "1". The user can program each OUT endpoint’s buffer size and starting location, and assign a buffer size up to 1024 bytes in units of 64 bytes to an endpoint. If double buffer mode is selected, the effective buffer size is 2 x buffer size specified. Continuous transfer mode is available for OUT EP1-4 bulk transfers only. When the continuous transfer mode is enabled, the user is responsible for ensuring that the buffer size is a multiple of the MAXP value. Also, the user must ensure that the last data set from the host either contains a short packet or is equal to the buffer size, otherwise there is no interrupt or status that will signify that the last data set was received. AUTO_CLR function is available for OUT EP1-4. AUTO_CLR and continuous transfer mode are disabled: Single Buffer Mode: The USB FCU updates the corresponding EPx OUT CSR’s OUT_BUF_STS1 & OUT_BUF_STS0 flags from 00 2 to 112 after it has successfully received a data packet from the host. The CPU writes "1" to the CLR_OUT_BUF_RDY bit after the data packet has been unloaded from the buffer by the CPU (updates the OUT_BUF_STS1 & OUT_BUF_STS0 flags from 11 2 to 002). Double Buffer Mode: The USB FCU updates the corresponding EPx OUT CSR's OUT_BUF_STS1 & OUT_BUF_STS0 flags after it has successfully received a data packet from the host.

• If the buffer has only one data packet, the buffer status flags transition from 00 2 to 102.
• If the buffer has two data packets, the buffer status flags transition from 10 2 to 112. The CPU writes "1" to the CLR_OUT_BUF_RDY bit after a data packet has been unloaded from the buffer by the CPU (updates the OUT_BUF_STS1 & OUT_BUF_STS0 flags).
• If the buffer has one more data packet in it, the buffer status flags transition from 11 2 to 102.
• If the buffer has no more data packet in it, the buffer status flags transition from 10 2 to 002. AUTO_CLR is disabled and continuous transfer mode enabled: Single Buffer Mode: The USB FCU updates the corresponding EPx OUT CSR’s OUT_BUF_STS1 & OUT_BUF_STS0 flags from 00 2 to 112 after it has successfully received from the host a data set equal to the buffer size, or a short packet. The CPU writes "1" to the CLR_OUT_BUF_RDY bit after the data set has been unloaded from the buffer by the CPU (updates the OUT_BUF_STS1 & OUT_BUF_STS0 flags from 11 2 to 002 ). Double Buffer Mode: The USB FCU updates the corresponding EPx OUT CSR’s OUT_BUF_STS1 & OUT_BUF_STS0 flags after it has successfully received a data set equal to its buffer size or a short packet from the host..
• If the buffer has only one data set, the buffer status flags transition from 00 2 to 102 .
• If the buffer has two data sets, the buffer status flags transition from 10 2 to 112 .

Rev.2.00 Oct 16, 2006 page 78 of 264 M30245 Group Universal Serial Bus REJ03B0005-0200 The CPU writes a "1" to the CLR_OUT_BUF_RDY bit after a data set has been unloaded from the buffer by the CPU (updates the OUT_BUF_STS1 & OUT_BUF_STS0 flags).

• If the buffer has one more data set in it, the buffer status flags transition from 11 2 to 102 .
• If the buffer has no more data set in it, the buffer status flags transition from 10 2 to 002 . AUTO_CLR is enabled and continuous transfer mode disabled: Single Buffer Mode: The USB FCU updates the corresponding EPx OUT CSR’s OUT_BUF_STS1 & OUT_BUF_STS0 flags from 00 2 to 112 after it has successfully received a data packet from the host. The USB FCU updates the OUT_BUF_STS1 & OUT_BUF_STS0 flags from 11 2 to 002 automatically when the data packet has been unloaded from the buffer by the CPU without the CPU writing a "1" to the CLR_OUT_BUF_RDY bit. Double Buffer Mode: The USB FCU updates the corresponding EPx OUT CSR’s OUT_BUF_STS1 & OUT_BUF_STS0 flags after it has successfully received a data packet from the host.
• If the buffer has only one data packet, the buffer status flags transition from 00 2 to 102 .
• If the buffer has two data packets, the buffer status flags transition from 10 2 to 112 . The USB FCU updates the OUT_BUF_STS1 & OUT_BUF_STS0 flags automatically when a data packet has been unloaded from the buffer by the CPU without the CPU writing a "1" to the CLR_OUT_BUF_RDY bit.
• If the buffer has one more data packet in it, the buffer status flags transition from 11 2 to 102 . AUTO_CLR is enable and continuous transfer mode enabled: Single Buffer Mode: The USB FCU updates the corresponding EPx OUT CSR’s OUT_BUF_STS1 & OUT_BUF_STS0 flags from 00 2 to 112 after it has successfully received a data set equal to its buffer size or a short packet from the host. The USB FCU updates the OUT_BUF_STS1 & OUT_BUF_STS0 flags from 11 2 to 002 automatically when the data set has been unloaded from the buffer by the CPU without the CPU writing a "1" to the CLR_OUT_BUF_RDY bit. Double Buffer Mode: The USB FCU updates the corresponding EPx OUT CSR’s OUT_BUF_STS1 & OUT_BUF_STS0 flags after it has successfully received a data set equal to its buffer size or a short packet from the host.
• If the buffer has only one data set, the buffer status flags transition from 00 2 to 102 .
• If the buffer has two data sets, the buffer status flags transition from 10 2 to 112 . The USB FCU updates the OUT_BUF_STS1 & OUT_BUF_STS0 flags automatically when a data set has been unloaded from the buffer by the CPU without the CPU writing a "1" to the CLR_OUT_BUF_RDY bit.
• If the buffer has one more data set in it, the buffer status flags transition from 11 2 to 102.
• If the buffer has no more data set in it, the buffer status flags transition from 10 2 to 002.

Rev.2.00 Oct 16, 2006 page 79 of 264 M30245 Group Universal Serial Bus REJ03B0005-0200 OUT Endpoint FIFO Flush A software flush causes the USB FCU to act as if a data set has been unloaded from the buffer. The user must only set the flush bit when OUT_BUF_STS1 = 1, which indicates that one or two data sets have been received. When there is one data set in the buffer, a flush causes the buffer to empty. When there are two data sets in the buffer, a flush causes the older data set to be flushed out from the buffer. A flush also updates the buffer status flags of the corresponding EPx OUT CSR. The status of Endpoint 1-4 OUT buffers can be obtained from the two status bits of the EPx OUT CSR of the corre- sponding endpoint as shown in Table 1.36. Table 1.36. Endpoints 1-4 OUT buffer status Interrupt Endpoints Any endpoint can be used for interrupt transfers. For normal interrupt transfers, the interrupt transactions behave the same as bulk transactions, i.e., no special setting is required. The IN endpoints may be used to communicate rate feedback information for certain types of isochronous functions. Setting the INTPT bit in the IN CSR register of the corresponding IN CSR enables this function. When the INTPT bit is set, the data toggle bit changes after each packet is sent regardless of the presence or type of handshake that is returned from the host. The operation sequence for an IN endpoint used to communicate rate feedback information is listed in the following steps. 1. Set single buffer mode for the endpoint in use; 2. Set INTPT bit of the IN CSR; 3. Load interrupt status information and set SET_IN_BUF_RDY bit in the IN CSR; 4. Repeat step 3 for all subsequent interrupt status updates. When an interrupt endpoint is used for rate feedback, the device always has data to send back to the host, even if the data conveys that everything is ‘fine’. Therefore, the device never NAKs an IN token from the host. The device always sends out the data in the FIFO in response to an IN token regardless of the IN buffer status bits. OUT_BUF_STS1 OUT_BUF_STS0 Buffer Status 0 0 No data set in the OUT buffer Single buffer mode: N/A Double buffer mode: N/A Single buffer mode: N/A Double buffer mode: One data set in the OUT buffer Single buffer mode: One data set in the OUT buffer Double buffer mode: Two data sets in the OUT buffer

Rev.2.00 Oct 16, 2006 page 80 of 264 M30245 Group Universal Serial Bus REJ03B0005-0200 USB Special Function Registers The MCU controls USB operation through the use of special function registers. Some USB-related special function registers have a mix of read/write, read only, and write only register bits. Additionally, the bits may be configured to allow the user to write only "0" or "1" to individual bits.

• When accessing these registers, writing "0" to a register that can only be set to "1" by the CPU has no effect on that register bit.
• Writing "1" to a register that can only be set to "0" by the CPU has no effect on that register bit. All USB SFRs, with the exceptions of Endpoint FIFO data registers, USBAD, and USBC can be accessed by word or by byte at an even or odd address. Endpoint FIFO Data Registers can be accessed by either word or by byte at even addresses only. The contents of all USB Special Functions Registers, including USB Attach/Detach and USB Control, are preserved after a software reset. USB Attach/Detach Register The USB Attach / Detach Register is shown in Figure 1.44. The register is used to attach and detach the USB function from a USB host without physically disconnecting the USB cable. This functionality is enabled by setting 0_SECOND to a "1". Doing this forces P9 0 to operate as a pull-up for D+ (through an external 1.5k ohm resistor). The port driver is tri-stated and a "1" is always read from the port bit in this mode. When the ATTACH/DETACH bit is a "1" (and P9 0_SECOND is a "1"), P9 0 is driven with the voltage on UVcc, causing D+ to be pulled up and the host to detect an attach. When the ATTACH/DETACH bit is a "0" (and P9 0_SECOND is a "1"), P90 is tri-stated, causing D+ to be pulled down (through the cable and 15k ohm resistor on the host/hub side) and a detach to be registered by the host. A 1.5k ohm pull-up resistor must be connected externally from P9 0 to D+ when this functionality is used. When it is not used, the 1.5k ohm resistor should be placed between UVcc and D+. See "Vbus Detect" for information on the vbus detect enable bit. Figure 1.44. USB Attach/Detach register (USBAD) USB Attach/Detach Register Symbol Address When reset USBAD 001F 16 00 16 Bit nameBit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : Normal mode for Port 90 1 : Forces Port 90 to operate as pull up for D+.P90-second Function Reserved Must always be set to "0" Port 90-Second Attach/ Detach Attach/Detach 0 : Tri-states, P90causing the host to detect a detach 1 : Drives P90 with voltage on UVcc, causing the host to detect an attach WR 0 0 0 0 0 VBDT Vbus detect enable 0 : Disabled 1 : Enabled

Rev.2.00 Oct 16, 2006 page 82 of 264 M30245 Group Universal Serial Bus REJ03B0005-0200 Power Management Register The USB Power Management Register, shown in Figure 1.47, is used for power management in the USB FCU. SUSPEND State Flag: When the USB FCU does not detect any bus activity on D+/D- (in the J-state) for at least 3ms, it updates the Suspend State Flag and generates an interrupt. This flag is cleared when active signaling from the host is detected on D+/D- (The USB FCU generates a resume interrupt), or the CPU sets the Remote Wake-up Bit while in suspend state and it is subsequently cleared by the CPU. If the USB clock was disabled during the suspend state, the SUSPEND state flag is not cleared until after the USB clock is re-enabled. WAKEUP Control Bit: The CPU writes a "1" to the WAKEUP Control Bit for remote wake-up. While this bit is set and the USB FCU is in suspend mode, resume signaling is sent to the host. The CPU must keep this bit set for a minimum of 1ms and a maximum of 15ms before writing a "0" to this bit. Figure 1.47. USB Power Management register (USBPM) USB Function Interrupt Status Register USB Function Interrupt Status register, shown in Figure 1.48, is used to indicate the condition that caused a USB function interrupt to the CPU. A "1" indicates the corresponding condition caused an interrupt. INTST0, INITST2, INTST4 or INTST6 is set to "1" by the USB FCU when:

• The endpoint is enabled from a disabled state;
• A data set is successfully sent;
• A hardware autoflush takes place or the CPU writes "1" to INxCSR6 (FLUSH) if there are one or two data sets in the buffer. This causes the EP1-4 IN buffer status flag to change states. INTST1, INTST3, INTST5 or INTST7 is set to "1" by the USB FCU when:
• A data set is successfully received. INTST8 is an Error Interrupt Status flag, which indicates that an error has been encountered at any endpoint. This flag is set to "1" by the USB FCU when:
• EP0CSR4 (FORCE_STALL) flag is set;
• EP0CSR5 (SETUP_END) flag is set;
• INxCSR2 (UNDER_RUN) flag is set on any EP1-4 IN endpoint;
• OUTxCSR2 (OVER_RUN) flag is set on any EP1-4 OUT endpoint;
• OUTxCSR3 (FORCE_STALL) flag is set on any EP1-4OUT endpoint; Bit Symbol Bit Name Function R W Must always be "0" O O Symbol USBPM Address 028216 When reset 000016 USB Power Management register (b15) (b8) SUSPEND b7 b0 00000000 Suspend state flag 0 : Not in suspend state 1 : In suspend state O O Reserved WAKEUP Remote wakeup 0 : End remote wakeup signal 1 : Remote wakeup signaling if SUSPEND="1" O O 00000 Note: Read only Note

M30245 Group Universal Serial Bus Rev.2.00 Oct 16, 2006 page 85 of 264 REJ03B0005-0200 USB ISO Control Register The USB ISO Control Register, shown in Figure 1.52, contains the isochronous data transfer control and status information.

• ISO_UPD The ISO_UPD bit is a global bit for endpoints 1-4 and works with IN isochronous pipes only. When ISO_UPD = "0", a data packet in an endpoints IN buffer is always 'ready to transmit' when it receives the next IN token from the host (with matched address and endpoint number), if the CPU writes "1" to the corresponding endpoint's SET_IN_BUF_RDY bit, or in AUTO_SET case, a data packet equal to EPx's MAXP value has been written to the FIFO. When ISO_UPD = "1" and the ISO bit of the corresponding endpoint's IN CSR is set, the internal 'ready to transmit' signal to the transmit control logic is not activated when the CPU writes "1" to the corresponding endpoint's SET_IN_BUF_RDY bit, or in the AUTO_SET case, a data packet equal to EPx's MAXP value has been written to the FIFO. Instead it is activated when the next SOF is received, thus the data loaded in frame n is transmitted out in frame n+1.
• AUTO_FL When AUTO_FL = "1", ISO_UPD = "1", IN endpoint's ISO bit is set, and the IN endpoint's IN_BUF_STS1 & IN_BUF_STS0 are "1"s at the time the USB FCU detects a SOF (from the host or from artificial SOF), it automatically flushes the oldest packet from the IN buffer. In this case, IN_BUF_STS1 & IN_BUF_STS0 are "1"s and indicate that two data packets are in the IN buffer. Double buffering is required for ISO transfer.
• ART_SOF_ENA An artificial SOF function enable bit.
• ART_SOF_SET Artificial SOF function status flag. When this flag is "1", it indicates that an artificial SOF will be generated by the device because of a missing or corrupt SOF packet (when the SOF enable bit is set to "1"). A corrupt SOF packet is any SOF having an error in its 8-bit Pakcet ID (PID) field.
• CLR_ART_SOF The CPU writes "1" to this bit to clear the ART_SOF_SET flag. Figure 1.52. USB ISO Control register (USBISOC) Bit Symbol Bit Name Function R W O O Symbol USBISOC Address 028C16 When reset 000016 USB ISO Control register (b15) (b8) b0b7 b0 00000000 0 : Hardware auto flush disabled 1 : Hardware auto flush enabled 0 : ISO update disabled 1 : ISO update enabled 0 : Artificial SOF disabled 1 : Artificial SOF enabled 0 : Not generated by device (Note 1) 1 : Generated by the device 0 : No action (Note 2) 1 : Clear ART_SOF_SET flag Must always be set to "0" O OAUTO_FL ISO_UPD ART_SOF_ENA ART_SOF_SET CLR_ART_SOF Reserved O O Auto flush ISO Update Artificial SOF enable Artificial SOF set flag Clear artificial SOF set flag O O O X O O Note 1: Read only Note 2: Always read "0"

M30245 Group Universal Serial Bus Rev.2.00 Oct 16, 2006 page 87 of 264 REJ03B0005-0200 USB Endpoint 0 CSR The Endpoint 0 CSR (Control & Status register), shown in Figure 1.55, contains the control and status information for EP0.

• EP0CSR0 (OUT_BUF_RDY): A status flag, "1" indicates a SETUP packet or an OUT data set is in the OUT buffer, ready for the CPU to unload. During the data phase, if noncontinuous mode is set, the OUT_BUF_RDY bit is "1" when:
• A data packet is received from the host During the data phase, if continuous mode is set, the OUT_BUF_RDY bit is "1" when:
• A data set equal to 128 bytes is received from the host
• A short packet is received from the host
• A control write status phase has started with pending OUT data packets in the buffer.
• EP0CSR1 (IN_BUF_RDY): A status flag, "1" indicates a data set is in the IN buffer, ready for transmission. The USB FCU clears this bit after the data set is successfully transmitted to the host, or the EP0CSR5 (SETUP_END) bit is set.
• EP0CSR2 (SETUP): A status flag, "1" indicates a SETUP packet has been received. The SETUP Flag is a subset of the OUT_BUF_RDY flag.
• EP0CSR3 (DATA_END): A status flag, "1" indicates the CPU sets the DATA_END bit. The USB FCU clears this flag after the status phase has started or a new SETUP is received. This flag is a maskable flag. If DATA_END Flag Mask is a "1" (default), this DATA_END flag is always a "0" and no EP0 interrupt is caused by the DATA_END flag being cleared.
• EP0CSR4 (FORCE_STALL): A status flag, "1" indicates a protocol error when one of the following occurs:
• Host sends an IN token in the absence of a SETUP stage
• Host sends a bad data toggle in the STATUS stage, (i.e. DATA0 is used)
• Host sends a bad data toggle in the SETUP stage, (i.e. DATA1 is used)
• Host requests more data than specified in the SETUP state, (i.e. IN token comes after DATA_END bit is set)
• Host sends more data than specified in the SETUP state, (i.e. OUT token comes after DATA_END bit is set)
• Host sends a larger data packet than the MAXP size All of the conditions stated (except bad data toggle in the SETUP stage) cause the device to send a STALL handshake for the current IN/OUT transaction. For the bad data toggle in the SETUP stage, the device sends ACK for the SETUP stage and then sends STALL for the next IN/OUT transaction. A STALL handshake caused by the above conditions lasts for one transaction and terminates the ongoing control transfer. Any packet after the STALL handshake will be seen as the beginning of a new control transfer.

M30245 Group Universal Serial Bus Rev.2.00 Oct 16, 2006 page 88 of 264 REJ03B0005-0200

• EP0CSR5 (SETUP_END): A status flag, "1" indicates a premature completion of a control transfer when one of the following events occurs:
• A control transfer ends before the specific length of data is transferred during the data phase (status phase starts before DATA_END bit is set)
• A new SETUP is received before successfully completing the status phase of the previous control transfer.
• EP0CSR6 (CLR_OUT_BUF_RDY): The CPU writes a "1" to this bit after unloading a data set from the buffer. Writing a "1" to this bit clears the OUT_BUF_RDY status flag.
• EP0CSR7 (SET_IN_BUF_RDY): The CPU writes a "1" to this bit after loading a data set to the buffer. Writing a "1" to this bit sets the IN_BUF_RDY status flag.
• EP0CSR8 (CLR_SETUP): The CPU writes a "1" to this bit to clear the SETUP status flag.
• EP0CSR9 (SET_DATA_END): The CPU writes a "1" to this bit when it writes (IN data phase) the last data packet to the buffer or reads (OUT data phase) the last data packet from the buffer. The CPU sets this bit at the same time (using the same instruction) as it sets the CLR_OUT_BUF_RDY bit or sets the SET_IN_BUF_RDY bit for the last data set. Writing a "1" to this bit sets the DATA_END status flag.
• EP0CSR10 (CLR_FORCE_STALL): The CPU writes a "1" to this bit to clear the FORCE_STALL status flag.
• EP0CSR11 (CLR_SETUP_END): The CPU writes a "1" to this bit to clear the SETUP_END status flag.
• EP0CSR12 (SEND_STALL): The CPU writes a "1" to this bit when it decodes an invalid or unsupported request from the host. The CPU should only write a "1" to this bit at the same time it writes a "1" to EP0CSR6 (CLR_OUT_BUF_RDY). When this bit is a "1", the USB FCU returns STALL handshakes for all subsequent IN/OUT transactions. The CPU writes a "0" to clear it after it receives a new SETUP packet. It is up to the firmware to decide what SETUP packet should lead the clearing of the SEND_STALL bit.
• EP0CSR13 (DATA_END_MASK): This bit is for the CPU to mask or unmask the clearing of DATA_END as an EP0 interrupt source - default is masked (clearing of DATA_END does not cause an EP0 interrupt).

M30245 Group Universal Serial Bus Rev.2.00 Oct 16, 2006 page 90 of 264 REJ03B0005-0200 USB Endpoint 0 WRT CNT Register The USB Endpoint 0 WRT CNT Register, shown in Figure 1.57, contains the number of bytes of the current data set in the OUT buffer. The USB FCU sets the value in the WRT_CNT Register after having successfully received a data set from the host. The CPU reads the register to determine the number of bytes to be read from the buffer. The WRT_CNT value does not decrement upon a CPU read from the FIFO Data Register. The WRT_CNT value is cleared when the CPU writes a "1" to the CLR_OUT_BUF_RDY bit of the EP0 CSR. Figure 1.57. USB Endpoint 0 write count register (EP0WC) USB Endpoint x IN CSR (x = 1 to 4) The USB Endpoint x IN control status register, shown in Figure 1.58, contains control and status information of the respective IN EP 1-4.

• INxCSR0 (IN_BUF_STS0) and INxCSR1 (IN_BUF_STS1): Two status flags, indicate the current status of the IN buffer. These two flags are "1"s after reset, and become "0"s when the respective endpoint is enabled from a disabled state. The buffer status flags get updated when one of the following events occurs: 1. The USB FCU successfully sends out a data set to the host. 2. The CPU loads a data set to the buffer (writes a "1" to SET_IN_BUF_RDY). 3. The CPU writes a "1" to the FLUSH bit or a hardware auto flush takes place.
• INxCSR2 (UNDER_RUN): A status flag, "1" indicates an under run has occurred in an isochronous data transfer. The USB FCU updates this flag to a "1" at the beginning of an IN token if no data packet is in the buffer.
• INxCSR3 (SET_IN_BUF_RDY): The CPU writes a "1" to this bit after loading a data set to the buffer. The CPU can only load data to the buffer and set this bit when INxCSR1 (IN_BUF_STS1) is a "0".
• INxCSR4 (CLR_UNDER_RUN): The CPU writes a "1" to this bit to clear the UNDER_RUN status flag.
• INxCSR5 (TOGGLE_INIT): The CPU writes a "1" to this bit to initialize the data sequence, force the next packet’s data PID to a DATA0 for transmis- sion. Setting the TOGGLE_INT bit also resets the FIFO read/write pointers.
• INxCSR5 (TOGGLE_INIT): The CPU writes a "1" to this bit to initialize the data sequence, force the next packet’s data PID to a DATA0 for transmis- sion. Setting the TOGGLE_INT bit also resets the FIFO read/write pointers. Bit Symbol Bit Name Function R W Must always be "0" O O Symbol EP0WC Address 029C16 When reset 000016 USB Endpoint 0 Write Count register (b15) (b8) EP0WC7-0 b7 b0 0000000 Receive byte count O X Reserved

M30245 Group Universal Serial Bus Rev.2.00 Oct 16, 2006 page 91 of 264 REJ03B0005-0200

• INxCSR6 (FLUSH): The CPU writes a "1" to this bit to flush the IN buffer.
• When there is one data set in the IN buffer, a flush causes the IN buffer to be empty.
• When there are two data sets in the IN buffer, a flush causes the older data set to be flushed out from the IN buffer. The USB FCU updates the buffer status bits the same way as a data set is transmitted to the host when it sees a FLUSH. Setting the FLUSH bit during transmission could produce unpredictable results.
• INxCSR7 (INTPT): The CPU writes a "1" to this bit to initialize the endpoint as a rate feedback interrupt endpoint.
• INxCSR8 (ISO): The CPU writes a "1" to this bit to set the endpoint as an isochronous data transfer endpoint.
• INxCSR9 (SEND_STALL): The CPU writes a "1" to this bit when the endpoint is stalled (transmitter halt). The USB FCU returns STALL handshakes while this bit is set. The CPU writes a "0" to clear this bit, If the STALL condition no longer exists.
• INxCSR10 (AUTO_SET): The CPU writes a "1" to this bit to enable the AUTO_SET function. AUTO_SET takes place only when a data packet that is equal to MAXP (or data set that is equal to BUF_SIZ, in continuous mode) is loaded to the buffer. See "IN (Transmit) FIFO" operation for details. Figure 1.58. USB Endpoint x IN Control & Status register (EPxICS) Bit Symbol Bit Name Function R W Symbol EPxICS (x = 1 - 4) Address 029E16, 02A416, 02AA16, 02B016 When reset 000316 USB Endpoint x IN Control and Status register (b15) (b8) INxCSR0 INxCSR1 INxCSR2 INxCSR3 INxCSR4 INxCSR5 INxCSR6 INxCSR7 INxCSR8 INxCSR9 INxCSR10 Reserved b7 b0 IN_BUF_STS0 flag IN_BUF_STS1 flag UNDER-RUN flag SET_IN_BUF_RDY CLR_UNDER_RUN TOGGLE_INT FLUSH INTPT ISO SEND_STALL AUTO_SET O X O O O X O O O O O O O O O O O O O O O O These two bits indicate the EPx IN buffer status Bit1 Bit0 0 0 : No data set in the IN buffer 0 1 : Single buffer mode: N/A Double buffer mode: one data set in the IN buffer 1 0 : Single buffer mode: N/A Double buffer mode: N/A 1 1 : Single buffer mode: one data set in the IN buffer Double buffer mode: two data sets in the IN buffer 0 : No underrun detected 1 : Underrun detected 0 : No action 1 : Data set loaded to the IN buffer (updates IN buffer status flags) 0 : No action 1 : Clears UNDER_RUN flag 0 : No action 1 : Initialize the next data PID as a DATA0 for transmission 0 : No action 1 : Flush out one data set 0 : Select non-rate feedback interrupt transfer 1 : Select rate feedback interrupt transfer 0 : Select non-isochronous endpoint 1 : Select isochronous endpoint 0 : No STALL by CPU 1 : STALL by CPU 0 : AUTO_SET disabled 1 : AUTO_SET enabled Must always be set to "0" Note Note Note Note Note: Always read a "0" 0 0 00 O X

M30245 Group Universal Serial Bus Rev.2.00 Oct 16, 2006 page 92 of 264 REJ03B0005-0200 USB Endpoint x IN MAXP Register (x = 1 to 4) The USB Endpoint x IN MAXP Register, shown in Figure 1.59, indicates the maximum packet size (MAXP) of EPx IN packet. The default values for all EPx IN MAXP are 0 bytes. Figure 1.59. USB Endpoint x IN MAXP register (EPxIMP) Bit Symbol Bit Name Function R W Must always be "0" O O Symbol EPxIMP ( x = 1 - 4) Address 02A016, 02A616, 02AC16, 02B216 When reset 000016 USB Endpoint x IN MAXP register (b15) (b8) IMAXP9-0 b7 b0 00000 Maximum packet size O O Reserved USB Endpoint x IN FIFO configuration Register (x = 1 to 4) The USB Endpoint x IN FIFO Configuration Register, shown in Figure 1.60, is used to select various FIFO configura- tions. When the double buffer bit is set, the effective buffer size = 2 x BUF_SIZ. Therefore other EP FIFO buffer’s starting locations have to be 2 x BUF_SIZ apart. The user should ensure:

• Buffer Starting Location + Buffer Size do not exceed the 3K byte boundary.
• Endpoint buffers do not overlap with each other.Figure 1.60. USB Endpoint x IN FIFO Configuration register (EPxIFC) Bit Symbol Bit Name Function R W O O Symbol EPxIFC (x = 1 - 4) Address 02A216, 02A816, 02AE16, 02B416 When reset 000016 USB Endpoint x IN FIFO Configuration register (b15) (b8) BUF_NUM BUF_SIZ DBL_BUF CONTINUE Reserved b7 b0 000 FIFO buffer start number FIFO buffer size Double buffer mode Continuous transfer mode O O Select the starting number for the EPx IN FIFO (in units of 64 bytes) 000000 : buffer starting location = 0 000001 : buffer starting location = 64 000010 : buffer starting location = 128 101111 : buffer starting location = 3008 (last starting number) Select the buffer size for the EPx IN FIFO (in units of 64 bytes) 0000 : buffer size = 64 0001 : buffer size = 128 0010 : buffer size = 192 1111 : buffer size = 1024 (largest buffer size) 0 : Disabled 1 : Enabled 0 : Disabled (Note) 1 : Enabled Must always be set to "0" O O O O O O Note: Valid for bulk transfer type only

M30245 Group Universal Serial Bus Rev.2.00 Oct 16, 2006 page 93 of 264 REJ03B0005-0200 USB Endpoint x OUT CSR (x = 1 to 4) The USB Endpoint x OUT CSR (Control and Status Register), shown in Figure 1.61, contains control and status information for the respective OUT EP 1-4.

• OUTxCSR0 (OUT_BUF_STS0) and OUTxCSR1 (OUT_BUF_STS1): Two status flags, indicate the current status of the OUT buffer. The buffer status flags are updated when one of the following events occurs: 1. The USB FCU successfully receives a data set from the host. 2. The CPU unloads a data set from the buffer (writes a "1" to CLR_OUT_BUF_RDY). 3. The CPU writes a "1" to the FLUSH bit.
• OUTxCSR2 (OVER_RUN): A status flag, "1" indicates an over run has occurred in an isochronous data transfer. The USB FCU updates this flag to a "1" at the beginning of an OUT token when two data packets are already present in the buffer.
• OUTxCSR3 (FORCE_STALL): A status flag, "1" indicates that the USB FCU detected a Packet size larger than MAXP violation. The USB FCU returns a STALL as a handshake packet for the current transaction.
• OUTxCSR4 (DATA_ERR): A status flag, "1" indicates a data error (bit stuffing or CRC error) has occurred in an OUT isochronous data packet.
• OUTxCSR5 (CLR_OUT_BUF_RDY): The CPU writes a "1" to this bit after unloading a data set from the buffer. The CPU can only unload data from the buffer and set this bit when OUTxCSR1 (OUT_BUF_STS1) is a "1".
• OUTxCSR6 (CLR_OVER_RUN): The CPU writes a "1" to this bit to clear the OVER_RUN status flag.
• OUTxCSR7 (CLR_FORCE_STALL): The CPU writes a "1" to this bit to clear the FORCE_STALL status flag.
• OUTxCSR8 (CLR_DATA_ERR): The CPU writes a "1" to this bit to clear the DATA_ERR status flag.
• OUTxCSR9 (TOGGLE_INIT): The CPU writes a "1" to this bit to initialize the data sequence, and force the next packet’s data PID to a DATA0 for reception.
• OUTxCSR10 (FLUSH): The CPU writes a "1" to this bit to flush the OUT buffer. This bit must only be set to a "1" when the OUT_BUF_STS1 flag is a "1".
• When there is one data set in the OUT buffer, a flush causes the OUT buffer to be empty.
• When there are two data sets in the OUT buffer, a flush causes the older packet to be flushed from the OUT buffer. The USB FCU updates the buffer status flags the same way as a data set is unloaded from the host when it sees a FLUSH. Setting the FLUSH bit during reception could produce unpredictable results.

M30245 Group Universal Serial Bus Rev.2.00 Oct 16, 2006 page 94 of 264 REJ03B0005-0200 Figure 1.61. USB Endpoint x OUT Control and Status register (EPxOCS)

• OUTxCSR11 (ISO): The CPU writes "1" to this bit to set the endpoint as an isochronous data transfer endpoint.
• OUTxCSR12 (SEND_STALL): The CPU writes "1" to this bit when the endpoint is stalled (receiver halt). The USB FCU returns STALL handshakes while this bit is set. The CPU writes "0" to clear this bit, if the STALL condition no longer exists.
• OUTxCSR13 (AUTO_CLR): The CPU writes "1" to this bit to enable the AUTO_CLR function. AUTO_CLR takes place when a data packet (or a data set, in continuous mode) is unloaded from the buffer, even if the data packet is less than MAXP (or data set is less than BUF_SIZ, in continuous mode). See "OUT (Receive) FIFO" operation for details.Bit Symbol Bit Name Function R W Symbol EPxOCS (x = 1 - 4) Address 02B616, 02BE16, 02C616, 02CE16 When reset 000016 USB Endpoint x OUT Control and Status register (b15) (b8) OUTxCSR0 OUTxCSR1 OUTxCSR2 OUTxCSR3 OUTxCSR4 OUTxCSR5 OUTxCSR6 OUTxCSR7 OUTxCSR8 OUTxCSR9 OUTxCSR10 OUTxCSR11 OUTxCSR12 OUTxCSR13 Reserved b7 b0 OUT_BUF_STS0 flag OUT_BUF_STS1 flag OVER-RUN flag FORCE_STALL flag DATA_ERR flag CLR_OUT_BUF_RDY CLR_OVER_RUN CLR_FORCE_STALL CLR_DATA_ERR TOGGLE_INIT FLUSH ISO SEND_STALL AUTO_CLR O X O O O X O X O X O O O O O O O O O O These two bits indicate the EPx OUT buffer status: Bit1 Bit0 0 0 : No data set in the OUT buffer 0 1 : Single buffer mode: N/A Double buffer mode: N/A 1 0 : Single buffer mode: N/A Double buffer mode: one data set in the OUT buffer 1 1 : Single buffer mode: one data set in the OUT buffer Double buffer mode: two data sets in the OUT buffer 0 : No over run detected 1 : Over run detected 0 : No packet size larger than MAXP violation detected 1 : Packet size larger than MAXP violation detected 0 : No data error detected 1 : Data error detected 0 : No action 1 : Data set unloaded from the OUT buffer (updates status flags) 0 : No action 1 : Clears OVER_RUN flag 0 : No action 1 : Clears FORCE_STALL flag 0 : No action 1 : Clears DATA_ERR flag 0 : No action 1 : Initialize the next data PID as a DATA0 for reception 0 : No action 1 : Flush out one data set 0 : Select non-isochronous endpoint 1 : Select isochronous endpoint 0 : No STALL by CPU 1 : STALL by CPU 0 : AUTO_CLR disabled 1 : AUTO_CLR enabled Must always be set to "0" Note Note Note: Always read a "0" when writing to this bit O X O O Note O O Note O O Note O O Note

M30245 Group Universal Serial Bus Rev.2.00 Oct 16, 2006 page 97 of 264 REJ03B0005-0200 USB Endpoint x OUT FIFO Data Register (x = 0 to 4) The USB Endpoint x OUT FIFO Data Registers, shown in Figure 1.66 are the USB OUT (receive) FIFO data registers. The CPU reads data from these registers for the respective Endpoint OUT FIFO. Figure 1.66. USB Endpoint x OUT FIFO Data register (EPxO) Bit Symbol Bit Name Function R W Symbol EPxO (x = 0 - 4) Address 02E216, 02E616, 02EA16, 02EE16, 02F216 When reset N/A USB Endpoint x OUT FIFO Data register (b15) (b8) DATA_15-0 b7 b0 EP0 OUT FIFO Data O X Note 1: Writing to this register might cause a system error. Note 2: Read only from this register with a Word command or a Byte command to the lower 8 bits. Do not read a byte of data from the upper 8 bits. (b8 - b15)

Rev.2.00 Oct 16, 2006 page 101 of 264 REJ03B0005-0200 Table 1.37. DMAC specifications Item Specification No. of channels 4 (cycle steal method) Transfer memory space From any address in the 1M bytes space to a fixed address [002016 to 003F16 and 018016 to 019F16] cannot be accessed) Maximum No. of bytes transferred 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers) DMA request factors (Note) Falling edge of INT0, INT1, INT2 or both edges Timer A0 to Timer A4 interrupt requests UART0-3 transfer and receive interrupt requests A/D conversion interrupt request Software triggers Serial Sound Interface 0-1 transmit and receive interrupt Channel priority High to low priority: DMA0, DMA1, DMA2, DMA3 Transfer unit 8 bits or 16 bits Transfer address direction Forward/fixed (forward direction cannot be specified for both source and destination simultaneously) Transfer mode Single transfer mode After the transfer counter underflows, the DMA enable bit is set to "0" and the DMAC becomes inactive Repeat transfer mode After the transfer counter underflows, the value of the transfer counter reload register is reloaded to the transfer counter. The DMAC remains active unless a "0" is written to the DMA enable bit. DMA interrupt request generation timing When an underflow occurs in transfer counter Active When the DMA enable bit is set to "1", the DMAC is active. When the DMAC is active, data transfer starts each time the DMA transfer request signal occurs. Inactive When the DMA enable bit is set to "0", the DMAC is inactive After the transfer counter underflows in single transfer mode. Forward address pointer and reload timing for transfer counter When data transfer starts immediately after turning DMAC active, or when the transfer counter underflows in repeat transfer mode, the value of the source pointer or destination pointer (whichever is specified for forward direction) is reloaded to the forward direction address pointer, and the value of the transfer counter reload register is reloaded to the transfer counter. Writing to register Registers specified for forward direction transfer are always write enabled. Registers specified for fixed address transfer are write-enabled when the DMA enable bit is "0". Reading the register Can be read at any time. However, when the DMA enable bit is "1", reading the register set-up as the forward register is the same as reading the value of the forward address pointer. Note: DMA transfer is not effective to any interrupts. DMA transfer is not affected by the interrupt enable flag (I flag) or by the interrupt priority level. DM Atriggers From a fixed address to any address in the 1M bytes space From a fixed address to a fixed address (note that DMA related registers USB triggers, selectable by endpoint

Rev.2.00 Oct 16, 2006 page 102 of 264 REJ03B0005-0200 Figure 1.71. DMAC register (1) Bit Symbol Bit Name Function R W DSEL0 DSEL1 DSEL2 DSEL3 DSEL4 b4 b3 b2 b1 b0 0 0 0 0 0 : Disabled 0 0 0 0 1 : INT0 (falling edge) 0 0 0 1 0 : INT0 (two edges) 0 0 0 1 1 : USB0 0 0 1 0 0 : Timer A0 0 0 1 0 1 : Timer A1 0 0 1 1 0 : Timer A2 0 0 1 1 1 : Timer A3 0 1 0 0 0 : Timer A4 0 1 0 0 1 : UART0 receive/ACK/SSI0 receive 0 1 0 1 0 : UART1 receive/ACK/SSI1 receive 0 1 0 1 1 : UART2 receive/ACK 0 1 1 0 0 : UART3 receive/ACK 0 1 1 0 1 : UART0 transmit/NACK/SSI0 transmit 0 1 1 1 0 : UART1 transmit/NACK/SSI1 transmit 0 1 1 1 1 : UART2 transmit/NACK 1 0 0 0 0 : UART3 transmit/NACK 1 0 0 0 1 : A/D 1 0 0 1 0 : Disabled 1 0 0 1 1 : DMA1 1 0 1 0 0 : DMA2 1 0 1 0 1 : DMA3 1 0 1 1 0 : Disabled 1 0 1 1 1 : Disabled 1 1 x x x : Disabled O O Symbol DM0SL Address 03B8 When reset 0016 DMA0 request cause select register (Note) b7 b5b6 b4 b3 b2 b1 b0 Nothing is assigned. Write "0" when writing to these bits. The value is "0" when read. DSR O O DMA request cause select bits O O O O O O _ _ O OSoftware DMA request bit Software trigger is always enabled Write "1" to trigger DSR bit. Bit Symbol Bit Name Function R W DSEL0 DSEL1 DSEL2 DSEL3 DSEL4 b4 b3 b2 b1 b0 0 0 0 0 0 : Disabled 0 0 0 0 1 : INT1 (falling edge) 0 0 0 1 0 : INT1 (two edges) 0 0 0 1 1 : USB1 0 0 1 0 0 : Timer A0 0 0 1 0 1 : Timer A1 0 0 1 1 0 : Timer A2 0 0 1 1 1 : Timer A3 0 1 0 0 0 : Timer A4 0 1 0 0 1 : UART0 receive/ACK/SSI0 receive 0 1 0 1 0 : UART1 receive/ACK/SSI1 receive 0 1 0 1 1 : UART2 receive/ACK 0 1 1 0 0 : UART3 receive/ACK 0 1 1 0 1 : UART0 transmit/NACK/SSI0 transmit 0 1 1 1 0 : UART1 transmit/NACK/SSI1 transmit 0 1 1 1 1 : UART2 transmit/NACK 1 0 0 0 0 : UART3 transmit/NACK 1 0 0 0 1 : A/D 1 0 0 1 0 : DMA0 1 0 0 1 1 : Disabled 1 0 1 0 0 : DMA2 1 0 1 0 1 : DMA3 1 0 1 1 0 : Disabled 1 0 1 1 1 : Disabled 1 1 x x x : Disabled O O Symbol DM1SL Address 03BA When reset 0016 DMA1 request cause select register (Note) b7 b5b6 b4 b3 b2 b1 b0 Nothing is assigned. Write "0" when writing to these bits. The value is "0" when read. DSR O O DMA request cause select bits O O O O O O _ _ O OSoftware DMA request bit Software trigger is always enabled Write "1" to trigger DSR bit. Note: Software is always enabled. Note: Software is always enabled.

Rev.2.00 Oct 16, 2006 page 103 of 264 REJ03B0005-0200 Figure 1.72. DMAC register (2) Bit Symbol Bit Name Function R W DSEL0 DSEL1 DSEL2 DSEL3 DSEL4 b4 b3 b2 b1 b0 0 0 0 0 0 : Disabled 0 0 0 0 1 : INT2 (falling edge) 0 0 0 1 0 : INT2 (two edges) 0 0 0 1 1 : USB2 0 0 1 0 0 : Timer A0 0 0 1 0 1 : Timer A1 0 0 1 1 0 : Timer A2 0 0 1 1 1 : Timer A3 0 1 0 0 0 : Timer A4 0 1 0 0 1 : UART0 receive/ACK/SSI0 receive 0 1 0 1 0 : UART1 receive/ACK/SSI1 receive 0 1 0 1 1 : UART2 receive/ACK 0 1 1 0 0 : UART3 receive/ACK 0 1 1 0 1 : UART0 transmit/NACK/SSI0 transmit 0 1 1 1 0 : UART1 transmit/NACK/SSI1 transmit 0 1 1 1 1 : UART2 transmit/NACK 1 0 0 0 0 : UART3 transmit/NACK 1 0 0 0 1 : A/D 1 0 0 1 0 : DMA0 1 0 0 1 1 : DMA1 1 0 1 0 0 : Disabled 1 0 1 0 1 : DMA3 1 0 1 1 0 : Disabled 1 0 1 1 1 : Disabled 1 1 x x x : Disabled O O Symbol DM2SL Address 03B016 When reset 0016 DMA2 request cause select register (Note) b7 b5b6 b4 b3 b2 b1 b0 Nothing is assigned. Write "0" when writing to these bits. The value is "0" when read. DSR O O DMA request cause select bits O O O O O O _ _ O OSoftware DMA request bit Software trigger is always enabled Write "1" to trigger DSR bit. Bit Symbol Bit Name Function R W DSEL0 DSEL1 DSEL2 DSEL3 DSEL4 b4 b3 b2 b1 b0 0 0 0 0 0 : Disabled 0 0 0 0 1 : INT0 (falling edge) 0 0 0 1 0 : INT0 (two edges) 0 0 0 1 1 : USB3 0 0 1 0 0 : Timer A0 0 0 1 0 1 : Timer A1 0 0 1 1 0 : Timer A2 0 0 1 1 1 : Timer A3 0 1 0 0 0 : Timer A4 0 1 0 0 1 : UART0 receive/ACK/SSI0 recieve 0 1 0 1 0 : UART1 receive/ACK/SSI1 receive 0 1 0 1 1 : UART2 receive/ACK 0 1 1 0 0 : UART3 receive/ACK 0 1 1 0 1 : UART0 transmit/NACK/SSI0 transmit 0 1 1 1 0 : UART1 transmit/NACK/SSI1 transmit 0 1 1 1 1 : UART2 transmit/NACK 1 0 0 0 0 : UART3 transmit/NACK 1 0 0 0 1 : A/D 1 0 0 1 0 : DMA0 1 0 0 1 1 : DMA1 1 0 1 0 0 : DMA2 1 0 1 0 1 : Disabled 1 0 1 1 0 : Disabled 1 0 1 1 1 : Disabled 1 1 x x x : Disabled O O Symbol DM3SL Address 03B216 When reset 0016 DMA3 request cause select register (Note) b7 b5b6 b4 b3 b2 b1 b0 Nothing is assigned. Write "0" when writing to these bits. The value is "0" when read. DSR O O DMA request cause select bits O O O O O O _ _ O OSoftware DMA request bit Software trigger is always enabled Write "1" to trigger DSR bit. Note: Software is always enabled. Note: Software is always enabled.

Rev.2.00 Oct 16, 2006 page 104 of 264 REJ03B0005-0200 Figure 1.73. DMAC register (3) b7 b3 b0 b7 b0 b7 b0 DMAi source pointer (i=0-3) Symbol SAR0 SAR1 SAR2 SAR3 Address 0022 16 to 002016 003216 to 003016 018216 to 018016 019216 to 019016 When reset Indeterminate Indeterminate Indeterminate Indeterminate Function Transfer count specification Source pointer stores the source address Nothing is assigned. Write "0" when writing to these bits. The value is "0" if read. 00000 16 to FFFFF16 R W O O _ _ Bit Name Function R W DMBIT DMASL DMAS DMAE DSD DAD 0 : 16 bits 1 : 8 bits 0 : Single transfer 1 : Repeat transfer 0 : DMA not requested 1 : DMA requested 0 : Disabled 1 : Enabled 0 : Fixed 1 : Forward 0 : Fixed 1 : Forward O O Symbol DMiCON (i=0-3) Address 002C 16, 003C16, 018C16, 019C16 When reset 00000X002 DMAi control register b7 b5b6 b4 b3 b2 b1 b0 Nothing is assigned. Write "0" when writing to these bits. The value is "0" when read. O O Transfer unit select bit Repeat transfer mode select bit DMA request bit (Note 1) DMA enable bit Source address direction select bit (Note 3) Destination address direction select bit (Note 3) O O O O O O _ _ O O Note 1: DMA request can be cleared by resetting the bit. Note 2: This bit can only be set to "0". Note 3: Source address direction select bit and destination address direction select bit cannot be set to "1" simultaneously. Bit Symbol (b15) (b8) DMAi transfer counter (i=0-3) Symbol TCR0 TCR1 TCR2 TCR3 Address 0029 16 to 002816 003916 to 003816 018916 to 018816 019916 to 019816 When reset Indeterminate Indeterminate Indeterminate Indeterminate Function Transfer count specification Transfer counter Set a value one less than the transfer count 0000 16 to FFFF16 R W O O b7 b3 b0 b7 b0 b7 b0 DMAi destination pointer (i=0-3) Symbol DAR0 DAR1 DAR2 DAR3 Address 0026 16 to 002416 003616 to 003416 018616 to 018416 019616 to 019416 When reset Indeterminate Indeterminate Indeterminate Indeterminate Function Transfer count specification Destination pointer stores the destination address Nothing is assigned. Write "0" when writing to these bits. The value is "0" if read. 00000 16 to FFFFF16 R W O O _ _ b7 b0b7 b0 (Note 2)

Rev.2.00 Oct 16, 2006 page 105 of 264 REJ03B0005-0200 Transfer modes Single transfer mode DMA transfer occurs until the tranfer counter underflows. Afterward, the DMA becomes inactive. Repeat transfer mode The DMA remains active even after the transfer counter underflows. The transfer counter and forward direction address pointer are reloaded after each transfer counter underflow. The DMA becomes inactive when "0" is written to the DMA enable bit. DMA enable bit Setting the DMA enable bit to "1" makes the DMAC active. If data transfer starts immediately after the DMAC is turned active, the following operations are carried out: (1) Reloads the value of either the source pointer or the destination pointer - the one specified for the forward direction - to the forward direction address pointer. (2) Reloads the value of the transfer counter reload register to the transfer counter. Thus writing "1" to the DMA enable bit with the DMAC being active carries out the operations given above, so the DMAC operates again from the initial state at the instant "1" is written to the DMA enable bit. DMA request bit The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of DMA request causes for each channel (DMiSL registers). DMA request causes include the following.

• Internal causes triggered by using the interrupt request signals from the built-in peripheral functions and software DMA request all controlled by software.
• External causes effected by utilizing the input from external interrupt signals. For the selection of DMA request causes, see the descriptions of the DMAi request cause select registers. The DMA request bit turns to "1" if the DMA transfer request signal occurs regardless of the DMAC's state (regardless of whether the DMA enable bit is set "1" or to "0"). It turns to "0" immediately before data transfer starts. In addition, this bit can be set to "0" by software, but it cannot be set to "1". There can be instances in which a change in the DMA request cause selection bits causes the DMA request bit to turn to "1". Make sure to set the DMA request bit to "0" after the DMA request cause selection bits are changed. The DMA request bit turns to "1" if a DMA transfer request signal occurs, and turns to "0" immediately before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the DMA request bit, if read by software, turns out to be "0" in most cases. To examine whether the DMAC is active, read the DMA enable bit. The timing changes of the DMA request bit are discussed in the following section.

Rev.2.00 Oct 16, 2006 page 107 of 264 REJ03B0005-0200 Transfer cycle The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) and the bus cycle in which the data is written to memory or to the SFR area (destination write). The number of read and write bus cycles depends on the source and destination addresses. In memory expansion mode and microprocessor mode, the number of read and write bus cycles also depends on the level of the BYTE pin. Also, the bus cycle is longer when software waits are inserted. Effect of source and destination addresses When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there are one more source read cycle and destination write cycle than when the source and destination both start at even addresses. Effect of BYTE pin level When transferring 16-bit data over an 8-bit data bus (BYTE pin = H") in memory expansion mode and microprocessor mode, the 16 bits of data are sent in two 8-bit blocks. Therefore, two bus cycles are required for reading the data and two are required for writing the data. Also, in contrast to when the CPU accesses internal memory, when the DMAC accesses internal memory (internal ROM, internal RAM, and SFR), these areas are accessed using the data size selected by the BYTE pin. Effect of software wait When the SFR area or a memory area with a software wait is accessed, the number of cycles is increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK. Figure 1.75 shows the example of the transfer cycles for a source read. For convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respective conditions to both the destination write cycle and the source read cycle. For example, if data is being transferred in 16-bit units on an 8-bit bus (2), two bus cycles are required for both the source read cycle and the destination write cycle. Transfer cycle calculations Any combination of even or odd transfer read and write addresses is possible. Table 1.38a shows the number of DMAC transfer cycles. Table 1.38b shows the Coefficient j,k. The number of DMAC transfer cycles calculation is: No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k

Rev.2.00 Oct 16, 2006 page 108 of 264 REJ03B0005-0200 Figure 1.75. Example of the transfer cycles for a source read BCLK Address bus RD WR Data bus CPU use CPU use CPU use CPU useSource Source Destination Destination (1) 8-bit transfers 16-bit transfers from even address and the source address is even. BCLK Address bus RD WR Data bus CPU use CPU use CPU use CPU useSource Source Destination Destination (3) One wait is inserted into the source read under the conditions in (1) BCLK Address bus RD WR Data bus CPU use CPU use CPU use CPU useSource Source Destination Destination Source + 1 Source + 1 (2) 16-bit transfers and the source address is odd BCLK Address bus RD WR Data bus CPU use CPU use CPU use CPU useSource Source Destination Destination Source + 1 Source + 1 (4) One wait is inserted into the source read under the conditions in (2) Note : The same timing changes occur with the respective conditions at the destination as at the source. Dummy cycle Dummy cycle Dummy cycle Dummy cycle Dummy cycle Dummy cycle Dummy cycle Dummy cycle Transferring 16-bit data on an 8-bit data bus (In this case, there are two destination write cycles) (When 16-bit data is transferred on an 8-bit data bus, there are two destination write cycles)

Rev.2.00 Oct 16, 2006 page 109 of 264 REJ03B0005-0200 Table 1.38a. DMA transfer cycles Internal memory External memory Internal ROM/RAM SFR area with wait (Note 1) 3 waits 1 23 4 1j k no wait 1 2 2 waits1 wait 2 342 Note 1: Depends on the value set in the CSE register. Transfer unit Bus width Access address Single-chip mode Memory expansion mode Microprocessor mode No. of read cycles No. of write cycles No. of read cycles No. of write cycles 8-bit transfers (DMBIT = "1") 16-bit (BYTE = "L") Even 1 Odd 1 Even Odd 16-bit transfers (DMBIT = "0") Even Odd Even Odd 111 111 _ _ 11 _ _ 11 1 111 2 222 _ _ 22 _ _ 22 16-bit (BYTE = "L") 8-bit (BYTE = "H") 8-bit (BYTE = "H") Table 1.38b. Coefficient j,k Precautions Writing to the DMAE bit in DMiCON register If the following conditions are met: The DMAE bit is set to "1" again while it is already set to "1" (DMAi is in active state). A DMA request may occur simultaneously when the DMAE bit is being written. Follow the steps below: Step 1: Write "1" to the DMAE bit and DMAS bit in DMiCON register simultaneously (Note 1). Step 2: Make sure that the DMAi is in an initial state (Note 2) in a program. If the DMAi is not in an initial state, the above steps should be repeated. Note 1: The DMAS bit remains unchanged even if "1" is written. However, if "0" is written to this bit, it is set to "0" (DMA not requested). In order to prevent the DMAS bit from being modified to "0", "1" should be written to the DMAS bit when "1" is written to the DMAE bit. In this way the state of the DMAS bit immediately before being written can be maintained. Similarly, when writing to the DMAE bit with a read-modify-write instruction, "1" should be written to the DMAS bit in order to maintain a DMA request which is generated during execution. Note 2: Read the TCRi register to verify whether the DMAi is in an initial state. If the read value is equal to a value which was written to the TCRi register before DMA transfer start, the DMAi is in an initial state. (If a DMA request occurs after writing to the DMAE bit, the value written to the TCRi register is "1".) If the read value is a value in the middle of a transfer, the DMAi is not in an initial state.

Rev.2.00 Oct 16, 2006 page 111 of 264 REJ03B0005-0200 Figure 1.77. Timer A block diagram (2)

• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode TA 0IN TA 1IN TA 2IN TA 3IN TA 4IN Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 f1 f8 f32 fC32 Timer A0 interrupt Timer A1 interrupt Timer A2 interrupt Timer A3 interrupt Timer A4 interrupt Noise filter Noise filter Noise filter Noise filter Noise filter 1/32 fC32 f32 XIN XCIN Clock prescaler reset flag (bit 7 at address 038116) set to "1" Reset Clock prescaler

Rev.2.00 Oct 16, 2006 page 112 of 264 REJ03B0005-0200 Figure 1.78. Timer A-related registers (1) Function R W Timer Ai register (i = 0 to 4) (Note 1) b8)(b15 O O O O X O X O X O 16-bit counter (set to divide ratio) 16-bit counter (set to divide ratio) (Note 2) 16-bit counter (set to one-shot width) (Note 6) 16-bit PWM (set to PWM pulse "H" width) (Note 4, 7) Low-order bits: 8-bit prescaler (set to PWM period) (Notes 5, 7) High-order bits : 8-bit PWM (set to PWM pulse "H" width) (Notes 5, 7) 0000 16 to FFFF16 Values that can be set 000016 to FFFF16 000016 to FFFF16 000016 to FFFF16 0016 to FE16 (Both high-order and low-order addresses) (Note 3) Note 1 : Read and write data in 16-bit units. Note 2 : Counts pulses from an external source or timer overflow. Note 3 : Use MOV instruction to write to this register. Note 4 : When setting value is n, PWM period and "H" width of PWM pulses are: PWM period : (2 16 - 1)/fi PWM pulse "H" width : n/fi Note 5 : When setting value of high-order address is n and setting value of low- order address is m, PWM period and "H" width of PWM pulse are: PWM period : (2 PWM pulse "H" width : (m + 1)n/fi Note 6 : When the Timer Ai register is set to "000016", the counter does not operate and the Timer Ai interrupt request is not generated. When the pulse is set to output, the pulse is not output from the TAiOUT pin. Note 7 : When the Timer Ai register is set to "0000 16", the pulse width modulator does not operate and the output level of the TAiOUT pin remains "L" level, therefore the Timer Ai interrupt request is not generated. This also occurs in the 8-bit pulse width modulator mode when the significant 8 high-order bits in the Timer Ai register are set to "00 16". b7 b0 Symbol TA0 TA1 TA2 TA3 TA4 Address 0387 16, 038616, 038916, 038816, 038B16, 038A16, 038D16, 038C16, 038F16, 038E16 When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate (Note 3) (Note 3) Bit Symbol Bit Name Function R W TA1TGL Timer A1 event/trigger select bit Symbol TRGSR Address 0383 When reset 0016 Trigger select register b7 b5b6 b4 b3 b2 b1 b0 O O TA1TGH TA2TGL TA2TGH TA3TGL TA3TGH TA4TGL TA4TGH O O O O O O O O O O O O O O Timer A2 event/trigger select bit Timer A3 event/trigger select bit Timer A4 event/trigger select bit 0 0 : Input on TA1 IN is selected (Note) 0 1 : Invalid 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected b1 b0 0 0 : Input on TA2IN is selected (Note) 0 1 : Invalid 1 0 : TA1 overflow is selected 1 1 : TA3 overflow is selected b3 b2 0 0 : Input on TA3IN is selected (Note) 0 1 : Invalid 1 0 : TA2 overflow is selected 1 1 : TA4 overflow is selected b5 b4 0 0 : Input on TA4IN is selected (Note) 0 1 : Invalid 1 0 : TA3 overflow is selected 1 1 : TA0 overflow is selected b7 b6 Note: Set the corresponding port direction register to "0" Timer mode Event counter mode One-shot timer mode 16-bit PWM 8-bit PWM Mode

Rev.2.00 Oct 16, 2006 page 113 of 264 REJ03B0005-0200 Figure 1.79. Timer A-related registers (2) Bit Symbol Bit Name Function R W TA0S Timer A0 count start flag Symbol TABSR Address 038016 When reset XXX0000016 Count start flag b7 b5b6 b4 b3 b2 b1 b0 O O TA1S TA2S TA3S TA4S O O O O O O O O _ _ Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag 0 : Stops counting 1 : Starts counting Bit Symbol Bit Name Function R W TMOD0 Operation mode select bit Symbol TAiMR (i=0 to 4) Address 0396 16 to 039A16 When reset 00000X002 Timer Ai mode register (i = 0 to 4) b7 b5b6 b4 b3 b2 b1 b0 O O TMOD1 O O O O O O O O O O O O 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : PWM mode b1 b0 MR0 MR1 MR2 MR3 TCK0 TCK1 Function varies with each mode operation Count source select bit Function varies with each mode operation Bit Symbol Bit Name Function R W CPSR Clock prescaler reset flag 0 : No effect 1 : Reset (The value is "0" when read) O O Symbol CPSRF Address 0381 When reset 0XXXXXXX2 Clock prescaler reset flag b7 b5b6 b4 b3 b2 b1 b0 Nothing is assigned. Write "0" when writing to these bits. The value is indeterminate if read. _ _ O O Nothing is assigned. Write "0" when writing to these bits. The value is indeterminate if read.

Rev.2.00 Oct 16, 2006 page 114 of 264 REJ03B0005-0200 Figure 1.80. Timer A-related register (3) Bit Symbol Bit Name Function R W TA0UD Timer A0 up/down flag Symbol UDF Address 038416 When reset 0016 Up/down flag (Note) b7 b5b6 b4 b3 b2 b1 b0 O O TA1UD TA2UD TA3UD TA4UD TA2P TA3P TA4P O O O O O O O O O O O Timer A1 up/down flag Timer A2 up/down flag Timer A3 up/down flag Timer A4 up/down flag Timer A2 two-phase pulse signal processing select bit 0 : Down count 1 : Up count Timer A3 two-phase pulse signal processing select bit Timer A4 two-phase pulse signal processing select bit This specification becomes valid when the up/down flag content is selected for up/down switching cause 0 : Disabled 1 : Enabled When not using the two-phase pulse signal processing function, set the select bit to "0" Note : Use MOV instruction to write to this register Bit Symbol Bit Name Function R W TA0OS O O Symbol ONSF Address 038216 When reset 0016 One-shot start flag b7 b5b6 b4 b3 b2 b1 b0 0 0 : Input on TA0IN is selected (Notes 2, 3) 0 1 : Invalid 1 0 : TA4 overflow is selected 1 1 : TA1 overflow is selected O OTA1OS b7 b6 TA2OS TA3OS TA4OS TA0TGL TA0TGH O O O O O O O O O O Timer A0 event/trigger select bit Timer A0 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag 0 : Invalid 1 : Timer start (Note 1) Note 1 : The value is "0" when read. Note 2 : Set the corresponding port direction register to "0". Note 3 : To start count in one-shot timer mode, do not use an extrenal trigger input. Reserved Always set to "0" O O

Rev.2.00 Oct 16, 2006 page 115 of 264 REJ03B0005-0200 Timer mode In this mode, the timer counts an internally generated count source. Timer A in timer mode specifications are shown in Table 1.39. Figure 1.81 shows the Timer Ai mode register in timer mode. Table 1.39. Timer mode specifications Item Specification Count source f1, f8, f32, fc32 Count operation Down count When the timer underflows, it loads the reload register contents before continuing counting Divide ratio 1/(n+1) n: Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing When the timer underflows TAiIN pin function Programmable I/O port or gate input. TAiOUT pin function Programmable I/O port or pulse output. Read from timer Count value can be re ad out by reading Timer Ai register Write to timer When counting is stopped and a value is written to Timer Ai register, it is written to both the reload register and counter Whencountingis in progressand avalue iswritten to Timer Ai register, itis written only to the reload register (to be transferred to counter at the next reload time) Select function Gate function-Counting can be started and stopped by TAiIN pin's input signal Pulse output function-Each time the timer underflows, the TAiOUT pin's polarity isreversed Figure 1.81. Timer Ai mode register in timer mode Bit Symbol Bit Name Function R W TMOD0 Operation mode select bit Symbol TAiMR (i=0 to 4) Address 0396 16 to 039A16 When reset 00000X002 Timer Ai mode register (i = 0 to 4) b7 b5b6 b4 b3 b2 b1 b0 O O TMOD1 O O O O O O O O O O O O 0 0 : Timer mode b1 b0 MR0 MR1 MR2 Count source select bit Gate function select bit

0 X : Gate funciton not available

(TAi IN pin is a normal port pin) (Note 1) 1 0 : Timer counts only when TAiIN pin is held "L" (Note 2) 1 1 : Timer counts only when TAiIN pin is held "H" (Note 2) b4 b3 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fc32 b7 b6 MR3 TCK0 TCK1 0 (Set to "0" in timer mode) Note 1: X value can be "0" or "1" Note 2: Set the corresponding port direction register to "0". Pulse output function select bit 0 : Pulse is not output (TAi OUT pin is a normal port pin) 1 : Pulse is output (TAiOUT pin is a pulse output pin) O O

Rev.2.00 Oct 16, 2006 page 116 of 264 REJ03B0005-0200 Event counter mode In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can count a single- phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase external signal. Table 1.40 lists timer specifications when counting a single-phase external signal. Table 1.41 lists timer specifications when counting a two-phase external signal. Figure 1.82 shows the Timer Ai mode register in event counter mode (excluding two-phase pulse signal processing). Figure 1.83 shows the Timer Ai mode register in event counter mode when using two-phase pulse signal processing. Table 1.40. Event counter mode specifications (excluding two-phase pulse signal) Note: This does not apply when the free-run function is selected Item Specification Count source • External signals input to TAiIN pin (effective edge can be selected by software) TAj overflow Count operation Up count or down count can be selected by external signal or software. When the timer overflows or underflows, it reloads the reload register contents before count- ing continues. (Note) Divide ratio 1/(FFFF16 - n + 1) for up count 1/(n + 1) for down count n: Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing The timer overflows or underflows TAiIN pin function Programmable I/O port or count source input TAiOUT pin function Programmable I/O port, pulse output, or up/down count select input. Read from timer Count value can be re ad out by reading Timer Ai register Write to timer When counting is stopped and a value is written to Timer Ai register, it is written to both the reload register and counter Whencountingis in progressand avalue iswritten to Timer Ai register, itis written only to the reload register (to be transferred to the counter at the next reload time) Select function Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded. Pulse output function Each time the timer overflows or underflows, the TAiOUT pin's polarity is reversed

Rev.2.00 Oct 16, 2006 page 117 of 264 REJ03B0005-0200 Table 1.41. Timer specifications in event counter mode (when processing two-phase pulse signal) Note 1: This does not apply when the free-run function is selected. Note 2: Timer A3 is selectable. Timer A2 is fixed to normal processing operation and Timer A4 is fixed to multiply-by-4 operation. Item Specification Count Source •Two-phase pulse signals input to TAiIN or TAiOUT pin Count operation Up count or down count can be selected by two-phase pulse signal When the timer overflows or underflows, the reload register content is loaded and the timer starts over again (Note 1) Divide ratio 1/ (FFFF16 - n + 1) for up count 1/ (n+1) for down count n: Set value Count start condition Count start flag is set (=1) Count stop condition Count start flag is reset (=0) Interrupt request generation timing Timer overflow or underflows TAi IN pin function Two-phase pulse input TAiOUT pin function Two-phase pulse input Read from timer Count value can be read out by reading Timer A2, A3, or A4 register Writer to timer When counting is stopped and a value is written to Timer A2, A3, or A4 register, it is written to both the reload register and counter When counting is in progress and a value is written to Timer A2, A3, or A4 register, it is written only to the reload register (to be transferred to the counter at the next reload time). Select function Normal processing operation (Timer A2 and A3) The timer counts up rising edges or counts down falling edges on the TAi IN pin when the input signal on the TAiOUT pin is "H" Multiply-by-4 processing operation (Timer A3 and Timer A4) If the phase relationship is such that the TAiIN pin goes "H" when the input signal on the TAiOUT pin is "H", the timer counts up rising and falling edges on the TAiOUT and TAiIN pins. If the phase relationship is such that the TAiIN pin goes "L" when the input signal on the TAiOUT pin is "H", the timer counts down rising and falling edges on the TAiOUT and TAiIN pins. TAiOUT TAiIN (i=2,3) Up count Up count Up count Down count Down count Down count Count up all edges Count down all edges Count down all edgesCount up all edges TAiOUT TAiIN (i=3,4) (Note 2)

Rev.2.00 Oct 16, 2006 page 119 of 264 REJ03B0005-0200 Item Specification Count source f1, f8, f32, fc32 Count operation

• The timer counts down When the count reaches 000016, the timer stops counting after reloading a new count If a trigger occurs when counting, the timer reloads a newcount and restarts counting Divide ratio 1/n n: Set value Count start condition An external trigger is input The timer overflows The one-shot flag is set (=1) Count stop condition A new count is reloaded after the count has reached 000016 The count start flag is reset (=0) Interrupt request generation timing The count reaches 000016 TAiIN pin function Programmable I/O port or trigger input. TAiOUT pin function Programmable I/O port or pulse output. Read from timer When Timer Ai regist er is read, the value is indeterminate. Write to timer When counting has stopped and a value is written to Timer Ai, it is also written to the reload register and counter. When counting is in progress and a value is written to Timer Ai, it is written to only the reload register (Transferred to the counter at next reload time) Bit Symbol Bit Name Function R W TMOD0 Operation mode select bit Symbol TAiMR (i=0 to 4) Address 0396 16 to 039A16 When reset 00000X002 Timer Ai mode register (i = 0 to 4) b7 b5b6 b4 b3 b2 b1 b0 O O TMOD1 O O O O O O O O 1 0 : One shot timer mode b1 b0 MR0 Pulse output function select bit External trigger select bit (Note 1) 0 : Falling edge of TAiIN input signal (Note 2) 1 : Rising edge of TAiIN input signal (Note 2) MR3 TCK0 TCK1 0 (Set to "0" in one-shot timer mode) Note 1: Valid only when the TAiIN pin is selected by the event trigger select bit (addresses 038216, 038316). Note 2: Set the corresponding port direction register to "0". MR1 MR2 Trigger select bit 0 : One-shot start flag is valid 1 : Selected by event/trigger select register O O O O Count operation type select bit b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fc32 0 : Pulse is not output (TAi OUT pin is a normal port pin) 1 : Pulse is output (TAiOUT pin is a pulse output pin) O O One-shot timer mode In this mode, the timer operates only once. Table 1.42 shows the timer specifications for Timer A in one-shot timer mode. When a trigger occurs, the timer starts counting down until it reaches 0000 16. Figure 1.84 shows the Timer Ai mode register in one-shot timer mode. Table 1.42. Timer specifications in one-shot timer mode Figure 1.84. Timer Ai mode register in one-shot timer mode

Rev.2.00 Oct 16, 2006 page 120 of 264 REJ03B0005-0200 Pulse width modulation (PWM) mode In this mode, the timer outputs pulses of a given width in succession. Table 1.43 shows the timer specification for Timer in pulse width modulation mode. In this mode, the counter functions as either a 16-bit pulse width modulator or an 8- bit pulse width modulator. Figure 1.85 shows the Timer Ai mode register in pulse width modulation mode. Figure 1.86 shows an example of how a 16-bit pulse width modulator operates. Figure 1.87 shows an example of how an 8-bit pulse width modulator operates. Count source f1, f8, f32, fc32 Count operation

• The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator) The timer reloads a new count at a rising edge of the PWM pulse and continues counting The timer is not affected by a trigger that occurs when counting 16-bit PWM High level width n/fi n=Set value Cycle time (216-1)/fi fixed 8-bit PWM High level width n X (m+1)/fi n: values set to Timer Ai register's high-order address Cycle time (28-1) X (m+1)/fi m:values set to Timer Ai register's low-order address Count start condition External trigger is input The timer overflows The count start flag is set (=1) Count stop condition The count start flag is reset (=0) Interrupt request generation timing PWM pulse goes "L" TAiIN pin function Programmable I/O port or trigger input TAiOUT pin function Pulse output Two-phase pulse input. Read from timer When Timer Ai is read, the value is indeterminate. Write to timer When counting has stopped and a value is written to Timer Ai, it is written to both the reload register and counter. When counting is in progress and a value is written to Timer Ai, it is written to only the reload register (Transferred to the counter at next reload time) SpecificationItem Table 1.43. Timer specifications in pulse width modulation mode

Rev.2.00 Oct 16, 2006 page 122 of 264 REJ03B0005-0200 Figure 1.87. Example of an 8-bit pulse width modulator operation Count source (Note1) TAiIN pin input signal Underflow signal of 8-bit prescaler (Note2) PWM pulse output from TAiOUT pin "H" "H" "H" "L" "L" "L" "1" "0" Timer Ai interrupt request bit Cleared to "0" when interrupt request is accepted, or cleared by softwarefi : Frequency of count source (f1, f8, f32, fC32) Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Condition : Reload register high-order 8 bits = 0216 Reload register low-order 8 bits = 0216 External trigger (falling edge of TAi IN pin input signal) is selected Note 3: m = 0016 to FE16; n = 0016 to FE16 (m + 1) / fi (n x (m + 1)) / fi

Rev.2.00 Oct 16, 2006 page 123 of 264 REJ03B0005-0200 Precautions Timer mode The value of the counter can be read, with arbitrary timing, by reading the Timer Ai register while a count is in progress. Reading the Timer Ai register with the reload timing gets "FFFF 16". After setting a value in the Timer Ai register, a proper value can be read with the counter stopped before it starts counting Event counter mode The value of the counter can be read, with arbitrary timing, by reading the Timer Ai register while a count is in progress. Reading the Timer Ai register with the reload timing gets "FFFF 16" by underflow or "0000 16" by overflow. After setting a value in the Timer Ai register, a proper value can be read with the counter stopped before it starts counting . Reset the timer when counting has stopped in free run type. If using "Free-Run type", the timer register contents may be unknown when counting begins. Set the timer value immediately after counting has started. Example if the up/down count is not switched:

• Enable the "Reload" function and write to the timer register before counting begins.
• Rewrite the value to the timer register immediately after counting has started.
• If counting up, rewrite "0000 16" to the timer register.
• If counting down, rewrite "FFFF1" to the timer register. This will cause the same operation as "Free-Run type". Example if the up/down count is switched:
• Use the "Reload type" operation until the first count pulse is input.
• Switch to "Free-Run type". One-shot timer mode Setting the count start flag to "0" while a count is in progress causes as the following:
• The counter stops counting and a content of reload register is reloaded.
• The TAi OUT pin outputs "L" level.
• The interrupt request generated and the Timer Ai interrupt request bit goes to"1". The output from the one-shot timer synchronizes with the count source generated internally. Therefore, when an external trigger has been selected, a delay of one cycle of count source (maximum) occurs between the trigger input to the TAi IN pin and the one-shot timer output.

Rev.2.00 Oct 16, 2006 page 124 of 264 REJ03B0005-0200 The Timer Ai interrupt request bit goes to "1" if the timer's operation mode is set using any of the following procedures:

• Selecting one-shot timer mode after reset.
• Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use Timer Ai interrupt (interrupt request bit), set Timer Ai interrupt request bit to "0" after the above listed changes have been made. If a trigger occurs while a count is in progress, after the counter performs one down count following the reoccurrence of a trigger, the reload register contents are reloaded, and the count continues. To generate a trigger while a count is in progress, generate the second trigger after a period longer than one cycle of the timer's count source after the previous trigger occurred. Pulse modulation mode The Timer Ai interrupt request bit becomes "1" if setting operation mode of the timer in compliance with any of the following procedures:
• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode. Therefore, to use Timer Ai interrupt (interrupt request bit), set Timer Ai interrupt request bit to "0" after the above listed changes have been made. Setting the count start flag to "0" while PWM pulses are being output causes the counter to stop counting. If the TAi OUT pin is outputting an "H" level in this instance, the output level goes to "L", and the Timer Ai interrupt request bit goes to "1". If the TAi OUT pin is outputting an "L" level in this instance, the level does not change, and the Timer Ai interrupt request bit does not becomes "1".

M30245 Group Serial Communication Rev.2.00 Oct 16, 2006 page 126 of 264 REJ03B0005-0200 Figure 1.88. UARTi block diagram ni : Values set to UARTi bit rate generator (UiBRG) RxDi Reception control circuit Transmission control circuit 1 / (ni+1) Bit rate generator Clock synchronous type (when internal clock is selected) UART reception Clock synchronous type UART transmission Clock synchronous type Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) Receive clock Transmit clock CLKi CTSi / RTSi f32 Vcc RTSi CTSi TxDiRxD polarity reversing circuit TxD polarity reversing circuit CTS/RTS disabled CTS/RTS disabled CTS/RTS selected CLK polarity reversing circuit Internal External Clock source selection Transmit/ receive unit (Note) Note :UART 2 is not CMOS output but N channel open drain output. SP SP PAR 2SP 1SP UART UART (7 bits) UART (8 bits) UART(7 bits) UART (9 bits) Clock synchronous type Clock synchronous type Data bus low-order bits TxDi UARTi transmit registerPAR disabled PAR enabled D8 D7 D6 D5 D4 D3 D2 D1 D0 UARTItransmit buffer register UART (8 bits) UART (9 bits) Clock synchronous type UARTi receive buffer register UARTi receive register 2SP 1SP UART (7 bits) UART (8 bits) UART(7 bits) UART (9 bits) Clock synchronous type Clock synchronous type RxDi UART (8 bits) UART (9 bits) Address 03AF Address 03AE16 Address 036F16 Address 036E16 Address 033F16 Address 033E16 Address 032F16 Address 032E16 Address 03AB16 Address 03AA16 Address 036B16 Address 036A16 Address 033B16 Address 033A16 Address 032B16 Address 032A16 Data bus high-order bits D7 D6 D5 D4 D3 D2 D1 D0D80000000 SP SP PAR "0" Reverse No reverse Error signal output circuit RxD data reverse circuit Error signal output enable Error signal output disable Reverse No reverse Logic reverse circuit + MSB/LSB conversion circuit Logic reverse circuit + MSB/LSB conversion circuit PAR enabled PAR disabled UART Clock synchronous type TxD data reverse circuitSP : Stop bit PAR : Parity bit i : 0 to 3

M30245 Group Serial Communication Rev.2.00 Oct 16, 2006 page 127 of 264 REJ03B0005-0200 Figure 1.89. Serial I/O-related registers (1) Bit Symbol Function (clock synchronous serial I/O mode) Function (UART mode) R W _ _ Symbol U0TB U1TB U2TB U3TB Address 03AB 16, 03AA16 036B16, 036A16 033B16, 033A16 032B16, 032A16 When reset Indeterminate Indeterminate Indeterminate Indeterminate UARTi transmit buffer register (i= 0 to 3) (Note) (b15) (b8) b0b7 b0 Transmit data X O Nothing is assigned. Write "0" when writing to these bits. The values are indeterminate when read. Bit Symbol Function (clock synchronous serial I/O mode) Function (UART mode) R W _ _ Symbol U0RB U1RB U2RB U3RB Address 03AF 16, 03AE16 036F16, 036E16 033F16, 033E16 032F16, 032E16 When reset Indeterminate Indeterminate Indeterminate Indeterminate UARTi receive buffer register (i= 0 to 3) (b15) (b8) b0b7 b0 O X Nothing is assigned. Write "0" when writing to these bits. The values are indeterminate when read. Note: Use MOV instruction to write to this register. ABT OER FER PER SUM Arbitration lost detecting flag (Note 1) Overrun error flag (Note 2) Framing error flag (Note 2) Parity error flag (Note 2) Error sum flag (Note 2) 0 : Not detected 1 : Detected 0 : No overrrun error 1 : Overrun error Invalid Invalid Invalid Invalid 0 : No overrun error 1 : Overrun error 0 : No framing error 1 : Framing error 0 : No parity error 1 : Parity error 0 : No error 1 : Error Receive data Receive data O O O X O X O X O X Bit name Note 1: Only "0" can be written to this bit. Note 2: Bits 15 to 12 are set to "00002" when the serial I/O mode select bit (bits 0 to 2 at addresses 03A816, 036816, 033816, 032816) are set to "0002" or the receive enable bit is set to "0". Bits 14 and 13 are also set to "0" when the lower byte of the UARTi receive buffer register (addresses 03AE 16, 036E16, 033E16, 032E16) is read. Transmit data X OTransmit data (9th bit) Receive data (9th bit) O X

M30245 Group Serial Communication Rev.2.00 Oct 16, 2006 page 128 of 264 REJ03B0005-0200 Figure 1.90. Serial I/O-related registers (2) Bit Symbol Function (clock synchronous serial I/O mode) Function (UART mode) R W Symbol UiMR (i = 0 to 3) Address 03A816, 036816, 033816, 032816 UARTi transmit/receive mode register (i= 0 to 3) b7 b0 O O When reset 0016 Bit Name SMD0 SMD1 SMD2 CKDIR STPS PRY PRYE IOPOL Serial I/O mode select bit Internal/external clock select bit Stop bit length select bit Odd/even parity select bit Parity enable bit TxD, RxD input/ output polarity switch bit 0 0 0: Serial I/O invalid 0 0 1: Serial I/O mode 0 1 0: I 2C mode Inhibited except in cases listed above 0 : Internal clock 1 : External clock (Note 1) Invalid Invalid Invalid 0 : Normal 1 : Reversed 0 0 0: Serial I/O invalid 1 0 0: Transfer data 7 bits long 1 0 1: Transfer data 8 bits long 1 1 0: Transfer data 9 bits long Inhibited except in cases listed above 0 : Internal clock 1 : External clock (Note 1) 0 : One stop bit 1 : Two stop bits Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled b2 b1 b0 b2 b1 b0 O O O O O O O O O O O O O O When reset Indeterminate Bit Symbol Function Values that can be set R W Symbol UiBRG (i = 0 to 3) Address 03A916, 036916, 033916, 032916 UARTi bit rate generator (i= 0 to 3) (Notes 1, 2) b7 b0 X OAssuming that set values = n, BRGi divides the count source by n + 1 Note 1: Use MOV instruction to write to this register Note 2: Write a value to this register while transmit/receive is stopped. 0016 to FF16 b1b2b3b4b5b6 (Note 2) (Note 3) Note 1: When I2C bus interface mode is selected, set the port direction register for the corresponding port (SCLi) to 0, or the port direction register to 1 and the port data register to 1. When a mode other than serial I/O mode is selected, set the port direction register for the corresponding port (CLKi) to 0. Note 2: Normally set to "0". Note 3: Set the corresponding port direction register to "0" when receiving.

M30245 Group Serial Communication Rev.2.00 Oct 16, 2006 page 129 of 264 REJ03B0005-0200 Figure 1.91. Serial I/O-related registers (3) Bit Symbol Function (clock synchronous serial I/O mode) Function (UART mode) R W Symbol UiC1 (i = 0 to 3) Address 03AD16, 036D16, 033D16, 032D16 UARTi transmit/receive control register 1 (i= 0 to 3) O O When reset 0216 Bit Name TE TI RE RI UiIRS UiRRM UiLCH UiERE Transmit enable bit Transmit buffer empty flag Receive enable bit Receive complete flag UARTi transmit interrupt cause select bit UARTi continuous receive mode enable bit Data logic select bit Error signal output enable bit 0 : Transmit disabled 1 : Transmit enable 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Receive disabled 1 : Receive enabled 0 : No data packet in receive buffer register 1 : Data packet in receive buffer register 0 : Transmit buffer empty (TI =1) 1 : Transmit buffer completed ( TXEPT =1) 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled 0 : No reverse 1 : Reverse O X O O O O O X O O O O O O Set to "0" 0 : Output disabled 1 : Output enabled Bit Symbol Function (clock synchronous serial I/O mode) Function (UART mode) R W Symbol UiC0 (i = 0 to 3) Address 03AC 16, 036C16, 033C16, 032C16 UARTi transmit/receive control register 0 (i= 0 to 3) O O Note 1: Set the corresponding port direction register to "0". Note 2: UART2 transfer pin (TxD2:P7 0 and SCL2:P71) is N-channel open drain output. It cannot be set to CMOS output. Note 3: Valid only in clock synchronous serial I/O mode and 8-bit UART mode. Note 4: The corresponding port register and port direction register are invalid. When reset Bit Name CLK0 CLK1 CRS TXEPT CRD NCH (Note 2) CKPOL UFORM BRG count source select bit CTS/RTS function select bit Transmit register empty flag CTS/RTS disable bit Data output select bit CLK polarity select bit Transfer format select bit (Note 3) 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Invalid Valid when bit 4 = "0" 0 : CTS is selected (Note 1) 1 : RTS is selected (Note 4) 0 : Data present in transmit register 1 : No data present in transmit register 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled 0 : TxDi/SDAi and SCLi pin is CMOS output 1 : TxDi/SDAi and SCLi pin is N-channel open drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge 0 : LSB first 1 : MSB first b1 b0 O O O O O X O O O O O O O O Set to "0" b7 b0 b1b2b3b4b5b6 b7 b0 b1b2b3b4b5b6 Set to "0"

M30245 Group Serial Communication Rev.2.00 Oct 16, 2006 page 130 of 264 REJ03B0005-0200 Figure 1.92. Serial I/O-related registers (4) Bit Symbol Function (clock synchronous serial I/O mode) Function (UART mode) R W Symbol UiSMR (i = 0 to 3) Address 03A716, 036716, 033716, 032716 UARTi special mode register (i= 0 to 3) O O Note 1: Only "0" may be written Note 2: UART0: Timer A3 underflow signal, UART1: Timer A4 underlfow signal, UART2 :Timer A0 underflow signal, UART3: Timer A3 underflow signal Note 3: Set to "0" in normal mode (IICM="0") When reset 0016 Bit Name IICM ABC BBS LSYN ABSCS ACSE SSS I2C mode select bit Arbitration lost detecting flag control bit Bus busy flag SCLL sync output enable bit Bus collision detect sampling clock select bit Auto-clear function select bit of transmit enable bit Transmit start condition select bit 0 : Normal mode 1 : I 2C mode 0 : Update per bit 1 : Update per byte 0 : STOP detected 1 : START detected 0 : Disabled 1 : Enabled (Note 3) Set to "0" Set to "0" Set to "0" O O O O O O O O O O O O Set to "0" Set to "0" Set to "0" (Note 1) Set to "0" 0 : Rising edge of transfer clock 1 : Timer Ai underflow signal (Note 2) 0 : No auto clear function 1 : Auto clear when bus occurs 0 : Ordinary 1 : Falling edge of RxDi Bit Symbol Function R W Symbol UiSMR2 (i = 0 to 3) Address 03A6 16, 036616, 033616, 032616 UARTi special mode register 2 (i= 0 to 3) When reset 0016 Bit Name IICM2 CSC ALS SDHI I2C mode select bit 2 Clock synchronous bit SDA output stop bit SDA output inhibit bit 0 : NACK/ACK interrupt (DMA source-ACK) Transfer to receive buffer at the rising edge of last bit of receive clock. Receive interrupt occurs at the rising edge of last bit of receive clock. 1 : UART transfer/receive interrupt (DMA source-UART receive) Transfer to receive buffer at the falling edge of last bit of receive clock. Receive interrupt occurs at the falling edge of last bit of receive clock 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled (high impedance) O O O O O O O O _ _ b7 b0 b1b2b3b4b5b6 b7 b0 b1b2b3b4b5b6 Nothing is assigned. Write "0" when writing to this bit. The value is indeterminate if read. Nothing is assigned. Write "0" when writing to this bit. The value is indeterminate if read. _ _ SWC SCL wait output bit (Note) 0 : Disabled 1 : Enabled 0 : Disabled 1 : EnabledSTC UARTi initialize bit (Note) SWC2 SCL wait output bit 2 (Note) 0 : UARTi clock 1 : output O O O O O O Note: These bits are unavailable when SCLi is external clock.

M30245 Group Serial Communication Rev.2.00 Oct 16, 2006 page 131 of 264 REJ03B0005-0200 Figure 1.93. Serial I/O-related registers (5) Bit Symbol Function R W Symbol UiSMR3 (i = 0 to 3) Address 03A516, 036516, 033516, 032516 UARTi special mode register 3 (i= 0 to 3) Note 1: Set SS function after setting CTS/RTS disable bit (bit 4 of UARTi transfer/receive control register 0) Note 2: Only "0" may be written. Note 3: These bits are used for SDAi (TxDi) output digital delay when using UARTi for I2C interface. Otherwise, set these to "000". Note 4: The amount of delay varies with the load on SCLi and SDAi pins. Also, when external clock is selected, delay is increased by approximately 100ns. When reset 0016 Bit Name SSE CKPH DINC NODC ERR DL0 DL1 DL2 SS port function enable bit (Note 1) Clock phase set bit Serial input port set bit Clock output select bit Fault error flag SDA (TxDi) digital delay time set bit (Notes 3,4) 0 : SS function disabled 1 : SS function enabled 0 : No clock delay 1 : Clock delay 0 : Select TxDi and RxDi (master mode) 1 : Select STxDi and SRxDi (slave mode) 0 : CLKi is CMOS output 1 : CLKi is N-channel open drain output 0 : No fault error 1 : Fault error (Note 2) 0 0 0 : No delay 0 0 1 : 1 to 2-cycle of UiBRG count source 0 1 0 : 2 to 3-cycle of UiBRG count source 0 1 1 : 3 to 4-cycle of UiBRG count source 1 0 0 : 4 to 5-cycle of UiBRG count source 1 0 1 : 5 to 6-cycle of UiBRG count source 1 1 0 : 6 to 7-cycle of UiBRG count source 1 1 1 : 7 to 8-cycle of UiBRG count source O O O O O O O O O O O O O O O O b7 b6 b5 Bit Symbol Function R W Symbol UiSMR4 (i = 0 to 3) Address 03A416, 036416, 033416, 032416 UARTi special mode register 4 (i= 0 to 3) When reset 0016 Bit Name STAREQ RSTAREQ STPREQ STSPSEL ACKD ACKC SCLHI Start condition generate bit (Note 1) Restart condition generate bit (Note 1) Stop condition generate bit (Note 1) SCL, SDA output select bit ACK data bit ACK data output enable bit SCL output stop enable bit 0 : Clear 1 : Start 0 : Clear 1 : Start 0 : Clear 1 : Start 0 : Ordinal block 1 : Start/stop condition generate block 0 : ACK 1 : NACK 0 : SI /O data output 1 : ACKD output 0 : Disabled 1 : Enabled O O O O O O O O O O O O O O Note 1: These bits automatically become "0" when a start condition is generated. Note 2: This bit is unavailable when SCLi is external clock. b7 b0 b1b2b3b4b5b6 b7 b0 b1b2b3b4b5b6 to "1". SWC9 SCL waitt output bit 3 (Note 2) 0 : SCL "L" hold disabled 1 : SCL "L" hold enabled O O

M30245 Group Clock synchronous serial I/O mode Rev.2.00 Oct 16, 2006 page 132 of 264 REJ03B0005-0200 Clock synchronous serial I/O mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 1.44 list the specifica- tions of the clock synchronous serial I/O mode. Table 1.44. Clock synchronous serial I/O mode specifications Note 1: "m" denotes the value 0016 to FF16 that is set in the UART bit rate generator. Note 2: If an overrun error occurs, the value of the UiRB register will be indeterminate. The IR bit of the SiRIC register does not change. Item Specification Transfer data format Transfer data length: 8-bits Transfer clock When internal clock is selected (bit 3 at address 03A8 16, 036816, 033816, 032816 ="0"): fi/2(m+1) (Note 1) fi = f1, f8, f32 When external clock is selected (bit 3 at 03A8 16, 036816, 033816, 032816 = "1"): Input from CLKi pin Transmission/reception control CTS function/RTS function/ CTS, RTS function not used Transmission start condition To start transfer, the following criteria must be met: -Transmit enable bit (bit 0 at 03AD16, 036D16, 033D16, 032D16) = "1" -Transmit buffer empty flag (bit 1 at 03AD16, 036D16, 033D16, 032D16) = "0" -When CTS function selected, CTS input level = "L" Furthermore, if external clock is select ed, the following requirements must also be met: -CLKi polarity select bit (bit 6 at 03AC 16, 036C16, 033C16, 032C16)= "0": CLKi input level = "H" -CLKi polarity select bit (bit 6 at 03AC 16, 036C16, 033C16, 032C16)= "1": CLKi input level = "L" Receive start condition To start reception, the following requirement must be met: -Receive enable bit (bit 2 at 03AD 16, 036D16, 033D16, 032D16) = "1" -Transmit enable bit (bit 0 at 03AD16, 036D16, 033D16, 032D16) = "1" -Transmit buffer empty flag (bit 1 at 03AD16, 036D16, 033D16, 032D16) = "0" Furthermore, if external clock is selec ted, the following requirement must be met: -CLKi polarity select bit (bit 6 at 03AC 16, 036C16, 033C16, 032C16)= "0": CLKi input level = "H" -CLKi polarity select bit (bit 6 at 03AC 16, 036C16, 033C16, 032C16)= "1": CLKi input level = "L" Interrupt request generation timing When transmitting: -Transmit interrupt cause select bit (bit 4 at 3AD16, 036D16, 033D16, 032D16) = "0": Interrupt requested when data transfer from UARTi transfer buffer register to UARTi transmit register is complete -Transmit interrupt cause select bit (bit 4 at 3AD16, 036D16, 033D16, 032D16) = "1": Interrupt requested when data transmission from UARTi transmit register is complete When receiving: -Interrupt requested when data transfer from UARTi receive register to UARTi receive buffer register is completed. Error detection Overrun error (Note 2) This error occurs if the serial I/O starts receiving the next data and receives the 7th bit of the next data before reading the UiRB register. Select function CLK polarity selection Whether transmit data is output/input at the rising edge or falling edge or the transfer clock can be selected LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected Continuous receive mode selection Reception is enabled simultaneously by a read form the receive buffer register Switching serial data log Reverse data when writing to the transmission buffer register or reading the reception buffer register can selected TxD, RxD, I/O polarity reverse This function reverses the TxD port output and RxD port input. All I/O data level is reversed.

M30245 Group Clock synchronous serial I/O mode Rev.2.00 Oct 16, 2006 page 133 of 264 REJ03B0005-0200 Table 1.45 lists the functions of the input/output pins during clock synchronous serial I/O mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a "H". (If the N-channel open drain is selected, this pin is in floating state.) Figure 1.94. shows the typical transmit receive timings in clock synchronous serial I/O mode. Table 1.45. Input/output pin functions in clock synchronous serial I/O mode Pin name Function Method of selection TxDi (P63, P67, P70, P74) Serial data output RxDi (P62, P66, P71, P75) Serial data input Port P62, P66, P 71and P75 direction register (bits 2 and 6 at address 03EE 16, bit 1 and 5 at address 03EF16) = "0". Can be used as an input port when performing transmission only. CLKi (P61, P 65, P72, P76) Programmable I/O port Internal/external clock select bit (bit 3 at addresses 03A8 16, 036816, 033816, 032816) = "0" Transfer clock input Internal/external clock select bit (bit 3 at addresses 03A8 16, 036816, 033816, 032816) = "1" Port P61, P65, P72 and P76 direction register (bits 1 and 5 at address 03EE16, bit 2 and 6 at address 03EF16) = "0" CTSi/RTSi (P60, P64, P73, P77) CTS input CTS/RTS disable bit (bit 4 at address 03AC16, 036C16, 033C16, 032C16) = "0" CTS/RTS function select bit (bit 2 at address 03AC16, 036C16, 033C16, 032C16) = "0" Port P60, P64, P73 and P77 direction register (bits 0 and 4 at address 03EE16, bits 3 and 7 at address 03EF16) = "0" RTS output CTS/RTS disable bit (bit 4 at addresses 03AC16, 036C16,033C 16, 032C166) = "0" CTS/RTS function select bit (bit 2 at address 03AC16, 036C16, 033C16, 032C16) = "1" Programmable I/O port CTS/RTS disable bit (bit 4 at address 03AC16, 036C16, 033C16, 032C16) = "1"

M30245 Group Clock synchronous serial I/O mode Rev.2.00 Oct 16, 2006 page 134 of 264 REJ03B0005-0200 Figure 1.94. Typical transmit/receive timing in clock synchronous serial I/O mode D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Tc TCLK Stopped pulsing because transfer enable bit = "0" Data is set in UARTi transmit buffer register Tc = TCLK = 2(m + 1) / fi fi : frequency of BRGi count source (f1, f8, f32) m : value set to BRGi Transfer clock Transmit enable bit (TE) Transmit buffer empty flag (Tl) CLKi TxDi Transmit register empty flag (TXEPT) "H" "L" "0" "1" "0" "1" "0" "1" CTSi The above timing applies to the following settings:

• Internal clock is selected.
• CTS function is selected.
• CLK polarity select bit = "0".
• Transmit interrupt cause select bit = "0". Transmit interrupt request bit (IR) "0" "1" Stopped pulsing because CTS = "H" Dummy data is set in UARTi transmit buffer registerTransmit enable bit (TE) Transmit buffer empty flag (Tl) CLKi RxDi Receive complete flag (Rl) RTSi "H" "L" "0" "1" "0" "1" "0" "1" Receive enable bit (RE) "0" "1" Receive data is taken in Transferred from UARTi transmit buffer register to UARTi transmit register The above timing applies to the following settings:
• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = "0". fEXT: frequency of external clock Transferred from UARTi receive register to UARTi receive buffer register Receive interrupt request bit (IR) "0" "1" Shown in ( ) are bit symbols. Transferred from UARTi transmit buffer register to UARTi transmit register The following conditions are met when the CLKi input before data reception = "H"
• Transmit enable bit "1"
• Receive enable bit "1"
• Dummy data write to UARTi transmit buffer register Shown in ( ) are bit symbols. Cleared to "0" when interrupt request is accepted, or cleared by software Cleared to "0" when interrupt request is accepted, or cleared by software 1 / fEXT D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D0 D1 D2 D3 D4 D5D7D6 Over run error flag (OER) "0" "1" Example of transmit timing when internal clock is selected Example of receive timing when external clock is selected Even if the reception is completed, RTS does not change. RTS becomes "L" when the RI bit changes from "1" to "0". Read out from UARTi receive buffer register

M30245 Group Clock synchronous serial I/O mode Rev.2.00 Oct 16, 2006 page 136 of 264 REJ03B0005-0200 Continuous receive function If the continuous receive mode enable bit (bit 5 at address 03AD 16, 036D16, 033D16, 032D16) is set to "1", the unit is placed in continuous receive mode. In this mode, when the receive buffer is read out, the unit simultaneously goes to a receive enable state without having to set dummy data back to the transmit buffer register again. Serial data logic switch function When the data logic select bit (bit 6 at address 03AD16, 036D16, 033D16, 032D16) = "1", and writing to the transmit buffer register or reading from the receive buffer register, data are inverted. Figure 1.97 shows the example of serial data logic switch timing. Figure 1.97. Serial data logic switch timing D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Transfer clock TxDi (no reverse) TxDi (reverse) "H" "L" "H" "L" "H" "L"

• When LSB first

M30245 Group Clock asynchronous serial I/O (UART) mode Rev.2.00 Oct 16, 2006 page 137 of 264 REJ03B0005-0200 Clock asynchronous serial I/O (UART) mode UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Table 1.46 lists the specifications of the UART mode. Table 1.46. Specifications of clock asynchronous serial I/O mode Note 1: 'm' denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: fEXT is input from the CLKi pin. Note 3: If an overrun error occurs, the value of the UiRB register will be indeterminate. The IR bit of the SiRIC register does not change. Item Specification Transfer data format Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected Start bit: 1 bit Parity bit: odd, even, or neither is selected Stop bit: 1 bit or 2 bits as selected Transfer clock When internal clock is selected (bit 3 at address 03A816, 036816, 033816, 032816 = "0"): fi/ 16(m+1) (Note 1) fi = f1, f8, f32 When external clock is selected (bit 3 at address 03A816, 036816, 033816, 0328 16 = "1"): fEXT/16/(m+1) (Notes 1, 2) Transmission/reception control CTS function, RTS function, CTS/RTS function chosen to be invalid Transmission start condition To start transmission, the following requirements must be met: -Transmit enable bit (bit 0 at addresses 03AD16, 036D16, 033D16, 032D16) = "1" -Transmit buffer empty flag (bit 1 at address 03AD16, 036D16, 033D 16, 032D16) = "0" -When CTS function is selected CTS input level = "1" Receive start condition To start receive, the following conditions must be met: -Receive enable bit (bit 2 at addresses 03AD16, 036D 16, 033D16, 032D16) = "1" -Start bit detection Interrupt request generation timing When transmitting -Transmit interrupt cause select bits (bit 4 at address 03AD16, 036D16, 033D16, 032D16) = "0": Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is complete. -Transmit interrupt cause select bits (bit 4 at address 03AD16, 036D16, 033D16, 032D16) = "1": Interrupts requested when data transmission from UARTi transfer register is complete. When receiving -Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is complete. Error detection Overrun error (Note 3) This error occurs if the serial I/O starts receiving the next data and receives the 7th bit of the next data before reading the UiRB register. Framing error This error occurs when the number of stop bits set is not detected Parity error If parity is enabled this error occurs when the number of "1"s in parity and character bits does not match the number of "1"s set Error sum flag This flag is set (=1) when any overrun, framing, and parity error occurs Select function Serial data logic switch This function reverses the logic of transferred data. Start bit, parity bit and stop bit are not reversed. TxD, RxD I/O polarity switch This function reverses the TxD port output and RxD port input. All I/O data levels are reversed.

M30245 Group Clock asynchronous serial I/O (UART) mode Rev.2.00 Oct 16, 2006 page 138 of 264 REJ03B0005-0200 Table 1.47 lists the functions of the input/output pins during UART mode. Note that the period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an "H". (If the N-channel open drain is selected, this pin is in floating state.) Figure 1.98 shows typical transmit timings in UART mode. Figure 1.99 shows typical receive timings in UART mode. Table 1.47. Input/output pin functions in UART mode Pin name Function Method of selection TxDi (P63, P67, P70, P74) Serial data output RxDi (P62, P66, P71, P75) Serial data input Port P62, P66, P 71and P75 direction register (bits 2 and 6 at address 03EE 16, bit 1 and 5 at address 03EF16) = "0". Can be used as an input port when performing transmission only. CLKi (P61, P 65, P72, P76) Programmable I/O port Internal/external clock select bit (bit 3 at addresses 03A8 16, 036816, 033816, 032816) = "0" Transfer clock input Internal/external clock select bit (bit 3 at addresses 03A8 16, 036816, 033816, 032816) = "1" Port P61, P65, P72 and P76 direction register (bits 1 and 5 at address 03EE16, bit 2 and 6 at address 03EF16) = "0" CTSi/RTSi (P60, P64, P73, P77) CTS input CTS/RTS disable bit (bit 4 at address 03AC16, 036C16, 033C16, 032C16) = "0" CTS/RTS function select bit (bit 2 at address 03AC16, 036C16, 033C16, 032C16) = "0" Port P60, P64, P73 and P77 direction register (bits 0 and 4 at address 03EE16, bits 3 and 7 at address 03EF16) = "0" RTS output CTS/RTS disable bit (bit 4 at addresses 03AC16, 036C16,033C 16, 032C166) = "0" CTS/RTS function select bit (bit 2 at address 03AC16, 036C16, 033C16, 032C16) = "1" Programmable I/O port CTS/RTS disable bit (bit 4 at address 03AC16, 036C16, 033C16, 032C16) = "1"

M30245 Group Clock asynchronous serial I/O (UART) mode Rev.2.00 Oct 16, 2006 page 139 of 264 REJ03B0005-0200 Figure 1.98. Typical transmit timings in UART mode Transmit enable bit (TE) Transmit buffer empty flag (TI) Transmit register empty flag (TXEPT) Start bit Parity bit TxDi CTSi The above timing applies to the following settings :

• Parity is enabled.
• One stop bit.
• CTS function is selected.
• Transmit interrupt cause select bit = "1". "1" "0" "1" "L" "H" "0" "1" Tc = 16 (m + 1) / fi or 16 (m + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) m : value set to BRGi Transmit interrupt request bit (IR) "0" "1" Cleared to "0" when interrupt request is accepted, or cleared by software Transmit enable bit (TE) Transmit buffer empty flag (TI) TxDi Transmit register empty flag (TXEPT) "0" "1" "0" "1" "0" "1" The above timing applies to the following settings :
• Parity is disabled.
• Two stop bits.
• TCS function is disabled.
• Transmit interrupt cause select bit = "0". Transfer clock Tc Tc = 16 (m + 1) / fi or 16 (m + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) m : value set to BRGi Transmit interrupt request bit (IR) "0" "1" Shown in ( ) are bit symbols. Shown in ( ) are bit symbols. Tc Transfer clock D0 D1 D2 D3 D4 D5 D6 D7ST P D0 D1 D2 D3 D4 D5 D6 D7SP ST P SP D0 D1ST Stopped pulsing because transmit enable bit = "0"Stop bit Transferred from UARTi transmit buffer register to UARTi transmit register Start bit The transfer clock stops momentarily as CTS is "H" when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTS changes to "L". Data is set in UARTi transmit buffer register D0 D1 D2 D3 D4 D5 D6 D7ST SPD8 D0 D1 D2 D3 D4 D5 D6 D7ST D8 D0 D1STSPSP Transferred from UARTi transmit buffer register to UARTi transmit register Stop bit Stop bit Data is set in UARTi transmit buffer register."0" SP Cleared to "0" when interrupt request is accepted, or cleared by software Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)

M30245 Group Clock asynchronous serial I/O (UART) mode Rev.2.00 Oct 16, 2006 page 141 of 264 REJ03B0005-0200 TxD, RxD I/O polarity reverse function This function reverses the TxD pin output and RxD pin input. The level of any data input or output including the start bit, stop bits and parity bit, is reversed. Set this function to "0", (not to reverse) for normal use. Bus collision detection function This function samples the output level of the TxD pin and the input level of the RxD pin at the rising edge of the transfer clock. If their values are different, then an interrupt request occurs. Figure 1.101 shows an example of detection timing of a bus collision in UART mode. Figure 1.101. Detection timing of a bus collision in UART mode ST : Start bit SP : Stop bit ST ST SP SP T ransfer clock TxDi RxDi Bus collision detection interrupt request signal "H" "L" "H" "L" "H" "L" "1" "0" Bus collision detection interrupt request bit "1" "0"

M30245 Group UART mode (compliant with the SIM interface) Rev.2.00 Oct 16, 2006 page 142 of 264 REJ03B0005-0200 UART mode (compliant with the SIM interface) The SIM interface is used for connecting the microcomputer with a memory card IC or a similar device. Adding some extra settings in UART mode allows the user to effect this function. Table 1.48 shows the specifications of UART mode compliant with SIM interface. Figure 1.102 shows typical transmit/receive timing in UART mode compliant with SIM interface. Table 1.48. Specifications of UART mode compliant with the SIM interface Note 1: 'm' denotes the value 0016 to FF16 that is set to the UARTi bit rate generator Note 2: fEXT is input from the CLKi pin. Item Specification Transfer data format Transfer data 8-bit UART mode (bits 2 to 0 of address 03A816, 036816, 033816, 032816 = "1012") One stop bit (bit 4 of addresses 03A816, 036816, 033816, 032816 = "0") With the direct format: -Set parity to "even" (bits 5 and 6 of addresses 03A816, 036816, 033816, 032816 = "1") -Set data logic to "direct" (bit 6 of address 03AD 16, 036D16, 033D16, 032D16 = "0") -Set transfer format to LSB (bit 7 of address 03AC16, 036C16, 033C16, 032C16 = "0") With the inverse format: -Set parity to "odd" (bit 5 and 6 of address 03A816, 036816, 033816, 032816 = "0" and "1" respec- tively) -Set data logic to "inverse" (bit 6 of address 03AD 16, 036D16, 033D16, 032D16 = "1") -Set transfer format to MSB (bit 7 of address 03AC16, 036C16, 033C16, 032C16 = "1") Transfer clock With the internal clock selected (bit 3 of address 03A8 16, 036816, 033816, 032816 = "0"): fi/ 16(m+1) (Note 1): fi=f1, f8, f32 With an external clock selected (bit 3 of address 03A816, 036816, 033816, 032816 = "1"): fEXT/ 16(m+1) (Notes 1,2) Disable the CTS and RTS function (bit 4 of address 03AC16, 036C16, 033C16, 032C16 = "1") Other settings Set transmission interrupt factor to “transmission completed” (bit 4 of address 03AD16, 036D16, 033D16, 032D16 = "1") Set N-channel open drain output to TxD pin in UART0, 1, 3 (bit 5 of address 03AC 16, 036C16, 032C16 = "1") Transmission start condition Transmit enable bit (bit 0 of address 03AD16, 036D16, 033D16, 032D16 = "1") Transmit buffer empty flag (bit 1 of address 03AD16, 036D16, 033D16, 032D16 = "0") Receive start condition Receive enable bit (bit 2 of address 03AD16, 036D16, 033D16, 032D16 = "1") Detection of a start bit Interrupt request generation timing When transmitting -When data transmission from the UART0 to UART3 transfer register is completed (bit 4 of address 03AD16, 036D16, 033D16, 032D16 = "1") When receiving -When data transfer from the UART0 to UART3 receive register to the UART0 to UART3 receive buffer register is completed. Error detection Overrun error (See UART specifications) Framing error (See UART specifications) Parity error (See UART specifications) -On the reception side, an "L" level is output from the TxDi pin by use of the parity error signal output functions (bit 7 of address 03AD16, 036D16, 033D16, 032D16 = "1") when a parity error is detected. -On the transmission side, a parity error is detected by the level of input to the RxDi pin when a transmit interrupt occurs The error sum flag (See UART specifications) Transmission/reception control

M30245 Group UART mode (compliant with the SIM interface) Rev.2.00 Oct 16, 2006 page 143 of 264 REJ03B0005-0200 Figure 1.102. Typical transmit/receive timing in UART mode compliant with the SIM interface D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Tc TCLK Stopped pulsing because transfer enable bit = "0" Data is set in UARTi transmit buffer register Tc = TCLK = 2(m + 1) / fi fi : frequency of BRGi count source (f1, f8, f32) m : value set to BRGi Transfer clock Transmit enable bit (TE) Transmit buffer empty flag (Tl) CLKi TxDi Transmit register empty flag (TXEPT) "H" "L" "0" "1" "0" "1" "0" "1" CTSi The above timing applies to the following settings:

• Internal clock is selected.
• CTS function is selected.
• CLK polarity select bit = "0".
• Transmit interrupt cause select bit = "0". Transmit interrupt request bit (IR) "0" "1" Stopped pulsing because CTS = "H" Dummy data is set in UARTi transmit buffer registerTransmit enable bit (TE) Transmit buffer empty flag (Tl) CLKi RxDi Receive complete flag (Rl) RTSi "H" "L" "0" "1" "0" "1" "0" "1" Receive enable bit (RE) "0" "1" Receive data is taken in Transferred from UARTi transmit buffer register to UARTi transmit register The above timing applies to the following settings:
• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = "0". fEXT: frequency of external clock Transferred from UARTi receive register to UARTi receive buffer register Receive interrupt request bit (IR) "0" "1" Shown in ( ) are bit symbols. Transferred from UARTi transmit buffer register to UARTi transmit register The following conditions are met when the CLKi input before data reception = "H"
• Transmit enable bit "1"
• Receive enable bit "1"
• Dummy data write to UARTi transmit buffer register Shown in ( ) are bit symbols. Cleared to "0" when interrupt request is accepted, or cleared by software Cleared to "0" when interrupt request is accepted, or cleared by software 1 / fEXT D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D0 D1 D2 D3 D4 D5D7D6 Over run error flag (OER) "0" "1" Example of transmit timing when internal clock is selected Example of receive timing when external clock is selected Even if the reception is completed, RTS does not change. RTS becomes "L" when the RI bit changes from "1" to "0". Read out from UARTi receive buffer register

M30245 Group I2C Bus interface mode Rev.2.00 Oct 16, 2006 page 145 of 264 REJ03B0005-0200 I2C Bus interface mode The I2C bus interface mode is provided with UARTi. When the I2C mode select bit (bit 0 in addresses 03A716, 036716, 033716, and 032716) is set to "1", the I 2C bus interface circuit is enabled. To use the I2C bus in slave mode, SCLi should be set to input or to output “1”. Also for UART0, 1 and 3, set the data output select bit (bit 5 in address 03AC 16, 036C16, and 032C16) to N-channel open drain output. Note: UART2 TxD and RxD (P7 0 and P71) are always N-channel open drain outputs and require external pull-up resistors. Table 1.49 shows the relationship of the I 2C mode select bit to control. To use the chip in the clock synchronized serial I/O mode or UART mode, always set this bit to “0”. Figure 1.106 shows a block diagram of I 2C mode. Table 1.49. I 2C features Note 1: When using I 2 C mode, set 0 1 0 in bits 2, 1, 0 of the UARTi transmit/receive mode register. Disable the CTS/ RTS function. Select MSB first function. Note 2: To switch from one factor to another: 1. Disable the interrupt of the corresponding number. 2. Switch to another factor. 3. Reset the interrupt request flag of the corresponding number. 4. Set the interrupt level of the corresponding number. Note 3: Set an initial value of SDA transmission output when I2C mode (I2C mode select bit = "1") is valid and serial I/O is invalid. Function Normal mode (IICM=0) I2C mode (IICM=1) (Note 1)

1 Cause of interrupt number 3 and 9

(Note 2) Bus collision detection Start condition detection or stop condition detection

2 Cause of interrupt number 13 and

15 (Note 2) UARTi transmit No acknowledgement detection (NACK)

3 Cause of interrupt number 2 and

21 (Note 2) UARTi receive Acknowledgment detection (ACK)

4 UARTi transmit output delay Not delayed Delayed

3, P67, P70, P74 at the same time UARTi is in use TxDi (output) SCLi (input/output)6 P62, P66, P71, P75 at the same time UARTi is in use RxDi (input)

7 P61, P65, P72, P76 at the same

time UARTi is in use CLKi P61, P65, P72, P76

8 DMA1 factor at the same time UARTi receive Acknowledgement detection (ACK)

9 Noise filter width 15 ns 50 ns

10 Reading P62, P66, P71, P75

Reading the terminal when 0 is assigned to the direction register

11 Initial value of UARTi output "H" level (when 0 is assigned to

CLKi polarity select bit) The value set in latch P6 3, P67, P70, P74 when the port is selected (Note 3) SDAi (input/output) (Note 3) Master mode: Reading the terminal regardless of the value of the direction register Slave mode: Reading the terminal when the corresponding port register is set to "0"

M30245 Group I2C Bus interface mode Rev.2.00 Oct 16, 2006 page 146 of 264 REJ03B0005-0200 Figure 1.106. I 2C mode functional block diagram Transmission register SCLi D T Q D T Q D T Q NACK ACK UARTi R S R Q ALS R S SWC SWC2 SDHI DMAi request SDAi STSPSEL=1 SDASTSP SCLSTSP ACK=1 ACK=0 Q Start and stop condition generation block IICM2=1 UARTi transmission NACK interrupt request IICM=1 and IICM2=0 IICM2=1 IICM=1 and IICM2=0 DMAi request UARTi receive ACK interrupt request DMA1 request 9th bit Reception register UARTi BUS busy CLK control UARTi 9th bit falling edge External clock Internal clock Port register (Note)I/O port STSPSEL=0 UARTi IICM=1 Falling edge detection Noise Filter Stop condition detection Start condition detection Noise Filter Start/stop condition detection interrupt request Arbitration STSPSEL=1 STSPSEL=0 ACKD register Delay circuit This diagram applies to the case where the UiMR register’s SMD2 to SMD0 bits=0102 and the UiSMR register’s IICM bit=1. IICM IICM2, SWC, ALS, SWC2, SDHI STSPSEL, ACKD, ACKC : UiSMR2 register bit : UiSMR register bit : UiSMR4 register bit i=0 to 3 Note: In I 2C master mode, the port terminal is to be readable even if "1" is assigned to P62, P66, P71, P75 of the direction register IICM=0

M30245 Group I2C Bus interface mode Rev.2.00 Oct 16, 2006 page 147 of 264 REJ03B0005-0200 UARTi Special Mode Register (UiSMR) Bit 0 is the I 2C mode select bit 1. When set to "1", ports operate respectively as the SDAi data transmit/receive pin, SCLi clock input/output pin and port. A delay circuit is added to SDAi transmission output, therefore after SCLi is at "L" level, SDAi output changes. In I 2C master mode, port (SCLi) is designed to read pin level regardless of the content of the port direction register. SDAi transmission output is initially set to port in this mode. Furthermore, interrupt factors for the bus collision detection interrupt and UARTi transmission interrupt change respectively to the start/stop condition detection interrupts, acknowledge non-detection interrupt and acknowledge detection interrupt. The start condition detection interrupt is generated when the falling edge at the SDAi pin is detected while the SCLi pin is in "H" state. The stop condition detection interrupt is generated when the falling edge at the SDAi pin is detected while the SCLi pin is in the "H" state. The acknowledge non-detect interrupt is generated when the "H" level at the SDAi pin is detected at the 9th rise of the transmission clock. The acknowledge detect interrupt is generated when the "L" level at the SDAi pin is detected at the 9th fall of the transmission clock. Also, DMA transfer can be started when the acknowledge is detected if UARTi transmission is selected as the DMAi request factor. Bit 1 is the arbitration detection flag control bit. Arbitration detects a conflict between data transmitted at SCLi rise and data at the SDAi pin. This detect flag is allocated to bit 11 in UARTi transmit buffer register (addresses 036F 16, 02EF16, 033F16, 032F16, 02FF16). It is set to "1" when a conflict is detected. With the arbitration lost detect flag control bit, it can be selected to update the flag in units of bits or bytes. When this bit is set to "1", update is set to units of byte. If a conflict is still detected, the arbitration lost detect flag control bit will be set to "1" at the 9th rise of the clock. When updating in units of byte, always clear ("0" interrupt) the arbitration lost detect flag control bit after the first byte has been acknowl- edge but before the next byte starts transmitting. Bit 2 is the bus busy flag. It is set to "1" when the start condition is detected, and reset to "0" when the stop condition is detected. Bit 3 is the SCLi L synchronization output enable bit. When this bit is set to "1", the port data register is set to "0" in sync with the "L" level at the SCLi pin. Bit 4 to Bit 6 : These are not used in I 2C bus interface mode. See "IE mode" section.

M30245 Group I2C Bus interface mode Rev.2.00 Oct 16, 2006 page 148 of 264 REJ03B0005-0200 UARTi Special Mode Register 2 (UiSMR2) Bit 0 is the I2C mode select bit 2. Table 1.50 lists the control changes by bit when the I 2C mode select bit is "1". Start and stop condition detection timing characteristics are shown in Figure 1.107. Table 1.50. Functions changed by I 2C mode select bit 2 Function IICM2=0 IICM2=1 Interrupt numbers 13, 15, 17, 19 factor Acknowledge not detected (NACK) UARTi transfer (rising edge of the last bit) Interrupt number 2, 8, 10, 21 factor Acknowledge detected (ACK) UARTi receive (falling edge of the last bit) DMA factor Acknowledge detected (ACK) UARTi receive (falling edge of the last bit) Data transfer timing from UART receive shift register to receive buffer Rising edge of the last bit of receive clock Rising edge of the last bit of receive clock UART receive/ACK interrupt request generation timing Rising edge of the last bit of receive clock Rising edge of the last bit of receive clock Figure 1.107. Start/stop condition detect timing characteristics Set up time Hold time SCL SDA (Start condition) SDA (Stop condition) 3 to 6 cyles < set up time (Note) 3 to 6 cycles < hold time (Note) Note: Cycle number shows main clock input oscillation frequency f(Xin) cycle number. Bit 1 is the clock synchronizing bit. When this bit is set to "1", if the falling edge is detected at pin SCLi while the internal SCL is "H", the internal SCL is changed to "L", the baud rate generator value is reloaded and the L sector count starts. Also, while the SCLi pin is "L", if the internal SCL changes from "L" to "H", baud rate generator stops counting. If the SCLi pin is "H", counting restarts. Because of this function, the UARTi transmit/receive clock takes the AND condition for the internal SCL and SCLi pin signals. This function operates from the clock half period before the first rise of the UARTi clock to the 9th rise. To use this function, select the internal clock as the transfer clock. Bit 2 is the SCL wait output bit. When this bit is set to "1", output from the SCLi pin is fixed to "L" at the clock's 9th fall. When set to "0", the "L" output lock is released. This bit is unavailable when SCLi is external clock. Bit 3 is the SDA output stop bit. When this bit is set to "1", an arbitration lost generated. If the arbitration lost detection flag is "1", the SDAi pin simultaneously becomes high impedance. Bit 4 is the UARTi initialize bit. While this bit is set to "1", the following operations are performed when the start condition is detected.

• The transmit shift register is initialized and the content of the transmission register is transmitted to the transmission shift register. Transmission starts with the first bit of the next input clock. However, the UARTi output value does not change when the start condition is detected. It also doesn't change when the clock is input and when the first bit of data is output.
• The receive shift register is initialized and reception starts with the first bit of the next input clock.
• The SCL wait output is set to "1". The SCLi pin becomes "L" level at the fall of the 9th bit of the clock.

M30245 Group I2C Bus interface mode Rev.2.00 Oct 16, 2006 page 149 of 264 REJ03B0005-0200 When UART transmit/receive is started using this function, the content of the transmit buffer available flag does not change. Also, to use this function, select an external clock as the transfer clock. This bit is unavailable when SCLi is external clock. Bit 5 is SCL wait output bit 2. When this bit is set to "1" and serial I/O is selected, an "L" level can be output from the SCLi pin even during UART operation. When this bit is set to "0", the "L" output from the SCLi pin is cancelled and the UARTi clock is input and output. This bit is unavailable when SCLi is external clock. Bit 6 is the SDA output disable bit. When this bit is set to "1", the SDAi pin is forced to high impedance. Overwrite this bit at the rise of the UART transfer clock. The arbitration lost detection flag may be set. UARTi Special Mode Register 3 (UiSMR3) Bit 0 : Not used in I 2C bus interface mode. See "SPI mode" section. Bit 1 is the clock phase set bit. When both the I 2C mode select bit (bit 0 of UiSMR) and the I 2C mode select bit 2 (bit 0 of UiSMR2) are "1", functions changed by these bits are shown in Table 1.51 and Figure 1.108. Bit 2 : Not used in I2C bus interface mode. See "SPI mode" section Bit 3 : Not used in I2C bus interface mode. Bit 4 : Not used in I2C bus interface mode. See "SPI mode" section. Bit 5 to 7 are the I2C SDAi digital delay setting bits. By setting these bits, it is possible to turn the SDAi delay OFF or set the f(Xin) delay to 2 to 8 cycles. Table 1.51. Functions changed by clock phase set bits Function CKPH=0, IICM=1, IICM2=1 CKPH=1, IICM=1, IICM2=1 SCL initial and last value Initial value = "H", last val ue = "H" Initial value = "L", last value = "L" Transfer interrupt factor Rising edge of 9th bit Falling edge of 10th bit Data transfer times from UART receive shift register to receive buffer register Falling edge of 9th bit Two-times: falling edge of 9th bit and rising edge of 9th bit Figure 1.108. Function changed by clock phase set bits

• CKPH= "1" (IICM=1, IICM2=1)
• CKPH= "0" (IICM=1, IICM2=1) (Internal clock, transfer data 9 bits long and MSB first selected.) D6 D5 D4 D3 D2 D1 D8D7SDA SCL Receive interrupt Transmit interrupt Transfer to UiRB register (Internal clock, transfer data 9 bits long and MSB first selected.) D6 D5 D4 D3 D2 D1 D8D7SDA SCL Receive interrupt Transmit interrupt Transfer to UiRB register

M30245 Group I2C Bus interface mode Rev.2.00 Oct 16, 2006 page 150 of 264 REJ03B0005-0200 UARTi Special Mode Register 4 (UiSMR4) Bit 0 is the start condition generate bit. When the SCL, SDA output select bit (bit 3 of UiSMR4) is "1" and this bit is "1", the start condition is generated. Bit 1 is the restart condition generate bit. When the SCL, SDA output select bit (bit 3 of UiSMR4) is "1" and this bit is "1", the restart condition is generated. Bit 2 is the stop condition generate bit. When the SCL, SDA output select bit (bit 3 of UiSMR4) is "1" and this bit is "1", the stop condition is generated. Bit 3 is SCL, SDA output select bit. Table 1.52 shows the functions that are changed by this bit. Figure 1.109 shows the functions changed by SCL, SDA output select bit. Bit 4 is ACK data bit. When the SCL, SDA output select bit (bit 3 of UiSMR4) is "0" and the ACK data output enable bit (bit 5 of UiSMR4) is "1", the content of ACK data bit is output to SDAi pin. Bit 5 is ACK data output enable bit. When the SCL, SDA output select bit (bit 3 of UiSMR4) is "0" and this bit is "1", the content of ACK data bit is output to SDAi pin. Bit 6 is SCL output stop bit. When this bit is "1", SCLi output is stopped at stop condition detection. (High-Z status). Bit 7 is SCL wait output bit 3. When this bit is "1", SCLi output is fixed to "L" at the falling edge of the 10th clock bit. When this bit is "0", SCLi output fixed to "L" is released. This bit is unavailable when SCLi is external clock. Function STSPSEL=0 STSPSEL=1 SCL, SDA output Output of S I/O control circuit Output of start/stop condition control circuit Start/stop condition interrupt factor Start/stop condition detection Completion of start/stop condition generation Master mode (CKDIR = 0, STSPSEL = 1) SCL SDA Start condition detection interrupt Stop condition detection interrupt STPREQ = 1 STAREQ =1 STSPSEL = 0STSPSEL = 1STSPSEL = 0STSPSEL = 1STSPSEL = 0 Table 1.52. Functions changed by SCL, SDA output select bit Figure 1.109. Functions changed by SCL, SDA output select bit

M30245 Group Serial Interface Special Function (SPI mode) Rev.2.00 Oct 16, 2006 page 151 of 264 REJ03B0005-0200 Serial Interface Special Function (SPI mode) SPI mode related control bit UARTi Special Mode Register 3 (UiSMR3) Bit 0 is the SS port function enable bit. Set this bit to "1" to enable the slave select output. Bit 1 is the clock phase set bit. Bit 2 is the serial input port set bit. Bit 4 is the fault error flag. When this bit is "1", a fault error has been detected. Bit 3, 5 to 7 : Not used in SPI mode. UARTi can control communications on the serial bus using the SSi input pins. The master outputting the transfer clock transfers data to the slave inputting the transfer clock. To prevent a bus collision, the master floats the output pin of other slaves/masters using the SSi input pins. Figure 1.110 shows the SSi input pin factors between the master and slave. Slave mode (STxDi and SRxDi are selected, DINC="1") When an "H" level signal is input to an SSi input pin, the STxDi and SRxDi pins both become high impedance and the clock input is ignored. When an "L" level signal is input to an input pin, SSi clock input becomes effective and serial communications are enabled. Master mode (TxDi and RxDi are selected, DINC="0") The SSi input pins are used with a multiple master system. When an SSi input pin is "H" level, transmission has priority and serial communications are enabled. When an "L" signal is input to an SSi input pin, another master exists, and the TxDi, RxDi and CLKi pins become high impedance and the trouble error interrupt request bit becomes "1". Communi- cations do not stop when a trouble error is generated during communications. To stop communications, set bit 0, 1, 2 of the UARTi transmit/receive mode register (addresses 03A8 16, 036816, 033816, and 0328 16) to "0". P13 P12 IC1 P77(SS3) P74(TxD3) P76(CLK3) P75(RxD3) IC2 P77(SS3) P74(SRxD3) P76(CLK3) P75(STxD3) IC3 P77(SS3) P74(SRxD3) P76(CLK3) P75(STxD3) M30245 (M) M30245 (S) M30245 (S) M :Master S :Slave Figure 1.110. Example of serial bus communication control using SSi input pins

Rev.2.00 Oct 16, 2006 page 154 of 264 REJ03B0005-0200 lE Mode (UiSMR) Bit 0 to 3 : Not used in IE mode. Bit 4 is the bus collision detection sampling clock select bit. The bus collision detection interrupt is generated when RxDi and TxDi level conflict with each other. When this bit is "0", a conflict is detected in sync with the rise of the transfer clo ck. When this bit is "1", detection is made when Timer Aj (Timer A3:UART0, Timer A4:UART1, Timer A0:UART2, Timer A3:UART3 and Timer A4:UART4) underflows. Timer Aj (one-shot mode) should be triggered with corresponding RxDi pin by connecting RxDi pin to TAjIN pin. The operation is shown in Figure 1.114. Bit 5 is the transmission enable bit automatic clear select bit. By setting this bit to "1", the transmission bit is automatically reset to "0" when the bus collision detection interrupt factor bit is "1" (when a conflict is detected). Bit 6 is the transmit start condition select bit. By setting this bit to "1", TxDi transmission starts in sync with the rise at the RxDi pin.

Rev.2.00 Oct 16, 2006 page 155 of 264 REJ03B0005-0200 (1) UiSMR register ABSCS bit (bus collision detect sampling clock select) (2) UiSMR register ACSE bit (auto clear of transmit enable bit) Transfer clock TxDi RxDi Timer Aj If ABSCS=0, bus collision is determined at the rising edge of the transfer clock Input to TAjIN Timer Aj : timer A3 when UART0; timer A4 when UART1; timer A0 when UART2; timer A3 when UART3) ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP If ABSCS=1, bus collision is determined when timer Aj (one-shot timer mode) underflows. (i=0 to 3) ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP Transfer clock TxDi RxDi UiC1 register TE bit Bus collision detect interrupt request bit If ACSE bit=1, (automatically clear when bus collision occurs), the TE bit is cleared to “0” (transmission disabled) when the UiBCNIC register’s IR bit=1 (unmatching detected). (3) UiSMR register SSS bit (Transmit start condition select) ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP Transfer clock TxDi CLKi Transmission enable condition is met If SSS bit=0, the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met. ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP (Note 2)TxDi RxDi If SSS bit=1, the serial I/O starts sending data at the rising edge (Note 1) of RxDi Note 1: The falling edge of RxDi when IOPOL=0; the rising edge of RxDi when IOPOL=1. Note 2: TheTransmit condition must be met before the falling edge (Note 1) of RxD. This diagram applies to the case where IOPOL=1 (reserved). Figure 1.114. Bus collision Detect Function-Related Bits

M30245 Group Serial Sound Interface Rev.2.00 Oct 16, 2006 page 157 of 264 REJ03B0005-0200 Data transmission format The transmitter/receiver must change channels on every WS transition. If the number of SCKs within a WS high/low period exceeds the channel width (set by the user via mode bits), the transmitter continues to transmit '0's, while the receiver will stop receiving data until the next WS edge. However, if the number of SCKs falls short, both the transmitter and the receiver will immediately switch to the next channel transmit and receive, respectively. The Serial Sound Interface architecture is shown in Figure 1.116. Figure 1.116. Serial Sound Interface architecture MCU Bus Data Interface Left buffer Right buffer 16/32 Bit 16/32 Bit Shift register Left buffer Right buffer Data Interface Interrupt generator Interrupt generator Rate Feedback counter Rate Feedback register MCU Bus XMT SCK RX Load on WS edgeLoad To ICU (DMATRIG) Number of Interrupts MCU write width Byte Word Channel width To ICU (DMATRIG) Store Store on WS edge SCK WS Shift register

M30245 Group Serial Sound Interface Rev.2.00 Oct 16, 2006 page 158 of 264 REJ03B0005-0200 The following features are supported via firmware controlled mode bits:

• Simultaneous transmit and receive (through separate transmit and receive pins) synchronized to the same SCK and WS signals.
• Transmit/receive data and WS synchronized to the rising edge or the falling edge of SCK as shown in Figure 1.117.
• Transmit and receive synchronized to the rising or the falling edge of WS as shown in Figure 1.118.
• Normal or delayed WS: WS transitions one SCK period before a channel change (normal mode) or concurrently with a channel change (delayed mode) as shown in Figure 1.119.
• Automatic interrupt on a channel change and on every access to the data buffer (transmit/receive) until each data buffer byte is accessed.
• Channel widths of 32, 24, and 16 bits.
• MSB or LSB first transmit and receive.
• Multiple receive formats: if the number of SCKs in a WS high/low period is less than the channel width, the data can be placed either MSB or LSB justified as shown in Figure 1.120.
• Rate feedback: when used with the USB interface, the Serial Sound Interface can count the number of WS’s or SCK’s per USB frame. Data SCK WS Data WS Data/WS synchronized to rising edge (SCKP = 1) Data/WS synchronized to falling edge (SCKP = 0) SCK Figure 1.117. Transmit and receive data (and WS) synchronized to SCK

M30245 Group Serial Sound Interface Rev.2.00 Oct 16, 2006 page 160 of 264 REJ03B0005-0200 Figure 1.120. Receiver setting effects Note: These example formats show the effects of the receiver settings on the received data when fewer than expected SCKs arrive for each channel. WS is shown 'LOW' for this example. SCK MSB first data on RX line WS MSB first MSB justified Data buffer MSB first LSB justified Data buffer SCK LSB first data on RX line WS LSB first MSB justified Data buffer LSB first LSB justified Data buffer Channel width set to 24 bits (MCU mode bits) 212223 54 23 4 32 1 0 4 0 0 00 4 32 1 0 8 7 6 54 0 12 18 19 0 Case I : MSB - first receive data (Note) Case II : LSB - first receive data (Note) 1623 22 21 20 19 18 17 1619 18 17 15 14 13 12 1623 22 21 20 19 18 17 0 0 0 0 23 22 21 20 4 32 1 0 0 0 0 00 4 32 1 0 4 3 2 10 1623 22 21 20 19 18 17 1619 18 17 15 14 13 12 1623 22 21 20 19 18 17 0 0 0 0 19 18 17 16

M30245 Group Serial Sound Interface Rev.2.00 Oct 16, 2006 page 161 of 264 REJ03B0005-0200 Overview The Serial Sound Interface is a serial data communication system. The parallel (MCU bus) to serial data conversion is accomplished by the shift registers. Figure 1.116 shows a description of each component of the Serial Sound Interface architecture. There are separate 32- bit shift registers for transmit and receive for full duplex operation. Each shift register can be configured for 32, 24, or 16 bits as defined by the channel width mode bits. The shift register loads (or stores for receiver) data from the data buffers on every WS edge. The first load and bit-shift begins on the first "valid" edge of WS (as defined by the mode bits) after the transmit/receive mode bits are set (see Figure 1.122). Therefore, the transmit data buffers must be loaded prior to enabling the transmitter to ensure that the first transmit contains valid data. Both the transmitter and receiver have their own set of data buffers. There are two data buffers (left and right) so that, on special conditions when the MCU is handling a higher priority task, additional time is available (channel width X TSCK) before there is data underflow or overflow. The shift register always loads from or stores to the left buffer first and alternates between the two buffers on every edge of WS. The placement of data within the buffers is described in detail in the Data Path section. The interrupt generator is a state machine which controls the data interface. The state machine makes the data transfer to or from the peripheral more efficient by generating interrupts until all the data needed for the data buffer has been accessed. The interrupt can be set up to be a DMA trigger for more efficient data transfer. The interrupt generator also tracks the read/write width (byte/word) so that no additional control is needed. The interrupt is first generated when a data word is loaded from the data buffer to the shift register (transmitter) or data are stored from the shift register into the data buffer (receiver). When the MCU is finished accessing (as a response to the interrupt) another interrupt is generated if the data buffer has not completely been accessed. For example, for a 24-bit trans- mitter, an interrupt is generated when the left buffer is loaded into the shift register. If the MCU writes a byte of data to the transmit buffer address, 8 of the 24 bits will be filled with new data. The interrupt generator triggers another interrupt causing the MCU to write more data. If this write is a 16-bit operation, no further interrupts are generated until the right buffer is loaded into the shift register. However, if the write operation is only 8 bit, then another interrupt is generated immediately. The data interface is used to simplify the data transfer process. The data buffer address is the same regardless of the actual data buffer width. The interface places the incoming or outgoing data in the correct position according to the channel width and the number of completed reads/writes for the data buffer. The operation of the data interface is demonstrated in the example below which is the case of 24-bit audio data with word writes. As previously explained, the state machine generates an interrupt when the left channel is loaded into the shift register for transmission. When the first word write occurs, the data interface places the data in the left buffer. Since 8 more bits are required to fully load the left buffer, another interrupt is generated. The MCU writes another word of data, of which one byte is placed in the left buffer. However, the remaining data is held in a tempo- rary buffer within the data interface since the right channel may not be loaded into the shift register yet. If the data is not held in a temporary buffer but written to the right buffer, it would overwrite the untransmitted data in the right buffer. When the right buffer is eventually loaded into the shift register for transmission, the state machine generates an interrupt to request additional data. An MCU word write causes the data in the temporary buffer, as well as the data on the MCU data bus, to be placed in the right buffer. No further interrupts are generated because all data buffers are filled.

M30245 Group Serial Sound Interface Rev.2.00 Oct 16, 2006 page 163 of 264 REJ03B0005-0200 Figure 1.122. Serial Sound Interface related registers (2) Serial Sound Interface mode register 0 Symbol SSIiMR0 (i = 0, 1) Address 031016, 037016 When reset 0016 SSIEN XMTEN RXEN RFBEN CWID0 CWID1 RFMT0 RFMT1 Serial Sound Interface enable bit Transmitter enable bit Receiver enable bit Rate feedback counter enable bit Channel width select bit 0 Channel width select bit 1 Receiver format select bit 0 Receiver format select bit 1 0 : Disable 1 : Enable 0 : Disable 1 : Enable 0 : Disable 1 : Enable 0 : Disable 1 : Enable 0 0 : 32 bit 0 1 : 24 bit 1 0 : Reserved 1 1 : 16 bit 0 : LSB first 1 : MSB first 0 : LSB justified 1 : MSB justified Bit symbol Bit name Function R W b7 b0b6 b5 b4 b3 b2 b1 O O O O O O O O O O O O O O Serial Sound Interface mode register 1 Symbol SSIiMR1 (i = 0, 1) Address 031116, 037116 When reset 0016 XMTFMT Reserved RFBSRC SCKP WSP WSDLY Reserved Transmit format select bit Rate feedback counter source SCK polarity WS polarity WS delay 0 : LSB first 1 : MSB first Always set to "0" 0 : SCK 1 : WS 0 : Negative edge 1 : Positive edge 0 : Negative edge 1 : Positive edge 0 : DelayedWS 1 : NormalWS Always set to "0" Bit symbol Bit name Function R W b7 b0b6 b5 b4 b3 b2 b1 O O O O O O O O O O O O O O O O b5 b4

M30245 Group Serial Sound Interface Rev.2.00 Oct 16, 2006 page 164 of 264 REJ03B0005-0200 Data Path The data path is designed to work with the USB on this device. Because the Serial Sound Interface is an audio interface, the USB audio class device specifications are used to define the data path. USB audio data can be multiple types: PCM, a-law, u-law, MPEG, AC-3, IEC 1937, etc. However, the data are always left (MSB) justified. '0's are padded to the LSB end to meet byte boundaries or packet size requirements. The USB data are transmitted as MSB first in standard formats. Therefore, for basic stereo data with 24-bit resolution (L 23 - L0 and R23 - R0) should arrive or set up in the USB Table 1.53. USB FIFO data setup Left Buffer Right Buffer Byte 2 Byte 1 Byte 0 Byte 2 Byte 1 Byte 0 L23 - L16 L15 - L8 L7 - L0 R23 - R16 R15 - R8 R7 - R0 Table 1.54. Serial Sound Interface buffer data FIFO ADDRESS FIFO DATA Comments

0 L7 - L0 Sample 0

1 L15 - L8

2 L23 - L16

3 R7 - R0

4 R15 - R8

6 Sample 1

... Sample n R23 - R165 L7 - L0 L15 - L8 L23 - L16 R7 - R0 R15 - R8 R23 - R16 L7 - L0 (offset from endpoint start address)

M30245 Group Serial Sound Interface Rev.2.00 Oct 16, 2006 page 165 of 264 REJ03B0005-0200 The USB FIFO is read using word accesses and each word is written to the transmit buffer. Table 1.55 lists the USB FIFO sequence operation. Note that DB refers to the MCU data bus. Table 1.55. USB FIFO sequence operation OPERATION Left Buffer Right Bufferi Byte 2 Byte 1 Byte 0 Byte 2 Byte 1 Byte 0 First Word Write DB7 - DB0 DB15 - DB8 Second Word Write DB7 - DB0 DB15 - DB8Third Word Write DB7 - DB0 DB15 - DB8 Data are placed in the buffer from the least significant byte to the most significant byte with the left buffer written first. If the write operation is a word, the lower order data bus bits (DB 7-DB0) are treated as more significant than the higher order data bus bits (D 15-DB8). This is compatible with the USB. The same operation sequences occur for the receive buffer read. On a byte access, data are placed on the bus with the most significant byte first. If the access is a word read, the lower order data bus bits (DB 7-DB0) are treated as more significant. Precautions

• Entering wait mode with the SSI active can produce unpredictable data transfers. Make sure to disable the SSI transmitter and receiver before entering wait mode, and re-enable the transmitter and receiver after exiting wait mode.
• For flash memory version SSI transmission data must be latched as the following timing by a receiver. - SCKP=0 (falling edge) : within 3 BCLK cycles from the rising edge of SCK - SCKP=1 (rising edge) : within 3 BCLK cycles from the falling edge of SCK

M30245 Group Serial Sound Interface Rev.2.00 Oct 16, 2006 page 166 of 264 REJ03B0005-0200 Figure 1.123. DMA request timing in 32/24/16 bit width (transmission) WSDLY="0" (Delayed WS) WSP="0" (Negative edge) SCKP="0" (Negative edge) CWID1/CWID0="00"(32bit) SCK WS DMA request trigger (internal signal) DMA request bit CWID1/CWID0="01"(24bit) SCK WS DMA request trigger (internal signal) DMA request bit CWID1/CWID0="11"(16bit) SCK WS DMA request trigger (internal signal) DMA request bit XMT XMT XMT XMITFMT="0" (LSB first) RFBEN="0"(Rate feedback counter disable) Word write DMA request for a write to the next Lch data(L1 (31) to L1 (16) ) DMA request for a write to the next Rch data(R1 (31) to R1 (16)) Cleared to "0" when DMA request is accepted C leared to "0" when DMA request is accepted DMA request for a write to the next Lch data(L1 (15) to L1 (0) ) DMA request for a write to the next Rch data(R1 (15) to R1 (0) ) Transmit L0 (31) to L0 (0) Transmit R0 (31) to R0 (0) Transmit L0 (23) to L0 (0) Transmit R0 (23) to R0 (0) DMA request for a write to the next Lch data(L1 (23) to L1 (16) ), Rch data(R1 (7) to R1 (0) ) Cleared to "0" when DMA request is accepted DMA request for a write to the next Lch data(L1 (15) to L1 (0) ) Cleared to "0" when DMA request is accepted DMA request for a write to the next Rch data(R1 (23) to R1 (8) ) Transmit L0 (15) to L0 (0) Cleared to "0" when DMA request is accepted DMA request for a write to the next Lch data(L1 (15) to L1 (0) ) Transmit R0 (15) to R0 (0) Cleared to "0" when DMA request is accepted DMA request for a write to the next Rch data(R1 (15) to R1 (0) ) (Note) (Note) (Note) (Note) (Note) (Note) Note : DMA request trigger and DMA request bit are synchronized not to SCLK but to BCLK.

M30245 Group Serial Sound Interface Rev.2.00 Oct 16, 2006 page 167 of 264 REJ03B0005-0200 Figure 1.124. DMA request timing in 32/24/16 bit width (reception) R1(0)L1(15) WSDLY="0" (Delayed WS) RFMT1="0"(LSB justified) WSP="0" (Negative edge) RFMT0="0"(LSB first) SCKP="0" (Negative edge) RFBEN="0"(Rate feedback counter disable) Word Read CWID1/CWID0="00"(32bit) SCK WS DMA request trigger (internal signal) DMA request bit CWID1/CWID0="01"(24bit) SCK WS DMA request trigger (internal signal) DMA request bit CWID1/CWID0="11"(16bit) SCK WS DMA request trigger (internal signal) DMA request bit RX RX RX Receive L0 (31) to L0 (0) Receive L0 (23) to L0 (0) Receive L0 (15) to L0 (0) DMA request for a read from Lch data(L0 (31) to L0 (16)) Cleared to "0" when DMA request is accepted DMA request for a read from Lch data(L0 (15) to L0 (0) ) Receive R0 (31) to R0 (0) DMA request for a read from Lch data(L0 (15) to L0 (0)) Cleared to "0" when DMA request is accepted Receive R0 (23) to R0 (0) DMA request for a read from Lch data(L0 (15) to L0 (0)) Cleared to "0" when DMA request is accepted Receive R0 (15) to R0 (0) DMA request for a read from Rch data (R0(31) to R0 (16)) DMA request for a read from Rch data(R0(15) to R0 (0)) Cleared to "0" when DMA request is accepted Receive L1 (31) to L1 (0) DMA request for a read from Rch data (R0(23) to R0 (8)) DMA request for a read from Lch data(L0(23) to L0 (16)) , Rch data(R0 (7) to R0 (0)) Cleared to "0" when DMA request is accepted Receive L1 (23) to L1 (0) Receive L1 (15) to L1 (0) DMA request for a read from Lch data(R0(15) to R0 (0)) Cleared to "0" when DMA request is accepted

M30245 Group A/D converter Rev.2.00 Oct 16, 2006 page 168 of 264 REJ03B0005-0200 A/D converter The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling amplifier. Pins P10 0 to P107 function as the analog signal input pins. Set the direction registers corresponding to a pin with A/D conversion to input. The result of an A/D conversion is stored in the AD registers of the selected pins. Table 1.56 shows the performance of the A/D converter. Figure 1.125 shows the block diagram of the A/D converter, and Figure 1.126 and Figure 1.127 show the A/D converter-related registers. Table 1.56. A/D Converter performance Note 1: Doesnot depend on use of sample and hold function. Note 2: Whenf(Xin) is over 10 MHz, the ΦAD frequency must be set under 10MHz with the frequency select bits (bits 7 at 03D616 and bit 4 at 03D716). Without the sample and hold function, set the ΦAD to 250kHz or higher. With the sample and hold function, set the ΦAD frequency to 1 MHz or higher. Note 3: Set the port direction register to input. Item Performance A/D conversion method Successiv e approximation (capacitive coupling amplifier) Analog input voltage (Note 1) 0V to AVcc (Vcc) Operating clock ΦAD (Note 2) fAD, fAD/2, fAD/3, fAD/4 fAD=f(Xin) Resolution 8-bit or 10-bit (selectable) Non-linear accuracy Operating modes

• One-shot mode Repeat mode Single sweep mode Repeat sweep mode 0 Repeat sweep mode 1 Analog input pins 8 pins (AN 0 to AN7) A/D conversion start condition Software trigger -A/D conversion startswhen the A/D conversion start flag changes to "1" External trigger (canberetriggered) -A/D conversion startswhen AD TRG/P93 input changes from "H" to "L" (Note 3) Conversion speedper pin Without sample and hold function 8-bit resolution: 49 ΦAD cycles 10-bit resolution: 59 ΦAD cycles With sampleand hold function 8-bit resolution: 28 ΦAD cycles 10-bit resolution: 33 ΦAD cycles

M30245 Group A/D converter Rev.2.00 Oct 16, 2006 page 169 of 264 REJ03B0005-0200 Figure 1.125. A/D converter block diagram AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AD register 0 AD register 1 AD register 2 AD register 3 AD register 4 AD register 5 AD register 6 AD register 7 r edoce D (03C116, 03C016) (03C316, 03C216) (03C516, 03C416) (03C716, 03C616) (03C916, 03C816) (03CB16, 03CA16) (03CD16, 03CC16) (03CF16, 03CE16) 000 001 010 011 100 101 110 111 Successive conversion register Resistor ladder AD control register 0 (address 03D616) AD control register 1 (address 03D716) 1/21/2 fAD φAD ADCON0 : CH2, CH1, CH0 P10 ComparatorAddress fAD fAD/3 fAD/2 fAD/4 CKS0 CKS1

M30245 Group A/D converter Rev.2.00 Oct 16, 2006 page 170 of 264 REJ03B0005-0200 Figure 1.126. A/D converter-related registers (1) Bit Symbol Function R W Symbol ADCON0 Address 03D616 AD control register 0 (Note 1) Note 1: If the AD control regsiter 0 is rewritten during A/D conversion, the conversion result is indeterminate. Note 2: When changing A/D operation mode, reset the analog input pin. Note 3: This bit is disabled in single-sweep mode, repeat-sweep mode 0 and repeat-sweep mode 1. Note 4: Set to "1" when AD TRG is selected. Note 5: When f(XIN) exceeds 10 MHz, the AD frequency must be set less than 10 MHz by dividing. When reset 0016 Bit Name CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 Analog input pin select bit A/D operation mode select bit 0 Trigger select bit A/D conversion start flag Frequency select bit (Note 5) 0 0 0 : AN0 0 0 1 : AN1 0 1 0 : AN2 0 1 1 : AN3 (Note 2, 3) 1 0 0 : AN4 1 0 1 : AN5 1 1 0 : AN6 1 1 1 : AN7 0 0 : One-shot mode 0 1 : Repeat mode (Note 2) 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 Repeat sweep mode 1 0 : Software trigger 1 : AD TRG trigger 0 : A/D conversion disabled 1 : A/D conversion enabled (Note 4) 0 : fAD/3 or fAD/4 is selected 1 : fAD/1 or fAD/2 is selected O O O O O O O O O O O O O O O O b2 b1 b0 b4 b3 Bit Symbol Function R W Symbol ADCON1 Address 03D716 AD control register 1 (Note 1) Note 1: If the AD control regsiter 1 is rewritten during A/D conversion, the conversion result is indeterminate. Note 2: This bit is invalid in one-shot mode and repeat mode. Channels shown in parentheses are valid when repeat-sweep mode 1 (bit 2 = "1") is selected. Note 3: When f(XIN) exceeds 10 MHz, the AD frequency must be set less than 10 MHz by dividing. When reset 0016 Bit Name SCAN0 SCAN1 MD2 BITS CKS1 VCUT A/D sweep pin select bit A/D operation mode select bit 1 8/10-bit mode select bit Frequency select bit (Note 3) Vref connect bit 0 0 : AN0, AN1 (AN0) 0 1 : AN0 to AN3 (AN0, AN1) (Note 2) 1 0 : AN0 to AN5 (AN0 to AN2) 1 1 : AN0 to AN7 (AN0 to AN3) 0 : Any mode other than repeat-sweep mode 1 1 : Repeat-sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD/1 or fAD/3 is selected 0 : Vref not connected 1 : Vref connected O O O O O O O O _ _ O O O O b1 b0 Nothing is assigned. Write "0" when writing to these bits. The value is indeterminate when read. b7 b0b6 b5 b4 b3 b2 b1 b7 b0b6 b5 b4 b3 b2 b1

M30245 Group A/D converter Rev.2.00 Oct 16, 2006 page 171 of 264 REJ03B0005-0200 Figure 1.127. A/D converter-related registers (2) Bit Symbol Function RW Symbol ADCON2 Address 03D416 AD control register 2 (Note) Note : If the AD control register 2 is rewritten during A/D conversion, the conversion result is indeterminate. When reset X00X0XX02 Bit Name SMP A/D conversion method select bit 0 :Without sample and hold 1 :With sample and hold O O O O Reserved Must always be set to "0" 00 0 b7 b0b6 b5 b4 b3 b2 b1 Function RW _ _ Symbol ADi (i = 0 to 7) Address 03C016 to 03CF 16 When reset Indeterminate AD register i (i = 0 to 7) (b15) (b8) b0b7 b0 O XEight low-order bits of A/D conversion results During 10-bit mode: Two high-order bits of A/D conversion results. During 8-bit mode: The values are indeterminate when read. Nothing is assigned. Write "0" when writing to these bits. The values are indeterminate when read. O X _ _Nothing is assigned. Write "0" when writing to these bits. The value is indeterminate when read. Nothing is assigned. Write "0" when writing to these bits. The value is indeterminate when read. Reserved Must always be set to "0" Nothing is assigned. Write "0" when writing to this bit. The value is indeterminate when read. _ _ _ _ O O

M30245 Group A/D converter Rev.2.00 Oct 16, 2006 page 172 of 264 REJ03B0005-0200 One-shot mode In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A/D conversion. Table 1.57 shows the specifications of one-shot mode. Table 1.57. One-shot mode specifications Item Specification Function The pin selected by the analog input pin select bit is used for one A/D conversion. Start condition Writing "1" to A/D conversion start flag, external trigger. Stop condition End of A/D conversion (A/D conversion start flag changes to "0" except when external trig- ger is selected) Writing "0" to A/D conversion start flag. Interrupt request generation timing End of A/D conversion. Input pin One of AN0 to AN7, as selected. A/D converter results Read AD register corresponding to selected pin. Repeat mode In repeat mode, the pin selected using the analog input pin select bit is used for repeated A/D conversion. Table 1.58 shows the specifications of repeat mode. Table 1.58. Repeat mode specifications Item Specification Function The pin selected by the analog input pin select bit is used for repeated A/D conversion. Start condition Writing "1" to A/D conversion start flag, external trigger. Stop condition Writing "0" to A/D conversion start flag. Interrupt request generation timing None generated. Input pin One of AN0 to AN7, as selected. A/D converter results Read AD register corre sponding to selected pin (at any time).

M30245 Group A/D converter Rev.2.00 Oct 16, 2006 page 173 of 264 REJ03B0005-0200 Single sweep mode In single sweep mode, the pins selected using the A/D sweep pin select bit are used for one-by-one A/D conversion. Table 1.59 shows the specifications of single sweep mode. Table 1.59. Single sweep mode specifications Item Specification Function The pins selected by the A/D sweep pin select bit are used for one-by-one A/D conversion. Start condition Writing "1" to A/D converter start flag, external trigger. Stop condition End of A/D conversion (A/D conversion start flag changes to "0" except when external trig- ger is selected). Writing "0" to A/D conversion start flag. Interrupt request generation timing End of Sweep. Input pin AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins). A/D converter results Read AD regis ter corresponding to selected pin. Repeat sweep mode 0 In repeat sweep mode 0, the pins selected using the A/D sweep pin select bit are used for repeat sweep A/D conversion. Table 1.60 shows the specifications of repeat sweep mode 0. Table 1.60. Repeat sweep 0 specifications Item Specification Function The pins selected by th e A/D sweep pin select bit are used for repeat sweep A/D conversion. Start condition Writing "1" to A/D conversion start flag. Stop condition Writing "0" to A/D conversion start flag. Interrupt request generation timing None generated. Input pin AN 0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins). A/D converter results Read AD register corresponding to selected pin (at any time).

M30245 Group A/D converter Rev.2.00 Oct 16, 2006 page 174 of 264 REJ03B0005-0200 Repeat sweep mode 1 In repeat sweep mode 1, all pins are used for A/D conversion with emphasis on the pin or pins selected using the A/ D sweep pin select bit. Table 1.61 shows the specifications of repeat sweep mode 1. Table 1.61. Repeat sweep mode 1 specifications Item Specification Function All pinsperform repeat sweep A/D conversion with emphasis on the pin or pins selected by the A/D sweep pin select bit. Example: AN0 selected: AN0 AN1 AN0 AN2 AN0 AN3 etc. Start condition Writing "1" to A/D conversion start flag. Stop condition Writing "0" to A/D conversion start flag. Interrupt request generation timing None generated. Input pin AN0 to AN7. Pin emphasis AN0 (1 pin) AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins). A/D converter results Read AD register corresponding to selected pin (at any time). Resolution select function 8 or 10-bit mode select bit of AD control register 1 (bit 3 at address 03D7 16) When set to 10-bit precision, the low 8-bits are stored in the even addresses and the high 2 bits in the odd ad- dresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses. Sample and hold Sample and hold is selected by setting bit 0 of the AD control register 2 (address 03D4 16) to "1". When sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 f AD cycle is achieved with 8-bit resolution and 33 f AD with 10-bit resolution. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before starting A/D conversion whether sample and hold is to be used. Power consumption reduction function The VREF connect bit (bit 5 at addresses 03D7 16) can be used to isolate the resistance ladder of the A/D converter from the reference voltage pin (V REF) when the A/D converter is not used. This stops any current from flowing into the resistance ladder from V REF, reducing the power dissipation. When using the A/D converter, start A/D conversion only after connecting VREF. Do not write A/D conversion start flag and V REF connect bit to "1" at the same time. Precautions

• Write to each bit (except bit 6) of AD control register 0, AD control register 1, and to bit 0 of AD control register 2 when A/D conversion is stopped (before a trigger occurs). When the V REF connection bit is changed from "0" to "1", wait 1 µs or longer before starting A/D conversion.
• When changing A/D operation mode, select the analog input pin again.

M30245 Group A/D converter Rev.2.00 Oct 16, 2006 page 175 of 264 REJ03B0005-0200

• Using one-shot mode or single sweep mode: Read the corresponding AD register after confirming A/D conversion is finished. (Check the A/D conversion interrupt request bit.)
• Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1: Use the undivided main clock as the internal CPU clock. When f(Xin) is faster than 10MHz, make the A/D frequency 10MHz or less by dividing. Output impedance of sensor at A/D conversion (Reference value). To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 1.126 has to be completed within a specified period of time T. Let the output impedance of sensor equivalent circuit be R0, the microcomputer's internal resistance be R, the precision (error) of the A/D converter be X, and the A/D converter’s resolution be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode). VC C (3.0pF)VIN Internal circuit of microprocessor Sensor-equivalent circuit R (7.8k )R0 Ω Vc is generally = VIN {1 - e - C(R0+R) } t And when t = T, Vc = VIN - X VIN = VIN (1 - X) YY T C(R0+R) = X Ye - T C(R0+R) = In X Y - Therefore, R0 = - C I n X Y T - R With the model shown in Figure 1.128 as an example, when the difference between V IN and VC becomes 0.1LSB, we find impedance R0 when voltage between pins VC changes from 0 to V IN-(0.1/1024) VIN in time T. (0.1/1024) means that A/D precision drop due to insufficient capacitor charge is held to 0.1LSB at time of A/D conversion in the 10-bit mode. Actual error however is the value of absolute precision added to 0.1LSB. When f(X in) = 10 MHz, T = 0.3 us in the A/D conversion mode with sample & hold. Output impedance R0 for sufficiently charging capacitor C within time T is determined as follows. If T = 0.3µs, R = 7.8kΩ, C = 3pF, X = 0.1, and Y = 1024 Then R0 = - 7.8 x 103 = approximately 3.0 x 1030.3 x 10-6 3.0 x 10-12 In 0.1 1024 Thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the A/D converter turns out Figure 1.128. A circuit equivalent to the A/D conversion terminal

M30245 Group A/D converter Rev.2.00 Oct 16, 2006 page 176 of 264 REJ03B0005-0200 Table 1.62. Output impedance values based on the LSB values (10-bit mode) Table 1.63. Output impedance values based on the LSB values (8-bit mode) f(XIN) (MHz) Cycle (µs) T (Sampling time) R (Kohm) C(pF) Resolution (LSB) R0max (Kohm) 10 0.1 0.3 (3 x cycle, sample and hold bit enabled 7.8 3.0 0.1 3.0 0.3 4.5 0.5 5.3 0.7 5.9 0.9 6.4 1.1 6.8 1.3 7.2 1.5 7.5 1.7 7.8 1.9 8.1 10 0.1 0.2 (2 x cycle, Sample and hold bit is enabled) 7.8 3.0 0.3 0.4 0.5 0.9 0.7 1.3 0.9 1.7 1.1 2.0 1.3 2.2 1.5 2.4 1.7 2.6 1.9 2.8 f(XIN) (MHz) T (Sampling time) R (Kohm) C(pF) Resolution (LSB) R0max (Kohm) 10 0.1 0.3 (3 x cycle, sample and hold bit enabled 7.8 3.0 0.1 4.9 0.3 7.0 0.5 8.2 0.7 9.1 0.9 9.9 1.1 10.5 1.3 11.1 1.5 11.7 1.7 12.1 1.9 12.6 10 0.1 0.2 (2 x cycle, Sample and hold bit is enabled) 7.8 3.0 0.1 0.7 0.3 2.1 0.5 2.9 0.7 3.5 0.9 4.0 1.1 4.4 1.3 4.8 1.5 5.2 1.7 5.5 1.9 5.8 Cycle (µs)

M30245 Group CRC Calculation Circuit Rev.2.00 Oct 16, 2006 page 178 of 264 REJ03B0005-0200 Figure 1.130. CRC-related registers Bit symbol R W _ _ O O When reset 0XXXXXX02 Symbol CRCMR Address 03B616 Function 0 : x16 + x12 + x5 + 1 (CRC-CCITT) 1 : x16 + x15 + x2 + 1 (CRC-16)CRCPS Nothing is assigned. Write "0" when writing to this bit. The value is indeterminate if read. CRCMS CRC mode polynomial selection bit CRC mode selection bit 0 : LSB first mode 1 : MSB first mode O O _ _ O O When reset Symbol CRCSAR Address 03B516, 03B416 CRC snoop address register b7 b0 (b8)(b15) b7 b0 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled Nothing is assigned. Write "0" when writing to this bit. The value is indeterminate if read. CRC Snoop on read enable bit O O CRC mode register b7 b0 CRC Snoop on write enable bit R W CRCSAR9-0 O O Bit name Bit name Function (b15) (b8) CRC data register Symbol CRCD Address 03BD16 to 03BC16 When reset Indeterminate Function Values that can be set CRC calculation result output 000016 to FFFF16 R W O O b7 b0b7 b0 Symbol CRCIN Address 03BE16 When reset Indeterminate Function Data input 0016 to FF16 R W O O b7 b0 CRC input register Values that can be set CRC Snoop address bits CRCSR CRCSW Bit symbol Note: Only USB, UART and SSI related registers can be snooped SFR address to snoop (Note)

M30245 Group CRC Calculation Circuit Rev.2.00 Oct 16, 2006 page 179 of 264 REJ03B0005-0200 Figure 1.131. CRC example using CRC-CCITT (LSB first mode) b15 b0 (1) Setting 000016 CRC data register CRCD [03BD16, 03BC16] b0b7 b15 b0 (2) Setting 0116 CRC input register CRCIN [03BE16] 2 cycles After CRC calculation is complete CRC data register CRCD [03BD 16, 03BC16] 118916 Stores CRC code b0b7 b15 b0 (3) Setting 2316 CRC input register CRCIN [03BE 16] After CRC calculation is complete CRC data register CRCD [03BD 16, 03BC16]0A4116 Stores CRC code The code resulting from sending 0116 in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial, (X16 + X12 + X5 + 1), becomes the remainder resulting from dividing (1000 0000) X 16 by (1 0001 0000 0010 0001) in conformity with the modulo-2 operation. Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000) corresponds to 118916 in hexadecimal notation. If the CRC operation in MSB first mode is necessary, set the CRC mode 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 1000 1000 LSB MSBLSB MSB 98 1 1 Modulo-2 operation is operation that complies with the law given below. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 -1 = 1 selection bit to "1". CRC data register stores CRC code for MSB first mode.

M30245 Group Programmable I/O Ports Rev.2.00 Oct 16, 2006 page 181 of 264 REJ03B0005-0200 Figure 1.132. Programmable I/O ports (1) P20 to P27, P30 to P37, P40 to P47, P50 to P54,P56 P13 to P17 Data bus Direction register Pull-up selection Port latch Data bus Direction register Pull-up selection Port latch Port P1 control register Note : symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. (Note) (Note) P00 to P07 Data bus Direction register Pull-up selection Port latch (Note) P10 to P12 Data bus Direction register Pull-up selection Port latch Port P1 control register (Note) AND Flash control AND flash port enable bit AND Flash control logic

M30245 Group Programmable I/O Ports Rev.2.00 Oct 16, 2006 page 182 of 264 REJ03B0005-0200 Figure 1.133. Programmable I/O ports (2) P70, P71 P55, P93 Data bus Direction register Pull-up selection Port latch Input to respective peripheral functions "1" Output Direction register Port latch Input to respective peripheral functions Note :1 symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. Note :2 symbolizes a parasitic diode. (Note1) (Note2) Data bus P72 to P77 Direction register Port latch Pull-up selection Data bus Input to respective peripheral functions "1" Output (Note 1) Drive capacity control register Drive capacity control register P57, P60 to P67 P80, P81 Direction register Port latch Pull-up selection Data bus Input to respective peripheral functions "1" Output (Note)

M30245 Group Programmable I/O Ports Rev.2.00 Oct 16, 2006 page 183 of 264 REJ03B0005-0200 Figure 1.134. Programmable I/O ports (3) Note : symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. P85 Data bus NMI interrupt input (Note) P82 to P84 Data bus Direction register Pull-up selection Port latch Input to respective peripheral functions (Note) P90 Direction register Pull-up selection Port latchData bus (Note) UVcc P90-second ATTACH P87 P86 fc Rf Data bus Direction register Pull-up selection Port latch "1" Output Direction register Pull-up selection Port latchData bus (Note) (Note) Rd

M30245 Group Programmable I/O Ports Rev.2.00 Oct 16, 2006 page 185 of 264 REJ03B0005-0200 Figure 1.137. Direction registers Bit Symbol Bit Name Function R W PD8_0 PD8_1 PD8_2 PD8_3 PD8_4 Port P80 direction register Port P81 direction register Port P82 direction register Port P83 direction register Port P84 direction register O O Symbol PD8 Address 03F216 When reset 00X000002 Port P8 direction register b7 b5b6 b4 b3 b2 b1 b0 O O O O O O O O O O O O _ _ Bit Symbol Bit Name Function R W PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7 Port Pi0 direction register Port Pi1 direction register Port Pi2 direction register Port Pi3 direction register Port Pi4 direction register Port Pi5 direction register Port Pi6 direction register Port Pi7 direction register 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) O O Symbol PDi (i = 0 to 7, 10) Address 03E216, 03E316, 03E616, 03E716, 03EA16 03EB16, 03EE16, 03EF16, 03F616 When reset 0016 Port Pi direction register (Note) b7 b5b6 b4 b3 b2 b1 b0 O O O O O O O O O O O O O O 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) Nothing is assigned. Write "0" when writing to this bit. The value is indeterminate if read. 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) PD8_6 PD8_7 Port P86 direction register Port P87 direction register Bit Symbol Bit Name Function R W PD9_0 PD9_2 PD9_3 Port P90 direction register Port P92 direction register Port P93 direction register Symbol PD9 Address 03F316 When reset XXXX00XX02 Port P9 direction register b7 b5b6 b4 b3 b2 b1 b0 O O O O O O _ _ 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) Nothing is assigned. Write "0" when writing to this bit. The value is "0" if read. 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) Nothing is assigned. Write "0" when writing to this bit. The value is "0" if read. _ _ Note: In memory expansion mode and microprocessor mode, the contents of corresponding Port Pi direction register of pins A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD HLDA and BCLK cannot be modified.

M30245 Group Programmable I/O Ports Rev.2.00 Oct 16, 2006 page 186 of 264 REJ03B0005-0200 Figure 1.138. Port registers Bit Symbol Bit Name Function R W Pi_0 Pi_1 Pi_2 Pi_3 Pi_4 Pi_5 Pi_6 Pi_7 Port Pi 0 register Port Pi1 register Port Pi2 register Port Pi3 register Port Pi4 register Port Pi5 register Port Pi6 register Port Pi7 register Data is input and output to and from each pin by reading the writing to and from each corresponding bit. 0 : "L" level data 1 : "H" level data (Note 1) O O Symbol Pi (i = 0 to 7, 10) Address 03E0 16, 03E116, 03E416, 03E516, 03E816 03E916, 03EC16, 03ED16, 03F416 When reset 0016 Port Pi register (Note 2) b7 b5b6 b4 b3 b2 b1 b0 O O O O O O O O O O O O O O Note 1: Because P70 and P71 are N-channel open drain ports, the data are high-impedance. Note 2: In memory expansion mode and microprocessor mode, the contents of corresponding port Pi register of pins A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD HLDA and BCLK cannot be modified. Bit Symbol Bit Name Function R W P8_0 P8_1 P8_2 P8_3 P8_4 P8_5 P8_6 P8_7 Port P8 0 register Port P81 register Port P82 register Port P83 register Port P84 register Port P85 register Port P86 register Port P87 register Data is input and output to and from each pin by reading the writing to and from each corresponding bit. 0 : "L" level data 1 : "H" level data (except P8 O O Symbol Address 03F016 When reset 00X000002 Port P8 register b7 b5b6 b4 b3 b2 b1 b0 O O O O O O O O O O O O O X Bit Symbol Bit Name Function R W P9_0 VBDS P9_2 P9_3 Port P90 register Vbus detect state bit Port P92 register Port P93 register _ _ Symbol Address 03F116 When reset Indeterminate Port P9 register b7 b5b6 b4 b3 b2 b1 b0 O O O O O O O X Nothing is assigned. Write "0" when writing to these bits. The value is "0" if read. 0 : "L" level data 1 : "H" level data 0 : Not powered 1 : Powered (Note) 0 : "L" level data 1 : "H" level data 0 : "L" level data 1 : "H" level data Note: This pin cannot be used for GPI/O. This bit reads "0" when Vbus detect is disabled.

M30245 Group Programmable I/O Ports Rev.2.00 Oct 16, 2006 page 187 of 264 REJ03B0005-0200 Figure 1.139. Pull-up control registers Bit Symbol Bit Name Function R W PU00 PU01 PU02 PU03 PU04 PU05 PU06 PU07 0 to P03 pull up P04 to P07 pull up P10 to P13 pull up P14 to P17 pull up P20 to P23 pull up P24 to P27 pull up P30 to P33 pull up P34 to P37 pull up The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high O O Symbol PUR0 Address 03FC When reset 0016 Pull-up control register 0 (Note) b7 b5b6 b4 b3 b2 b1 b0 O O O O O O O O O O O O O O Note: In memory expansion and microprocessor mode, the contents of this register can be changed but the pull-up resistor is not connected. Nothing is assigned. Write "0" when writing to these bits. The value is "0" if read. Bit Symbol Bit Name Function R W PU10 PU11 PU12 PU13 PU14 PU15 PU16 PU17 0 to P43 pull up (Note 3) P44 to P47 pull up P50 to P53 pull up (Note 3) P54 to P57 pull up P60 to P63 pull up P64 to P67 pull up P70 to P73 pull up (Note 1) P74 to P77 pull up The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high O O Symbol PUR1 Address 03FD16 When reset (Note 2) 0016 Pull-up control register 1 b7 b5b6 b4 b3 b2 b1 b0 O O O O O O O O O O O O O O Note 1: Pull-up is not available for P70 and P71 because they are N-channel open drain ports. Note 2: This register becomes 0216 when reset under the following conditions: a) Hardware reset: when Vcc is applied to the CNVss pin. b) Software reset: if bit 1 and bit 0 of processor mode register 0 (address 000416) are 102 or 112 before reset. Note 3: In memory expansion and microprocessor mode, the contents of this register can be changed but the pull-up resistor is not connected. Bit Symbol Bit Name Function R W PU20 PU21 PU22 P80 to P83 pull up P84 to P87 pull up (except P85) P90 to P93 pull up (except P91) The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high O O Symbol PUR2 Address 03FE When reset 0016 Pull-up control register 2 b7 b5b6 b4 b3 b2 b1 b0 O O _ _ O O O O O O PU24 PU25 P100 to P103 pull up P104 to P107 pull up The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high _ _Nothing is assigned. Write "0" when writing to these bits. The value is "0" if read.

M30245 Group Programmable I/O Ports Rev.2.00 Oct 16, 2006 page 188 of 264 REJ03B0005-0200 Figure 1.140. High drive capacity register Bit Symbol Bit Name Function R W P7DR0 P7DR1 P7DR2 P7DR3 P7DR4 P7DR5 P7DR6 P7DR7

0 LED drive capacity

capacity is activated for the corresponding bit. 0 : Normal drive 1 : N-channel high drive O O Symbol P7DR Address 03FA When reset 0016 Port 7 drive capacity register b7 b5b6 b4 b3 b2 b1 b0 O O O O O O O O O O O O O O Figure 1.141. Port control register Note 1: With external clock input to XIN pin. Note 2: VbusDTCT pin is pulled down internaly. Pin name Connection P0 to P10 (excluding P85) After setting to input mode, connect every pin to Vss or Vcc using a resistor. OR Leave these pins open after setting to output mode. Xout (Note 1) Open NMI Connect using resistor to Vcc (pull-up) UVcc, AVcc Connect to Vcc AVss, VREF, BYTE Connect to Vss USB D+, USB D-, LPF, VbusDTCT (Note 2) Open Table 1.64. Example connection of unused pins in single-chip mode When reset 0016 Bit Symbol Bit Name Function R W PCR0 Port P1 control register Symbol PCR Address 03FF16 Port control register b7 b5b6 b4 b3 b2 b1 b0 O O _ _ 0 : When input port, read port input level. When output port, read the contents of Port P1 register. 1 : Read the contents of Port P1 register through input/output port. Nothing is assigned. Write "0" when writing to this bit. The value is"0" when read. OECTRL WECTRL AFPE AND Flash OE control bit AND Flash WE control bit AND Flash port enable bit 0 : Data read mode enabled 1 : Output disabled 0 : Input disabled 1 : Command/Address mode enabled 0 : P0 & P1( 0-2) GPI/O function 1 : P0 & P1(0-2) AND Flash control function O O O O O O

M30245 Group Programmable I/O Ports Rev.2.00 Oct 16, 2006 page 189 of 264 REJ03B0005-0200 Note 1: With external clock input to XIN pin. Note 2: VbusDTCT pin is pulled down internaly. Pin name Connection P6 to P10 (excluding P85) After setting to input mode, connect every pin to Vss or Vcc using a resistor. OR Leave these pins open after setting to output mode. P45/CS1 to P47/CS3 Set ports to input mode, set bits CS1 to CS3 to "0" (chip select disabled), connect to Vcc using resistors (pull-up) BHE, ALE, HLDA, XOUT (Note 1), BCLK Open HOLD, RDY, NMI Connect using a resistor to Vcc (pull-up) UVcc, AVcc Connect to Vcc AVss, VREF, BYTE Connect to Vss USB D+, USB D-, LPF, VbusDTCT (Note 2) Open Table 1.65. Example connection of unused pins in memory expansion mode Figure 1.142. Example connection of unused pins Precautions Dedicated Input Pins If a dedicated input pin is connected to a power supply different from the supply that Vcc is connected to, a resistor (approximately 1k ohm) should be added between the input pin and the connected power supply. However, if the dedicated input pin voltage is higher than Vcc, latch up could occur. A resistor is not required when using a Vcc voltage equal or greater than the voltage of the dedicated input pin. Port P0 to P10 (except for P85) (Input mode).. (Input mode) (Output mode) NMI XOUT UVcc, AVcc BYTE AVSS VREF Microcomputer VSS In single-chip mode Port P6 to P10 (except for P85) (Input mode).. (Input mode) (Output mode) NMI XOUT UVcc, AVcc AVSS VREF Open Microcomputer VCC VSS In memory expansion mode or in microprocessor mode HOLD RDY ALE BCLK (Note) BHE HLDA Open Open Open ... ... Port P45 / CS1 to P47 / CS3 Note : When the BCLK output disable bit (bit 7 at address 000416) is set to "1", connect to VCC using a pull-up resistor. LPF Open USB D+, USB D- Open OpenUSB D+, USB D- Open LPF VbusDTCT Open Vcc Vcc Vcc OpenVbusDTCT Vcc

M30245 Group And Flash Control Circuit Rev.2.00 Oct 16, 2006 page 193 of 264 REJ03B0005-0200 Sample AND Flash Code Figures 1.147 and 1.148 show sample code segments of AND flash read and write (program) assembly routines. ; Test Read Access to AND Flash MOV.B #03EH, P1 ; Initialize Port 1 MOV.B #07FH, PD1 ; Initialize Port 1 MOV.B #00AH, PCR ; Initialize AND_Flash Control Register MOV.B #040H, P1 ; Release AND_Flash RESET BCLR 3, P1 ; Select External Flash memory BCLR 4, P1 ; Mode : Command Mode BSET 1, PCR ; Release Data Read Mode BSET 2, PCR ; Mode : Write Command / Address Mode MOV.B #000H, P0 ; Write Command 00 = Read BSET 4, P1 ; Mode : Address Mode MOV.B #034H, P0 ; Sector Address 1 MOV.B #012H, P0 ; Sector Address 2 MOV.B #000H, P0 ; Column Address 1 MOV.B #000H, P0 ; Column Address 2 BCLR 1, PCR ; Mode : Data Read Mode RYBY02: BTST 7, P1 ; Wait to RY/BYB = 0 JNE RYBY02 RYBY12: BTST 7, P1 ; Wait to RY/BYB = 1 JEQ RYBY12 MOV.W #$0000H, A0 ; Initialize A0 READDATA: MOV.B P0, RAMAD[A0] ; Read Data CMP.W #0083FH, A0 ; I = 2112? JEQ READEND INC.W A0 ; I = I + 1 JMP READDATA READEND: BSET 1, PCR ; Release Data Read Mode BSET 3, P1 ; Unselect External Flash memory Figure 1.147. AND Flash read example program

M30245 Group And Flash Control Circuit Rev.2.00 Oct 16, 2006 page 194 of 264 REJ03B0005-0200 Figure 1.148 AND Flash write example program ; Test Write Access to AND Flash MOV.B #03EH, P1 ; Initialize Port 1 MOV.B #07FH, PD1 ; Initialize Port 1 MOV.B #00AH, PCR ; Initialize AND_Flash Control Register MOV.B #040H, P1 ; Release AND_Flash RESET BCLR 3, P1 ; Select External Flash memory BCLR 4, P1 ; Mode : Command Mode BSET 1, PCR ; Release Data Read Mode BSET 2, PCR ; Mode : Write Command / Address Mode MOV.B #011H, P0 ; Write Command 11 = Program 4 BSET 4, P1 ; Mode : Address Mode MOV.B #034H, P0 ; Sector Address 1 MOV.B #012H, P0 ; Sector Address 2 MOV.B #000H, P0 ; Column Address 1 MOV.B #000H, P0 ; Column Address 2 BCLR 2, PCR ; Release Command Mode RYBY03: BTST 7, P1 ; Wait to RY/BYB = 0 JNE RYBY03 RYBY13: BTST 7, P1 ; Wait to RY/BYB = 1 JEQ RYBY13 BCLR 4, P1 ; Mode : Data Entry Mode MOV.W #$0000H, A0 TRANSDATA: MOV.B RAMAD[A0], P0 CMP.W #0083FH, A0 JEQ TRANSEND INC.W A0 JMP TRANSDATA TRANSEND: BSET 2, PCR ; Mode : Write Command / Address Mode MOV.B #040H, P0 ; Auto Program Data BSET 4, P1 ; Mode : CDE=H RYBY13B: BTST 7, P1 ; Wait to RY/BYB = 1 JEQ RYBY13B BSET 1, PCR ; Release Data Read Mode BSET 3, P1 ; Unselect External Flash memory

Rev.2.00 Oct 16, 2006 page 195 of 264 REJ03B0005-0200 Flash memory The M30245FC contains flash memory that can be rewritten with a single voltage of 3.3 V. Three flash memory modes are available to read, program, and erase:

• CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU).
• Parallel I/O and standard serial I/O modes can be manipulated using a programmer The flash memory is divided into several blocks as shown in Figure 1.149. Memory can be erased one block at a time. Each block has a lock bit to enable or disable execution of an erase or program operation. This allows data in each block to be protected. Table 1.67 shows an overview of the M30245 (flash memory version). In addition to the ordinary user ROM area that stores the microcomputer operation program, the flash memory has a boot ROM area that stores a program to control rewriting in CPU rewrite and standard serial I/O modes. The boot ROM area has a standard serial I/O mode control program stored in it when it is shipped from the factory. However, the user can write a CPU rewrite control program in this area specific to the user's applica- tion system. The boot ROM area can only be rewritten in parallel I/O mode. User ROM area Boot ROM area Note 1: The boot ROM area can be rewritten only in parallel input/ output mode. (Access to any other areas is inhibited.) Note 2: To specify a block, use the maximum address in the block that is an even address. 8K bytesFE00016 FFFFF16 F000016 Block 3 : 32K bytes F800016 Block 2 : 8K bytes F A00016 Block 1 : 8K bytes Block 0 : 16K bytes FC00016 FFFFF16 E000016 Block 4 : 64K bytes Figure 1.149. Flash memory version user ROM memory map

Rev.2.00 Oct 16, 2006 page 196 of 264 REJ03B0005-0200 Table 1.67. M30245 Flash Memory Overview Note: The boot ROM contains a stored standard serial I/O control program when it is shipped from the factory. This area can be erased and programmed in parallel I/O mode only. Item Performance Power supply voltage 3.0V to 3.6V Program/erase voltage 3.0V to 3.6V Flash memory operation mode 3 modes: CPUrewrite Parallel I/O Standard serial I/O Erase block division User ROM area See Figure 1.141 Boot ROM area One division (8 Kbytes) Note Program method In page units (256 bytes) Erase method Collective erase/block erase Program/erase control method Program/erase control by software command Protect method Protection for each block by lock bit Number of commands 8 Program/erase count 100 times Data holding 10 years ROM code protect Parallel I/O and Standa rd serial I/O modes are supported

M30245 Group CPU Rewrite Mode Rev.2.00 Oct 16, 2006 page 197 of 264 REJ03B0005-0200 CPU Rewrite Mode In CPU rewrite mode, the on-chip flash memory can be read, programmed, or erased under control of the Central Processing Unit (CPU). Only the user ROM area, shown in Figure 1.149, can be rewritten. The boot of the user ROM area.ROM area cannot be rewritten. Make sure the program and block erase commands are issued only for each block The control program for CPU rewrite mode can be stored in either the user ROM or the boot ROM area. Because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to an area other than the internal flash memory before it can be executed. Overview In the CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by software commands. Operations are executed from a memory other than the internal flash memory, such as the internal RAM. When the CPU rewrite mode select bit (bit 1 at address 02F7 16) is set to "1", transition to CPU rewrite mode occurs and software commands can be accepted. Read and write software commands and data to even-numbered addresses ("0" for address A0) in 16-bit units. For 8-bit mode, always write 8-bit software commands to even-numbered addresses. Commands are ignored with odd-numbered addresses. Use software commands to control program and erase operations. The status register can verify if a program or erase operation has terminated normally or in error. Figure 1.150 shows the flash memory control register 0. Figure 1.151 shows a flowchart for enabling/disabling the CPU rewrite mode. Always follow the operation as indicated in these flowcharts. Bit 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming and erase operations, it is "0". Otherwise, it is "1". Bit 1 is the CPU rewrite mode select bit. The CPU rewrite mode is entered by setting this bit to "1" to make software commands accepted. In CPU rewrite mode, the CPU becomes unable to access the internal flash memory directly so, write bit 1 in an area other than the internal flash memory. To set this bit to "1", it is necessary to write "0" and then write "1" in succession when the NMI pin is "H" level. The bit can be set to "0" by only writing "0". Bit 2 is the lock bit disable bit. By setting this bit to "1", it is possible to disable erase and write protect (block lock) effected by the lock bit data. The lock bit disable select bit only disables the lock bit function; it does not change the lock data bit value. However, if an erase operation is performed when this bit = "1", the lock bit data that is "0" (locked) is set to "1" (unlocked) after being erased. To set this bit to "1", it is necessary to write "0" and then write "1" in succession. This bit can be controlled only when the CPU rewrite mode select bit = "1". Bit 3 is the flash memory reset bit used to reset the control circuit of the internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access has failed. When the CPU rewrite mode select bit is "1", writing "1" to this bit resets the control circuit. To release the reset, set this bit to "0". Bit 5 is the user ROM area select bit that is effective only in boot mode. If this bit is set to "1", the accessed area is switched from the boot ROM area to the user ROM area. When the CPU rewrite mode is used in boot mode, set this bit to "1". If the microcomputer is booted from the user ROM area, the user ROM area is always accessed and this bit has no effect. When in boot mode, the function of this bit is effective regardless of whether the CPU rewrite mode is on or off. Use a control program that is not running in the internal flash memory to rewrite this bit.

M30245 Group CPU Rewrite Mode Rev.2.00 Oct 16, 2006 page 199 of 264 REJ03B0005-0200 Microcomputer Mode and Boot Mode The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in parallel I/O mode. If the control program is written into the boot ROM area, the standard serial I/O mode becomes unusable. Normal microcomputer mode is entered when the microcomputer is reset when pulling CNV SS pin low. In this case, the CPU starts operating using the control program in the user ROM area. When the microcomputer is reset by pulling the P5 5 pin low, and the CNVSS pin and P5 0 pin high, the CPU starts operating using the control program in the boot ROM area. This mode is called the "boot" mode. The control program in the boot ROM area can also be used to rewrite the user ROM area. Block Address Block addresses refer to the maximum even address of each block. These addresses are used in the block erase command, lock bit program command, and read lock status command. Software Commands Table 1.68 lists the software commands available with the M30245 (flash memory version). After setting the CPU rewrite mode select bit to 1, write a software command to specify an erase or program operation. When entering a software command, the upper byte (D 8 to D15) is ignored. Table 1.68. List of software commands Note 1: When a software command is input, the data high-order byte (D8 to D15) is ignored. Note 2: SRD= Status register data Note 3: WA = Write address, WD = Write data. WA and WD must be set sequentially from 0016 to FE16 (even byte address). The page size is 256 bytes. Note 4: BA = Block address. Enter the maximum address of each block that is an even address. Note 5: D6 corresponds to the block lock status. When D6 = "1", the unlocked blocks are "0". Note 6: X denotes a given even address in the user ROM area. Command First bus cycle Second bus cycle Third bus cycle Mode Address Data (D0 to D7) Mode Address Data (D0 to D7) Mode Address Data (D0 to D7)

1 Read array Write X (Note 6) FF 16

2 Read status register Write X 70 16 Read X SRD (Note 2)

3 Clear status register Write X 50 16

4 Page program (Note 3) Write X 41 16 Write WA0 (Note 3) WD0 (Note 3) Write WA1 WD1

5 Block erase Write X 20 16 Write BA (Note 4) D0 16

6 Erase all unlocked blocks Write X A7 16 Write X D0 16

7 Lock bit program Write X 77 16 Write BA D0 16

8 Read lock bit status Write X 71 16 Read BA D 6 (Note 5)

M30245 Group CPU Rewrite Mode Rev.2.00 Oct 16, 2006 page 200 of 264 REJ03B0005-0200 1. Read Array Command (FF 16) The read array mode is entered by writing the command code "FF 16" in the first bus cycle. When an even address that is to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data bus (D 0-D15), 16 bits at a time. The read array mode is retained until another command is written. 2. Read Status Register Command (70 16) When the command code "70 16" is written in the first bus cycle, the content of the status register is read out at the data bus (D 0-D7) by a read in the second bus cycle. 3. Clear Status Register Command (50 16) This command clears the bits SR3 to SR5 of the status register after being set. These bits indicate that opera- tion has ended in an error. To use this command, write the command code "50 16" in the first bus cycle. 4. Page Program Command (41 16) Page program allows for high-speed programming in units of 256 bytes. Page program operation starts when the command code "41 16" is written in the first bus cycle. In the second bus cycle through the 129th bus cycle, the write data is sequentially written 16 bits at a time. At this time, the addresses A 0-A7 need to be incremented by 2 from “00 16” to "FE16." When the system finishes loading the data, it starts an auto write operation (data program and verify operation). Figure 1.152 shows an example of a page program flowchart. The completed auto write operation can be confirmed by reading the status register or the flash memory control register 0. At the same time the auto write operation starts, the read status register mode is automati- cally entered, so the content of the status register can be read out. The status register bit 7 (SR7) is set to 0 at the same time the auto write operation starts and is returned to 1 when the auto write operation has been completed. In this case, the read status register mode remains active until the Read Array command (FF 16) or Read Lock Bit Status command (71 16) is written or the flash memory is reset using its reset bit. The RY/BY status flag of the flash memory control register 0 is "0" during auto write operation and "1" when the auto write operation and status register bit 7 have been completed. After the auto write operation is completed, the status register can read out the results of the auto write opera- tion. Refer to the status register section for more details. Each block of the flash memory can be write protected by using a lock bit. Refer to the data protect function section for more details. Additional writes to the pages previously programmed are prohibited. n = FE16 Start Write 4116 n = 0 Write address n and data n RY/BY status flag = 1? Check full status Page program completed n = n + 2 NO YES NO YES Figure 1.152. Page program flowchart

M30245 Group CPU Rewrite Mode Rev.2.00 Oct 16, 2006 page 201 of 264 REJ03B0005-0200 5. Block Erase Command (2016/D016) By writing the command code "2016" in the first bus cycle and the confirmation command code "D016" in the second bus cycle to the block address of a flash memory block, the system initiates an auto erase (erase and erase verify) operation. Figure 1.153 is an example of a block erase flowchart. Read the status register or the flash memory control register 0 to confirm the completion of the auto erase operation. At the same time the auto erase operation starts, the read status register mode is automatically entered, so the contents of the status register can be read out. The status register bit 7 (SR7) is set to "0" at the same time the auto erase operation starts and is returned to "1" when the auto erase operation is completed. The read status register mode remains active until the Read Array command (FF 16) or Read Lock Bit Status command (71 16) is written or the flash memory is reset using its reset bit. The RY/BY status flag of the flash memory control register 0 is "0" during auto erase operation and "1" when the auto erase operation and status register bit 7 is completed. After the auto erase operation is completed, the status register can read for the results of the auto erase operation. Refer to the status register for more details. A lock bit protects each block of the flash memory against erasure. Refer to the data protect function section for more details. Figure 1.153. Block erase flowchart 6. Erase All Unlock Blocks Command (A716/D016) By writing the command code "A716" in the first bus cycle and the confirmation command code "D016" in the second bus cycle that follows, the system starts erasing blocks successively. Reading the status register or the flash memory control register 0 confirms whether the erase all unlock blocks command was terminated in the same way as for block erase. Also, the status register can read out the results of the auto erase operation. When the lock bit disable bit of the flash memory control register 0 = "1", all blocks are erased regardless of how the lock bit is set. On the other hand, when the lock bit disable bit = "0", the function of the lock bit is effective and only unlocked blocks (where lock bit data = "1") are erased. Write 2016 Write D016 Block address Check full status check Block erase completed Start RY/BY status flag = 1? NO YES

M30245 Group CPU Rewrite Mode Rev.2.00 Oct 16, 2006 page 203 of 264 REJ03B0005-0200 Data Protect Function (Block Lock) Each block in Figure 1.149 has a nonvolatile lock bit to specify that the block is protected (locked) against erase/write. The lock bit program command is used to set the lock bit to 0 (locked). The lock bit of each block can be read out using the read lock bit status command. Whether block lock is enabled or disabled is determined by the status of the lock bit and the lock bit disable bit in flash memory control register 0. (1) When the lock bit disable bit = "0", a specified block can be locked or unlocked by the lock bit status (lock bit data). If lock bit data = "0" (locked), they are disabled against erase/write. On the other hand, if lock bit data = "1" (unlocked) they are enabled for erase/write. (2) When the lock bit disable bit = "1", all blocks are unlocked regardless of the lock bit data, and enabled for erase/write. In this case, the lock bit data is set to "1" (unlocked) after erasure, so that the lock bit is disabled. Status Register The status register indicates the flash memory operating status and whether an erase or program operation has terminated normally or in error. Table 1.69 details the status register. The contents of this register can be read out only by writing the read status register command (70 16). Writing the Clear Status Register command (50 16) clears the status register. After a reset, the status register is set to "80 16." Table 1.69. Status register bit definition Each SRD bit Status name Definition "1" "0" SR7 (Bit 7) Write state machine (WSM) Ready Busy SR6 (Bit 6) Reserved _ _ SR5 (Bit 5) Erase status Terminated in error Terminated normally SR4 (Bit 4) Program status Terminated in error Terminated normally SR4 (Bit 3) Block status after program Terminated in error Terminated normally SR2 (Bit 2) Reserved _ _ SR1 (Bit 1) Reserved _ _ SR0 (Bit 0) Reserved _ _ Write state machine (WSM) status (SR7) After power-on, the write state machine (WSM) status is set to "1". The write state machine (WSM) status indicates the operating status of the RY/BY pin output. This status bit is set to "0" during an auto write or auto erase operation and is set to "1" when the operation is completed.

M30245 Group CPU Rewrite Mode Rev.2.00 Oct 16, 2006 page 204 of 264 REJ03B0005-0200 Erase status (SR5) The erase status indicates the operating status of an auto erase to the CPU. It is set to "1" when an erase error occurs. The erase status is reset to "0" when cleared. Program status (SR4) The program status indicates the operating status of an auto write to the CPU. It is set to "1" when a write error occurs. The program status is reset to "0" when cleared. When an erase command is in error, which occurs if the command entered after the block erase command (20 16) is not the confirmation command (D0 16), both the program status and erase status (SR5) are set to "1". If the program status or erase status = "1", the following commands entered by command write are not accepted and SR4 and SR5 are set to "1" (command sequence error): (1) A valid command is not entered correctly (2) The data entered in the second bus cycle of lock bit program (77 16/D016), block erase (2016/D016), or erase all unlocked blocks (A7 16/D016) is not the D0 16 or FF16. However, if FF 16 is entered, read array is assumed and the command that has been set up in the first bus cycle is canceled. Block status after program (SR3) If data is overwritten (this occurs when a memory cell becomes overcharged and data incorrectly read), "1" is set for the program status after the program at the end of the page write operation. In other words:

• When writing ends successfully, "80 16" is output;
• When writing fails, "9016" is output;
• When excessive data is written, "8816" is output. Full-Status Check A full-status check allows the user to review the erase and program operations. Figure 1.156 shows a full-status check flowchart and the action to take when an error occurs. Read status register SR4=1 and SR5=1 ? NO Command sequence error YES SR5=0? YES Block erase errorNO SR4=0? YES Program error (page or lock bit) NO End (block erase, program) Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. If a block erase error occurs, the block in error cannot be used. Execute the read lock bit status command (7116) to see if the block is locked. After removing the lock, execute a write operation the same way. If the error still occurs, the page in error cannot be used. Note: When one of SR5 to SR3 is set to 1, none of the page program, block erase, erase all YES SR3=0? Program error (block) NO After erasing the block in error, exectue the operation again. If the same error still occurs, the block in error cannot be used. unlocked blocks and lock bit program commands are accepted. Execute the clear status register command (5016) before executing these commands. Figure 1.156. Full-status check flowchart

M30245 Group CPU Rewrite Mode Rev.2.00 Oct 16, 2006 page 205 of 264 REJ03B0005-0200 Precautions Operation speed During CPU rewrite mode, set the main clock frequency to 6.25MHz or less using the main clock division select bits (bit 6 at address 0006 16, and bits 6 and 7 at address 0007 16). Prohibited Instructions The UND, INTO, JMPS, JSRS, and BRK instructions cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory. Prohibited Interrupts The address match interrupt cannot be used during CPU rewrite mode because it refers to the internal data of the flash memory. If the interrupt's vector is in the variable vector table, it can be used by transferring the vector into the RAM area. The NMI and watchdog timer interrupts can be used to change the CPU rewrite mode select bit forcibly to normal mode (FMR01="0") when the interrupt occurs. If the rewrite operation is stopped when the NMI or watchdog timer interrupts occurs, the CPU rewrite mode select bit should be set to "1" and the erase/program operation should be repeated. Reset Reset input is always accepted. Access To set the CPU rewrite mode select bit, and the lock bit disable bit to "1", the user must write a "0" and then a "1". This sequence must be followed to set this bit to "1". This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Write to the CPU rewrite mode select bit when NMI pin is a "H" level. Access disable Write the CPU rewrite mode select bit, and the user ROM area select bit in an area other than the internal flash memory. Writing in the user ROM area If power is lost while rewriting blocks that contain the flash rewrite program with the CPU rewrite mode, the blocks may not be correctly rewritten. Afterwards, it is possible that the flash memory can not be rewritten. Therefore, use the standard serial I/O mode or parallel I/O mode to rewrite these blocks. Using the lock bit In CPU rewrite mode, use a program that can set and clear the lock bit disable bit (FMR02).

M30245 Group Parallel I/O Mode Rev.2.00 Oct 16, 2006 page 206 of 264 REJ03B0005-0200 Parallel I/O Mode The parallel I/O mode can be used to input and output the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. In this mode, the M30245 (flash memory version) operates in a manner similar to other flash memory from Renesas. Because there are some differences with some functions not available with the microcomputer and the memory capacity, the M30245 cannot be programmed by a programmer for other Renesas flash memory. Use an exclusive programmer that supports the M30245 (flash memory version). Refer to the instruction manual of each programmer manufacturer for usage details. User ROM and Boot ROM Areas In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 1.149 can be rewritten. Both areas of flash memory can be operated on in the same way. Program and block erase operations can be performed in the user ROM area. The user ROM area and it's blocks are shown in Figure 1.149. The boot ROM area is 8 Kbytes in size. In parallel I/O mode, it is located at addresses 0FE000 16 through 0FFFFF 16. Ensure that the program and block erase operations are always performed within this address range. Access to any location outside this address range is prohibited. In the boot ROM area, an erase block operation is applied to only one 8 Kbyte block. The boot ROM area has a standard serial I/O mode control program installed at the Renesas factory, therefore, it is unnecessary to write to the boot ROM area when using standard serial I/O mode.

M30245 Group Parallel I/O Mode Rev.2.00 Oct 16, 2006 page 207 of 264 REJ03B0005-0200 ROM code protect function To prevent the contents of the flash memory from being read out or rewritten too easily, the device incorporates a ROM code protect function for use in parallel I/O mode. The ROM code protect function prevents reading out or modifying the contents of the flash memory by using the ROM code protect control register (0FFFFF 16) during parallel I/O mode. Figure 1.157 shows the ROM code protect control address. (This address exists in the user ROM area.) If one pair of ROM code protect bits is set to "0", ROM code protect is turned on so that the contents of the flash memory are protected against being read out or modified. The ROM code protect function is implemented in two levels. If level 2 is selected, the flash memory is protected even against readout by a shipment inspection LSI tester, etc. If both level 1 and level 2 are selected, level 2 is selected by default. If both of the two ROM code protect reset bits are set to "00," the ROM code protect function is turned off so that the contents of the flash memory can be read out or modified. Once ROM code protect is turned on, the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/O mode or another mode to rewrite the contents of the ROM code protect reset bits. Bit Symbol Bit Name Function Reserved ROMCP2 ROMCR ROMCP1 ROM code protect level 2 set bit (Note 1, 2) ROM code protect reset bit (Note 3) ROM code protect level 1 set bit (Note 1) Always set to "1" b3 b2 0 0 : Protect enable 0 1 : Protect enable 1 0 : Protect enable 1 1 : Protect enable b5 b4 0 0 : No protect set bit 0 1 : Protect set bit active 1 0 : Protect set bit active 1 1 : Protect set bit active b7 b6 0 0 : Protect enable 0 1 : Protect enable 1 0 : Protect enable 1 1 : Protect enable Symbol ROMCP Address 0FFFFF ROM code protect control register b7 b5b6 b4 b3 b2 b1 b0 Note 1: When ROM code protect is turned on, the on-chip flash memory is protected against readout or modification in parallel input/output mode. Note 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection LSI tester, etc, is inhibited. Note 3: The ROM code protect reset bits can be used to turn off ROM code protect levels 1 and 2. However, because these bits cannot be changed in parallel input/output mode, they need to be rewritten in serial input/output or some other mode. When reset FF16 Figure 1.157. ROM code protect control register

M30245 Group Serial I/O Mode Rev.2.00 Oct 16, 2006 page 208 of 264 REJ03B0005-0200 Standard Serial I/O Mode The standard serial I/O mode serially inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. It uses a specific serial programmer to accomplish this. It is different from the parallel I/O mode because the CPU controls operations like rewriting the flash memory (using the CPU rewrite mode) and serially inputting data. The standard serial I/O mode is entered by clearing the reset with the P50 (CE) pin set to a "H" level, the P55 (EPM) pin set to a "L" level and the CNVss pin set to a "H" level. (For normal microprocessor mode, set the CNVss pin to "L" level.) A control program is written in the boot ROM area when the product is shipped from Renesas. The standard serial I/O mode cannot be used if the boot ROM area is rewritten in the parallel I/O mode. Figure 1.158 shows the pin connections for the standard serial I/O mode. Table 1.70 lists the pin functions for standard serial IO mode. There are two standard serial I/O modes that both require a purpose-specific serial programmer: clock synchronous and clock asynchronous. Standard serial I/O switches between mode 1 (clock synchronous) and mode 2 (clock asynchronous) according to the level of the CLK1 pin when the reset is released. Serial data I/O uses UART1 and transfers the data serially in 8-bit units. To use standard serial I/O mode 1 (clock synchronous):

• Set the CLK1 pin to "H" level and release the reset
• This mode uses the four UART1 pins CLK1, RxD1, TxD1 and RTS1 (BUSY).
• The CLK1 pin is the transfer clock input pin through which an external transfer clock is input.
• The TxD1 pin is for CMOS output.
• The RTS1 (BUSY) pin outputs an "L" level when ready for reception and an "H" level when reception starts. To use standard serial I/O mode 2 (clock asynchronous):
• Set the CLK1 pin to "L" level and release the reset.
• This mode uses the two UART1 pins RxD1 and TxD1. In standard serial I/O mode, only the user ROM area indicated in Figure 1.149 can be rewritten. The boot ROM cannot. The standard serial I/O mode uses a 7-byte ID code. When there is data in the flash memory, commands sent from the programmer are not accepted unless the ID codes are identical. ID Code Check Function The ID code check function can be used in serial I/O mode to protect the contents of the flash memory from being read out or rewritten. If the contents of the flash memory are not blank, the ID code sent from the serial programmer is compared with the ID code written in the flash. If the ID codes are not identical, the commands sent from the serial programmer are not accepted. Figure 1.159 shows the ID code store addresses. The ID code consists of 8-bit data: (beginning with the first byte) 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. Write a program that has the ID code preset at these addresses.

M30245 Group Serial I/O Mode Rev.2.00 Oct 16, 2006 page 210 of 264 REJ03B0005-0200 Table 1.70. Flash memory standard serial I/O mode pin functions Pin Name IO Description Vcc, Vss Power input Apply program/erase voltage to Vcc pin and 0V to Vss pin CNVss CNVss I Connect to Vcc pin. RESET Reset input I Reset input pin. While reset is "L" level, a 20 cycle or longer clock must be input to XIN pin. XIN Clock input I Connect a ceramic re sonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin. XOUT Clock output O BYTE BYTE I Connect this pin to Vcc or Vss. AVcc, AVss Analog power supply input I Connect AVss to Vss and AVcc to Vcc respectively. VREF Reference voltage input I Enter the reference voltage for A/D converter from this pin. P00 to P07 Input Port P0 I Input "H" or "L" level signal or open. P10 to P17 Input Port P1 I Input "H" or "L" level signal or open. P20 to P27 Input Port P2 I Input "H" or "L" level signal or open. P30 to P37 Input Port P3 I Input "H" or "L" level signal or open. P40 to P47 Input Port P4 I Input "H" or "L" level signal or open. P51 to P54, P56, P57 Input Port P5 I Input "H" or "L" level signal or open. P50 CE input I Input "H" level signal. P55 EPM input I Input "L" level signal. P60 to P63 Input Port P6 I Input "H" or "L" level signal or open. P64 BUSY output O Standard serial mode 1: BUSY signal output pin Standard serial mode 2: Monitors the program operation check. P65 SCLK input I Standard serial mode 1: Serial clock input pin Standard serial mode 2: Input "L" level signal P66 RxD input I Serial data input pin P67 TxD output O Serial data output pin P70 to P77 Input Port P7 I Input "H" or "L" level signal or open. P80 to P84, P86, P87 Input Port P8 I Input "H" or "L" level signal or open. P85 NMI input I Connect this pin to Vcc P90, P92 Input Port P9 I Input "H" or "L" level signal or open. P100 to P107 Input Port P10 I Input "H" or "L" level signal or open. , P93

M30245 Group Serial I/O Mode 1 Rev.2.00 Oct 16, 2006 page 212 of 264 REJ03B0005-0200 Software Commands In the standard serial I/O mode 1, erase , program and read operations are controlled by transferring software com- mands using the RxD1 pin. Data and status registers in memory can be read after inputting software commands. Reading the status register can check the status of the flash memory operating state or successful completion of a program or erase operation. Table 1.71 lists the software commands. Table 1.71. Software commands Note 1: The shaded areas indicate a transfer from flash memory MCU to peripheral unit. All other data is transferred from the peripheral unit to the flash memory MCU. Note 2: SRD refers to Status Register Data. SRD1 refers to Status Register Data 1. Note 3: All commands are accepted if the flash memory is blank. Control command 2nd byte 3rd byte 4th byte 5th byte 6th byte When ID is not verified

1 Page read FF 16 Address

(middle) Address (high) Data output Data output Data output Data output to 259th byte Not acceptable

2 Page program 41 16 Address

(middle) Address (high) Data input Data input Data input Data input to 259th byte Not acceptable

3 Block erase 20 16 Address

(middle) Address (high) D016 Not acceptable

4 Erase all

16 D016 Not

5 Read status

7016 SRD

6 Clear status

5016 Not

7 Read lock bit

16 Address

(middle) Address (high) Lock bit data output Not acceptable

8 Lock bit

(middle) Address (high) D016 Not acceptable

9 Lock bit enable 7A 16 Not

10 Lock bit disable 75 16 Not

11 ID check

(low) Address (middle) Address (high) ID size ID1 To ID7 Acceptable

12 Download

(low) Size (high) Check sum Data input As required Not acceptable Version data output function FB16 Version data output Version data output Version data output Version data out- put Version data output Version data output to 9th byte Acceptable

14 Boot ROM area

(middle) Address (high) Data output Data output Data output Data output to 259th byte Not acceptable Read check data FD16 Check data (low) Check data (high) Not acceptable

M30245 Group Serial I/O Mode 1 Rev.2.00 Oct 16, 2006 page 220 of 264 REJ03B0005-0200 Data Protection (Block Lock) Each block in Figure 1.176 has a nonvolatile lock bit that indicates protection (block lock) against erasing/writing. A block is locked (writing "0" for the lock bit) with the lock bit program command. Any lock bit can be read with the read lock bit status command. Block lock disable/enable is determined by the status of the lock bit and execution status of the lock bit disable and lock bit enable commands. (1) After reset and the lock bit enable command is executed, the specified block can be locked/unlocked using the lock bit (lock bit data). Blocks with a "0" lock bit data are locked and cannot be erased or written to. Blocks with a "1" lock bit data are unlocked and can be erased or written to. (2) After the lock bit disable command has been executed, all blocks are unlocked regardless of the lock bit data status and can be erased or written to. In this case, any lock bit data that was "0" before the block was erased is set to "1" (unlocked) after erasing. Figure 1.176. Block diagram of the flash memory version User ROM area Boot ROM area Note 1: The boot ROM area can be rewritten only in parallel input/ output mode. (Access to any other areas is inhibited.) Note 2: To specify a block, use the maximum address in the block that is an even address. 8K bytesFE00016 FFFFF16 F000016 Block 3 : 32K bytes F800016 Block 2 : 8K bytes F A00016 Block 1 : 8K bytes Block 0 : 16K bytes FC00016 FFFFF16 E000016 Block 4 : 64K bytes Status Register (SRD) The status register indicates the flash memory operating status and whether an erase or program operation has terminated normally or in error. It can be read by using the read status register command (7016). Writing the clear status register command (50 16) clears the status register. Table 1.72 defines each status register bit. After reset, the status register outputs "80 16". Table 1.72. Status register (SRD) Each SRD bit Status name Definition "1" "0" SR7 (Bit 7) Write state machine (WSM) Ready Busy SR6 (Bit 6) Reserved _ _ SR5 (Bit 5) Erase status Terminated in error Terminated normally SR4 (Bit 4) Program status Terminated in error Terminated normally SR4 (Bit 3) Block status after program Terminated in error Terminated normally SR2 (Bit 2) Reserved _ _ SR1 (Bit 1) Reserved _ _ SR0 (Bit 0) Reserved _ _

M30245 Group Serial I/O Mode 1 Rev.2.00 Oct 16, 2006 page 221 of 264 REJ03B0005-0200 Write State Machine (WSM) Status (SR7) The write state machine (WSM) status indicates the operating status of the flash memory. When power is turned on, "1" (ready) is set. The bit is set to "0" (busy) during an auto-write or auto-erase operation, but returns to "1" when the operation ends. Erase Status (SR5) The erase status reports the operating status of the auto-erase operation. If an erase error occurs, it is set to "1". When the erase status is cleared, it is set to "0". Program Status (SR4) The program status reports the operating status of the auto-write operation. If a write error occurs, it is set to "1". When the program status is cleared, it is set to "0". Block Status After Program (SR3) If data is overwritten (this occurs when a memory cell becomes overcharged and data is incorrectly read), a "1" is set for the block status after program at the end of the page write operation. In other words:

• When writing ends successfully "80 16" is output
• When writing fails, "9016" is output
• When excessive data is written, "8816" is output. If "1" is written to any SR5, SR4 or SR3 bits, the page program, block erase, erase all unlocked blocks and lock bit program commands are not accepted. Before executing these commands, execute the clear status register com- mand (50 16). Status Register 1 (SRD1) Status register 1 indicates the status of serial communications, ID check results, and check sum comparisons. It can be read after the SRD by writing the read status register command (70 16). Status register 1 can be cleared by writing the clear status register command (50 16). Table 1.73 defines each status register 1 bit. "00 16" is output when power is turned ON and the flag status is maintained even after the reset. Table 1.73. Status register 1 (SRD1) SRD1 bits Status name Definition "1" "0" SR15 (Bit 7) Boot update complete bit Completed Not updated SR14 (Bit 6) Reserved _ _ SR13 (Bit 5) Reserved _ _ SR12 (Bit 4) Checksum match bit Match No match SR11 (Bit 3) SR10 (Bit 2) ID check completed bits 0 0 Not verified 0 1 Verified no match 1 0 Reserved 1 1 Verified SR9 (Bit 1) Data receive time out Time out Normal operation SR8 (Bit 0) Reserved _ _

M30245 Group Serial I/O Mode 1 Rev.2.00 Oct 16, 2006 page 222 of 264 REJ03B0005-0200 Boot Update Completed Bit (SR15) This flag indicates if the control program was properly downloaded (using the download function) to RAM. Check Sum Consistency Bit (SR12) This flag indicates if the check sum matches after a program is downloaded for execution (using the download function). ID Check Completed Bits (SR11 and SR10) These flags indicate the result of ID checks. Some commands cannot be accepted without an ID check. Data Reception Time Out (SR9) This flag indicates when a time out error is generated during data reception. If this flag is set during data reception, the received data is discarded and the microcomputer returns to the command wait state. Full Status Check A full-status check allows the user to review the erase and program operations. Figure 1.177 shows a full-status check flowchart and the action to take when an error occurs. Read status register SR4=1 and SR5=1 ? NO Command sequence error YES SR5=0? YES Block erase errorNO SR4=0? YES Program error (page or lock bit) NO End (block erase, program) Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. If a block erase error occurs, the block in error cannot be used. Execute the read lock bit status command (7116) to see if the block is locked. After removing the lock, execute a write operation the same way. If the error still occurs, the page in error cannot be used. Note: When one of SR5 to SR3 is set to 1, none of the page program, block erase, erase all YES SR3=0? Program error (block) NO After erasing the block in error, exectue the operation again. If the same error still occurs, the block in error cannot be used. unlocked blocks and lock bit program commands are accepted. Execute the clear status register command (5016) before executing these commands. Figure 1.177. Full status check flowchart

M30245 Group Serial I/O Mode 2 Rev.2.00 Oct 16, 2006 page 223 of 264 REJ03B0005-0200 Standard serial I/O mode 2 In standard serial I/O mode 2 (clock asynchronous), software commands, addresses and data are input and output between the MCU and peripheral units (serial programmer, etc.) using 2-wire clock-asynchronous serial I/O (UART1). Standard serial I/O mode is entered by releasing the reset with the P6 5 (CLK1) pin at a "L" level. The TxD1 pin is set to CMOS output. Data transfer is in 8-bit units with LSB first, 1 stop bit and parity OFF. After reset, connections can be established at 9,600 bps when initial communications are made with a peripheral unit. This requires a main clock with a minimum 2 MHz input oscillation frequency. The baud rate can also be changed from 9,600 bps to 19,200, 38,400, or 57,600 bps by executing software commands. Communication errors may occur because of the main clock oscillation frequency. If errors occur, change the main clock's oscillation frequency and the baud rate. After executing commands from a peripheral unit that require time to erase and write data, as with the erase and program commands, allow a sufficient time interval or execute the read status command and check how the process- ing ended before executing the next command. Data and status registers can be read after transmitting software commands. Reading the status register can check status of the flash memory operating state or successful completion of a program or erase operation. Initial communications with peripheral units After reset, the bit rate generator is adjusted to 9,600 bps to match the main clock’s oscillation frequency, by sending the code as prescribed by the protocol for initial communications with peripheral units. Figure 1.178 shows the initial communication with peripheral units. (1) Transmit "00 16" from a peripheral unit 16 times. (The MCU with internal flash memory sets the bit rate generator so that "0016" can be successfully received.) (2) The MCU with internal flash memory outputs the “B0 16” check code and initial communications end successfully. Initial communications must be transmitted at a speed of 9,600 bps and a transfer interval of a minimum 15 ms. Also, the baud rate at the end of initial communications is 9,600 bps. MCU with internal flash memory Peripheral unit (1) Transfer "0016" 16 times At least 15ms transfer interval 1st 2nd 15th 16th (2) Transfer check code "B016" "0016" "0016" "0016" "B016" "0016" Reset The bit rate generator setting completes (9600bps) Note. If the peripheral unit cannot receive "B0 16" successfully, change the oscillation frequency of the main clock. Figure 1.178. Peripheral unit and initial communication

M30245 Group Serial I/O Mode 2 Rev.2.00 Oct 16, 2006 page 224 of 264 REJ03B0005-0200 Frequency identification When "00 16" data is received 16 times from a peripheral unit at a baud rate of 9,600 bps, the value of the bit rate generator is set to match the operating frequency (2 - 16 MHz). The highest speed is taken from the first 8 transmissions and the lowest from the last 8. These values are then used to calculate the bit rate generator value for a baud rate of 9,600 bps. Baud rate cannot be attained with some operating frequencies. Table 1.74 lists the operation frequency and the baud rate. Table 1.74. Operation frequency and baud rate + : Communications possible _ : Communications not possible Operation Frequency Baud rate 9,600 Baud rate 19,200 Baud rate 38,400 Baud rate 57,600

16 MHz

12 MHz

11 MHz

10 MHz

8 MHz

7.3728 MHz

6 MHz

5 MHz

4.5 MHz

4.194304 MHz

4 MHz

3.58 MHz

3 MHz

2 MHz

Example Circuit Application Figure 1.179 shows a circuit application for the standard serial I/O mode 2. Figure 1.179. Example circuit application for the standard serial I/O mode 2 Monitor output Data input Data output Note: In this example, the microprocessor mode and standard serial I/O mode are switched via a switch. RTS1(BUSY) CLK1 RXD1 TXD1 CNVss P50(CE) P55(EPM) NMI M30245 Flash memory version

M30245 Group Serial I/O Mode 2 Rev.2.00 Oct 16, 2006 page 225 of 264 REJ03B0005-0200 Software Commands In the standard serial I/O mode 2, erase, program, and read operations are controlled by transferring software com- mands using the RxD1 pin. Standard serial I/O mode 2 adds four transmission speed commands - 9,600, 19,200, 38,400, and 57,600 bps - to the software commands of standard serial I/O mode 1. Table 1.75 lists the software commands for serial I/O mode 2. Table 1.75. Software commands Note 1: The shaded areas indicate a transfer from flash memory MCU to peripheral unit. All other data is transferred from the peripheral unit to the flash memory MCU. Note 2: SRD refers to Status Register Data. SRD1 refers to Status Register Data 1. Note 3: All commands are accepted if the flash memory is blank. Control command 2nd byte 3rd byte 4th byte 5th byte 6th byte When ID is not verified (middle) Address (high) Data output Data output Data output Data output to 259th byte Not acceptable (middle) Address (high) Data input Data input Data input Data input to 259th byte Not acceptable (middle) Address (high) D016 Not acceptable

4 Erase all unlocked

16 SRD

16 Not

(middle) Address (high) Lock bit data output Not acceptable (middle) Address (high) D016 Not acceptable (low) Address (middle) Address (high) ID size ID1 To ID7 Acceptable (low) Size (high) Check sum Data input As required Not acceptable Version data output function FB

16 Version

14 Boot ROM area out-

(middle) Address (high) Data output Data output Data output Data output to 259th byte Not acceptable Read check data FD 16 Check data (low) Check data (high) Not acceptable

16 Baud rate 9600 B0 16 B016 Acceptable

17 Baud rate 19200 B1 16 B116 Acceptable

18 Baud rate 38400 B2 16 B216 Acceptable

19 Baud rate 57600 B3 16 B316 Acceptable

M30245 Group Serial I/O Mode 2 Rev.2.00 Oct 16, 2006 page 233 of 264 REJ03B0005-0200 18. Baud Rate 38400 This command changes the baud rate to 38,400 bps. Figure 1.197 shows the baud rate 38400 command timing. To execute the baud rate 38400 bps command: (1) Transfer the "B2 16" command code with the 1st byte. (2) After the "B216" check code is output with the 2nd byte, change the baud rate to 38,400 bps. Figure 1.197. Timing of baud rate 38400 RxD1 TxD1 (M30245 reception data) (M30245 transmit data) B216 B216 19. Baud Rate 57600 This command changes the baud rate to 57,600 bps. Figure 1.198 shows the baud rate 57600 command timing. To execute the baud rate 57600 bps command: (1) Transfer the "B3 16" command code with the 1st byte. (2) After the "B316"check code is output with the 2nd byte, change the baud rate to 57,600 bps. F.igure 1.198. Timing of baud rate 57600 RxD1 TxD1 (M30245 reception data) (M30245 transmit data) B316 B316

M30245 Group Ele ctrical Characteristics Rev.2.00 Oct 16, 2006 page 234 of 264 REJ03B0005-0200 Electrical Specifications Absolute Maximum Ratings Table 1.76. Absolute maximum ratings Symbol Parameter Condition Rated value Unit Vcc Supply voltage Vcc = AVcc = UVcc -0.3 to 4.0 V AVcc Analog supply voltage -0.3 to 4.0 V VI Input voltage RESET, CNVss, BYTE, P00 to P07, P 10 to P17, P20 to P27, P 30 to P37, P 40 to P47, P 50 to P57, P 60 to P67, P72 , P 80 to P87 P93, P100 to P107, VREF, XIN, D+, D- -0.3 to Vcc + 0.3 V P70 to P71 -0.3 to 4.0 V VO Output voltage P0 0 to P07, P 10 to P17, P 20 to P27, P 30 to P37, P 40 to P47, P50 to P57, P 60 to P67, P 72 to P77, P 80 to P84, P 86, P 87, P93, P100 to -0.3 to Vcc + 0.3 V P70 to P71 -0.3 to 4.0 V Pd Power dissipation 300 mW Topr Operating ambient temperature -20 to 85 Tstg Storage temperature -65 to 150 °C P90, P 92 , to P77 P90, P 92, P107, XOUT, D+, D- VbusDTCT -0.3 to 5.50 V Vcc = AVcc = UVcc UVcc USB circuit supply voltage Vcc = AVcc = UVcc -0.3 to 4.0 V Topr = 25°C

M30245 Group Ele ctrical Characteristics Rev.2.00 Oct 16, 2006 page 235 of 264 REJ03B0005-0200 Recommended operating conditions Table 1.77. Recommended operating conditions (Note 1) Note 1: Vcc = 3.0V to 3.6V at Topr = -20 to 85°C unless otherwise stated. Note 2: The mean output current is the mean values within 100ms. Note 3: The total IOL (peak) and I OH (peak) for Ports P0, P1, P2, P8 6, P87, P9 and P10 must be 80mA max. The total IOL (peak) for Ports P3, P4, P5, P6, P7 and P8 0 to P84 must be 80mA max. The total I OH (peak) for ports P3, P4, P5, P6, P72 toP7 7 and P8 0 to P84 must be 80mA max. Note 4: When using the USB function, set f(X IN) to 4MHz or higher. Symbol Parameter Standard Unit Min. Typ. Max. Vcc Supply voltage 3.0 3.3 3.6 V AVcc Analog supply voltage Vcc V Vss Supply voltage 0 V AVss Analog supply voltage 0 V VIH HIGH input voltage 0 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P87, P90, P92, P93, P100 to P107, XIN, RESET, CNVss, BYTE

0.8 Vcc Vcc V

P70 to P71 4.0 V VIL LOW input voltage IOH (peak) HIGH peak output current P00 to P07, P10 to P17, P20 to P2 7, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86, P87, P90, P92, P93, P100 to P107 -10.0 mA IOH (avg) HI GH aver- age output current -5.0 mA I OL (peak) LOW peak output current 10.0 mA I OL (avg) L OW aver- age output current 5.0 mA f(XIN) Main clock input oscillation frequency 16 f(XCIN) Sub clock oscillation frequency 32.768 50 kHz V V

0.2 Vcc

P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P87, P90, P92, P93, P100 to P107, XIN, RESET, CNVss, BYTE VbusDTCT 5.25 V

0.8 Vcc

UVcc USB supply voltage 3.0 3.3 3.6 V P70 to P71 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86, P87, P90, P92, P93, P100 to P107 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86, P87, P90, P92, P93, P100 to P107 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86, P87, P90, P92, P93, P100 to P107 V0.8D+, D- V2.0D+, D- 4.0 VbusDTCT 1.0 V (Note 4)

M30245 Group Ele ctrical Characteristics Rev.2.00 Oct 16, 2006 page 236 of 264 REJ03B0005-0200

Electrical characteristics

Table 1.78. Electrical characteristics (Note 1) P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90, P92, P93, P100 to P107, XIN, RESET, CNVSS, BYTE Note 1 : Vcc = 3.0V to 3.6V, Vss = 0V at Topr = -20°C to 85°C, f(XIN) = 16MHz unless otherwise stated. Note 2 : With one timer operated using fc32. Symbol Parameter Measuring condition Standard Unit Min. Typ. Max. VOH HIGH output voltage 0 to P07, P 10 to P17, P 20 to P27, P 30 to P37, P40 to P47, P 50 to P57, P 60 to P62, P 64 to P66, P70 to P77, P 80 to P84, P 86, P 87, P90, P 92, P 93, P100 to P107 IOH = -1mA 2.5 V VOL LOW output voltage I OL = 1mA 0.5 V VT + - VT - Hysteresis HOLD, RDY, TA0 IN to TA4IN, INT0 to INT2, ADTRG, CTS0 to CTS3, CLK0, CLK1, TA2OUT to TA4OUT, NMI, KI0 to KI7, RXD0 to RXD3, SCL, SDA 0.2 1.0 V VbusDTCT 1.0 V IIH HIGH input current VI = VCC IIL LOW input current V I = 0V RPULLUP Pull-up resistance VI = 0V 30.0 50.0 167.0 k RfXIN Feedback resistance XIN 1.0 M RfXCIN XCIN 10 M VRAM RAM retention voltage When clock is stopped V Icc Power supply current In single-chip mode, the output pins are open and other pins are Vss f(X IN) = 16MHz Square wave, no division, USB off mA Topr = 45°C, when clock is stopped, USB suspend mode 2.0 V V XOUT XCOUT HIGHPOWER HIGHPOWER LOWPOWER LOWPOWER V V XOUT XCOUT HIGHPOWER HIGHPOWER LOWPOWER LOWPOWER IOH = -0.1mA IOH = 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 IOL = P63, P 67 IOH = -10mA 2.0 V P63, P 67, P 70 to P77 (P7 high drive mode) IOL = 10mA 0.8 V IOL = 0.1mA P00 to P07, P 10 to P17, P 20 to P27, P 30 to P37, P40 to P47, P 50 to P57, P 60 to P62, P 64 to P66, P70 to P77, P 80 to P84, P 86, P 87, P90, P 92, P 93, P100 to P107 0.2 1.8 V P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90, P92, P93, P100 to P107, XIN, RESET, CNVSS, BYTE, VbusDTCT P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P84, P86, P87, P90, P92, P93, P100 to P107 mA25 43f(XIN) = 16MHz Square wave, no division, USB on f(XCIN) = 32kHz Square wave f(XCIN) = 32kHz When a WAIT instruction is executed. (Note 2) VbusDTCT 50 RESET 420 Topr = 25°C, when clock is stopped, USB suspend mode Topr = 45°C, when clock is stopped, USB suspend mode 190 Topr = 25°C, when clock is stopped, USB suspend mode 95 235Flash memory version Mask ROM version

M30245 Group Ele ctrical Characteristics Rev.2.00 Oct 16, 2006 page 237 of 264 REJ03B0005-0200 Table 1.79. USB electrical characteristics (Note 1) Note1 : Vcc = 3.0V to 3.6V, Vss = 0V, Topr = -20°C to 85°C unless otherwise specified. Symbol Parameter Measuring Condition Standard Unit Min Typ Max VOH D+, D- 2.2 V VOL D+, D- 0.8 V Isusp Suspend current USB suspend mode, internal clock stopped, with / without Vbus Detect 3.6 Flash memory version Mask ROM version Topr=25°C Topr=45°C Topr=25°C Topr=45°C 235 420 190 I Rx = 33Ω /I = +/- 18.3mA, UV CC = 3.00V,OH OL I Rx = 33Ω /I = +/- 18.3mA, UV CC = 3.00V,OH OL Table 1.80. A/D conversion characteristics (Note 1) Symbol Parameter Measuring condition Standard Unit Min Typ Max - Resolution V REF = VCC 10 Bits - Absolute accuracy Sample and hold function not used (10 bit) +4 Sample and hold function used (10 bit) +4 Sample and hold function not used (8 bit) +2 Sample and hold function used (8 bit) +2 RLADDER Ladder resistance tCONV Conversion time (10 bit) tCONV Conversion time (8 bit) tSAMP Sampling time 0.3 VREF Reference voltage Vcc V VIA Analog input voltage 0 Vcc V 3.3 2.8 VREF = VCC VREF = VCC VREF = VCC VREF = VCC VREF = VCC VREF = VCC VREF = VCC LSB LSB LSB LSB Note 1 : VCC, AVCC, VREF = 3.3V, VSS, AVSS = 0V, Topr = 25°C, f(XIN) = 16MHz. Note 2 : Divide the frequency if f(XIN) exceeds 10MHz, and make ΦAD equal to or less than 10MHz. Table 1.81. Flash memory version electrical characteristics (Note 1) Note 1: Vcc = 3.0V to 3.6V, Vss = 0V, Topr = 0°C to 60°C Note 2: N denotes the number of block erases. Symbol Parameter Measuring condition Standard Unit Min Typ Max - Page Program Time ms - Block erase time ms - Erase all unlocked blocks time ms - Lock bit program time ms 1206 1206 600 50xN 60xN (Note 2) (Note 2)

M30245 Group Ele ctrical Characteristics Rev.2.00 Oct 16, 2006 page 238 of 264 REJ03B0005-0200 Timing requirements (Vcc = 3.3V, Vss=0V, Topr =-20 C to 85 C unless otherwise stated) Table 1.82. External clock input Symbol Parameter Standard Unit Min Max tc External clock input cycle time ns tw(H) External clock input HIGH pulse width ns tw(L) External clock input LOW pulse width ns tr External clock rise time ns tf External clock fall time ns 62.5 29.5 29.5 Table 1.83. Memory expansion and microprocessor modes S ym bol P arame ter Standard Unit Min Max tac1 (RD-DB) Data input access time (no wait) ns tac2 (RD-DB) Data input access time (with wait) ns tsu (DB-RD) Data input setup time ns tsu (RDY-BCLK) RDY input setup time ns tsu (HOLD-BCLK) HOLD input setup time ns th (RD-DB) Data input hold time ns th (BCLK-RDY) RDY input hold time ns th (BCLK-HOLD) HOLD input hold time ns 105 (Note 1) (Note 2) Note 1: tac1 = tcyc / 2 - 60nS Note 2: tac2 = (m+0.5) x tcyc - 60nS m = number of wait states (1 to 3) Table 1.84. Timer A input (counter input in event counter mode) Symbol Parameter Standard Unit Min Max tc(TA)A i IN input cycle time 100 ns tw(TAH)T A i IN input HIGH pulse width 50 ns tw(TAL)T A i IN input LOW pulse width 40 ns Table 1.85. Timer A input (gating input in timer mode) Symbol Parameter Standard Unit Min Max tc(TA)A i IN input cycle time Note ns tw(TAH)T A i IN input HIGH pulse width Note ns tw(TAL)T A i IN input LOW pulse width Note ns Note: When using the external gating mode feature, the width of TAi IN needs to be greater than the period of the clock source selected.

M30245 Group Ele ctrical Characteristics Rev.2.00 Oct 16, 2006 page 239 of 264 REJ03B0005-0200 Timing requirements (Vcc = 3.3V, Vss=0V, Topr =-20 C to 85 C unless otherwise stated) Table 1.86. Timer A input (external trigger input in one-shot timer mode) Symbol Parameter Standard Unit Min Max tc(TA)A i IN input cycle time 200 ns tw(TAH)T A i IN input HIGH pulse width 100 ns tw(TAL)T A i IN input LOW pulse width 100 ns Table 1.87. Timer A input (external trigger input in pulse width modulation mode) Symbol Parameter Standard Unit Min Max tw(TAH)T A i IN input HIGH pulse width 100 ns tw(TAL)T A i IN input LOW pulse width 100 ns Table 1.88. Timer input (up/down input in event counter mode) Symbol Parameter Standard Unit Min Max tc(UP)A i OUT input cycle time 2000 ns tw(UPH)T A i OUT input HIGH pulse width 1000 ns tw(UPL)T A i OUT input LOW pulse width 1000 ns tsu(UP-TIN)T A i OUT input setup time 400 ns th(TIN-UP)T A i OUT input hold time 400 ns Table 1.89. A/D trigger input Symbol Parameter Standard Unit Min Max tc(AD) ADTRG input cycle time(triggerable minimum) 1000 ns tw(ADL) ADTRG input LOW pulse width 125 ns Table 1.90. External interrupt INTi inputs Symbol Parameter Standard Unit Min Max tw(INH)I N T I input HIGH pulse width 250 ns tw(INL)I N T I input LOW pulse width 250 ns

M30245 Group Ele ctrical Characteristics Rev.2.00 Oct 16, 2006 page 240 of 264 REJ03B0005-0200 Timing requirements (Vcc = 3.3V, Vss=0V, Topr =-20 C to 85 C unless otherwise stated) Table 1.91. Serial I/O timing Symbol Parameter Standard Unit Min Max tc(CK) CLKi input cycle time 160 ns tw(CKH) CLKi input HIGH pulse width 60 ns tw(CKL) CLKi input LOW pulse width 60 ns tsu(D-C) RxDi input setup time 60 ns th(C-D) RxDi input hold time 20 ns Table 1.92. Vbus Detect interrupt Symbol Parameter Standard Unit Min Max tw(INT) VbusDTCT Interrupt pulse width 50 µS Table 1.93. Serial Sound Interface (SSI) Symbol Parameter Standard Unit Min Max tc(SCK) SCKi input cycle time 62.5 ns tw(SCKH) SCKi input HIGH pulse width 29.5 ns tw(SCKL) SCKi input LOW pulse width 29.5 ns tsu(SRxD-SCK) SRxDi input setup time 10 ns th(SCK-SRxD) SRxDi input hold time 10 ns t1(SCK-WS) SCKP=0 10 ns t2(WS-SCK) SCKP=0 10 ns 10 nsSCKi falling edge to WS edge SCKi rising edge to WS edge SCKP=1 SCKP=1 WS edge to SCKi rising edge WS edge to SCKi falling edge 10 Table 1.94. AND Flash Control timing th2(SC-D) Symbol Parameter Standard UnitMin Max ns ns ns ns tsu(D-OE) th(OE-D) tsu(D-SC) AND_DATA (status data) input hold time AND_DATA input hold time AND_DATA (status data) input setup time AND_DATA input setup time

M30245 Group Ele ctrical Characteristics Rev.2.00 Oct 16, 2006 page 241 of 264 REJ03B0005-0200 Switching characteristics (Vcc = 3.3V, Vss=0V, Topr =-20 C to 85 C unless otherwise stated) Table 1.95. Memory expansion mode and microprocessor mode Note 1:Calculated according toothe BCLK frequency as shown below: Note 2: Calculated as follows: th (WR-DB) = tcyc / 2 Note 3: Calculated as follows: th (WR-CS) = tcyc / 2 Symbol Parameter Measuring condition Standard Unit Min. Max. td (BCLK-AD) Address output delay time See Figure 1.199 VIL = 0.2Vcc, VIH = 0.8Vcc, VOL = 0.5Vcc, VOH = 0.5Vcc ns th (BCLK-AD) Address output hold time ns th (RD-AD) Address output hold time ns th (WR-AD) Address output hold time ns td (BCLK-CS) Chip select output delay time ns th (BCLK-CS) Chip select output hold time ns td (BCLK-ALE) ALE signal output delay time ns th (BCLK-ALE) ALE signal output hold time ns td (BCLK-RD) RD signal output delay time ns th (BCLK-RD) RD signal output hold time ns td (BCLK-WR) WR signal output delay time ns th (BCLK-WR) WR signal output hold time ns td (BCLK-DB) Data output delay time ns th (BCLK-DB) Data output tristate time td (DB-WR) Data output delay time ns th (WR-DB) Data output hold time ns (Note 1) (When PM16 = 0) td (DB-WR) = (m-0.5) X tcyc - 40nS (When PM16 = 1) td (DB-WR) = m X tcyc - 40nS (Note 2) ns(Note 3)th (WR-CS) Write high to Chip select high time

0 Wait selected: m = 1

1 Wait selected: m = 1

2 Wait selected: m = 2

3 Wait selected: m = 3

td (BCLK-HLDA) HLDA output delay time ns40 Figure 1.199. Port P0 to P10 measurement circuit P10 30pF

M30245 Group Ele ctrical Characteristics Rev.2.00 Oct 16, 2006 page 242 of 264 REJ03B0005-0200 Switching characteristics (Vcc = 3.3V, Vss=0V, Topr =-20 C to 85 C unless otherwise stated) Table 1.96. Serial I/O switching Symbol Parameter Standard Unit Min Max td(C-Q) TxDi output delay time 80 ns th(C-Q) TxDi hold time 0 ns tr(CK) CLKi output rise time 7 ns tf(CK) CLKi output fall time 7 ns 30 nsInternal clock is selected as transfer clock Internal clock is selected as transfer clock Internal clock is selected as transfer clock External clock is selected as transfer clock Table 1.97. Serial Sound Interface (SSI) Symbol Parameter Standard Unit Min Max td(WS-XMT) XMTi output delay time (WS based) 20 ns td(SCK-XMT) XMTi output delay time (SCK based) 20 ns Table 1.98. AND Flash Control switching AND_OE LOW pulse width th1(SC-D) Symbol Parameter Standard Unit Min Max AND_DATA (program data) output delay time ns ns ns ns (Note 1) (Note 2) Note 1: td(D-SC) = 0.5tcyc - 15nS Note 2: td(D-WE) = 1.5tcyc - 43nS Note 3: th1(SC-D) = 1.5tcyc - 30nS Note 4: th(WE-D) = 0.5tcyc nS Note 5: tw(OEL) = 1.5tcyc - 10nS Note 6: tw1(SCH) = tcyc - 15nS Note 7: tw2(SCH) = 1.5tcyc - 10nS Note 8: tw(WEL) = tcyc - 15nS td(D-WE) tw(WEL) th(WE-D) td(D-SC) tw1(SCH) tw2(SCH) tw(OEL) AND_DATA (command/address data) output delay time AND_DATA (program data) output hold time AND_DATA (command/address data) output hold time AND_WE LOW pulse width AND_SC write HIGH pulse width AND_SC read HIGH pulse width (Note 3) (Note 4) (Note 5) (Note 6) (Note 7) (Note 8) ns ns ns ns

M30245 Group Ele ctrical Characteristics Rev.2.00 Oct 16, 2006 page 243 of 264 REJ03B0005-0200 Timing Diagrams Figure 1.200. Timing diagram 1 tsu(D–C) TAiIN input TAiOUT input During event counter mode CLKi TxDi RxDi tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C–Q) th(C–D) th(C–Q) th(TIN–UP) tsu(UP–TIN) TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) TAiOUT input (Up/down input) INTi input ADTRG input tf(CK)tr(CK)

M30245 Group Ele ctrical Characteristics Rev.2.00 Oct 16, 2006 page 244 of 264 REJ03B0005-0200 Figu!re 1.201. Timing diagram 2 BCLK CSi ALE RD Hi-Z DB ADi BHE Read timing td(BCLK-AD) td(BCLK-ALE) th(BCLK-ALE) tSU(DB-RD) td(BCLK-RD) tac1(RD-DB) Memory Expansion Mode and Microprocessor Mode (With no wait) td(BCLK-CS) tcyc th(BCLK-CS) th(BCLK-AD) th(RD-AD) t th(RD-DB) BCLK CSi ALE th(WR-AD) ADi BHE DBi (PM16=0) Write timing WR,WRL, WRH (PM16=0) td(BCLK-CS) tcyc th(BCLK-CS) th(WR-CS) th(BCLK-AD)td(BCLK-AD) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-WR) th(BCLK-DB) td(BCLK-DB) td(DB-WR) th(WR-DB) th(BCLK-WR) WR,WRL, WRH (PM16=1) td(BCLK-WR) th(BCLK-WR) th(BCLK-DB)td(BCLK-DB) td(DB-WR) th(WR-DB) DBi (PM16=1) h(BCLK-RD)

M30245 Group Ele ctrical Characteristics Rev.2.00 Oct 16, 2006 page 245 of 264 REJ03B0005-0200 Figure 1.202. Timing diagram 3 BCLK CSi ALE RD Hi-Z DB ADi BHE Read timing td(BCLK-RD) th(RD-AD) Memory Expansion Mode and Microprocessor Mode (When accessing external memory area with 1 wait) td(BCLK-CS) tcyc th(BCLK-CS) th(BCLK-AD)td(BCLK-AD) td(BCLK-ALE) th(BCLK-ALE) th(BCLK-RD) tac2(RD-DB) th(RD-DB)tSU(DB-RD) BCLK CSi ALE th(WR-AD) ADi BHE DBi (PM16=0) Write timing WR,WRL, WRH (PM16=0) td(BCLK-CS) tcyc th(BCLK-CS) th(WR-CS) th(BCLK-AD)td(BCLK-AD) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-WR) th(BCLK-DB) td(BCLK-DB) td(DB-WR) th(WR-DB) th(BCLK-WR) WR,WRL, WRH (PM16=1) td(BCLK-WR) th(BCLK-WR) DBi (PM16=1) th(BCLK-DB) td(BCLK–DB) td(DB-WR) th(WR-DB)

M30245 Group Ele ctrical Characteristics Rev.2.00 Oct 16, 2006 page 246 of 264 REJ03B0005-0200 Figure 1.203. Serial Sound Interface timing diagram 1 (SCKP=0, SCK falling edge is before WS edge) th(SCK-RX) SCKi WSi RXi XMTi Serial Sound Interface Timing tw(SCKH) tc(SCK) tsu(RX-SCK) tw(SCKL) td(WS-XMT) t1(SCK-WS) t2(WS-SCK) th(SCK-RX) SCKi WSi RXi XMTi (SCKP=0, SCK falling edge is after WS edge) tw(SCKH) tc(SCK) tsu(RX-SCK) tw(SCKL) td(SCK-XMT) t1(SCK-WS) t2(WS-SCK)

M30245 Group Ele ctrical Characteristics Rev.2.00 Oct 16, 2006 page 247 of 264 REJ03B0005-0200 Figure 1.204. Serial Sound Interface timing diagram 2 (SCKP=1, SCK rising edge is before WS edge) th(SCK-RX) SCKi WSi RXi XMTi Serial Sound Interface Timing tw(SCKL) tc(SCK) tsu(RX-SCK) tw(SCKH) td(WS-XMT) t1(SCK-WS) t2(WS-SCK) th(SCK-RX) SCKi WSi RXi XMTi (SCKP=1, SCK rising edge is after WS edge) tw(SCKL) tc(SCK) tsu(RX-SCK) tw(SCKH) td(SCK-XMT) t1(SCK-WS) t2(WS-SCK)

M30245 Group Ele ctrical Characteristics Rev.2.00 Oct 16, 2006 page 248 of 264 REJ03B0005-0200 Figure 1.205. AND Flash Control read timing diagram BCLK tw(OEL) tsu(D-OE) AND_SC (P10) AND_SC (P10) AND_OE (P12) AND_OE (P12) AND_WE (P11) AND_WE (P11) 'H' tw2(SCH) 'Hi-Z'AND_DATA (P0) OECTL=0, WECTL=1 'L' OECTL=0, WECTL=0 => INHIBITED 'H' Read Cycle AND Flash Control Timing ADi Read timing 03E0h (P0) 'Hi-Z'AND_DATA (P0) OECTL=1, WECTL=1 'L' OECTL=1, WECTL=0 th(OE-D) => No Read Function => Status Read => Data Read tsu(D-SC) th2(SC-D)

M30245 Group Ele ctrical Characteristics Rev.2.00 Oct 16, 2006 page 249 of 264 REJ03B0005-0200 Figure 1.206. AND Flash Control write timing diagram th(WE-D) tw(WEL) OECTL=0, WECTL=1 => No Write Function Write Cycle AND_DATA (P0) AND_SC (P10) 'H' td(D-WE) AND Flash Control Timing BCLK ADi Write timing 03E0h (P0) 'Hi-Z'AND_DATA (P0) OECTL=1, WECTL=1 AND_SC (P10) 'H' 'L' OECTL=1, WECTL=0 'Hi-Z' 'H' th1(SC-D) td(D-SC) tw1(SCH) => Program Data Write => Command/Address Write OECTL=0, WECTL=0 => INHIBITED AND_WE (P11) AND_OE (P12) AND_WE (P11) AND_OE (P12)

Rev.2.00 Oct 16, 2006 page 250 of 264 REJ03B0005-0200 Usage Notes Timer A Timer mode The value of the counter can be read, with arbitrary timing, by reading the Timer Ai register while a count is in progress. Reading the Timer Ai register with the reload timing gets “FFFF 16”. After setting a value in the Timer Ai register, a proper value can be read with the counter stopped before it starts counting. Event counter mode The value of the counter can be read, with arbitrary timing, by reading the Timer Ai register while a count is in progress. Reading the Timer Ai register with the reload timing gets “FFFF 16” by underflow or “0000 16” by overflow. After setting a value in the Timer Ai register, a proper value can be read with the counter stopped before it starts counting . Reset the timer when counting has stopped in free run type. If using “Free-Run type”, the timer register contents may be unknown when counting begins. Set the timer value immediately after counting has started. Example if the up/down count is not switched:

• Enable the “Reload” function and write to the timer register before counting begins.
• Rewrite the value to the timer register immediately after counting has started.
• If counting up, rewrite “0000 16” to the timer register.
• If counting down, rewrite “FFFF1” to the timer register. This will cause the same operation as “Free-Run type”. Example if the up/down count is switched:
• Use the “Reload type” operation until the first count pulse is input.
• Switch to “Free-Run type”. One-shot timer mode Setting the count start flag to “0” while a count is in progress causes as the following:
• The counter stops counting and a content of reload register is reloaded.
• The TAi OUT pin outputs “L” level.
• The interrupt request generated and the Timer Ai interrupt request bit goes to “1”. The output from the one-shot timer synchronizes with the count source generated internally. Therefore, when an external trigger has been selected, a delay of one cycle of count source (maximum) occurs between the trigger input to the TAi IN pin and the one-shot timer output. The Timer Ai interrupt request bit goes to “1” if the timer's operation mode is set using any of the following procedures:
• Selecting one-shot timer mode after reset.
• Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use Timer Ai interrupt (interrupt request bit), set Timer Ai interrupt request bit to “0” after the above listed changes have been made. If a trigger occurs while a count is in progress, after the counter performs one down count following the reoccurrence of a trigger, the reload register contents are reloaded, and the count continues. To generate a trigger while a count is in progress, generate the second trigger after a period longer than one cycle of the timer's count source after the previous trigger occurred.

Rev.2.00 Oct 16, 2006 page 251 of 264 REJ03B0005-0200 Pulse modulation mode The Timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compliance with any of the following procedures:

• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode. Therefore, to use Timer Ai interrupt (interrupt request bit), set Timer Ai interrupt request bit to “0” after the above listed changes have been made. Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop counting. If the TAi OUT pin is outputting an “H” level in this instance, the output level goes to “L”, and the Timer Ai interrupt request bit goes to “1”. If the TAiOUT pin is outputting an “L” level in this instance, the level does not change, and the Timer Ai interrupt request bit does not becomes “1”. A/D converter
• Write to each bit (except bit 6) of AD control register 0, AD control register 1, and to bit 0 of AD control register 2 when A/D conversion is stopped (before a trigger occurs). When the V REF connection bit is changed from "0" to “1”, wait 1 µs or longer before starting A/D conversion.
• When changing A/D operation mode, select the analog input pin again.
• Using one-shot mode or single sweep mode: Read the corresponding AD register after confirming A/D conversion is finished. (Check the A/D conversion interrupt request bit.)
• Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1: Use the undivided main clock as the internal CPU clock. When f(X in) is faster than 10MHz, make the A/D frequency 10MHz or less by dividing.

Description

Serial I/O (UART Mode) When the CLKi and CTSi pin level goes to “H” (Note 1), if the UiMR register is set to either of the following settings, the UiERE bit of the UiC1 register is set to “1” (parity error signal output enabled). When the PRYE bit of the UiMR register is set to “1” while the UiERE bit is “1” (parity error signal output enabled), if a parity error occurs at receiving data, the T XDi pin outputs the “L” level. To prevent this, set the UiERE bit after setting the UiMR register.

• Set bits SMD2 through SMD0 to “0002” (serial I/O disabled) through “1012” (UART mode transfer data 8 bits long)
• Set bits SMD2 through SMD0 to “0012” (clock synchronous serial I/O mode) through “1002” (UART mode transfer data 7 bits long)
• Set bits SMD2 through SMD0 to “0012” (clock synchronous serial I/O mode) through “1012” (UART mode transfer data 8 bits long)
• Set bits SMD2 through SMD0 to “0012” (clock synchronous serial I/O mode) transfer data 9 bits long)
• Set bits SMD2 through SMD0 to “0102” (I2C mode) through “1012” (UART mode transfer data 8 bits long) Note 1: If the pins are not used as CLKi or CTSi, these conditions apply when the pin level goes to “H”.

Rev.2.00 Oct 16, 2006 page 252 of 264 REJ03B0005-0200 DMA (1) Additional description of the DMA enable bit Bit 3 of the DMA0 and DMA1 control registers is assigned as the DMA enable bit. Setting the DMA enable bit to “1” makes DMA active. If data transfer starts immediately after the DMA becomes active, the DMAC performs the following operations. (a) The value of either the source pointer or the destination pointer, whichever is set to the forward direction, is reloaded to the forward direction address pointer. (b) The value of the transfer counter register is reloaded to the transfer counter. Thus, writing “1” to the DMA enable bit when DMA is active causes the above operations to be carried out, and the DMAC operates again from the initial state at that point. (2) Additional description of the DMA request bit Bit 2 of the DMA0 and DMA1 control registers is assigned as the DMA request bit. The DMA request bit is set to “1” if a DMA transfer request signal occurs even if DMA is not active. Also, changing the DMA transfer request cause select bits may set the DMA request bit to “1”. Make sure to set the DMA request bit to “0” after changing the DMA request cause select bits. The DMA request bit is set to “1” if a DMA transfer request signal occurs and is set to “0” immediately after data transfer starts. If DMA is active, data transfer starts immediately, so the value of the DMA request bit, if read by software, will be “0” in most cases. To determine whether DMA is active, read the DMA enable bit. Figure 1.207 shows the setting routine for the DMA-related registers. Yes No Set DMA control register DMA enable bit = "0"? Select DMA request causes Set source pointer Set destination pointer Set transfer counter DMA request bit ← "0" DMA request bit ← "1" START END Figure 1.207. Setting routine of DMA control registers

Rev.2.00 Oct 16, 2006 page 253 of 264 REJ03B0005-0200 (3) Writing to the DMAE bit in DMiCON register If the following conditions are met: The DMAE bit is set to “1” again while it is already set to “1” (DMAi is in active state). A DMA request may occur simultaneously when the DMAE bit is being written. Follow the steps below: Step 1: Write “1” to the DMAE bit and DMAS bit in DMiCON register simultaneously (Note 1). Step 2: Make sure that the DMAi is in an initial state (Note 2) in a program. If the DMAi is not in an initial state, the above steps should be repeated. Note 1: The DMAS bit remains unchanged even if “1” is written. However, if “0” is written to this bit, it is set to “0” (DMA not requested). In order to prevent the DMAS bit from being modified to “0”, “1” should be written to the DMAS bit when “1” is written to the DMAE bit. In this way the state of the DMAS bit immediately before being written can be maintained. Similarly, when writing to the DMAE bit with a read-modify-write instruction, “1” should be written to the DMAS bit in order to maintain a DMA request which is generated during execution. Note 2: Read the TCRi register to verify whether the DMAi is in an initial state. If the read value is equal to a value which was written to the TCRi register before DMA transfer start, the DMAi is in an initial state. (If a DMA request occurs after writing to the DMAE bit, the value written to the TCRi register is “1”.) If the read value is a value in the middle of a transfer, the DMAi is not in an initial state.

Rev.2.00 Oct 16, 2006 page 254 of 264 REJ03B0005-0200 Stop Mode and Wait Mode (1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock oscillation is stabilized. (2) When switching to either wait mode or stop mode, instructions occupying four bytes either from the WAIT instruction or from the instruction that sets the all clock stop control bit to “1” within the instruction queue are prefetched and then the program stops. So put at least four NOPs in succession either to the WAIT instruction or to the instruction that sets the all clock stop control bit to “1”. (3) When using low-speed mode and low power dissipation mode, set the WAIT peripheral function clock stop bit (CM02) to “1” and do not shift to wait mode. (4) When using f SYN as the internal system clock, change to f(X IN) before entering to stop mode (set bit 0 of the frequency synthesizer control register to “0”). Interrupts Reading address 00000 16 When maskable interrupt occurs, the CPU reads the interrupt information (the interrupt number and interrupt request evel) in the interrupt sequence. The interrupt request bit of the interrupt written in address 00000 16 will then be set to “0”. Do not read address 00000 16 by software. Reading address 00000 16 by software sets enabled highest priority interrupt source request bit to “0”. Though the interrupt is generated, the interrupt routine may not be executed. Setting the stack pointer The value of the stack pointer immediately after reset is initialized to 0000 16. Accepting an interrupt before setting a value in the stack pointer may cause program runaway. Be sure to set a value in the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack pointer at the beginning of a program. Generating any interrupts including the NMI interrupt is prohibited for the first instruction immediately after reset. The NMI interrupt The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc with a pull-up resistor if unused. Do not go into stop mode when the NMI pin set to “L”. The NMI pin also serves as P8 5, which is exclusively an input. Reading the contents of the P8 register allows the pin value to be read. Reading this pin is only to be used for establishing the pin level when the NMI interrupt is input. Do not reset the CPU with the input to the NMI pin in the “L” state. Do not attempt to go into stop mode when the input to the NMI pin is in “L” state. When the input to the NMI is in “L” state, CM10 is fixed to “0” thereby refusing to go into stop mode. Do not attempt to go into wait mode when the input to the NMI pin is in “L” state. When the input to the NMI pin is in “L” state, the CPU stops but the oscillation does not. This action does not save power. When this occurs, the CPU is returned to the normal state by a later interrupt. Signals input to the NMI pin require an “L” level of (2 clocks + 300nS) or more from the operation clock of the CPU. External interrupt Either an “H” or “L” level of at least 250 ns width is necessary for the signal input to pins INT0 to INT2 regardless of the CPU operation clock. When the polarity of the INT0 to INT2 pins is changed, the interrupt request bit is sometimes set to “1”. After chang- ing the polarity, reset the interrupt request bit to “0”. Figure 1.208 shows the procedure for changing the INT interrupt generate factor.

Rev.2.00 Oct 16, 2006 page 255 of 264 REJ03B0005-0200 Figure 1.208. Switching condition of INT interrupt request Set the polarity select bit Clear the interrupt request bit to "0" Set the interrupt priority level 1 to 7 (Enable the INTi interrupt requests) Set the interrupt priority level to level 0 (Disable INTi interrupt) Clear the interrupt enable flag to "0" (Disable interrupt) Set the interrupt enable flag to "1" (Enable interrupt) Note: Execute the settings individually. Do not execute two or more settings simultaneously.

Rev.2.00 Oct 16, 2006 page 256 of 264 REJ03B0005-0200 Clearing the Interrupt request bit Even when the IR bit (bit 3 of the interrupt control register) is cleared to "0" (interrupt not requested), it may not actually get cleared to "0" depending on the instruction used to clear it. Therefore, use the MOV instruction to clear the IR bit. Rewriting the interrupt control register Rewrite the interrupt control register so that it does not generate an interrupt request for that register. If an interrupt request occurs, rewrite the interrupt control register after the interrupt is disabled. Some program examples are described below. When an instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not always set even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the instructions below to change the register. Instructions: AND, OR, BCLR, BSET Examples 1 through 3 show how to prevent the I flag from being set to "1" (interrupts enabled) before the interrupt control register is rewritting, due to the effects of the internal bus and the instruction queue buffer. Example 1: INT_SWITCH1: FCLR I :Disable interrupts. AND.B #00h, 0054h ;Clear TA0IC int. priority level and int. request bit. NOP ;Four NOP instructions are required when using the HOLD function . NOP FSET I ;Enable interrupts. Example 2: INT_SWITCH2: FCLR I :Disable interrupts. AND.B #00h, 0054h ;Clear TA0IC int. priority level and int. request bit. MOV.W MEM, R0 ;Dummy read. FSET I ;Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG ;Push Flag register onto stack FCLR I ;Diable interrupts. AND.B #00h, 0054h ;Clear TA0IC int. priority level and int. request bit.‘ POPC FLG ;Enable interrupts. The reason why two NOP instructions (four using the HOLD function) or a dummy read is inserted before "FSET I" in Examples 1 and 2, is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to the effects of the instruction queue.

Rev.2.00 Oct 16, 2006 page 258 of 264 REJ03B0005-0200 Programming Notes USB The following Programming Notes should be incorporated into user code, to ensure strict adherence to the USB protocol for Control Transfers. (1) In applications requiring high-reliability, we recommend providing the system with protective measures, such as USB function initialization by software or USB reset by the host, to prevent USB communication from being termi- nated unexpectedly, for example due to external causes such as noise. (2) USB2.0 specification stipulates a driver impedance 28 to 44 Ω (see 7.1.1.1 Full-speed (12Mb/s) Driver Characteris- tics). Connect a serial resistor (recommended value: 27 to 33Ω) to the USB D+ pin and the USB D- pin to satisfy this specification. Also connect, if required, a capacitor between the USB D+ pin or USB D-pin and the Vss pin. These capacitors are to control ringing or adjust the rise and fall times and the crossover point of D+/D-. The numerical values and configuration of the peripheral components need to be adjusted according to differences in the charac- teristic impedance and layout of the printed circuit board. on which they are mounted. Therefore, perform careful evaluation of the system in use and observe the waveforms before deciding on connection or disconnection and adjusting the values of the resistors and capacitors. (3) Do not connect the D+ pin or the D- pin to a choke coil. (4) If the USB Attach/Detach function will not be used, connect the UVcc pin and the USB D+ pin via a 1.5 k Ω resistor. (The D+ line pull-up timing depends on the UVcc pin.) If the USB Attach/Detach function is used, connect the P9 ATTACH pin and the USB D+ pin via a 1.5 kΩ resistor. Regardless of whether or not the USB Attach/Detach function is used, connect the UVcc pin to the power supply. In addition, the time required for the host PC to recognize the USB Attach/Detach state will vary depending state of the system as a whole, including board resistance and capacitance components, USB cable capacitance, and the board characteristics and processing speed of the host. Perform careful evaluation of the system in use. (5) The interrupt service routine (ISR) associated with those USB Function interrupts that are caused by errors must have execution priority over the ISR for EP0 interrupts. Upon receipt of a USB Function interrupt, the following actions should be taken: Step #1: From the USB Interrupt Status (USBIS) and the USB Endpoint 0 Control & Status (EP0CS) registers, determine if the 'Error Interrupt Status Flag' & the SETUP_END flag (i.e., INTST8 & EP0CSR5, respectively) are both set. [YES] => Set CLR_SETUP_END (EP0CSR11). Go to Step #2. [NO] => No special S/W action required. Go to Step #1 after the next USB Function interrupt. Step #2: Is EP0 IN FIFO loading in progress - i.e., data has been written to EP0 IN FIFO, but SET_IN_BUF_RDY (EP0CSR7) is not yet set? [YES] => Set SET_IN_BUF_RDY (EP0CSR7). Go to Step #3 after the next EP0 interrupt. [NO] => No special S/W action required. Go to Step #1 after the next USB Function interrupt. Step #3: Are OUT_BUF_RDY & SETUP (i.e., EP0CSR0 & EP0CSR2, respectively) set? [YES] => Go to Step #4. [NO] => Go to Step #3 after the next EP0 interrupt. Step #4: Does the current Control Transfer Setup stage DATA0 packet identify a Control Read Transfer? [YES] => Complete loading EP0 IN FIFO. Set CLR_OUT_BUF_RDY, SET_IN_BUF_RDY, & CLR_SETUP (i.e., EP0CSR6, EP0CSR7, & EP0CSR8, respectively). Go to Step #1 after the next USB Function interrupt. [NO] => Go to Step #3 after the next EP0 interrupt. Refer to the flowchart in Figure 1.211 for more information on this programming note.

Rev.2.00 Oct 16, 2006 page 259 of 264 REJ03B0005-0200 Figure 1.211. USB Programming Note 1 Flowchart No No Yes No Yes No Yes Yes Wait for EP0 Interrupt. Step #1 'Error Interrupt Status Flag'=1? SETUP_END = 1? CLR_SETUP_END = 1 SET_IN_BUF_RDY = 1 1) Complete loading EP0 IN FIFO. 2) Set: CLR_OUT_BUF_RDY = 1 Is EP0 IN FIFO loading in progress => data written, but SET_IN_BUF_RDY not yet set? Step #2 Step #3 OUT_BUF_RDY = 1? SETUP = 1? Step #4 Does the current Setup DATA0 packet identify a Control Read Transfer? USB Function Interrupt

Rev.2.00 Oct 16, 2006 page 260 of 264 REJ03B0005-0200 (6) Additional actions to take upon receipt of an EP0 interrupt are as follows (Refer to the flowchart in Figure 1.212): Step #1: Is OUT_BUF_RDY (EP0CSR0) set? [YES] => Go to Step #2. [NO] => No special S/W action required. Go to Step #1 after the next EP0 interrupt. Step #2: Is SETUP_END (EP0CSR5) set? [YES] => Set CLR_OUT_BUF_RDY, CLR_SETUP_END, & SEND_STALL (i.e., EP0CSR6, EP0CSR11, & EP0CSR12, respectively). [Also set CLR_SETUP, if SETUP flag == '1'.] Go to Step #1 after the next EP0 interrupt. [NO] => Go to Step #3. Step #3: Read number of data bytes equal to the EP0 'Receive Byte Count', stored in EP0WC7-0, from EP0 OUT FIFO. Is this the final DATA packet of a Control Write Transfer? [YES] => Go to Step #4_0. [NO] => Go to Step #5_0. Step #4_0: Is SETUP_END (EP0CSR5) set? [YES] => Set CLR_OUT_BUF_RDY, CLR_SETUP_END, & SEND_STALL (i.e., EP0CSR6, EP0CSR11, & EP0CSR12, respectively). [Also set CLR_SETUP, if SETUP flag == '1'.] Go to Step #1 after the next EP0 interrupt. [NO] => Set CLR_OUT_BUF_RDY & SET_DATA_END (i.e., EP0CSR6 & EP0CSR9, respectively). [Also set CLR_SETUP, if SETUP flag == '1'.] Go to Step #4_1. Step #4_1: Is SETUP_END (EP0CSR5) set? [YES] => Set SEND_STALL (EP0CSR12). Go to Step #6_0. [NO] => Go to Step #1 after the next EP0 interrupt. Step #5_0: Is SETUP_END (EP0CSR5) set? [YES] => Set CLR_OUT_BUF_RDY, CLR_SETUP_END, & SEND_STALL (i.e., EP0CSR6, EP0CSR11, & EP0CSR12, respectively). [Also set CLR_SETUP, if SETUP flag == '1'.] Go to Step #1 after the next EP0 interrupt. Step #5_1: Is SETUP_END (EP0CSR5) set? [YES] => Set SEND_STALL (EP0CSR12). Go to Step #6_0. [NO] => Go to Step #1 after the next EP0 interrupt. Step #6_0: Are OUT_BUF_RDY & SETUP (EP0CSR0 & EP0CSR2) set? [YES] => Go to Step #6_1. [NO] => Go to Step #6_0 after the next EP0 interrupt. Step #6_1: Is SETUP_END (EP0CSR5) set? [YES] => Set CLR_OUT_BUF_RDY, CLR_SETUP, & CLR_SETUP_END (EP0CSR6, EP0CSR8 & EP0CSR11). Go to Step #6_0 after the next EP0 interrupt. [NO] => Set CLR_OUT_BUF_RDY & CLR_SETUP (EP0CSR6 & EP0CSR8), and clear SEND_STALL (EP0CSR12). Go to Step #1 after the next EP0 interrupt. (7) Writing to the USB Function Interrupt Clear Register (USBIC). Writing to the USB Function Interrupt Clear Register (USBIC) to clear USB Function Interrupt Status bits requires special consideration. Before performing this operation, the USB Function Interrupt Enable Register (USBIE) should be cleared (i.e., all bits disabled). Upon completion of the write to USBIC, the value of USBIE just prior to its clearing should be restored.

Rev.2.00 Oct 16, 2006 page 261 of 264 REJ03B0005-0200 Figure 1.212. USB Programming Note 2 Flowchart Yes No No Yes Yes No SEND_STALL = 1 Read # of data bytes equal to EP0 ‘Receive Byte Count’ (i.e., EP0WC 7-0) from EP0 OUT FIFO . Read packet data EP0 Interrupt Step #3 No No Yes Yes Yes Step #2 SETUP_END = 1? Step #1 OUT_BUF_RDY = 1? CLR_OUT_BUF_RDY = 1 CLR_SETUP = 1 (if SETUP is set) CLR_SETUP_END = 1 SEND_STALL = 1 No No No CLR_OUT_BUF_RDY = 1 CLR_SETUP = 1 (if SETUP is set) SET_DATA_END = 1 CLR_OUT_BUF_RDY = 1 CLR_SETUP = 1 (if SETUP is set) Yes Yes Yes CLR_OUT_BUF_RDY = 1 CLR_SETUP = 1 OUT_BUF_RDY = 1? SETUP = 1? Step #6_0 Wait for EP0 Interrupt. SETUP_END = 1? Step #6_1 Final packet of Control Write Transfer? CLR_OUT_BUF_RDY = 1 CLR_SETUP = 1 Step #5_0 SETUP_END = 1? Step #5_1 SETUP_END = 1? Step #4_0 SETUP_END = 1? Step #4_1 SETUP_END = 1? No

Rev.2.00 Oct 16, 2006 page 262 of 264 REJ03B0005-0200 Using HOLD Signal When HOLD input is used, set P4 0 to P47 and P50 to P52 as input before the CPU shifts from single-chip mode to microprocessor mode or memory expansion mode. Decreasing Power Consumption When A/D conversion is not carried out, select not to connect V REF using the VREF connect bit in AD control register 1. To carry out A/D conversion, start the conversion 1 µs or longer after connecting VREF. Microprocessor Mode and Shifting from Microprocessor Mode to Memory Expansion Mode or Single- chip Mode In microprocessor mode, the SFR, internal RAM and external memory space can be accessed. Therefore, the internal ROM area cannot be accessed. If microprocessor mode is set (“H” is applied to the CNV SS pin) when coming out of a reset, the internal ROM cannot be accessed even if the CPU shifts to memory expansion mode or single-chip mode. Resetting when "H" is applied to CNVss pin If the microprocessor is reset when “H” is applied to the CNVss pin, the internal ROM cannot be read. Noise Connect a bypass capacitor (at least 0.1 µF) using the shortest and thickest wire possible. Input-only Pins If different power supplies are provided to the system, as shown in Figure 1.213 Circuit example, and the voltage of an unused input-only pin is higher than Vcc, do not directly connect the dedicated input pin to the power supply. As in the circuit example indicated by the arrow, connect the input-only pin to the power supply via a resistor rated at approxi- mately 1 kΩ. The above applies even if the power rise time is different at power-on. If the voltage of the input pin voltage is higher than Vcc, latch up could occur. *: A resistor is not required when using a Vcc voltage equal to or higher than the voltage of the dedicated input pin. Figure 1.213. Circuit example Different power supplies Vcc Dedicated input pin (ex. NMI pin) M30245 group Different power supplies Vcc Dedicated input pin (ex. NMI pin) M30245 group

Rev.2.00 Oct 16, 2006 page 263 of 264 REJ03B0005-0200 Electric Characteristic Differences Between Mask ROM and Flash Memory Version MCUs There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between Mask ROM and Flash Memory version MCUs due to the difference in the manufac-turing processes. When manufacturing an application system with the Flash Memory version and then switching to use of the Mask ROM ver-sion, please perform sufficient evaluations for the commercial samples of the Mask ROM version. Mask ROM Version Do not write to the internal ROM area in the Mask ROM version. ROM ORDERING METHOD 1.Mask ROM Order Confirmation Form 2.Mark Specification Form 3.Data to be written to ROM, in one floppy disk. * For the mask ROM confirmation and the mark specifications, refer to the “Renesas Technology Corp.” Homepage (http://www.renesas.com).

Rev.2.00 Oct 16, 2006 page 264 of 264 REJ03B0005-0200 Package Outline Terminal cross section bp c DO NOT INCLUDE MOLD FLASH. NOTE) DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. y Index mark x 12 5 5175 100 F ZE ZD E D HD HE bp Detail F A2A1 L A c ZE ZD bp HE HD y 0.08 e 0.5 c 0° 8° x L 0.35 0.5 0.65 0.05 0.1 0.15 A 1.7 15.8 16.0 16.2 15.8 16.0 16.2 A2 1.4 E 13.9 14.0 14.1 D 13.9 14.0 14.1 Reference Symbol Dimension in Millimeters Min Nom Max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 Previous CodeJEITA Package Code RENESAS Code PLQP0100KB-A 100P6Q-A / FP-100U / FP-100UV MASS[Typ.] 0.6gP-LQFP100-14x14-0.50 e PLQP0100KB-A

REVISION HISTORY M30245 Group Datasheet Rev. Date Description Page Summary

1.20 Jul 20, 2004 −

2.00 Oct 16, 2006All pages

Figure 1.8 revised Modifying the interrupt control registers revised “In I 2C master mode, .... of the direction register” Figure 1.106 Note revised UARTi Special Mode Register (UiSMR) “Port (SCLi) is .... of the port direction register.” → “In I Usage Notes added Programming Notes; USB (1) to (4) added Using HOLD Signal, Decreasing Power Consumption, Microprocessor Mode and Shifting from Microprocessor Mode to Memory Expan- sion Mode or Singlechip Mode, Resetting when “H” is applied to CNVss pin, Noise, Input-only Pins added Electric Characteristic Differences Between Mask ROM and Flash Memory Version MCUs, Mask ROM Version, ROM ORDERING METHOD added Package Outline added

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