M30201M4-XXXSP integrated circuit reference — Local datasheet available

Logic IC

M30201M4-XXXSP

Renesas Technology Corp

The M30201 group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core. M30201 group is packaged in a 52-pin plastic m…

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2.3.7 Precautions for Timer B (pulse period/pulse width measurement mode)

Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

MITSUBISHI 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY M30201 Group User's manual

Keep safety first in your circuit designs! Notes regarding these materials G Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. G These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. G Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. G All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http:// www.mitsubishichips.com). G When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. G Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. G The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. G If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. G Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semicon ductor product distributor for further details on these materials or the products con tained therein.

This user's manual is written for the M30201 group. The reader of this manual is expected to have the basic knowledge of electric and logic circuits and microcomputers. This manual is for the use of the models below.

M30201M4-XXXSP/FP • M30201M4T-XXXFP • M30201M6-XXXFP
M30201M6T-XXXFP • M30201F6SP/FP • M30201F6TFP These products have similar features except for the memories, which differ from one product to another. This manual gives descriptions of M30201M4-XXXSP. Memories built-in are as shown below. Be careful when writing a program, as the memories have different capacities. The figure of each register configuration describes its functions, contents at reset, and attributes as follows : This manual comprises of eight chapters. Use the suggested chapters as a reference for the following topics:
Bit attribute TA2OS TA0OS One-shot start flag Symbol Address When reset ONSF 0382 16 00X000002 Timer A0 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag TA3OS TA4OS Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. TA0TGL TA0TGH 0 0 : Input on TA0IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA4 overflow is selected 1 1 : TA1 overflow is selected Timer A0 event/trigger select bit b7 b6 Note: Set the corresponding port direction register to “0”. WR 1 : Timer start When read, the value is “0” /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Bit attribute RAM Size (Byte) 16K 32K M30201M4-XXXSP/FP M30201M4T-XXXFP 512 ROM Size (Byte) M30201F6SP/FP M30201F6TFP M30201M6-XXXFP M30201M6T-XXXFP 48K

This manual comprises of five chapters. Use the suggested chapters as a reference for the following topics: * To understand the basic way of using peripheral * To observe applications of This manual includes a quick reference immediately following the Table of Contents, indicate the page of the topic to be pursued. * To find a page describing a specific register

M16C Family-related document list Usages (Microcomputer development flow) Outline design of system Selection of microcomputer Detail design of system Hard- ware devel- opment System evaluation Soft- ware devel- opment

Contents

Hardware specifications (pin assignment, memory map, specifications of peripheral func- tions, electrical characteristics, timing charts) Detailed description about hardware specifica- tions, operation, and application examples (connection with peripherals, relationship with software) Method for creating programs using assembly and C languages Detailed description about operation of each instruction (assembly language) Hardware Type of document Data sheet and data book User’s manualSoftware M16C Family M16C/80 Series M16C/80 Group M16C/60 Series M16C/60 Group M16C/61 Group M16C/62 Group M16C/20 Series M16C/20 Group M16C/21 Group M16C/22 Group M16C/24 Group M16C Family Line-up Programming manual Software manual

2.2.7 Operation of timer A (2-phase pulse signal process in event counter mod normal mode se-

2.2.8 Operation of timer A (2-phase pulse signal process in event counter mode,multiply-by-4 mode

2.5.3 Operation of the Serial I/O (transmission in clock-synchronous serial I/O mode, transfer clock

Chapter 3 Examples of Peripheral functions Applications ________

Quick Reference to Pages Classified by Address 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C 16 004D 16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C 16 005D 16 005E16 005F16 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C 16 001D 16 001E16 001F16 INT1 interrupt control register (INT1IC) Timer B0 interrupt control register (TB0IC) Timer X0 interrupt control register (TX0IC) Timer X2 interrupt control register (TX2IC) UART0 transmit interrupt control register (S0TIC) INT0 interrupt control register (INT0IC) Timer B1 interrupt control register (TB1IC) Timer A0 interrupt control register (TA0IC) Timer X1 interrupt control register (TX1IC) UART0 receive interrupt control register (S0RIC) UART1 transmit interrupt control register (S1TIC) UART1 receive interrupt control register (S1RIC) Key input interrupt control register (KUPIC) A-D conversion interrupt control register (ADIC)Watchdog timer start register (WDTS) Watchdog timer control register (WDC) Processor mode register 0 (PM0) Address match interrupt register 0 (RMAD0) Address match interrupt register 1 (RMAD1) System clock control register 0 (CM0) System clock control register 1 (CM1) Address match interrupt enable register (AIER) Protect register (PRCR) Processor mode register 1(PM1) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 Address Register PageAddress Register Page

Quick Reference to Pages Classified by Address Address Register Page Address Register Page 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C 16 038D 16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C 16 039D 16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA 16 03AB 16 03AC 16 03AD 16 03AE 16 03AF 16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA 16 03BB 16 03BC 16 03BD 16 03BE 16 03BF 16 UART0 transmit/receive mode register (U0MR) UART0 transmit buffer register (U0TB) UART0 receive buffer register (U0RB) UART1 transmit/receive mode register (U1MR) UART1 transmit buffer register (U1TB) UART1 receive buffer register (U1RB) Timer A0 (TA0) Timer X0 (TX0) Timer X1 (TX1) Timer B0 (TB0) Timer B1 (TB1) Count start flag (TABSR) One-shot start flag (ONSF) Timer A0 mode register (TA0MR) Timer X0 mode register (TX0MR) Timer X1 mode register (TX1MR) Timer B0 mode register (TB0MR) Timer B1 mode register (TB1MR) Up-down flag (UDF) Timer X2 (TX2) Clock divided counter (CDC) Timer X2 mode register (TX2MR) Trigger select register (TRGSR) UART0 bit rate generator (U0BRG) UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1) UART1 bit rate generator (U1BRG) UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1) UART transmit/receive control register 2 (UCON) Clock prescaler reset flag (CPSRF) 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA 16 03EB 16 03EC 16 03ED 16 03EE 16 03EF 16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA 16 03FB 16 03FC 16 03FD 16 03FE 16 03FF16 03C0 16 03C1 16 03C2 16 03C3 16 03C4 16 03C5 16 03C6 16 03C7 16 03C8 16 03C9 16 03CA 16 03CB 16 03CC 16 03CD 16 03CE 16 03CF 16 03D0 16 03D1 16 03D2 16 03D3 16 03D4 16 03D5 16 03D6 16 03D7 16 03D8 16 03D9 16 03DA 16 03DB 16 03DC 16 03DD 16 03DE 16 03DF 16 Port P0 (P0) Port P0 direction register (PD0) Port P1 (P1) Port P1 direction register (PD1) Port P2 (P2) Port P2 direction register (PD2) Port P3 (P3) Port P3 direction register (PD3) Port P4 (P4) Port P4 direction register (PD4) Port P5 (P5) Port P5 direction register (PD5) Port P6 (P6) Port P6 direction register (PD6) Port P7 (P7) Port P7 direction register (PD7) Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) Pull-up control register 2 (PUR2) A-D register 7 (AD7) A-D register 0 (AD0) A-D register 1 (AD1) A-D register 2 (AD2) A-D register 3 (AD3) A-D register 4 (AD4) A-D register 5 (AD5) A-D register 6 (AD6) A-D control register 0 (ADCON0) A-D control register 1 (ADCON1) A-D control register 2 (ADCON2) 104 103 104 103 104 103 104 103 105 Flash memory control register 0 (FCON0) (Note) Flash memory control register 1 (FCON1) (Note) Flash command register (FCMD) (Note) Note: This register is only exist in flash memory version. 127

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Description

The M30201 group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core. M30201 group is packaged in a 52-pin plastic molded SDIP, or 56-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of execut- ing instructions at high speed. The M30201 group includes a wide range of products with different internal memory types and sizes and various package types.

Features

2.7 to 5.5V (f(XIN)=3.5MHz ):mask ROM version 4.0 to 5.5V (f(XIN)=10MHz) :flash memory version (including key input interrupt)

Clock output (built-in feedback resistor, and external ceramic or quartz oscillator)

Applications

Home appliances, Audio, office equipment, Automobiles

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER P10(LED0) P11(LED1) P12(LED2) P13(LED3) P14(LED4) P15(LED5) P16(LED6) P17(LED7) M30201MX-XXXSPM30201F6SP P00/KI0 P30 P31 P32P33 P34 P35 P40/TA0IN/TXD 1 P41/TA0OUT P42/RXD 1 P44/INT1/TX1INOUT P43/INT0/TX0INOUT Pin Configuration Figures 1.1 to 1.2 show the pin configurations (top view). PIN CONFIGURATION (top view) Package: 52P4B Figure 1.1. Pin configuration for the M30201 group (shrink DIP product) (top view)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER /AN 3/CLKS/AN V REF 0/AN 1/AN AV SS AV CC P10(LED0) 4(LED M30201MX-XXXFP M30201MXT-XXXFP M30201F6FP M30201F6TFP N.C. N.C. N.C. N.C. P00/KI0 2/AN 3/AN 4/AN 5/AN 6/AN P01/KI1 P02/KI2 P03/KI3 P04/KI4 P05/KI5 P06/KI6 P07/KI7 P11(LED1) P12(LED2) P13(LED3) 5(LED 6(LED 7(LED P44/INT1/TX1INOUT P43/INT0/TX0INOUT 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 56 55 54 53 27 28 Figure 1.2. Pin configuration for the M30201 group (QFP product) (top view) Package: 56P6S-A PIN CONFIGURATION (top view)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.1. Performance outline of M30201 group Performance Outline Table 1.1 is performance outline of M30201 group. Item Performance Number of basic instructions 91 instructions Shortest instruction execution time 100ns (f(X IN)=10MHz Memory ROM (See figure 4. ROM expansion.) capacity RAM (See figure 4. ROM expansion.) I/O port P0 to P7 43 lines Multifunction TA0 16 bits x 1 timer TB0, TB1 16 bits x 2 TX0, TX1, TX2 16 bits x 3 Serial I/O UART0 (UART or clock synchronous) x 1 UART1 UART x 1 A-D converter 10 bits x 8 channels (Expandable up to 13 channels) Watchdog timer 15 bits x 1 (with prescaler) Interrupt 13 internal and 3 external sources, 4 software sources Clock generating circuit 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) Supply voltage 4.0 to 5.5V (f(X IN)=10MHz) :mask ROM version 2.7 to 5.5V (f(XIN)=3.5MHz) :mask ROM version 4.0 to 5.5V (f(XIN)=10MHz) :flash memory version Power consumption 11mW (f(X IN)=3.5MHz , Vcc=3V) :mask ROM version 95mW (f(XIN)=10MHz, Vcc=5V) :flash memory version I/O I/O withstand voltage 5V characteristics Output current 5mA (15mA:LED drive port) Device configuration CMOS silicon gate Package 52-pin plastic mold SDIP 56-pin plastic mold QFP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Mitsubishi plans to release the following products in the M30201 group: (1) Support for mask ROM version and flash memory version (2) ROM capacity (3) Package 52P4B : Plastic molded SDIP (mask ROM version and flash memory version) 56P6S-A : Plastic molded QFP (mask ROM version and flash memory version) RAM Size (Byte) 16K 32K M30201M4-XXXSP/FP M30201M4T-XXXFP 512 ROM Size (Byte) M30201F6SP/FP M30201F6TFP M30201M6-XXXFP M30201M6T-XXXFP 48K Figure 1.4. ROM expansion Apr. 2001 Package type: SP : Package 52P4B FP : Package 56P6S-A ROM No. Omitted for flash memory version Shows difference of characteristics and usage etc: Nothing : Common T : Automobiles Memory type: M : Mask ROM version F : Flash memory version Type No. M 3 0 2 0 1 M 4 T – X X X S P M30201 Group M16C Family Shows pin count, etc (The value itself has no specific meaning) ROM capacity: 4 : 32K bytes 6 : 48K bytesFigure 1.5. Type No., memory size, and package

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin Description VCC , VSS CNV SS XIN XOUT AV CC AV SS VREF P00 to P07 P10 to P17 P30 to P35 P40 to P45 Signal name Power supply input CNV SS Reset input Clock input Clock output Analog power supply input Reference voltage input I/O port P0 I/O port P1 I/O port P3 I/O port P4 Supply 2.7 to 5.5 V to the V CC pin. Supply 0 V to the VSS pin. Function Connect it to the VSS pin. A “L” on this input resets the microcomputer. These pins are provided for the main clock generating circuit. Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. This pin is a power supply input for the A-D converter. Connect it to V CC . This pin is a power supply input for the A-D converter. Connect it to V SS . This pin is a reference voltage input for the A-D converter. This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When set for input, the user can specify in units of four bits via software whether or not they are tied to a pull-up resistor. This is an 8-bit I/O port equivalent to P0. This is a 6-bit I/O port equivalent to P0. This is a 6-bit I/O port equivalent to P0. The P4 0 pin is shared with timer A0 input and serial I/O output TxD1. The P41 pin is shared with timer A0 output. The P42 pin is shared with serial I/O input RxD1. The P43 pin is shared with external interrupt INT0 and timer X0 input/output TX0INOUT . The P44 pin is shared with external interrupt INT1 and timer X1 input/output TX1 INOUT . The P45 pin is shared with timer X2 input/output TX2 INOUT . Pin name Input Input Input Output Input Input/output Input/output I/O type Analog power supply input Input/output Input/output RESET I/O port P5 Input/output Input/output Input/output I/O port P6 I/O port P7 P50 to P54 P60 to P67 P70 to P71 This is a 5-bit I/O port equivalent to P0. The P50, P51, P52, and P53 pins are shared with serial I/O pins TxD0, RxD0, CLK0, and CLKS. The P54 pin is shared with clock output CLKOUT . Also, these pins are shared with analog input pins AN50 through AN54. This is an 8-bit I/O port equivalent to P0. These pins are shared with analog input pins AN0 through AN7. This is a 2-bit I/O port equivalent to P0 . These pins are used for input/output to and from the oscillator circuit for the clock. Connect a crystal oscillator between the X CIN and the XCOUT pins. Pin Description

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C 16 001D 16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C 16 004D 16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C 16 005D 16 005E16 005F16 Watchdog timer start register (WDTS) Watchdog timer control register (WDC) Processor mode register 0 (PM0) Address match interrupt register 0 (RMAD0) Address match interrupt register 1 (RMAD1) System clock control register 0 (CM0) System clock control register 1 (CM1) Address match interrupt enable register (AIER) Protect register (PRCR) Processor mode register 1(PM1) Timer X0 interrupt control register (TX0IC) UART0 transmit interrupt control register (S0TIC) Timer A0 interrupt control register (TA0IC) Timer X1 interrupt control register (TX1IC) UART0 receive interrupt control register (S0RIC) UART1 transmit interrupt control register (S1TIC) UART1 receive interrupt control register (S1RIC) Key input interrupt control register (KUPIC) A-D conversion interrupt control register (ADIC) INT1 interrupt control register (INT1IC) Timer B0 interrupt control register (TB0IC) Timer X2 interrupt control register (TX2IC) INT0 interrupt control register (INT0IC) Timer B1 interrupt control register (TB1IC) Note: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. Figure 1.7. Location of peripheral unit control registers (1)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory Figure 1.8. Location of peripheral unit control registers (2) 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C 16 038D 16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C 16 039D 16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA 16 03AB 16 03AC 16 03AD 16 03AE 16 03AF 16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA 16 03BB 16 03BC 16 03BD 16 03BE 16 03BF 16 Timer A0 (TA0) Timer X0 (TX0) Timer X1 (TX1) Timer B0 (TB0) Timer B1 (TB1) Count start flag (TABSR) One-shot start flag (ONSF) Timer A0 mode register (TA0MR) Timer X0 mode register (TX0MR) Timer X1 mode register (TX1MR) Timer B0 mode register (TB0MR) Timer B1 mode register (TB1MR) Up-down flag (UDF) Timer X2 (TX2) Clock divided counter (CDC) Timer X2 mode register (TX2MR) Trigger select register (TRGSR) Clock prescaler reset flag (CPSRF) UART0 transmit/receive mode register (U0MR) UART0 transmit buffer register (U0TB) UART0 receive buffer register (U0RB) UART1 transmit/receive mode register (U1MR) UART1 transmit buffer register (U1TB) UART1 receive buffer register (U1RB) UART0 bit rate generator (U0BRG) UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1) UART1 bit rate generator (U1BRG) UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1) UART transmit/receive control register 2 (UCON) Flash memory control register 0 (FCON0) (Note1) Flash memory control register 1 (FCON1) (Note1) Flash command register (FCMD) (Note) Note 1: This register is only exist in flash memory version. Note 2: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. 03C0 16 03C1 16 03C2 16 03C3 16 03C4 16 03C5 16 03C6 16 03C7 16 03C8 16 03C9 16 03CA 16 03CB 16 03CC 16 03CD 16 03CE 16 03CF 16 03D0 16 03D1 16 03D2 16 03D3 16 03D4 16 03D5 16 03D6 16 03D7 16 03D8 16 03D9 16 03DA 16 03DB 16 03DC 16 03DD 16 03DE 16 03DF 16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA 16 03EB 16 03EC 16 03ED 16 03EE 16 03EF 16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA 16 03FB 16 03FC 16 03FD 16 03FE 16 03FF16 A-D register 7 (AD7) A-D register 0 (AD0) A-D register 1 (AD1) A-D register 2 (AD2) A-D register 3 (AD3) A-D register 4 (AD4) A-D register 5 (AD5) A-D register 6 (AD6) Port P0 (P0) Port P0 direction register (PD0) Port P1 (P1) Port P1 direction register (PD1) Port P2 (P2) (Reserved) Port P2 direction register (PD2) (Reserved) Port P3 (P3) Port P3 direction register (PD3) Port P4 (P4) Port P4 direction register (PD4) Port P5 (P5) Port P5 direction register (PD5) Port P6 (P6) Port P6 direction register (PD6) Port P7 (P7) Port P7 direction register (PD7) Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) Port P1 drive control register (DRR) A-D control register 0 (ADCON0) A-D control register 1 (ADCON1) A-D control register 2 (ADCON2)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Central Processing Unit (CPU) The CPU has a total of 13 registers shown in Figure 1.9. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks. (1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3) Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H, R1H), and low-order bits as (R0L, R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32-bit data registers (R2R0, R3R1). (2) Address registers (A0 and A1) Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). Figure 1.9. Central processing unit register /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines H L b15 b8 b7 b0 R0 (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines H L b15 b8 b7 b0 R1 (Note) R2 (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 R3 (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 A0(Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 A1(Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 FB (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 Data registers Address registers Frame base registers b15 b0 b15 b0 b15 b0 b15 b0 b0 b19 b0 b19 H L Program counter Interrupt table register User stack pointer Interrupt stack pointer Static base register Flag register PC INTB USP ISP SB FLG Note: These registers consist of two register banks. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines C D Z S B O I UIPL

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU (3) Frame base register (FB) Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing. (4) Program counter (PC) Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed. (5) Interrupt table register (INTB) Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table. (6) Stack pointer (USP/ISP) Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config- ured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG). (7) Static base register (SB) Static base register (SB) is configured with 16 bits, and is used for SB relative addressing. (8) Flag register (FLG) Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.10 shows the flag register (FLG). The following explains the function of each flag:

Bit 0: Carry flag (C flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
Bit 1: Debug flag (D flag) This flag enables a single-step interrupt. When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is cleared to “0” when the interrupt is acknowledged.
Bit 2: Zero flag (Z flag) This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
Bit 3: Sign flag (S flag) This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”.
Bit 4: Register bank select flag (B flag) This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
Bit 5: Overflow flag (O flag) This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
Bit 6: Interrupt enable flag (I flag) This flag enables a maskable interrupt. An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0” when the interrupt is acknowledged.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU

Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected when this flag is “1”. This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos. 0 to 31 is executed.
Bits 8 to 11: Reserved area
Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled.
Bit 15: Reserved area The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details. Figure 1.10. Flag register (FLG) Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area Flag register (FLG) /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines C D Z S B O I UIPL b0 b15

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Reset Figure 1.13. Device's internal status after a reset is cleared x : Nothing is mapped to this bit ? : Undefined The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. (1) (0004 16)···Processor mode register 0 (2) (000516)···Processor mode register 1 (3) (000616)···System clock control register 0 (4) (000716)···System clock control register 1 (5) (6) (000916)···Address match interrupt enable register (7) (000A 16)··· (9) (000F16)···Watchdog timer control register (11) (001416)··· (001516)··· (001616)··· (12) (13) (21) (22) (23) (004D16)···Key input interrupt control register (20) (8) Protect register (001016)···Address match interrupt register 0 (0011 16)··· (001216)··· (10) (14) (15) (16) (17) (18) (19) (24) A-D conversion interrupt control register (25) (26) (004E 16)··· (27) (28) (29) (30) UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register (31) (32) (33) (34) (35) (36) (37) Timer A0 interrupt control register Timer X0 interrupt control register Timer X1 interrupt control register Timer X2 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register (38) (39) INT0 interrupt control register (40) INT1 interrupt control register (41) (0051 16)··· (005216)··· (005316)··· (005416)··· (005516)··· (005616)··· (005716)··· (005816)··· (005A16)··· (005B16)··· (005D16)··· (005E16)··· (038316)···Trigger select flag (038416)···Up-down flag (039616)···Timer A0 mode register (039716)···Timer X0 mode register (039816)···Timer X1 mode register (039B16)···Timer B0 mode register (039C16)···Timer B1 mode register (039916)···Timer X2 mode register (038216)···One-shot start flag (03A816)··· UART1 transmit/receive control register 0 (03AD16)···UART1 transmit/receive control register 1 (03B0 16)···UART transmit/receive control register 2 (03A0 16)···UART0 transmit/receive mode register (03A4 16)···UART0 transmit/receive control register 0 (03A5 16)···UART0 transmit/receive control register 1 Count start flag (0380 16)··· (038116)···Clock prescaler reset flag 01001000 000 0 0 0 0 1 000 0000 0016 0016 0016 0016 0016 0016 0016 000 0 0016 0016 000? 000? 000? 000? 000? 000? 000? 000? 000? 000? 000? 000? 00 000? 00 000? 00 0 0 00 00 0 0 0 000000 00010000 00000100 00010000 00000100 0016 0016 00 0000? 00 0000? (03AC16)··· UART1 transmit/receive mode register Address match interrupt register 1 (48) (49) (46) (47) (45) (50) (51) (52) (53) (59) (57) (58) (55) (56) (54) (64) (63) (65) (66) (62) (03D4 16)···A-D control register 2 (03D616)···A-D control register 0 (03D716)···A-D control register 1 (60) (61) (03E216)···Port P0 direction register (03E316)···Port P1 direction register (03E616)···Port P2 direction register (03E716)···Port P3 direction register (03EA16)···Port P4 direction register (03EB16)···Port P5 direction register (03EE16)···Port P6 direction register (03EF16)···Port P7 direction register (03FC16)···Pull-up control register 0 (03FD16)···Pull-up control register 1 (03FE16)···Port P1 drive capacity control register Frame base register (FB) Address registers (A0/A1) Interrupt table register (INTB) User stack pointer (USP) Interrupt stack pointer (ISP) Static base register (SB) Flag register (FLG) Data registers (R0/R1/R2/R3) 00000??? 0016 0016 0016 0016 0016 0016 0016 000016 000016 000016 0000016 000016 000016 000016 000016 0000000 000000 00000 0 00000 0 0 0 (43) (44) (42) (03B416)···Flash memory control register 0 (Note ) (03B516)···Flash memory control register 1 (Note) (03B6 16)···Flash command register 0016 0 0 0 0 000 0 0 1 0 0 Note: This register is only exist in flash memory version.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The following paragraphs describes the clocks generated by the clock generating circuit. (1) Main clock The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation. After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the X IN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is re- tained. (2) Sub-clock The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset. After oscillation is started using the port Xc select bit (bit 4 at address 0006 16), the sub-clock can be selected as BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the sub-clock oscillation has fully stabilized before switching. After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock oscillation circuit can be reduced using the X CIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit changes to “1” when shifting to stop mode and at a reset. (3) BCLK The BCLK is the clock that drives the CPU, and is fc or the clock is derived by dividing the main clock by 1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The main clock division select bit 0(bit 6 at address 0006 16) changes to “1” when shifting from high- speed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. (4) Peripheral function clock (f1, f8, f32, fAD ) The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 0006 16) to “1” and then executing a WAIT instruction. (5) fC32 This clock is derived by dividing the sub-clock by 32. It is used for the timer A, timer B and timer X counts. (6) fC This clock has the same frequency as the sub-clock. It is used for BCLK and for the watchdog timer.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock Output The clock output function select bit allows you to choose the clock from f8, fc, or a divide-by-n clock that is output from the P54/CKOUT pin. The clock divide counter is an 8-bit counter whose count source is f32, and its divide ratio can be set in the range of 0016 to FF16. Figure 1.19 shows a block diagram of clock output. Figure 1.19. Block diagram of clock output Clock source selection Reload register (8) Low-order 8 bits Data bus low-order bits P54 fC Division n+1 n=0016 to FF16 Clock divided couter (8) Example: When f(XIN)=10MHz n=0716 : approx. 19.5kHz n=2616 : approx. 4.0kHz n=4D 16 : approx. 2.0kHz n=9B 16 : approx. 1.0kHz P54/CKOUT f32 Address 038E16

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin States Port Retains status before wait mode CLK OUT When fC selected Does not stop When f8, clock devided Does not stop when the WAIT counter output selected peripheral function clock stop bit is “0”. When the WAIT peripheral function clock stop bit is “1”,the status immedi- ately prior to entering wait mode is maintained. Wait Mode When a WAIT instruction is executed, BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. However, peripheral function clock f C32 does not stop so that the peripherals using fC32 do not contribute to the power saving. When the MCU running in low- speed or low power dissipation mode, do not enter WAIT mode with this bit set to “1”. Table 1.4 shows the status of the ports in wait mode. Wait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, the microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected when the WAIT instruction was executed. Table 1.4. Port status during wait mode Table 1.3. Port status during stop mode Stop Mode, Wait Mode Pin States Port Retains status before stop mode CLK OUT When fC selected “H” When f8, clock devided Retains status before stop mode counter output selected Stop Mode Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcom- puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains above 2V. Because the oscillation of BCLK, f1 to f32, fc, fc32, and fAD stops in stop mode, peripheral functions such as the A-D converter and watchdog timer do not function. However, timer A, timer B and timer X operate provided that the event counter mode is set to an external pulse, and UART0 functions provided an external clock is selected. Table 1.3 shows the status of the ports in stop mode. Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled. If returning by an interrupt, that interrupt routine is executed. When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division select bit 0 (bit 6 at address 0006 16) is set to “1”. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 0 1 0 0 0 Invalid Division by 2 mode 1 0 0 0 0 Invalid Division by 4 mode Invalid Invalid 0 1 0 Invalid Division by 8 mode 1 1 0 0 0 Invalid Division by 16 mode 0 0 0 0 0 Invalid No-division mode Invalid Invalid 1 Invalid 0 1 Low-speed mode Invalid Invalid 1 Invalid 1 1 Low power dissipation mode Status Transition of BCLK Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table 1.5 shows the operating modes corresponding to the settings of system clock control regis- ters 0 and 1. When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address 0006 16) changes to “1” when shifting from high-speed/medium-speed to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. The following shows the operational modes of BCLK. (1) Division by 2 mode The main clock is divided by 2 to obtain the BCLK. (2) Division by 4 mode The main clock is divided by 4 to obtain the BCLK. (3) Division by 8 mode The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption mode, make sure the sub-clock is oscillating stably. (4) Division by 16 mode The main clock is divided by 16 to obtain the BCLK. (5) No-division mode The main clock is divided by 1 to obtain the BCLK. (6) Low-speed mode fC is used as BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub- clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled. (7) Low power dissipation mode fC is the BCLK and the main clock is stopped. CM17 CM16 CM07 CM06 CM05 CM04 Operating mode of BCLK Status Transition of BCLK Table 1.5. Operating modes dictated by settings of system clock control registers 0 and 1 Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which the count source is going to be switched must be oscillating stably. Allow a wait time in software for the oscillation to stabilize before switching over the clock.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Power Saving There are three power save modes. (1) Normal operating mode

High-speed mode In this mode, one main clock cycle forms BCLK. The CPU operates on the BCLK. The peripheral functions operate on the clocks specified for each respective function.
Medium-speed mode In this mode, the main clock is divided into 2, 4, 8, or 16 to form BCLK. The CPU operates on the BCLK. The peripheral functions operated on the clocks specified for each respective function.
Low-speed mode In this mode, fc forms BCLK. The CPU operates on the fc clock. fc is the clock supplied by the subclock. The peripheral functions operate on the clocks specified for each respective function.
Low power-dissipation mode This mode is selected when the main clock is stopped from low-speed mode. The CPU operates on the fc clock. fc is the clock supplied by the subclock. Only the peripheral functions for which the subclock was selected as the count source continue to run. (2) Wait mode CPU operation is halted in this mode. The oscillator continues to run. (3) Stop mode All oscillators stop in this mode. The CPU and internal peripheral functions all stop. Of all 3 power saving modes, power savings are greatest in this mode. Figure 1.20 shows the transition between each of the three modes, (1), (2), and (3). Power Saving

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.20. Clock transition Transition of stop mode, wait mode Transition of normal mode Reset Medium-speed mode (divided-by-8 mode)Interrupt CM10 = “1” All oscillators stopped CPU operation stopped Medium-speed mode (divided-by-8 mode) BCLK : f(XIN)/8 Low-speed mode High-speed mode Main clock is oscillating Sub clock is stopped Main clock is oscillating Sub clock is stopped Main clock is stopped Sub clock is oscillating Main clock is oscillating Sub clock is oscillating Low power dissipation mode High-speed/medium- speed mode Low-speed/low power dissipation mode Normal mode Stop mode Stop mode Stop mode All oscillators stopped All oscillators stopped Wait mode Wait mode Wait mode CPU operation stopped CPU operation stopped Interrupt WAIT instruction Interrupt WAIT instruction Interrupt WAIT instruction CM10 = “1” Interrupt Interrupt CM10 = “1” BCLK : f(XIN)/2 Medium-speed mode (divided-by-2 mode) BCLK : f(XIN)/16 Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/4 Medium-speed mode (divided-by-4 mode) BCLK : f(XIN) BCLK : f(XIN)/8 Medium-speed mode (divided-by-8 mode) CM07 = “0” CM06 = “1” High-speed mode BCLK : f(XIN)/2 Medium-speed mode (divided-by-2 mode) BCLK : f(XIN)/16 Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/4 Medium-speed mode (divided-by-4 mode) BCLK : f(XIN) BCLK : f(XCIN) CM07 = “1” BCLK : f(XCIN) CM07 = “1” Main clock is oscillating Sub clock is oscillating CM07 = “0” (Note 1, 3) CM07 = “0” (Note 1) CM06 = “1” (Note 2) CM07 = “0” (Note 1) CM06 = “0” (Note 3) CM04 = “1” CM07 = “1” (Note 2) CM05 = “1” CM06 = “0” (Notes 1,3) CM06 = “1” (Notes 1, 3) Note 1: Switch clock after oscillation of main clock is sufficiently stable. Note 2: Switch clock after oscillation of sub clock is sufficiently stable. Note 3: Change CM06 after changing CM17 and CM16. Note 4: Transit in accordance with arrow. (Refer to the following for the transition of normal mode.) Power Saving

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Protection The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 1.21 shows the protect register. The values in the processor mode register 0 (address 0004 16), processor mode register 1 (address 000516), system clock control reg- ister 0 (address 000616), system clock control register 1 (address 000716) and port P4 direction register (address 03EA16) can only be changed when the respective bit in the protect register is set to “1”. There- fore, important outputs can be allocated to port P4. If, after “1” (write-enabled) has been written to the port P4 direction register write-enable bit (bit 2 at address 000A 16), a value is written to any address, the bit automatically reverts to “0” (write-inhibited). However, the system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and 1 write-enable bit (bit 1 at 000A16) do not automatically return to “0” after a value has been written to an address. The program must therefore be written to return these bits to “0”. Protect register Symbol Address When reset PRCR 000A 16 XXXXX000 2 Bit name Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : Write-inhibited 1 : Write-enabled PRC1 PRC0 PRC2 Enables writing to processor mode registers 0 and 1 (addresses 000416 and 000516) Function 0 : Write-inhibited 1 : Write-enabled Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) Enables writing to port P4 direction register (address 03EA 16) (Note) 0 : Write-inhibited 1 : Write-enabled W R Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note: Writing a value to an address after “1” is written to this bit returns the bit to “0” . Other bits do not automatically return to “0” and they must therefore be reset by the program. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Figure 1.21. Protect register Protection

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts.

Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction.
Overflow interrupt An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to “1”. The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
BRK interrupt A BRK interrupt occurs when executing the BRK instruction.
INT interrupt An INT interrupt occurs when assigning one of software interrupt numbers 0 through 63 and executing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/O interrupt does. The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is involved. So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts. (1) Special interrupts Special interrupts are non-maskable interrupts.

Reset Reset occurs if an “L” is input to the RESET pin.
DBC interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances.
Watchdog timer interrupt Generated by the watchdog timer.
Single-step interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to “1”. If an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. (2) Peripheral I/O interrupts A peripheral I/O interrupt is generated by one of built-in peripheral functions. The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
Key-input interrupt ___ A key-input interrupt occurs if an “L” is input to the KI pin.
A-D conversion interrupt This is an interrupt that the A-D converter generates.
UART0 and UART1 transmission interrupt These are interrupts that the serial I/O transmission generates.
UART0 and UART1 reception interrupt These are interrupts that the serial I/O reception generates.
Timer A0 interrupt This is an interrupts that timer A0 generates.
Timer B0 and timer B2 interrupt These are interrupts that timer B generates.
Timer X0 to timer X2 interrupt These are interrupts that timer X generates.
INT0 and INT1 interrupt An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Interrupts and Interrupt Vector Tables If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Figure 1.23 shows format for specifying interrupt vector addresses. Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting. Interrupt source Vector table addresses Remarks Address (L) to address (H) Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction Overflow FFFE0 16 to FFFE316 Interrupt on INTO instruction BRK instruction FFFE4 16 to FFFE716 If the vector is filled with FF16, program execution starts from the address shown by the vector in the variable vector table Address match FFFE8 16 to FFFEB16 There is an address-matching interrupt enable bit Single step (Note) FFFEC 16 to FFFEF16 Do not use Watchdog timer FFFF0 16 to FFFF316 DBC (Note) FFFF4 16 to FFFF716 Do not use - FFFF8 16 to FFFFB16 - Reset FFFFC 16 to FFFFF16 Table 1.6. Interrupt and fixed vector address Figure 1.23. Format for specifying interrupt vector addresses Note: Interrupts used for debugging purposes only. /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Mid address/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Low address /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 0 0 0 0 High address /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 0 0 0 0 0 0 0 0 Vector address + 0 Vector address + 1 Vector address + 2 Vector address + 3 LSBMSB

Fixed vector tables The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table 1.6 shows the interrupts assigned to the fixed vector tables and addresses of vector tables.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Table 1.7. Interrupt causes (variable interrupt vector addresses) Software interrupt number Interrupt sourceVector table address Address (L) to address (H) Remarks Cannot be masked by I flag+0 to +3 (Note) BRK instructionSoftware interrupt number 0 +44 to +47 (Note) Software interrupt number 11 +48 to +51 (Note) Software interrupt number 12 +52 to +55 (Note) Software interrupt number 13 +56 to +59 (Note) Software interrupt number 14 +68 to +71 (Note) Software interrupt number 17 +72 to +75 (Note) Software interrupt number 18 +76 to +79 (Note) Software interrupt number 19 +80 to +83 (Note) Software interrupt number 20 +84 to +87 (Note) Software interrupt number 21 +88 to +91 (Note) Software interrupt number 22 +92 to +95 (Note) Software interrupt number 23 +96 to +99 (Note) Software interrupt number 24 +100 to +103 (Note)Software interrupt number 25 +104 to +107 (Note)Software interrupt number 26 +108 to +111 (Note)Software interrupt number 27 +112 to +115 (Note)Software interrupt number 28 +116 to +119 (Note)Software interrupt number 29 +120 to +123 (Note)Software interrupt number 30 +124 to +127 (Note)Software interrupt number 31 +128 to +131 (Note)Software interrupt number 32 +252 to +255 (Note)Software interrupt number 63 to Note : Address relative to address in interrupt table register (INTB). to Key input interrupt A-D UART0 transmit UART0 receive UART1 transmit UART1 receive Timer A0 Timer X0 Timer X1 Timer X2 Timer B0 Timer B1 INT0 INT1 Software interrupt Cannot be masked by I flag

Variable vector tables The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the address the INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 1.7 shows the interrupts assigned to the variable vector tables and addresses of vector tables.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Interrupt Control Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level select bit, and processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indi- cated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are located in the flag register (FLG). Figure 1.24 shows the interrupt control registers.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Figure 1.24. Interrupt control register Symbol Address When reset INTiIC(i=0, 1) 005D 16, 005E16 XX00X000 2 Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines ILVL0 IR POL Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Interrupt priority level select bit Interrupt request bit Polarity select bit Reserved bit 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Always set to “0” ILVL1 ILVL2 Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts. (Note 1) Interrupt control register (Note 2) b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines Bit name FunctionBit symbol W R Symbol Address When reset KUPIC 004D 16 XXXXX000 2 ADIC 004E 16 XXXXX000 2 SiTIC(i=0, 1) 0051 16, 005316 XXXXX000 2 SiRIC(i=0, 1) 0052 16, 005416 XXXXX000 2 TAiIC(i=0) 0055 16 XXXXX000 2 TXiIC(i=0 to 2) 0056 16 to 005816 XXXXX000 2 TBiIC(i=0, 1) 005A 16, 005B16 XXXXX000 2 ILVL0 IR Interrupt priority level select bit Interrupt request bit 0 : Interrupt not requested 1 : Interrupt requested ILVL1 ILVL2Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. (Note 1) Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts. 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Interrupt Enable Flag The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set to “0” after reset. Interrupt Request Bit The interrupt request bit is set to “1” by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The interrupt request bit can also be set to “0” by software. (Do not set this bit to "1"). Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL) Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt priority level to “0” disables the interrupt. Table 1.8 shows the settings of interrupt priority levels and Table 1.9 shows the interrupt levels enabled, according to the contents of the IPL. The following are conditions under which an interrupt is accepted:

interrupt enable flag (I flag) = 1
interrupt request bit = 1
interrupt priority level > IPL The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are independent, and they are not affected by one another. Table 1.9. Interrupt levels enabled according to the contents of the IPL Table 1.8. Settings of interrupt priority levels Interrupt priority level select bit Interrupt priority level Priority order 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Low High b2 b1 b0 Enabled interrupt priority levels 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 4 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled IPL2 IPL1 IPL0 IPL

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Changing the Interrupt Control Register < Program examples > The program examples are described as follow: Example 1: INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. NOP ; Four NOP instructions are required when using HOLD function. NOP FSET I ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. MOV.W MEM, R0 ; Dummy read. FSET I ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG ; Push Flag register onto stack FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. POPC FLG ; Enable interrupts. The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. If changing the interrupt control register using an instruction other than the instructions listed hear, and if an interrupt occurs associated with this register during execution of the instruction, there can be instances in which the interrupt request bit is not set. To avoid this problem, use one of the instruc- tions given below to change the register. Following instructions: AND, OR, BCLR or BSET

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. In the interrupt sequence, the processor carries out the following in sequence given: (1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 00000 16. After this, the corresponding interrupt request bit becomes "0". (2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU. (3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to “0” (the U flag, however, does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed). (4) Saves the content of the temporary register (Note) within the CPU in the stack area. (5) Saves the content of the program counter (PC) in the stack area. (6) Sets the interrupt priority level of the accepted instruction in the IPL. Interrupt Response Time 'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). Figure 1.25 shows the interrupt response time. Instruction Interrupt sequence Instruction in interrupt routine Time Interrupt response time (a) (b) Interrupt request acknowledgedInterrupt request generated (a) Time from interrupt request is generated to when the instruction then under execution is completed. (b) Time in which the instruction sequence is executed. Figure 1.25. Interrupt response time After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. Note: This register cannot be utilized by the user.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Interrupt sources without priority levels Value set in the IPL Watchdog timer Other Not changed Variation of IPL when Interrupt Request is Accepted If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in Table 1.11 is set in the IPL. Table 1.11. Relationship between interrupts without interrupt priority levels and IPL Table 1.10. Time required for executing the interrupt sequence Reset Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction (without wait). Time (b) is as shown in Table 1.10. Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match interrupt or of a single-step interrupt. Note 2: Locate an interrupt vector address in an even address, if possible. Figure 1.26. Time required for executing the interrupt sequence Stack pointer (SP) valueInterrupt vector address 16-bit bus, without wait 8-bit bus, without wait Even Even Odd (Note 2) Odd (Note 2) Even Odd Even Odd 18 cycles (Note 1) 19 cycles (Note 1) 19 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) Indeterminate 123456789 1 0 1 1 12 13 14 15 16 17 18 The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs. Indeterminate SP-2

000016 Indeterminate SP-2 SP-4 vec vec+2 PC

W R

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Saving Registers In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the stack area. First, the processor saves the 4 high-order bits of the program counter, and 4 high-order bits and 8 low- order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 low-order bits of the program counter. Figure 1.27 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM instruction alone can save all the registers except the stack pointer (SP). Figure 1.27. State of stack before and after acceptance of interrupt request Address Content of previous stack Stack area [SP] Stack pointer value before interrupt occurs m m – 1 m – 2 m – 3 m – 4 Stack status before interrupt request is acknowledged Stack status after interrupt request is acknowledged Content of previous stackm + 1 MSB LSB m m – 1 m – 2 m – 3 m – 4 Address Flag register (FLG Content of previous stack Stack area Flag register (FLGH ) Program counter (PCH ) [SP] New stack pointer value Content of previous stackm + 1 MSB LSB Program counter (PC Program counter (PCM )

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Figure 1.28. Operation of saving registers The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer (Note), at the time of acceptance of an interrupt request, is even or odd. If the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Figure 1.28 shows the operation of the saving registers. Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the stack pointer indicated by the U flag. Otherwise, it is the interrupt stack pointer (ISP). (2) Stack pointer (SP) contains odd number [SP] (Odd) [SP] – 1 (Even) [SP] – 2(Odd) [SP] – 3 (Even) [SP] – 4(Odd) [SP] – 5 (Even) Address Sequence in which order registers are saved (2) (1) Finished saving registers in four operations. (3) (4) (1) Stack pointer (SP) contains even number [SP] (Even) [SP] – 1(Odd) [SP] – 2 (Even) [SP] – 3(Odd) [SP] – 4 (Even) [SP] – 5 (Odd) Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. Address Program counter (PCM ) Stack area Flag register (FLGL) Program counter (PCL) Sequence in which order registers are saved (2) Saved simultaneously, all 16 bits (1) Saved simultaneously, all 16 bits Finished saving registers in two operations. Program counter (PCM ) Stack area Flag register (FLGL) Program counter (PCL) Saved simultaneously, all 8 bits Flag register (FLGH ) Program counter (PCH ) Flag register (FLGH ) Program counter (PCH )

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Key Input Interrupt Key Input Interrupt If the direction register of any of P00 to P07 is set for input and a falling edge is input to that port, a key input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. Figure 1.31 shows the block diagram of the key input interrupt. Note that if an “L” level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an interrupt. Figure 1.31. Block diagram of key input interrupt Interrupt control circuit Key input interrupt control register (address 004D16) Key input interrupt request P07/KI7 P06/KI6 P01/KI1 P00/KI0 Port P04-P07 pull-up select bit Port P07 direction register Pull-up transistor Port P07 direction register Port P06 direction register Port P01 direction register Port P00 direction register Pull-up transistor Pull-up transistor Pull-up transistor

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Precautions for Interrupts (1) Reading address 0000016

When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”. Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”. Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 0000016 by software. (2) Setting the stack pointer
The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the stack pointer before accepting an interrupt. Concerning the first instruction immediately after reset, generating any interrupts is prohibited. (3) External interrupt
Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0 and INT1 regardless of the CPU operation clock.
When changing a polarity of pins INT0 and INT1, the interrupt request bit may become "1". Clear the interrupt request bit after changing the polarity. Figure 1.33 shows the switching condition of INT inter- rupt request. Figure 1.33. Switching condition of INT interrupt request (4) Changing interrupt control register See "Changing Interrupt Control Register". Set the interrupt priority level to level 0 (Disable INTi interrupt) Set the polarity select bit Clear the interrupt request bit to “0” Set the interrupt priority level to level 1 to 7 (Enable the accepting of INTi interrupt request) Clear the interrupt enable flag to “0” (Disable interrupt) Set the interrupt enable flag to “1” (Enable interrupt)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Watchdog Timer Watchdog timer control register Symbol Address When reset WDC 000F 16 000XXXXX 2 FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 High-order bit of watchdog timer WDC7 Bit name Prescaler select bit 0 : Divided by 16 1 : Divided by 128 Watchdog timer start register Symbol Address When reset WDTS 000E 16 Indeterminate W R b7 b0 Function The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to “7FFF16” regardless of whatever value is written. Reserved bit Reserved bit Must always be set to “0” Must always be set to “0” 0 0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Figure 1.35. Watchdog timer control and start registers

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Timer There are six 16-bit timers. These timers can be classified by function into timer A (one), timers B (two) and timers X (three). All these timers function independently. Figure 1.36 show the block diagram of timers. Figure 1.36. Timer block diagram TA0 IN TX0 INOUT TB0 IN TB1 IN f1 f8 f32 fc32 1/32 fC32 f32 XIN XCIN TX1 INOUT TX2 INOUT Noise filter Noise filter Noise filter Noise filter Noise filter Noise filter

Event counter mode
Event counter mode
Event counter mode
Timer mode
One-shot mode
PWM mode
Timer mode
One-shot mode
PWM mode
Pulse width measuring mode
Timer mode
One-shot mode
PWM mode
Pulse width measuring mode
Event counter mode
Event counter mode
Event counter mode
Timer mode
One-shot mode
PWM mode
Pulse width measuring mode
Timer mode
Pulse width measuring mode
Timer mode
Pulse width measuring mode Timer A0 Timer X0 Timer X1 Timer X2 Timer B0 Timer B1 Timer A0 Timer X0 Timer X1 Timer X2 Timer B0 Timer B1 Clock prescaler reset flag (bit 7 at address 038116) set to “1” Reset Clock prescaler

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Figure 1.39. Timer A-related registers (2) Timer A0 up/down flag Timer A0 two-phase pulse signal processing select bit Symbol Address When reset UDF 0384

16 XXX0XXX0 2

Up/down flag (Note) Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 TA0UD 0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled When not using the two-phase pulse signal processing function, set the select bit to “0” Symbol Address When reset TABSR 0380 16 000X00002 Count start flag Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Clock devided count start flag Timer B1 count start flag Timer B0 count start flag Timer X2 count start flag Timer X1 count start flag Timer X0 count start flag Timer A0 count start flag0 : Stops counting 1 : Starts counting CDCS TB1S TB0S Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. TX2S TX1S TX0S TA0S Symbol Address When reset TA0 0387 16,038616 Indeterminate b7 b0 b7 b0 (b15) (b8) Timer A0 register (Note 1) W R

Timer mode 0000 16 to FFFF16 Counts an internal count source Function Values that can be set
Event counter mode 0000 16 to FFFF16 Counts pulses from an external source or timer overflow
One-shot timer mode 0000 16 to FFFF16 Counts a one shot width (Note 2)
Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator
Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 16 to FF16(Note 2) (Both high-order and low-order addresses) 000016 to FFFE16 (Note 2) Note 1: Read and write data in 16-bit units. Note 2: Use MOV instruction to write to this register. /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 0 : Stops counting 1 : Starts counting Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note : Use MOV instruction to write to this register.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Figure 1.40. Timer A-related registers (3) Symbol Address When reset CPSRF 0381 16 0XXXXXXX 2 Clock prescaler reset flag Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Clock prescaler reset flag0 : No effect 1 : Prescaler is reset (When read, the value is “0”) CPSR W R Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. TA0TGL Symbol Address When reset TRGSR 0383 16 0016 Timer A0 event/trigger select bit 0 0 : Input on TA0IN is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX2 overflow is selected 1 1 : TX0 overflow is selected Trigger select register Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : Input on TX0INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TX1 overflow is selected 0 0 : Input on TX1INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX0 overflow is selected 1 1 : TX2 overflow is selected 0 0 : Input on TX2INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX1 overflow is selected 1 1 : TA0 overflow is selected Timer X0 event/trigger select bit Timer X1 event/trigger select bit Timer X2 event/trigger select bit W R TA0TGH TX0TGL TX0TGH TX1TGL TX1TGH TX2TGL TX2TGH b1 b0 b3 b2 b5 b4 b7 b6 Note: Set the corresponding port direction register to “0”(input mode). TX0OS TX1OS TA0OS One-shot start flag Symbol Address When reset ONSF 0382 16 XXXX0000 2 Timer A0 one-shot start flag Timer X0 one-shot start flag Timer X1 one-shot start flag Timer X2 one-shot start flag TX2OS Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. W R 1 : Timer start When read, the value is “0” /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Item Specification Count source f 1, f8, f32, fc32 Count operation • Down count

When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingWhen the timer underflows TA0IN pin function Programmable I/O port or gate input TA0OUT pin function Programmable I/O port or pulse output Read from timer Count value can be read out by reading timer A0 register Write to timer • When counting stopped When a value is written to timer A0 register, it is written to both reload register and counter
When counting in progress When a value is written to timer A0 register, it is written to only reload register (Transferred to counter at next reload time) Select function • Gate function Counting can be started and stopped by the TA0IN pin’s input signal
Pulse output function Each time the timer underflows, the TA0OUT pin’s polarity is reversed (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 1.12.) Figure 1.41 shows the timer A0 mode register in timer mode. Table 1.12. Specifications of timer mode Figure 1.41. Timer A0 mode register in timer mode Note 1: Set the corresponding port direction register to “1” (output mode). Note 2: The bit can be “0” or “1”. Note 3: Set the corresponding port direction register to “0” (input mode). Timer A0 mode register Symbol Address When reset TA0MR 0396 16 0016 Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 Operation mode select bit 0 0 : Timer mode b1 b0 TMOD1 TMOD0 MR0 Pulse output function select bit 0 : Pulse is not output (TA0 OUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TA0 OUT pin is a pulse output pin) Gate function select bit0 X (Note 2): Gate function not available (TA0IN pin is a normal port pin) 1 0 : Timer counts only when TA0IN pin is held “L” (Note 3) 1 1 : Timer counts only when TA0IN pin is held “H” (Note 3) b4 b3 MR2 MR1 MR3 0 (Must always be “0” in timer mode) 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 TCK1 TCK0 Count source select bit 000 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Item Specification Count source • External signals input to TA0IN pin (effective edge can be selected by software)

TB1 overflow, TX0 overflow, TX2 overflow Count operation • Up count or down count can be selected by external signal or software
When the timer overflows or underflows, it reloads the reload register con tents before continuing counting (Note) Divide ratio 1/ (FFFF 16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingThe timer overflows or underflows TA0 IN pin function Programmable I/O port or count source input TA0 OUT pin function Programmable I/O port, pulse output, or up/down count select input Read from timer Count value can be read out by reading timer A0 register Write to timer • When counting stopped When a value is written to timer A0 register, it is written to both reload register and counter
When counting in progress When a value is written to timer A0 register, it is written to only reload register (Transferred to counter at next reload time) Select function • Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded to it
Pulse output function Each time the timer overflows or underflows, the TA0OUT pin’s polarity is reversed Note: This does not apply when the free-run function is selected. (2) Event counter mode In this mode, the timer counts an external signal or an internal timer’s overflow. Timer A0 can count a single-phase and a two-phase external signal. Table 1.13 lists timer specifications when counting a single-phase external signal. Figure 1.42 shows the timer A0 mode register in event counter mode. Table 1.14 lists timer specifications when counting a two-phase external signal. Figure 1.43 shows the timer A0 mode register in event counter mode. Table 1.13. Timer specifications in event counter mode (when not processing two-phase pulse signal) Figure 1.42. Timer A0 mode register in event counter mode Timer A0 mode register (When not using two-phase pulse signal processing) Note 1: Set the corresponding port direction register to “1” (output mode). Note 2: This bit is valid when only counting an external signal. Note 3: Set the corresponding port direction register to “0” (input mode). Note 4: When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 0384 16) is set to “1” and event/trigger select bits (addresses 038316) to “00”. Symbol Address When reset TA0MR 0396 16 0016 W R b7 b6 b5 b4 b3 b2 b1 b0 Operation mode select bit 0 1 : Event counter mode b1 b0 TMOD0 MR0 Pulse output function select bit 0 : Pulse is not output (TA0OUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TA0OUT pin is a pulse output pin) Count polarity select bit (Note 2) MR2 MR1 MR3 0 (Must always be “0” in event counter mode) TCK0 Count operation type select bit 010 0 : Counts external signal's falling edge 1 : Counts external signal's rising edge Up/down switching cause select bit 0 : Up/down flag's content 1 : TA iOUT pin's input signal (Note 3) 0 : Reload type 1 : Free-run type Bit symbol Bit name Function RW TCK1 TMOD1 /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Two-phase pulse operation select bit (Note 4) 0 : Normal processing operation 1 : Multiply-by-4 processing operation

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Item Specification Count source • Two-phase pulse signals input to TA0 IN or TA0OUT pin Count operation • Up count or down count can be selected by two-phase pulse signal

When the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (Note) Divide ratio • 1/ (FFFF 16 - n + 1) for up count
1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingTimer overflows or underflows TA0 IN pin function Two-phase pulse input TA0 OUT pin function Two-phase pulse input Read from timer Count value can be read out by reading timer A0 register Write to timer • When counting stopped When a value is written to timer A0 register, it is written to both reload regis- ter and counter
When counting in progress When a value is written to timer A0 register, it is written to only reload regis- ter. (Transferred to counter at next reload time.) Select function • Normal processing operation The timer counts up rising edges or counts down falling edges on the TA0IN pin when input signal on the TA0OUT pin is “H”
Multiply-by-4 processing operation If the phase relationship is such that the TA0IN pin goes “H” when the input signal on the TA0OUT pin is “H”, the timer counts up rising and falling edges on the TA0OUT and TA0IN pins. If the phase relationship is such that the TA0 IN pin goes “L” when the input signal on the TA0OUT pin is “H”, the timer counts down rising and falling edges on the TA0OUT and TA0IN pins. Note: This does not apply when the free-run function is selected. Table 1.14. Timer specifications in event counter mode (when processing two-phase pulse signal) TA0 OUT Up count Up count Up count Down count Down count Down count TA0 IN TA0 OUT TA0 IN Count up all edges Count up all edges Count down all edges Count down all edges

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Figure 1.43. Timer A0 mode register in event counter mode Note: When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 038416) is set to “1”. Also, always be sure to set the event/trigger select bit (addresses 038316) to “00”. Timer A0 mode register (When using two-phase pulse signal processing) Symbol Address When reset TA0MR 0396 16 0016 b7 b6 b5 b4 b3 b2 b1 b0 Operation mode select bit0 1 : Event counter mode b1 b0 TMOD1 TMOD0 MR0 0 (Must always be “0” when using two-phase pulse signal processing) 0 (Must always be “0” when using two-phase pulse signal processing) MR2 MR1 MR3 0 (Must always be “0” when using two-phase pulse signal processing) TCK1 TCK0 010 1 (Must always be “1” when using two-phase pulse signal processing) Bit name Function W R Count operation type select bit Two-phase pulse processing operation select bit (Note) 0 : Reload type 1 : Free-run type 0 : Normal processing operation 1 : Multiply-by-4 processing operation 0 0 1 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Item Specification Count source f 1, f8, f32, fC32 Count operation • The timer counts down

When the count reaches 000016, the timer stops counting after reloading a new count
If a trigger occurs when counting, the timer reloads a new count and restarts counting Divide ratio 1/n n : Set value Count start condition • An external trigger is input
The timer overflows
The one-shot start flag is set (= 1) Count stop condition • A new count is reloaded after the count has reached 000016
The count start flag is reset (= 0) Interrupt request generation timingThe count reaches 000016 TA0 IN pin function Programmable I/O port or trigger input TA0 OUT pin function Programmable I/O port or pulse output Read from timer When timer A0 register is read, it indicates an indeterminate value Write to timer • When counting stopped When a value is written to timer A0 register, it is written to both reload register and counter
When counting in progress When a value is written to timer A0 register, it is written to only reload register (Transferred to counter at next reload time) Table 1.15. Timer specifications in one-shot timer mode Figure 1.44. Timer A0 mode register in one-shot timer mode (3) One-shot timer mode In this mode, the timer operates only once. (See Table 1.15.) When a trigger occurs, the timer starts up and continues operating for a given period. Figure 1.44 shows the timer A0 mode register in one-shot timer mode. Bit name Function Bit symbol Operation mode select bit1 0 : One-shot timer mode b1 b0 TMOD1 TMOD0 MR0 Pulse output function select bit 0 : Pulse is not output (TA0 OUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TA0 OUT pin is a pulse output pin) MR2 MR1 MR3 0 (Must always be “0” in one-shot timer mode) 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 TCK1 TCK0 Count source select bit 100 0 : One-shot start flag is valid 1 : Selected by event/trigger select register Trigger select bit External trigger select bit (Note 2) 0 : Falling edge of TA0IN pin's input signal (Note 3) 1 : Rising edge of TA0IN pin's input signal (Note 3) W R /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Note 1: Set the corresponding port direction register to “1” (output mode). Note 2: Valid only when the TA0IN pin is selected by the event/trigger select bit (addresses 038316). If timer overflow is selected, this bit can be “1” or “0”. Note 3: Set the corresponding port direction register to “0” (input mode). Timer A0 mode register Symbol Address When reset TA0MR 0396 16 0016 b7 b6 b5 b4 b3 b2 b1 b0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A (4) Pulse width modulation (PWM) mode In this mode, the timer outputs pulses of a given width in succession. (See Table 1.16.) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.45 shows the timer A0 mode register in pulse width modulation mode. Figure 1.46 shows the example of how a 16-bit pulse width modulator operates. Figure 1.47 shows the example of how an 8-bit pulse width modulator operates. Figure 1.45. Timer A0 mode register in pulse width modulation mode Table 1.16. Timer specifications in pulse width modulation mode Item Specification Count source f 1, f8, f32, fc32 Count operation • The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)

The timer reloads a new count at a rising edge of PWM pulse and continues counting
The timer is not affected by a trigger that occurs when counting 16-bit PWM • High level width n / fi n : Set value
Cycle time (216-1) / fi fixed 8-bit PWM •High level width n (m+1) / fi n : values set to timer A0 register’s high-order address
Cycle time (28-1) (m+1) / fi m : values set to timer A0 register’s low-order address Count start condition • External trigger is input
The timer overflows
The count start flag is set (= 1) Count stop condition • The count start flag is reset (= 0) 8 bits PWM • Set value of "H" level width is except FF16, 0016 : PWM pulse goes “L”
Set value of "H" level width is FF16, 0016 : Timing that count value goes to 0116 16 bits PWM • Set value of "H" level width is except FFFF16, 000016 : PWM pulse goes “L”
Set value of "H" level width is FFFF16, 000016 : Timing that count value goes to 000116 TA0 IN pin function Programmable I/O port or trigger input TA0 OUT pin function Pulse output Read from timer When timer A0 register is read, it indicates an indeterminate value Write to timer • When counting stopped :When a value is written to timer A0 register, it is written to both reload register and counter
When counting in progress : When a value is written to timer A0 register, it is written to only reload register (Transferred to counter at next reload time) Bit name FunctionBit symbol Operation mode select bit 1 1 : PWM mode b1 b0 TMOD1 TMOD0 MR0 MR2 MR1 MR3 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 TCK1 TCK0 Count source select bit W R 111 1 (Must always be “1” in PWM mode) 16/8-bit PWM mode select bit 0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator Trigger select bit External trigger select bit (Note 1) 0: Falling edge of TA0IN pin's input signal (Note 2) 1: Rising edge of TA0IN pin's input signal (Note 2) 0: Count start flag is valid 1: Selected by event/trigger select register Note 1: Valid only when the TA0 IN pin is selected by the event/trigger select bit (addresses 038316). If timer overflow is selected, this bit can be “1” or “0”. Note 2: Set the corresponding port direction register to “0” (input mode). Note 3: Set the corresponding port direction register to “1” (output mode) when the pulse is output. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines Timer A0 mode register Symbol Address When reset TA0MR 0396 16 0016 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request generation timing Note: When set value of "H" level width is 0016 or 000016, pulse outputs "L" level and inversion value, FF16 or FFFF16 is set to timer.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B Symbol Address When reset CPSRF 0381 16 0XXXXXXX 2 Clock prescaler reset flag Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Clock prescaler reset flag0 : No effect 1 : Prescaler is reset (When read, the value is “0”) CPSR Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. /LiteDiagLines /LiteDiagLines Symbol Address When reset TB0 0391 16, 039016 Indeterminate TB1 0393 16, 039216 Indeterminateb7 b0 b7 b0 (b15) (b8) Timer Bi register (Note) W R

Pulse period / pulse width measurement mode Measures a pulse period or width
Timer mode 0000 16 to FFFF16 Counts the timer's period Function Values that can be set
Event counter mode 0000 16 to FFFF16 Counts external pulses input or a timer overflow Note1: Read and write data in 16-bit units. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Symbol Address When reset TABSR 0380 16 000X00002 Count start flag Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Clock devided count start flag Timer B1 count start flag Timer B0 count start flag Timer X2 count start flag Timer X1 count start flag Timer X0 count start flag Timer A0 count start flag0 : Stops counting 1 : Starts counting CDCS TB1S TB0S Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. TX2S TX1S TX0S TA0S /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines 0 : Stops counting 1 : Starts counting Figure 1.50. Timer B-related registers (2)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B Item Specification Count source f 1, f8, f32, fC32 Count operation • Counts down

When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingThe timer underflows TBiIN pin function Programmable I/O port Read from timer Count value is read out by reading timer Bi register Write to timer • When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter
When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 1.17.) Figure 1.51 shows the timer Bi mode register in timer mode. Table 1.17. Timer specifications in timer mode Timer Bi mode register Symbol Address When reset TBiMR(i=0, 1) 039B 16 to 039C16 00XX0000 2 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Operation mode select bit0 0 : Timer mode b1 b0 TMOD1 TMOD0 MR0 Invalid in timer mode Can be “0” or “1”MR1 MR3 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 TCK1 TCK0 Count source select bit Invalid in timer mode. In an attempt to write to this bit, write “0”. The value, if read in timer mode, turns out to be indeterminate. b7 b6 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. Figure 1.51. Timer Bi mode register in timer mode

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B Item Specification Count source • External signals input to TBi IN pin

Effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software Count operation • Counts down
When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingThe timer underflows TBiIN pin function Count source input Read from timer Count value can be read out by reading timer Bi register Write to timer • When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter
When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) (2) Event counter mode In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.18.) Figure 1.52 shows the timer Bi mode register in event counter mode. Table 1.18. Timer specifications in event counter mode Figure 1.52. Timer Bi mode register in event counter mode Timer Bi mode register Symbol Address When reset TBiMR(i=0, 1) 039B 16 to 039C16 00XX0000 2 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines Operation mode select bit 0 1 : Event counter mode b1 b0 TMOD1 TMOD0 MR0 Count polarity select bit (Note 1) MR1 MR3 Invalid in event counter mode. In an attempt to write to this bit, write “0”. The value, if read in event counter mode, turns out to be indeterminate. TCK1 TCK0 0 0 : Counts external signal's falling edges 0 1 : Counts external signal's rising edges 1 0 : Counts external signal's falling and rising edges 1 1 : Inhibited b3 b2 Note 1: Valid only when input from the TBiIN pin is selected as the event clock. If timer's overflow is selected, this bit can be “0” or “1”. Note 2: Set the corresponding port direction register to “0” (input mode). Invalid in event counter mode. Can be “0” or “1”. Event clock select 0 : Input from TBiIN pin (Note 2) 1 : TBj overflow ( j = 1 when i = 0, j = 0 when i = 1) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Figure 1.58. Timer X-related registers (2) Symbol Address When reset TABSR 0380 16 000X00002 Count start flag Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Clock devided count start flag Timer B1 count start flag Timer B0 count start flag Timer X2 count start flag Timer X1 count start flag Timer X0 count start flag Timer A0 count start flag0 : Stops counting 1 : Starts counting CDCS TB1S TB0S Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. TX2S TX1S TX0S TA0S Symbol Address When reset TX0 0389 16,038816 Indeterminate TX1 038B 16,038A16 Indeterminate TX2 038D 16,038C16 Indeterminate b7 b0 b7 b0 (b15) (b8) Timer Xi register (Note 1) W R

Timer mode 0000 16 to FFFF16 Counts an internal count source Function Values that can be set
Event counter mode 0000 16 to FFFF16 Counts pulses from an external source or timer overflow
One-shot timer mode 0000 16 to FFFF16 Counts a one shot width (Note 2)
Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator
Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 16 to FF16(Note 2) (High-order addresses) 0016 to FF16 (Note 2) (Low-order addresses) 000016 to FFFE16 (Note 2) Note 1: Read and write data in 16-bit units. Note 2: Use MOV instruction to write to this register. /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 0 : Stops counting 1 : Starts counting
Pulse period / pulse width measurement mode Measures a pulse period or width /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Figure 1.59. Timer X-related registers (3) Symbol Address When reset CPSRF 0381 16 0XXXXXXX 2 Clock prescaler reset flag Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Clock prescaler reset flag0 : No effect 1 : Prescaler is reset (When read, the value is “0”) CPSR W R Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. TA0TGL Symbol Address When reset TRGSR 0383 16 0016 Timer A0 event/trigger select bit 0 0 : Input on TA0IN is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX2 overflow is selected 1 1 : TX0 overflow is selected Trigger select register Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : Input on TX0INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TX1 overflow is selected 0 0 : Input on TX1INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX0 overflow is selected 1 1 : TX2 overflow is selected 0 0 : Input on TX2INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX1 overflow is selected 1 1 : TA0 overflow is selected Timer X0 event/trigger select bit Timer X1 event/trigger select bit Timer X2 event/trigger select bit W R TA0TGH TX0TGL TX0TGH TX1TGL TX1TGH TX2TGL TX2TGH b1 b0 b3 b2 b5 b4 b7 b6 Note: Set the corresponding port direction register to “0”(input mode). TX0OS TX1OS TA0OS One-shot start flag Symbol Address When reset ONSF 0382 16 XXXX0000 2 Timer A0 one-shot start flag Timer X0 one-shot start flag Timer X1 one-shot start flag Timer X2 one-shot start flag TX2OS Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. W R 1 : Timer start When read, the value is “0”/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Item Specification Count source f 1, f8, f32, fC32 Count operation • Down count

When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingWhen the timer underflows TXiINOUT pin function Programmable I/O port, gate input or pulse output Read from timer Count value can be read out by reading timer Xi register Write to timer • When counting stopped When a value is written to timer Xi register, it is written to both reload register and counter
When counting in progress When a value is written to timer Xi register, it is written to only reload register (Transferred to counter at next reload time) Select function • Gate function Counting can be started and stopped by the TXiINOUT pin’s input signal
Pulse output function Each time the timer underflows, the TXiINOUT pin’s polarity is reversed (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 1.20.) Figure 1.60 shows the timer Xi mode register in timer mode. Table 1.20. Specifications of timer mode Figure 1.60. Timer Xi mode register in timer mode Note 1: Set the corresponding port direction register to “1” (output mode). Gate function cannot be selected when pulse output function is selected. Note 2: The bit can be “0” or “1”. Note 3: Set the corresponding port direction register to “0” (input mode). Pulse output function cannot be selected when gate function is selected. Timer Xi mode register Symbol Address When reset TXiMR(i = 0 to 2) 0397 16 to 039916 0016 Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 Operation mode select bit 0 0 : Timer mode b1 b0 TMOD1 TMOD0 MR0 Pulse output function select bit 0 : Pulse is not output (TXi INOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TXi INOUT pin is a pulse output pin) Gate function select bit0 X (Note 2): Gate function not available (TXiINOUT pin is a normal port pin) 1 0 : Timer counts only when TXiINOUT pin is held “L” (Note 3) 1 1 : Timer counts only when TXiINOUT pin is held “H” (Note 3) b4 b3 MR2 MR1 MR3 0 (Must always be fixed to “0” in timer mode) 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 TCK1 TCK0 Count source select bit 000 /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Item Specification Count source • External signals input to TXiINOUT pin (effective edge can be selected by software)

TB1 overflow, TA0 overflow, TXi overflow Count operation • Down count
When the timer underflows, it reloads the reload register contents before continuing counting (Note) Divide ratio 1/ (n + 1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingThe timer underflows TXiINOUT pin function Programmable I/O port, count source input or pulse output Read from timer Count value can be read out by reading timer Xi register Write to timer • When counting stopped When a value is written to timer Xi register, it is written to both reload register and counter
When counting in progress When a value is written to timer Xi register, it is written to only reload register (Transferred to counter at next reload time) Select function • Free-run count function Even when the timer underflows, the reload register content is not reloaded to it
Pulse output function Each time the timer underflows, the TXiINOUT pin’s polarity is reversed Note: This does not apply when the free-run function is selected. (2) Event counter mode In this mode, the timer counts an external signal or an internal timer’s overflow. (See Table 1.21.) Figure 1.61 shows the timer Xi mode register in event counter mode. Table 1.21. Timer specifications in event counter mode (when not processing two-phase pulse signal) Figure 1.61. Timer Xi mode register in event counter mode Timer Xi mode register Note 1: Count source is selected by event/trigger select bit(address 038316) in event counter mode. Note 2: Set the corresponding port direction register to “1” (output mode). TXiINOUT pin input is not selected as count source when pulse output function is selected. Note 3: This bit is valid when only counting an external signal. Symbol Address When reset TXiMR(i = 0 to 2) 039716 to 039916 0016 W R b7 b6 b5 b4 b3 b2 b1 b0 Operation mode select bit 0 1 : Event counter mode (Note 1) b1 b0 TMOD0 MR0 Pulse output function select bit 0 : Pulse is not output (TXiINOUT pin is a normal port pin) 1 : Pulse is output (Note 2) (TXiINOUT pin is a pulse output pin) Count polarity select bit (Note 3) MR2 MR1 MR3 0 (Must always be “0” in event counter mode) TCK0 Count operation type select bit 010 0 : Counts external signal's falling edge 1 : Counts external signal's rising edge 0 : Reload type 1 : Free-run type Bit symbol Bit name Function RW TCK1 TMOD1 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Invalid in event counter mode. Can be “0” or “1”. Invalid in event counter mode. Can be “0” or “1”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Item Specification Count source f 1, f8, f32, fC32 Count operation • The timer counts down

When the count reaches 000016, the timer stops counting after reloading a new count
If a trigger occurs when counting, the timer reloads a new count and restarts counting Divide ratio 1/n n : Set value Count start condition • An external trigger is input
The timer overflows
The one-shot start flag is set (= 1) Count stop condition • A new count is reloaded after the count has reached 000016
The count start flag is reset (= 0) Interrupt request generation timingThe count reaches 000016 TXiINOUT pin function Programmable I/O port, trigger input or pulse output Read from timer When timer Xi register is read, it indicates an indeterminate value Write to timer • When counting stopped When a value is written to timer Xi register, it is written to both reload register and counter
When counting in progress When a value is written to timer Xi register, it is written to only reload register (Transferred to counter at next reload time) Table 1.22. Timer specifications in one-shot timer mode Figure 1.62. Timer Xi mode register in one-shot timer mode (3) One-shot timer mode In this mode, the timer operates only once. (See Table 1.22.) When a trigger occurs, the timer starts up and continues operating for a given period. Figure 1.62 shows the timer Xi mode register in one-shot timer mode. Bit name Function Bit symbol Operation mode select bit 1 0 : One-shot timer mode or pulse period / pulse width measurement mode b1 b0 TMOD1 TMOD0 MR0 Pulse output function select bit 0 : Pulse is not output (TXi INOOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TXi INOOUT pin is a pulse output pin) MR2 MR1 MR3 0 (Must always be “0” in one-shot timer mode) 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 TCK1 TCK0 Count source select bit 100 0 : One-shot start flag is valid 1 : Selected by event/trigger select register (Note 4) Trigger select bit External trigger select bit (Note 2) 0 : Falling edge of TXiINOOUT pin's input signal (Note 3) 1 : Rising edge of TXiINOOUT pin's input signal (Note 3) W R /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Note 1: Set the corresponding port direction register to “1” (output mode). External trigger cannot be selected as count start condition when pulse output function is selected. Note 2: Valid only when the TXiINOUT pin is selected by the event/trigger select bit (addresses 038316). If timer overflow is selected, this bit can be “1” or “0”. Note 3: Set the corresponding port direction register to “0” (input mode). Note 4: Pulse output function cannot be selected when TXiINOUT pin is selected by the event/trigger select bit (addresses 038316). Timer Xi mode register Symbol Address When reset TXiMR(i = 0 to 2) 0397 16 to 039916 0016 b7 b6 b5 b4 b3 b2 b1 b0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Item Specification f1, f8, f32, fC32

Down counts (operating as an 8-bit or a 16-bit pulse width modulator)
The timer reloads a new count at a rising edge of PWM pulse and continues counting
The timer is not affected by a trigger that occurs when counting
"H" level width n / fi n : Set value
Cycle time (216-1) / fi fixed
"H" level width n (m+1)/ fi n:values set to timer Xi register’s high-order address
Cycle time (28-1) (m+1) / fi m : values set to timer Xi register’s low-order address
The timer overflows
The count start flag is set (= 1)
The count start flag is reset (= 0)
Set value of "H" level width is except FF16, 0016 : PWM pulse goes “L”
Set value of "H" level width is FF16, 0016 : Timing that count value goes to 0116
Set value of "H" level width is except FFFF16, 000016 : PWM pulse goes “L”
Set value of "H" level width is FFFF16, 000016 : Timing that count value goes to 000116 Pulse output When timer Xi register is read, it indicates an indeterminate value
When counting stopped When a value is written to timer Xi register, it is written to both reload register and counter
When counting in progress When a value is written to timer Xi register, it is written to only reload register (Transferred to counter at next reload time) (5) Pulse width modulation (PWM) mode In this mode, the timer outputs pulses of a given width in succession. (See Table 1.24.) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.66 shows the timer Xi mode register in pulse width modulation mode. Figure 1.67 shows the example of how a 16-bit pulse width modulator operates. Figure 1.68 shows the example of how an 8-bit pulse width modulator operates. Figure 1.66. Timer Xi mode register in pulse width modulation mode Table 1.24. Timer specifications in pulse width modulation mode Bit name FunctionBit symbol Operation mode select bit 1 1 : PWM mode b1 b0 TMOD1 TMOD0 MR0 MR2 MR1 MR3 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 TCK1 TCK0 Count source select bit W R 111 1 (Must always be “1” in PWM mode) 16/8-bit PWM mode select bit 0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator Trigger select bit 0: Count start flag is valid 1: Selected by event/trigger select register Note 1: TXiINOUT pin inout cannot be selected by the event/trigger select bit(addresses 038316). Note 2: Set the corresponding port direction register to “1” (output mode). /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Timer Xi mode register Symbol Address When reset TXiMR(i = 0 to 2) 039716 to 039916 0016 b7 b6 b5 b4 b3 b2 b1 b0 Invalid in PWM mode. Can be “0” or “1”. (Note 1) Count source Count operation 16-bit PWM 8-bit PWM Count start condition Count stop condition 8 bits PWM 16 bits PWM TXiINOUT pin function Read from timer Write to timer Interrupt request generation timing Note: When set value of "H" level width is 0016 or 000016, pulse outputs "L" level and inversion value, FF16 or FFFF16 is set to timer.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.70. Block diagram of transmit/receive unit SP SP PAR 2SP 1SP UART UART (7 bits) UART (8 bits) UART (7 bits) UART (9 bits) Clock synchronous type Clock synchronous type TxDi UARTi transmit register PAR enabled PAR disabled D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 SP: Stop bit PAR: Parity bit UARTi transmit buffer register MSB/LSB conversion circuit UART (8 bits) UART (9 bits) Clock synchronous type UARTi receive buffer register UARTi receive register 2SP 1SP PAR enabled PAR disabled UART UART (7 bits)UART (9 bits) Clock synchronous type Clock synchronous type UART (7 bits) UART (8 bits) RxDi Clock synchronous type UART (8 bits) UART (9 bits) Data bus low-order bits MSB/LSB conversion circuit D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0D 80000000 SP SP PAR “0” Data bus high-order bits Note: UART1 cannot be used in clock synchronous serial I/O.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O Figure 1.71. Serial I/O-related registers (1) UARTi bit rate generator (Note 1, 2) b0 Symbol Address When reset U0BRG 03A1 16 Indeterminate U1BRG 03A9 16 Indeterminate Function Assuming that set value = n, BRGi divides the count source by n + 1 0016 to FF16 Values that can be set W R /LiteDiagLines b7 b0 (b15) (b8) b7 b0 UARTi transmit buffer register (Note) Function Transmit data Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Symbol Address When reset U0TB 03A3 16, 03A216 Indeterminate U1TB 03AB 16, 03AA16 Indeterminate W R /LiteDiagLines (b15) Symbol Address When reset U0RB 03A7 16, 03A616 Indeterminate U1RB 03AF 16, 03AE16 Indeterminate b7 b0 (b8) b7 b0 UARTi receive buffer register Function (During UART mode) Function (During clock synchronous serial I/O mode) Bit nameBit symbol 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found Note: Bits 15 through 12 are set to “0” when the receive enable bit is set to “0”. (Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the lower byte of the UARTi receive buffer register (addresses 03A6 16, and 03AE16) is read out. Invalid Invalid Invalid OER FER PER SUM Overrun error flag (Note) Framing error flag (Note) Parity error flag (Note) Error sum flag (Note) 0 : No overrun error 1 : Overrun error found 0 : No overrun error 1 : Overrun error found Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Receive data W R Receive data /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Note : Use MOV instruction to write to this register. Note 1: Write a value to this register while transmit/receive halts. Note 2: Use MOV instruction to write to this register.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.72. Serial I/O-related registers (2) UARTi transmit/receive mode register Symbol Address When reset UiMR(i=0,1) 03A0 16, 03A816 0016 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol W R Must be fixed to 001 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited b2 b1 b0 CKDIR SMD1 SMD0 Serial I/O mode select bit (Note 1) SMD2 Internal/external clock select bit (Note 2) STPS PRY PRYE SLEP Parity enable bit 0 : Internal clock (Note 3) 1 : External clock (Note 4) Stop bit length select bit Odd/even parity select bit Sleep select bit 0 : One stop bit 1 : Two stop bits 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited b2 b1 b0 0 : Internal clock (Note 3) 1 : External clock (Note 4) Invalid Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity Invalid Invalid Must always be “0” Function (During UART mode) Function (During clock synchronous serial I/O mode) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines UARTi transmit/receive control register 0 Symbol Address When reset UiC0(i=0,1) 03A4 16, 03AC16 0816 b7 b6 b5 b4 b3 b2 b1 b0 Function (During UART mode) W R Function (Note) (During clock synchronous serial I/O mode) TXEPT CLK1 CLK0 NCH CKPOL BRG count source select bit Transmit register empty flag 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge CLK polarity select bit Data output select bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : fc is selected b1 b0 0 : LSB first 1 : MSB first 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open-drain output UFORM Transfer format select bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : fc is selected b1 b0 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output Must always be “0” Bit nameBit symbol Must always be “0” Note: UART1 cannot be used in clock synchronous serial I/O. /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Note 1: UART1 cannot be used in clock synchronous serial I/O. Note 2: UART1 can use only internal clock. Must set this bit to “1”. Note 3: Set the corresponding port direction register to “1” (output mode). Note 4: Set the corresponding port direction register to “0” (input mode). Set this bit to “0”. Set this bit to “1”. 1 0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O Figure 1.73. Serial I/O-related registers (3) UARTi transmit/receive control register 1 Symbol Address When reset UiC1(i=0,1) 03A5 16,03AD 16 0216 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol Function (During UART mode) Function (Note 1) (During clock synchronous serial I/O mode) TE TI RE RI Transmit enable bit Receive enable bit (Note 2) Receive complete flag Transmit buffer empty flag 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : No data present in receive buffer register 1 : Data present in receive buffer register Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. Note 1: UART1 cannot be used in clock synchronous serial I/O. Note 2: When using multiple pins to output the transfer clock, the following requirements must be met:

UART0 internal/external clock select bit (bit 3 at address 03A016) = “0”. UART transmit/receive control register 2 Symbol Address When reset UCON 03B0 16 XX000000 2 b7 b6 b5 b4 b3 b2 b1 b0 Bit name Bit symbol Function (During UART mode) Function (During clock synchronous serial I/O mode) CLKMD0 CLKMD1 UART0 transmit interrupt cause select bit UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enable Set this bit to “0”. CLK/CLKS select bit 0 UART1 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Normal mode (CLK output is CLK0 only) 1 : Transfer clock output from multiple pins function selected 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) Must always be “0” U0IRS U1IRS U0RRM CLK/CLKS select bit 1 (Note 2) Valid when bit 5 = “1” 0 : Clock output to CLK1 1 : Clock output to CLKS1 Note 1: UART1 cannot be used in clock synchronous serial I/O. Note 2: If you are using clock asynchronous serial I/O mode, you can enable 'receive enable bit' when RxD port input is “H”. If RxD port input is “L” and you have enabled 'receive enable bit' , then receive operation starts immediately. W R /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines W R /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines Set this bit to “0”. Must always be “0” Must always be “0” Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) Clock synchronous serial I/O mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. (See Table 1.25.) Figure 1.65 shows the UART0 transmit/receive mode register. Table 1.25. Specifications of clock synchronous serial I/O mode Specification

Transfer data length: 8 bits
When internal clock is selected (bit 3 at address 03A016 = “0”) : fi/ 2(n+1) (Note 1) fi = f1, f8, f32, fc
When external clock is selected (bit 3 at address 03A016 = “1”) : Input from CLK0 pin
To start transmission, the following requirements must be met: _ Transmit enable bit (bit 0 at address 03A516) = “1” _ Transmit buffer empty flag (bit 1 at addresses 03A516) = “0”
Furthermore, if external clock is selected, the following requirements must also be met: _ CLK0 polarity select bit (bit 6 at address 03A416) = “0”: CLK0 input level = “H” _ CLK0 polarity select bit (bit 6 at address 03A416) = “1”: CLK0 input level = “L”
To start reception, the following requirements must be met: _ Receive enable bit (bit 2 at address 03A516) = “1” _ Transmit enable bit (bit 0 at address 03A516) = “1” _ Transmit buffer empty flag (bit 1 at address 03A516) = “0”
Furthermore, if external clock is selected, the following requirements must also be met: _ CLK0 polarity select bit (bit 6 at address 03A416) = “0”: CLK0 input level = “H” _ CLK0 polarity select bit (bit 6 at address 03A416) = “1”: CLK0 input level = “L”
When transmitting _ Transmit interrupt cause select bit (bit 0 at address 03B016) = “0”: Interrupts re- quested when data transfer from UART0 transfer buffer register to UART0 transmit register is completed _ Transmit interrupt cause select bit (bit 0 at address 03B016) = “1”: Interrupts re- quested when data transmission from UART0 transfer register is completed
When receiving _ Interrupts requested when data transfer from UART0 receive register toUART0 receive buffer register is completed
Overrun error (Note 2) This error occurs when the next data is ready before contents of UART0receive buffer register are read out
CLK polarity selection Whether transmit data is output/input at the rising edge or falling edge of the trans- fer clock can be selected
LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected
Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register
Transfer clock output from multiple pins selection UART0 transfer clock can be chosen by software to be output from one of the two pins set Clock synchronous serial I/O mode Item Transfer data format Transfer clock Transmission start condition Reception start conditio Interrupt request generation timing Error detection Select function Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator. Note 2: If an overrun error occurs, the UART0 receive buffer will have the next data written in. Note also that the UART0 receive interrupt request bit does not change.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O Figure 1.74. UART0 transmit/receive mode register in clock synchronous serial I/O mode Clock synchronous serial I/O mode Symbol Address When reset U0MR 03A0 16 0016 CKDIR UART0 transmit/receive mode registers Internal/external clock select bit STPS PRY PRYE SLEP 0 : Internal clock (Note 1) 1 : External clock (Note 2) Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 0 (Must always be “0” in clock synchronous serial I/O mode) 010 SMD0 SMD1 SMD2 Serial I/O mode select bit 0 0 1 : Clock synchronous serial I/O mode b2 b1 b0 Invalid in clock synchronous serial I/O mode /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Note 1: Set the corresponding port direction register to “1” (output mode). Note 2: Set the corresponding port direction register to “0” (input mode). Table 1.26 lists the functions of the input/output pins during clock synchronous serial I/O mode. Note that for a period from when the UART0 operation mode is selected to when transfer starts, the TxD0 pin outputs a “H”. (If the N-channel open-drain is selected, this pin is in floating state.) Table 1.26. Input/output pin functions in clock synchronous serial I/O mode Pin name Function Method of selection TxD0 (P50) Serial data output Serial data input Transfer clock output Transfer clock input Port P50 direction register (bit 0 at address 03EB16)= “1” (Outputs dummy data when performing reception only) RxD0 (P51) CLK0 (P52) Internal/external clock select bit (bit 3 at address 03A016) = “0” Internal/external clock select bit (bit 3 at address 03A016) = “1” Port P52 direction register (bit 2 at address 03EB16) = “0” Port P51 direction register (bit 1 at address 03EB16)= “0” (Can be used as an input port when performing transmission only)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.75. Typical transmit/receive timings in clock synchronous serial I/O mode

Example of transmit timing (when internal clock is selected)
Example of receive timing (when external clock is selected) Clock synchronous serial I/O mode Tc = TCLK = 2(n + 1) / fi fi: frequency of BRG0 count source (f1, f8, f32, fc) n: value set to BRG0 Transfer clock Transmit enable bit (TE) Transmit buffer empty flag (Tl) CLK0 TxD0 Transmit register empty flag (TXEPT) “0” “1” “0” “1” “0” “1” The above timing applies to the following settings:
Internal clock is selected.
CLK polarity select bit = “0”.
Transmit interrupt cause select bit = “0”. Transmit interrupt request bit (IR) “0” “1” 1 / fEXT Dummy data is set in UART0 transmit buffer register Transmit enable bit (TE) Transmit buffer empty flag (Tl) CLK0 RxD0 Receive complete flag (Rl) “0” “1” “0” “1” “0” “1” Receive enable bit (RE) “0” “1” Receive data is taken in Transferred from UART0 transmit buffer register to UART0 transmit register Read out from UART0 receive buffer register The above timing applies to the following settings:
External clock is selected.
CLK polarity select bit = “0”. f EXT : frequency of external clock Transferred from UART0 receive register to UART0 receive buffer register Receive interrupt request bit (IR)“0” “1” D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 Shown in ( ) are bit symbols. Meet the following conditions are met when the CLK input before data reception = “H”
Transmit enable bit “1”
Receive enable bit “1”
Dummy data write to UART0 transmit buffer register Shown in ( ) are bit symbols. Cleared to “0” when interrupt request is accepted, or cleared by software Tc TCLK Stopped pulsing because transfer enable bit = “0” Data is set in UART0 transmit buffer register Transferred from UART0 transmit buffer register to UART0 transmit register Cleared to “0” when interrupt request is accepted, or cleared by software D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (c) Transfer clock output from multiple pins function This function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.78.) The multiple pins function is valid only when the internal clock is selected for UART0. Figure 1.78. The transfer clock output from the multiple pins function usage (d) Continuous receive mode If the continuous receive mode enable bit (bits 2 and 3 at address 03B016) is set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. Clock synchronous serial I/O mode Microcomputer TXD 0 (P50) CLKS (P53) CLK 0 (P52) IN CLK IN CLK Note: This applies when the internal clock is selected and transmission is performed only in clock synchronous serial I/O mode.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O Item Specification

Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
Start bit: 1 bit
Parity bit: Odd, even, or nothing as selected
Stop bit: 1 bit or 2 bits as selected
When internal clock is selected (bit 3 at addresses 03A016, 03A816 = “0”) : fi/16(n+1) (Note 1) fi = f1, f8, f32, fC
When external clock is selected (bit 3 at addresses 03A016=“1”) : fEXT /16(n+1) (Note 1) (Note 2)
To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 at addresses 03A516, 03AD16) = “1” - Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”
To start reception, the following requirements must be met: - Receive enable bit (bit 2 at addresses 03A516, 03AD16) = “1” - Start bit detection
When transmitting - Transmit interrupt cause select bits (bits 0,1 at address 03B016) = “0”: Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed - Transmit interrupt cause select bits (bits 0, 1 at address 03B016) = “1”: Interrupts requested when data transmission from UARTi transfer register is completed
When receiving - Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed
Overrun error (Note 3) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out
Framing error This error occurs when the number of stop bits set is not detected
Parity error This error occurs when if parity is enabled, the number of 1’s in parity and character bits does not match the number of 1’s set
Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
Sleep mode selection This mode is used to transfer data to and from one of multiple slave micro- computers (2) Clock asynchronous serial I/O (UART) mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer Table 1.27. Specifications of UART Mode Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UART bit rate generator. Note 2: fEXT is input from the CLK0 pin. Since UART1 does not have this pin, cannot select external clock. Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit does not change. Clock asynchronous serial I/O (UART) mode Transfer data format Transfer clock Transmission start condition Reception start condi- tion Interrupt request gen- eration timing Error detection Select function

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O Figure 1.79. UARTi transmit/receive mode register in UART mode Clock asynchronous serial I/O (UART) mode Symbol Address When reset UiMR(i=0,1) 03A0 16, 03A816 0016 CKDIR UARTi transmit / receive mode registers Internal / external clock select bit (Note 1) STPS PRY PRYE SLEP 0 : Internal clock (Note 2) 1 : External clock (Note 3) Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 SMD0 SMD1 SMD2 Serial I/O mode select bitb2 b1 b0 0 : One stop bit 1 : Two stop bits 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity Stop bit length select bit Odd / even parity select bit Parity enable bit Sleep select bit /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Note 1: UART1 can use only internal clock. Must set this bit to “1”. Note 2: Set the corresponding port direction register to “1” (output mode). Note 3: Set the corresponding port direction register to “0” (input mode). Table 1.28 lists the functions of the input/output pins during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”. (If the N- channel open-drain is selected, this pin is in floating state.) Table 1.28. Input/output pin functions in UART mode Pin name Function Method of selection TxDi (P50, P40) Serial data output Serial data input Programmable I/O port Transfer clock input RxDi (P51, P42) CLK0 (P52) Internal/external clock select bit (bit 3 at address 03A016) = “0” Internal/external clock select bit (bit 3 at address 03A016) = “1” Port P51 and P42 direction register (bit 1 at address 03EB16, bit 2 at address 03EA16)= “0” (Can be used as an input port when performing transmission only) Port P51 and P42 direction register (bit 0 at address 03EB16, bit 0 at address 03EA16)= “1” (Can be used as an input port when performing reception only)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O

Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) Figure 1.80. Typical transmit timings in UART mode Clock asynchronous serial I/O (UART) mode Transmit enable bit(TE) Transmit buffer empty flag(TI) Transmit register empty flag (TXEPT) Start bit Parity bit TxDi The above timing applies to the following settings :
Parity is enabled.
One stop bit.
Transmit interrupt cause select bit = “1”. “1” “0” “1” “0” “1” Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32, fc) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Transmit interrupt request bit (IR)“0” “1” Cleared to “0” when interrupt request is accepted, or cleared by software Transmit enable bit(TE) Transmit buffer empty flag(TI) TxDi Transmit register empty flag (TXEPT) “0” “1” “0” “1” “0” “1” The above timing applies to the following settings :
Parity is disabled.
Two stop bits.
Transmit interrupt cause select bit = “0”. Transfer clock Tc Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Transmit interrupt request bit (IR)“0” “1” Shown in ( ) are bit symbols. Shown in ( ) are bit symbols. Tc Transfer clock D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7SP ST P SP D 0 D 1ST Stopped pulsing because transmit enable bit = “0”Stop bit Transferred from UARTi transmit buffer register to UARTi transmit register Start bit Data is set in UARTi transmit buffer register D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST SPD 8 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST D 8 D 0 D 1STSP SP Transferred from UARTi transmit buffer register to UARTi transmit register Stop bit Stop bit Data is set in UARTi transmit buffer register.“0” SP Cleared to “0” when interrupt request is accepted, or cleared by software

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O

Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) Figure 1.81. Typical receive timing in UART mode (a) Sleep mode This mode is used to transfer data between specific microcomputers among multiple microcomputers connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses 03A0 16, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”. Clock asynchronous serial I/O (UART) mode D 0Start bit Sampled “L” Receive data taken in BRGi count source Receive enable bit RxDi Transfer clock Receive complete flag Stop bit “1” “0” “0” “1” The above timing applies to the following settings :
Parity is disabled.
One stop bit. Receive interrupt request bit “0” “1” Transferred from UARTi receive register to UARTi receive buffer register Reception triggered when transfer clock is generated by falling edge of start bit D 7D 1 Cleared to “0” when interrupt request is accepted, or cleared by software

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter Item Performance Method of A-D conversion Successive approximation (capacitive coupling amplifier) Analog input voltage (Note 1)0V to AVCC (VCC ) Operating clock φAD (Note 2)VCC = 5V f AD , divide-by-2 of fAD , divide-by-4 of fAD , fAD =f(XIN) VCC = 3V divide-by-2 of fAD , divide-by-4 of fAD , fAD =f(XIN) Resolution 8-bit or 10-bit (selectable) Absolute precision V CC = 5V • Without sample and hold function ±3LSB

With sample and hold function (8-bit resolution) ±2LSB
With sample and hold function (10-bit resolution) ±3LSB VCC = 3V • Without sample and hold function (8-bit resolution) ±2LSB Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 Analog input pins 8 pins (AN 0 to AN7) + 5 pins (AN50 to AN54) A-D conversion start condition• Software trigger A-D conversion starts when the A-D conversion start flag changes to “1” Conversion speed per pin • Without sample and hold function 8-bit resolution: 49 φAD cycles, 10-bit resolution: 59 φAD cycles
With sample and hold function 8-bit resolution: 28 φAD cycles, 10-bit resolution: 33 φAD cycles A-D Converter The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P60 to P67, and P50 to P54 also function as the analog signal input pins. The direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D7 16) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF ) when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from VREF , reducing the power dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF . The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses. Table 1.29 shows the performance of the A-D converter. Figure 1.82 shows the block diagram of the A-D converter, and Figures 1.83 and 1.84 show the A-D converter-related registers. Note 1: Does not depend on use of sample and hold function. Note 2: Without sample and hold function, set the φAD frequency to 250kHz min. With the sample and hold function, set the φAD frequency to 1MHz min. Table 1.29. Performance of A-D converter

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter Figure 1.82. Block diagram of A-D converter φAD fAD A-D conversion rate selection (03C116, 03C016) (03C316, 03C216) (03C516, 03C416) (03C716, 03C616) (03C916, 03C816) (03CB16, 03CA16) (03CD16, 03CC16) (03CF16, 03CE16) CKS1=1 CKS0=0 A-D register 0(16) A-D register 1(16) A-D register 2(16) A-D register 3(16) A-D register 4(16) A-D register 5(16) A-D register 6(16) A-D register 7(16) Resistor ladder Successive conversion register A-D control register 0 (address 03D616) A-D control register 1 (address 03D716) Vref VIN Data bus high-order Data bus low-order V REF VCUT=0 AV SS VCUT=1 CKS0=1 CKS1=0 Decoder Comparator Addresses P60/AN0 P61/AN1 P62/AN2 P63/AN3 P65/AN5 P66/AN6 P67/AN7 P64/AN4 CH2,CH1,CH0=000 CH2,CH1,CH0=001 CH2,CH1,CH0=010 CH2,CH1,CH0=011 CH2,CH1,CH0=100 CH2,CH1,CH0=101 CH2,CH1,CH0=110 CH2,CH1,CH0=111 P50/AN50 P52/AN52 P53/AN53 P54/AN54 P51/AN51 CH2,CH1,CH0=000 CH2,CH1,CH0=001 CH2,CH1,CH0=010 CH2,CH1,CH0=011 CH2,CH1,CH0=100 ADGSEL0=0 ADGSEL0=1 Port P6 group Port P5 group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter Figure 1.83. A-D converter-related registers (1) A-D control register 0 (Note 1) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bit0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected (Note 2, 3) CH0 Bit symbol Bit name Function CH1 CH2 A-D operation mode select bit 0 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 Repeat sweep mode 1 (Note 2) MD0 MD1 ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selectedCKS0 W R A-D control register 1 (Note 1) Symbol Address When reset ADCON1 03D7 16 0016 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bit SCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit ADGSEL0 A-D operation mode select bit 1 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 0 : Vref not connected 1 : Vref connected A-D input group select bit W R b2 b1 b0 b4 b3 When single sweep and repeat sweep mode 0 are selected 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) b1 b0 When repeat sweep mode 1 is selected 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) b1 b0 0 : Port P6 group is selected 1 : Port P5 group is selected Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again. Note 3: AN50 to AN54 can be used in the same way as for AN0 to AN4. Frequency select bit 1 0 : fAD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4. Note 3: If port P5 group is selected, the contents of A-D registers 5 to 7 are indeterminate. If port P5 group is selected, do not select 8 pins sweep mode. /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Set this bit to “0”. (Note 2, 3) Set this bit to “0”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter Figure 1.84. A-D converter-related registers (2) A-D control register 2 (Note) Symbol Address When reset ADCON2 03D4 16 XXXX0000 2 b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion method select bit 0 : Without sample and hold 1 : With sample and hold Bit symbol Bit name Function R W Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.A-D register i Symbol Address When reset ADi(i=0 to 7) 03C0 16 to 03CF16 Indeterminate Eight low-order bits of A-D conversion result Function R W (b15) b7b7 b0 b0 (b8)

During 10-bit mode Two high-order bits of A-D conversion result Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
During 8-bit mode The value, if read, turns out to be indeterminate. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines SMP 000 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesReserved bit Always set to “0”

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter (1) One-shot mode In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conver- Figure 1.85. A-D conversion register in one-shot mode Item Specification Function The pin selected by the analog input pin select bit is used for one A-D conversion Start condition Writing “1” to A-D conversion start flag Stop condition •End of A-D conversion (A-D conversion start flag changes to “0”)

Writing “0” to A-D conversion start flag Interrupt request generation timingEnd of A-D conversion Input pin One of AN 0 to AN7, as selected (Note) Reading of result of A-D converterRead A-D register corresponding to selected pin Note : AN50 to AN54 can be used in the same way as for AN0 to AN4. A-D control register 0 (Note 1) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bit0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected (Note 2, 3) CH0 Bit symbol Bit name Function CH1 CH2 A-D operation mode select bit 0 0 0 : One-shot mode (Note 2)MD0 MD1 ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selectedCKS0 W R A-D control register 1 (Note) Symbol Address When reset ADCON1 03D7 16 0016 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bitSCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit ADGSEL0 A-D operation mode select bit 1 1 : Vref connected A-D input group select bit W R b2 b1 b0 b4 b3 0 : Port P6 group is selected 1 : Port P5 group is selected Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again. Note 3: AN50 to AN54 can be used in the same way as for AN0 to AN4. Frequency select bit 1 0 : fAD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Set this bit to “0”. Set this bit to “0”. 0 1 Invalid in one-shot mode Set this bit to “0” in this mode. Table 1.30. One-shot mode specifications

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter (2) Repeat mode In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion. (See Table 1.31.) Figure 1.86 shows the A-D control register in repeat mode. Figure 1.86. A-D conversion register in repeat mode Item Specification Function The pin selected by the analog input pin select bit is used for repeated A-D conversion Start condition Writing “1” to A-D conversion start flag Stop condition Writing “0” to A-D conversion start flag Interrupt request generation timingNone generated Input pin One of AN 0 to AN7, as selected (Note) Reading of result of A-D converterRead A-D register corresponding to selected pin (at any time) Table 1.31. Repeat mode specifications A-D control register 0 (Note 1) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bit0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected (Note 2, 3) CH0 Bit symbol Bit name Function CH1 CH2 A-D operation mode select bit 0 0 1 : Repeat mode (Note 2)MD0 MD1 ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selectedCKS0 W R A-D control register 1 (Note) Symbol Address When reset ADCON1 03D7 16 0016 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bitSCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit ADGSEL0 A-D operation mode select bit 1 1 : Vref connected A-D input group select bit W R b2 b1 b0 b4 b3 0 : Port P6 group is selected 1 : Port P5 group is selected Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again. Note 3: AN50 to AN54 can be used in the same way as for AN0 to AN4. Frequency select bit 1 0 : fAD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Set this bit to “0”. Set this bit to “0”. 0 1 Invalid in repeat mode Set this bit to “0” in this mode. Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter (3) Single sweep mode In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D Figure 1.87. A-D conversion register in single sweep mode Item Specification Function The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion Start condition Writing “1” to A-D converter start flag Stop condition • End of A-D conversion (A-D conversion start flag changes to “0”.)

Writing “0” to A-D conversion start flag Interrupt request generation timingEnd of A-D conversion Input pin AN 0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)(Note) Reading of result of A-D converterRead A-D register corresponding to selected pin Note : AN50 to AN54 can be used in the same way as for AN0 to AN4. A-D control register 0 (Note) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bitInvalid in single sweep modeCH0 Bit symbol Bit name Function CH1 CH2 A-D operation mode select bit 0 1 0 : Single sweep modeMD0 MD1 ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selectedCKS0 W R A-D control register 1 (Note 1) Symbol Address When reset ADCON1 03D7 16 0016 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bit SCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit ADGSEL0 A-D operation mode select bit 1 1 : Vref connected A-D input group select bit W R b4 b3 0 : Port P6 group is selected 1 : Port P5 group is selected Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Frequency select bit 1 0 : fAD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4. Note 3: If port P5 group is selected, the contents of A-D registers 5 to 7 are indeterminate. If port P5 group is selected, do not select 8 pins sweep mode. /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Set this bit to “0”. Set this bit to “0”. 0 1 When single sweep and repeat sweep mode 0 are selected 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) b1 b0 (Note 2, 3) Set this bit to “0” in this mode. Table 1.32. Single sweep mode specifications

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter (4) Repeat sweep mode 0 In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep Figure 1.88. A-D conversion register in repeat sweep mode 0 Item Specification Function The pins selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion Start condition Writing “1” to A-D conversion start flag Stop condition Writing “0” to A-D conversion start flag Interrupt request generation timingNone generated Input pin AN 0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)(Note) Reading of result of A-D converterRead A-D register corresponding to selected pin (at any time) Table 1.33. Repeat sweep mode 0 specifications Note : AN50 to AN54 can be used in the same way as for AN0 to AN4. A-D control register 0 (Note) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bitInvalid in repeat sweep mode 0CH0 Bit symbol Bit name Function CH1 CH2 A-D operation mode select bit 0 1 1 : Repeat sweep mode 0MD0 MD1 ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selectedCKS0 W R A-D control register 1 (Note 1) Symbol Address When reset ADCON1 03D7 16 0016 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bit SCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit ADGSEL0 A-D operation mode select bit 1 1 : Vref connected A-D input group select bit W R b4 b3 0 : Port P6 group is selected 1 : Port P5 group is selected Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Frequency select bit 1 0 : fAD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4. Note 3: If port P5 group is selected, the contents of A-D registers 5 to 7 are indeterminate. If port P5 group is selected, do not select 8 pins sweep mode. /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Set this bit to “0”. Set this bit to “0”. 0 1 When single sweep and repeat sweep mode 0 are selected 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) b1 b0 (Note 2, 3) Set this bit to “0” in this mode.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter Item Specification Function All pins perform repeat sweep A-D conversion, with emphasis on the pin or pins selected by the A-D sweep pin select bit Example : AN0 selected AN0 AN1 AN0 AN2 AN0 AN3, etc Start condition Writing “1” to A-D conversion start flag Stop condition Writing “0” to A-D conversion start flag Interrupt request generation timingNone generated Input pin AN 0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins) (Note) Reading of result of A-D converterRead A-D register corresponding to selected pin (at any time) (5) Repeat sweep mode 1 In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using the Figure 1.89. A-D conversion register in repeat sweep mode 1 Table 1.34. Repeat sweep mode 1 specifications A-D control register 0 (Note) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bitInvalid in repeat sweep mode 1CH0 Bit symbol Bit name Function CH1 CH2 A-D operation mode select bit 0 1 1 : Repeat sweep mode 1MD0 MD1 ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selectedCKS0 W R A-D control register 1 (Note 1) Symbol Address When reset ADCON1 03D7 16 0016 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bit SCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit ADGSEL0 A-D operation mode select bit 1 Set “1” in this mode. 1 : Vref connected A-D input group select bit W R b4 b3 0 : Port P6 group is selected 1 : Port P5 group is selected Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Frequency select bit 1 0 : fAD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Set this bit to “0”. Set this bit to “0”. 1 1 When single sweep and repeat sweep mode 1 are selected 0 0 : AN0 (1 pins) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) b1 b0 (Note 2) Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter

Sample and hold Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”. When sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 φAD cycle is achieved with 8-bit resolution and 33 φAD with 10-bit resolution. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and hold is to be used.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Port 100 Figure 1.90. Programmable I/O ports (1) P30 to P35 Data bus Direction register Pull-up selection Port latch P00 to P07, P42, P71 Data bus Pull-up selection Input to respective peripheral functions Direction register Port latch P41, P70 Data bus Pull-up selection output Direction register Port latch P40, P43, P44, P45 Data bus Pull-up selection output Input to respective peripheral functions Direction register Port latch

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Port 101 Figure 1.91. Programmable I/O ports (2) P10 to P17 Data bus Pull-up selection Drive capacity control register Direction register Port latch P50, P53, P54 Data bus Pull-up selection output Direction register Port latch Analog input P52 Data bus Pull-up selection output Direction register Port latch Analog input Serial clock input P51 Data bus Pull-up selection Analog input Port latch Direction register Serial I/O input

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Port 102 Figure 1.92. Programmable I/O ports (3) P60 to P67 Data bus Pull-up selection Analog input Port latch Direction register

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Port 103 Figure 1.93. Direction register Port Pi direction register (Note 1) Symbol Address When reset PDi (i = 0 to 7) 03E216, 03E316, 03E716, 03EA16, 0016 03EB 16, 03EE16, 03EF16 0016 Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 PDi_0 Port Pi 0 direction register PDi_1 Port Pi 1 direction register PDi_2 Port Pi 2 direction register PDi_3 Port Pi 3 direction register PDi_4 Port Pi 4 direction register PDi_5 Port Pi 5 direction register PDi_6 Port Pi 6 direction register PDi_7 Port Pi 7 direction register 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) (i = 0 to 7 except 2) Note 1: Set bit 2 of protect register (address 000A16) to “1” before rewriting to the port P4 direction register. Note 2: Nothing is assigned in direction register of P36, P37, P46, P47, P55 to p57, P72 to P77. These bits can either be set nor reset. When read, its contents are indeterminate. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Port 104 Figure 1.94. Port register Port Pi register Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 Pi_0 Port Pi 0 register Pi_1 Port Pi 1 register Pi_2 Port Pi 2 register Pi_3 Port Pi 3 register Pi_4 Port Pi 4 register Pi_5 Port Pi 5 register Pi_6 Port Pi 6 register Pi_7 Port Pi 7 register Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : “L” level data 1 : “H” level data (i = 0 to 7 except 2) /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Symbol Address When reset Pi (i = 0 to 7) 03E016, 03E116, 03E516, 03E816, Indeterminate 03E916, 03EC16, 03ED16 Indeterminate Note: Nothing is assigned in direction register of P36, P37, P46, P47, P55 to p57, P72 to P77. This bit can either be set nor reset. When read, its content is indeterminate.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Port 105 Figure 1.95. Pull-up control register Pull-up control register 0 Symbol Address When reset PUR0 03FC 16 0016 Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 PU00 P0 0 to P03 pull-up PU01 P0 4 to P07 pull-up PU02 P1 0 to P13 pull-up PU03 P1 4 to P17 pull-up PU06 P3 0 to P33 pull-up PU07 P3 4 to P35 pull-up The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Pull-up control register 1 Symbol Address When reset PUR1 03FD 16 0016 Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 PU10 P4 0 to P43 pull-up PU11 P4 4 to P47 pull-up PU12 P5 0 to P53 pull-up PU13 P5 4 pull-up PU14 P6 0 to P63 pull-up PU15 P6 4 to P67 pull-up PU16 P7 0 to P71 pull-up The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Port P1 drive capacity control register Symbol Address When reset DRR 03FE 16 0016 Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 DRR0 Port P10 drive capacuty DRR1 Port P11 drive capacuty DRR2 Port P12 drive capacuty DRR3 Port P13 drive capacuty DRR4 Port P14 drive capacuty DRR5 Port P15 drive capacuty DRR6 Port P16 drive capacuty DRR7 Port P17 drive capacuty Set P1 N-channel output transistor drive capacity 0 : LOW 1 : HIGH /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Port 106 Example connection of unused pins Table 1.36. Example connection of unused pins Pin name Connection Ports P0, P1, P3 to P7 XOUT (Note) AV SS , VREF AV CC After setting for input mode, connect every pin to VSS (pull-down); or after setting for output mode, leave these pins open. Open Connect to VCC Connect to VSS Note: With external clock input to XIN pin.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Usage precaution 107 Usage Precaution Timer A (timer mode) (1) Reading the timer A0 register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer A0 register with the reload timing gets “FFFF16”. Reading the timer A0 register after setting a value in the timer A0 register with a count halted but before the counter starts counting gets a proper value. Timer A (event counter mode) (1) Reading the timer A0 register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer A0 register with the reload timing gets “FFFF16” by under- flow or “000016” by overflow. Reading the timer A0 register after setting a value in the timer A0 register with a count halted but before the counter starts counting gets a proper value. (2) When stop counting in free run type, set timer again. Timer A (one-shot timer mode) (1) Setting the count start flag to “0” while a count is in progress causes as follows:

The counter stops counting and a content of reload register is reloaded.
The TA0 OUT pin outputs “L” level.
The interrupt request generated and the timer A0 interrupt request bit goes to “1”. (2) The timer A0 interrupt request bit goes to “1” if the timer's operation mode is set using any of the following procedures:
Selecting one-shot timer mode after reset.
Changing operation mode from timer mode to one-shot timer mode.
Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use timer A0 interrupt (interrupt request bit), set timer A0 interrupt request bit to “0” after the above listed changes have been made. Timer A (pulse width modulation mode) (1) The timer A0 interrupt request bit becomes “1” if setting operation mode of the timer in compliance with any of the following procedures:
Selecting PWM mode after reset.
Changing operation mode from timer mode to PWM mode.
Changing operation mode from event counter mode to PWM mode. Therefore, to use timer A0 interrupt (interrupt request bit), set timer A0 interrupt request bit to “0” after the above listed changes have been made. (2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop counting. If the TA0 OUT pin is outputting an “H” level in this instance, the output level goes to “L”, and the timer A0 interrupt request bit goes to “1”. If the TA0OUT pin is outputting an “L” level in this instance, the level does not change, and the timer A0 interrupt request bit does not becomes “1”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Usage precaution 108 Timer B (timer mode, event counter mode) (1) Reading the timer Bi register while a count is in progress allows reading , with arbitrary timing, the value of the counter. Reading the timer Bi register with the reload timing gets “FFFF16”. Reading the timer Bi register after setting a value in the timer Bi register with a count halted but before the counter starts counting gets a proper value. Timer B (pulse period/pulse width measurement mode) (1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt request bit goes to “1”. (2) When the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. At this time, timer Bi interrupt request is not generated. Timer X (timer mode) (1) Reading the timer Xi register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Xi register with the reload timing gets “FFFF16”. Reading the timer A0 register after setting a value in the timer Xi register with a count halted but before the counter starts counting gets a proper value. Timer X (event counter mode) (1) Reading the timer Xi register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Xi register with the reload timing gets “FFFF16” by underflow or “000016” by overflow. Reading the timer Xi register after setting a value in the timer Xi register with a count halted but before the counter starts counting gets a proper value. (2) When stop counting in free run type, set timer again. Timer X (one-shot timer mode) (1) Setting the count start flag to “0” while a count is in progress causes as follows:

The counter stops counting and a content of reload register is reloaded.
The TXi INOUT pin outputs “L” level.
The interrupt request generated and the timer Xi interrupt request bit goes to “1”. (2) The timer Xi interrupt request bit goes to “1” if the timer's operation mode is set using any of the following procedures:
Selecting one-shot timer mode after reset.
Changing operation mode from timer mode to one-shot timer mode.
Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use timer Xi interrupt (interrupt request bit), set timer Xi interrupt request bit to “0” after the above listed changes have been made.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Usage precaution 109 Timer X (pulse width modulation mode) (1) The timer Xi interrupt request bit becomes “1” if setting operation mode of the timer in compliance with any of the following procedures:

Selecting PWM mode after reset.
Changing operation mode from timer mode to PWM mode.
Changing operation mode from event counter mode to PWM mode. Therefore, to use timer Xi interrupt (interrupt request bit), set timer Xi interrupt request bit to “0” after the above listed changes have been made. (2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop counting. If the TXi INOUT pin is outputting an “H” level in this instance, the output level goes to “L”, and the timer Xi interrupt request bit goes to “1”. If the TXiINOUT pin is outputting an “L” level in this instance, the level does not change, and the timer Xi interrupt request bit does not becomes “1”. Timer X (pulse period/pulse width measurement mode) (1) If changing the measurement mode select bit is set after a count is started, the timer Xi interrupt request bit goes to “1”. (2) When the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. At this time, timer Xi interrupt request is not generated. A-D Converter (1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit 0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs). In particular, when the Vref connection bit is changed from “0” to “1”, start A-D conversion after an elapse of 1 µs or longer. (2) When changing A-D operation mode, select analog input pin again. (3) Using one-shot mode or single sweep mode Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by A- D conversion interrupt request bit.) (4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1 Use the undivided main clock as the internal CPU clock. Stop Mode and Wait Mode (1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock oscillation is stabilized. (2) When shifting to WAIT mode or STOP mode, the program stops after reading 8 bytes from the WAIT instruction and the instruction that sets all clock stop bits to “1” in the instruction queue. Therefore, insert a minimum of 8 NOPs after the WAIT instruction and the instruction that sets all clock stop bits to “1”. (3) When the MCU running in low-speed or low power dissipation mode, do not enter WAIT mode with WAIT peripheral function clock stop bit set to “1”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Usage precaution 110 Interrupts (1) Reading address 0000016

When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”. Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”. Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 0000016 by software. (2) Setting the stack pointer
The value of the stack pointer immediately after reset is initialized to 000016. Accepting an inter- rupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the stack pointer before accepting an interrupt. Concerning the first instruction immediately after reset, generating any interrupt is prohibited. (3) External interrupt
When changing a polarity of pins INT0 and INT1, the interrupt request bit may become "1". Clear the interrupt request bit after changing the polarity. (4) Changing interrupt control register See "Changing Interrupt Control Register".

Electrical characteristics (Vcc = 5V) M itsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 111 Table 1.36. Absolute maximum ratings Note 1: Flash memory version: –0.3 to 7 (V) . Note 2: When writing to flash MCU, CNVss is –0.3 to 13 (V) . Note 3: Flat package (56P6S-A) is 300 mW. Note 4: Extended operating temperature version: -40 to 85 °C. When flash memory version is program/erase mode: 25±5 °C. Note 5: Extended operating temperature version: -65 to 150 °C. P70, P71, VREF , XIN RESET, CNVss, VO - 0.3 to Vcc + 0.3 (Note 2) - 0.3 to Vcc + 0.3 Pd Ta = 25 °C - 0.3 to 6.5 (Note 1) - 0.3 to 6.5 (Note 1) V V V VI AVcc Vcc Tstg Topr mW V - 40 to 150 (Note 5) 1000 (Note 3) - 20 to 85 (Note 4) P40 to P45, P50 to P54, P60 to P67, P00 to P07, P10 to P17, P30 to P35, P70, P71, VREF , XINP50 to P54, P60 to P67, P00 to P07, P10 to P17, P30 to P35, P40 to P45, Parameter Unit Rated valueConditionSymbol Operating ambient temperature Input voltage Analog supply voltage Supply voltage Output voltage Power dissipation Storage temperature

Electrical characteristics

Electrical characteristics (Vcc = 5V) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 112 2.7 5.5Vcc 5.0 VccAVcc V V 0 Vss AVss 0.8Vcc V V V Vcc 0.2Vcc0 - 5.0 - 10.0 10.0 5.0 f (XIN) MHz IOL (peak) mA f (XcIN) kHz50 32.768 V Vcc=4.0V to 5.5V 5 x VCC MHz P50 to P54, P60 to P67, P70, P71, XIN, RESET, CNVSS , VIH V IL IOH (avg) IOH (peak) IOL (peak) P10 to P17 IOL (avg) mA mA mA mA 30.0 P00 to P07, P10 to P17, P30 to P35, P40 to P45, P50 to P54, P60 to P67, P70, P71, XIN, RESET, CNV SS P00 to P07, P10 to P17, P30 to P35, P40 to P45, P50 to P54, P60 to P67, P70, P71 P00 to P07, P10 to P17, P30 to P35, P40 to P45, P50 to P54, P60 to P67, P70, P71 P00 to P07, P30 to P35, P40 to P45, P50 to P54, P60 to P67, P70, P71 P00 to P07, P10 to P17, P30 to P35, P40 to P45, P50 to P54, P60 to P67, P70, P71 P00 to P07, P30 to P35, P40 to P45, IOL (avg) P10 to P17 15.0 mA 10.0 HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER 5.0 0Vcc=2.7V to 4.0V - 10.000 Typ. Max. UnitParameter Symbol Min Standard Supply voltage Analog supply voltage Analog supply voltage Supply voltage LOW input voltage HIGH input voltage HIGH average output current HIGH peak output current LOW peak output current Main clock input oscillation frequency LOW average output current Subclock oscillation frequency LOW peak output current LOW average output current Mask ROM version Flash memory version 4.0 5.5 5.0 Mask ROM version Flash memory version MHz10Vcc=4.0V to 5.5V 0 Note 1: Unless otherwise noted: VCC = 2.7V to 5.5V, Vss = 0V, Ta = – 20 to 85oC (Extended operating temperature version:– 40 to 85oC). Flash version: VCC = 4.0V to 5.5V, Vss = 0V, Ta = – 20 to 85oC (Extended operating temperature version:– 40 to 85oC.) Note 2: The average output current is an average value measured over 100ms. Note 3: Keep output current as follows: The sum of port P3 and P4 IOL (peak) is under 40 mA. The sum of port P1 IOL (peak) is under 60 mA. The sum of port P1, P3 and P4 IOH (peak) is under 40 mA. The sum of port P0, P5, P6 and P7 IOL (peak) is under 80 mA. The sum of port P0, P5, P6 and P7 IOH (peak) is under 80 mA. Note 4: Relationship between main clock oscillation frequency and supply voltage. Table 1.37. Recommended operating conditions (Note 1) /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 5.5 4.0 2.70.0 3.5 10.0 Main clock input oscillation frequency (Without wait) Power supply voltage [V] (M ain clock : no division) Highest operation frequency [MHz] 5 x Vcc - 10.000MHz

Electrical characteristics (Vcc = 5V) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 113 Table 1.38. Electrical characteristics (Note1) VO H VO H VO L V 4 . 7 V2 . 0 3 . 0IO H = - 5 m A IO H = - 2 0 0 µ A IO L = 5 m A P 00 t o P 07, P 10 t o P 17, P 30 t o P 35, P 0 t o P 45, P 50 t o P 54, P 60 t o P 67, P 00 t o P 07, P 10 t o P 17, P 30 t o P 35, P 0 t o P 45, P 50 t o P 54, P 60 t o P 67, V P 0 t o P 07, P 30 t o P 35, P 40 t o P 45 P 0 t o P 54, P 60 t o P 67, P 70, P 71 VO L IO L = 2 0 0 µ A 0 . 4 5 V VO L P 0 t o P 17 IO L = 1 5 m A V 2 . 0 IO L = 2 0 0 µ A 0 . 3 VVOL P 0 t o P 17 P70,P71 P70,P71 P 0 t o P 07, P 30 t o P 35, P 40 t o P 45 P 0 t o P 54, P 60 t o P 67, P 70, P 71 II H V R A M I c c VT+ -VT- VT+ -VT- 0.2 0.8 V 0 . 2 1.8 V 5.0 µA µA When clock is stopped 2.0 V 1 . 0 µA mA 20.0 R E S E T T A 0I N , T X 0I N O U T, T X 1I N O U T, T X 2I N O U T TB0 IN,TB1IN INT0,INT1,CLK0,KI0 to KI7 VI = 5 V VI = 0 V - 5 . 0 19.0 38.0 4 . 0 µA9 0 . 0 P 00 t o P 07, P 10 t o P 17, P 30 t o P 35, P 0 t o P 45, P 50 t o P 54, P 60 t o P 67 P 0, P 71, R E S E T , C N V s s IIL P00 to P07,P10 to P17,P30 to P35, P 0 t o P 45, P 50 t o P 54, P 60 t o P 67, VOH XOUT H I G H P O W E R LOWPOWER V 3 . 0 3.0 VO L XOUT HIGHPOWER LOWPOWER V 2.0 2.0 IOH = 1 mA IOH = 0.5 mA IO H = - 1 m A IOH = - 0.5 mA HIGHPOWER IO L = 5 m A 2 . 0L O W P O W E R IO L = 2 0 0 µ A 0.45 H I G H P O W E R L O W P O W E R kΩ167.050.0 30.0 S y m b o l S t a n d a r d T y p . U n i tMeasuring condition M i n a x a r a m e t e r H I G H o u t p u t v o l t a g e L O W o u t p u t v o l t a g e L O W o u t p u t v o l t a g e L O W o u t p u t v o l t a g e H y s t e r e s i s Hysteresis HIGH input current L O W i n p u t c u r r e n t RAM retention voltage Power supply current H I G H o u t p u t v o l t a g e H I G H o u t p u t v o l t a g e L O W o u t p u t v o l t a g e L O W o u t p u t v o l t a g e f(XIN)=10MHz Square wave, no division f(XCIN)=32kHz Square wave Ta=25 C when clock is stopped Ta=85 C when clock is stopped I/O pin has no load f(XCIN)=32kHz When a WAIT instruction is executed (Note 2) VO H XC O U T H I G H P O W E R L O W P O W E R V 3 . 0 1 . 6 N o l o a d N o l o a d H I G H o u t p u t v o l t a g e VO L XOUT H I G H P O W E R LOWPOWER V L O W o u t p u t v o l t a g e VI = 0VR P U L L U P P 00 t o P 07, P 10 t o P 17, P 30 t o P 35, P 0 t o P 45, P 50 t o P 54, P 60 t o P 67,P 0, P 71 P u l l u p r e s i s t o r P 70, P 71, R E S E T , C N V s s M Ω1.0R X I N XI NFeedback resistor M Ω6. 0R X C I N XC I NFeedback resistor µ A No load No load R x D 0, R x D 1 Note 1: Unless otherwise noted: VCC = 5V, VSS = 0V at Ta = -20 to 85oC, f(XIN) = 10MHz (Extended operating temprature version; -40 to 85oC) Note 2: With one timer operated using fC32 . VCC = 5V

Electrical characteristics (Vcc = 5V) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 114 Table 1.39. A-D conversion characteristics (Note) VCC = 5V Bits LSB VREF =VCC VREF =VCC = 5V R LADDER tCONV kohm µs V VIA VREF VCC VREF 3.3 µs2.8tCONV tSAMP 0.3 µs VREF =V CC VREF =VCC = 5V LSB±3 VREF = VCC = 5V ±2 LSB Symbol Standard Typ. UnitMeasuring condition Min. Max.Parameter Resolution Absolute accuracy Ladder resistance Conversion time(10bit) Reference voltage Analog input voltage Conversion time(8bit) Sampling time Sample & hold function not available Sample & hold function available(10bit) Sample & hold function available(8bit) Note : Unless otherwise noted: VCC =AVCC = VREF =5V, VSS =AVSS = 0V at Ta = -25oC, f(XIN) = 10MHz

Electrical characteristics (Vcc = 5V) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 115 Table 1.41. Timer A input (counter input in event counter mode) Table 1.42. Timer A input (gating input in timer mode) Table 1.43. Timer A input (external trigger input in one-shot timer mode) Table 1.44. Timer A input (external trigger input in pulse width modulation mode) Table 1.45. Timer A input (up/down input in event counter mode) Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = -20 to 85oC (*) unless otherwise specified) * Extended operating temprature version; -40 to 85oC Table 1.40. External clock input nstr ns ns ns ns tc tw(H) tw(L) tf Parameter Symbol Standard UnitMin. Max. External clock input LOW pulse width External clock input HIGH pulse width External clock input cycle time External clock fall time External clock rise time 100 nstw(TAL) ns nstw(TAH) tc(TA) ns ns ns tc(TA) tw(TAH) tw(TAL) ns ns ns tc(TA) tw(TAH) tw(TAL) ns ns tw(TAH) tw(TAL) ns ns ns ns ns tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) 100 400 200 200 200 100 100 100 100 2000 1000 1000 400 400 TA0 IN input LOW pulse width TA0 IN input HIGH pulse width Parameter Symbol TA0 IN input cycle time Standard UnitMin. Max. Symbol Symbol Symbol Symbol Parameter Parameter Parameter Parameter Standard UnitMin. Max. Standard UnitMin. Max. Standard UnitMin. Max. Standard UnitMin. Max. TA0 IN input LOW pulse width TA0 IN input HIGH pulse width TA0 IN input cycle time TA0 IN input LOW pulse width TA0 IN input HIGH pulse width TA0 IN input cycle time TA0 IN input LOW pulse width TA0 IN input HIGH pulse width TA0 OUT input LOW pulse width TA0 OUT input HIGH pulse width TA0 OUT input cycle time TA0 OUT input hold time TA0 OUT input setup time VCC = 5V

Electrical characteristics (Vcc = 5V) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 116 ns ns ns tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBL) tw(TBH) ns ns ns ns ns tc(TB) tw(TBH) tw(TBL) ns ns ns tc(TB) tw(TBL) ns tw(TBH) ns ns tc(TX) tw(TXH) tw(TXL) ns ns ns tc(TX) tw(TXL) ns tw(TXH) ns ns tc(TX) tw(TXL) ns tw(TXH) Parameter Symbol Standard UnitMin. Max. Parameter Symbol Standard UnitMin. Max. Parameter Symbol Standard UnitMin. Max. Parameter Symbol Standard UnitMin. Max. Parameter Symbol Standard UnitMin. Max. Parameter Symbol Standard UnitMin. Max. TXiINOUT input LOW pulse width TXiINOUT input HIGH pulse width TXiINOUT input cycle time TXiINOUT input LOW pulse width TXiINOUT input HIGH pulse width TXiINOUT input cycle time TXiINOUT input LOW pulse width TXiINOUT input HIGH pulse width TXiINOUT input cycle time TBiIN input LOW pulse width TBiIN input HIGH pulse width TBiIN input cycle time TBiIN input LOW pulse width TBiIN input HIGH pulse width TBiIN input cycle time TBiIN input LOW pulse width (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input cycle time (counted on both edges) TBiIN input LOW pulse width (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input cycle time (counted on one edge) 100 200 400 200 200 400 200 200 100 400 200 200 200 100 100 Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = -20 to 85oC (*) unless otherwise specified) * Extended operating temprature version; -40 to 85oC Table 1.46. Timer B input (counter input in event counter mode) Table 1.47. Timer B input (pulse period measurement mode) Table 1.48. Timer B input (pulse width measurement mode) Table 1.49. Timer X input (counter input in event counter mode) Table 1.50. Timer X input (gate input in timer mode) Table 1.51. Timer X input (external trigger input in one-shot timer mode) VCC = 5V

Electrical characteristics (Vcc = 5V) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 117 Table 1.52. Timer X input (pulse period measurement mode) Table 1.53. Timer X input (pulse width measurement mode) Table 1.54. Serial I/O ns ns tc(TX) tw(TXH) tw(TXL) ns ns ns tc(TX) tw(TXL) ns tw(TXH) ns ns tw(INH) tw(INL) ns ns ns ns ns ns ns tc(CK) tw(CKH) tw(CKL) td(C-Q) tsu(D-C) th(C-Q) th(C-D) Parameter Symbol Standard UnitMin. Max. Parameter Symbol Standard UnitMin. Max. Parameter Symbol Standard UnitMin. Max. Parameter Symbol Standard UnitMin. Max. TXiINOUT input LOW pulse width TXiINOUT input HIGH pulse width TXiINOUT input cycle time TXiINOUT input LOW pulse width TXiINOUT input HIGH pulse width TXiINOUT input cycle time CLK0 input cycle time CLK0 input HIGH pulse width CLK0 input LOW pulse width TxDi hold time RxDi input setup time TxDi output delay time RxDi input hold time INTi input LOW pulse width INTi input HIGH pulse width 400 200 200 400 200 200 250 250 200 100 100 VCC = 5V Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = -20 to 85oC (*) unless otherwise specified) * Extended operating temprature version; -40 to 85oC Table 1.55. External interrupt INTi inputs

Electrical characteristics (Vcc = 5V) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 118 tsu(D–C) TA0 IN input TA0 OUT input During event counter mode TBiIN input CLK0 TxDi RxDi tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C–Q) th(C–D) th(C–Q) th(TIN–UP) tsu(UP–TIN) TA0 IN input (When count on falling edge is selected) TA0 IN input (When count on rising edge is selected) TA0 OUT input (Up/down input) INTi input TXiINOUT input tc(TX) tw(TXH) tw(TXL) VCC = 5V

Electrical characteristics (Vcc = 3V) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 119 Table 1.56. Electrical characteristics (Note 1) VO H VO L V V0 . 5 2.5IOH = - 1mA IOL = 1 mA P 00 t o P 07, P 10 t o P 17, P 30 t o P 35, P 0 t o P 45, P 50 t o P 54, P 60 t o P 67, P00 to P07,P30 to P35,P40 to P45 P50 to P54,P60 to P67,P70,P71 VO L P10 to P17 IOL = 3 mA V 0 . 5 P70,P71 II H V R A M I c c VT - VT VT+ -VT- 0 . 20 . 8V 0.2 1.8 V 4 . 0 µA µA W h e n c l o c k i s s t o p p e d2 . 0V 1 . 0 µ A m A 20.0 RESET VI = 3V VI = 0V -4.0 3 . 57 . 0 2.8 µ A 40 . 0 P 00 t o P 07, P 10 t o P 17, P 30 t o P 35, P 0 t o P 45, P 50 t o P 54, P 60 t o P 67, P70,P71, RESET, CNVss II L P 0 t o P 07, P 10 t o P 17, P 30 t o P 35, P40 to P45,P50 to P54,P60 to P67, VO H XO U T H I G H P O W E R LOWPOWER V 2.5 2.5 VOL XO U T H I G H P O W E R LOWPOWER V 0 . 5 0 . 5 IOH = 0.1 mA IOH = 50 µA IOH = - 1 mA IOH = - 50 µA H I G H P O W E R IOL = 1 mA 0 . 5L O W P O W E R kΩ5 0 0. 0 1 20 . 0 6 6. 0 S y m b o l S t a n d a r d T y p . U n i tMeasuring condition M i n a x a r a m e t e r HIGH output voltage LOW output voltage LOW output voltage Hysteresis Hysteresis HIGH input current LOW input current RAM retention voltage Power supply current HIGH output voltage L O W o u t p u t v o l t a g e f(XIN)=3.5MHz Square wave, no division f XC I N ) k H z W h e n a W A I T i n s t r u c t i o n i s e x e c u t e d O s c i l l a t i o n c a p a c i t y H I G H N o t e Ta=25 C when clock is stopped Ta=85 C when clock is stopped I/O pin has no load f(XCIN)=32kHz When a WAIT instruction is executed Oscillation capacity LOW (Note 2) VOH XC O U T H I G H P O W E R L O W P O W E R V 3 . 0 1 . 6 No load No load HIGH output voltage VO L XO U T H I G H P O W E R L O W P O W E R V LOW output voltage VI = 0 VR P U L L U P P 00 t o P 07, P 10 t o P 17, P 30 t o P 35, P40 to P45,P50 to P54,P60 to P67,P70,P71 Pull-up resistor P 70, P 71, R E S E T , C N V s s M Ω3.0R X I N XI NF e e d b a c k r e s i s t o r M Ω1 0. 0R X I N XI NFeedback resistor µ A No load No load f(XCIN)=32kHz Square wave 0.9 µ A T A 0I N , T X 0I N O U T, T X 1I N O U T, T X 2I N O U T T B 0 I N , T B 1I N I N T0, I N T1, C L K0, K I0 t o K I7 RxD 0, RxD1 Note 1: Unless otherwise noted: VCC = 3V, VSS = 0V at Ta = -20 to 85oC, f(XIN) = 3.5MHz) (Extended operating temprature version; -40 to 85oC) Note 2: With one timer operated using fC32 . VCC = 3V

Electrical characteristics (Vcc = 3V) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 120 Table 1.57. A-D conversion characteristics (Note) VCC = 3V Bits LSB VREF =VCC VREF =VCC = 3V, Ø AD = fAD R LADDER kohm V VIA VREF 2.7 VCC VREF µs14.0tCONV VREF =VCC Symbol Standard Typ. UnitMeasuring condition Min. Max.Parameter Resolution Absolute accuracy Ladder resistance Reference voltage Analog input voltage Conversion time(8bit) Sample & hold function not available (8bit) VCC = 3V Note : Unless otherwise noted: VCC =AVCC = VREF =3V, VSS =AVSS = 0V at Ta = 25oC, f(XIN) = 3.5MHz.

Electrical characteristics (Vcc = 3V) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 121 Table 1.59. Timer A input (counter input in event counter mode) Table 1.60. Timer A input (gating input in timer mode) Table 1.61. Timer A input (external trigger input in one-shot timer mode) Table 1.62. Timer A input (external trigger input in pulse width modulation mode) Table 1.63. Timer A input (up/down input in event counter mode) Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = -20 to 85oC (*) unless otherwise specified) * Extended operating temprature version; -40 to 85oC Table 1.58. External clock input nstr ns ns ns ns tc tw(H) tw(L) tf Parameter Symbol Standard UnitMin. Max. External clock input LOW pulse width External clock input HIGH pulse width External clock input cycle time External clock fall time External clock rise time 286 120 120 VCC = 3V nstw(TAL) ns nstw(TAH) tc(TA) ns ns ns tc(TA) tw(TAH) tw(TAL) ns ns ns tc(TA) tw(TAH) tw(TAL) ns ns tw(TAH) tw(TAL) ns ns ns ns ns tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) 120 300 120 1200 600 600 600 300 300 300 300 6000 3000 3000 1200 1200 TA0 IN input LOW pulse width TA0 IN input HIGH pulse width Parameter Symbol TA0 IN input cycle time Standard UnitMin. Max. Symbol Symbol Symbol Symbol Parameter Parameter Parameter Parameter Standard UnitMin. Max. Standard UnitMin. Max. Standard UnitMin. Max. Standard UnitMin. Max. TA0 IN input LOW pulse width TA0 IN input HIGH pulse width TA0 IN input cycle time TA0 IN input LOW pulse width TA0 IN input HIGH pulse width TA0 IN input cycle time TA0 IN input LOW pulse width TA0 IN input HIGH pulse width TA0 OUT input LOW pulse width TA0 OUT input HIGH pulse width TA0 OUT input cycle time TA0 OUT input hold time TA0 OUT input setup time

Electrical characteristics (Vcc = 3V) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 122 ns ns ns tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBL) tw(TBH) ns ns ns ns ns tc(TB) tw(TBH) tw(TBL) ns ns ns tc(TB) tw(TBL) ns tw(TBH) ns ns tc(TX) tw(TXH) tw(TXL) ns ns ns tc(TX) tw(TXL) ns tw(TXH) ns ns tc(TX) tw(TXL) ns tw(TXH) Parameter Symbol Standard UnitMin. Max. Parameter Symbol Standard UnitMin. Max. Parameter Symbol Standard UnitMin. Max. Parameter Symbol Standard UnitMin. Max. Parameter Symbol Standard UnitMin. Max. Parameter Symbol Standard UnitMin. Max. TXiINOUT input LOW pulse width TXiINOUT input HIGH pulse width TXiINOUT input cycle time TXiINOUT input LOW pulse width TXiINOUT input HIGH pulse width TXiINOUT input cycle time TXiINOUT input LOW pulse width TXiINOUT input HIGH pulse width TXiINOUT input cycle time TBiIN input LOW pulse width TBiIN input HIGH pulse width TBiIN input cycle time TBiIN input LOW pulse width TBiIN input HIGH pulse width TBiIN input cycle time TBiIN input LOW pulse width (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input cycle time (counted on both edges) TBiIN input LOW pulse width (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input cycle time (counted on one edge) 300 120 120 320 320 600 1200 600 600 1200 600 600 300 120 120 1200 600 600 600 300 300 Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = -20 to 85oC (*) unless otherwise specified) * Extended operating temprature version; -40 to 85oC Table 1.64. Timer B input (counter input in event counter mode) Table 1.65. Timer B input (pulse period measurement mode) Table 1.66. Timer B input (pulse width measurement mode) Table 1.67. Timer X input (counter input in event counter mode) Table 1.68. Timer X input (gate input in timer mode) Table 1.69. Timer X input (external trigger input in one-shot timer mode) VCC = 3V

Electrical characteristics (Vcc = 3V) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 123 Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = -20 to 85oC (*) unless otherwise specified) * Extended operating temprature version; -40 to 85oC Table 1.70. Timer X input (pulse period measurement mode) Table 1.71. Timer X input (pulse width measurement mode) Table 1.72. Serial I/O ns ns tc(TX) tw(TXH) tw(TXL) ns ns ns tc(TX) tw(TXL) ns tw(TXH) ns ns tw(INH) tw(INL) ns ns ns ns ns ns ns tc(CK) tw(CKH) tw(CKL) td(C-Q) tsu(D-C) th(C-Q) th(C-D) Parameter Symbol Standard UnitMin. Max. Parameter Symbol Standard UnitMin. Max. Parameter Symbol Standard UnitMin. Max. Parameter Symbol Standard UnitMin. Max. TXiINOUT input LOW pulse width TXiINOUT input HIGH pulse width TXiINOUT input cycle time TXiINOUT input LOW pulse width TXiINOUT input HIGH pulse width TXiINOUT input cycle time CLK0 input cycle time CLK0 input HIGH pulse width CLK0 input LOW pulse width TxDi hold time RxDi input setup time TxDi output delay time RxDi input hold time INTi input LOW pulse width INTi input HIGH pulse width 1200 600 600 1200 600 600 380 380 300 150 150 160 VCC = 3V Table 1.73. External interrupt INTi inputs

Electrical characteristics (Vcc = 3V) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 124 tsu(D–C) TA0 IN input TA0 OUT input During event counter mode TBiIN input CLK0 TxDi RxDi tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C–Q) th(C–D) th(C–Q) th(TIN–UP) tsu(UP–TIN) TA0 IN input (When count on falling edge is selected) TA0 IN input (When count on rising edge is selected) TA0 OUT input (Up/down input) INTi input TXiINOUT input tc(TX) tw(TXH) tw(TXL) VCC = 3V

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description (Flash memory version) 125 Item Power supply voltage Program/erase voltage Flash memory operation mode Erase block division Program method Erase method Program/erase control method Number of commands Program/erase count ROM code protect Performance 4.0V to 5.5 V (f(XIN)=10MHz) VPP =12V ± 5% (f(XIN)=10MHz, Ta=25±5°C) Three modes (parallel I/O, standard serial I/O, CPU rewrite) See Figure 1.96 One division (3.5 Kbytes) (Note) In units of byte Collective erase Program/erase control by software command 6 commands 100 times Parallel I/O mode is supported. Note: The boot ROM area contains a standard serial I/O mode control program which is stored in it when shipped from the factory. This area can be erased and programmed in only parallel I/O mode. User ROM area Boot ROM area VCC =5V ± 10% (f(XIN)=10MHz, Ta=25±5°C) Table 1.74. Outline Performance of the M30201 (flash memory version) Outline Performance Table 1.74 shows the outline performance of the M30201 (flash memory version).

Description (Flash memory version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 126 Flash Memory The M30201 (flash memory version) contains the NOR type of flash memory that requires a high-voltage VPP power supply for program/erase operations, in addition to the VCC power supply for device operation. For this flash memory, three flash memory modes are available in which to read, program, and erase: parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a program- mer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU). Each mode is detailed in the pages to follow. In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user’s application system. This boot ROM area can be rewritten in only parallel I/O mode. Figure 1.96. Block diagram of flash memory version SFR RAM SFR RAM SFR RAM 0000016 0040016 YYYYY 16 DF000 16 DFDFF 16 XXXXX 16 FFFFF 16 M30201F6 XXXXX 16 F400016 YYYYY 16 00BFF 16 Microcomputer mode Parallel I/O mode CPU rewrite mode Standard serial I/O mode Boot ROM area (3.5K bytes) Boot ROM area (3.5K bytes) User ROM area User ROM area User ROM area Collective erasable/ programmable area Type No. Note 1: In CPU rewrite and standard serial I/O modes, the user ROM is the only erasable/programmable area. Note 2: In parallel I/O mode, the area to be erased/programmed can be selected by the address A17 input. The user ROM area is selected when this address input is high and the boot ROM area is selected when this address input is low. Collective erasable/ programmable area Collective erasable/ programmable area

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Rewrite Mode (Flash memory version) 128 Microcomputer Mode and Boot Mode The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard serial I/O mode becomes unusable.) See Figure 1.96 for details about the boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNV SS pin low (VSS ). In this case, the CPU starts operating using the control program in the user ROM area. When the microcomputer is reset by pulling the P52 pin high (VCC ), the CNVSS pin high(VPPH ), the CPU starts operating using the control program in the boot ROM area. This mode is called the “boot” mode. The control program in the boot ROM area can also be used to rewrite the user ROM area. CPU rewrite mode operation procedure The internal flash memory can be operated on to program, read, verify, or erase it while being placed on- board by writing commands from the CPU to the flash memory control register (addresses 03B4 16, 03B516) and flash command register (address 03B616). Note that when in CPU rewrite mode, the boot ROM area cannot be accessed for program, read, verify, or erase operations. Before this can be accom- plished, a CPU write control program must be written into the boot ROM area in parallel input/output mode. The following shows a CPU rewrite mode operation procedure. <Start procedure (Note 1)> (1) Apply VPP H to the CNVSS /VPP pin and VCC to the port P52 pin for reset release. Or the user can jump from the user ROM area to the boot ROM area using the JMP instruction and execute the CPU write control program. In this case, set the CPU write mode select bit of the flash memory control register to “1” before applying V PP H to the CNVSS /VPP pin. (2) After transferring the CPU write control program from the boot ROM area to the internal RAM, jump to this control program in RAM. (The operations described below are controlled by this program.) (3) Set the CPU rewrite mode select bit to “1”. (4) Read the CPU rewrite mode monitor flag to see that the CPU rewrite mode is enabled. (5) Execute operation on the flash memory by writing software commands to the flash command regis- ter. Note 1: In addition to the above, various other operations need to be performed, such as for entering the data to be written to flash memory from an external source (e.g., serial I/O), initializing the ports, and writing to the watchdog timer. <Clearing procedure> (1) Apply VSS to the CNVSS /VPP pin. (2) Set the CPU rewrite mode select bit to “0”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Rewrite Mode (Flash memory version) 129 Precautions on CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During erase/program mode, set BCLK to 5 MHz or less by changing the divide ratio. (2) Instructions inhibited against use The instructions listed below cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction (3) Interrupts inhibited against use No interrupts can be used that look up the fixed vector table in the flash memory area. Maskable interrupts may be used by setting the interrupt vector table in a location outside the flash memory area.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Rewrite Mode (Flash memory version) 130 Command Program verify Read Program 03B616 First bus cycle Second bus cycle 0016 4016 C0 16 Write Write Write Program address Write Read Erase verify A016Write Verify address Verify data Read Erase 2016Write 03B616 2016Write Verify address Reset FF16Write Mode Address Mode Address Data (D0 to D7) Data (D0 to D7) 03B616 03B616 03B616 03B616 03B616 Program data Verify data FF16Write 03B616 Software Commands Table 1.75 lists the software commands available with the M30201 (flash memory version). When CPU rewrite mode is enabled, write software commands to the flash command register to specify the operation to erase or program. The content of each software command is explained below. Table 1.75. List of Software Commands (CPU Rewrite Mode) Read Command (00 16) The read mode is entered by writing the command code “0016” to the flash command register in the first bus cycle. When an address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data bus (D 0–D 7), 8 bits at a time. The read mode is retained intact until another command is written. After reset and after the reset command is executed, the read mode is set. Program Command (40 16) The program mode is entered by writing the command code “4016” to the flash command register in the first bus cycle. When the user execute an instruction to write byte data to the desired address (e.g., STE instruction) in the second bus cycle, the flash memory control circuit executes the program op- eration. The program operation requires approximately 20 µs. Wait for 20 µs or more before the user go to the next processing. During program operation, the watchdog timer remains idle, with the value “7FFF 16” set in it. Note 1: The write operation is not completed immediately by writing a program command once. The user must always execute a program-verify command after each program command executed. And if verification fails, the user need to execute the program command repeatedly until the verification passes. See Figure 1.99 for an example of a programming flowchart.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Rewrite Mode (Flash memory version) 131 Program-verify command (C016) The program-verify mode is entered by writing the command code “C016” to the flash command register in the first bus cycle. When the user execute an instruction (e.g., LDE instruction) to read byte data from the address to be verified (the previously programmed address) in the second bus cycle, the content that has actually been written to the address is read out from the memory. The CPU compares this read data with the data that it previously wrote to the address using the program command. If the compared data do not match, the user need to execute the program and program-verify operations one more time. Erase command (20 16 + 2016) The flash memory control circuit executes an erase operation by writing command code “2016” to the flash command register in the first bus cycle and the same command code to the flash command register again in the second bus cycle. The erase operation requires approximately 20 ms. Wait for 20 ms or more before the user go to the next processing. Before this erase command can be performed, all memory locations to be erased must have had data “00 16” written to by using the program and program-verify commands. During erase operation, the watchdog timer remains idle, with the value “7FFF16 set in it. Note 1: The erase operation is not completed immediately by writing an erase command once. The user must always execute an erase-verify command after each erase command executed. And if verification fails, the user need to execute the erase command repeatedly until the verification passes. See Figure 1.99 for an example of an erase flowchart. Erase-verify command (A0 16) The erase-verify mode is entered by writing the command code “A016” to the flash command register in the first bus cycle. When the user execute an instruction to read byte data from the address to be verified (e.g., LDE instruction) in the second bus cycle, the content of the address is read out. The CPU must sequentially erase-verify memory contents one address at a time, over the entire area erased. If any address is encountered whose content is not “FF 16” (not erased), the CPU must stop erase-verify at that point and execute erase and erase-verify operations one more time. Note 1: If any unerased memory location is encountered during erase-verify operation, be sure to execute erase and erase-verify operations one more time. In this case, however, the user does not need to write data “00 16” to memory before erasing.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Rewrite Mode (Flash memory version) 132 Start Address = first location Loop counter : X=0 Write program command Write : 4016 Duration = 20 µs Duration = 6 µs X=25 ? Verify OK ? PASS FAIL FAIL PASS YES PASS NO NO FAIL Write program data/ address Loop counter : X=X+1 Write program verify command Last address ?Next address ? Write read command Write read command Verify OK ? Write : Program data Write : C016 Write : 0016 Write:2016 Duration = 6µs X=1000 ? Verify OK? PASS FAIL FAIL PASS YES PASS NO NO FAIL Duration = 20ms YES NO Start All bytes = "0016"? Program all bytes = "0016" Address = First address Loop counter X=0 Write erase command Write erase command Loop counter X=X+1 Write erase verify command/address Verify OK? Last address?Next address Write read command Write read command Write:2016 Write:A016 Write:0016 Read: expect value=FF16 Figure 1.99. Program and erase execution flowchart in the CPU rewrite mode Program Erase Reset command (FF16 + FF16) The reset command is used to stop the program command or the erase command in the middle of operation. After writing command code “4016” or “2016” twice to the flash command register, write command code “FF16” to the flash command register in the first bus cycle and the same command code to the flash command register again in the second bus cycle. The program command or erase command is disabled, with the flash memory placed in read mode.

Appendix Parallel I/O Mode (Flash memory version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 133 Pin name Signal name I/O Function VCC ,VSS Power supply input Apply 5 V ± 10 % to the Vcc pin and 0 V to the Vss pin. CNV SS CNV SS Apply 12 V ± 5 % to the CNVSS pin.I RESET Reset input Connect this pin to VSS .I XIN Clock input Connect a ceramic or crystal resonator between the XIN and XOUT pins. When entering an externally derived clock, enter it from XIN and leave XOUT open. I XOUT Clock output O AV CC , AVSS Analog power supply input VREF Reference voltage input I Connect AVSS to Vss and AVcc to Vcc, respectively. Connect this pin to VSS . P00 to P07 Data I/O D0 to D7 These are data D0–D 7 input/output pins. These are address A4–A7 input pins. IP30 to P33 P34 to P35 I P41 This is a OE input pin.I P50 Address input A17 P64 to P67 I/O Address input A4 to A7 Input port P3 OE input P42, P44, P45 Input port P4 I Enter high signals or low signals to these pins. Input port P6 Enter high signals or low signals to these pins.I P70 to P71 Input port P7 I CE input This is a CE input pin.IP43 Enter low signals to these pins. P40 WE input This is a WE input pin.I I This is address A17 input pin. P51 VRFY input I Apply VIH (5 V) to this pin when VPP = VPPH (12 V), or VIL (0 V) when VPP = VPPL (5 V). P52 IInput port P5 Enter low signal to this pin. P53, P54 Input port P5 I Enter high signals or low signals to these pins. These are address A0–A3 input pins. IP60 to P63 Address input A0 to A3 Enter high signals or low signals to these pins. P10 to P17 Address input A8 to A15 These are address A8–A15 input pins.I Description of Pin Function (Flash Memory Parallel I/O Mode)

Appendix Parallel I/O Mode (Flash memory version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 134 M30201(flash memory version) M5M28F101 VCC VSS VCC VSS VCC VSS Address input Data I/O OE input CE input P60 to P63, P30 to P33, P10 to P17, P50 P00 to P07 P41 P43 A0 to A15, A17 D 0 to D7 OE CE WE input VRFY input (Note) P40 P51 WE Note: The VRFY input only selects read-only or read/write mode, and does not have any pin associated with it on the M5M28F101. Parallel I/O Mode The parallel I/O mode is entered by making connections shown in Figures 1.101 and 1.102 and then turning the VPPH power supply on. In this mode, the M30201 (flash memory version) operates in a manner similar to the NOR flash memory M5M28F101 from Mitsubishi. Note, however, that there are some differences with regard to the functions not available with the microcomputer (function of read device identification code) and matters related to memory capacity. Table 1.76 shows pin relationship between the M30201 and M5M28F101 in parallel I/O mode. Table 1.76. Pin relationship in parallel I/O mode SFR RAM SFR RAM SFR RAM 0000016 0040016 YYYYY 16 DF000 16 DFDFF 16 XXXXX 16 FFFFF 16 M30201F6 XXXXX 16 F400016 YYYYY 16 00BFF 16 Microcomputer mode Parallel I/O mode CPU rewrite mode Standard serial I/O mode Boot ROM area (3.5K bytes) Boot ROM area (3.5K bytes) User ROM area User ROM area User ROM area Collective erasable/ programmable area Type No. Note 1: In CPU rewrite and standard serial I/O modes, the user ROM is the only erasable/programmable area. Note 2: In parallel I/O mode, the area to be erased/programmed can be selected by the address A17 input. The user ROM area is selected when this address input is high and the boot ROM area is selected when this address input is low. Collective erasable/ programmable area Collective erasable/ programmable area Figure 1.100. Block diagram of flash memory version

Appendix Parallel I/O Mode (Flash memory version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 135 P63/AN3 P62/AN2 P61/AN1 P60/AN0 VREF XIN XOUT P50/TXD 0/AN50 P67/AN7 P66/AN6 P65/AN5 P64/AN4 VSS RESET VCC CNV SS P51/RXD 0/AN51 P52/CLK0/AN52 AV SS P45/TX2INOUT P70/TB0IN/XCOUT P71/TB1IN/XCIN P54/CKOUT /AN54 P53/CLKS/AN53 AV CC P07/KI7 P06/KI6 P05/KI5 P04/KI4 P03/KI3 P02/KI2 P01/KI1 P10(LED0) P11(LED1) P12(LED2) P13(LED3) P14(LED4) P15(LED5) P16(LED6) P17(LED7) M30201F6SP P00/KI0 P30 P31 P32P33 P34 P35 P40/TA0IN/TXD 1 P41/TA0OUT P42/RXD 1 P44/INT1/TX1INOUT P43/INT0/TX0INOUTCE OE WE A10 A11 A13 A14 A15 A12 A17 VSS VCC VPPH Connect oscillator circuit. VRFY Figure 1.101. Pin connection diagram in parallel I/O mode (1)

Appendix Parallel I/O Mode (Flash memory version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 136 Figure 1.102. Pin connection diagram in parallel I/O mode (2) 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 56 55 54 53 27 28 XIN XOUT P50/TXD 0/AN50 P67/AN7 VSS RESET VCC CNV SS P51/RXD 0/AN51 2/CLK 0/AN P45/TX2INOUT P71/TB1IN/XCIN P70/TB0IN/XCOUT 1/TA0 OUT 0/TA0 IN XD 2/R XD 4/CK OUT /AN 3/CLKS/AN V REF 0/AN 1/AN AV SS AV CC P10(LED0) 4(LED M30201F6FP M30201F6TFP N.C. N.C. N.C. N.C. P00/KI0 2/AN 3/AN 4/AN 5/AN 6/AN P01/KI1 P02/KI2 P03/KI3 P04/KI4 P05/KI5 P06/KI6 P07/KI7 P11(LED1) P12(LED2) P13(LED3) 5(LED 6(LED 7(LED P44/INT1/TX1INOUT P43/INT0/TX0INOUT A17 D7A8 A10 A11 A12 A13A15 A14A4A6 A5A7 V SS VCC CE OE WE VRFY VPPH Connect oscillator circuit.

Appendix Parallel I/O Mode (Flash memory version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 137 Read only Read/ Write Read Write Output disabled Stand by Read Output disabled Stand by Data output Hi-Z Data output Hi-Z Data input V IL VIL VIH VIL VIL VIH VIL VIH VIL VIH VIH VIH VIL VIL VIL VIH VIH VIH VIH VIH Mode Pin name CE OE WE V RFY D 0 to D7 Note: X can be VIL or VIH. VPPH VPP VPPH VPPH VPPH VPPH VPPH VPPH X X X X Hi-Z Hi-Z VIL VIH VIL VIH User ROM and Boot ROM Areas In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 1.100 can be rewritten. In the boot ROM area, an erase block operation is applied to only one 3.5 K byte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory. Therefore, using the device in standard serial input/output mode, the user does not need to write to the boot ROM area. Functional Outline (Parallel I/O Mode) In parallel I/O mode, bus operation modes—Read, Output Disable, Standby, and Write—are selected by the status of the CE, OE, WE, VRFY , and CNVSS input pins. The contents of erase, program, and other operations are selected by writing a software command. The data in memory can only be read out by a read after software command input. Program and erase operations are controlled using software commands. Table 1.77. Relationship between control signals and bus operation modes

Appendix Parallel I/O Mode (Flash memory version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 138 The following explains about bus operation modes, software commands, and status register. Bus Operation Modes Read-only mode is entered by applying VPPH to the CNVSS pin and a low voltage to the VRFY pin. Read-only mode has three states: Read, Output Disable, and Standby which are selected by setting the CE, OE, and WE pins high or low. Read-write mode is entered by applying VPPH to the CNVSS pin and a high voltage to the VRFY pin. Read-write mode has four states: Read, Output Disable, Standby, and Write which are selected by setting the CE, OE, and WE pins high or low. Read The Read mode is entered by pulling the WE pin high when the CE and OE pins are low. In Read mode, the data corresponding to each software command entered is output from the data I/O pins D 0–D 7. Output Disable The Output Disable mode is entered by pulling the CE pin low and the WE and OE pins high. Also, the data I/O pins are placed in the high-impedance state. Standby The Standby mode is entered by driving the CE pin high. Also, the data I/O pins are placed in the high-impedance state. Write The Write mode is entered by applying V PPH to the CNVSS pin and a high voltage to the VRFY pin and then pulling the WE pin low when the CE pin is low and OE pin is high. In this mode, the device accepts the software commands or write data entered from the data I/O pins. A program, erase, or some other operation is initiated depending on the content of the software command entered here. The input data such as address is latched at the falling edge of WE pin. The input data such as software command is latched at the rising edge of WE pin.

Appendix Parallel I/O Mode (Flash memory version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 139 Command Program verify Read Program First bus cycle Second bus cycle 0016 4016 C0 16 Write Write Write Program address Write Read Erase verify A016Write Verify data Read Erase 2016Write 20 16Write Reset FF16Write Mode Address Mode Address Data (D0 to D7) Data (D0 to D7) x Program data Verify data FF16Write x x x x Verify address x x x x Software Commands Table 1.78 lists the software commands available with the M30201 (flash memory version). By entering a software command from the data I/O pins (D0–D 7) in Write mode, specify the content of the operation, such as erase or program operation, to be performed. The following explains the content of each software command. Table 1.78. Software command list (parallel I/O mode) Read Command (00 16) The read mode is entered by writing the command code “0016” in the first bus cycle. When an address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data I/O pins (D 0–D 7). The read mode is retained intact until another command is written. After reset and after the reset command is executed, the read mode is set. Program Command (40 16) The program mode is entered by writing the command code “4016” in the first bus cycle. When an address and data to be program is write in the second bus cycle, the flash memory control circuit executes the program operation. The program operation requires approximately 20 µs. Wait for 20 µs or more before the user go to the next processing. Note 1: The write operation is not completed immediately by writing a program command once. The user must always execute a program-verify command after each program command executed. And if verification fails, the user need to execute the program command repeatedly until the verification passes. See Figure 1.103 for an example of a programming flowchart.

Appendix Parallel I/O Mode (Flash memory version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 140 Program-verify command (C016) The program-verify mode is entered by writing the command code “C016” in the first bus cycle and the verify data is output from the data I/O pins (D0–D 7) in the second bus cycle. Erase command (2016 + 2016) The flash memory control circuit executes an erase operation by writing command code “2016” in the first bus cycle and the same command code again in the second bus cycle. The erase operation requires approximately 20 ms. Wait for 20 ms or more before the user go to the next processing. Before this erase command can be performed, all memory locations to be erased must have had data “00 16” written to by using the program and program-verify commands. Note 1: The erase operation is not completed immediately by writing an erase command once. The user must always execute an erase-verify command after each erase command executed. And if verification fails, the user need to execute the erase command repeatedly until the verification passes. See Figure 1.103 for an example of an erase flowchart. Erase-verify command (A0 16) The erase-verify mode is entered by writing the command code “A016” in the first bus cycle and the verify data is output from the data I/O pins (D0–D 7) in the second bus cycle. Note 1: If any unerased memory location is encountered during erase-verify operation, be sure to execute erase and erase-verify operations one more time. In this case, however, the user does not need to write data “00 16” to memory before erasing.

Appendix Parallel I/O Mode (Flash memory version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 141 Start Address = first location Loop counter : X=0 Write program command Write : 4016 Duration = 20 µs Duration = 6 µs X=25 ? Verify OK ? PASS FAIL FAIL PASS YES PASS NO NO FAIL Write program data/ address Loop counter : X=X+1 Write program verify command Last address ?Next address ? Write read command Write read command Verify OK ? Write : Program data Write : C016 Write : 0016 Write:2016 Duration = 6µs X=1000 ? Verify OK? PASS FAIL FAIL PASS YES PASS NO NO FAIL Duration = 20ms YES NO Start All bytes = "0016"? Program all bytes = "0016" Address = First address Loop counter X=0 Write erase command Write erase command Loop counter X=X+1 Write erase verify command/address Verify OK? Last address?Next address Write read command Write read command Write:2016 Write:A016 Write:0016 Read: expect value=FF16 Figure 1.103. Program and erase execution flowchart in the CPU rewrite mode Program Erase Reset command (FF16 + FF16) The reset command is used to stop the program command or the erase command in the middle of operation. After writing command code “4016” or “2016” twice, write command code “FF16” in the first bus cycle and the same command code again in the second bus cycle. The program command or erase command is disabled, with the flash memory placed in read mode.

Appendix Parallel I/O Mode (Flash memory version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 142 Figure 1.104. Protect control address Protect function In parallel I/O mode, the internal flash memory has the “protect function” available. This function protects the flash memory contents from being read or rewritten easily. Depending on the content at the protect control address (FFFFF 16) in parallel I/O mode, this function inhibits the flash memory contents against read or modification. The protect control address (FFFFF16) is shown in Figure 1.104. (This address exists in the user ROM area.) The protect function is enabled by setting one of the two protect set bits to “0”, so that the internal flash memory contents are inhibited against read or modification. The protect function is disabled by setting both of the two protect reset bits to “00”, so that the internal flash memory contents can be read or modified. Once the protect function is set, the user cannot change settings of the protect clear bits while in parallel I/O mode. Settings of the protect reset bits can only be changed in CPU rewrite mode. Symbol Address When shipping ROMCP FFFFF 16 FF16 Protect control address Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 00: Protect removed 01: Protect set bit effective 10: Protect set bit effective 11: Protect set bit effective 00: Protect enabled 01: Protect enabled 10: Protect enabled 11: Protect disabled Protect reset bit Protect set bit ROMCR ROMCP b5 b4 b7 b6 Note 1: When protect is turned on, the flash memory version is protected against readout or modification in parallel I/O mode. Note 2: The protect reset bits can be used to turn off protect . However, since these bits cannot be changed in parallel I/O mode, they need to be rewritten in CPU rewrite mode. Reserved bit Always set to "1". 1 1 1 1

Appendix Standard Serial I/O Mode (Flash Memory Version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 143 Pin Description VCC ,VSS Apply 5V ± 10 % to Vcc pin and 0 V to Vss pin. CNV SS Mode entry pin. Apply 12V ± 5 % to this pin. RESET Reset input pin. While reset is "L" level, a 20 cycle or longer clock must be input to XIN pin. XIN Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin.XOUT AV CC , AVSS VREF Connect AVSS to Vss and AVcc to Vcc, respectively. Enter the reference voltage for AD from this pin. P00 to P07 Input "H" or "L" level signal or open. P10 to P17 Input "H" or "L" level signal or open. P30 to P35 Input "H" or "L" level signal or open. P40 to P45 Input "H" or "L" level signal or open. P54 Input "H" or "L" level signal or open. P50 Serial data output pin. P51 P52 Mode entry pin. Supply "H" level when powering on MCU. When startup is completed this pin serves the serial input clock. P60 to P67 Input "H" or "L" level signal or open. P70 to P71 Input "H" or "L" level signal or open. Name Power input CNV SS Reset input Clock input Clock output Analog power supply input Reference voltage input Input port P0 Input port P1 Input port P3 Input port P4 Input port P5 TxD output SCLK input BUSY Input port P6 Input port P7 I/O I I I O I I I I I I I I I I O RxD input Serial data input pin. I ->O This pin sets the type of serial flash programming mode.

An "H" level input (mode 1) sets the mode to clock synchronous.
An "L" level input (mode 2) sets the mode to clock asynchronous. This pin changes to "output" after entry into standard serial I/O mode. Pin functions (Flash memory standard serial I/O mode)

Appendix Standard Serial I/O Mode (Flash Memory Version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 144 Figure 1.105. Pin connections for standard serial I/O mode (1) P63/AN3 P62/AN2 P61/AN1 P60/AN0 VREF XIN XOUT P50/TXD 0/AN50 P67/AN7 P66/AN6 P65/AN5 P64/AN4 VSS RESET VCC CNV SS P51/RXD 0/AN51 P52/CLK0/AN52 AV SS P45/TX2INOUT P70/TB0IN/XCOUT P71/TB1IN/XCIN P54/CKOUT /AN54 P53/CLKS/AN53 AV CC P07/KI7 P06/KI6 P05/KI5 P04/KI4 P03/KI3 P02/KI2 P01/KI1 P10(LED0) P11(LED1) P12(LED2) P13(LED3) P14(LED4) P15(LED5) P16(LED6) P17(LED7) M30201F6SP P00/KI0 P30 P31 P32P33 P34 P35 P40/TA0IN/TXD 1 P41/TA0OUT P42/RXD 1 P44/INT1/TX1INOUT P43/INT0/TX0INOUT BUSY SCLK R XD TXD VSS VCC CNV SS VSS VCC RESET CNV SS VPP H RESET V SS VCC Mode setup method Signal Value Connect oscillator circuit. SCLK V CC (Note) Note: Apply VCC when powering on MCU.

Appendix Standard Serial I/O Mode (Flash Memory Version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 145 Figure 1.106. Pin connections for serial I/O mode (2) 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 56 55 54 53 27 28 XIN XOUT P50/TXD 0/AN50 P67/AN7 VSS RESET VCC CNV SS P51/RXD 0/AN51 2/CLK 0/AN P45/TX2INOUT P71/TB1IN/XCIN P70/TB0IN/XCOUT 1/TA0 OUT 0/TA0 IN XD 2/R XD 4/CK OUT /AN 3/CLKS/AN V REF 0/AN 1/AN AV SS AV CC P10(LED0) 4(LED M30201F6FP M30201F6TFP N.C. N.C. N.C. N.C. P00/KI0 2/AN 3/AN 4/AN 5/AN 6/AN P01/KI1 P02/KI2 P03/KI3 P04/KI4 P05/KI5 P06/KI6 P07/KI7 P11(LED1) P12(LED2) P13(LED3) 5(LED 6(LED 7(LED P44/INT1/TX1INOUT P43/INT0/TX0INOUT V SSV CC BUSYSCLK R XD TXD CNV SS RESET VSS VCCConnect oscillator circuit. CNV SS VPP H RESET V SS VCC Mode setup method Signal Value SCLK V CC (Note) Note: Apply VCC when powering on MCU.

Appendix Standard Serial I/O Mode (Flash Memory Version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 146 Standard serial I/O mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is serial. There are actually two standard serial I/O modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. Both modes require a purpose-specific peripheral unit. The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory rewrite (uses the CPU's rewrite mode), rewrite data input and so forth. It is started when the reset is re- leased, which is done when the P5 2 (SCLK) pin is "H" level, the CNVss pin "VppH" level. (In the ordinary command mode, set CNVss pin to "L" level.) This control program is written in the boot ROM area when the product is shipped from Mitsubishi. Accord- ingly, make note of the fact that the standard serial I/O mode cannot be used if the boot ROM area is rewritten in the parallel I/O mode. Figures 1.105 and 1.106 show the pin connections for the standard serial I/O mode. Serial data I/O uses UART0 and transfers the data serially in 8-bit units. Standard serial I/O switches between mode 1 (clock synchronized) and mode 2 (clock asynchronized) according to the level of 3 (BUSY) pin when the reset is released. To use standard serial I/O mode 1 (clock synchronized), set the P53 (BUSY) pin to "H" level and release the reset. The operation uses the four UART0 pins CLK0, RxD0, TxD0 and P53 (BUSY). The CLK0 pin is the transfer clock input pin through which an external transfer clock is input. The TxD0 pin is for CMOS output. The P53 (BUSY) pin outputs an "L" level when ready for reception and an "H" level when reception starts. To use standard serial I/O mode 2 (clock asynchronized), set the P53 (BUSY) pin to "L" level and release the reset. The operation uses the two UART0 pins RxD0 and TxD0. In the standard serial I/O mode, only the user ROM area indicated in Figure 1.96 can be rewritten. The boot ROM cannot. In the standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, com- mands sent from the peripheral unit are not accepted unless the ID code matches.

Appendix Standard Serial I/O Mode 1 (Flash Memory Version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 147 Overview of standard serial I/O mode 1 (clock synchronized) In standard serial I/O mode 1, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using clock-synchronized serial I/O (UART0) and P53 (BUSY). Standard serial I/O mode 1 is engaged by releasing the reset with the P53 (BUSY) pin "H" level. In reception, software commands, addresses and program data are synchronized with the rise of the transfer clock that is input to the CLK 0 pin, and are then input to the MCU via the RxD0 pin. In transmis- sion, the read data and status are synchronized with the fall of the transfer clock, and output from the TxD 0 pin. The TxD0 pin is for CMOS output. Transfer is in 8-bit units with LSB first. When busy, such as during transmission, reception, erasing or program execution, the P53 (BUSY) pin is "H" level. Accordingly, always start the next transfer after the P53 (BUSY) pin is "L" level. Also, data and status registers in memory can be read after inputting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following are explained software commands, status registers, etc.

Appendix Standard Serial I/O Mode 1 (Flash Memory Version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 148 Software Commands Table 1.79 lists software commands. In the standard serial I/O mode 1, erase operations, programs and reading are controlled by transferring software commands via the RxD0 pin. Software commands are explained here below. Table 1.79. Software commands (Standard serial I/O mode 1) Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is trans- ferred from the peripheral unit to the flash memory microcomputer. Note 2: SRD refers to status register data. SRD1 refers to status register 1 data. Note 3: All commands can be accepted when the flash memory is totally blank. Control command 2nd byte 3rd byte 4th byte 5th byte 6th byte

1 Page read

2 Page program

3 Erase all unlocked blocks

4 Read status register

5 Clear status register

6 Read lockbit status

7 ID check function

8 Download function

9 Version data output function

10 Boot area output function

(high) Check- sum Version data output Data output Address (high) Address (high) SRD1 output Address (high) Address (middle) Size (high) Version data output Address (high) Address (middle) Address (middle) D0 16 SRD output Address (middle) Address (low) Size (low) Version data output Address (middle) FF 16 4116 A7 16 7016 5016 7116 F516 FA 16 FB 16 FC 16

Appendix Standard Serial I/O Mode 1 (Flash Memory Version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 152 Download Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the “FA16” command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM. Figure 1.113. Timing for download FA 16 Program data Program data Data size (high) Data size (low) Check sum CLK0 RxD0 TxD0 P53(BUSY) (M16C reception data) (M16C transmit data)

Appendix Standard Serial I/O Mode 1 (Flash Memory Version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 155 Status Register (SRD) The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read status register command (70 16). Also, the status register is cleared by writing the clear status register command (5016). Table 1.80 gives the definition of each status register bit. After clearing the reset, the status register outputs “80 16”. Table 1.80. Status register (SRD) Status bit (SR7) The status bit indicates the operating status of the flash memory. When power is turned on, “1” (ready) is set for it. The bit is set to “0” (busy) during an auto write or auto erase operation, but it is set back to “1” when the operation ends. Erase Status (SR5) The erase status reports the operating status of the auto erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is set to “0”. Program Status (SR4) The program status reports the operating status of the auto write operation. If a write error occurs, it is set to “1”. When the program status is cleared, it is set to “0”. SRD0 bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Status name Status bit Reserved Erase bit Program bit Reserved Reserved Reserved Reserved Definition "1" "0" Ready Terminated in error Terminated in error Busy Terminated normally Terminated normally

Appendix Standard Serial I/O Mode 1 (Flash Memory Version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 156 Status Register 1 (SRD1) Status register 1 indicates the status of serial communications, results from ID checks and results from check sum comparisons. It can be read after the SRD by writing the read status register command (7016). Also, status register 1 is cleared by writing the clear status register command (5016). Table 1.81 gives the definition of each status register 1 bit. “0016” is output when power is turned ON and the flag status is maintained even after the reset. Table 1.81. Status register 1 (SRD1) Boot Update Completed Bit (SR15) This flag indicates whether the control program was downloaded to the RAM or not, using the down- load function. Check Sum Consistency Bit (SR12) This flag indicates whether the check sum matches or not when a program, is downloaded for execu- tion using the download function. ID Check Completed Bits (SR11 and SR10) These flags indicate the result of ID checks. Some commands cannot be accepted without an ID check. Data Reception Time Out (SR9) This flag indicates when a time out error is generated during data reception. If this flag is attached during data reception, the received data is discarded and the microcomputer returns to the command wait state. SRD1 bits SR15 (bit7) SR14 (bit6) SR13 (bit5) SR12 (bit4) SR11 (bit3) SR10 (bit2) SR9 (bit1) SR8 (bit0) Status name Boot update completed bit Reserved Reserved Checksum match bit ID check completed bits Data receive time out Reserved Definition "1" "0" Update completed Match Not update Mismatch Normal operation Not verified Verification mismatch Reserved Verified Time out

Appendix Standard Serial I/O Mode 1 (Flash Memory Version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 157 Example Circuit Application for The Standard Serial I/O Mode 1 The below figure shows a circuit application for the standard serial I/O mode 1. Control pins will vary according to programmer, therefore see the peripheral unit manual for more information. Figure 1.118. Example circuit application for the standard serial I/O mode 1 P53(BUSY) CLK0 R XD0 TXD0 CNVss Clock input P53 output Data input Data output M30201 Flash memory version VPP (1) Control pins and external circuitry will vary according to peripheral unit. For more information, see the peripheral unit manual. (2) In this example, the microprocessor mode and standard serial I/O mode are switched via a switch.

Appendix Standard Serial I/O Mode 2 (Flash Memory Version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 158 Overview of standard serial I/O mode 2 (clock asynchronized) In standard serial I/O mode 2, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using 2-wire clock-asynchronized serial I/O (UART0). Standard serial I/O mode 2 is engaged by releasing the reset with the P5 3 (BUSY) pin "L" level. The TxD0 pin is for CMOS output. Data transfer is in 8-bit units with LSB first, 1 stop bit and parity OFF. After the reset is released, connections can be established at 9,600 bps when initial communications (Fig- ure 1.119) are made with a peripheral unit. However, this requires a main clock with a minimum 2 MHz input oscillation frequency. Baud rate can also be changed from 9,600 bps to 19,200, 38,400 or 57,600 bps by executing software commands. However, communication errors may occur because of the oscillation fre- quency of the main clock. If errors occur, change the main clock's oscillation frequency and the baud rate. After executing commands from a peripheral unit that requires time to erase and write data, as with erase and program commands, allow a sufficient time interval or execute the read status command and check how processing ended, before executing the next command. Data and status registers in memory can be read after transmitting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following are explained initial communications with peripheral units, how frequency is identified and software commands. Initial communications with peripheral units After the reset is released, the bit rate generator is adjusted to 9,600 bps to match the oscillation fre- quency of the main clock, by sending the code as prescribed by the protocol for initial communications with peripheral units (Figure 1.119). (1) Transmit "B0 16" from a peripheral unit. If the oscillation frequency input by the main clock is 10 MHz, the MCU with internal flash memory outputs the "B016" check code. If the oscillation frequency is anything other than 10 MHz, the MCU does not output anything. (2) Transmit "0016" from a peripheral unit 16 times. (The MCU with internal flash memory sets the bit rate generator so that "0016" can be successfully received.) (3) The MCU with internal flash memory outputs the "B016" check code and initial communications end successfully *1. Initial communications must be transmitted at a speed of 9,600 bps and a transfer interval of a minimum 15 ms. Also, the baud rate at the end of initial communications is 9,600 bps. *1. If the peripheral unit cannot receive "B016" successfully, change the oscillation frequency of the main clock. Figure 1.119. Peripheral unit and initial communication MCU with internal flash memory Peripheral unit (1) Transfer "B016" If the oscillation frequency input by the main clock is 10 MHz, the MCU outputs "B0 16". If other than

10 MHz, the MCU does not

output anything. (2) Transfer "00 16" 16 times At least 15ms transfer interval 1st 2nd 15 th 16th (3) Transfer check code "B016" "B016" "0016" "0016" "0016" "B016" "B016" "0016" Reset The bit rate generator setting completes (9600bps)

Appendix Standard Serial I/O Mode 2 (Flash Memory Version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 159 How frequency is identified When "0016" data is received 16 times from a peripheral unit at a baud rate of 9,600 bps, the value of the bit rate generator is set to match the operating frequency (2 - 10 MHz). The highest speed is taken from the first 8 transmissions and the lowest from the last 8. These values are then used to calculate the bit rate generator value for a baud rate of 9,600 bps. Baud rate cannot be attained with some operating frequencies. Table 1.82 gives the operation frequency and the baud rate that can be attained for. Table 1.82 Operation frequency and the baud rate Operation frequency (MH Z) Baud rate 9,600bps Baud rate 19,200bps Baud rate 38,400bps Baud rate 57,600bps 10MH Z 8MH Z 7.3728MH Z 6MH Z 5MH Z 4.5MH Z 4.194304MH Z 4MH Z 3.58MH Z 3MH Z 2MH Z √ : Communications possible – : Communications not possible

Appendix Standard Serial I/O Mode 2 (Flash Memory Version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 160 Software Commands Table 1.83 lists software commands. In the standard serial I/O mode 2, erase operations, programs and reading are controlled by transferring software commands via the RxD0 pin. Standard serial I/O mode 2 adds four transmission speed commands - 9,600, 19,200, 38,400 and 57,600 bps - to the software com- mands of standard serial I/O mode 1. Software commands are explained here below. Table 1.83. Software commands (Standard serial I/O mode 2) Control command 2nd byte 3rd byte 4th byte 5th byte 6th byte

6 Read lock bit status

7 Code processing function

10 Boot ROM area output

11 Baud rate 9600

12 Baud rate 19200

13 Baud rate 38400

14 Baud rate 57600

(middle) Address (middle) D0 16 SRD output Address (middle) Address (low) Size (low) Version data output Address (middle) B0 16 B1 16 B2 16 B3 16 Address (high) Address (high) SRD1 output Address (high) Address (middle) Size (high) Version data output Address (high) Data output Data input Lock bit data output Address (high) Check- sum Version data output Data output Data output Data input ID size Data input Version data output Data output Data output Data input ID1 To required number of times Version data output Data output Data output to 259th byte Data input to 259th byte To ID7 Version data output to 9th byte Data output to 259th byte FF 16 4116 A7 16 7016 5016 7116 F516 FA 16 FB 16 FC 16 B0 16 B1 16 B2 16 B3 16 When ID is not verified Not acceptable Not acceptable Not acceptable Acceptable Not acceptable Not acceptable Acceptable Not acceptable Acceptable Not acceptable Acceptable Acceptable Acceptable Acceptable 1st byte transfer Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is trans- ferred from the peripheral unit to the flash memory microcomputer. Note 2: SRD refers to status register data. SRD1 refers to status register 1 data. Note 3: All commands can be accepted when the flash memory is totally blank.

Appendix Standard Serial I/O Mode 2 (Flash Memory Version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 163 Erase All Unlocked Blocks Command This command erases the content of all blocks. Execute the erase all unlocked blocks command as explained here following. (1) Transfer the “A716” command code with the 1st byte. (2) Transfer the verify command code “D016” with the 2nd byte. With the verify command code, the erase operation will start and continue for all blocks in the flash memory. When block erasing ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. The result of the erase operation can be known by reading the status register. Figure 1.124. Timing for erasing all unlocked blocks A716 D0 16RxD0 TxD0 (M16C reception data) (M16C transmit data)

Appendix Standard Serial I/O Mode 2 (Flash Memory Version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 167 Baud Rate 9600 This command changes baud rate to 9,600 bps. Execute it as follows. (1) Transfer the "B016" command code with the 1st byte. (2) After the "B016" check code is output with the 2nd byte, change the baud rate to 9,600 bps. Figure 1.131. Timing of baud rate 9600 RxD0 TxD0 B016(M16C reception data) (M16C transmit data) B016

Appendix Standard Serial I/O Mode 2 (Flash Memory Version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 169 Example Circuit Application for The Standard Serial I/O Mode 2 The below figure shows a circuit application for the standard serial I/O mode 2. Figure 1.135. Example circuit application for the standard serial I/O mode 2 P53(BUSY) CLK0 R XD0 TXD0 CNVss Data input Data output M30201 Flash memory version VPP (1) Control pins and external circuitry will vary according to peripheral unit. For more information, see the peripheral unit manual. (2) In this example, the microprocessor mode and standard serial I/O mode are switched via a switch.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 170 SDIP52-P-600-1.78 Weight(g) JEDEC Code 5.1 Alloy 42/Cu Alloy 52P4B Plastic 52pin 600mil SDIP Symbol Min Nom Max A b c E D L Dimension in Millimeters A1 0.51 – – –3 . 8– 0.4 0.5 0.59 0.9 1.0 1.3 0.65 0.75 1.05 0.22 0.27 0.34 45.65 45.85 46.05 12.85 13.0 13.15 – 1.778 – – 15.24 – 3.0 – – 0° –1 5 ° – – 5.5 e 52 27 261 E ce1 A2A1 bb1 b2e L A SEATING PLANE D MMP QFP56-P-1010-0.65 0.59 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Alloy 42 56P6S-A Plastic 56pin 10✕ 10mm body QFP – – – – Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D A1 0.2 0.1 0.35 – –I2 1.3 – –M D 10.6 – –M E 10.6 10°0° 0.1 1.4 0.8 0.6 0.4 13.1 12.8 12.5 13.1 12.8 12.5 0.65 10.2 10.0 9.8 10.2 10.0 9.8 0.2 0.15 0.13 0.4 0.3 0.25 2.8 3.05 e e e E c H E 56 43 H D D M D M E A F A1 A2 Ly Recommended Mount Pad Detail F x – – 0.13 b x M

Peripheral Functions Usage

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Protect 172

2.1.2 Protect Operation

The following explains the protect operation. Figure 2.1.2 shows the set-up procedure. (1) Setting “1” in the write-enable bit of system clock control registers 0 and 1 causes system clock control register 0 and system clock control register 1 to be in write-enabled state. (2) The contents of system clock control register 0 and that of system clock control register 1 are changed. (3) Setting “0” in the write-enable bit of system control registers 0 and 1 causes system clock control register 0 and system control register 1 to be in write-inhibited state. (4) To change the contents of processor mode register 0 and that of processor mode register 1, follow the same steps as in dealing with system clock control registers. (5) The write-enable bit of port P4 direction register goes to “0” when the next write instruction is executed after write-enabled state is readied. Make changes in input/output immediately af- ter the instruction that sets “1” in the write-enable bit of port P4 direction register (avoid causing an interrupt). Operation

2.1.1 Overview

'Protect' is a function that causes a value held in a register to be unchanged even when a program runs away. The following is an overview of the protect function: (1) Registers affected by the protect function The registers affected by the protect function are: (a) System clock control registers 0, 1 (addresses 0006 16 and 000716) (b) Processor mode registers 0, 1 (addresses 000416 and 000516) (c) Port P4 direction register (address 03EA16) The values in registers (1) through (3) cannot be changed in write-protect state. To change values in the registers, put the individual registers in write-enabled state. (2) Protect register Figure 2.1.1 shows protect register.

2.1 Protect

Figure 2.1.1. Protect register Protect register Symbol Address When reset PRCR 000A 16 XXXXX000 2 Bit name Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : Write-inhibited 1 : Write-enabled PRC1 PRC0 PRC2 Enables writing to processor mode registers 0 and 1 (addresses 000416 and 000516) Function 0 : Write-inhibited 1 : Write-enabled Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) Enables writing to port P4 direction register (address 03EA 16) (Note) 0 : Write-inhibited 1 : Write-enabled W R Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note: Writing a value to an address after “1” is written to this bit returns the bit /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 173 Figure 2.1.2. Set-up procedure for protect function (1) Clearing the protect (set to write-enabled state) Protect register [Address 000A16] PRCR Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) 1 : Write-enabled Enables writing to port P4 direction register (address 03EA16) 0 : Write-inhibited 1 : Write-enabled b7 b0 (3) Setting the protect (set to write-inhibited state) Protect register [Address 000A16] PRCR Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) 0 : Write-inhibited Enables writing to port P4 direction register (address 03EA16) 0 : Write-inhibited 1 : Write-enabled b7 b0 (4) Clearing the protect (set to write-enabled state) Protect register [Address 000A16] PRCR Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) 0 : Write-inhibited 1 : Write-enabled Enables writing to port P4 direction register (address 03EA16) 1 : Write-enabled b7 b0 Setting system clock control register i (i = 0, 1)(2) Changes in port P4 direction register(5)

2.1.3 Precaution for Protect

(1) The write-enable bit of port P4 direction register goes to “0” when the next write instruction is executed after write-enabled state is readied. Make changes in input/output immediately af- ter the instruction that sets “1” in the write-enable bit of port P4 direction register (avoid causing an interrupt).

SINGLE -CHIP 16-BIT CMOS MICROCOMPUTER Timer A 174

2.2.1 Overview

The following is an overview for timer A, a 16-bit timer. (1) Mode Timer A operates in one of the four modes: (a) Timer mode In this mode, the internal count source is counted. Two functions can be selected: the pulse output function that reverses output from a port every time an overflow occurs, or the gate function which controls the count start/stop according to the input signal from a port. (b) Event counter mode This mode counts the pulses from the outside and the number of overflows in other timers. The free- run type, in which nothing is reloaded from the reload register, can be selected when an underflow occurs. The pulse output function can also be selected. Please refer to the timer mode explanation for details, as the operation is identical. Furthermore, Timer A has a 2-phase pulse signal processing function which generates an up count or down count in the event counter mode, depending on the phase of the two input signals. (c) One-shot timer mode In this mode, the timer is started by the trigger and stops when the timer goes to “0”. The trigger can be selected from the following 3 types: an external input signal, an overflow of the timer, or a software trigger. The pulse output function can also be selected. Please refer to the timer mode explanation for details, as the operation is identical. (d) Pulse width modulation (PWM) mode In this mode, the arbitrary pulses are successively output. Either a 16-bit fixed-period PWM mode or 8-bit variable-period mode can be selected. The trigger for initiating output can also be selected. Please refer to the one-shot timer mode explanation for details, as the operation is identical.

2.2 Timer A

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A 175 (2) Count source The internal count source can be selected from f1, f8, f32, and fC32 . Clocks f1, f8, and f32 are derived by dividing the CPU's main clock by 1, 8, and 32 respectively. Clock fC32 is derived by dividing the CPU's secondary clock by 32. (3) Frequency division ratio In timer mode or pulse width modulation mode, [the value set in the timer register + 1] becomes the frequency division ratio. In event counter mode, [the set value + 1] becomes the frequency division ratio when a down count is performed, or [FFFF 16 - the set value + 1] becomes the frequency division ratio when an up count is performed. In one-shot timer mode, the value set in the timer register be- comes the frequency division ratio. The counter overflows (or underflows) when a count source equal to a frequency division ratio is input, and an interrupt occurs. For the pulse output function, the output from the port varies (the value in the port register does not vary). (4) Reading the timer Either in timer mode or in event counter mode, reading the timer register takes out the count at that moment. Read it in 16-bit units. The data either in one-shot timer mode or in pulse width modulation mode is indeterminate. (5) Writing to the timer To write to the timer register when a count is in progress, the value is written only to the reload register. When writing to the timer register when a count is stopped, the value is written both to the reload register and to the counter. Write a value in 16-bit units. (6) Relation between the input/output to/from the timer and the direction register With the output function of the timer, set the direction register of the relevant port to input. To input an external signal to the timer, set the direction register of the relevant port to input. (7) Pins related to timer A (a) TA0 IN Input pins to timer A. (b) TA0 OUT Output pins from timer A. They become input pins to timer A when event counter mode is active.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A 177 Figure 2.2.3. Timer A-related registers (2) Symbol Address When reset TABSR 0380 16 000X00002 Count start flag Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Clock devided count start flag Timer B1 count start flag Timer B0 count start flag Timer X2 count start flag Timer X1 count start flag Timer X0 count start flag Timer A0 count start flag0 : Stops counting 1 : Starts counting CDCS TB1S TB0S Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. TX2S TX1S TX0S TA0S Symbol Address When reset TA0 0387 16,038616 Indeterminate b7 b0 b7 b0 (b15) (b8) Timer A0 register (Note 1) W R

Timer mode 0000 16 to FFFF16 Counts an internal count source Function Values that can be set
Event counter mode 0000 16 to FFFF16 Counts pulses from an external source or timer overflow
One-shot timer mode 0000 16 to FFFF16 Counts a one shot width (Note 2)
Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator
Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 16 to FF16(Note 2) (Both high-order and low-order addresses) 000016 to FFFE16 (Note 2) Note 1: Read and write data in 16-bit units. Note 2: Use MOV instruction to write to this register. /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines 0 : Stops counting 1 : Starts counting

SINGLE -CHIP 16-BIT CMOS MICROCOMPUTER Timer A 178 Figure 2.2.4. Timer A-related registers (3) TX0OS TX1OS TA0OS One-shot start flag Symbol Address When reset ONSF 0382 16 XXXX0000 2 Timer A0 one-shot start flag Timer X0 one-shot start flag Timer X1 one-shot start flag Timer X2 one-shot start flag TX2OS Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. W R 1 : Timer start When read, the value is “0” /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Timer A0 up/down flag Timer A0 two-phase pulse signal processing select bit Symbol Address When reset UDF 0384 Up/down flag (Note) Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 TA0UD 0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled When not using the two-phase pulse signal processing function, set the select bit to “0” /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note : Use MOV instruction to write to this register.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A 179 Figure 2.2.5. Timer A-related registers (4) Symbol Address When reset CPSRF 0381 16 0XXXXXXX 2 Clock prescaler reset flag Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Clock prescaler reset flag0 : No effect 1 : Prescaler is reset (When read, the value is “0”) CPSR W R Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. TA0TGL Symbol Address When reset TRGSR 0383 16 0016 Timer A0 event/trigger select bit 0 0 : Input on TA0IN is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX2 overflow is selected 1 1 : TX0 overflow is selected Trigger select register Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : Input on TX0INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TX1 overflow is selected 0 0 : Input on TX1INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX0 overflow is selected 1 1 : TX2 overflow is selected 0 0 : Input on TX2INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX1 overflow is selected 1 1 : TA0 overflow is selected Timer X0 event/trigger select bit Timer X1 event/trigger select bit Timer X2 event/trigger select bit W R TA0TGH TX0TGL TX0TGH TX1TGL TX1TGH TX2TGL TX2TGH b1 b0 b3 b2 b5 b4 b7 b6 Note: Set the corresponding port direction register to “0”(input mode). /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines

SINGLE -CHIP 16-BIT CMOS MICROCOMPUTER Timer A 180 In timer mode, choose functions from those listed in Table 2.2.1. Operations of the circled items are Item Count source Pulse output function Gate function Set-up O O O Internal count source (f1 / f8 / f32 / fc32) No pulses output Pulses output No gate function Performs count only for the period in which the TA0IN pin is at “L” level Performs count only for the period in which the TA0IN pin is at “H ” level Operation (1) Setting the count start flag to “1” causes the counter to perform a down count on the count source. (2) If an underflow occurs, the content of the reload register is reloaded, and the count continues. At this time, the timer A0 interrupt request bit goes to “1”. (3) Setting the count start flag to “0” causes the counter to hold its value and to stop.

2.2.2 Operation of Timer A (timer mode)

Table 2.2.1. Choosed functions Figure 2.2.6. Operation timing of timer mode FFFF 16 n 000016 Time Start count again Count start flag Timer A0 interrupt request bit “1” “1” Counter content (hex) n = reload register content Set to “1” by software “0” “0” Set to “1” by softwareCleared to “0” by software Cleared to “0” when interrupt request is accepted, or cleared by software (1) Start count (2) Underflow (3) Stop count

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A 181 Figure 2.2.7. Set-up procedure of timer mode Setting divide ratio Can be set to 000016 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer A0 register [Address 038716, 038616]T A 0 Start count Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 Setting count start flag Count start flag [Address 038016] TABSR Timer A0 count start flag b7 b0 Pulse output function select bit 0 : Pulse is not output (TA0OUT pin is a normal port pin) Selecting timer mode and functions Timer A0 mode register [Address 039616] TA0MR Selection of timer mode b7 b0 0000 0 0 (Must always be “0” in timer mode) Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Gate function select bit 0 0 : 0 1 : b4 b3 Gate function not available (TA0IN pin is a normal port pin)

SINGLE -CHIP 16-BIT CMOS MICROCOMPUTER Timer A 182

2.2.3 Operation of Timer A (timer mode, gate function selected)

Figure 2.2.8. Operation timing of timer mode, gate function selected In timer mode, choose functions from those listed in Table 2.2.2. Operations of the circled items are Item Count source Pulse output function Gate function Set-up O O O Internal count source(f1 / f8 / f32 / fc32) No pulses output Pulses output No gate function Performs count only for the period in which the TA0IN pin is at “L” level Performs count only for the period in which the TA0IN pin is at “H ” level Table 2.2.2. Choosed functions (1) When the count start flag is set to “1” and the TA0IN pin inputs at “H ” level, the counter performs a down count on the count source. (2) When the TA0IN pin inputs at “L” level, the counter holds its value and stops. (3) If an underflow occurs, the content of the reload register is reloaded and the count continues. At this time, the timer A0 interrupt request bit goes to “1”. (4) Setting the count start flag to “0” causes the counter to hold its value and to stop.

Make the pulse width of the signal input to the TA0IN pin not less than two cycles of the count source. Operation Note FFFF 16 n 000016 Time Count start flag Timer A0 interrupt request bit “1” “1” Counter content (hex) n = reload register content TA0 IN pin input signal (2) Stop count “0” “0” Set to “1” by software “H ” “L” (4) Stop count (1) Start count Cleared to “0” when interrupt request is accepted, or cleared by software (3) Underflow Set to “1” by software Cleared to “0” by software Start count again.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A 183 Figure 2.2.9. Set-up procedure of timer mode, gate function selected Setting divide ratio Can be set to 000016 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer A0 register [Address 038716, 038616]T A 0 Pulse output function select bit 0 : Pulse is not output (TA0OUT pin is a normal port pin) Selecting timer mode and functions Timer A0 mode register [Address 039616] TA0MR Gate function select bit 1 1 : Timer counts only when TA0IN pin is held “H ” (Note) b4 b3 Selection of timer mode b7 b0 0000 0 (Must always be “0” in timer mode) Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Note: Set the corresponding port direction register to “0” (input mode). 1 1 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 Setting count start flag Count start flag [Address 038016] TABSR Timer A0 count start flag b7 b0 Start count

SINGLE -CHIP 16-BIT CMOS MICROCOMPUTER Timer A 184 Figure 2.2.10. Operation timing of timer mode, pulse output function selected

2.2.4 Operation of Timer A (timer mode, pulse output function selected)

In timer mode, choose functions from those listed in Table 2.2.3. Operations of the circled items are dure. FFFF 16 n 000016 Time Count start flag Timer A0 interrupt request bit “1” “1” Counter content (hex) n = reload register content Pulse output from TA0 OUT pin “H ” “0” “L” “0” Set to “1” by software Set to “1” by software Cleared to “0” by software (3) Stop count Cleared to “0” when interrupt request is accepted, or cleared by software (1) Start count (2) Underflow Start count again Item Count source Pulse output function Gate function Set-up O O O Internal count source(f1 / f8 / f32 / fc32) No pulses output Pulses output No gate function Performs count only for the period in which the TA0IN pin is at “L” level Performs count only for the period in which the TA0IN pin is at “H ” level Table 2.2.3. Choosed functions (1) Setting the count start flag to “1” causes the counter to perform a down count on the count source. (2) If an underflow occurs, the content of the reload register is reloaded and the count continues. At this time, the timer A0 interrupt request bit goes to “1”. Also, the output polarity of the TA0 OUT pin reverses. (3) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the TA0 OUT pin outputs an “L” level. Operation

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A 185 Figure 2.2.11. Set-up procedure of timer mode, pulse output function selected Setting divide ratio Can be set to 000016 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer A0 register [Address 038716, 038616]T A 0 Start count Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 Pulse output function select bit (Note) 1 : Pulse is output (TA0OUT pin is a pulse output pin) Selecting timer mode and functions Timer A0 mode register [Address 039616] TA0MR Selection of timer mode b7 b0 0001 0 0 (Must always be “0” in timer mode) Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Gate function select bit 0 0 : 0 1 : b4 b3 Gate function not available (TA0IN pin is a normal port pin) Note: Set the corresponding port direction register to “1” (output mode). Setting count start flag Count start flag [Address 038016] TABSR Timer A0 count start flag b7 b0

SINGLE -CHIP 16-BIT CMOS MICROCOMPUTER Timer A 186 Figure 2.2.12. Operation timing of event counter mode, reload type selected

2.2.5 Operation of Timer A (event counter mode, reload type selected)

In event counter mode, choose functions from those listed in Table 2.2.4. Operations of the circled items procedure. (1) Setting the count start flag to “1” causes the counter to count the falling edges of the count source. (2) If an underflow occurs, the content of the reload register is reloaded, and the count continues. At this time, the timer A0 interrupt request bit goes to “1”. (3) If switching from an up count to a down count or vice versa while a count is in progress, the switch takes effect from the next effective edge of the count source. (4) Setting the count start flag to “0” causes the counter to hold its value and to stop. (5) If an overflow occurs, the content of the reload register is reloaded, and the count continues. At this time, the timer A0 interrupt request bit goes to “1”. Operation Table 2.2.4. Choosed functions Item ItemSet-up Set-up Count source Input signal to TA0IN (counting falling edges) Input signal to TA0IN (counting rising edges) Timer overflow (TB1/TX0/TX2 overflow) Count operation type Reload type Free-run type Factor for switching between up and down Content of up/down flag Input signal to TA0OUT Pulse output function No pulses output Pulses output O O O O FFFF 16 n 000016 Time Counter content (hex) n = reload register content (1) Start count Count start flag“1” Set to “1” by software “0” Timer A0 interrupt request bit “1” “0” Up/down flag “1” “0” Set to “1” by software Set to “1” by software (5) Overflow Cleared to “0” when interrupt request is accepted, or cleared by software Start count again /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines (2) Underflow /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines (3) Switch count Cleared to “0” by software (4) Stop count

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A 187 Figure 2.2.13. Set-up procedure of event counter mode, reload type selected Selecting event counter mode and functions b7 b0 Pulse output function select bit 0 : Pulse is not output (TA0OUT pin is a normal port pin) Timer A0 mode register [Address 039616] TA0MR Up/down switching cause select bit 0 : Up/down flag's content Selection of event counter mode Invalid when not using two-phase pulse signal processing Count operation type select bit 0 : Reload type 0 (Must always be “0” in event counter mode) Count polarity select bit 0 : Counts external signal's falling edge 0100 000 Setting trigger select register Trigger select register [Address 038316] TRGSR b7 b0 Timer A0 event/trigger select bit 0 0 : Input on TA0IN is selected (Note) b1 b0 Note: Set the corresponding port direction register to “0” (input mode). Setting divide ratio Can be set to 000016 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer A0 register [Address 038716, 038616]T A 0 Start count b7 b0 0 0 Up/down flag [Address 038416] UDF Timer A0 up/down flag 0 : Down count Timer A0 two-phase pulse signal processing select bit 0 : Two-phase pulse signal processing disabled Setting up/down flag Setting count start flag Count start flag [Address 038016] TABSR Timer A0 count start flag b7 b0

SINGLE -CHIP 16-BIT CMOS MICROCOMPUTER Timer A 188 Figure 2.2.14. Operation timing of event counter mode, free run type selected

2.2.6 Operation of Timer A (event counter mode, free run type selected)

In event counter mode, choose functions from those listed in Table 2.2.5. Operations of the circled items procedure. (1) Setting the count start flag to “1” causes the counter to count the falling edges of the count source. (2) Even if an underflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the timer A0 interrupt request bit goes to “1”. (3) If switching from an up count to a down count or vice versa while a count is in progress, the switch takes effect from the next effective edge of the count source. (4) Even if an overflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the timer A0 interrupt request bit goes to “1”. Item ItemSet-up Set-up Count source Input signal to TA0IN (counting falling edges) Input signal to TA0IN (counting rising edges) Timer overflow (TB1/TX0/TX2 overflow) Count operation type Reload type Free-run type Factor for switching between up and down Content of up/down flag Input signal to TA0OUT Pulse output function No pulses output Pulses output O O O O Table 2.2.5. Choosed functions Operation FFFF 16 n 000016 Time Counter content (hex) n = reload register content (1) Start count Count start flag“1” “0” Timer A0 interrupt request bit “1” Cleared to “0” when interrupt request is accepted, or cleared by software “0” Up/down flag “1” “0” Set to “1” by software (2) Underflow (3) Switch count (4) Overflow Set to “1” by software

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A 189 Figure 2.2.15. Set-up procedure of event counter mode, free run type selected Setting divide ratio Can be set to 000016 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer A0 register [Address 038716, 038616]T A 0 Start count Pulse output function select bit 0 : Pulse is not output (TA0OUT pin is a normal port pin) Selecting event counter mode and functions Timer A0 mode register [Address 039616] TA0MR Up/down switching cause select bit 0 : Up/down flag's content Selection of event counter mode Invalid when not using two-phase pulse signal processing Count operation type select bit 1 : Free-run type 0 (Must always be “0” in event counter mode) Count polarity select bit 0 : Counts external signal's falling edge b7 b0 0100 001 Setting trigger select register b7 b0 Trigger select register [Address 038316] TRGSR Timer A0 event/trigger select bit 0 0 : Input on TA0IN is selected (Note) b1 b0 Note: Set the corresponding port direction register to “0” (input mode). b7 b0 0 0 Setting up/down flag Up/down flag [Address 038416] UDF Timer A0 up/down flag 0 : Down count Timer A0 two-phase pulse signal processing select bit 0 : Two-phase pulse signal processing disabled Setting count start flag Count start flag [Address 038016] TABSR Timer A0 count start flag b7 b0

SINGLE -CHIP 16-BIT CMOS MICROCOMPUTER Timer A 190 Figure 2.2.16. Operation timing of 2-phase pulse signal process in event counter mode, normal mode selected

2.2.7 Operation of timer A (2-phase pulse signal process in event counter mode,

normal mode selected) In processing 2-phase pulse signals in event counter mode, choose functions from those listed in Table Figure 2.2.17 shows the set-up procedure. Item Count operation type 2-phase pulses process Set-up O O Reload type Free run type Normal processing 4-multiplication processing Table 2.2.6. Choosed functions (1) Setting the count start flag to “1” causes the counter to count effective edges of the count source. (2) Even if an underflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the timer A0 interrupt request bit goes to “1”. (3) Even if an overflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the timer A0 interrupt request bit goes to “1”.

The up count or down count conditions are as follows: If a rising edge is present at the TA0IN pin when the input signal level to the TA0OUT pin is “H ”, an up count is performed. If a falling edge is present at the TA0IN pin when the input signal level to the TA0OUT pin is “H ”, a down count is performed. Operation Note 000016 Count start flag Timer A0 interrupt request bit “1” “0” “1” “0” FFFF 16 Counter content (hex) Input pulse TA0 OUT “H ” “L” “H ” “L” TA0 IN Set to “1” by software Cleared to “0” when interrupt request is accepted, or cleared by software (1) Start count (2) Underflow (3) Overflow Time

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A 191 Figure 2.2.17. Set-up procedure of 2-phase pulse signal process in event counter mode, normal mode selected Setting divide ratio Can be set to 000016 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer A0 register [Address 038716, 038616]T A 0 Start count Selecting event counter mode and functions 0 (Must always be “0” when using two-phase pulse signal processing) Timer A0 mode register [Address 039616] TA0MR 1 (Must always be “1” when using two-phase pulse signal processing) Selection of event counter mode Two-phase pulse signal processing operation select bit 0 : Normal processing operation Count operation type select bit 1 : Free-run type 0 (Must always be “0” when using two-phase pulse signal processing) 0 (Must always be “0” when using two-phase pulse signal processing) b7 b0 0100 1001 Note: Set the corresponding port direction register which inputs the pulse to “0” (input mode). Two-phase pulse signal processing select bit b7 b0 Up/down flag [Address 038416] UDF Timer A0 two-phase pulse signal processing select bit 1 : Two-phase pulse signal processing enabled b7 b0 Trigger select register [Address 038316] TRIGGER 00 (Must always be “00” when using two-phase pulse signal processing) 0 0 Setting count start flag Count start flag [Address 038016] TABSR Timer A0 count start flag b7 b0

SINGLE -CHIP 16-BIT CMOS MICROCOMPUTER Timer A 192 Figure 2.2.18. Operation timing of 2-phase pulse signal process in event counter mode, multiply-by-4 mode selected

2.2.8 Operation of timer A (2-phase pulse signal process in event counter mode,

multiply-by-4 mode selected) In processing 2-phase pulse signals in event counter mode, choose functions from those listed in Table Figure 2.2.19 shows the set-up procedure. Table 2.2.7. Choosed functions Item ItemSet-up Set-up Count operation type Reload type Free run typeO Processing 2 phase pulses O Normal processing 4-multiplication processing (1) Setting the count start flag to “1” causes the counter to count effective edges of the count source. (2) Even if an underflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the timer A0 interrupt request bit goes to “1”. (3) Even if an overflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the timer A0 interrupt request bit goes to “1”.

The up count or down count conditions are as follows: Operation Note Up count Input signal to the TA0 OUT pin Input signal to the TA0 IN pin Down count Input signal to the TA0 OUT pin Input signal to the TA0 IN pin “H ” level “L” level Rising Falling Rising Falling “L” level “H ” level “H ” level “L” level Rising Falling Falling Rising “H ” level “L” level TimeSet to “1” by software 000016 Count start flag Timer A0 interrupt request bit “1” “0” “1” “0” FFFF 16 Counter content (hex) Input pulse TA0 OUT “H ” “L” “H ” “L”TA0 IN (1) Start count (2) Underflow (3) Overflow Cleared to “0” when interrupt request is accepted, or cleared by software Table 2.2.8. The up count or down count conditions

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A 193 Figure 2.2.19. Set-up procedure of2-phase pulse signal process in event counter mode, multiply-by-4 mode selected Start count Selecting event counter mode and functions 0 (Must always be “0” when using two-phase pulse signal processing) Timer A0 mode register [Address 039616] TA0MR 1 (Must always be “1” when using two-phase pulse signal processing) Selection of event counter mode Two-phase pulse signal processing operation select bit 1 : Multiply-by-4 processing operation Count operation type select bit 1 : Free-run type 0 (Must always be “0” when using two-phase pulse signal processing) 0 (Must always be “0” when using two-phase pulse signal processing) b7 b0 0100 10 11 Note: Set the corresponding port direction register which inputs the pulse to “0” (input mode). Setting divide ratio Can be set to 000016 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer A0 register [Address 038716, 038616]T A 0 Two-phase pulse signal processing select bit b7 b0 Up/down flag [Address 038416] UDF Timer A0 two-phase pulse signal processing select bit 1 : Two-phase pulse signal processing enabled b7 b0 Trigger select register [Address 038316] TRIGGER 00 (Must always be “00” when using two-phase pulse signal processing) 0 0 Setting count start flag Count start flag [Address 038016] TABSR Timer A0 count start flag b7 b0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 194

2.2.9 Operation of Timer A (one-shot timer mode)

Figure 2.2.20. Operation timing of one-shot mode In one-shot timer mode, choose functions from those listed in Table 2.2.9. Operations of the circled items procedure. Operation(1) Setting the one-shot start flag to “1” with the count start flag set to “1” causes the counter to perform a down count on the count source. At this time, the TA0 OUT pin outputs an “H ” level. (2) The instant the value of the counter becomes “000016”, the TA0OUT pin outputs an “L” level, and the counter reloads the content of the reload register and stops counting. At this time, the timer A0 interrupt request bit goes to “1”. (3) If a trigger occurs while a count is in progress, the counter reloads the value in the reload register again and continues counting. The reload timing is in step with the next count source input after the trigger. (4) Setting the count start flag to “0” causes the counter to stop and to reload the content of the reload register. Also, the TA0 OUT pin outputs an “L” level. At this time, the timer A0 interrupt request bit goes to “1”. Item Count source Pulse output function Count start condition Set-up O O O Internal count source (f1 / f8 / f32 / fc32) No pulses output Pulses output External trigger input (falling edge of input signal to the TA0IN pin) External trigger input (rising edge of input signal to the TA0IN pin) Timer overflow (TB1/TX0/TX2 overflow) Writing “1” to the one-shot start flag Table 2.2.9. Choosed functions FFFF 16 n 000116 Timer A0 interrupt request bit Counter content (hex) n = reload register content Reload One-shot pulse output from TA0 OUT pin “H ” 1 / fi X (n) “L” Time Reload 1 / fi X (n+1) Write signal to one-shot start flag “1” “0” Count start flag “1” “0” (1) Start count Cleared to “0” when interrupt request is accepted, or cleared by software (2) Stop count (3) Start count (4) Stop countStart count Reload Set to “1” by software Cleared to “0” by software

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 195 Figure 2.2.21. Set-up procedure of one-shot mode Setting one-shot timer's time Can be set to 000116 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer A0 register [Address 038716, 038616]T A 0 Start count Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 Clearing timer A0 interrupt request bit Timer A0 interrupt control register [Address 005516] TA0IC Interrupt request bit b7 b0 Refer to 'Precaution for Timer A (one shot timer mode)' Setting count start flag Count start flag [Address 038016] TABSR Timer A0 count start flag b7 b0 Setting one-shot start flag One-shot start flag [Address 038216] ONSF Timer A0 one-shot start flag b7 b0 Pulse output function select bit 1 : Pulse is output (Note) Selecting one-shot timer mode and functions Timer A0 mode register [Address 039616] TA0MR External trigger select bit When internal is selected, this bit can be “1” or “0” Selection of one-shot timer mode b7 b0 1001 0 0 (Must always be “0” in one-shot timer mode) Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Trigger select bit 0 : When the one-shot start flag is set “1” Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Note: Set the corresponding port direction register to “1” (output mode).

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 196 In one-shot timer mode, choose functions from those listed in Table 2.2.10. Operations of the circled procedure.

2.2.10 Operation of Timer A (one-shot timer mode, external trigger selected)

Figure 2.2.22. Operation timing of one-shot mode, external trigger selected Operation(1) If the TA0IN pin input level changes from “L” to “H ” with the count start flag set to “1”, the counter performs a down count on the count source. At this time, the TA0OUT pin output level goes to “H ” level. (2) If the value of the counter becomes “000016”, the TA0OUT pin outputs an “L” level, and the counter reloads the content of the reload register and stops counting. At this time, the timer A0 interrupt request bit goes to “1”. (3) If a trigger occurs while a count is in progress, the counter reloads the value of the reload register again and continues counting. The reload timing is in step with the next count source input after the trigger. (4) Setting the count start flag to “0” causes the counter to stop and to reload the content of the reload register. Also, the TA0 OUT pin outputs an “L” level. At this time, the timer A0 interrupt request bit goes to “1”. Item Count source Pulse output function Count start condition Set-up O O O Internal count source (f1 / f8 / f32 / fc32) No pulses output Pulses output External trigger input (falling edge of input signal to the TA0IN pin) External trigger input (rising edge of input signal to the TA0IN pin) Timer overflow (TB1/TX0/TX2 overflow) Writing “1” to the one-shot start flag Table 2.2.10. Choosed functions FFFF 16 n 000116 Timer A0 interrupt request bit Counter content (hex) n = reload register content ReloadReload (4) Stop count One-shot pulse output from TA0 OUT pin “H ” 1 / fi X (n) “L” 1 / fi X (n+1) TA0 IN pin input signal “H ” “L” “1” Cleared to “0” when interrupt request is accepted, or cleared by software “0” Count start flag “1” “0” (2) Stop count (1) Start count (3) Start count Time Reload Start count Set to “1” by software Trigger during count Cleared to “0” by software

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 197 Figure 2.2.23. Set-up procedure of one-shot mode, external trigger selected Setting one-shot timer's time Can be set to 000116 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer A0 register [Address 038716, 038616]T A 0 Start count Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 Clearing timer A0 interrupt request bit Timer A0 interrupt control register [Address 005516] TA0IC Interrupt request bit b7 b0 Refer to 'Precaution for Timer A (one shot timer mode)' Setting count start flag Count start flag [Address 038016] TABSR Timer A0 count start flag b7 b0 Trigger select register [Address 038316] TRGSR b7 b0 Timer A0 event/trigger select bit 0 0 : Input on TA0IN is selected (Note 2) b1 b0 Note 2: Set the corresponding port direction register to “0”(input mode). 0 0 Setting Trigger select register Pulse output function select bit 1 : Pulse is output (Note 1) Selecting one-shot timer mode and functions Timer A0 mode register [Address 039616] TA0MR External trigger select bit 1 : Rising edge of TA0IN pin's input signal Selection of one-shot timer mode b7 b0 10111 0 (Must always be “0” in one-shot timer mode) Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Trigger select bit 1 : Selected by event/trigger select register Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Note 1: Set the corresponding port direction register to “1”(output mode).

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 198 In pulse width modulation mode, choose functions from those listed in Table 2.2.11. Operations of the set-up procedure.

2.2.11 Operation of Timer A (pulse width modulation mode, 16-bit PWM mode selected)

Figure 2.2.24. Operation timing of pulse width modulation mode, 16-bit PWM mode selected Item Count source PWM mode Count start condition Set-up O O O Internal count source (f1 / f8 / f32 / fc32) 16-bit PWM 8-bit PWM External trigger input (falling edge of input signal to the TA0IN pin) External trigger input (rising edge of input signal to the TA0IN pin) Timer overflow (TB1/TX0/TX2 overflow) Table 2.2.11. Choosed functions (1) If the TA0IN pin input level changes from “L” to “H ” with the count start flag set to “1”, the counter performs a down count on the count source. Also, the TA0OUT pin outputs an “H ” level. (2) The TA0OUT pin output level changes from “H ” to “L” when a set time period elapses. At this time, the timer A0 interrupt request bit goes to “1”. (3) The counter reloads the content of the reload register every time PWM pulses are output for one cycle, and continues counting. (4) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the TA0 OUT outputs an “L” level.

PWM pulse cycle is (216 -1)/fi, whereas H level duration is n/fi. However, when “000016” is set for the timer A0 register, the PWM output is “L” level for the entire period, and an interrupt request is generated for every PWM output cycle. Also, when “FFFF 16” is set for the timer A0 register, the PWM output is “H ” level for the entire period, and an interrupt request is generated for every PWM output cycle. (fi: Count source frequency f1, f8, f32, fC32 n: Timer value) Operation Note Count source TA0 IN pin input signal PWM pulse output from TA0OUT pin Timer A0 interrupt request bit Count start flag 1 / fi X (2 –1) Conditions: Reload register = 000316, external trigger (rising edge of TA0IN pin input signal) is selected Trigger is not generated by this signal “H ” “H ” “L” “L” “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software 1 / fi X n “1” “0” Set to “1” by software (1) Start count (2) Output level “H ” to “L” Note: n = 000016 to FFFE16 (3) One period is complete (4) Stop count Cleared to “0” by software

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 199 Setting PWM pulse's “H ” level width Can be set to 000016 to FFFE16 b7 b0 (b15) (b8) b7 b0 Timer A0 register [Address 038716, 038616]T A 0 Start count Setting count starts flag Count start flag [Address 038016] TABSR Timer A0 count start flag b7 b0 Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 1 (Must always be “1” in PWM mode) Selecting PWM mode and functions Timer A0 mode register [Address 039616] TA0MR External trigger select bit 1 : Rising edge of TA0IN pin's input signal (Note 1) Selection of PWM mode b7 b0 11111 16/8-bit PWM mode select bit 0 : Functions as a 16-bit pulse width modulator b7 b6 Count source select bit 0 0 : f1 0 1 : f81 0 : f321 1 : fC32 Trigger select bit 1 : Selected by event/trigger select register Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Note 1: Set the corresponding port direction register which outputs the pulse to “1” (output mode). Clearing timer A0 interrupt request bit Timer A0 interrupt control register [Address 005516] TA0IC Interrupt request bit b7 b0 Refer to 'Precaution for Timer A (pulse width modulation mode)' b7 b0 Timer A0 event/trigger select bit 0 0 : Input on TA0IN is selected (Note 2) b1 b0 Note 2: Set the corresponding port direction register to “0” (input mode). Trigger select register [Address 038316] TRGSR Setting trigger select register Figure 2.2.25. Set-up procedure of pulse width modulation mode, 16-bit PWM mode selected

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 200

2.2.12 Operation of Timer A (pulse width modulation mode, 8-bit PWM mode selected)

Figure 2.2.26. Operation timing of pulse width modulation mode, with 8-bit PWM mode selected In pulse width modulation mode, choose functions from those listed in Table 2.2.12. Operations of the set-up procedure. Item Count source PWM mode Count start condition Set-up O O O Internal count source (f1 / f8 / f32 / fc32) 16-bit PWM 8-bit PWM External trigger input (falling edge of input signal to the TA0IN pin) External trigger input (rising edge of input signal to the TA0IN pin) Timer overflow (TB1/TX0/TX2 overflow) Table 2.2.12. Choosed functions (1) If the TA0IN pin input level changes from “H ” to “L” with the count start flag set to “1”, the counter performs a down count on the count source. Also, the TA0OUT pin outputs an “H ” level. (2) The TA0OUT pin output level changes from “H ” to “L” when a set time period elapses. At this time, the timer A0 interrupt request bit goes to “1”. (3) The counter reloads the content of the reload register every time PWM pulses are output for one cycle, and continues counting. (4) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the TA0 OUT pin outputs an “L” level.

PWM pulse cycle is (m + 1( x (28 -1)/fi, whereas “H ” level duration is n x (m + 1)/fi. However, when “0016” is set for the significant 8 bits of the timer A0 register, the PWM output is “L” level for the entire period, and an interrupt request is generated for every PWM output cycle. Also, when “FF16” is set for the significant 8 bits of the timer A0 register, the PWM output is “H ” level for the entire period, and an interrupt request is generated for every PWM output cycle. (fi: Count source frequency f 1, f8, f32, fC32 n: Timer value) Operation Note Count source (Note 1) Reload register high-order 8 bits = 0216 Reload register low-order 8 bits = 0216 External trigger (falling edge of TA0IN pin input signal) is selected TA0 IN pin input Underflow signal of 8-bit prescaler (Note 2) PWM pulse output from TA0 OUT pin “H ” “H ” “L” “L” Timer A0 interrupt request bit /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines “H ” “L” “1” “0” Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: m = 00 16 to FF16; n = 0016 to FF16. 1 / fi X (m + 1) X n Count start flag “1” “0” (1) Start count (2) Output level “H ” to “L” Cleared to “0” when interrupt request is accepted, or cleared by software (3) (4) Stop count 1 / fi X (m+1) Conditions: One period is complete

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 201 Figure 2.2.27. Set-up procedure of pulse width modulation mode, 8-bit PWM mode selected Start count Setting PWM pulse's period and “H ” level width Can be set to 0016 to FE16 b7 b0 (b15) (b8) b7 b0 Timer A0 register [Address 038716, 038616]T A 0 Can be set to 0016 to FE16 Setting trigger select register Trigger select register [Address 038316] TRGSR b7 b0 Timer A0 event/trigger select bit 0 0 : Input on TA0IN is selected (Note 2) b1 b0 Note 2: Set the corresponding port direction register to “0” (input mode). Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 1 (Must always be “1” in PWM mode) Selecting PWM mode and function Timer A0 mode register [Address 039616] TA0MR External trigger select bit 0 : Falling edge of TA0IN pin's input signal (Note 1) Selection of PWM mode b7 b0 11011 16/8-bit PWM mode select bit 1: Functions as an 8-bit pulse width modulator b7 b6 Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Trigger select bit 1 : Selected by event/trigger select register Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Note 1: Set the corresponding port direction register which outputs the pulse to “1” (output mode). Clearing timer A0 interrupt request bit Timer A0 interrupt control register [Address 005516 ] TA0IC Interrupt request bit b7 b0 Refer to 'Precaution for Timer A (pulse width modulation mode)' Setting count start flag Count start flag [Address 038016] TABSR Timer A0 count start flag b7 b0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A 202

2.2.13 Precautions for Timer A (timer mode)

Figure 2.2.28. Reading timer A0 register (1) To clear reset, the count start flag is set to “0”. Set a value in the timer A0 register, then set the flag to “1”. (2) Reading the timer A0 register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer A0 register with the reload timing shown in Figure 2.2.28 gets “FFFF 16”. Reading the timer A0 register after setting a value in the timer A0 register with a count halted but before the counter starts counting gets a proper value. 210 n n – 1Counter value (Hex.) 21 0 F F F F n – 1Read value (Hex.) Reload Time n = reload register content

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 203 (1) To clear reset, the count start flag is set to “0”. Set a value in the timer A0 register, then set the flag to “1”. (2) Reading the timer A0 register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer A0 register with the reload timing shown in Figure 2.2.29 gets “FFFF 16” by underflow or “000016” by overflow. Reading the timer A0 register after setting a value in the timer A0 register with a count halted but before the counter starts counting gets a proper value. (3) Please note the standards for the differences between the 2 pulses used in the 2-phase pulse signals input signals to the TA0 IN pin and TA0OUT pin as shown in Figure 2.2.30. (4) When free run type is selected, if count is stopped, set a value in the timer A0 register again.

2.2.14 Precautions for Timer A (event counter mode)

Figure 2.2.30. Standard of 2-phase pulses 210 n n – 1Counter value (Hex.)

210 FFFFRead value

(Hex.) Reload Time n = reload register content (1) Down count FFFD FFFE FFFF n n + 1Counter value (Hex.) FFFD FFFE FFFF 0000 n + 1Read value (Hex.) /LiteDiagLines /LiteDiagLines Reload Time n = reload register content (2) Up count n – 1 Figure 2.2.29. Reading timer A0 register T2 T3 TA2 OUT TA3 OUT TA4 OUT TA2 IN TA3 IN TA4 IN (Min.) T2, T3 (Min.) Vcc = 5V, f(XIN) = 10MHz 800ns 200ns (Min.) T2, T3 (Min.) Vcc = 3V, f(XIN) = 7MHz, one-wait 2µs 500ns

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A 204 (1) To clear reset, the count start flag is set to “0”. Set a value in the timer A0 register, then set the flag to “1”. (2) Setting the count start flag to “0” while a count is in progress causes as follows:

The counter stops counting and a content of reload register is reloaded.
The TA0OUT pin outputs “L” level.
The interrupt request generated and the timer A0 interrupt request bit goes to “1”. (3) The output from the one-shot timer synchronizes with the count source generated internally. Therefore, when an external trigger has been selected, a delay of one cycle of count source as a maximum occurs between the trigger input to the TA0IN pin and the one-shot timer output. (4) The timer A0 interrupt request bit goes to “1” if the timer's operation mode is set using any of the following procedures:
Selecting one-shot timer mode after reset.
Changing operation mode from timer mode to one-shot timer mode.
Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use timer A0 interrupt (interrupt request bit), set timer A0 interrupt request bit to “0” after the above listed changes have been made. (5) If a trigger occurs while a count is in progress, after the counter performs one down count following the reoccurrence of a trigger, the reload register contents are reloaded, and the count continues. To generate a trigger while a count is in progress, generate the second trigger after an elapse longer than one cycle of the timer's count source after the previous trigger occurred.

2.2.15 Precautions for Timer A (one-shot timer mode)

Note: The above applies when an external trigger (falling edge of TA0IN pin input signal) is selected. TA0 IN pin input signal“H ” “L” Count source Trigger input Start one-shot pulse output One-shot pulse output from TA0OUT pin Figure 2.2.31. One-shot timer delay

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 205 (1) To clear reset, the count start flag is set to “0”. Set a value in the timer A0 register, then set the flag to “1”. (2) The timer A0 interrupt request bit becomes “1” if setting operation mode of the timer in com- pliance with any of the following procedures:

Selecting PWM mode after reset.
Changing operation mode from timer mode to PWM mode.
Changing operation mode from event counter mode to PWM mode. Therefore, to use timer A0 interrupt (interrupt request bit), set timer A0 interrupt request bit to “0” after the above listed changes have been made. (3) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop counting. If the TA0OUT pin is outputting an “H ” level in this instance, the output level goes to “L”, and the timer A0 interrupt request bit goes to “1”. If the TA0OUT pin is outputting an “L” level in this instance, the level does not change, and the timer A0 interrupt request bit does not becomes “1”. (4) Normal PWM output is restored according to the interrupt request generate timing, both in the case of 16-bit PWM and 8-bit PWM, when PWM output is either “H ” or “L” level for the entire period. This holds only when a value other than “000016” or “FFFF 16” is set during 16- bit PWM, or a value other than “0016” or “FF16” is set during 8-bit PWM.

2.2.16 Precautions for Timer A (pulse width modulation mode)

Figure 2.2.32. Operation timing of PWM output mode Timer A0 interrupt request bit PWM pulse output from TA0OUT pin "H" 1 / fi X (n) "L" "1" "0" Timer A0 interrupt request bit PWM pulse output from TA0OUT pin "H" 1 / fi X (n) "L" "1" "0" Writing to the timer A0 Writing to the timer A0 Normal PWM restored here Cleared to “0” when interrupt request is accepted, or cleared by software When PWM output is “H ” level for the entire period Cleared to “0” when interrupt request is accepted, or cleared by software When PWM output is “L” level for the entire period

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 206

2.3 Timer B

2.3.1 Overview

The following is an overview for timer B, a 16-bit timer. (1) Mode Timer B operates in one of three modes: (a) Timer mode The internal count source is counted. (b) Event counter mode The number of pulses coming from outside and the number of the timer overflows are counted. (c) Pulse period measurement/pulse width measurement mode External pulse period or external pulse widths are measured. If pulse period measurement mode is selected, the periods of input pulses are continuously measured. If pulse width measurement mode is selected, widths of “H ” level pulses and those of “L” level pulses are continuously measured. (2) Count source An internal count source can be selected from f 1, f8, f32, and fC32 . f1, f8, and f32 are clocks obtained by dividing the CPU main clock by 1, 8, and 32 respectively. fC32 is the clock obtained by dividing the CPU secondary clock by 32. (3) Frequency division ratio The frequency division ratio equals [the value set in the timer register + 1]. The counter underflows when a count source equal to a frequency division ratio is input, and an interrupt request occurs. (4) Reading the timer In timer mode or event counter mode, the count value at the time of reading the timer register will be read. Read the register in 16-bit increments. In both the pulse period measurement mode and pulse width measurement mode, an indeterminate value is read until the second effective edge is input after a count is started, otherwise, the measurement results are read. (5) Writing to the timer When writing to the timer register while a count is in progress, the value is written only to the reload register. When writing to the timer register while a count has stopped, the value is written both to the reload register and the count. Write the value in 16-bit increments. The timer register cannot be written to in either the pulse period measurement mode or the pulse width measurement mode.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 208 Figure 2.3.2. Timer B-related registers (1) Timer Bi mode register Symbol Address When reset TBiMR(i = 0, 1) 039B16, 039C16 00XX0000 2 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/pulse width measurement mode 1 1 : Inhibited b1 b0 TCK1 MR3 MR2 MR1 TMOD1 MR0 TMOD0 TCK0 Function varies with each operation mode Count source select bit (Function varies with each operation mode) Operation mode select bit (Note 1) (Note 2) Note 1: Timer B0. Note 2: Timer B1. Note 3: Must set“00”to operation mode select bit ofM30200 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 209 Symbol Address When reset CPSRF 0381 16 0XXXXXXX 2 Clock prescaler reset flag Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Clock prescaler reset flag0 : No effect 1 : Prescaler is reset (When read, the value is “0”) CPSR Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. /LiteDiagLines/LiteDiagLines Symbol Address When reset TB0 0391 16, 039016 Indeterminate TB1 0393 16, 039216 Indeterminateb7 b0 b7 b0 (b15) (b8) Timer Bi register (Note) W R

Pulse period / pulse width measurement mode Measures a pulse period or width
Timer mode 0000 16 to FFFF16 Counts the timer's period Function Values that can be set
Event counter mode 0000 16 to FFFF16 Counts external pulses input or a timer overflow Note1: Read and write data in 16-bit units. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines Symbol Address When reset TABSR 0380 16 000X00002 Count start flag Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Clock devided count start flag Timer B1 count start flag Timer B0 count start flag Timer X2 count start flag Timer X1 count start flag Timer X0 count start flag Timer A0 count start flag0 : Stops counting 1 : Starts counting CDCS TB1S TB0S Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. TX2S TX1S TX0S TA0S /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines 0 : Stops counting 1 : Starts counting Figure 2.3.3. Timer B-related registers (2)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 210 In timer mode, choose functions from those listed in Table 2.3.1. Operations of the circled items are

2.3.2 Operation of Timer B (timer mode)

O Internal count source (f1 / f8 / f32 / fc32) Operation Table 2.3.1. Choosed functions (1) Setting the count start flag to “1” causes the counter to perform a down count on the count source. (2) If an underflow occurs, the content of the reload register is reloaded, and the counter contin- ues counting. At this time, the timer Bi interrupt request bit goes to “1”. (3) Setting the count start flag to “0” causes the counter to hold its value and to stop. Figure 2.3.4. Operation timing of timer mode FFFF 16 n 000016 Time Count start flag Timer Bi interrupt request bit “1” “1” Counter content (hex) n = reload register content Set to “1” by software “0” “0” Set to “1” by softwareCleared to “0” by software (2) Underflow (3) Stop count(1) Start count Cleared to “0” when interrupt request is accepted, or cleared by software Start count again

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 211 Figure 2.3.5. Set-up procedure of timer mode Setting divide ratio Can be set to 000016 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer B0 register [Address 039116, 039016]T B 0 Timer B1 register [Address 039316, 039216]T B 1 Start count Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 Setting count start flag Count start flag [Address 038016] TABSR Timer B0 count start flag Timer B1 count start flag b7 b0 Selecting timer mode and functions Invalid in timer mode Can be “0” or “1” Timer Bi mode register (i=0 , 1) [Address 039B16, 039C16] TBiMR (i=0 to 2) Selection of timer mode b7 b0 Fixed to “0” in timer mode Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 212 In event counter mode, choose functions from those listed in Table 2.3.2. Operations of the circled items are

2.3.3 Operation of Timer B (event counter mode)

Count source Input signal to the TBiIN pin (counting falling edges) Timer overflow(TBj overflow) O Input signal to the TBiIN pin (counting rising edges) Input signal to the TBiIN pin (counting rising edges and falling edges) Operation Table 2.3.2. Choosed functions Figure 2.3.6. Operation timing of event counter mode FFFF 16 n 000016 Time Count start flag Timer Bi interrupt request bit “1” “1” Counter content (hex) n = reload register content Set to “1” by software “0” “0” Set to “1” by softwarCleared to “0” by software (1) Start count (2) Underflow (3) Stop count Cleared to “0” when interrupt request is accepted, or cleared by software Start count again (1) Setting the count start flag to “1” causes the counter to count the falling edges of the count source. (2) If an underflow occurs, the content of the reload register is reloaded, and the count continues. At this time, the timer Bi interrupt request bit goes to “1”. (3) Setting the count start flag to “0” causes the counter to hold its value and to stop.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 213 Figure 2.3.7. Set-up procedure of event counter mode Setting divide ratio Can be set to 000016 to FFFF16 (n) b7 b0 (b15) (b8) b7 b0 Timer B0 register [Address 039116, 039016]T B 0 Timer B1 register [Address 039316, 039216]T B 1 Start count Selecting event counter mode and functions Timer Bi mode register (i=0, 1) [Address 039B16, 039C16] TBiMR (i=0, 1) Selection of event counter mode b7 b0 Fixed to “0” in event counter mode Event clock select 0 : Input from TBiIN pin (Note) 0 0 0 Count polarity select bit 0 0 : Counts external signal falling edges b3 b2 Note: Set the corresponding port direction register to “0” (input mode). Setting count start flag Count start flag [Address 038016] TABSR Timer B0 count start flag Timer B1 count start flag b7 b0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 214 In pulse period/pulse width measurement mode, choose functions from those listed in Table 2.3.3. Op- erations of the circled items are described below. Figure 2.3.8 shows the operation timing, and Figure 2.3.9 shows the set-up procedure.

2.3.4 Operation of Timer B (pulse period measurement mode)

Figure 2.3.8. Operation timing of pulse period measurement mode Item Set-up Count source Internal count source (f1 / f8 / f32 / fc32) Pulse width measurement (interval between measurement pulse falling edge to rising edge, and between rising edge to falling edge) O Pulse period measurement (interval between measurement pulse falling edge to falling edge) Pulse period measurement (interval between measurement pulse rising edge to rising edge) OMeasurement mode Table 2.3.3. Choosed functions Operation Note (1) Setting the count start flag to “1” causes the counter to start counting the count source. (2) If a measurement pulse changes from “H ” to “L”, the value of the counter goes to “000016”, and measurement is started. In this instance, an indeterminate value is transferred to the reload register. The timer Bi interrupt request does not generate. (3) If a measurement pulse changes from “H ” to “L” again, the value of the counter is transferred to the reload register, and the timer Bi interrupt request bit goes to “1”. Then the value of the counter becomes “000016”, and the measurement is started again.

The timer Bi interrupt request bit goes to “1” when an effective edge of a measurement pulse is input or timer Bi is overflowed. The factor of interrupt request can be determined by use of the timer Bi overflow flag within the interrupt routine.
The value of the counter at the beginning of a count is indeterminate. Thus there can be in- stances in which the timer Bi overflow flag goes to “1” immediately after a count is performed.
The timer Bi overflow flag goes to “0” if timer Bi mode register is written to when the count start flag is “1”. This flag cannot be set to “1” by software. Count source Measurement pulse Count start flag Timer Bi interrupt request bit Timing at which counter reaches “0000 16” “1” “H ” “1” Transfer (indeterminate value)Reload register ← counter transfer timing “L” “0” “0” Timer Bi overflow flag“1” “0” Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. Measurement of pulse time interval from falling edge to falling edge Transfer (measured value) Cleared to “0” when interrupt request is accepted, or cleared by software (1) Start count (2) Start measurement(3) Start measurement again (Note 1) (Note 1) (Note 2)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 215 Start count Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 Selecting pulse period / pulse width measurement mode and functions Timer Bi mode register (i=0 , 1) [Address 039B16, 039C16] TBiMR (i=0, 1) Selection of pulse period / pulse width measurement mode b7 b0 Timer Bi overflow flag 0 : Timer did not overflow 1 : Timer has overflowed Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Measurement mode select bit 0 0 : Pulse period measurement (Interval between measurement pulse falling edge to falling edge) b3 b2 0 0 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Note: Set the corresponding port direction register which sets the measurement pulse to “0” (input mode). Setting count start flag Count start flag [Address 038016] TABSR Timer B0 count start flag Timer B1 count start flag b7 b0 Clearing overflow flag Timer Bi mode register (i=0, 1) [Address 039B16 to 039D16] TBiMR (i=0, 1) b7 b0 Timer Bi overflow flag 0 : Timer did not overflow Figure 2.3.9. Set-up procedure of pulse period measurement mode

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 216 In pulse period/pulse width measurement mode, choose functions from those listed in Table 2.3.4. Op- erations of the circled items are described below. Figure 2.3.10 shows the operation timing, and Figure 2.3.11 shows the set-up procedure.

2.3.5 Operation of Timer B (pulse width measurement mode)

Figure 2.3.10. Operation timing of pulse width measurement mode Operation Note Item Set-up Count source Internal count source (f1 / f8 / f32 / fc32) Pulse width measurement (interval between measurement pulse falling edge to rising edge, and between rising edge to falling edge) O Pulse period measurement (interval between measurement pulse falling edge to falling edge) Pulse period measurement (interval between measurement pulse rising edge to rising edge) O Measurement mode Table 2.3.4. Choosed functions (1) Setting the count start flag to “1” causes the counter to start counting the count source. (2) If an effective edge of a pulse to be measured is input, the value of the counter goes to “000016”, and measurement is started. In this instance, an indeterminate value is transferred to the reload register. The timer Bi interrupt request does not generate. (3) If an effective edge of a pulse to be measured is input again, the value of the counter is transferred to the reload register, and the timer Bi interrupt request bit goes to “1”. Then the value of the counter becomes “000016”, and measurement is started again.

The timer Bi interrupt request bit goes to “1” when an effective edge of a pulse to be measured is input or timer Bi is overflows. The factor of interrupt request can be determined by use of the timer Bi overflow flag within the interrupt routine.
The value of the counter at the beginning of a count is indeterminate. Thus there can be in- stances in which the timer Bi overflow flag goes to “1” immediately after a count is performed.
The timer Bi overflow flag goes to “0” if timer Bi mode register is written to when the count start flag is “1”. This flag cannot be set to “1” by software. Measurement pulse “H ” Count source Reload register ← counter transfer timing Count start flag Timer Bi interrupt request bit Timing at which counter reaches “000016” “1” “1” “L” “0” “0” Timer Bi overflow flag “1” “0” Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. (Note 1)(Note 1)(Note 1) (Note 2) (1) Start count (2) Start measurement (3) Start measurement again Cleared to “0” when interrupt request is accepted, or cleared by software Transfer (indeterminate value) Transfer(measured value) (Note 1)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 217 Figure 2.3.11. Set-up procedure of pulse width measurement mode Start count Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 Selecting pulse period / pulse width measurement mode and functions Timer Bi mode register (i=0, 1) [Address 039B16, 039C16] TBiMR (i=0 , 1) Selection of pulse period / pulse width measurement mode b7 b0 Timer Bi overflow flag 0 : Timer did not overflow 1 : Timer has overflowed Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Measurement mode select bit 1 0 : Pulse width measurement (Interval between measurement pulse falling edge to rising edge, and between rising edge to falling edge) b3 b2 0 1 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Note: Set the corresponding port direction register which sets the measurement pulse to “0” (input mode). Setting count start flag Count start flag [Address 038016] TABSR Timer B0 count start flag Timer B1 count start flag b7 b0 Clearing overflow flag Timer Bi mode register (i=0, 1) [Address 039B16, 039C16] TBiMR (i=0, 1) b7 b0 Timer Bi overflow flag 0 : Timer did not overflow

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 218 (1) To clear reset, the count start flag is set to “0”. Set a value in the timer Bi register, then set the flag to “1”. (2) Reading the timer Bi register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Bi register with the reload timing shown in Figure 2.3.12 gets “FFFF 16”. Reading the timer Bi register after setting a value in the timer Bi regis- ter with a count halted but before the counter starts counting gets a proper value.

2.3.6 Precautions for Timer B (timer mode, event counter mode)

Figure 2.3.12. Reading timer Bi register 21 0 nn – 1Counter value (Hex.) 21 0 FFFF n – 1Read value (Hex.) Reload Time n = reload register content

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 219 (1) The timer Bi interrupt request bit goes to “1” when an effective edge of a measurement pulse is input or timer Bi is overflowed. The factor of interrupt request can be determined by use of the timer Bi overflow flag within the interrupt routine. (2) If the timer overflow occurs simultaneously with the input of a measurement pulse, and if the interrupt factor cannot be determined from the timer Bi overflow flag, connect the timers and count the number of overflows. (3) When reset, the timer Bi overflow flag goes to “1”. This flag can be set to “0” by writing to the timer Bi mode register when the count start flag is “1”. (4) Use the timer Bi interrupt request bit to detect only overflows. Use the timer Bi overflow flag only to determine the interrupt factor within the interrupt routine. (5) When the first effective edge is input after a count is started, an indeterminate value is trans- ferred to the reload register. At this time, timer Bi interrupt request is not generated. (6) The value of the counter is indeterminate at the beginning of a count. Therefore the timer Bi overflow flag may go to “1” immediately after a count is started. (7) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt request bit goes to “1”. (8) If the input signal to the TBi IN pin is affected by noise, precise measurement may not be performed in some cases. It is recommended to see that measurements fall within a specific range by use of software. (9) For pulse width measurement, pulse widths are successively measured. Use software to check whether the measurement result is an “H ” level width or an “L” level width.

2.3.7 Precautions for Timer B (pulse period/pulse width measurement mode)

SINGLE -CHIP 16-BIT CMOS MICROCOMPUTER Timer X 220

2.4.1 Overview

The following is an overview for timer X, a 16-bit timer. (1) Mode Timer X operates in one of the four modes: (a) Timer mode In this mode, the internal count source is counted. Two functions can be selected: the pulse output function that reverses output from a port every time an overflow occurs, or the gate function which controls the count start/stop according to the input signal from a port. (b) Event counter mode This mode counts the pulses from the outside and the number of overflows in other timers. The free- run type, in which nothing is reloaded from the reload register, can be selected when an underflow occurs. The pulse output function can also be selected. (c) One-shot timer mode In this mode, the timer is started by the trigger and stops when the timer goes to “0”. The trigger can be selected from the following 3 types: an external input signal, an overflow of the timer, or a software trigger. (d) Pulse period measurement/pulse width measurement mode External pulse period or external pulse widths are measured. If pulse period measurement mode is selected, the periods of input pulses are continuously measured. If pulse width measurement mode is selected, widths of “H ” level pulses and those of “L” level pulses are continuously measured. (d) Pulse width modulation (PWM) mode In this mode, the arbitrary pulses are successively output. Either a 16-bit fixed-period PWM mode or 8-bit variable-period mode can be selected. The trigger for initiating output can also be selected. (2) Count source The internal count source can be selected from f1, f 8, f32, and fC32 . Clocks f1, f8, and f32 are derived by dividing the CPU's main clock by 1, 8, and 32 respectively. Clock fC32 is derived by dividing the CPU's secondary clock by 32.

2.4 Timer X

SINGLE -CHIP 16-BIT CMOS MICROCOMPUTER Timer X 222 Figure 2.4.2. Timer X-related registers (1) Timer Xi mode register Symbol Address When reset TXiMR(i = 0 to 2) 039716 to 039916 0016 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode or pulse period/ pulse width measurement mode 1 1 : Pulse width modulation (PWM) mode b1 b0 TCK1 MR3 MR2 MR1 TMOD1 MR0 TMOD0 TCK0 Function varies with each operation mode Count source select bit (Function varies with each operation mode) Operation mode select bit Note 1: Must set “00” to operation mode select bit when using timer X2 of M30200. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Symbol Address When reset TABSR 0380 16 000X00002 Count start flag Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Clock devided count start flag Timer B1 count start flag Timer B0 count start flag Timer X2 count start flag Timer X1 count start flag Timer X0 count start flag Timer A0 count start flag0 : Stops counting 1 : Starts counting CDCS TB1S TB0S Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. TX2S TX1S TX0S TA0S Symbol Address When reset TX0 0389 16,038816 Indeterminate TX1 038B 16,038A16 Indeterminate TX2 038D 16,038C16 Indeterminate b7 b0 b7 b0 (b15) (b8) Timer Xi register (Note 1) W R

Timer mode 0000 16 to FFFF16 Counts an internal count source Function Values that can be set
Event counter mode 0000 16 to FFFF16 Counts pulses from an external source or timer overflow
One-shot timer mode 0000 16 to FFFF16 Counts a one shot width (Note 2)
Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator
Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 16 to FF16(Note 2) (High-order addresses) 0016 to FF16 (Note 2) (Low-order addresses) 000016 to FFFE16 (Note 2) Note 1: Read and write data in 16-bit units. Note 2: Use MOV instruction to write to this register. /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines 0 : Stops counting 1 : Starts counting
Pulse period / pulse width measurement mode Measures a pulse period or width /LiteDiagLines/LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X 223 Figure 2.4.3. Timer X-related registers (2) Symbol Address When reset CPSRF 0381 16 0XXXXXXX 2 Clock prescaler reset flag Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Clock prescaler reset flag0 : No effect 1 : Prescaler is reset (When read, the value is “0”) CPSR W R Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. TA0TGL Symbol Address When reset TRGSR 0383 16 0016 Timer A0 event/trigger select bit 0 0 : Input on TA0IN is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX2 overflow is selected 1 1 : TX0 overflow is selected Trigger select register Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : Input on TX0INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TX1 overflow is selected 0 0 : Input on TX1INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX0 overflow is selected 1 1 : TX2 overflow is selected 0 0 : Input on TX2INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX1 overflow is selected 1 1 : TA0 overflow is selected Timer X0 event/trigger select bit Timer X1 event/trigger select bit Timer X2 event/trigger select bit W R TA0TGH TX0TGL TX0TGH TX1TGL TX1TGH TX2TGL TX2TGH b1 b0 b3 b2 b5 b4 b7 b6 Note: Set the corresponding port direction register to “0”(input mode). TX0OS TX1OS TA0OS One-shot start flag Symbol Address When reset ONSF 0382 16 XXXX0000 2 Timer A0 one-shot start flag Timer X0 one-shot start flag Timer X1 one-shot start flag Timer X2 one-shot start flag TX2OS Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. W R 1 : Timer start When read, the value is “0” /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines

SINGLE -CHIP 16-BIT CMOS MICROCOMPUTER Timer X 224 In timer mode, choose functions from those listed in Table 2.4.1. Operations of the circled items are Operation (1) Setting the count start flag to “1” causes the counter to perform a down count on the count source. (2) If an underflow occurs, the content of the reload register is reloaded, and the count continues. At this time, the timer Xi interrupt request bit goes to “1”. (3) Setting the count start flag to “0” causes the counter to hold its value and to stop.

2.4.2 Operation of Timer X (timer mode)

Table 2.4.1. Choosed functions Figure 2.4.4. Operation timing of timer mode Item Count source Pulse output function Gate function Set-up O O O Internal count source (f1 / f8 / f32 / fc32) No pulses output Pulses output No gate function Performs count only for the period in which the TXiINOUT pin is at “L” level Performs count only for the period in which the TXiINOUT pin is at “H ” level FFFF 16 n 000016 Time Start count again Count start flag Timer Xi interrupt request bit “1” “1” Counter content (hex) n = reload register content Set to “1” by software “0” “0” Set to “1” by softwareCleared to “0” by software Cleared to “0” when interrupt request is accepted, or cleared by software (1) Start count (2) Underflow (3) Stop count

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X 225 Figure 2.4.5. Set-up procedure of timer mode Setting divide ratio Can be set to 000016 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer X0 register [Address 038916, 038916]T X 0 Timer X1 register [Address 038B16, 038A16]T X 1 Timer X2 register [Address 038D16, 038C16]T X 2 Start count Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 Setting count start flag Count start flag [Address 038016] TABSR Timer X0 count start flag b7 b0 Pulse output function select bit 0 : Pulse is not output (TXiINOUT pin is a normal port pin) Selecting timer mode and functions Timer Xi mode register (i = 0 to 2) [Address 039716 to 039916] TXiMR (i = 0 to 2) Selection of timer mode b7 b0 0000 0 0 (Must always be “0” in timer mode) Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Gate function select bit 0 0 : 0 1 : b4 b3 Gate function not available (TXiINOUT pin is a normal port pin) Timer X1 count start flag Timer X2 count start flag

SINGLE -CHIP 16-BIT CMOS MICROCOMPUTER Timer X 226

2.4.3 Operation of Timer X (timer mode, gate function selected)

Figure 2.4.6. Operation timing of timer mode, gate function selected In timer mode, choose functions from those listed in Table 2.4.2. Operations of the circled items are Table 2.4.2. Choosed functions (1) When the count start flag is set to “1” and the TXiINOUT pin inputs at “H ” level, the counter performs a down count on the count source. (2) When the TXiINOUT pin inputs at “L” level, the counter holds its value and stops. (3) If an underflow occurs, the content of the reload register is reloaded and the count continues. At this time, the timer Xi interrupt request bit goes to “1”. (4) Setting the count start flag to “0” causes the counter to hold its value and to stop.

Make the pulse width of the signal input to the TXiINOUT pin not less than two cycles of the count source. Operation Note Item Count source Pulse output function Gate function Set-up O O O Internal count source (f1 / f8 / f32 / fc32) No pulses output Pulses output No gate function Performs count only for the period in which the TXiINOUT pin is at “L” level Performs count only for the period in which the TXiINOUT pin is at “H ” level FFFF 16 n 000016 Time Count start flag Timer Xi interrupt request bit “1” “1” Counter content (hex) n = reload register content TXiINOUT pin input signal (2) Stop count “0” “0” Set to “1” by software “H ” “L” (4) Stop count (1) Start count Cleared to “0” when interrupt request is accepted, or cleared by software (3) Underflow Set to “1” by software Cleared to “0” by software Start count again.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X 227 Figure 2.4.7. Set-up procedure of timer mode, gate function selected Can be set to 000016 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer X0 register [Address 038916, 038816]T X 0 Timer X1 register [Address 038B16, 038A16]T X 1 Timer X2 register [Address 038D16, 038c16]T X 2 Setting divide ratio Pulse output function select bit 0 : Pulse is not output (Set to “0” when gate function selected) Selecting timer mode and functions Timer Xi mode register (i = 0 to 2) [Address 039716 to 039916] TXiMR (i = 0 to 2) Gate function select bit 1 1 : Timer counts only when TXiINOUT pin is held “H ” (Note) b4 b3 Selection of timer mode b7 b0 0000 0 (Must always be “0” in timer mode) Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Note: Set the corresponding port direction register to “0” (input mode). 1 1 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 Start count Setting count start flag Count start flag [Address 038016] TABSR Timer X0 count start flag b7 b0 Timer X1 count start flag Timer X2 count start flag

SINGLE -CHIP 16-BIT CMOS MICROCOMPUTER Timer X 228 Figure 2.4.8. Operation timing of timer mode, pulse output function selected

2.4.4 Operation of Timer X (timer mode, pulse output function selected)

In timer mode, choose functions from those listed in Table 2.4.3. Operations of the circled items are Table 2.4.3. Choosed functions (1) Setting the count start flag to “1” causes the counter to perform a down count on the count source. (2) If an underflow occurs, the content of the reload register is reloaded and the count continues. At this time, the timer Xi interrupt request bit goes to “1”. Also, the output polarity of the TXiINOUT pin reverses. (3) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the TXiINOUT pin outputs an “L” level. Operation Item Count source Pulse output function Gate function Set-up O O O Internal count source (f1 / f8 / f32 / fc32) No pulses output Pulses output No gate function Performs count only for the period in which the TXiINOUT pin is at “L” level Performs count only for the period in which the TXiINOUT pin is at “H ” level FFFF 16 n 000016 Time Count start flag Timer Xi interrupt request bit “1” “1” Counter content (hex) n = reload register content Pulse output from TXiINOUT pin “H ” “0” “L” “0” Set to “1” by software Set to “1” by software Cleared to “0” by software (3) Stop count Cleared to “0” when interrupt request is accepted, or cleared by software (1) Start count (2) Underflow Start count again

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X 229 Figure 2.4.9. Set-up procedure of timer mode, pulse output function selected Setting divide ratio Can be set to 000016 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer X0 register [Address 038916, 038816]T X 0 Timer X1 register [Address 038B16, 038A16]T X 1 Timer X2 register [Address 038D16, 038C16]T X 2 Start count Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 Pulse output function select bit 1 : Pulse is output (Note) (TXiINOUT pin is a pulse output pin) Selecting timer mode and functions Timer Xi mode register (i = 0 to 2) [Address 039716 to 039916] TXiMR (i = 0 to 2) Selection of timer mode b7 b0 0001 0 0 (Must always be “0” in timer mode) Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Gate function select bit 0 0 : 0 1 : b4 b3 Gate function not available (Set to “0X” when pulse output function selected) Note: Set the corresponding port direction register to “1” (output mode). Setting count start flag Count start flag [Address 038016] TABSR Timer X0 count start flag b7 b0 Timer X1 count start flag Timer X2 count start flag

SINGLE -CHIP 16-BIT CMOS MICROCOMPUTER Timer X 230 Figure 2.4.10. Operation timing of event counter mode, reload type selected

2.4.5 Operation of Timer X (event counter mode, reload type selected)

In event counter mode, choose functions from those listed in Table 2.4.4. Operations of the circled items procedure. (1) Setting the count start flag to “1” causes the counter to count the falling edges of the count source. (2) If an underflow occurs, the content of the reload register is reloaded, and the count continues. At this time, the timer Xi interrupt request bit goes to “1”. (3) Setting the count start flag to “0” causes the counter to hold its value and to stop. Operation Table 2.4.4. Choosed functions Item Set-up Count source Input signal to TXi INOUT (counting falling edges) Input signal to TXiINOUT (counting rising edges) Timer overflow(TB1/TA0/TXi overflow) Count operation type Reload type Free-run type Pulse output function No pulses output Pulses output O O O FFFF 16 n 000016 Time Count start flag Timer Xi interrupt request bit “1” “1” Counter content (hex) n = reload register content Set to “1” by software “0” “0” Set to “1” by software Cleared to “0” by software (1) Start count (2) Underflow (4) Stop count Start count again Cleared to “0” when interrupt request is accepted, or cleared by software

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X 231 Figure 2.4.11. Set-up procedure of event counter mode, reload type selected Selecting event counter mode and functions b7 b0 Pulse output function select bit (Note) 1 : Pulse is output (TXiINOUT pin is a pulse output pin) Timer Xi mode register (i = 0 to 2) [Address 039716 to 039916] TXiMR (i = 0 to 2) Invalid in event counter mode Can be “0” or “1”. Selection of event counter mode Invalid in event counter mode Can be “0” or “1”. Count operation type select bit 0 : Reload type 0 (Must always be “0” in event counter mode) Invalid when the external signal is not used as a count source. 01010 Setting divide ratio Can be set to 000016 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer X0 register [Address 038916, 038816]T X 0 Timer X1 register [Address 038B16, 038A16]T X 1 Timer X2 register [Address 038D16, 038C16]T X 2 Start count Setting trigger select register Trigger select register [Address 038316] TRGSR b7 b0 Timer X0 event/trigger select bit 0 1 : TB1 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TX1 overflow is selected b3 b2 Timer X1 event/trigger select bit 0 1 : TB1 overflow is selected 1 0 : TX0 overflow is selected 1 1 : TX2 overflow is selected b5 b4 Timer X1 event/trigger select bit 0 1 : TB1 overflow is selected 1 0 : TX1 overflow is selected 1 1 : TA0 overflow is selected b7 b6 Setting count start flag Count start flag [Address 038016] TABSR Timer X0 count start flag b7 b0 Timer X1 count start flag Timer X2 count start flag Note : Set the corresponding port direction register to “1” (output mode). TXiINOUT pin input is not selected as count source when pulse output function is selected.

SINGLE -CHIP 16-BIT CMOS MICROCOMPUTER Timer X 232 Figure 2.4.12. Operation timing of event counter mode, free run type selected

2.4.6 Operation of Timer X (event counter mode, free run type selected)

In event counter mode, choose functions from those listed in Table 2.4.5. Operations of the circled items procedure. (1) Setting the count start flag to “1” causes the counter to count the falling edges of the count source. (2) Even if an underflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the timer Xi interrupt request bit goes to “1”. (3) Setting the count start flag to “0” causes the counter to hold its value and to stop. Table 2.4.5. Choosed functions Operation Item Set-up Count source Input signal to TXi INOUT (counting falling edges) Input signal to TXiINOUT (counting rising edges) Timer overflow(TB1/TA0/TXi overflow) Count operation type Reload type Free-run type Pulse output function No pulses output Pulses output O O O FFFF 16 n 000016 Count start flag Timer Xi interrupt request bit “1” “1” Counter content (hex) n = reload register content “0” “0” (1) Start count Time Set to “1” by software Cleared to “0” by software (2) Underflow (4) Stop count Cleared to “0” when interrupt request is accepted, or cleared by software Set to “1” by software Start count again

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X 233 Figure 2.4.13. Set-up procedure of event counter mode, free run type selected Setting divide ratio Can be set to 000016 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer X0 register [Address 038916, 038816]T X 0 Timer X1 register [Address 038B16, 038A16]T X 1 Timer X2 register [Address 038D16, 038C16]T X 2 Start count Setting count start flag Count start flag [Address 038016] TABSR Timer X0 count start flag b7 b0 Timer X1 count start flag Timer X2 count start flag Selecting event counter mode and functions b7 b0 Pulse output function select bit 0 : Pulse is not output Timer Xi mode register (i = 0 to 2) [Address 039716 to 039916] TXiMR (i = 0 to 2) Invalid in event counter mode Can be “0” or “1”. Selection of event counter mode Invalid in event counter mode Can be “0” or “1”. Count operation type select bit 1 : Free-run type 0 (Must always be “0” in event counter mode) Count polarity select bit 0 : Counts external signal's falling edge 010010 Setting trigger select register Trigger select register [Address 038316] TRGSR b7 b0 Timer X0 event/trigger select bit 0 0 : Input on TX0INOUT is selected (Note) b3 b2 Timer X1 event/trigger select bit 0 0 : Input on TX1INOUT is selected (Note) b5 b4 Timer X1 event/trigger select bit 0 0 : Input on TX2 INOUT is selected (Note) b7 b6 Note: Set the corresponding port direction register to “0”(input mode).

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 234

2.4.7 Operation of Timer X (one-shot timer mode)

Figure 2.4.14. Operation timing of one-shot mode In one-shot timer mode, choose functions from those listed in Table 2.4.6. Operations of the circled items procedure. Operation(1) Setting the one-shot start flag to “1” with the count start flag set to “1” causes the counter to perform a down count on the count source. At this time, the TXi INOUT pin outputs an “H ” level. (2) The instant the value of the counter becomes “000016”, the TXiINOUT pin outputs an “L” level, and the counter reloads the content of the reload register and stops counting. At this time, the timer Xi interrupt request bit goes to “1”. (3) If a trigger occurs while a count is in progress, the counter reloads the value in the reload register again and continues counting. The reload timing is in step with the next count source input after the trigger. (4) Setting the count start flag to “0” causes the counter to stop and to reload the content of the reload register. Also, the TXi INOUT pin outputs an “L” level. At this time, the timer Xi interrupt request bit goes to “1”. Table 2.4.6. Choosed functions Item Count source Pulse output function Count start condition Set-up O O O Internal count source (f1 / f8 / f32 / fc32) No pulses output Pulses output External trigger input (falling edge of input signal to the TXiINOUT pin) External trigger input (rising edge of input signal to the TXiINOUT pin) Timer overflow (TB1/TX0/TXi overflow) Writing “1” to the one-shot start flag FFFF 16 n 000116 Timer Xi interrupt request bit Counter content (hex) n = reload register content Reload One-shot pulse output from TXi INOUT pin “H ” 1 / fi X (n) “L” Time Reload 1 / fi X (n+1) Write signal to one-shot start flag “1” “0” Count start flag “1” “0” (1) Start count Cleared to “0” when interrupt request is accepted, or cleared by software (2) Stop count (3) Start count (4) Stop countStart count Reload Set to “1” by software Cleared to “0” by software

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 235 Figure 2.4.15. Set-up procedure of one-shot mode Setting one-shot timer's time Can be set to 000116 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer X0 register [Address 038916, 038816] TX0 Timer X1 register [Address 038B16, 038A16] TX1 Timer X2 register [Address 038D16, 038C16] TX1 Start count Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 Clearing timer Xi interrupt request bit Timer Xi interrupt control register [Address 005516] TXiIC (i = 0 to 2) Interrupt request bit b7 b0 Refer to 'Precaution for Timer X (one shot timer mode)' Pulse output function select bit (Note) 1 : Pulse is output (TXiINOUT pin is a pulse output pin) Selecting one-shot timer mode and functions Timer Xi mode register (i = 0 to 2) [Address 039716 to 039916] TXiMR (i = 0 to 2) Invalid when the external signal is not used as a count source. Selection of one-shot timer mode b7 b0 1001 0 0 (Must always be “0” in one-shot timer mode) Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Trigger select bit 0 : When the one-shot start flag is set “1” Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Note: Set the corresponding port direction register to “1” (output mode). TXiINOUT pin is not selected as count source when pulse output function selected. Setting count start flag Count start flag [Address 038016] TABSR Timer X0 count start flag b7 b0 Timer X1 count start flag Timer X2 count start flag Setting one-shot start flag One-shot start flag [Address 038216] ONSF Timer X0 one-shot start flag b7 b0 Timer X1 one-shot start flag Timer X2 one-shot start flag

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 236 In pulse period/pulse width measurement mode, choose functions from those listed in Table 2.4.7. Op- erations of the circled items are described below. Figure 2.4.16 shows the operation timing, and Figure 2.4.17 shows the set-up procedure.

2.4.8 Operation of Timer X (pulse period measurement mode)

Figure 2.4.16. Operation timing of pulse period measurement mode Table 2.4.7. Choosed functions Operation Note (1) Setting the count start flag to “1” causes the counter to start counting the count source. (2) If a measurement pulse changes from “H ” to “L”, the value of the counter goes to “000016”, and measurement is started. In this instance, an indeterminate value is transferred to the reload register. The timer Xi interrupt request does not generate. (3) If a measurement pulse changes from “H ” to “L” again, the value of the counter is transferred to the reload register, and the timer Xi interrupt request bit goes to “1”. Then the value of the counter becomes “000016”, and the measurement is started again.

The timer Xi interrupt request bit goes to “1” when an effective edge of a measurement pulse is input or timer Xi is overflowed. The factor of interrupt request can be determined by use of the timer Xi overflow flag within the interrupt routine.
The value of the counter at the beginning of a count is indeterminate. Thus there can be in- stances in which the timer Xi overflow flag goes to “1” immediately after a count is performed.
The timer Xi overflow flag goes to “0” if timer Xi mode register is written to when the count start flag is “1”. This flag cannot be set to “1” by software. Item Set-up Count source Internal count source (f1 / f8 / f32 / fc32) Pulse width measurement (interval between measurement pulse falling edge to rising edge, and between rising edge to falling edge) O Pulse period measurement (interval between measurement pulse falling edge to falling edge) Pulse period measurement (interval between measurement pulse rising edge to rising edge) OMeasurement mode Count source Measurement pulse Count start flag Timer Xi interrupt request bit Timing at which counter reaches “0000 16” “1” “H ” “1” Transfer (indeterminate value)Reload register ← counter transfer timing “L” “0” “0” Timer Xi overflow flag“1” “0” Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. Measurement of pulse time interval from falling edge to falling edge Transfer (measured value) Cleared to “0” when interrupt request is accepted, or cleared by software (1) Start count (2) Start measurement(3) Start measurement again (Note 1) (Note 1) (Note 2)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 237 Figure 2.4.17. Set-up procedure of pulse period measurement mode Start count Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 Clearing overflow flag Timer Xi mode register (i=0 to 2) [Address 039716 to 039916] TXiMR (i=0 to 2) b7 b0 Timer Xi overflow flag 0 : Timer did not overflow Selecting pulse period / pulse width measurement mode and functions Timer Xi mode register (i=0 to 2) [Address 039716 to 039916] TXiMR (i=0 to 2) Selection of pulse period / pulse width measurement mode b7 b0 Timer Xi overflow flag 0 : Timer did not overflow 1 : Timer has overflowed Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Measurement mode select bit 0 0 : Pulse period measurement (Interval between measurement pulse falling edge to falling edge) b3 b2 0 0 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Note: Set the corresponding port direction register which sets the measurement pulse to “0” (input mode). 1 (Must always be “1” in pulse period / pulse width measurement mode) Setting count start flag Count start flag [Address 038016] TABSR Timer X0 count start flag Timer X1 count start flag b7 b0 Timer X2 count start flag

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 238 In pulse period/pulse width measurement mode, choose functions from those listed in Table 2.4.8. Op- erations of the circled items are described below. Figure 2.4.18 shows the operation timing, and Figure 2.4.19 shows the set-up procedure.

2.4.9 Operation of Timer X (pulse width measurement mode)

Figure 2.4.18. Operation timing of pulse width measurement mode Operation Note Table 2.4.8. Choosed functions (1) Setting the count start flag to “1” causes the counter to start counting the count source. (2) If an effective edge of a pulse to be measured is input, the value of the counter goes to “000016”, and measurement is started. In this instance, an indeterminate value is transferred to the reload register. The timer Xi interrupt request does not generate. (3) If an effective edge of a pulse to be measured is input again, the value of the counter is transferred to the reload register, and the timer Xi interrupt request bit goes to “1”. Then the value of the counter becomes “000016”, and measurement is started again.

The timer Xi interrupt request bit goes to “1” when an effective edge of a pulse to be measured is input or timer Xi is overflows. The factor of interrupt request can be determined by use of the timer Xi overflow flag within the interrupt routine.
The value of the counter at the beginning of a count is indeterminate. Thus there can be in- stances in which the timer Xi overflow flag goes to “1” immediately after a count is performed.
The timer Xi overflow flag goes to “0” if timer Xi mode register is written to when the count start flag is “1”. This flag cannot be set to “1” by software. Item Set-up Count source Internal count source (f1 / f8 / f32 / fc32) Pulse width measurement (interval between measurement pulse falling edge to rising edge, and between rising edge to falling edge) O Pulse period measurement (interval between measurement pulse falling edge to falling edge) Pulse period measurement (interval between measurement pulse rising edge to rising edge) O Measurement mode Measurement pulse “H ” Count source Reload register ← counter transfer timing Count start flag Timer Xi interrupt request bit Timing at which counter reaches “000016” “1” “1” “L” “0” “0” Timer Xi overflow flag “1” “0” Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. (Note 1)(Note 1)(Note 1) (Note 2) (1) Start count (2) Start measurement (3) Start measurement again Cleared to “0” when interrupt request is accepted, or cleared by software Transfer (indeterminate value) Transfer(measured value) (Note 1)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 239 Figure 2.4.19. Set-up procedure of pulse width measurement mode Start count Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 Clearing overflow flag Timer Xi mode register (i=0 to 2) [Address 039716 to 039916] TXiMR (i=0 to 2) b7 b0 Timer Xi overflow flag 0 : Timer did not overflow Selecting pulse period / pulse width measurement mode and functions Timer Xi mode register (i=0 to 2) [Address 039716 to 039916] TXiMR (i=0 to 2) Selection of pulse period / pulse width measurement mode b7 b0 Timer Xi overflow flag 0 : Timer did not overflow 1 : Timer has overflowed Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 0 1 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Note: Set the corresponding port direction register which sets the measurement pulse to “0” (input mode). 1 (Must always be “1” in pulse period / pulse width measurement mode) Setting count start flag Count start flag [Address 038016] TABSR Timer X0 count start flag Timer X1 count start flag b7 b0 Timer X2 count start flag Measurement mode select bit 1 0 : Pulse width measurement (Interval between measurement pulse falling edge to rising edge, and between rising edge to falling edge) b3 b2

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 240 In pulse width modulation mode, choose functions from those listed in Table 2.4.9. Operations of the set-up procedure.

2.4.10 Operation of Timer X (pulse width modulation mode, 16-bit PWM mode selected)

Figure 2.4.20. Operation timing of pulse width modulation mode, 16-bit PWM mode selected Table 2.4.9. Choosed functions Operation Note Item Count source PWM mode Count start condition Set-up O O O Internal count source (f1 / f8 / f32 / fc32) 16-bit PWM 8-bit PWM Timer overflow (TB1/TA0/TXi overflow) (1) Selected timer overflow is generated with the count start flag set to “1”, the counter performs a down count on the count source. Also, the TXiINOUT pin outputs an “H ” level. (2) The TXiINOUT pin output level changes from “H ” to “L” when a set time period elapses. At this time, the timer Xi interrupt request bit goes to “1”. (3) The counter reloads the content of the reload register every time PWM pulses are output for one cycle, and continues counting. (4) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the TXiINOUT outputs an “L” level.

PWM pulse cycle is (216 -1)/fi, whereas “H ” level duration is n/fi. However, when “000016” is set for the timer A0 register, the PWM output is “L” level for the entire period, and an interrupt request is generated for every PWM output cycle. Also, when “FFFF 16” is set for the timer A0 register, the PWM output is “H ” level for the entire period, and an interrupt request is generated for every PWM output cycle. (fi: Count source frequency f1, f8, f32, fC32 n: Timer value) 1 / fi X (2 –1) Count source Timer Interrupt request bit becoming trigger PWM pulse output from TXi INOUT pin Conditions: Reload register = 000316, when timer overflow is selected in trigger “H ” “H ” “L” “L” Timer Xi interrupt request bit “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software 1 / fi X n Count start flag“1” “0” Set to “1” by software (1) Start count (2) Output level “H ” to “L” Note: n = 000016 to FFFE16 (4) Stop count (3) One period is complete Cleared to “0” by software Cleared to “0” when interrupt request is accepted, or cleared by software

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 241 Figure 2.4.21. Set-up procedure of pulse width modulation mode, 16-bit PWM mode selected Setting PWM pulse's “H ” level width Can be set to 000016 to FFFE16 b7 b0 (b15) (b8) b7 b0 Timer X0 register [Address 038916, 038816]T X 0 Timer X1 register [Address 038B16, 038A16]T X 1 Timer X2 register [Address 038D16, 038C16]T X 2 Start count Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 1 (Must always be “1” in PWM mode) Selecting PWM mode and functions Timer Xi mode register (i = 0 to 2) [Address 039716 to 039916] TXiMR (i = 0 to 2) Invalid in event counter mode Can be “0” or “1”. Selection of PWM mode b7 b0 111 1 16/8-bit PWM mode select bit 0 : Functions as a 16-bit pulse width modulator b7 b6 Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Trigger select bit 1 : Selected by event/trigger select register Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Note: Set the corresponding port direction register which outputs the pulse to “1” (output mode). Clearing timer Xi interrupt request bit Timer Xi interrupt control register (i = 0 to 2) [Address 005616 to 005816] TXiIC (i = 0 to 2) Interrupt request bit b7 b0 Refer to 'Precaution for Timer X (pulse width modulation mode)' Setting trigger select register Trigger select register [Address 038316] TRGSR b7 b0 Timer X0 event/trigger select bit 0 1 : TB1 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TX1 overflow is selected b3 b2 Timer X1 event/trigger select bit 0 1 : TB1 overflow is selected 1 0 : TX0 overflow is selected 1 1 : TX2 overflow is selected b5 b4 Timer X1 event/trigger select bit 0 1 : TB1 overflow is selected 1 0 : TX1 overflow is selected 1 1 : TA0 overflow is selected b7 b6 Setting count starts flag Count start flag [Address 038016] TABSR Timer X0 count start flag b7 b0 Timer X1 count start flag Timer X2 count start flag

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 242

2.4.11 Operation of Timer X (pulse width modulation mode, 8-bit PWM mode selected)

Figure 2.4.22. Operation timing of pulse width modulation mode, with 8-bit PWM mode selected In pulse width modulation mode, choose functions from those listed in Table 2.4.10. Operations of the set-up procedure. Table 2.4.10. Choosed functions (1) Selected timer overflow is generated with the count start flag set to “1”, the counter performs a down count on the count source. Also, the TXiINOUT pin outputs an “H ” level. (2) The TXiINOUT pin output level changes from “H ” to “L” when a set time period elapses. At this time, the timer Xi interrupt request bit goes to “1”. (3) The counter reloads the content of the reload register every time PWM pulses are output for one cycle, and continues counting. (4) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the TXiOUT pin outputs an “L” level.

PWM pulse cycle is (m + 1( x (28 -1)/fi, whereas “H ” level duration is n x (m + 1)/fi. However, when “0016” is set for the significant 8 bits of the timer A0 register, the PWM output is “L” level for the entire period, and an interrupt request is generated for every PWM output cycle. Also, when “FF 16” is set for the significant 8 bits of the timer A0 register, the PWM output is “H ” level for the entire period, and an interrupt request is generated for every PWM output cycle. (fi: Count source frequency f 1, f8, f32, fC32 n: Timer value) Operation Note Item Count source PWM mode Count start condition Set-up O O O Internal count source (f1 / f8 / f32 / fc32) 16-bit PWM 8-bit PWM Timer overflow (TB1/TA0/TXi overflow) Conditions:Reload register high-order 8 bits = 0216 Reload register low-order 8 bits = 0216 When timer overflow is selected in trigger 1 / fi X (m + 1) X n 1 / fi X (m+1) Count source (Note 1) Interrupt request bit of timer becoming trigger Underflow signal of 8 -bit prescaler (Note 2) PWM pulse output from TXi INOUT pin “H ” “H ” “L” “L” Timer Xi interrupt request bit /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines “H ” “L” “1” “0” Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: m = 00 16 to FF16; n = 0016 to FF16. Count start flag “1” “0” (1) Start count (2) Output level “H ” to “L” Cleared to “0” when interrupt request is accepted, or cleared by software (3) One period is complete (4) Stop count Cleared to “0” when interrupt request is accepted, or cleared by software

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 243 Figure 2.4.23. Set-up procedure of pulse width modulation mode, 8-bit PWM mode selected Setting PWM pulse's “H ” level width Can be set to 000016 to FFFE16 b7 b0 (b15) (b8) b7 b0 Timer X0 register [Address 038916, 038816]T X 0 Timer X1 register [Address 038B16, 038A16]T X 1 Timer X2 register [Address 038D16, 038C16]T X 2 Start count Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 1 (Must always be “1” in PWM mode) Selecting PWM mode and functions Timer Xi mode register (i = 0 to 2) [Address 039716 to 039916] TXiMR (i = 0 to 2) Invalid in event counter mode Can be “0” or “1”. Selection of PWM mode b7 b0 111 1 16/8-bit PWM mode select bit 1 : Functions as a 8-bit pulse width modulator b7 b6 Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Trigger select bit 1 : Selected by event/trigger select register Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Note: Set the corresponding port direction register which outputs the pulse to “1” (output mode). Clearing timer Xi interrupt request bit Timer Xi interrupt control register (i = 0 to 2)[Address 005616 to 005816] TXiIC (i = 0 to 2) Interrupt request bit b7 b0 Refer to 'Precaution for Timer X (pulse width modulation mode)' Setting trigger select register Trigger select register [Address 038316] TRGSR b7 b0 Timer X0 event/trigger select bit 0 1 : TB1 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TX1 overflow is selected b3 b2 Timer X1 event/trigger select bit 0 1 : TB1 overflow is selected 1 0 : TX0 overflow is selected 1 1 : TX2 overflow is selected b5 b4 Timer X1 event/trigger select bit 0 1 : TB1 overflow is selected 1 0 : TX1 overflow is selected 1 1 : TA0 overflow is selected b7 b6 Setting count starts flag Count start flag [Address 038016] TABSR Timer X0 count start flag b7 b0 Timer X1 count start flag Timer X2 count start flag

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 244

2.4.12 Precautions for Timer X (timer mode, event counter mode)

Figure 2.4.24. Reading timer Xi register (1) To clear reset, the count start flag is set to “0”. Set a value in the timer Xi register, then set the flag to “1”. (2) Reading the timer Xi register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Xi register with the reload timing shown in Figure 2.4.24 gets “FFFF 16”. Reading the timer Xi register after setting a value in the timer Xi regis- ter with a count halted but before the counter starts counting gets a proper value. 210 n n – 1Counter value (Hex.) 21 0 F F F F n – 1Read value (Hex.) Reload Time n = reload register content

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 245 (1) To clear reset, the count start flag is set to “0”. Set a value in the timer Xi register, then set the flag to “1”. (2) Setting the count start flag to “0” while a count is in progress causes as follows:

The counter stops counting and a content of reload register is reloaded.
The TXiINOUT pin outputs “L” level.
The interrupt request generated and the timer Xi interrupt request bit goes to “1”. (3) The timer Xi interrupt request bit goes to “1” if the timer's operation mode is set using any of the following procedures:
Selecting one-shot timer mode after reset.
Changing operation mode from timer mode to one-shot timer mode.
Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use timer Xi interrupt (interrupt request bit), set timer Xi interrupt request bit to “0” after the above listed changes have been made. (4) If a trigger occurs while a count is in progress, after the counter performs one down count following the reoccurrence of a trigger, the reload register contents are reloaded, and the count continues. To generate a trigger while a count is in progress, generate the second trigger after an elapse longer than one cycle of the timer's count source after the previous trigger occurred.

2.4.13 Precautions for Timer X (one-shot timer mode)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 246 (1) The timer Xi interrupt request bit goes to “1” when an effective edge of a measurement pulse is input or timer Xi is overflowed. The factor of interrupt request can be determined by use of the timer Xi overflow flag within the interrupt routine. (2) If the timer overflow occurs simultaneously with the input of a measurement pulse, and if the interrupt factor cannot be determined from the timer Xi overflow flag, connect the timers and count the number of overflows. (3) When reset, the timer Xi overflow flag goes to “1”. This flag cannot be set to “0” by writing to the timer Xi mode register when the count start flag is “1”. (4) Use the timer Xi interrupt request bit to detect only overflows. Use the timer Xi overflow flag only to determine the interrupt factor within the interrupt routine. (5) When the first effective edge is input after a count is started, an indeterminate value is trans- ferred to the reload register. At this time, timer Xi interrupt request is not generated. (6) The value of the counter is indeterminate at the beginning of a count. Therefore the timer Xi overflow flag may go to “1” immediately after a count is started. (7) If changing the measurement mode select bit is set after a count is started, the timer Xi interrupt request bit goes to “1”. (8) If the input signal to the TXi INOUT pin is affected by noise, precise measurement may not be performed in some cases. It is recommended to see that measurements fall within a specific range by use of software. (9) For pulse width measurement, pulse widths are successively measured. Use software to check whether the measurement result is an “H ” level width or an “L” level width.

2.4.14 Precautions for Timer X (pulse period/pulse width measurement mode)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 247 (1) To clear reset, the count start flag is set to “0”. Set a value in the timer Xi register, then set the flag to “1”. (2) The timer Xi interrupt request bit becomes “1” if setting operation mode of the timer in compli- ance with any of the following procedures:

Selecting PWM mode after reset.
Changing operation mode from timer mode to PWM mode.
Changing operation mode from event counter mode to PWM mode. Therefore, to use timer Xi interrupt (interrupt request bit), set timer Xi interrupt request bit to “0” after the above listed changes have been made. (3) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop counting. If the TXiINOUT pin is outputting an “H ” level in this instance, the output level goes to “L”, and the timer Xi interrupt request bit goes to “1”. If the TXiINOUT pin is outputting an “L” level in this instance, the level does not change, and the timer Xi interrupt request bit does not becomes “1”. (4) Normal PWM output is restored according to the interrupt request generate timing, both in the case of 16-bit PWM and 8-bit PWM, when PWM output is either “H ” or “L” level for the entire period. This holds only when a value other than “000016” or “FFFF 16” is set during 16- bit PWM, or a value other than “0016” or “FF16” is set during 8-bit PWM.

2.4.15 Precautions for Timer X (pulse width modulation mode)

Figure 2.4.25. Operation timing of PWM output mode Timer Xi interrupt request bit PWM pulse output from TXiINOUT pin "H" 1 / fi X (n) "L" "1" "0" Timer Xi interrupt request bit PWM pulse output from TXiINOUT pin "H" 1 / fi X (n) "L" "1" "0" Writing to the timer Xi Writing to the timer Xi Normal PWM restored here Cleared to “0” when interrupt request is accepted, or cleared by software Cleared to “0” when interrupt request is accepted, or cleared by software When PWM output is “H ” level for the entire period (i = 0 to 2) When PWM output is “L” level for the entire period

Clock-Synchronous Serial I/O M itsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 248

2.5.1 Overview

Clock-synchronous serial I/O carries out 8-bit data communications in synchronization with the clock. The following is an overview of the clock-synchronous serial I/O. (1) Transmission/reception format 8-bit data (2) Transfer rate If the internal clock is selected as the transfer clock, the divide-by-2 frequency, resulting from the bit rate generator division, becomes the transfer rate. The bit rate generator count source can be se- lected from the following: f 1, f8, f32, and fC . Clocks f1, f8 and f32 are derived by dividing the CPU’s main clock by 1, 8, and 32 respectively. Clock fC is derived by dividing the CPU’s sub clock by 1 respec- tively. Furthermore, if an external clock is selected as the transfer clock, the clock frequency input to the CLK pin becomes the transfer rate. (3) Error detection Only overrun error can be detected. Overrun error is an error that occurs when the next data is made ready before the reception buffer register is read. (4) How to deal with an error When receiving data, read an error flag and reception data simultaneously to determine which error has occurred. If the data read is erroneous, initialize the error flag and the UART0 receive buffer register, then receive the data again. To initialize the UART0 receive buffer register 1. Set the receive enable bit to “0” (disable reception). 2. Set the serial I/O mode select bit to “000 2” (invalid serial I/O). 3. Set the serial I/O mode select bit. 4. Set the receive enable bit to “1” again (enable reception). To transmit data again due to an error on the reception side when external clock is selected, clear the UART0 transmit buffer register, then transmit the data again. To clear the UART0 transmit buffer register 1. Set the port P5 2 (CLK0 pin) direction register to “0” (input mode). 2. Set the port P50 (TxD0 pin) direction register to “0” (input mode). 3. Set the internal/external clock select bit to “0” (internal clock). 4. Checking complection of transmission (no data present in transmit register). 5. Set the internal/external clock select bit to “1” (external clock). 6. Set the port P5 0 (TxD0 pin) direction register to “1” (output mode), then set transmission data in the UART0 transmit buffer register.

2.5 Clock-Synchronous Serial I/O

Clock-Synchronous Serial I/O Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 249 (5) Function selection For clock-synchronous serial I/O, the following functions can be selected: (a) Function for choosing polarity This function switches the polarity of the transfer clock. The following operations are available:

Data is input at the falling edge of the transfer clock, and is output at the rising edge.
Data is input at the rising edge of the transfer clock, and is output at the falling edge. (b) Function for choosing which bit to transmit first This function is to choose whether to transmit data from bit 0 or from bit 7. Choose either of the following:
LSB first Data is transmitted from bit 0.
MSB first Data is transmitted from bit 7. (c) Function for choosing successive reception mode Successive reception mode is a mode in which reading the receive buffer register makes the recep- tion-enabled status ready. In this mode, there is no need to write dummy data to the transmit buffer register so as to make the reception-enabled status ready. But at the time of starting reception, read the receive buffer register into a dummy manner.
Normal mode Writing dummy data to the transmit buffer register makes the reception enabled status ready.
Successive reception mode Reading the reception buffer register makes the reception-enabled status ready. (d) Function for outputting transfer clock to multiple pins This function is to switch among pins to output the transfer clock. This function is effective only when selecting the internal clock. Switching among pins for outputting the transfer clock allows data trans- mission to two external ICs in a time-sharing manner. (e) Function for choosing a transmission interrupt factor The timing to generate a transmission interrupt can be selected from the following: the instant the transmission buffer is emptied or the instant the transmission register is emptied. When transmis- sion buffer empty timing is selected, an interrupt occurs when transmitted data is moved from the transmission buffer to the transmission register. Therefore, data can be transmitted in succession. When transmission register empty timing is selected, an interrupt occurs when data transmission is complete. Following are some examples in which various functions (a) through (e) are selected:
Transmission Operation WITH: transmission at falling edge of transfer clock, LSB First, interrupt at instant transmission buffer is emptied; WITHOUT transfer clock output to multiple pins function ...
Transmission Operation WITH: transmission at falling edge of transfer clock, LSB First, interrupt at instant transmission is completed; WITH transfer clock output to multiple pins function (UART0
Reception WITH: reception at falling edge of transfer clock, LSB First, successive reception mode

Clock-Synchronous Serial I/O Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 251 Figure 2.5.2. Serial I/O-related registers (1) UARTi bit rate generator (Note 1, 2) b0 Symbol Address When reset U0BRG 03A1 16 Indeterminate U1BRG 03A9 16 Indeterminate Function Assuming that set value = n, BRGi divides the count source by n + 1 0016 to FF16 Values that can be set W R /LiteDiagLines/LiteDiagLines b7 b0 (b15) (b8) b7 b0 UARTi transmit buffer register (Note) Function Transmit data Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Symbol Address When reset U0TB 03A3 16, 03A216 Indeterminate U1TB 03AB 16, 03AA16 Indeterminate W R /LiteDiagLines/LiteDiagLines (b15) Symbol Address When reset U0RB 03A7 16, 03A616 Indeterminate U1RB 03AF 16, 03AE16 Indeterminate b7 b0 (b8) b7 b0 UARTi receive buffer register Function (During UART mode) Function (During clock synchronous serial I/O mode) Bit nameBit symbol 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found Note: Bits 15 through 12 are set to “0” when the receive enable bit is set to “0”. (Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the lower byte of the UARTi receive buffer register (addresses 03A6 16, and 03AE16) is read out. Invalid Invalid Invalid OER FER PER SUM Overrun error flag (Note) Framing error flag (Note) Parity error flag (Note) Error sum flag (Note) 0 : No overrun error 1 : Overrun error found 0 : No overrun error 1 : Overrun error found Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Receive data W R Receive data /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Note : Use MOV instruction to write to this register. Note 1: Write a value to this register while transmit/receive halts. Note 2: Use MOV instruction to write to this register.

Clock-Synchronous Serial I/O Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 252 Figure 2.5.3. Serial I/O-related registers (2) UARTi transmit/receive mode register Symbol Address When reset UiMR(i=0,1) 03A0 16, 03A816 0016 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol W R Must be fixed to 001 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited b2 b1 b0 CKDIR SMD1 SMD0 Serial I/O mode select bit (Note 1) SMD2 Internal/external clock select bit (Note 2) STPS PRY PRYE SLEP Parity enable bit 0 : Internal clock (Note 3) 1 : External clock (Note 4) Stop bit length select bit Odd/even parity select bit Sleep select bit 0 : One stop bit 1 : Two stop bits 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited b2 b1 b0 0 : Internal clock (Note 3) 1 : External clock (Note 4) Invalid Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity Invalid Invalid Must always be “0” Function (During UART mode) Function (During clock synchronous serial I/O mode) /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines UARTi transmit/receive control register 0 Symbol Address When reset UiC0(i=0,1) 03A4 16, 03AC16 0816 b7 b6 b5 b4 b3 b2 b1 b0 Function (During UART mode) W R Function (Note) (During clock synchronous serial I/O mode) TXEPT CLK1 CLK0 NCH CKPOL BRG count source select bit Transmit register empty flag 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge CLK polarity select bit Data output select bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : fc is selected b1 b0 0 : LSB first 1 : MSB first 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open-drain output UFORM Transfer format select bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : fc is selected b1 b0 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output Must always be “0” Bit nameBit symbol Must always be “0” Note: UART1 cannot be used in clock synchronous serial I/O. /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines Note 1: UART1 cannot be used in clock synchronous serial I/O. Note 2: UART1 can use only internal clock. Must set this bit to “1”. Note 3: Set the corresponding port direction register to “1” (output mode). Note 4: Set the corresponding port direction register to “0” (input mode). Set this bit to “0”. Set this bit to “1”. 1 0

Clock-Synchronous Serial I/O Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 253 Figure 2.5.4. Serial I/O-related registers (3) UARTi transmit/receive control register 1 Symbol Address When reset UiC1(i=0,1) 03A5 16,03AD 16 0216 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol Function (During UART mode) Function (Note 1) (During clock synchronous serial I/O mode) TE TI RE RI Transmit enable bit Receive enable bit (Note 2) Receive complete flag Transmit buffer empty flag 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : No data present in receive buffer register 1 : Data present in receive buffer register Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. Note 1: UART1 cannot be used in clock synchronous serial I/O. Note 2: When using multiple pins to output the transfer clock, the following requirements must be met:

UART0 internal/external clock select bit (bit 3 at address 03A016) = “0”. UART transmit/receive control register 2 Symbol Address When reset UCON 03B0 16 XX000000 2 b7 b6 b5 b4 b3 b2 b1 b0 Bit name Bit symbol Function (During UART mode) Function (During clock synchronous serial I/O mode) CLKMD0 CLKMD1 UART0 transmit interrupt cause select bit UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enable Set this bit to “0”. CLK/CLKS select bit 0 UART1 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Normal mode (CLK output is CLK0 only) 1 : Transfer clock output from multiple pins function selected 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) Must always be “0” U0IRS U1IRS U0RRM CLK/CLKS select bit 1 (Note 2) Valid when bit 5 = “1” 0 : Clock output to CLK1 1 : Clock output to CLKS1 Note 1: UART1 cannot be used in clock synchronous serial I/O. Note 2: If you are using clock asynchronous serial I/O mode, you can enable 'receive enable bit' when RxD port input is “H ”. If RxD port input is “L” and you have enabled 'receive enable bit' , then receive operation starts immediately. W R /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines W R /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Set this bit to “0”. Must always be “0” Must always be “0” Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.

Clock-Synchronous Serial I/O Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 254 In transmitting data in clock-synchronous serial I/O mode, choose functions from those listed in Table

2.5.2 Operation of Serial I/O (transmission in clock-synchronous serial I/O mode)

Note: This can be selected only when UART0 is used in combination with the internal clock. (1) Setting the transmit enable bit to “1” and writing transmission data to the UART0 transmit buffer register makes data transmissible status ready. (2) In synchronization with the first falling edge of the transfer clock, transmission data held in the UART0 transmit buffer register is transmitted to the UART0 transmit register. At this time, the UART0 transmit interrupt request bit goes to “1”. Also, the first bit of the transmission data is transmitted from the TxD 0 pin. Then the data is transmitted bit by bit from the lower order in synchronization with the falling edges. (3) When transmission of 1-byte data is completed, the transmit register empty flag goes to “1”, which indicates that transmission is completed. The transfer clock stops at “H ” level. (4) If the next transmission data is set in the UART0 transmit buffer register while transmission is in progress (before the eighth bit has been transmitted), the data is transmitted in succession. Operation Table 2.5.1. Choosed functions Item Set-up Transfer clock source Internal clock (f1 / f8 / f32 / fc) External clock (CLK0 pin) CLK polarity Output transmission data at the falling edge of the transfer clock Output transmission data at the rising edge of the transfer clock O O Transmission interrupt factor Transmission buffer empty Transmission complete Output transfer clock to multiple pins (Note) Not selected Selected O O Transfer clock LSB first MSB first O

Clock-Synchronous Serial I/O Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 255 Example of wiring Figure 2.5.5. Operation timing of transmission in clock-synchronous serial I/O mode Example of operation CLK0 TXD0 CLK R XD Microcomputer Receiver side IC Transfer clock Transmit enable bit (TE) Transmit buffer empty flag (Tl) “0” “1” “0” “1” /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines (1) Transmission enabled /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines (2) Start transmissionTc /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines (3) Transmission is complete /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines (4) Transmit next data Data is set to UARTi transmit buffer register Transferred from UARTi transmit buffer register to UARTi transmit register D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 TCLK Stopped pulsing because transfer enable bit = “0” Tc = TCLK = 2(n + 1) / fi fi: frequency of BRGi count source (f1, f8, f32, fC ) n: value set to BRGi CLK0 TxD0 Transmit register empty flag (TXEPT) “0” “1” Transmit interrupt request bit (IR) “0” “1” Cleared to “0” when interrupt request is accepted, or cleared by software D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Shown in ( ) are bit symbols. The above timing applies to the following settings:

Internal clock is selected.
CLK polarity select bit = “0”.
Transmit interrupt cause select bit = “0”.

Clock-Synchronous Serial I/O Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 256 Figure 2.5.6. Set-up procedure of transmission in clock-synchronous serial I/O mode (1) Continued to the next page Internal/external clock select bit 0 : Internal clock Setting UART0 transmit/receive mode register UART0 transmit/receive mode register U0MR [Address 03A016] Invalid in clock synchronous I/O mode Must be fixed to “001” b7 b0 0100 0 Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode Sleep select bit Must be “0” in clock synchronous I/O mode Setting UART0 transmit/receive control register 0 UART0 transmit/receive control register 0 U0C0 [Address 03A416] CLK polarity select bit 0 : Transmission data is output at falling edge of transfer clock and reception data is input at rising edge b7 b0 1000 BRG count source select bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : fC is selected b1 b0 Must be “0” in clock synchronous I/O mode Must be “1” in clock synchronous I/O mode Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) Transfer format select bit 0 : LSB first Note: Set the corresponding port direction register to “1” (output mode). Data output select bit (Note) 0 : TxDi pin is CMOS output 1 : TxDi pin is N-channel open-drain output UART transmit/receive control register 2 UCON [Address 03B016] UART0 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) CLK/CLKS select bit 1 0 : Normal mode Must be “0” in clock synchronous I/O mode Valid when bit 5 = “1” b7 b0 Setting UART transmit/receive control register 2 000 Must be “0” in clock synchronous I/O mode

Clock-Synchronous Serial I/O Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 257 Figure 2.5.7. Set-up procedure of transmission in clock-synchronous serial I/O mode (2) Start transmission Setting UART0 bit rate generator UART0 bit rate generator [Address 03A116] U0BRG Can be set to 0016 to FF16 (Note) b7 b0 Note: Write to UART0 bit rate generator when transmission/reception is halted. Transmission is complete Continued from the previous page UART0 transmit/receive control register 1 [Address 03A516] U0C1 Transmit enable bit 1 : Transmission enabled b7 b0 Transmission enabled Writing transmit data UART0 transmit buffer register [Address 03A316, 03A216] U0TB Setting transmission data b7 b0 b7 b0 (b15) (b8) UART0 transmit/receive control register 1 [Address 03A516]U0C1 b7 b0 Transmit buffer empty flag 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register (Writing next transmit data enabled) Checking the status of UART0 transmit buffer register Writing next transmit data UART0 transmit buffer register [Address 03A316, 03A216] U0TB Setting transmission data b7 b0 b7 b0 (b15) (b8)

Clock-Synchronous Serial I/O Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 258

2.5.3 Operation of the Serial I/O (transmission in clock-synchronous serial I/O

mode, transfer clock output from multiple pins function selected) Note: This can be selected only when UART0 is used in combination with the internal clock. (1) Setting the transmit enable bit to “1” makes data transmissible status ready. (2) When transmission data is written to the UART0 transmit buffer register, transmission data held in the UART0 transmit buffer register is transmitted to the UART0 transmit register in synchronization with the first falling edge of the transfer clock. At this time, the first bit of the transmission data is transmitted from the TxD 0 pin. Then the data is transmitted bit by bit from the lower order in synchronization with the falling edges of the transfer clock. (3) When transmission of 1-byte data is completed, the transmit register empty flag goes to “1”, which indicates that the transmission is completed. The transfer clock stops at “H ” level. At this time, the UART0 transmit interrupt request bit goes to “1”. (4) Setting CLK/CLKS select bit 1 to “1” and setting CLK/CLKS select bit 0 to “1” causes the CLKS pin to go to the transfer clock output pin. Change the transfer clock output pin when transmission is halted. Operation In transmitting data in clock-synchronous serial I/O mode, choose functions from those listed in Table Table 2.5.2. Choosed functions Item Set-up Transfer clock source Internal clock (f1 / f8 / f32 / fc) External clock (CLK0 pin) CLK polarity Output transmission data at the falling edge of the transfer clock Output transmission data at the rising edge of the transfer clock O O Transmission interrupt factor Transmission buffer empty Transmission complete Output transfer clock to multiple pins (Note) Not selected Selected O O Transfer clock LSB first MSB first O

Clock-Synchronous Serial I/O Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 259 Example of wiring Example of operation Figure 2.5.8. Operation timing of transmission in clock-synchronous serial I/O mode, transfer clock output from multiple pins function selected Microcomputer TXD 0 (P50) CLKS (P53) CLK 0 (P52) IN CLK IN CLK Note: This applies when performing only transmission with an internal clock selected in the clock synchronous serial I/O mode. Transmit interrupt request bit “0” “1” Cleared to “0” when interrupt request is accepted, or cleared by software Transmit buffer empty flag CLK 0 TxD 0 “0” “1” Transmit enable bit “0” “1” Transfer clock CLKS D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 CLK, CLKS select bit 1 “0” “1” “0” “1”CLK, CLKS select bit 0 (1) Transmission enabled (2) Start transmission (3) Transmission is complete (4) Clock switched

Clock-Synchronous Serial I/O Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 260 Figure 2.5.9. Set-up procedure of transmission in clock-synchronous serial I/O mode, transfer clock output from multiple pins function selected (1) Continued to the next page Internal/external clock select bit 0 : Internal clock Setting UART0 transmit/receive mode register UART0 transmit/receive mode register U0MR [Address 03A016] Invalid in clock synchronous I/O mode Must be fixed to “001” b7 b0 0100 0 Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode Sleep select bit Must be “0” in clock synchronous I/O mode Setting UART0 transmit/receive control register 0 UART0 transmit/receive control register 0 U0C0 [Address 03A416] CLK polarity select bit 0 : Transmission data is output at falling edge of transfer clock and reception data is input at rising edge b7 b0 1000 BRG count source select bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : fC is selected b1 b0 Must be “0” in clock synchronous I/O mode Must be “1” in clock synchronous I/O mode Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) Transfer format select bit 0 : LSB first Note: Set the corresponding port direction register to “1” (output mode). Data output select bit (Note) 0 : TxDi pin is CMOS output 1 : TxDi pin is N-channel open-drain output UART transmit/receive control register 2 UCON [Address 03B016] UART0 transmit interrupt cause select bit 1 : Transmission completed (TXEPT = 1) CLK/CLKS select bit 1 1 : Transfer clock output from multiple pins finction selected Must be “0” in clock synchronous I/O mode CLK/CLKS select bit 0 0 : Clock output to CLK0 1 : Clock output to CLKS b7 b0 Setting UART transmit/receive control register 2 010 Must be “0” in clock synchronous I/O mode

Clock-Synchronous Serial I/O Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 261 Figure 2.5.10. Set-up procedure of transmission in clock-synchronous serial I/O mode, transfer clock output from multiple pins function selected (2) Start transmission Setting UART0 bit rate generator UART0 bit rate generator [Address 03A116] U0BRG Can be set to 0016 to FF16 (Note) b7 b0 Note: Write to UART0 bit rate generator when transmission/reception is halted. Transmission is complete Continued from the previous page UART0 transmit/receive control register 1 [Address 03A516] U0C1 Transmit enable bit 1 : Transmission enabled b7 b0 Transmission enabled Writing transmit data UART0 transmit buffer register [Address 03A316, 03A216] U0TB Setting transmission data b7 b0 b7 b0 (b15) (b8) UART0 transmit/receive control register 1 [Address 03A516]U0C1 b7 b0 Transmit buffer empty flag 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register (Writing next transmit data enabled) Checking the status of UART0 transmit buffer register Writing next transmit data UART0 transmit buffer register [Address 03A316, 03A216] U0TB Setting transmission data b7 b0 b7 b0 (b15) (b8)

Clock-Synchronous Serial I/O Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 262 In receiving data in clock-synchronous serial I/O mode, choose functions from those listed in Table 2.5.3. Operations of the circled items are described below. Figure 2.5.11 shows the operation timing, and Fig-

2.5.4 Operation of Serial I/O (reception in clock-synchronous serial I/O mode)

Table 2.5.3. Choosed functions Note: This can be selected only when UART0 is used in combination with the internal clock. Operation (1) Writing dummy data to the UART0 transmit buffer register, setting the receive enable bit to “1”, and the transmit enable bit to “1”, makes the data receivable status ready. (2) In synchronization with the first rising edge of the transfer clock, the input signal to the RxD0 pin is stored in the highest bit of the UART0 receive register. Then, data is taken in by shifting right the content of the UART0 reception data in synchronization with the rising edges of the transfer clock. (3) When 1-byte data lines up in the UART0 receive register, the content of the UART0 receive register is transmitted to the UART0 receive buffer register. The transfer clock stops at “H ” level. At this time, the receive complete flag and the UART0 receive interrupt request bit goes to “1”. (4) The receive complete flag goes to “0” when the lower-order byte of the UART0 buffer register is read. Item Set-up Transfer clock source Internal clock (f1 / f8 / f32 / fc) External clock (CLK0 pin) CLK polarity Output transmission data at the falling edge of the transfer clock Output transmission data at the rising edge of the transfer clock O O Continuous receive mode Disabled Enabled Output transfer clock to multiple pins (Note) Not selected Selected O O Transfer clock LSB first MSB first O

Clock-Synchronous Serial I/O Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 263 Example of wiring Figure 2.5.11. Operation timing of reception in clock-synchronous serial I/O mode Example of operation CLK0 R XD0 CLK TXD Microcomputer Transmitter side IC 1 / fEXT Transmit enable bit (TE) Transmit buffer empty flag (Tl) CLK0 RxD0 Receive complete flag (Rl) “0” “1” “0” “1” “0” “1” Receive enable bit (RE) “0” “1” The above timing applies to the following settings:

External clock is selected.
CLK polarity select bit = “0”. fEXT : frequency of external clock Make sure that the following conditions are met when the CLK0 pin input =“H ” before data reception
Transmit enable bit → “1”
Receive enable bit → “1”
Dummy data write to UART0 transmit buffer register Receive interrupt request bit (IR)“0” “1” Cleared to “0” when interrupt request is accepted, or cleared by software D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 Shown in ( ) are bit symbols. Reception data is taken in Transferred from UART0 receive register to UART0 receive buffer register (1) Reception enabled (2) Start reception (3) Reception is complete Read out from UART0 receive buffer register Transferred from UART0 transmit buffer register to UART0 transmit register (4) Read of reception data Dummy data is set in UART0 transmit buffer register

Clock-Synchronous Serial I/O Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 264 Figure 2.5.12. Set-up procedure of reception in clock-synchronous serial I/O mode (1) Continued to the next page Internal/external clock select bit 1 : External clock Setting UART0 transmit/receive mode register UART0 transmit/receive mode register U0MR [Address 03A016] Invalid in clock synchronous I/O mode Must be fixed to “001” b7 b0 0100 1 Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode Sleep select bit Must be “0” in clock synchronous I/O mode Setting UARTi transmit/receive control register 0 (i=0 to 2) UART0 transmit/receive control register 0 U0C0 [Address 03A416] CLK polarity select bit (Note) 0 : Transmission data is output at falling edge of transfer clock and reception data is input at rising edge b7 b0 1000 BRG count source select bit Invalid when external clock is selected Must be “0” in clock synchronous I/O mode Must be “1” in clock synchronous I/O mode Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) Transfer format select bit 0 : LSB first Data output select bit 0 : TxD0 pin is CMOS output 1 : TxD0 pin is N-channel open-drain output Note: Set the corresponding port direction register to “0” (input mode). UART transmit/receive control register 2 UCON [Address 03B016] UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled CLK/CLKS select bit 1 0 : Normal mode Must be “0” in clock synchronous I/O mode Valid when bit 5 = “1” b7 b0 Setting UART transmit/receive control register 2 Must be “0” in clock synchronous I/O mode

Clock-Synchronous Serial I/O Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 265 Figure 2.5.13. Set-up procedure of reception in clock-synchronous serial I/O mode (2) Writing dummy data UART0 transmit buffer register [Address 03A316, 03A216] U0TB Setting dummy data b7 b0 b7 b0 (b15) (b8) Checking completion of reception UART0 transmit/receive control register 1 [Address 03A516] U0C1 b7 b0 Receive complete flag 0 : No data present in receive buffer register 1 : Data present in receive buffer register Start reception Processing after reading out reception data Continued from the previous page Checking error UART0 receive buffer register [Address 03A716, 03A616]U0RB Overrun error flag 0 : No overrun error 1 : Overrun error found b7 b0 b7 b0 (b15) (b8) Receive data Reception enabled UART0 transmit/receive control register 1 [Address 03A516] U0C1 Transmit enable bit 1 : Transmission enabled b7 b0 Receive enable bit (Note) 1 : Reception enabled 1 1 Note: Set the corresponding port direction register to “0” (input mode).

Clock-Synchronous Serial I/O Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 266

2.5.5 Precautions for Serial I/O (in clock-synchronous serial I/O)

(1) With an external clock selected, perform the following set-up procedure with the CLK0 pin input level = “H ” if the CLK polarity select bit = “0” or with the CLK0 pin input level = “L” if the CLK polarity select bit = “1”: 1. Set the transmit enable bit (to “1”) 2. Write transmission data to the UART0 transmit buffer register

Clock-Synchronous Serial I/O Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 267 (1) In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock. Fix settings for transmission even when using the device only for reception. Dummy data is output to the outside from the TxD0 pin (transmission pin) when receiving data. (2) With the internal clock selected, setting the transmit enable bit to “1” (transmission-enabled status) and setting dummy data in the UART0 transmission buffer register generates a shift clock. With the external clock selected, a shift clock is generated when the transmit enable bit is set to “1”, dummy data is set in the UART0 transmit buffer register, and the external clock is input to the CLK0 pin. (3) In receiving data in succession, an overrun error occurs when the next reception data is made ready in the UART0 receive register with the receive complete flag set to “1” (before the content of the UART0 receive buffer register is read), and overrun error flag is set to “1”. In this instance, the next data is written to the UART0 receive buffer register, so handle with this problem by writing programs on transmission side and reception side so that the previous data is transmitted again. If an overrun error occurs, the UART0 receive interrupt request bit does not go to “1”. (4) To receive data in succession, set dummy data in the lower-order byte of the UART0 transmit buffer register every time reception is made. (5) With an external clock selected, perform the following set-up procedure with the CLK0 pin input level = “H ” if the CLK polarity select bit = “0” or with the CLK0 pin input level = “L” if the CLK polarity select bit = “1”: 1. Set receive enable bit (to “1”) 2. Set transmit enable bit (to “1”) 3. Write dummy data to the UART0 transmit buffer register Reception

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 268

2.6 Clock-Asynchronous Serial I/O (UART)

2.6.1 Overview

UART handles communications by means of character-by-character synchronization. The transmission side and the reception side are independent of each other, so full-duplex communication is possible. The following is an overview of the clock-asynchronous serial I/O. (1) Transmission/reception format Figure 2.6.1 shows the transmission/reception format, and Table 2.6.1 shows the names and func- tions of transmission data. Figure 2.6.1. Transmission/reception format Table 2.6.1. Transmission data names and functions Transfer data length : 7 bits 1ST – 7DATA 1SP 1ST – 7DATA 2SP 1ST – 7DATA – 1PAR – 1SP 1ST – 7DATA – 1PAR – 2SP Transfer data length : 8 bits 1ST – 8DATA 1SP 1ST – 8DATA 2SP 1ST – 8DATA – 1PAR – 1SP 1ST – 8DATA – 1PAR – 2SP Transfer data length : 9 bits 1ST – 9DATA 1SP 1ST – 9DATA 2SP 1ST – 9DATA – 1PAR – 1SP 1ST – 9DATA – 1PAR – 2SP ST : Start bit DATA : Character bit (Transfer data) PAR : Parity bit SP : Stop bit Name Function ST (start bit) DATA (character bits) SP (stop bit) A 1-bit “L” signal to be added immediately before character bits. This bit signals the start of data transmission. Transmission data set in the UARTi transmit buffer register. A signal to be added immediately after character bits so as to increase data reliability. The level of this signal so varies that the total number of 1's in character bits and this bit always becomes even or odd depending on which parity is chosen, even or odd. PAR (parity bit) Either 1-bit or 2-bit “H ” signal to be added immediately after character bits (after the parity bit if parity is checked). This / they signals the end of data transmission.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 269 (2) Transfer rate The divide-by-16 frequency, resulting from division in the bit rate generator (BRG), becomes the trans- fer rate. The count source for the transfer rate register can be selected from f1, f8, f32, and the input from the CLK pin. Clocks f1, f8, f32 are derived by dividing the CPU’s main clock by 1, 8, and 32 respectively. Table 2.6.2. Example of baud rate setting Baud rate (bps) BRG's count source System clock : 10MHz System clock : 7.3728MHz BRG's set value : n Actual time (bps) BRG's set value : n 600 1200 2400 4800 9600 14400 19200 28800 31250 f 129 (8116) 64 (4016) 32 (2016) 129 (8116) 64 (4016) 42 (2A16) 32 (2016) 21 (1516) 19 (1316) 600 1201 2367 4807 9615 14534 18939 28409 31250 95 (5F 16) 47 (2F16) 23 (1716) 95 (5F16) 47 (2F16) 31 (1F16) 23 (1716) 15 (F16) 600 1200 2400 4800 9600 14400 19200 28800 Actual time (bps)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 270 Table 2.6.3. Error detection (3) An error detection In clock-asynchronous serial I/O mode, detect errors are shown in Table 2.6.3. Type of error When the flag turns onDescription How to clear the flag

This error occurs when the next data lines up before the content of the UARTi receive buffer register is read.
The next data is written to the UARTi receive buffer register.
The UARTi receive interrupt request bit does not change.
This error occurs when the stop bit falls short of the set number of stop bits.
With parity enabled, this error occurs when the total number of 1's in character bits and the parity bit is different from the specified number.
This flag turns on when any error (overrun, framing, or parity) is detected. The error is detected when data is transferred from the UARTi receive register to the UARTi receive buffer register.
Set the receive enable bit to “0”.
When all error (overrun, framing, and parity) are removed, the flag is cleared.
Set the receive enable bit to “0”.
Read the lower-order byte of the UARTi receive buffer register. Overrun error Framing error Parity error Error-sum flag

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 271 (4) Functions selection In operating UART, the following functions can be used: (a) Sleep mode Sleep mode is a mode in which data is transferred to a particular microcomputer among those con- nected by use of clock-asynchronous serial I/O devices. The following are examples in which functions (a) to (e) are chosen: (5) Input/output to the serial I/O and the direction register To input an external signal to the serial I/O, set the direction register of the relevant port to input. To output a signal from the serial I/O, set the direction register of the relevant port to output. (6) Pins related to the serial I/O

CLK 0 pins :Input pins for the transfer clock
RxD0, RxD1 pins :Input pins for data
TxD0, TxD1 pins :Output pins for data

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 273 Figure 2.6.3. UARTi-related registers (1) UARTi bit rate generator (Note 1, 2) b0 Symbol Address When reset U0BRG 03A1 16 Indeterminate U1BRG 03A9 16 Indeterminate Function Assuming that set value = n, BRGi divides the count source by n + 1 0016 to FF16 Values that can be set W R /LiteDiagLines b7 b0 (b15) (b8) b7 b0 UARTi transmit buffer register (Note) Function Transmit data Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Symbol Address When reset U0TB 03A3 16, 03A216 Indeterminate U1TB 03AB 16, 03AA16 Indeterminate W R /LiteDiagLines (b15) Symbol Address When reset U0RB 03A7 16, 03A616 Indeterminate U1RB 03AF 16, 03AE16 Indeterminate b7 b0 (b8) b7 b0 UARTi receive buffer register Function (During UART mode) Function (During clock synchronous serial I/O mode) Bit nameBit symbol 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found Note: Bits 15 through 12 are set to “0” when the receive enable bit is set to “0”. (Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the lower byte of the UARTi receive buffer register (addresses 03A6 16, and 03AE16) is read out. Invalid Invalid Invalid OER FER PER SUM Overrun error flag (Note) Framing error flag (Note) Parity error flag (Note) Error sum flag (Note) 0 : No overrun error 1 : Overrun error found 0 : No overrun error 1 : Overrun error found Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Receive data W R Receive data /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Note : Use MOV instruction to write to this register. Note 1: Write a value to this register while transmit/receive halts. Note 2: Use MOV instruction to write to this register.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 274 Figure 2.6.4. UARTi-related registers (2) UARTi transmit/receive mode register Symbol Address When reset UiMR(i=0,1) 03A0 16, 03A816 0016 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol W R Must be fixed to 001 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited b2 b1 b0 CKDIR SMD1 SMD0 Serial I/O mode select bit (Note 1) SMD2 Internal/external clock select bit (Note 2) STPS PRY PRYE SLEP Parity enable bit 0 : Internal clock (Note 3) 1 : External clock (Note 4) Stop bit length select bit Odd/even parity select bit Sleep select bit 0 : One stop bit 1 : Two stop bits 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited b2 b1 b0 0 : Internal clock (Note 3) 1 : External clock (Note 4) Invalid Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity Invalid Invalid Must always be “0” Function (During UART mode) Function (During clock synchronous serial I/O mode) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines UARTi transmit/receive control register 0 Symbol Address When reset UiC0(i=0,1) 03A4 16, 03AC16 0816 b7 b6 b5 b4 b3 b2 b1 b0 Function (During UART mode) W R Function (Note) (During clock synchronous serial I/O mode) TXEPT CLK1 CLK0 NCH CKPOL BRG count source select bit Transmit register empty flag 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge CLK polarity select bit Data output select bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : fc is selected b1 b0 0 : LSB first 1 : MSB first 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open-drain output UFORM Transfer format select bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : fc is selected b1 b0 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output Must always be “0” Bit nameBit symbol Must always be “0” Note: UART1 cannot be used in clock synchronous serial I/O. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines Note 1: UART1 cannot be used in clock synchronous serial I/O. Note 2: UART1 can use only internal clock. Must set this bit to “1”. Note 3: Set the corresponding port direction register to “1” (output mode). Note 4: Set the corresponding port direction register to “0” (input mode). Set this bit to “0”. Set this bit to “1”. 1 0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 275 Figure 2.6.5. UARTi-related registers (3) UARTi transmit/receive control register 1 Symbol Address When reset UiC1(i=0,1) 03A5 16,03AD 16 0216 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol Function (During UART mode) Function (Note 1) (During clock synchronous serial I/O mode) TE TI RE RI Transmit enable bit Receive enable bit (Note 2) Receive complete flag Transmit buffer empty flag 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : No data present in receive buffer register 1 : Data present in receive buffer register Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. Note 1: UART1 cannot be used in clock synchronous serial I/O. Note 2: When using multiple pins to output the transfer clock, the following requirements must be met:

UART0 internal/external clock select bit (bit 3 at address 03A016) = “0”. UART transmit/receive control register 2 Symbol Address When reset UCON 03B0 16 XX000000 2 b7 b6 b5 b4 b3 b2 b1 b0 Bit name Bit symbol Function (During UART mode) Function (During clock synchronous serial I/O mode) CLKMD0 CLKMD1 UART0 transmit interrupt cause select bit UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enable Set this bit to “0”. CLK/CLKS select bit 0 UART1 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Normal mode (CLK output is CLK0 only) 1 : Transfer clock output from multiple pins function selected 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) Must always be “0” U0IRS U1IRS U0RRM CLK/CLKS select bit 1 (Note 2) Valid when bit 5 = “1” 0 : Clock output to CLK1 1 : Clock output to CLKS1 Note 1: UART1 cannot be used in clock synchronous serial I/O. Note 2: If you are using clock asynchronous serial I/O mode, you can enable 'receive enable bit' when RxD port input is “H ”. If RxD port input is “L” and you have enabled 'receive enable bit' , then receive operation starts immediately. W R /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines W R /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Set this bit to “0”. Must always be “0” Must always be “0” Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 276 In transmitting data in UART mode, choose functions from those listed in Table 2.6.4. Operations of the show the set-up procedures.

2.6.2 Operation of Serial I/O (transmission in UART mode)

Table 2.6.4. Choosed functions Note: UART1 cannot be selected external clock. Operation Item Set-up Transfer clock source Internal clock (f1 / f8 / f32 / fC ) External clock (CLK0 pin) (Note) O Transmission interrupt factor Transmission buffer empty Transmission completeO Sleep mode Sleep mode off Sleep mode selected O (1) Setting the transmit enable bit to “1” and writing transmission data to the UARTi transmit buffer register readies the data transmissible status. (2) Transmission data held in the UARTi transmit buffer register is transmitted to the UARTi transmit register. At this time, the first bit (the start bit) of the transmission data is transmitted from the TxDi pin. Then, data is transmitted, bit by bit, in sequence: LSB, ····, MSB, parity bit, and stop bit(s). (3) When the stop bit(s) is (are) transmitted, the transmit register empty flag goes to “1”, which indicates that transmission is completed. At this time, the UARTi transmit interrupt request bit goes to “1”. The transfer clock stops at “H ” level. (4) If the transmission condition of the next data is ready when transmission is completed, a start bit is generated following to stop bit(s), and the next data is transmitted.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 277 Example of wiring Example of operation Figure 2.6.6. Operation timing of transmission in UART mode TXDi R XD Microcomputer Receiver side IC Transmit enable bit (TE) Transmit buffer empty flag (Tl) Transmit register empty flag (TXEPT) D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P Start bit Parity bit TxDi “0” “1” “0” “1” “0” “1” Transmit interrupt request bit (IR) “0” “1” Cleared to “0” when interrupt request is accepted, or cleared by software D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SP D 0 D 1ST Shown in ( ) are bit symbols. SP Stopped pulsing because transfer enable bit = “0”Stop bit Data is set in UARTi transmit buffer register Transferred from UARTi transmit buffer register to UARTi transmit register Tc Transfer clock (1) Transmission enabled (2) Start transmission (3) Confirme stop bit (4) Start transmission The above timing applies to the following settings :

Parity is enabled.
One stop bit.
Transmit interrupt cause select bit = “1”. Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32, fC ) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 278 Figure 2.6.7. Set-up procedure of transmission in UART mode (1) Continued to the next page Setting UARTi transmit/receive mode register (i=0, 1) Internal/external clock select bit 0 : Internal clock Stop bit length select bit 0 : One stop bit b7 b0 0101 0 Odd/even parity select bit (Valid when bit 6 = “1”) 0 : Odd parity Parity enable bit 1 : Parity enabled Sleep select bit 0 : Invalid Serial I/O mode select bit 1 0 1 : Transfer data 8 bits long b2 b1 b0 0 1 0 UART0 transmit/receive mode register U0MR [Address 03A016] UART1 transmit/receive mode register U1MR [Address 03A816] Setting UARTi transmit/receive control register 0 (i = 0, 1) UART0 transmit/receive control register 0 U0C0 [Address 03A416] UART1 transmit/receive control register 0 U1C0 [Address 03AC16] Must be “0” in UART mode b7 b0 1000 BRG count source select bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : fC is selected b1 b0 Must be “0” in UART mode Data output select bit (Note) 0 : TxDi pin is CMOS output 1 : TxDi pin is N-channel open-drain output Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) Must be “0” in UART mode Must be “1” in UART mode Note: Set the corresponding port direction register to “1” (output mode). Setting UART transmit/receive control register 2 UART transmit/receive control register 2 UCON [Address 03B016] UART0 transmit interrupt cause select bit 1 : Transmission completed (TXEPT = 1) Must be “0” in UART mode UART1 transmit interrupt cause select bit 1 : Transmission completed (TXEPT = 1) Invalid in UART mode Must be “0” in UART mode Invalid in UART mode 0 0 b7 b0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 279 Figure 2.6.8. Set-up procedure of transmission in UART mode (2) Start transmission Setting UARTi bit rate generator (i = 0,1) UARTi bit rate generator (i = 0, 1) [Address 03A116, 03A916] UiBRG (i = 0, 1) Can be set to 0016 to FF16 (Note) b7 b0 Note: Write to UARTi bit rate generator when transmission/reception is halted. Transmission is complete Continued from the previous page UART0 transmit/receive control register 1 U0C1 [Address 03A516] UART1 transmit/receive control register 1 U1C1 [Address 03AD16] Transmit enable bit 1 : Transmission enabled b7 b0 Transmission enabled Writing transmit data UART0 transmit buffer register [Address 03A316, 03A216] U0TB UART1 transmit buffer register [Address 03AB16, 03AA16] U1TB Setting transmission data b7 b0 b7 b0 (b15) (b8) UART0 transmit/receive control register 1 U0C1 [Address 03A516] UART1 transmit/receive control register 1 U1C1 [Address 03AD16] b7 b0 Transmit buffer empty flag 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register (Writing next transmit data enabled) Checking the status of UARTi transmit buffer register (i = 0, 1) Writing next transmit data UART0 transmit buffer register [Address 03A316, 03A216] U0TB UART1 transmit buffer register [Address 03AB16, 03AA16] U1TB Setting transmission data b7 b0 b7 b0 (b15) (b8)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 280 In receiving data in UART mode, choose functions from those listed in Table 2.6.5. Operations of the 2.6.11 show the set-up procedures.

2.6.3 Operation of Serial I/O (reception in UART mode)

Table 2.6.5. Choosed functions (1) Setting the receive enable bit to “1” readies data-receivable status. (2) When the first bit (the start bit) of reception data is received from the RxDi pin. Then, data is received, bit by bit, in sequence: LSB, ····, MSB, and stop bit(s). (3) When the stop bit(s) is (are) received, the content of the UARTi receive register is transmitted to the UARTi receive buffer register. At this time, the receive complete flag goes to “1” to indicate that the reception is completed, the UARTi receive interrupt request bit goes to “1”. (4) The receive complete flag goes to “0” when the lower-order byte of the UARTi buffer register is read. Operation Item Set-up Transfer clock source Internal clock (f1 / f8 / f32 / fC ) External clock (CLK0 pin) (Note)O Sleep mode Sleep mode off Sleep mode selected O Note: UART1 cannot be selected external clock.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 281 Example of wiring Example of operation Figure 2.6.9. Operation timing of reception in UART mode R XD0 T XD Microcomputer Transmitter side IC CLK0 CLK D 0 D 1 D 7Start bit Reception started when transfer clock is generated by falling edge of start bit Sampled “L” Receive data taken in BRG0's count source Receive enable bit RxD Transfer clock Receive complete flag Stop bit “1” “0” “0” “1” Timing of transfer data 8 bits long applies to the following settings :

Transfer data length is 8 bits.
Parity is disabled.
One stop bit Receive interrupt request bit “0” “1” Cleared to “0” when interrupt request is accepted, or cleared by software Transferred from UART0 receive register to UART0 receive buffer register (1) Reception enabled (2) Start reception (4) Data is read (3) Receiving is completed Read to UART0 receive buffer register

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 282 Figure 2.6.10. Set-up procedure of reception in UART mode (1) Continued to the next page Setting UART0 transmit/receive control register 0 UART0 transmit/receive control register 0 U0C0 [Address 03A416] Must be “0” in UART mode b7 b0 1000 BRG count source select bit Invalid when external clock is selected Must be “0” in UART mode Data output select bit 0 : TxD0 pin is CMOS output 1 : TxD0 pin is N-channel open-drain output Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) Must be “0” in UART mode Must be “1” in UART mode Setting UART transmit/receive control register 2 UART transmit/receive control register 2 UCON [Address 03B016] Must be “0” in UART mode Invalid in UART mode Must be “0” in UART mode Invalid in UART mode 0 0 b7 b0 Setting UART0 transmit/receive mode register Internal/external clock select bit 1 : External clock (Note) Stop bit length select bit 0 : One stop bit b7 b0 0101 1 Valid when bit 6 = “1” Parity enable bit 0 : Parity diabled Sleep select bit 0 : Sleep mode diabled Serial I/O mode select bit 1 0 1 : Transfer data 8 bits long b2 b1 b0 0 0 UART0 transmit/receive mode register U0MR [Address 03A016] Note: UATRT1 cannot be selected external clock.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 283 Figure 2.6.11. Set-up procedure of reception in UART mode (2) Start reception Processing after reading out reception data Continued from the previous page Checking error UART0 receive buffer register [Address 03A716, 03A616]U0RB Overrun error flag 0 : No overrun error 1 : Overrun error found b7 b0 b7 b0 (b15) (b8) Receive data Framing error flag 0 : No framing error 1 : Framing error found Parity error flag 0 : No parity error 1 : Parity error found Error sum flag 0 : No error 1 : Error found Setting UART0 bit rate generator UART0 bit rate generator [Address 03A116, 03A916] U0BRG Can be set to 0016 to FF16 (Note 1) b7 b0 Note 1: Write to UARTi bit rate generator when transmission/reception is halted. Checking completion of reception UART0 transmit/receive control register 1 U0C1 [Address 03A516] b7 b0 Receive complete flag 0 : No data present in receive buffer register 1 : Data present in receive buffer register Reception enabled UART0 transmit/receive control register 1 U0C1 [Address 03A516] UART1 transmit/receive control register 1 U1C1 [Address 03AD16] b7 b0 Receive enable bit 1 : Reception enabled Note 2: Set the corresponding port direction register to “0” (input mode).

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 284

2.7 A-D Converter

Table 2.7.1. Conversion time every operation clock Note 1: The number of conversion cycles per one analog input pin. Note 2: The conversion time per one analog input pin (when fAD = f(XIN) = 10 MHz)

2.7.1 Overview

The A-D converter used in the M16C/60 group operates on a successive conversion basis. The following is an overview of the A-D converter. (1) Mode The A-D converter operates in one of five modes: (a) One-shot mode Carries out A-D conversion on input level of one specified pin only once. (b) Repetition mode Repeatedly carries out A-D conversion on input level of one specified pin. (c) Single sweep mode Carries out A-D conversion on input level of two or more specified pins only once. (d) Repeated sweep mode 0 Repeatedly carries out A-D conversion on input level of two or more pins. (e) Repeated sweep mode 1 Repeatedly carries out A-D conversion on input level of two or more pins. This mode is different from the repeated sweep mode 0 in that weights can be assigned to specifing pins control the number of conversion times. (2) Operation clock The operation clock in 5 V operation can be selected from the following: f AD , divide-by-2 fAD , and divide-by-4 fAD . In 3 V operation, the selection is divide-by-2 fAD or divide-by-4. The fAD frequency is equal to that of the CPU’s main clock. (3) Conversion time Number of conversion for A-D convertor varies depending on resolution as given. Table 2.7.1 shows relation between the A-D converter operation clock and conversion time. Sample & Hold function selected: 33 cycles for 10-bit resolution, or 28 cycles for 8-bit resolution No Sample & Hold function: 59 cycles for 10-bit resolution, or 49 cycles for 8-bit resolution Frequency selection bit 0 A-D converter's operation clock Min. conversion cycles (Note 1) Min. conversion time (Note 2) 8-bit mode 8-bit mode 10-bit mode 10-bit mode 0 1 φAD = 4 fAD φAD = 2 fAD

28 X φAD

33 X φAD

11.2µs 13.2µs 6.6µs 5.6µs Frequency selection bit 1 0 1 Invalid φAD = fAD 2.8µs 3.3µs

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 285 (4) Functions selection (a) Sample & Hold function Sample & Hold function samples input voltage when A-D conversion starts and carries out A-D conversion on the voltage sampled. When A-D conversion starts, input voltage is sampled for 3 cycles of the operation clock. When the Sample & Hold function is selected, set the operation clock for A-D conversion to 1 MHz or higher. (b) 8-bit A-D to 10-bit A-D switching function Either 8-bit resolution or 10-bit resolution can be selected. When 8-bit resolution is selected, the 8 higher-order bits of the 10-bit A-D are subjected to A-D conversion. The equations for 10-bit resolu- tion and 8-bit resolution are given below: 10-bit resolution (Vref X n / 2 10 ) – (Vref X 0.5 / 210 ) (n = 1 to 1023), 0 (n = 0) 8-bit resolution (Vref X n / 28 ) – (Vref X 0.5 / 210 ) (n = 1 to 256), 0 (n = 0) (c) Analog input group function The analog input pins can be switched between the port P6 group (AN0 to AN4) and the port P5 group (AN50 to AN54). (d) Connecting or cutting Vref Cutting Vref allows decrease of the current flowing into the A-D converter. To decrease the microcomputer's power consumption, cut Vref. To carry out A-D conversion, start A-D conversion 1 µs or longer after connecting Vref. The following are exsamples in which functions (a) through (d) are selected: (5) Input to A-D converter and direction register To use the A-D converter, set the direction register of the relevant port to input. (6) Pins related to A-D converter (a) AN 0 pin through AN7 pin Input pins of the A-D converter (Port P6 group ) (b) AN50 pin through AN57 pin Input pins of the A-D converter (Port P5 group ) (c) AVcc pin Power source pin of the analog section (d) V REF pin Input pin of reference voltage (e) AVss pin GND pin of the analog section

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 287 Figure 2.7.2. A-D converter-related registers (1) A-D control register 0 (Note 1) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bit0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected (Note 2, 3) CH0 Bit symbol Bit name Function CH1 CH2 A-D operation mode select bit 0 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 Repeat sweep mode 1 (Note 2) MD0 MD1 ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selectedCKS0 W R b2 b1 b0 b4 b3 Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again. Note 3: AN50 to AN54 can be used in the same way as for AN0 to AN4. /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Set this bit to “0”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 288 Figure 2.7.3. A-D converter-related registers (2) A-D control register 1 (Note 1) Symbol Address When reset ADCON1 03D7 16 0016 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bit SCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit ADGSEL0 A-D operation mode select bit 1 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 0 : Vref not connected 1 : Vref connected A-D input group select bit W R When single sweep and repeat sweep mode 0 are selected 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) b1 b0 When repeat sweep mode 1 is selected 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) b1 b0 0 : Port P6 group is selected 1 : Port P5 group is selected gg p , g p p g Note 3: AN50 to AN54 can be used in the same way as for AN0 to AN4. Frequency select bit 1 0 : fAD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4. Note 3: If port P5 group is selected, the contents of A-D registers 5 to 7 are indeterminate. If port P5 group is selected, do not select 8 pins sweep mode. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines (Note 2, 3) Set this bit to “0”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 289 Figure 2.7.4. A-D converter-related registers (3) A-D control register 2 (Note) Symbol Address When reset ADCON2 03D4 16 XXXX0000 2 b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion method select bit 0 : Without sample and hold 1 : With sample and hold Bit symbol Bit name Function R W Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. /LiteDiagLines /LiteDiagLines Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. A-D register i Symbol Address When reset ADi(i=0 to 7) 03C0 16 to 03CF16 Indeterminate Eight low-order bits of A-D conversion result Function R W (b15) b7b7 b0 b0 (b8)

During 10-bit mode Two high-order bits of A-D conversion result Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
During 8-bit mode The value, if read, turns out to be indeterminate. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines SMP 000 /LiteDiagLines /LiteDiagLines Reserved bit Always set to “0”

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 290 In one-shot mode, choose functions from those listed in Table 2.7.2. Operations of the circled items are

2.7.2 Operation of A-D converter (one-shot mode)

Figure 2.7.5. Operation timing of one-shot mode Operation Table 2.7.2. Choosed functions (1) Setting the A-D conversion start flag to “1” causes the A-D converter to begin operating. (2) After A-D conversion is completed, the content of the successive comparison register (con- version result) is transmitted to A-D register i. At this time, the A-D conversion interrupt re- quest bit goes to “1”. Also, the A-D conversion start flag goes to “0”, and the A-D converter stops operating. A-D conversion start flag “1” “0” A-D conversion interrupt request A-D register i “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software Result φAD 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles Set to “1” by software (1) Start A-D conversion (2) A-D conversion is complete Note: When φAD frequency is less than 1MHZ, sample and hold function cannot be selected. Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution. Item Set-up Operation clock φAD Divided-by-4 fAD / divided-by-2 fAD / fADO 8-bit / 10-bitResolution Analog input pin One of AN 0 pin to AN7 pin (Note) O O Sample & Hold Not activated ActivatedO Note : When the port P5 group is selected, analog input pins are changed from AN0 to AN4 to pins AN50 to AN54.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 291 Figure 2.7.6. Set-up procedure of one-shot mode b7 b0 Setting A-D conversion start flag A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 1 : A-D conversion started Reading conversion result Eight low-order bits of A-D conversion result b7 b0 (b15) (b8) b7 b0 A-D register 0 [Address 03C116, 03C016]A D 0 A-D register 1 [Address 03C316, 03C216]A D 1 A-D register 2 [Address 03C516, 03C416]A D 2 A-D register 3 [Address 03C716, 03C616]A D 3 A-D register 4 [Address 03C916, 03C816]A D 4 A-D register 5 [Address 03CB16, 03CA16]A D 5 A-D register 6 [Address 03CD16, 03CC16]A D 6 A-D register 7 [Address 03CF16, 03CE16]A D 7 During 10-bit mode Two high-order bits of A-D conversion result During 8-bit mode When read, the content is indeterminate Start A-D conversion Stop A-D conversion b7 b0 Selecting Sample and hold A-D control register 2 [Address 03D416] ADCON2 A-D conversion method select bit 1 : With sample and hold 1 0 0 0 Must be fixed to “0” b7 b0 Setting A-D control register 0 and A-D control register 1 A-D control register 0 [Address 03D616] ADCON0 Analog input pin select bit (Note 2) 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected b2 b1 b0 b7 b0 A-D control register 1 [Address 03D716] ADCON1 A-D operation mode select bit 1 (Note 1) 0 (Must always be “0” in one-shot mode) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : f AD /2 or fAD /4 is selected 1 : fAD is selectedOne-shot mode is selected (Note 1) Must be fixed to “0” A-D conversion start flag 0 : A-D conversion disabled Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selected 000 0 Invalid in one-shot mode Vref connect bit 1 : Vref connected A-D input group select bit 0 : Port P6 group is selected 1 : Port P5 group is selected 00 1 Note 1: Rewrite to analog input pin select bit after changing A-D operation mode. Note 2: Set the corresponding port direction register to “0” (input mode). When the port P5 group is selected, analog input pins are changed from AN0 to AN4 to pins AN50 to AN54. Must be fixed to “0”

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 292 In repeat mode, choose functions from those listed in Table 2.7.3. Operations of the circled items are

2.7.3 Operation of A-D Converter (in repeat mode)

(1) Setting the A-D conversion start flag to “1” causes the A-D converter to start operating. (2) After the first conversion is completed, the content of the successive comparison register (conversion result) is transmitted to A-D register i. The A-D conversion interrupt request bit does not go to “1”. (3) The A-D converter continues operating until the A-D conversion start flag is set to “0” by software. The conversion result is transmitted to A-D register i every time a conversion is completed. Table 2.7.3. Choosed functions Operation Figure 2.7.7. Operation timing of repeat mode Item Set-up Operation clock φAD Divided-by-4 fAD / divided-by-2 fAD / fADO 8-bit / 10-bitResolution Analog input pin One of AN 0 pin to AN7 pin (Note) O O Sample & Hold Not activated ActivatedO Note : When the port P5 group is selected, analog input pins are changed from AN0 to AN4 to pins AN50 to AN54. A-D conversion start flag “1” “0” A-D register i Result Set to “1” by software φAD 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles (1) Start A-D conversion (2) Conversion result is transferred to the A-D register (3) A-D conversion is complete Cleared to “0” by software A-D conversion Result Stop Convert Convert Convert Stop Note:When φAD frequency is less than 1MHz, sample and hold function cannot be selected. Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution. 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 293 Figure 2.7.8. Set-up procedure of repeat mode b7 b0 Setting A-D conversion start flag A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 1 : A-D conversion started Reading conversion result Eight low-order bits of A-D conversion result b7 b0 (b15) (b8) b7 b0 A-D register 0 [Address 03C116, 03C016]A D 0 A-D register 1 [Address 03C316, 03C216]A D 1 A-D register 2 [Address 03C516, 03C416]A D 2 A-D register 3 [Address 03C716, 03C616]A D 3 A-D register 4 [Address 03C916, 03C816]A D 4 A-D register 5 [Address 03CB16, 03CA16]A D 5 A-D register 6 [Address 03CD16, 03CC16]A D 6 A-D register 7 [Address 03CF16, 03CE16]A D 7 During 10-bit mode Two high-order bits of A-D conversion result During 8-bit mode When read, the content is indeterminate Start A-D conversion b7 b0 Selecting Sample and hold A-D control register 2 [Address 03D416] ADCON2 A-D conversion method select bit 1 : With sample and hold 1 0 0 0 Must be fixed to “0” b7 b0 Setting A-D control register 0 and A-D control register 1 A-D control register 0 [Address 03D616] ADCON0 Analog input pin select bit (Note 2) 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected b2 b1 b0 b7 b0 A-D control register 1 [Address 03D716] ADCON1 A-D operation mode select bit 1 (Note 1) 0 (Must always be “0” in repeat mode) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : f AD /2 or fAD /4 is selected 1 : fAD is selectedRepeat mode is selected (Note 1) Must be fixed to “0” A-D conversion start flag 0 : A-D conversion disabled Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selected 000 1 Invalid in repeat mode Vref connect bit 1 : Vref connected A-D input group select bit 0 : Port P6 group is selected 1 : Port P5 group is selected 00 1 Note 1: Rewrite to analog input pin select bit after changing A-D operation mode. Note 2: Set the corresponding port direction register to “0” (input mode). When the port P5 group is selected, analog input pins are changed from AN0 to AN4 to pins AN50 to AN54. Must be fixed to “0” b7 b0 Setting A-D conversion start flag A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 0 : A-D conversion disabled Stop A-D conversion

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 294 In single sweep mode, choose functions from those listed in Table 2.7.4. Operations of the circled items

2.7.4 Operation of A-D Converter (in single sweep mode)

Figure 2.7.9. Operation timing of single sweep mode Operation (1) Setting the A-D conversion start flag to “1” causes the A-D converter to start the conversion on voltage input to the AN0/AN50 pin. (2) After the A-D conversion of voltage input to the AN0/AN50 pin is completed, the content of the successive comparison register (conversion result) is transmitted to A-D register 0. The A-D converter converts all analog input pins selected by the user. The conversion result is trans- mitted to A-D register i corresponding to each pin, every time conversion on one pin is com- pleted. (3) When the A-D conversion on all the analog input pins selected is completed, the A-D conver- sion interrupt request bit goes to “1”. At this time, the A-D conversion start flag goes to “0”. The A-D converter stops operating. Table 2.7.4. Choosed functions Item Set-up Operation clock φAD Divided-by-4 fAD / divided-by-2 fAD / fADO 8-bit / 10-bitResolution O Analog input pin AN 0 and AN1 (2 pins) / AN0 to AN3 (4 pins) / AN0 to AN5 (6 pins) / AN0 to AN7 (8 pins) (Note)O Sample & Hold Not activated ActivatedO Note : When the port P5 group is selected, analog input pins are changed from AN0 to AN4 to pins AN50 to AN54. Cleared to “0” when interrupt request is accepted, or cleared by software A-D conversion start flag “1” “0” A-D register 0 A-D register 1 φAD A-D register i Result Result Result Set to “1” by software 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles (1) Start A-D conversion After A-D conversion on AN0/AN50 pin is complete, A-D converter begins converting all pins selected A-D conversion is complete (2) Note: When φAD frequency is less than 1MHZ, sample and hold function cannot be selected. Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution. (3) A-D conversion interrupt request bit “1” “0”

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 295 Figure 2.7.10. Set-up procedure of single sweep mode b7 b0 Setting A-D conversion start flag A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 1 : A-D conversion started Reading conversion result Eight low-order bits of A-D conversion result b7 b0 (b15) (b8) b7 b0 A-D register 0 [Address 03C116, 03C016]A D 0 A-D register 1 [Address 03C316, 03C216]A D 1 A-D register 2 [Address 03C516, 03C416]A D 2 A-D register 3 [Address 03C716, 03C616]A D 3 A-D register 4 [Address 03C916, 03C816]A D 4 A-D register 5 [Address 03CB16, 03CA16]A D 5 A-D register 6 [Address 03CD16, 03CC16]A D 6 A-D register 7 [Address 03CF16, 03CE16]A D 7 During 10-bit mode Two high-order bits of A-D conversion result During 8-bit mode When read, the content is indeterminate Start A-D conversion Stop A-D conversion b7 b0 Selecting Sample and hold A-D control register 2 [Address 03D416] ADCON2 A-D conversion method select bit 1 : With sample and hold 1 0 0 0 Must be fixed to “0” b7 b0 Setting A-D control register 0 and A-D control register 1 A-D control register 0 [Address 03D616] ADCON0 Invalid in single sweep mode b7 b0 A-D control register 1 [Address 03D716] ADCON1 A-D operation mode select bit 1 (Note 1) 0 (Must always be “0” in single sweep mode) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : f AD /2 or fAD /4 is selected 1 : fAD is selected Single sweep mode is selected (Note 1) Must be fixed to “0” A-D conversion start flag 0 : A-D conversion disabled Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selected 001 0 Vref connect bit 1 : Vref connected A-D input group select bit 0 : Port P6 group is selected 1 : Port P5 group is selected 00 1 Note 1: Rewrite to analog input pin select bit after changing A-D operation mode. Note 2: Set the corresponding port direction register to “0” (input mode). When the port P5 group is selected, analog input pins are changed from AN0 to AN4 to pins AN50 to AN54. Must be fixed to “0” A-D sweep pin select bit (Note 2) 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) b1 b0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 296 In repeat sweep 0 mode, choose functions from those listed in Table 2.7.5. Operations of the circled items

2.7.5 Operation of A-D Converter (in repeat sweep mode 0)

Table 2.7.5. Choosed functions (1) Setting the A-D conversion start flag to “1” causes the A-D converter to start the conversion on voltage input to the AN0/AN50 pin. (2) After the A-D conversion of voltage input to the AN0/AN50 pin is completed, the content of the successive comparison register (conversion result) is transmitted to A-D register 0. (3) The A-D converter converts all pins selected by the user. The conversion result is transmitted to A-D register i corresponding to each pin every time A-D conversion on the pin is com- pleted. The A-D conversion interrupt request bit does not go to “1”. (4) The A-D converter continues operating until the A-D conversion start flag is set to “0” by software. Figure 2.7.11. Operation timing of repeat sweep 0 mode Item Set-up Operation clock φAD Divided-by-4 fAD / divided-by-2 fAD / fADO 8-bit / 10-bitResolution O Analog input pin AN 0 and AN1 (2 pins) / AN0 to AN3 (4 pins) / AN0 to AN5 (6 pins) / AN0 to AN7 (8 pins) (Note)O Sample & Hold Not activated ActivatedO Note : When the port P5 group is selected, analog input pins are changed from AN0 to AN4 to pins AN50 to AN54. (2) AN1/AN51 conversion begins after AN0/AN50 conversion is complete A-D conversion start flag “1” “0” A-D register 0 A-D register 1 φAD A-D register i Result Result Result 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles (3) Consecutive conversion A-D conversion is complete (1) Start A-D conversion Set to “1” by software. Cleared to “0” by software Note:When φAD frequency is less than 1MHZ, sample and hold function cannot be selected. Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution. (4)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 297 Figure 2.7.12. Set-up procedure of repeat sweep 0 mode b7 b0 Setting A-D conversion start flag A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 1 : A-D conversion started Reading conversion result Eight low-order bits of A-D conversion result b7 b0 (b15) (b8) b7 b0 A-D register 0 [Address 03C116, 03C016]A D 0 A-D register 1 [Address 03C316, 03C216]A D 1 A-D register 2 [Address 03C516, 03C416]A D 2 A-D register 3 [Address 03C716, 03C616]A D 3 A-D register 4 [Address 03C916, 03C816]A D 4 A-D register 5 [Address 03CB16, 03CA16]A D 5 A-D register 6 [Address 03CD16, 03CC16]A D 6 A-D register 7 [Address 03CF16, 03CE16]A D 7 During 10-bit mode Two high-order bits of A-D conversion result During 8-bit mode When read, the content is indeterminate Start A-D conversion b7 b0 Selecting Sample and hold A-D control register 2 [Address 03D416] ADCON2 A-D conversion method select bit 1 : With sample and hold 1 0 0 0 Must be fixed to “0” b7 b0 Setting A-D conversion start flag A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 0 : A-D conversion disabled Stop A-D conversion b7 b0 Setting A-D control register 0 and A-D control register 1 A-D control register 0 [Address 03D616] ADCON0 Invalid in repeat sweep mode 0 b7 b0 A-D control register 1 [Address 03D716] ADCON1 A-D operation mode select bit 1 (Note 1) 0 (Must always be “0” in repeat sweep mode 0) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : f AD /2 or fAD /4 is selected 1 : fAD is selected Repeat sweep mode 0 is selected (Note 1) Must be fixed to “0” A-D conversion start flag 0 : A-D conversion disabled Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selected 001 1 Vref connect bit 1 : Vref connected A-D input group select bit 0 : Port P6 group is selected 1 : Port P5 group is selected 00 1 Note 1: Rewrite to analog input pin select bit after changing A-D operation mode. Note 2: Set the corresponding port direction register to “0” (input mode). When the port P5 group is selected, analog input pins are changed from AN0 to AN4 to pins AN50 to AN54. Must be fixed to “0” A-D sweep pin select bit (Note 2) 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) b1 b0 Repeatedly carries out A-D conversion on pins selected through the A-D sweep pin select bit.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 298

2.7.6 Operation of A-D Converter (in repeat sweep mode 1)

Figure 2.7.14. Operation timing of repeat sweep 1 mode In repeat sweep 1 mode, choose functions from those listed in Table 2.7.6. Operations of the circled items are 2.7.15 shows the set-up procedure. Operation (1) Setting the A-D conversion start flag to “1” causes the A-D converter to start the conversion on voltage input to the AN0/AN50 pin. (2) After the A-D conversion on voltage input to the AN0/AN50 pin is completed, the content of the succes- sive comparison register (conversion result) is transmitted to A-D register 0. (3) Every time the A-D converter carries out A-D conversion on a selected analog input pin, the A-D converter carries out A-D conversion on only one unselected pin, and then the A-D converter carries out A-D conver- sion from the AN0 pin again. (See Figure 2.7.13.) The conversion result is transmitted to A-D register i every time conversion on a pin is completed. The A-D conversion interrupt request bit does not go to “1”. (4) The A-D converter continues operating until software goes the A-D conversion start flag to “0”. Table 2.7.6. Choosed functions Figure 2.7.13. ANi pin's sweep sequence in repeat sweep mode Item Set-up Operation clock φAD Divided-by-4 fAD / divided-by-2 fAD / fADO 8-bit / 10-bitResolution O Analog input pin AN 0 (1 pins) / AN0 to AN1 (2 pins) / AN0 to AN2 (3 pins) / AN0 to AN3 (4 pins) (Note)O Sample & Hold Not activated ActivatedO Note : When the port P5 group is selected, analog input pins are changed from AN0 to AN4 to pins AN50 to AN54. When AN 0 is selected Converted analog input pin Time 0000000000 When AN 0, AN1 are selected Converted analog input pin Time 0000000 1111111 Converted analog input pin Time 0000000 222222 111111 When AN 0 to AN2 are selected Converted analog input pin Time 000000 3333 11111 2222 When AN 0 to AN3 are selected A-D conversion start flag “1” “0” A-D register 0 A-D register 1 φAD A-D register 2 Result Result Result Set to “1” by software Result Cleared to “0” by software (2) (3) Consecutive conversion 8-bit resolution : 28 φAD cycles 10-bit resolution : φAD cycles A-D conversion is complete (4) Conversion result is transfered to A-D conversion register Note: When φAD frequency is less than 1MHz, sample and hold function cannot be selected. Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution. 8-bit resolution : 28 φAD cycles 10-bit resolution : φAD cycles 8-bit resolution : φAD cycles 10-bit resolution : φAD cycles 8-bit resolution : AD cycles 10-bit resolution : AD cycles (1) Start AN0 /AN50 pin conversion

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 299 Figure 2.7.15. Set-up procedure of repeat sweep 1 mode b7 b0 Setting A-D conversion start flag A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 1 : A-D conversion started Reading conversion result Eight low-order bits of A-D conversion result b7 b0 (b15) (b8) b7 b0 A-D register 0 [Address 03C116, 03C016]A D 0 A-D register 1 [Address 03C316, 03C216]A D 1 A-D register 2 [Address 03C516, 03C416]A D 2 A-D register 3 [Address 03C716, 03C616]A D 3 A-D register 4 [Address 03C916, 03C816]A D 4 A-D register 5 [Address 03CB16, 03CA16]A D 5 A-D register 6 [Address 03CD16, 03CC16]A D 6 A-D register 7 [Address 03CF16, 03CE16]A D 7 During 10-bit mode Two high-order bits of A-D conversion result During 8-bit mode When read, the content is indeterminate Start A-D conversion b7 b0 Selecting Sample and hold A-D control register 2 [Address 03D416] ADCON2 A-D conversion method select bit 1 : With sample and hold 1 0 0 0 Must be fixed to “0” b7 b0 Setting A-D conversion start flag A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 0 : A-D conversion disabled Stop A-D conversion b7 b0 Setting A-D control register 0 and A-D control register 1 A-D control register 0 [Address 03D616] ADCON0 Invalid in repeat sweep mode 1 b7 b0 A-D control register 1 [Address 03D716] ADCON1 A-D operation mode select bit 1 (Note 1) 1 (Must always be “1” in repeat sweep mode 1) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : f AD /2 or fAD /4 is selected 1 : fAD is selected Repeat sweep mode 1 is selected (Note 1) Must be fixed to “0” A-D conversion start flag 0 : A-D conversion disabled Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selected 001 1 Vref connect bit 1 : Vref connected A-D input group select bit 0 : Port P6 group is selected 1 : Port P5 group is selected 01 1 Note 1: Rewrite to analog input pin select bit after changing A-D operation mode. Note 2: Set the corresponding port direction register to “0” (input mode). When the port P5 group is selected, analog input pins are changed from AN0 to AN4 to pins AN50 to AN54. Must be fixed to “0” A-D sweep pin select bit (Note 2) 0 0 : AN0 (1 pins) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) b1 b0 Converts non-selected pin after converting pins selected through the A-D sweep pin select bit.

M itsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 300 2.7. 7 Precautions for A-D Converter Figure 2.7.16. Use of capacitors to reduce noice (1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit 0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs). In particular, when the Vref connection bit is changed from 0 to 1, start A-D conversion after an elapse of 1 µs or longer. (2) To reduce conversion error due to noise, connect a voltage to the AVcc pin and to the Vref pin from an independent source. It is recommended to connect a capacitor between the AVss pin and the AVcc pin, between the AVss pin and the Vref pin, and between the AVss pin and the analog input pin (ANi/AN 5i). Figure 2.7.16 shows the an example of connecting the capaci- tors to these pins. AV SS AV CC VREF AN i Microcomputer C1 C2 C3 C 10.47 µF, C 20.47 µF, C 3100 pF (for reference) Use thick and shortest possible wiring to connect capacitors. Note Note 2: VCC (3) Set the direction register of the following ports to input: the port corresponding to a pin to be used as an analog input pin and external trigger input pin. (4) If using the A-D converter with Vcc = 2.7V to 4.0 V: Use without fAD (no frequency division) for AD . Select without the Sample & Hold feature. Select 8-bit mode. (5) Rewrite to analog input pin after changing A-D operation mode. The two cannot be set at the same time. (6) When using the one-shot or single sweep mode Confirm that A-D conversion is complete before reading the A-D register. (Note: When A-D conversion interrupt request bit is set, it shows that A-D conversion is completed.) (7) When using the repeat mode or repeat sweep mode 0 or 1 Use the undivided main clock as the internal CPU clock.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 301 (1) The A-D converter compares the reference voltage (Vref) generated internally based on the contents of the successive comparison register with the analog input voltage (VIN) input from the analog input pin. Each bit of the comparison result is stored in the successive comparison register until analog-to-digital conversion (successive comparison method) is complete. If a trigger occurs, the A-D converter carries out the following: 1. Fixes bit 9 of the successive comparison register. Compares Vref with V IN: [In this instance, the contents of the successive comparison register are “10000000002” (default).] Bit 9 of the successive comparison register varies depending on the comparison re- sult as follows. If Vref < V IN, then “1” is assigned to bit 9. If Vref > VIN, then “0” is assigned to bit 9. 2. Fixes bit 8 of the successive comparison register. Sets bit 8 of the successive comparison register to “1”, then compares Vref with VIN. Bit 8 of the successive comparison register varies depending on the comparison result as follows: If Vref < V IN, then “1” is assigned to bit 8. If Vref > VIN, then “0” is assigned to bit 8. 3. Fixes bit 7 through bit 0 of the successive comparison register. Carries out step 2 above on bit 7 through bit 0. After bit 0 is fixed, the contents of the successive comparison register (conversion result) are transmitted to A-D register i. Vref is generated based on the latest content of the successive comparison register. Table 2.7.7 shows the relationship of the successive comparison register contents and Vref. Table 2.7.8 shows how the successive comparison register and Vref vary while A-D conversion is in progress. Figure 2.7.17 shows theoretical A-D conversion characteristics.

2.7.8 Method of A-D Conversion (10-bit mode)

Table 2.7.7. Relationship of the successive comparison register contents and Vref Successive approximation register : n Vref (V) x –1024 VREF 2048 VREFn 1 to1023

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 302 Figure 2.7.17. Theoretical A-D conversion characteristics (10-bit mode) Table 2.7.8. Variation of the successive comparison register and Vref while A-D conversion is in progress (10-bit mode) 000000000 000000000 100000000 n9 n8 10000000 n9 n8 n7 n6 n5 n4 n3 n2 n1 0 n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 b9 b0 1st comparison result 2nd comparison result Successive approximation register V ref change A-D converter stopped 1st comparison 2nd comparison 3rd comparison 10th comparison Conversion complete VREF ± ±2 VREF VREF 1024 – 2048 VREF [V] 2 [V] VREF 2048 VREF [V] ± ±2 VREF VREF VREF – 2048 VREF [V] 4n9 = 1 + n9 = 0 – n8 = 1 + VREFn8 = 0 – VREF VREF – 2048 VREF [V] VREF VREF VREF This data transfers to the bit 0 to bit 9 of A-D register. 00016 00116 00216 00316 3FE 16 3FF16 Result of A-D conversion Analog input voltage VREF 1024 x 1 VREF 1024 x 2 VREF 1024 x 3 x 1021VREF 1024 VREF 1024 x 1022 VREF 1024 x 1023 VREF VREF 1024 x 0.5 Theoretical A-D conversion characteristic Ideal A-D conversion characteristic

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 303 (1) In 8-bit mode, 8 higher-order bits of the 10-bit successive comparison register becomes A-D conversion result. Hence, if compared to a result obtained by using an 8-bit A-D converter, the voltage compared is different by 3 VREF /2048 (see what are underscored in Table 2.7.9), and differences in stepping points of output codes occur as shown in Figure 2.7.18.

2.7.9 Method of A-D Conversion (8-bit mode)

Figure 2.7.18. The level conversion characteristics of 8-bit mode and 8-bit A-D converter Table 2.7.9. The comparison voltage in 8-bit mode compared to 8-bit A-D converter Comparison voltage Vref 8-bit mode 8-bit A-D converter VREF 210 VREFn x 0.5 x – VREF VREFn x 0.5 n = 0 n = 1 to 255 x Analog input voltage (mV) Output code (Result of A-D conversion) Analog input voltage (mV) Output code (Result of A-D conversion) 10-bit mode 8-bit mode 8bit-mode 10bit-mode 10 30 17.5 37.5 (Note) Optimal conversion characteristics of 8-bit A-D converter (VREF = 5.12 V) Optimal conversion characteristics in 8-bit mode (VREF = 5.12 V) Note: Differences in stepping points of output code for analog input voltage.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 304 Table 2.7.10. Variation of the successive comparison register and Vref while A-D conversion is in progress (8-bit mode) Figure 2.7.19. Theoretical A-D conversion characteristics (8-bit mode) 000000000 000000000 100000000 n9 n8 10000000 n9 n8 n7 n6 n5 n4 n3 100 n9 n8 n7 n6 n5 n4 n3 n2 00 b9 b0 1st comparison result 2nd comparison result Successive approximation register Vref change A-D converter stopped 1st comparison 2nd comparison 3rd comparison 8th comparison Conversion complete ± ±2 VREF VREF 256 – 2048 VREF [V] VREF [V] VREF 2048 VREF [V] VREF VREF – 2048 VREF [V] ± ±2 VREF VREF VREF – 2048 VREF [V] VREFn9 = 1 + VREF n9 = 0 – VREFn8 = 1 + VREF n8 = 0 – This data transfers to bit 0 to bit 7 of A-D register. 0016 0116 0216 0316 FE 16 FF16 Result of A-D conversion Analog input voltage x 2VREF 256 VREF 256 x 3 x 4VREF 256 VREF 256 x 254 VREF 256 x 255 VREF VREF 2048 x 3 Theoretical A-D conversion characteristic of general 8-bit A-D converter

0 VREF

Theoretical A-D conversion characteristic in the 8-bit mode

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 305

2.7.10 Absolute Accuracy and Differential Non-Linearity Error

Absolute accuracy Absolute accuracy is the difference between output code based on the theoretical A-D conversion characteristics, and actual A-D conversion result. When measuring absolute accuracy, the voltage at the middle point of the width of analog input voltage (1-LSB width), that can meet the expectation of outputting an equal code based on the theoretical A-D conversion characteristics, is used as an ana- log input voltage. For example, if 10-bit resolution is used and if V REF (reference voltage) = 5.12 V, then 1-LSB width becomes 5 mV, and 0 mV, 5 mV, 10 mV, 15 mV, 20 mV, ···· are used as analog input voltages. If analog input voltage is 25 mV, “absolute accuracy =± 3LSB ” refers to the fact that actual A-D conversion falls on a range from “00216” to ”00816” though an output code, “00516”, can be ex- pected from the theoretical A-D conversion characteristics. Zero error and full-scale error are included in absolute accuracy. Also, all the output codes for analog input voltage between V REF and AVcc becomes “3FF16”. Figure 2.7.20. Absolute accuracy (10-bit resolution) 00016 00116 00216 00316 00416 00516 00616 Analog input voltage (mV) Theoretical A-D conversion characteristic 5 1 0 1 52 02 53 03 5 4 04 55 05 5 00716 00816 00916 00A16 00B16 +3LSB –3LSB Output code (result of A-D conversion)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 306

Differential non-linearity error Differential non-linearity error refers to the difference between 1-LSB width based on the theoretical A- D conversion characteristics (an analog input width that can meet the expectation of outputting an equal code) and an actually measured 1-LSB width (analog input voltage width that outputs an equal code). If 10-bit resolution is used and if V REF (reference voltage) = 5.12 V, “differential non-linearity error = ± 1LSB” refers to the fact that 1-LSB width actually measured falls on a range from 0 mV to 10 mV though 1-LSB width based on the theoretical A-D conversion characteristics is 5 mV (see 5.2 A-D converter's standard characteristics). Figure 2.7.21. Differential non-linearity error (10-bit resolution) 00016 00116 00216 00316 00416 00516 00616 Analog input voltage (mV) Differential non-linear error 5 1 01 5 2 02 5 3 03 54 0 4 5 00716 00816 00916 Output code (result of A-D conversion) 1LSB width for theoretical A-D conversion characteristic

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 307

2.7.11 Internal Equivalent Circuit of Analog Input

Figure 2.7.22 shows the internal equivalent circuit of analog input. Figure 2.7.22. Internal equivalent circuit to analog input ON resistor approx. 2k A-D successive conversion register Analog input voltage AVcc AVss Chopper-type amplifier ADT/A-D conversion interrupt request Vcc Vss VIN A-D control register 0 Comparison voltage Comparison reference voltage (Vref) generator VREF AVss Vref b2 b1 b0 Vcc Vss AN i Wiring resistor approx. 0.2k ON resistor approx. 0.6k SW2 Sampling control signal SW1 C = Approx. 3.0pF SW3SW4 AMP ON resistor, approx. 5k SW2 Reference control signal Resistor ladder Control signal for SW2 Control signal for SW3 Connect to Connect to Comparison Connect to Connect to Sampling i ladder-type switches i ladder-type wiring resistors ON resistor approx. 0.6k AN0 Parasitic diode SW1 SW1 conducts only on the ports selected for analog input. SW2 and SW3 are open when A-D conversion is not in progress; their status varies as shown by the waveforms in the diagrams on the left. SW4 conducts only when A-D conversion is not in progress. Parasitic diode Warning: Use only as a standard for designing this data. Mass production may cause some changes in device characteristics. (i = 10) (i = 10) Ω Ω Ω Ω Ω

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 308 To carry out A-D conversion properly, charging the internal capacitor C shown in Figure 2.7.23 has to be completed within a specified period of time. With T as the specified time, time T is the time that switches SW2 and SW3 are connected to O in Figure 2.7.22. Let output impedance of sensor equivalent circuit be R0, microcomputer’s internal resistance be R, precision (error) of the A-D converter be X, and the A-D converter’s resolution be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode). Vc is generally V C = VIN {1 – e} And when t = T, VC =VIN – VIN=VIN(1 – ) e = – =ln Hence, R0 = –– R With the model shown in Figure 2.7.29 as an example, when the difference between VIN and VC becomes 0.1LSB, we find impedance R0 when voltage between pins VC changes from 0 to VIN-(0.1/1024) VIN in time T. (0.1/1024) means that A-D precision drop due to insufficient capacitor charge is held to 0.1LSB at time of A-D conversion in the 10-bit mode. Actual error however is the value of absolute precision added to 0.1LSB. When f(X IN) = 10 MHz, T = 0.3 us in the A-D conversion mode with sample & hold. Output impedance R0 for sufficiently charging capacitor C within time T is determined as follows. T = 0.3 µs, R = 7.8 kΩ , C = 3 pF, X = 0.1, and Y = 1024 . Hence, R0 = –– 7.8 X103 3.0 X 103

2.7.12 Sensor’s Output Impedance under A-D Conversion

Thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the A-D con- based on the LSB values. Figure 2.7.23 A circuit equivalent to the A-D conversion terminal C (R0 +R) T C (R0 + R) T C (R0 + R) t Y X Y X Y X Y X C • ln T Y X

3.0 X 10 –12 • ln

0.1

0.3 X 10-6

C (3.0pF)VIN Microprocessor's inside Sensor-equivalent circuit R (7.8k )R 0 Ω

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 309 Tables 2.7.11. Relation between output impedance and precision (error) of A-D converter (10-bit mode) Reference value Tables 2.7.12. Relation between output impedance and precision (error) of A-D converter (8-bit mode) Reference value f(Xin) Cycle Sampling time R C Resolution R0 (MHz) (pF) (LSB) (3 x cycle, 0.3 4.5 Sample & hold 0.5 5.3 bit is 0.7 5.9 enabled) 0.9 6.4 1.1 6.8 1.3 7.2 1.5 7.5 1.7 7.8 1.9 8.1 (2 x cycle, 0.5 0.9 Sample & hold 0.7 1.3 bit is 0.9 1.7 disabled) 1.1 2.0 1.3 2.2 1.5 2.4 1.7 2.6 1.9 2.8 f(Xin) Cycle Sampling time R C Resolution R0 (MHz) (pF) (LSB) (3 x cycle, 0.3 7.0 Sample & hold 0.5 8.2 bit is 0.7 9.1 enabled) 0.9 9.9 1.1 10.5 1.3 11.1 1.5 11.7 1.7 12.1 1.9 12.6 (2 x cycle, 0.3 2.1 Sample & hold 0.5 2.9 bit is 0.7 3.5 disabled) 0.9 4.0 1.1 4.4 1.3 4.8 1.5 5.2 1.7 5.5 1.9 5.8

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER W atchdog Timer 310

2.8.1 Overview

The watchdog timer can detect a runaway program using its 15-bit timer prescaler. The following is an overview of the watchdog timer. (1) Watchdog timer start procedure When reset, the watchdog timer is in stopped state. Writing to the watchdog timer start register initializes the watchdog timer to 7FFF 16 and causes it to start performing a down count. The watchdog timer, once started operating, cannot be stopped by any means other than stopping conditions. (2) Watchdog timer stop conditions The watchdog timer stops in any one of the following states: (a) Period in which the CPU is in stopped state (b) Period in which the CPU is in waiting state (3) Watchdog timer initialization The watchdog timer is initialized to 7FFF 16 in the cases given below, and begins a down count. (a) When the watchdog timer writes to the watchdog timer start register while a count is in progress (b) When the watchdog timer underflows (4) Runaway detection When the watchdog timer underflows, a watchdog timer interrupt occurs. In writing a program, write to the watchdog timer start register before the watchdog timer underflows. The watchdog timer interrupt occurs regardless of the status of the interrupt enable flag (I flag). In processing a watchdog timer interrupt, set the software reset bit to “1” to reset software. (5) Watchdog timer cycle The watchdog timer cycle varies depending on the BCLK and the frequency division ratio of the prescaler selected.

2.8 Watchdog Timer

Table 2.8.1. The watchdog timer cycle CM07 CM06 CM17 CM16 BCLK WDC7 Period 0001 0 M H z 00 1 5 M H z 0 1 0 2.5MHz 0 1 1 0.625MHz 1 Invalid Invalid 1.25MHz Invalid Invalid Invalid 32kHz Invalid Approx. 52.4ms (Note) Approx. 419.2ms (Note) Approx. 104.9ms (Note) Approx. 838.8ms (Note) Approx. 209.7ms (Note) Approx. 1.68s (Note) Approx. 838.8ms (Note) Approx. 6.71s (Note) Approx. 419.2ms (Note) Approx. 3.35s (Note) Approx. 2s (Note) Note: An error due to the prescaler occurs.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Watchdog Timer 312

2.8.2 Operation of Watchdog Timer

The following is an operation of the watchdog timer. Figure 2.8.3 shows the operation timing, and Figure 2.8.4 shows the set-up procedure. (1) Writing to the watchdog timer start register initializes the watchdog timer to 7FFF16 and causes it to start a down count. (2) With a count in progress, writing to the watchdog timer start register again initializes the watchdog timer to 7FFF16 and causes it to resume counting. (3) Either executing the WAIT instruction or going to the stopped state causes the watchdog timer to hold the count in progress and to stop counting. The watchdog timer resumes count- ing after returning from the execution of the WAIT instruction or from the stopped state. (4) If the watchdog timer underflows, it is initialized to 7FFF 16 and continues counting. At this time, a watchdog timer interrupt occurs. Operation Figure 2.8.3. Operation timing of watchdog timer (1) Start count Write signal to the watchdog timer start register 7FFF 000016 “H ” “L” (4) Generate watchdog timer interrupt (2) Write operation (3)In stopped state, or WAIT instruction is executing, etc

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Watchdog Timer 313 Figure 2.8.4. Set-up procedure of watchdog timer Reserved bit Must always be “0” Watchdog timer control register [Address 000F16] WDC Setting watchdog timer control register b7 b0 Setting watchdog timer start register The watchdog timer is initialized and starts counting with a write instruction to this register. The watchdog timer value is always initialized to “7FFF 16” regardless of the value written. Watchdog timer start register [Address 000E16] WDTS b0b7 Software reset Software reset bit The device is reset when this bit is set to “1”. The value of this bit is “0” when read. Processor mode register 0 [Address 000416] PM0 b7 b0 Generating watchdog timer interrupt Prescaler select bit 0 : Divided by 16 1 : Divided by 128

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Address Match Interrupt 314

2.9.1 Overview

The address match interrupt is used for correcting a ROM or for a simplified debugging-purpose monitor. The following is an overview of the address match interrupt. (1) Enabling/disabling the address match interrupt The address match interrupt enable bit can be used to enable and disable an address match interrupt. It is affected neither by the processor interrupt priority level (IPL) nor the interrupt enable flag (I flag). (2) Timing of the address match interrupt An interrupt occurs immediately before executing the instruction in the address indicated by the ad- dress match interrupt register. Set the first address of the instruction in the address match interrupt register. Setting a half address of an instruction or an address of tabulated data does not generate an address match interrupt. The first instruction of an interrupt routine does not generate an address match interrupt either. (3) Returning from an address match interrupt The return address put in the stack when an address match interrupt occurs depends on the instruc- tion not yet executed (the instruction the address match interrupt register indicates). The return ad- dress is not put in the stack. For this reason, to return from an address match interrupt, either rewrite the content of the stack and use the REIT instruction or use the POP instruction to restore the stack to the state as it was before the interrupt occurred and return by use of a jump instruction. Figure 2.9.1 shows unexecuted instructions and corresponding the stacked addresses.

2.9 Address Match Interrupt

<Instructions whose address is added to by 2 when an address match interrupt occurs>

16-bit operation code instructions
8-bit operation code instructions given below ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ.B:S #IMM8,dest STNZ.B:S #IMM8,dest STZX.B:S #IMM81,#IMM82,dest CMP.B:S #IMM8,dest PUSHM src POPM dest JMPS #IMM8 JSRS #IMM8 MOV.B:S #IMM,dest (However, dest = A0/A1) <Instructions whose address is added to by 1 when an address match interrupt occurs>
Instructions other than those listed above Figure 2.9.1. Unexecuted instructions and corresponding stacked addresses (4) How to determine an address match interrupt Address match interrupts can be set at two different locations. However, both location will have the same vector address. Therefore, it is necessary to determine which interrupt has occurred; address match interrupt 0 or address match interrupt 1. Using the content of the stack, etc., determine which interrupt has occurred according to the first part of the address match interrupt routine.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Address Match Interrupt 316

2.9.2 Operation of Address Match Interrupt

The following is an operation of address match interrupt. Figure 2.9.4 shows the set-up procedure of address match interrupt, and Figure 2.9.5 shows the overview of the address match interrupt handling routine. Operation (1) The address match interrupt handling routine sets an address to be used to cause the ad- dress match interrupt register to generate an interrupt. (2) Setting the address match enable flag to “1” enables an interrupt to occur. (3) An address match interrupt occurs immediately before the instruction in the address indicated by the address match interrupt register as a program is executed. Figure 2.9.4. Set-up procedure of address match interrupt Can be set to “0000016” to “FFFFF 16” b7 b0 (b23) (b16) b7 b0 Address match interrupt register 0 [Address 001216 to 001016] RMAD0 Address match interrupt register 1 [Address 001616 to 001416] RMAD1 Setting address match interrupt enable register Address match interrupt enable register [Address 000916] AIER Address match interrupt 0 enable bit 1: Interrupt enabled b7 b0 Setting address match interrupt register b7 b0 (b15) (b8) (b20) (b19) Address match interrupt 1 enable bit 1: Interrupt enabled

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Address Match Interrupt 317 Figure 2.9.5. Overview of the address match interrupt handling routine Address match interrupt routine [1] Storing registers [2] Determining the interrupt address Address match 0? Address match 0 program [3] Rewriting the stack Restoring registers REIT No Yes Address match 1? Address match 1 program No Yes Handling an error [1]Storing the contents of the registers holding the main program status to be kept. [2] Determining the interrupt address Determining which factor generated the interrupt. [3] Rewriting the stack Rewriting the return address. Explanation:

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Key-Input Interrupt 318 Figure 2.10.1. Memory map of key-input interrupt-related registers

2.10 Key-Input Interrupt

2.10.1 Overview

Key-input interrupt occurs when a falling edge is input to P00 through P07. The following is an overview of the key-input interrupt: (1) Enabling/disabling the key-input interrupt The key-input interrupt can be enabled and disabled using the key-input interrupt register. The key- input interrupt is affected by the interrupt priority level (IPL) and the interrupt enable flag (I flag). (2) Occurrence timing of the key-input interrupt With key-input interrupt acceptance enabled, pins P00 through P07, which are set to input, become key-input interrupt pins (KI0 through KI7). A key-input interrupt occurs when a falling edge is input to a key-input interrupt pin. At this moment, the level of other key-input interrupt pins must be “H ”. No interrupt occurs when the level of other key-input interrupt pins is “L”. (3) How to determine a key-input interrupt A key-input interrupt occurs when a falling edge is input to one of eight pins, but each pin has the same vector address. Therefore, read the input level of pins P0 0 through P07 in the key-input interrupt routine to determine the interrupted pin. (4) Registers related to the key-input interrupt Figure 2.10.1 shows the memory map of key-input interrupt-related registers, and Figure 2.10.2 shows key-input interrupt-related registers. Port P0 direction register (PD0) Pull-up control register 0 (PUR0) 004D 16 03E216 03FC 16 Key input interrupt control register(KUPIC)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Key-Input Interrupt 319 Figure 2.10.2. key-input interrupt-related registers Pull-up control register 0 Symbol Address When reset PUR0 03FC 16 0016 Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 PU00 P0 0 to P03 pull-up PU01 P0 4 to P07 pull-up PU02 P1 0 to P13 pull-up PU03 P1 4 to P17 pull-up PU06 P3 0 to P33 pull-up PU07 P3 4 to P35 pull-up The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port P0 direction register Symbol Address When reset PD0 03E2 16 0016 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 PD0_0 Port P0 0 direction register PD0_1 Port P0 1 direction register PD0_2 Port P0 2 direction register PD0_3 Port P0 3 direction register PD0_4 Port P0 4 direction register PD0_5 Port P0 5 direction register PD0_6 Port P0 6 direction register PD0_7 Port P0 7 direction register 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Interrupt control register (Note 2) b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Bit name Function Bit symbol W R Symbol Address When reset KUPIC 004D 16 XXXXX000 2 ILVL0 IR Interrupt priority level select bit Interrupt request bit 0 : Interrupt not requested 1 : Interrupt requested ILVL1 ILVL2 (Note1) 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Key-Input Interrupt 320 Figure 2.10.4. Example of operation of key-input interrupt

2.10.2 Operation of Key-Input Interrupt

The following is an operation of key-input interrupt. Figure 2.10.3 shows an example of a circuit that uses the key-input interrupt, Figure 2.10.4 shows an example of operation of key-input interrupt, and Figure 2.10.5 shows the setting procedure of key-input interrupt. (1) Set the direction register of the ports to be changed to key-input interrupt pins to input, and set the pull-up function. (2) Setting the key-input interrupt control register and setting the interrupt enable flag makes the interrupt-enabled state ready. (3) If a falling edge is input to either KI0 through KI7, the key-input interrupt request bit goes to “1”. Operation Figure 2.10.3. Example of circuit using the key-input interrupt P30 P31 P32 P33 P00 / KI0 P01 / KI1 P02 / KI2 P03 / KI3 P04 / KI4 P05 / KI5 P06 / KI6 P07 / KI7 VREF I/O port P30 output P31 output P32 output P33 output P04 to P07 input Key input Key OFF Key OFF Key ON Key input interrupt processing Key matrix scan /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines (1) Enter to stop mode /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines(2) Cancel stop mode /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines (3) Key scan /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines (4) Enter to stop mode Key ON

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Key-Input Interrupt 321 Figure 2.10.5. Set-up procedure of key-input interrupt Setting interrupt control register Key input interrupt control register [Address 004D16] KUPIC b7 b0 Interrupt priority level select bit 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 Interrupt request bit 0 : Interrupt not requested Setting port P10 direction register Port P0 direction register [Address 03E216] PD0 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) b7 b0 Setting pull-up control register 0 Pull-up control register 0 [Address 03FC16] PUR0 b7 b0 1 : Pulled high (P00 to P03) 1 : Pulled high (P04 to P07)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Power Control 322

2.11 Power Control

2.11.1 Overview

‘Power Control’ refers to the reduction of CPU power consumption by stopping the CPU and oscillators, or decreasing the operation clock. The following is a description of the three available power control modes: (1) Modes Power control is available in three modes. (a) Normal operation mode

High-speed mode Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the BCLK selected. Each peripheral function operates according to its assigned clock.
Medium-speed mode Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the BCLK. The CPU operates according to the BCLK selected. Each peripheral function operates according to its assigned clock.
Low-speed mode fc becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the secondary clock. Each peripheral function operates according to its assigned clock.
Low power consumption mode The main clock operating in low-speed mode is stopped. The CPU operates according to the fc clock. The fc clock is supplied by the secondary clock. The only peripheral functions that operate are those with the sub-clock selected as the count source. (b) Wait mode The CPU operation is stopped. The oscillators do not stop. (c) Stop mode All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three modes listed here, is the most effective in decreasing power consumption. Figure 2.11.1 is the state transition diagram of the above modes.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Power Control 323 Figure 2.11.1. State transition diagram of power control mode Transition of stop mode, wait mode Transition of normal mode Reset Medium-speed mode (divided-by-8 mode)Interrupt CM10 = “1” All oscillators stopped CPU operation stopped Medium-speed mode (divided-by-8 mode) BCLK : f(XIN)/8 Low-speed mode High-speed mode Main clock is oscillating Sub clock is stopped Main clock is oscillating Sub clock is stopped Main clock is stopped Sub clock is oscillating Main clock is oscillating Sub clock is oscillating Low power dissipation mode High-speed/medium- speed mode Low-speed/low power dissipation mode Normal mode Stop mode Stop mode Stop mode All oscillators stopped All oscillators stopped Wait mode Wait mode Wait mode CPU operation stopped CPU operation stopped Interrupt WAIT instruction Interrupt WAIT instruction Interrupt WAIT instruction CM10 = “1” Interrupt Interrupt CM10 = “1” BCLK : f(XIN)/2 Medium-speed mode (divided-by-2 mode) BCLK : f(XIN)/16 Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/4 Medium-speed mode (divided-by-4 mode) BCLK : f(XIN) BCLK : f(XIN)/8 Medium-speed mode (divided-by-8 mode) CM07 = “0” CM06 = “1” High-speed mode BCLK : f(XIN)/2 Medium-speed mode (divided-by-2 mode) BCLK : f(XIN)/16 Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/4 Medium-speed mode (divided-by-4 mode) BCLK : f(XIN) BCLK : f(XCIN) CM07 = “1” BCLK : f(XCIN) CM07 = “1” Main clock is oscillating Sub clock is oscillating CM07 = “0” (Note 1, 3) CM07 = “0” (Note 1) CM06 = “1” CM04 = “0” CM07 = “1” (Note 2) CM07 = “0” (Note 1) CM06 = “0” (Note 3) CM04 = “1” CM07 = “1” (Note 2) CM05 = “1” CM06 = “0” (Notes 1,3) CM06 = “1” (Notes 1, 3) Note 1: Switch clock after oscillation of main clock is sufficiently stable. Note 2: Switch clock after oscillation of sub clock is sufficiently stable. Note 3: Change CM06 after changing CM17 and CM16. Note 4: Transit in accordance with arrow. (Refer to the following for the transition of normal mode.)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Power Control 324 (2) Switching the driving capacity of the oscillation circuit Both the main clock and the secondary clock have the ability to switch the driving capacity. Reducing the driving capacity after the oscillation stabilizes allows for further reduction in power consumption. (3) Clearing stop mode and wait mode The stop mode and wait mode can be cleared by generating an interrupt request, or by resetting hardware. Set the priority level of the interrupt to be used for clearing, higher than the processor interrupt priority level (IPL), and enable the interrupt enable flag (I flag). When an interrupt clears a mode, that interrupt is processed. Table 2.11.1 shows the interrupts that can be used for clearing a stop mode and wait mode. (4) BCLK in returning from wait mode or stop mode (a) Returning from wait mode The processor immediately returns to the BCLK, which was in use before entering wait mode. (b) Returning from stop mode If operation was performed in the high speed mode or medium speed mode prior to engaging the stop mode, CM06 will change to “1” when operation shifts to the stop mode. CM17, CM16 and CM07 do not change. Accordingly, when operation is restored from the stop mode, operation starts in the 8 division mode. Also, if operation was performed in the low speed mode prior to engaging the stop mode, CM06, CM17, CM16 and CM07 do not change. When operation is restored from the stop mode, operation starts in the low speed mode. Table 2.11.1. Interrupts available for clearing stop mode and wait mode Can be used when an external clock in clock synchronous serial I/O mode is selected. Can be used when the external signal is being counted in event counter mode. Can be used in one-shot mode and one-shot sweep mode. When the MCU running in low-speed or low power dissipation mode, do not enter WAIT mode with CM02 set to 1. Note 1: Note 2: Note 3: Note 4: CM02 = 0 Possible Note 3 Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Key input interrupt A-D interrupt UART0 transmit interrupt UART0 receive interrupt UART1 transmit interrupt UART1 receive interrupt Timer A0 interrupt Timer B0 interrupt Timer B1 interrupt Timer X0 interrupt Timer X1 interrupt Timer X2 interrupt INT0 interrupt INT1 interrupt Wait modeInterrupt for clearing Possible Impossible Note 1 Note 1 Impossible Impossible Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Possible Possible Stop modeCM02 = 1(Note 4), CM07=0, CM05=0 Possible Impossible Note 1 Note 1 Impossible Impossible Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Possible Possible

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Power Control 327

2.11.2 Stop Mode Set-Up

(1) Enables the interrupt used for returning from stop mode. (2) Sets the interrupt enable flag (I flag) to “1”. (3) Clearing the protection and setting every-clock stop bit to “1” stops oscillation and causes the processor to go into stop mode. Operation Settings and operation for entering stop mode are described here. Figure 2.11.5. Example of stop mode set-up All clocks off (stop mode) b7 b0 (3) Canceling protect Protect register [Address 000A16] PRCR1 Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) 1 : Write-enabled (3) All clocks off (stop mode) b7 b0 System clock control register [Address 000716] CM10000 Reserved bit Must be set to “0” All clock stop control bit 1 : All clocks off (stop mode) Interrupt control register KUPIC [Address 004D 16] ADIC [Address 004E 16] SiTIC(i=0, 1) [Address 005116, 005316] SiRIC(i=0, 1) [Address 005216, 005416] TAiIC(i=0) [Address 0055 16] TXiIC(i=0 to 2) [Address 005616 to 005816] TBiIC(i=0, 1) [Address 005A16, 005B16] (1) Setting interrupt to cancel stop mode Make sure that the interrupt priority level of the interrupt which is used to cancel the wait mode is higher than the processor interrupt priority(IPL) of the routine where the WAIT instruction is executed. Interrupt priority level select bit b7 b0 INTiIC(i=0, 1) [Address 005D16, 005E16] Make sure that the interrupt priority level of the interrupt which is used to cancel the wait mode is higher than the processor interrupt priority(IPL) of the routine where the WAIT instruction is executed. Interrupt priority level select bit b7 b0 Reserved bit Must be set to “0” As this register becomes setting mentioned above when operating with XCIN (count source of BCLK is XCIN), the user does not need to set it again. When operating with XIN, set port Xc select bit to “1” before setting system clock select bit to “1”. The both bits cannot be set at the same time. System clock control register [Address 000616] CM0 (3) Setting operation clock after returning from stop mode Main clock (XIN-XOUT ) stop bit On b7 b0 System clock select bit XIN, XOUT As this register becomes setting mentioned above when operating with X IN (count source of BCLK is XIN), the user does not need to set it again. System clock control register 0 [Address 000616] CM0 Port XC select bit XCIN-XCOUT generation b7 b0 System clock select bit XCIN, XCOUT 1 1 (When operating with XCIN after returning)(When operating with XIN after returning) (2) Interrupt enable flag (I flag) “1” As this register becomes setting mentioned above when operating with XCIN (count source of BCLK is XCIN), the user does not need to set it again. When operating with XIN, set port Xc select bit to “1” before setting system clock select bit to “1”. The both bits cannot be set at the same time.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Power Control 328

2.11.3 Wait Mode Set-Up

Figure 2.11.6. Example of wait mode set-up Settings and operation for entering wait mode are described here. (1) Enables the interrupt used for returning from wait mode. (2) Sets the interrupt enable flag (I flag) to “1”. (3) Clears the protection and changes the content of the system clock control register. (4) Executes the WAIT instruction. Operation Wait mode (3) Canceling protect b7 b0 Protect register [Address 000A16] PRCR1 Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) 1 : Write-enabled (4) WAIT instruction (3) Control of CPU clock Note 1: When switching the system clock, it is necessary to wait for the oscillation to stabilize. Note 2: Set the WAIT peripheral function clock stop bit to “0” when the system clock select bit is “1”. b7 b0 WAIT peripheral function clock stop bit(Note 2) 0 : Do not stop f1, f8, f32 in wait mode 1 : Stop f1, f8, f32 in wait mode Port XC select bit 0 : I/O port 1 : X CIN-XCOUT generation Main clock (XIN-XOUT ) stop bit 0 : On 1 : Off Main clock division select bit 0 0 : CM16 and CM17 valid 1 : Division by 8 mode System clock select bit (Note 1, Note 2) 0 : X IN, XOUT 1 : XCIN, XCOUT System clock control register 0 [Address 000616] CM0 b7 b0 System clock control register 1 [Address 000716] CM10000 Reserved bit Must be set to “0” Main clock division select bit 0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode b7 b6 Interrupt control register KUPIC [Address 004D 16] ADIC [Address 004E 16] SiTIC(i=0, 1) [Address 005116, 005316] SiRIC(i=0, 1) [Address 005216, 005416] TAiIC(i=0) [Address 0055 16] TXiIC(i=0 to 2) [Address 005616 to 005816] TBiIC(i=0, 1) [Address 005A16, 005B16] (1) Setting interrupt to cancel wait mode Make sure that the interrupt priority level of the interrupt which is used to cancel the wait mode is higher than the processor interrupt priority (IPL) of the routine where the WAIT instruction is executed. Interrupt priority level select bit b7 b0 INTiIC(i=0 , 1) [Address 005D16, 005E16] Make sure that the interrupt priority level of the interrupt which is used to cancel the wait mode is higher than the processor interrupt priority (IPL) of the routine where the WAIT instruction is executed. Interrupt priority level select bit b7 b0 Reserved bit Must be set to “0” (2) Interrupt enable flag (I flag) “1”

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Power Control 329 (1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock oscillation is stabilized. (2) When switching to either wait mode or stop mode, instructions occupying four bytes either from the WAIT instruction or from the instruction that sets the every-clock stop bit to “1” within the instruction queue are prefetched and then the program stops. So put at least four NOPs in succession either to the WAIT instruction or to the instruction that sets the every-clock stop bit to “1”. (3) Suggestions to reduce power consumption

Ports The processor retains the state of each programmable I/O port even when it goes to wait mode or to stop mode. A current flows in active I/O ports. A pass current flows in input ports that float. When entering wait mode or stop mode, set non-used ports to input and stabilize the potential. (a) A-D converter A current always flows in the V REF pin. When entering wait mode or stop mode, set the Vref connection bit to “0” so that no current flows into the VREF pin. (b) Stopping peripheral functions In wait mode, stop non-used wait peripheral functions using the peripheral function clock stop bit. However, peripheral function clock f C32 does not stop so that the pe- ripherals using fC32 do not contribute to the power saving. When the MCU running in low-speed or low power dissipation mode, do not enter WAIT mode with this bit set to “1”. (c) Switching the oscillation-driving capacity Set the driving capacity to “LOW ” when oscillation is stable. (d) External clock When using an external clock input for the CPU clock, set the main clock stop bit to “1”. Setting the main clock stop bit to “1” causes the X OUT pin not to operate and the power consumption goes down (when using an external clock input, the clock signal is input regardless of the content of the main clock stop bit).

2.11.4 Precautions in Power Control

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Ports 330

2.12 Programmable I/O Ports

2.12.1 Overview

Fourty-three programmable I/O ports. I/O pins also serve as I/O pins for built-in peripheral functions. Each port has a direction register that defines the I/O direction and also has a port register for I/O data. In addition, each port has a pull-up control register that defines pull-up in terms of 4 bits. Port P1 can be set to N-channel output transistor drive capacity. The following is an overview of the programmable I/O ports: (1) Writing to a port register With the direction register set to output, the level of the written values from each relevant pin is output by writing to a port register. The output level conforms to CMOS output. Writing to the port register, with the direction register set to input, inputs a value to the port register, but nothing is output to the relevant pins. The output level remains floating. (2) Reading a port register With the direction register set to output, reading a port register takes out the content of the port regis- ter, not the content of the pin. With the direction register set to input, reading the port register takes out the content of the pin. (3) Effect of the protection register Data written to the direction register of P4 is affected by the protection register. The direction register of P4 cannot be easily rewritten. (4) Setting pull-up The pull-up control bit allows setting of the pull-up, in terms of 4 bits, either in use or not in use. For the four bits chosen, pull-up is effective only in the ports whose direction register is set to input. Pull-up is not effective in ports whose direction register is set to output. Do not set pull-up of corresponding pin when X CIN/XCOUT is set or a port is used as A-D input. (5) Drive capacity control The drive capacity of the N channel output transistor on P1 can be set between “LOW ” and “HIGH ” in units of 1 bit. One bit corresponds to one pin.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Ports 331 (6) I/O functions of built-in peripheral devices Table 2.12.1 shows relation between ports and I/O functions of built-in peripheral devices. Table 2.12.1. Relation between ports and I/O functions of built-in peripheral devices (7) Examples of working on non-used pins Table 2.12.2 contains examples of working on non-used pins. There are shown here for mere ex- amples. In practical use, make suitable changes and perform sufficient evaluation in compliance with you application. Table 2.12.2. Examples of working on unused pins in single-chip mode Port Internal peripheral device I/O pins key-input interrupt function input pins I/O pin for serial I/O communication/Timer A input pinP40 P42 Serial I/O input pin P43, P44 Input pins for external interrupt/Timer X I/O pins P45 Timer X I/O pin P50 to P54 I/O pins for serial I/O communication/A-D converter input pins P6 A-D converter input pins P70, P71 Timer B input pins Timer A output pinP41 Pin name Connection Ports P0, P1, P3 to P7 XOUT (Note 2) After setting for input mode, connect every pin to VSS or VCC via a resistor; or after setting for output mode, leave these pins open. (Note 1) Open AV SS , VREF , BYTE Connect to V SS If setting these pins in output mode and opening them, ports are in input mode until switched into output mode by use of software after reset. Thus the voltage levels of the pins become unstable, and there can be instances in which the power source current increases while the ports are in input mode. In view of an instance in which the contents of the direction registers change due to a runaway generated by noise or other causes, setting the contents of the direction registers periodically by use of software increases program reliability. When an external clock is input to the X IN pin. Note 1: Note 2: AV CC Connect to VCC

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Ports 333 Figure 2.12.2. Programmable I/O ports-related registers (1) Port Pi direction register (Note 1) Symbol Address When reset PDi (i = 0 to 7) 03E216, 03E316, 03E716, 03EA16, 0016 03EB 16, 03EE16, 03EF16 0016 Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 PDi_0 Port Pi 0 direction register PDi_1 Port Pi 1 direction register PDi_2 Port Pi 2 direction register PDi_3 Port Pi 3 direction register PDi_4 Port Pi 4 direction register PDi_5 Port Pi 5 direction register PDi_6 Port Pi 6 direction register PDi_7 Port Pi 7 direction register 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) (i = 0 to 7 except 2) Note 1: Set bit 2 of protect register (address 000A16) to “1” before rewriting to the port P4 direction register. Note 2: Nothing is assigned in direction register of P36, P37, P46, P47, P55 to p57, P72 to P77. These bits can either be set nor reset. When read, its contents are indeterminate. /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines Port Pi register Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 Pi_0 Port Pi 0 register Pi_1 Port Pi 1 register Pi_2 Port Pi 2 register Pi_3 Port Pi 3 register Pi_4 Port Pi 4 register Pi_5 Port Pi 5 register Pi_6 Port Pi 6 register Pi_7 Port Pi 7 register Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : “L” level data 1 : “H ” level data (i = 0 to 7 except 2) /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines Symbol Address When reset Pi (i = 0 to 7) 03E016, 03E116, 03E516, 03E816, Indeterminate 03E916, 03EC16, 03ED16 Indeterminate Note: Nothing is assigned in direction register of P36, P37, P46, P47, P55 to p57, P72 to P77. This bit can either be set nor reset. When read, its content is indeterminate.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Ports 334 Figure 2.12.3. Programmable I/O ports-related registers (2) Pull-up control register 0 Symbol Address When reset PUR0 03FC 16 0016 Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 PU00 P0 0 to P03 pull-up PU01 P0 4 to P07 pull-up PU02 P1 0 to P13 pull-up PU03 P1 4 to P17 pull-up PU06 P3 0 to P33 pull-up PU07 P3 4 to P35 pull-up The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines Pull-up control register 1 Symbol Address When reset PUR1 03FD 16 0016 Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 PU10 P4 0 to P43 pull-up PU11 P4 4 to P47 pull-up PU12 P5 0 to P53 pull-up PU13 P5 4 pull-up PU14 P6 0 to P63 pull-up PU15 P6 4 to P67 pull-up PU16 P7 0 to P71 pull-up The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Port P1 drive capacity control register Symbol Address When reset DRR 03FE 16 0016 Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 DRR0 Port P10 drive capacuty DRR1 Port P11 drive capacuty DRR2 Port P12 drive capacuty DRR3 Port P13 drive capacuty DRR4 Port P14 drive capacuty DRR5 Port P15 drive capacuty DRR6 Port P16 drive capacuty DRR7 Port P17 drive capacuty Set P1 N-channel output transistor drive capacity 0 : LOW 1 : HIGH /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines

Examples of Peripheral functions Applications

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Applications 336 This chapter presents applications in which peripheral functions built in the M16C/20 are used. They are shown here as examples. In practical use, make suitable changes and perform sufficient evaluation. For basic use, see Chapter 2 How to Use Peripheral Functions. Here follows the list of applications that appear in this chapter.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Applications 337 [MEMO]

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Applications 338

3.1 Long-Period Timers

Figure 3.1.1. Operation timing of long-period timers In this process, Timer X0 and Timer X1 are connected to make a 16-bit timer with a 16-bit Use the following peripheral functions:

Timer mode of timer X
Event counter mode of timer X (1) Set timer X0 to timer mode, and set timer X1 to event counter mode. (2) Perform a count on count source f 1 using timer X0 to count for 1 ms, and perform a count on timer X0 using timer X1 to count for 1 second. (3) Connect a 10-MHz oscillator to XIN. (1) Setting the count start flag to “1” causes the counter to begin counting. The counter of timer X0 performs a down count on count source f1. (2) If the counter of timer X0 underflows, the counter reloads the content of the reload register and continues counting. At this time, the timer X0 interrupt request bit goes to “1”. The counter of timer X1 performs a down count on underflows in timer X0. (3) If the counter of timer X1 underflows, the counter reloads the content of the reload register and continues counting. At this time, the timer X1 interrupt request bit goes to “1”. FFFF 16 l 000016 Timer X0 counter content (hex) l = reload register content Timer X1 count start flag “1” “0” Timer X1 interrupt request bit “1” “0” Timer X0 interrupt request bit “1” “0” Timer X0 count start flag “1” “0” Timer X1 counter content (hex)000016 n FFFF 16 Time (1) Start count Start count. Time n = reload register content Set to “1” by software Set to “1” by software Cleard “0” by software Cleared to “0” when interrupt request is accepted, or cleared by software (2) Timer X0 underflow (3) Timer X1 underflow

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Applications 339 Figure 3.1.2. Connection diagram of long-period timers f32 fC32 Timer X0 Timer X1 Timer X0 interrupt request bit Timer X1 interrupt request bit Used for timer mode Used for event counter mode

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Applications 340 Figure 3.1.3. Set-up procedure of long-period timers (1) Continued to the next page Setting timer X0 Selecting timer mode and functions Pulse output function select bit 0 : Pulse is not output (TX0INOUT pin is a normal port pin) Timer X0 mode register [Address 039716] TX0MR Gate function select bit 0 0 : Gate function not available (TX0INOUT pin is a normal port pin) b4 b3 Selection of timer mode b7 b0 0000 0 0 (Must always be “0” in timer mode) Count source select bit 0 0 : f1 b7 b6 000 Setting divide ratio b7 b0 (b15) (b8) b7 b0 Timer X0 register [Address 038916, 038816] TX02716 0F16 Selecting event counter mode and each function Setting timer X1 Pulse output function select bit] 0 : Pulse is not output (TX1INOUT pin is a normal port pin) Timer X1 mode register [Address 039816] TX1MR 0 (Must always be “0” in event counter mode) Selection of event counter mode 0 (Must always be “0” in event counter mode) Count operation type select bit 0 : Reload type 0 (Must always be “0” in event counter mode) Count polarity select bit b7 b0 010000 0 0 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Applications 341 Figure 3.1.4. Set-up procedure of long-period timers (2) Start counting Continued from the previous page b7 b0 Trigger select register [Address 038316] TRGSR Timer X1 event/trigger select bit 1 0 : TX0 overflow is selected b5 b4 0 1 Setting trigger select register Setting divide ratio b7 b0 (b15) (b8) b7 b0 Timer X1 register [Address 038B16, 038A16] TX10316 E716 Setting count start flag Count start flag [Address 038016] TABSR Timer X0 count start flag 1 : Starts counting Timer X1 count start flag 1 : Starts counting b7 b0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Applications 342 In this process, Timer X0 and A1 are used to generate variable-period, variable-duty PWM out- Use the following peripheral functions:

Timer mode of timer X
One-shot timer mode of timer X (1) Set timer X0 in timer mode, and set timer X1 in one-shot timer mode with pulse-output function. (2) Set 1 ms, the PWM period, to timer X0. Set 500 µs, the width of PWM “H ” pulse, to timer X1. Both timer X0 and timer X1 use f1 for the count source. (3) Connect a 10-MHz oscillator to XIN. (1) Setting the count start flag to “1” causes the counter of timer X0 to begin counting. The counter of timer X0 performs a down count on count source f1. (2) If the counter of timer X0 underflows, the counter reloads the content of the reload register and continues counting. At this time, the timer X0 interrupt request bit gose to “1”. (3) An underflow in timer X0 triggers the counter of timer X1 and causes it to begin counting. When the counter of timer X1 begins counting, the output level of the TX1INOUT pin gose to “H ”. (4) As soon as the count of the counter of timer X1 becomes “000016”, the output level of TX1 INOUT pin gose to “L”, and the counter reloads the content of the reload register and stops counting. At the same time, the timer X1 interrupt request bit gose to “1”.

3.2 Variable-Period Variable-Duty PWM Output

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Applications 344 Figure 3.2.3. Set-up procedure of variable-period variable-duty PWM output (1) Continued to the next page Setting timer X0 Pulse output function select bit 0 : Pulse is not output (TX0INOUT pin is a normal port pin) Selecting timer mode and functions Timer X0 mode register [Address 039716 ] TX0MR Gate function select bit 0 0 : Gate function not available (TX0INOUT pin is a normal port pin) b4 b3 Selection of timer mode b7 b0 0000 0 0 (Must always be “0” in timer mode) Count source select bit 0 0 : f1 b7 b6 00 0 Setting divide ratio b7 b0 (b15) (b8) b7 b0 Timer X0 register [Address 038916, 038816] TX02716 0F16 Setting timer X1 Pulse output function select bit (Note) 1 : Pulse is output Selecting one-shot timer mode and functions Timer X1 mode register [Address 039816 ] TX1MR External trigger select bit (Invalid when choosing timer's overflow as trigger) Selection of one-shot timer mode b7 b0 1001 1 0 (Must always be “0” in one-shot timer mode) Trigger select bit 1 : Selected by event/trigger select register 0 0 0 Count source select bit 0 0 : f1 b7 b6 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Note: Set the corresponding port direction register to “1” (output mode).

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Applications 345 Figure 3.2.4. Set-up procedure of variable-period variable-duty PWM output (2) Start counting Continued from the previous page b7 b0 Trigger select register [Address 038316] TRGSR Timer X1 event/trigger select bit 1 0 : TX0 overflow is selected b5 b4 0 1 Setting trigger select register Setting one-shot timer's time b7 b0 (b15) (b8) b7 b0 Timer X1 register [Address 038B16, 038A16] TX11316 8816 Setting count start flag Count start flag [Address 038016] TABSR Timer X0 count start flag 1 : Starts counting Timer X1 count start flag 1 : Starts counting b7 b0 1 1

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Applications 346 The following are steps of outputting a pulse only once after a specified elapse since an external Use the following peripheral function:

One-shot timer mode of timer X (1) Set timer X0 in one-shot timer mode, and set timer X1 in one-shot timer mode with pulse- output function. (2) Set 1 ms, an interval before a pulse is output, in timer X0; and set 50 µs, a pulse width, in timer X1. Both timer X0 and timer X1 use f 1 for the count source. (3) Connect a 10-MHz oscillator to XIN. (1) Setting the trigger select bit to “1” and setting the count start flag to “1” enables the counter of timer X0 to count. (2) If an effective edge, selected by use of the external trigger select bit, is input to the TX0INOUT pin, the counter begins a down count. The counter of timer X0 performs a down count on count source f (3) As soon as the counter of timer X0 becomes “000016”, the counter reloads the content of the reload register and stops counting. At this time, the timer X0 interrupt request bit gose to “1”. (4) An underflow in timer X0 triggers the counter of timer X1 and causes it to begin counting. When timer X1 begins counting, the output level of the TX1INOUT pin gose to “H ”. (5) As soon as the counter of timer X1 becomes “000016”, the output level of the TX1INOUT pin gose to “L”, the counter reloads the content of the reload register, and stops counting. At this time, timer X1 interrupt request bit gose to “1”.

3.3 Delayed One-Shot Output

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Applications 348 Figure 3.3.3. Set-up procedure of delayed one-shot output (1) Continued to the next page Setting timer X0 Setting trigger select register (Select TX0INOUT pin to input TX0 trigger) b7 b0 Trigger select register [Address 038316] TRGSR Timer X0 event/trigger select bit 0 0 : Input on TX0INOUT is selected (Note) b3 b2 Note: Set the corresponding port direction register to “0” (input mode). Setting delay time b7 b0 (b15) (b8) b7 b0 Timer X0 register [Address 038916, 038816] TX02716 1016 Pulse output function select bit 0 : Pulse is not output Selecting one-shot timer mode and functions Timer X0 mode register [Address 039716] TX0MR External trigger select bit 0 : Falling edge of TX0INOUT pin's input signal Selection of one-shot timer mode b7 b0 1000 1 0 (Must always be “0” in one-shot timer mode) Count source select bit 0 0 : f1 b7 b6 Trigger select bit 1 : Selected by event/trigger select register 000 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 0 0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Applications 349 Figure 3.3.4. Set-up procedure of delayed one-shot output (2) Start counting Continued from the previous page Setting one-shot timer's time b7 b0 (b15) (b8) b7 b0 Timer X1 register [Address 038B16, 038A16] TX10116 3216 Setting timer X1 Setting trigger select register (Set timer X0 to trigger timer X1) b7 b0 Trigger select register [Address 038316] TRGSR0 1 Timer X1 event/trigger select bit 1 0 : TX0 overflow is selected b5 b4 Selecting one-shot timer mode and functions Pulse output function select bit (Note) 1 : Pulse is output (TX1INOUT pin is pulse output pin) Timer X1 mode register [Address 039816] TX1MR External trigger select bit Invalid when choosing timer's overflow Selection of one-shot timer mode b7 b0 1001 1 0 (Must always be “0” in one-shot timer mode) Count source select bit 0 0 : f1 b7 b6 Trigger select bit 1 : Selected by event/trigger select register 000 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Note: Set the corresponding port direction register to “1” (output mode). Setting count start flag Count start flag [Address 038016] TABSR Timer X0 count start flag 1 : Starts counting Timer X1 count start flag 1 : Starts counting b7 b0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Applications 350

3.4 Buzzer Output

Figure 3.4.1. Operation timing of buzzer output The timer mode is used to make the buzzer ring. Figure 3.4.1 shows the operation timing, and Figure 3.4.2 shows the set-up procedure. Use the following peripheral function:

The pulse-outputting function in timer mode of timer X. (1) Sound a 2-kHz buzz beep by use of timer X0. (2) Effect pull-up in the relevant port by use of a pull-up resistor. When the buzzer is off, set the port high-impedance, and stabilize the potential resulting from pulling up. (3) Connect a 10-MHz oscillator to X IN. (1) The microcomputer begins performing a count on timer X0. Timer X0 has disabled interrupts. (2) P4 3 is TX0INOUT pin. Setting the port P43 direction register to “1” (output mode) and outputs 2- kHz pulses. (3) The microcomputer stops outputting pulses by setting the port P43 direction register to “0” (input mode). P43 goes to an input pin, and the output from the pin becomes high-impedance. “0” “1” “0” “1” Timer X0 overflow timing Count start flag Port P43 direction register P43 output “0” “1” High-impedance High-impedance (1) Start count (2) Buzzer output ON (3) Buzzer output OFF

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Applications 351 Initialization of port P4 direction register b7 b0 Port P43 direction register 0 : Input mode

0 Port P4 direction register [Address 03EA16]

Enables writing to port P4 direction register 1 : Write-enabled

1 Protect register [Address 000A16]

Initialization of timer X0 b7 b0 Selection of timer mode Pulse output function select bit 1 : Pulse is output Gate function select bit b4 b3 0 0 : Gate function not available 0 (Must always be “0” in timer mode) Count source select bit b7 b6 0 0 : f1 Timer X0 mode register TX0MR [Address 039716 ]00 01 0000 Timer X0 register TX0 [Address 038916, 038816] b15 b8 b7 b0

0016 F916

Count start flag [Address 038016] TABSR b7 b0 Timer X0 count start flag 1 : Starts counting Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Buzzer ON b7 b0 Port P43 direction register 1 : Output mode

1 Port P4 direction register [Address 03EA16]

Enables writing to port P4 direction register 1 : Write-enabled Port P43 direction register 0 : Input mode Enables writing to port P4 direction register 1 : Write-enabled Figure 3.4.2. Set-up procedure of buzzer output

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Applications 352

3.5 Solution for External Interrupt Pins Shortage

The following are solution for external interrupt pins shortage. Figure 3.5.1 shows the set-up procedure. Use the following peripheral function:

Event counter mode of timer X (1) Inputting a falling edge to the TX0 INOUT pin generates a timer X0 interrupt. (1) Set timer X0 to event counter mode, set timer to “0”, and set interrupt priority levels in timer X0. (2) Inputting a falling edge to the TX0INOUT pin generates a timer X0 interrupt.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Applications 353 Figure 3.5.1. Set-up procedure of solution for a shortage of external interrupt pins Setting interrupt priority levels in timer X0 b7 b0 Timer X0 interrupt control register [Address 005616] TX0IC Interrupt control level (set a value 1 to 7) Setting interrupt enable flag (I flag) Initialization of timer X0 b7 b0 Selection of event counter mode Pulse output function select bit 0 : Pulse is not output (TX0INOUT pin is a normal port pin) Count polarity select bit 0 : Counts external signal's falling edge 0 (Must always be “0” in event counter mode) 0 (Must always be “0” in event counter mode) Count operation type select bit 0 : Reload type 0 (Must always be “0” in event counter mode) Timer X0 mode register TX0MR [Address 039716 ]00 00 1000 Trigger select register [Address 038316] TRGSR b7 b0 b7 b0 Timer X0 count start flag 1 : Starts counting Count start flag [Address 038016] TABSR1 Timer X0 register TX0 [Address 038916, 038816] b15 b8 b7 b0 0016 0016 b7 b0 Timer X0 event/trigger select bit 0 0 : Input on TX0INOUT is selected b3 b2 Initialization of port P4 direction register b7 b0 Port P43 direction register 0 : Input mode Enables writing to port P4 direction register 1 : Write-enabled

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Controlling Power Applications 354

3.6 Controlling Power Using Stop Mode

The following are steps for controlling power using stop mode. Figure 3.6.1 shows the operation procedure. Use the following peripheral functions:

Key-input interrupts
Stop mode
Pull-up function (1) Use P30 through P33 for the scan output pins of a key matrix. Use the input pins (KI0 through KI7) of the key-input interrupt function for the key-input reading pins. The pull-up function is also used. (2) If a key-input interrupt request occurs, clear the stop mode and read a key. (1) Enable a key-input interrupt and set the pull-up function to pins KI0 through KI7. Change the output of P30 through P33 to “L” and enter stop mode. (2) If a key is pressed, “L” is input to one of pins KI0 through KI7 to clear stop mode. A key-input interrupt occurs to execute the key-input interrupt handling routine. (3) Sequentially set P30 through P33 to “L” to determine which key was pressed. (4) When the process to determine the key pressed is completed, change the output from P30 through P33 to “L” again and enter stop mode. Figure 3.6.1. Operation timing of controlling power using stop mode Overview Specifications Operation P30 output P31 output P32 output P33 output P00 to P07 input Key input Key OFF Key OFF Key ON Stop mode Key input interrupt processing CPU clock Stop mode Key matrix scan /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines (1) Shift to stop mode /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines (2) Cancel a stop mode /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines (3) Key scan /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines (4) Shift to stop mode Key ON

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Controlling Power Applications 355 Figure 3.6.2. Example of circuit of controling power using stop mode P30 P31 P32 P33 P00 / KI0 P01 / KI1 P02 / KI2 P03 / KI3 P04 / KI4 P05 / KI5 P06 / KI6 P07 / KI7 VREF I/O port

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Controlling Power Applications 356 Figure 3.6.3. Set-up procedure of controlling power using stop mode (1) Canceling protect Protect register [Address 000A16] PRCR b7 b0 Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) 1 : Write-enabled Main NOP instruction X 5 Key input interrupt request generation Setting interrupt except stop mode cancel Interrupt control register KUPIC [Address 004D16] ADIC [Address 004E 16] SiTIC(i=0, 1) [Address 005116, 005316] SiRIC(i=0, 1) [Address 005216, 005416] TAiIC(i=0) [Address 0055 16] TXiIC(i=0 to 2) [Address 005616 to 005816] TBiIC(i=0, 1) [Address 005A16, 005B16] Interrupt priority level select bit 0 0 0 : Interrupt disabled b7 b0 0 0 0 Interrupt priority level select bit 0 0 0 : Interrupt disabled b7 b0 0 0 0INTiIC(i=0, 1) [Address 005D16, 005E16]0 Always set to “0” All clocks off (stop mode) System clock control register 1 [Address 000716] CM1 b7 b0 All clock stop control bit 1 : All clocks off (stop mode) 10000 Reserved bit Always set to “0” Setting operation clock after returning from stop mode System clock control register 0 [Address 000616] CM0 XCIN-XCOUT generation Port XC select bit b7 b0 System clock select bit XCIN, XCOUT As this register becomes setting mentioned above when operating with XCIN (count source of BCLK is XCIN), the user does not need to set it again. When operating with XIN, set port Xc select bit to “1” before setting system clock select bit to “1”. The both bits cannot be set at the same time. 1 1 (When operating with XCIN after returning) System clock control register 0 [Address 000616] CM0 On Main clock (XIN-XOUT ) stop bit b7 b0 System clock select bit XIN, XOUT As this register becomes setting mentioned above when operating with X IN (count source of BCLK is XIN), the user does not need to set it again. (When operating with XIN after returning) Interrupt enable flag (I flag) “1” Initial condition b7 b0 Pull-up control register 0 [Address 03FC16] PUR0 P00 to P03 pulled high Port P3 register [Address 03E516] b7 b0 0 0 0 0 Key scan data Interrupt enable level (IPL) = 0 Interrupt enable flag (I) =0 Key input interrupt control register [Address 004D16] KUPIC Interrupt priority level select bit Set higher value than the present IPL b7 b0 1 0 0 Port P0 direction register [Address 03E216] PD0 Key scan input port b7 b0 0 0 0 0 0 0 0 0 P04 to P07 pulled high Port P3 direction register [Address 03E716] PD3 Key scan output port b7 b0 1 1 1 1

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Controlling Power Applications 357 Figure 3.6.4. Set-up procedure of controlling power using stop mode (2) Key-input interrupt Store the registers Restore the registers REIT instruction Decision of key-input data Key matrix scan Port P3 register [Address 03E516] Key scan data 1110, 1101, 1011, 0111 b7 b0 Key scan data Port P3 register [Address 03E5416] b7 b0 0 0 0 0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Controlling Power Applications 358

3.7 Controling Power Using Wait Mode

The following are steps for controling power using wait mode. Figure 3.7.1 shows the operation Use the following peripheral functions:

Timer mode of timer B
Wait mode A flag named “F-WIT” is used in the set-up procedure. The purpose of this flag is to decide whether or not to clear wait mode. If F_WIT = “1” in the main program, the wait mode is entered; if F_WIT = “0”, the wait mode is cleared. (1) Connect a 32.768-kHz oscillator to X CIN to serve as the timer count source. As interrupts occur every one second, which is a count the timer reaches, the controller returns from wait mode and count the clock using a program. (2) Clear wait mode if a INT0 interrupt request occurs. (1) Switch the system clock from XIN to XCIN to get low-speed mode. (2) Stop XIN and enter wait mode. In this instance, enable the timer B0 interrupt and the INT0 interrupt. (3) When a timer B0 interrupt request occurs (at 1-second intervals), start supplying the BCLK from XCIN. At this time, count the clock within the routine that handles the timer B0 interrupts and enter wait mode again. (4) If a INT0 interrupt occurs, start supplying the BCLK from XCIN. Start the XIN oscillation within the INT0 interrupt, and switch the system clock to XIN. Overview Specifications Operation Figure 3.7.1. Operation timing of controling power using wait mode Timer B0 interrupt processing Timer B0 overflow XCIN XOUT BCLK INT0 (1) Shift to low-speed mode (2) Stop XIN (3) Timer B0 interrupt (4) INT0 interrupt “H ” “L” High-speed Low-speed Low-speed Low-speed Low-speed High-speed

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Controlling Power Applications 359 Figure 3.7.2. Set-up procedure of controlling power using wait mode (1) Main Setting interrupt except clearing wait mode Interrupt control register KUPIC [Address 004D 16] ADIC [Address 004E 16] SiTIC (i = 0, 1) [Address 005116, 005316] SiRIC (i = 0, 1) [Address 005216, 005416] TAiIC (i = 0) [Address 005516] TXiIC (i = 0 to 2) [Address 005616 to 005816] TBiIC (i = 0, 1) [Address 005A16, 005B16] b7 b0 0 0 0 Interrupt priority level select bit b2 b1 b0 0 0 0 : Interrupt disabled Initial condition System clock select bit 0 : XIN-XOUT b7 b0 00 1 System clock control register 0 [Address 000616] CM0 Port Xc select bit 1 : Functions as XCIN-XCOUT oscillator Main clock (XIN-XOUT ) stop bit 0 : Oscillating Main clock divide ratio select bit 0 XCIN-XCOUT drive capacity select bit Continued to the next page Interrupt priority level (IPL) = 0 Interrupt enable flag (I) = 0 b15 b8 b7 b0

0316 FF16 Timer B0 register [Address 039116, 039016]

1 Clock prescaler reset flag [Address 038116]

Count start flag [Address 038016] TABSR 1 TB0 start counting b7 b0 1 0 0Timer B0 interrupt control register [Address 005A16] TB0IC TB0 interrupt priority level b7 b0 Timer B0 mode register [Address 039B16] TB0MR 10 01 Operation mode select bit b1 b0 0 0 : Timer mode Count source select bit b7 b6 1 1 : fC32 (f(XCIN) divided by 32) b7 b0 1 0 0INT0 interrupt control register [Address 005D16] INT0IC INT0 interrupt priority level WAIT peripheral function clock stop bit 0 : Do not stop peripheral function clock in wait mode

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Controlling Power Applications 360 Figure 3.7.3. Set-up procedure of controlling power using wait mode (2) Canceling protect Protect register [Address 000A16] PRCR b7 b0 Enables writing to system clock control registers 0 and 1 (address 000616 and 000716) 1 : write-enabled Switching system clock b7 b0 System clock select bit 1 : XCIN-XCOUT

1 System clock control register 0 [Address 000616]

Main clock (XIN-XOUT ) stop bit 1 : Off [F_WIT] = 1 WAIT instruction Switching system clock b7 b0 System clock select bit 0 : XIN-XOUT

0 System clock control register 0 [Address 000616]

Main clock (XIN-XOUT ) stop bit 0 : On Starting main clock oscillator [F_WIT] : 1 = TB0 interrupt request generated INT0 interrupt request generated NOP instruction X 5 Continued from the previous page Interrupt enable flag (I flag) “1”

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Controlling Power Applications 361 Figure 3.7.4. Set-up procedure of controlling power using wait mode (3) Store the registers Restore the registers REIT instruction [F_WIT] = 0 INT0 interrupt Store the registers Restore the registers REIT instruction Counting clock Timer B0 interrupt

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Controlling Power Applications 362 [MEMO]

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt 364

Maskable interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level.
Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level. Figure 4.1.1. Classification of interrupts Interrupt Software Hardware Special Peripheral I/O (Note) Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Reset DBC Watchdog timer Single step Address matched Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.

4.1 Overview of Interrupt

4.1.1 Type of Interrupts

Figure 4.1.1 lists the types of interrupts.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt 365

4.1.2 Software Interrupts

A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts.

Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction.
Overflow interrupt An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to “1”. The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
BRK interrupt A BRK interrupt occurs when executing the BRK instruction.
INT interrupt An INT interrupt occurs when assiging one of software interrupt numbers 0 through 63 and executing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/O interrupt does. The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is involved. So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt re- quest. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt 366

4.1.3 Hardware Interrupts

Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts. (1) Special interrupts Special interrupts are non-maskable interrupts.

Reset Reset occurs if an “L” is input to the RESET pin.
DBC interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances.
Watchdog timer interrupt Generated by the watchdog timer.
Single-step interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to “1”. If an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. For address match interrupt, see 2.9 Address match Interrupt. (2) Peripheral I/O interrupts A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func- tions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INI instruction uses. Peripheral I/O interrupts are maskable interrupts.
Key-input interrupt ___ A key-input interrupt occurs if an “L” is input to the KI pin.
A-D conversion interrupt This is an interrupt that the A-D converter generates.
UART0 and UART1 transmission interrupt These are interrupts that the serial I/O transmission generates.
UART0 and UART1 reception interrupt These are interrupts that the serial I/O reception generates.
Timer A0 interrupt This is an interrupt that timer A generates.
Timer B0 interrupt and timer B1 interrupt These are interrupts that timer B generates.
Timer X0 interrupt through timer X2 interrupt
INT0 interrupt and INT1 interrupt An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt 367 Interrupt source Vector table addresses Remarks Address (L) to address (H) Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction Overflow FFFE0 16 to FFFE316 Interrupt on INTO instruction BRK instruction FFFE4 16 to FFFE716 If the vector contains FF16, program execution starts from the address shown by the vector in the variable vector table Address match FFFE8 16 to FFFEB16 There is an address-matching interrupt enable bit Single step (Note) FFFEC 16 to FFFEF16 Do not use Watchdog timer FFFF0 16 to FFFF316 DBC (Note) FFFF4 16 to FFFF716 Do not use FFFF8 16 to FFFFB16 Reset FFFFC 16 to FFFFF16 Note: Interrupts used for debugging purposes only.

4.1.4 Interrupts and Interrupt Vector Tables

If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting.

Fixed vector tables The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFDC 16 to FFFFF16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table 4.1.1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. Table 4.1.1. Interrupts assigned to the fixed vector tables and addresses of vector tables

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt 368 Table 4.1.2. Interrupts assigned to the variable vector tables and addresses of vector tables

Variable vector tables The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the ad- dress the INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 4.1.2 shows the interrupts assigned to the variable vector tables and addresses of vector tables. Software interrupt number Interrupt sourceVector table address Address (L) to address (H) Remarks Cannot be masked by I flag+0 to +3 (Note) BRK instructionSoftware interrupt number 0 +44 to +47 (Note) Software interrupt number 11 +48 to +51 (Note) Software interrupt number 12 +52 to +55 (Note) Software interrupt number 13 +56 to +59 (Note) Software interrupt number 14 +68 to +71 (Note) Software interrupt number 17 +72 to +75 (Note) Software interrupt number 18 +76 to +79 (Note) Software interrupt number 19 +80 to +83 (Note) Software interrupt number 20 +84 to +87 (Note) Software interrupt number 21 +88 to +91 (Note) Software interrupt number 22 +92 to +95 (Note) Software interrupt number 23 +96 to +99 (Note) Software interrupt number 24 +100 to +103 (Note)Software interrupt number 25 +104 to +107 (Note)Software interrupt number 26 +108 to +111 (Note)Software interrupt number 27 +112 to +115 (Note)Software interrupt number 28 +116 to +119 (Note)Software interrupt number 29 +120 to +123 (Note)Software interrupt number 30 +124 to +127 (Note)Software interrupt number 31 +128 to +131 (Note)Software interrupt number 32 +252 to +255 (Note)Software interrupt number 63 to Note : Address relative to address in interrupt table register (INTB). to Key input interrupt A-D UART0 transmit UART0 receive UART1 transmit UART1 receive Timer A0 Timer X0 Timer X1 Timer X2 Timer B0 Timer B1 INT0 INT1 Software interrupt Cannot be masked by I flag

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt 369 Table 4.2.1. Memory map of the interrupt control registers

4.2 Interrupt Control

Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a non-maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are located in the flag register (FLG). Table 4.2.1 shows the memory map of the interrupt control registers, and Table 4.2.2 shows the interrupt control registers. 004D 16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C 16 005D 16 005E16 INT1 interrupt control register (INT1IC) Timer B0 interrupt control register (TB0IC) Timer X0 interrupt control register (TX0IC) Timer X2 interrupt control register (TX2IC) UART0 transmit interrupt control register (S0TIC) INT0 interrupt control register (INT0IC) Timer B1 interrupt control register (TB1IC) Timer A0 interrupt control register (TA0IC) Timer X1 interrupt control register (TX1IC) UART0 receive interrupt control register (S0RIC) UART1 transmit interrupt control regster(S1TIC) UART1 receive interrupt control register(S1RIC) Key input interrupt control register(KUPIC) A-D conversion interrupt control register (ADIC)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt 370 Figure 4.2.2. Interrupt control registers Symbol Address When reset INTiIC(i=0, 1) 005D 16, 005E16 XX00X000 2 Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines ILVL0 IR POL Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Interrupt priority level select bit Interrupt request bit Polarity select bit Reserved bit 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Always set to “0” ILVL1 ILVL2 Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts. (Note 1) Interrupt control register (Note 2) b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Bit name FunctionBit symbol W R Symbol Address When reset KUPIC 004D 16 XXXXX000 2 ADIC 004E 16 XXXXX000 2 SiTIC(i=0, 1) 0051 16, 005316 XXXXX000 2 SiRIC(i=0, 1) 0052 16, 005416 XXXXX000 2 TAiIC(i=0) 0055 16 XXXXX000 2 TXiIC(i=0 to 2) 0056 16 to 005816 XXXXX000 2 TBiIC(i=0, 1) 005A 16, 005B16 XXXXX000 2 ILVL0 IR Interrupt priority level select bit Interrupt request bit 0 : Interrupt not requested 1 : Interrupt requested ILVL1 ILVL2Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. (Note 1) Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts. 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt 371 Figure 4.2.3. The timing of reflecting the change in the I flag to the interrupt

4.2.1 Interrupt Enable Flag

The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set to “0” after reset. The content is changed when the I flag is changed causes the acceptance of the interrupt request in the following timing:

When changing the I flag using the REIT instruction, the acceptance of the interrupt takes effect as the REIT instruction is executed.
When changing the I flag using one of the FCLR, FSET, POPC, and LDC instructions, the acceptance of the interrupt is effective as the next instruction is executed.

4.2.2 Interrupt Request Bit

The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The interrupt request bit can also be set to "0" by software. (Do not set this bit to "1"). Previous instruction REIT Interrupt sequence Time Interrupt request generated Determination whether or not to accept interrupt request Previous instruction FSET I Interrupt sequence Next instruction Interrupt request generated Determination whether or not to accept interrupt request When changed by REIT instruction When changed by FCLR, FSET, POPC, or LDC instruction (If I flag is changed from 0 to 1 by REIT instruction) (If I flag is changed from 0 to 1 by FSET instruction) Time

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt 372

4.2.3 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)

Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt priority level to “0” disables the interrupt. Table 4.2.1 shows the settings of interrupt priority levels and Table 4.2.2 shows the interrupt levels en- abled, according to the consist of the IPL. The following are conditions under which an interrupt is accepted:

interrupt enable flag (I flag) = 1
interrupt request bit = 1
interrupt priority level > IPL The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are independent, and they are not affected by one another. Table 4.2.2. Interrupt levels enabled according to the contents of the IPL Table 4.2.1. Settings of interrupt priority levels When either the IPL or the interrupt priority level is changed, the new level is reflected to the interrupt in the following timing:
When changing the IPL using the REIT instruction, the reflection takes effect as of the instruction that is executed in 2 clock cycles after the last clock cycle in volved in the REIT instruction.
When changing the IPL using either the POPC, LDC or LDIPL instruction, the reflection takes effect as of the instruction that is executed in 3 cycles after the last clock cycle involved in the instruction used.
When changing the interrupt priority level using the MOV or similar instruction, the reflection takes effect as of the instruction that is executed in 2 clock cycles after the last clock cycle involved in the instruction used. Interrupt priority level select bit Interrupt priority level Priority order 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Low High b2 b1 b0 Enabled interrupt priority levels 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 4 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled IPL2 IPL1 IPL0 IPL

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt 373

4.2.4 Rewrite the interrupt control register

To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow: When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET Example 1: INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. NOP ; Four NOP instructions are required when using HOLD function. NOP FSET I ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. MOV.W MEM, R0 ; Dummy read. FSET I ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG ; Push Flag register onto stack FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. POPC FLG ; Enable interrupts. The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt 374

4.3.1 Interrupt Response Time

'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). Figure 4.3.1 shows the interrupt response time. Figure 4.3.1. Interrupt response time

4.3 Interrupt Sequence

An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. In the interrupt sequence, the processor carries out the following in sequence given: After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. Note: This register cannot be utilized by the user. (1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading ad- dress 00000 16. (2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU. (3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to “0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed) (4) Saves the content of the temporary register (Note 1) within the CPU in the stack area. (5) Saves the content of the program counter (PC) in the stack area. (6) Sets the interrupt priority level of the accepted instruction in the IPL. Instruction Interrupt sequence Instruction in interrupt routine Time Interrupt response time (a) (b) Interrupt request acknowledgedInterrupt request generated (a) Time from interrupt request is generated to when the instruction then under execution is completed. (b) Time in which the instruction sequence is executed.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt 375 Interrupt sources without priority levels Value set in the IPL Watchdog timer Other Not changed

4.3.2 Variation of IPL when Interrupt Request is Accepted

If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in Table 4.3.2 is set in the IPL. Table 4.3.2. Relationship between interrupts without interrupt priority levels and IPL Table 4.3.1. Time required for executing the interrupt sequence Reset Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction (without wait). Time (b) is as shown in Table 4.3.1.________ Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence interrupt or of a single-step interrupt. Note 2: Locate an interrupt vector address in an even address, if possible. Figure 4.3.2. Time required for executing the interrupt sequence Stack pointer (SP) valueInterrupt vector address 16-Bit bus, without wait 8-Bit bus, without wait Even Even Odd (Note 2) Odd (Note 2) Even Odd Even Odd 18 cycles (Note 1) 19 cycles (Note 1) 19 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) Indeterminate 123456789 1 0 1 1 12 13 14 15 16 17 18 The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs. Indeterminate SP-2

0000 Indeterminate SP-2 SP-4 vec vec+2 PC

W R

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt 376

4.3.3 Saving Registers

In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the stack area. First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. Figure 4.3.3 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM instruction alone can save all the registers except the stack pointer (SP). Figure 4.3.3. State of stack before and after acceptance of interrupt request Address Content of previous stack Stack area [SP] Stack pointer value before interrupt occurs m m – 1 m – 2 m – 3 m – 4 Stack status before interrupt request is acknowledged Stack status after interrupt request is acknowledged Content of previous stackm + 1 MSB LSB m m – 1 m – 2 m – 3 m – 4 Address Flag register (FLGL) Content of previous stack Stack area Flag register (FLGH ) Program counter (PCH ) [SP] New stack pointer value Content of previous stackm + 1 MSB LSB Program counter (PC Program counter (PCM )

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt 377 Figure 4.3.4. Operation of saving registers The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Figure 4.3.4 shows the operation of the saving registers. Note: Stack pointer indicated by U flag. (2) Stack pointer (SP) contains odd number [SP] (Odd) [SP] – 1 (Even) [SP] – 2(Odd) [SP] – 3 (Even) [SP] – 4(Odd) [SP] – 5 (Even) Address Sequence in which order registers are saved (2) (1) Finished saving registers in four operations. (3) (4) (1) Stack pointer (SP) contains even number [SP] (Even) [SP] – 1(Odd) [SP] – 2 (Even) [SP] – 3(Odd) [SP] – 4 (Even) [SP] – 5 (Odd) Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. Address Program counter (PCM ) Stack area Flag register (FLGL) Program counter (PCL) Sequence in which order registers are saved (2) Saved simultaneously, all 16 bits (1) Saved simultaneously, all 16 bits Finished saving registers in two operations. Program counter (PCM ) Stack area Flag register (FLGL) Program counter (PCL) Saved simultaneously, all 8 bits Flag register (FLGH ) Program counter (PCH ) Flag register (FLGH ) Program counter (PCH )

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt 378

4.5 Interrupt Priority

If there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted (see Figure 4.5.1). Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. Figure 4.5.2 shows the priorities of hardware interrupts. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine.

4.4 Returning from an Interrupt Routine

Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter (PC), both of which have been saved in the stack area. Then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process resumes. Return the other registers saved by software within the interrupt routine using the POPM or similar instruc- tion before executing the REIT instruction.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt 380

4.6 Multiple Interrupts

The state when control branched to an interrupt routine is described below:

The interrupt enable flag (I flag) is set to “0” (the interrupt is disabled).
The interrupt request bit of the accepted interrupt is set to “0”.
The processor interrupt priority level (IPL) is assigned to the same interrupt priority level as assigned to the accepted interrupt. Setting the interrupt enable flag (I flag) to “1” within an interrupt routine allows an interrupt request assigned a priority higher than the IPL to be accepted. Figure 4.6.1 shows the scheme of multiple interrupts. An interrupt request that is not accepted because of low priority will be held. If the condition following is met when the REIT instruction returns the IPL and the interrupt priority is determined, then the interrupt request being held is accepted. Interrupt priority level of the interrupt request being held > Returned the IPL

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt 381 Figure 4.6.1. Multiple interrupts Main routineReset I = 0 IPL = 0 I = 1 Interrupt 1 I = 0 IPL = 3 I = 1 Interrupt 2 I = 0 IPL = 5 REIT I = 1 IPL = 3 Interrupt 3 REIT I = 1 IPL = 0 Interrupt 3 I = 0 IPL = 2 REIT I = 1 IPL = 0 Interrupt 1 Interrupt priority level = 3 Interrupt 2 Interrupt 3 Interrupt priority level = 5 Interrupt priority level = 2 Not acknowledged because of low interrupt priority Interrupt request generated Nesting Time : Automatically executed. : Be sure to set in software. I : Interrupt enable flag IPL : Processor interrupt priority level Main routine instructions are not executed. Multiple interrupts

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt 382 Figure 4.7.1. Switching condition of INT interrupt request

4.7 Precautions for Interrupts

(1) Reading address 0000016

When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”. Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”. Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 00000 16 by software. (2) Setting the stack pointer
The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the stack pointer before accepting an interrupt. Concerning the first instruction immediately after reset, generating any interrupts is prohibited. (3) External interrupt
Either an “L” level or an “H ” level of at least 250 ns width is necessary for the signal input to pins INT0 and INT1 regardless of the CPU operation clock.
When the polarity of the INT0 and INT1 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0". Figure 4.7.1 shows the procedure for changing the INT interrupt generate factor. Set the interrupt priority level to level 0 (Disable INTi interrupt) Set the polarity select bit Clear the interrupt request bit to “0” Set the interrupt priority level to level 1 to 7 (Enable the accepting of INTi interrupt request) Set the interrupt enable flag to “1” (Enable interrupt) Clear the interrupt enable flag to “0” (Disable interrupt)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt 383 (4) Rewrite the interrupt control register

To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow:
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET Example 1: INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. NOP ; Four NOP instructions are required when using HOLD function. NOP FSET I ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. MOV.W MEM, R0 ; Dummy read. FSET I ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG ; Push Flag register onto stack FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. POPC FLG ; Enable interrupts. The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt 384 [MEMO]

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 386

5.1 Standard DC Characteristics

The standard characteristics given in this section are examples of M30201M4-XXXFP. The contents of these examples cannot be guaranteed. For standardized values, see “Electric characteristics”.

5.1.1 Standard Ports Characteristics

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 389

5.1.2 Standard Characteristics of ICC -f(XIN)

given in this section are examples of M30201M4-XXXFP. The contents of these examples cannot be guaranteed. For standardized values, see “Electric characteristics”. Figures 5.1.7. Standard characteristics of ICC -f(XIN) (VCC = 5V) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines XIN / 1 XIN / 2 XIN / 4 XIN / 8 XIN / 16 0 246 8 10 ICC [mA] f(XIN) [MHz]

Measurement conditions : VCC = 5V, Ta = 25˚C, f(XIN) : square waveform input, single-chip mode When access to ROM and RAM without wait
Register setting condition XIN - XOUT drive capacity select bit = “1” (HIGH) Main clock (XIN - XOUT ) stop bit = “0” (On) Note: Data described here are characteristic examples. The data values are not guaranteed. Re fer to section“Electrical characteristics”for rated values. VCC =5V

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 390 Figures 5.1.8. Standard characteristics of ICC -f(XIN) (VCC = 3V) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines XIN / 1 XIN / 2 XIN / 4 XIN / 8 XIN / 16 0 246 8 10 ICC [mA] f(XIN) [MHz] Note: Data described here are characteristic examples. The data values are not guaranteed. Refer to section “Electrical characteristics” for rated values. VCC =3V /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

Measurement conditions : VCC = 3V, Ta = 25˚C, f(XIN) : square waveform input, single-chip mode When access to ROM and RAM without wait
Register setting condition XIN - XOUT drive capacity select bit = “1” (HIGH) Main clock (XIN - XOUT ) stop bit = “0” (On)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 391 Note: Data described here are characteristic examples. The data values are not guaranteed.

5.2 Standard Characteristics of Pull-Up Resistor

Figure 5.2.1 shows an example of the standard characteristics of the pull-up resistor. The standard character- istics given in this section are examples of M30201M4-XXXFP. The contents of these examples cannot be guaranteed. For standardized values, see “Electric characteristics”. Figure 5.2.1. Example of the standard characteristics of the pull-up resistor — 50 — 100 — 150 102 3 4 5 II [µ VI [V] VCC =5V VCC =3V Ta=25°C

Standard Characteristics (Flash memory version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 392

5.3 Standard DC Characteristics (Flash memory version)

The standard characteristics given in this section are examples of M30201F6FP. The contents of these examples cannot be guaranteed. For standardized values, see “Electric characteristics”.

5.3.1 Standard Ports Characteristics

Standard Characteristics (Flash memory version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 394

5.3.2 Standard Characteristics of ICC -f(XIN)

Figure 5.3.4 shows the Characteristics of ICC -f(XIN). The standard characteristics given in this section are examples of M30201F6FP. The contents of these examples cannot be guaranteed. For standardized values, see “Electric characteristics”. Figures 5.3.4. Standard characteristics of ICC -f(XIN) (VCC = 5V) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines XIN / 1 XIN / 2 XIN / 4 XIN / 8 XIN / 16 246 8 10 ICC [mA] f(XIN) [MHz]

Measurement conditions : VCC = 5V, Ta = 25˚C, f(XIN) : square waveform input, single-chip mode When access to ROM and RAM without wait
Register setting condition XIN - XOUT drive capacity select bit = “1” (HIGH) Main clock (XIN - XOUT ) stop bit = “0” (On) Note: Data described here are characteristic examples. The data values are not guaranteed. Refer to section “Electrical characteristics” for rated values. VCC =5V

Standard Characteristics (Flash memory version) Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 395 Note: Data described here are characteristic examples. The data values are not guaranteed.

5.4 Standard Characteristics of Pull-Up Resistor

Figure 5.4.1 shows an example of the standard characteristics of the pull-up resistor. The standard character- istics given in this section are examples of M30201F6FP. The contents of these examples cannot be guaran- teed. For standardized values, see “Electric characteristics”. Figure 5.4.1. Example of the standard characteristics of the pull-up resistor — 50 — 100 — 150 102 3 4 5 II [µ VI [V] VCC =5V Ta=25°C

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 396 Appendix 1 Check Sheet The following check sheet was created based on items which had been the source of problems in the past. We recommend you refer to the check sheet when troubleshooting. Checks regarding register initial settings Has the initial setting been made in the interrupt stack pointer (ISP) at the top of the program? Has the initial setting been made in the user stack pointer (USP)? (Only if using the USP) Does the USP overlap the ISP area? (Only if using the USP) Is interrupt enabled after setting the ISP and USP? Is the top address of the variable interrupt vector table set in the interrupt table register (INTB)? Is interrupt enabled after setting the INTB? Has the initial setting been made in the frame base register (FB)? (Only if using the FB) Has the initial setting been made in the stack base register (SB)? (Only if using the SB) Checks regarding the internal memory Does the RAM capacity used in the program exceed the RAM capacity of the microcomputer? Does the ROM capacity used in the program exceed the ROM capacity of the microcomputer? Checks regarding the protect register Is writing enabled in the protect register (address 000A16) before writing in the system clock control register (addresses 000616 and 000716)? Is writing enabled in the protect register before writing in the processor mode register (addresses 000416 and 000516)? Is writing enabled in the protect register before writing in the port P4 direction register (address 03EA 16)? Is writing effectuated in the port P4 direction register by the next instruction after writing is enabled in the protect register? Does not an interrupt generate between the instruction writing is enabled in the protect register and the instruction writing in the port P4 direction register?

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 397 Checks regarding the timer Is the timer started after a value is set in the timer register? Checks regarding low power consumption In the low power consumption mode, does not current flow from Vref when the Vref connection bit (bit 5 in address 03D716) is set? Is not voltage level of port floating in the low power consumption mode? Checks regarding Interrupt When rewrite the interrupt register, do so at a point that does not generate the interruput request? Checks regarding low voltage When using at low voltage, have you checked recommended operating conditions and changed the wait bit (address 0005 16, bit 7) to “1”? Checks regarding A-D converter Have you selected other than fAD (no dividing) for øAD when using the A-D converter at VCC = 2.7 - 4.0V? Have you selected no sample & hold function when using the A-D converter at V CC = 2.7 - 4.0V? Have you selected 8-bit mode when using the A-D converter at VCC = 2.7 - 4.0V?

Appendix 2 Hexadecimal instruction CODE table 398 Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER D7 to D4 0000 0001 0010 0011 0100 0101 0110 0111 D3 to D0 0 1 2 3 4 5 6 7 R0H,R0L R0H,R0L R0H,A0 0,11[SB] 0,11[SB] label src,dest R0L,dsp:8[SB] dsp:8[SB],R0L dsp:8[SB],R0L dsp:8[SB],A0 1,11[SB] 1,11[SB] label src,dest R0L,dsp:8[FB] dsp:8[FB],R0L dsp:8[FB],R0L dsp:8[FB],A0 2,11[SB] 2,11[SB] label src,dest R0L,abs16 abs16,R0L abs16,R0L abs16,A0 3,11[SB] 3,11[SB] label src,dest 0100 4 NOP AND.B:S ADD.B:S MOV.B:S BCLR:S BNOT:S JMP.S CODE_74 R0L,R0H R0L,R0H R0 Ç k,A1 4,11[SB] 4,11[SB] label R0H,dsp:8[SB] dsp:8[SB],R0H dsp:8[SB],R0H dsp:8[SB],A1 5,11[SB] 5,11[SB] label R0H,dsp:8[FB] dsp:8[FB],R0H dsp:8[FB],R0H dsp:8[FB],A1 6,11[SB] 6,11[SB] label R0H,abs16 abs16,R0H abs16,R0H abs16,A1 7,11[SB] 7,11[SB] label R0H,R0L R0H,R0L R0H,R0L R0H,R0L 0,11[SB] 0,11[SB] label src,dest dsp:8[SB],R0L dsp:8[SB],R0L dsp:8[SB],R0L dsp:8[SB],R0L 1,11[SB] 1,11[SB] label src,dest 1010 A MOV.B:S OR.B:S SUB.B:S CMP.B:S BSET:S BTST:S JEQ/Z CODE_7A dsp:8[FB],R0L dsp:8[FB],R0L dsp:8[FB],R0L dsp:8[FB],R0L 2,11[SB] 2,11[SB] label 1011 B MOV.B:S OR.B:S SUB.B:S CMP.B:S BSET:S BTST:S JN CODE_7B abs16,R0L abs16,R0L abs16,R0L abs16,R0L 3,11[SB] 3,11[SB] label 1100 C MOV.B:S OR.B:S SUB.B:S CMP.B:S BSET:S BTST:S JLTU/NC CODE_7C R0L,R0H R0L,R0H R0L,R0H R0L,R0H 4,11[SB] 4,11[SB] label 1101 D MOV.B:S OR.B:S SUB.B:S CMP.B:S BSET:S BTST:S JLEU CODE_7D dsp:8[SB],R0H dsp:8[SB],R0H dsp:8[SB],R0H dsp:8[SB],R0H 5,11[SB] 5,11[SB] label 1110 E MOV.B:S OR.B:S SUB.B:S CMP.B:S BSET:S BTST:S JNE/JNZ CODE_7E dsp:8[FB],R0H dsp:8[FB],R0H dsp:8[FB],R0H dsp:8[FB],R0H 6,11[SB] 6,11[SB] label 1111 F MOV.B:S OR.B:S SUB.B:S CMP.B:S BSET:S BTST:S JPZ abs16,R0H abs16,R0H abs16,R0H abs16,R0H 7,11[SB] 7,11[SB] label The next instruction is arranged in each CODE. CODE_74:STE,MOV,PUSH,NEG,ROT,NOT,LDE,POP,SHL,SHA CODE_75:STE,MOV,PUSH,NEG,ROT,NOT,LDE,POP,SHL,SHA CODE_76:TST,XOR,AND,OR,ADD,SUB,ADC,SBB,CMP,DIVX,ROLC,RORC,DIVU,DIV,ADCF,ABS CODE_77:TST,XOR,AND,OR,ADD,SUB,ADC,SBB,CMP,DIVX,ROLC,RORC,DIVU,DIV,ADCF,ABS CODE_7A:XCHG,LDC CODE_7B:XCHG,STC CODE_7C:MOV Dir,MULU,MUL,EXTS,STC,DIVU,DIV,PUSH,DIVX,DADD,DSUB,DADC,DSBB,SMOVF,SMOVB,SSTR,ADD,LDCTX,RMPA,ENTER CODE_7D:JMPI,JSRI,MULU,MUL,PUSHA,LDIPL,ADD,J Cnd ,BMCnd ,DIVU,DIV,PUSH,DIVX,DADD,DSUB,DADC,DSBB,SMOVF,SMOVB,SSTR, STCTX,RMPA,EXITD,WAIT CODE_7E:BTSTC,BM Cnd ,BNTST,BAND,BNAND,BOR,BNOR,BCLR,BSET,BNOT,BTST,BXOR,BNXOR CODE_EB:SHL,FSET,FCLR,MOVA,LDC,SHA,PUSHC,POPC,INT

Appendix 2 Hexadecimal instruction CODE table 399 Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER D7 to D4 1000 1001 1010 1011 1100 1101 1110 1111 D3 to D0 8 9 A B C D E F src,dest src,dest src,dest src,dest src,dest #IMM,dest #IMM,dest #IMM,dest src,dest src,dest src,dest src,dest src,dest #IMM,dest #IMM,dest #IMM,dest R0L R0L #IMM,A0 A0 A0 A0 #IMM,A0 A0 #IMM8,R0H #IMM8,R0H R0H #0,R0H #IMM8,R0H #IMM8,R0H #IMM8,R0H #IMM8,R0L #IMM8,R0L R0L #0,R0L #IMM8,R0L #IMM8,R0L #IMM8,R0L label #IMM8,dsp:8[SB] #IMM8,dsp:8[SB] dsp:8[SB] #0,dsp:8[SB] #IMM8,dsp:8[SB] #IMM8,dsp:8[SB] #IMM8,dsp:8[SB] label #IMM8,dsp:8[FB] #IMM8,dsp:8[FB] dsp:8[FB] #0,dsp:8[FB] #IMM8,dsp:8[FB] #IMM8,dsp:8[FB] #IMM8,dsp:8[FB] #IMM8,abs16 #IMM8,abs16 abs16 #0,abs16 #IMM8,abs16 #IMM8,abs16 #IMM8,abs16 src,dest src,dest src,dest src,dest #IMM,dest #IMM,dest #IMM,dest #IMM,dest,label src,dest src,dest src,dest src,dest #IMM,dest #IMM,dest #IMM,dest #IMM,dest,label R0H R0H #IMM,A1 A1 A1 A1 #IMM,A1 A1 1011 B SUB.B:S OR.B:S DEC.B NOT.B:S STZ STZX CODE_EB REIT #IMM8,R0H #IMM8,R0H R0H R0H #IMM8,R0H #IMM8,#IMM8,R0H #IMM8,R0L #IMM8,R0L R0L R0L #IMM8,R0L #IMM8,#IMM8,R0L src label #IMM8,dsp:8[SB] #IMM8,dsp:8[SB] dsp:8[SB] dsp:8[SB] #IMM8,dsp:8[SB] #IMM8,#IMM8,dsp:8[SB] dest label #IMM8,dsp:8[FB] #IMM8,dsp:8[FB] dsp:8[FB] dsp:8[FB] #IMM8,dsp:8[FB] #IMM8,#IMM8,dsp:8[FB] #IMM8 label 1111 F SUB.B:S OR.B:S DEC.B NOT.B:S STZ STZX JSRS UND #IMM8,abs16 #IMM8,abs16 abs16 abs16 #IMM8,abs16 #IMM8,#IMM8,abs16 #IMM8

MITSUBISHI Single-Chip Microcomputer User's Manual M30201 Group REV.C Mar. First Edition 1999 May. Second Edition 1999 Jun. Third Edition 2001 Editioned by Committee of editing of Mitsubishi Semiconductor USER'S MANUAL Published by Mitsubishi Electric Corp., Kitaitami Works This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. ©2001 MITSUBISHI ELECTRIC CORPORATION

Product Information

M30201M4-XXXSP specifications and overview.

Summary

16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY

Description

The M30201 group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core. M30201 group is packaged in a 52-pin plastic molded SDIP, or 56-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed.

Source title M30201M4-XXXSP Datasheet(PDF) - Renesas Technology Corp

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