M301N2F8FP

M16C1N RENESAS | Alldatasheet

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RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES M16C/1N Group16 Rev. 1.00 Revision date: Oct 20, 2004 Hardware Manual www.renesas.com Before using this material, please visit our website to confirm that this is the most current document available. REJ09B0007-0100Z

Keep safety first in your circuit designs! Notes regarding these materials 1. Renesas Technology Corporation puts the maximum effort into making semiconductor prod- ucts better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with ap- propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap. 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringe- ment of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, pro- grams and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that custom- ers contact Renesas Technology Corporation or an authorized Renesas Technology Cor- poration product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all informa- tion as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any dam- age, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is poten- tially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product con- tained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be im- ported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.

1. Introduction This hardware manual provides detailed information on the M16C/1N Group of microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers. 2. Register Diagram The symbols, and descriptions, used for bit function in each register are shown below. Function XXX Register Bit NameBit Symbol Symbol Address After Reset XXX XXX 00 16 RW RW RW WO RO XXX0 XXX1 (b2) (b4 - b3) XXX bit Reserved bit XXX7 Set to "0" 0: XXX 1: XXX Nothing is assigned. When write, set to "0". When read, its content is indeterminate. XXX bit 0 0: XXX 0 1: XXX 1 0: Do not set a value 1 1: XXX b1b0 XXX bit Function varies depending on mode of operation XXX5 XXX6 RW RW b7 b6 b5 b4 b3 b2 b1 b0 Blank:Set to "0" or "1" according to the application 0: Set to "0" 1: Set to "1" X: Nothing is assigned RW: Read and write RO: Read only WO: Write only –: Nothing is assigned

• Reserved bit Reserved bit. Set to specified value.
• Nothing is assigned Nothing is assigned to the bit concerned. As the bit may be use for future functions, set to "0" when writing to this bit.
• Do not set a value The operation is not guaranteed when a value is set.
• Function varies depending on mode of operation Bit function varies depending on peripheral function mode. Refer to respective register for each mode.

1. M16C Family Documents The following documents were prepared for the M16C family. (1) Document Contents Short Sheet Hardware overview Data Sheet Hardware overview and electrical characteristics Hardware Manual Hardware specifications (pin assignments, memory maps, peripheral specifi- cations, electrical characteristics, timing charts) Software Manual Detailed description of assembly instructions and microcomputer perfor- mance of each instruction Application Note • Application examples of peripheral functions

• Sample programs
• Introduction to the basic functions in the M16C family
• Programming method with Assembly and C languages Technical Update Preliminary report about the specification of a product, a document, etc. NOTES : 1. Before using this material, please visit the our website to confirm that this is the most current document available.

M16C/1N Group Usage Note Reference Book For the most current Usage Note Reference Book, please visit our website. Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition.

Quick Reference to Pages Classified by Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Processor mode register 0 Processor mode register 1 System clock control register 0 System clock control register 1 Address match interrupt enable register Protect register Oscillation stop detection register Watchdog timer start register Watchdog timer control register Address match interrupt register 0 Address match interrupt register 1 INT0 input filter select register PM0 PM1 CM0 CM1 AIER PRCR CM2 WDTS WDC RMAD0 RMAD1 INT0F 22, 41 22, 41, 69 26, 37 60, 94 Note 1: The blank areas are reserved. Address Register Symbol Page 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 007016 007116 007216 007316 007416 007516 007616 007716 007816 007916 007A16 007B16 007C16 007D16 007E16 007F16 CAN0 wake up interrupt control register CAN0 error interrupt control register CAN0 successful reception interrupt control register CAN0 successful transmission interrupt control register Key input interrupt control register A/D conversion interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer 1 interrupt control register Timer X interrupt control register Timer Y interrupt control register Timer Z interrupt control register CNTR0 interrupt control register TCIN interrupt control register Timer C interrupt control register INT3 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register C01WKIC C01ERRIC C0RECIC C0TRMIC KUPIC ADIC S0TIC S0RIC S1TIC S1RIC T1IC TXIC TYIC TZIC CNTR0IC TCINIC TCIC INT3IC INT0IC INT1IC INT2IC Address Register Symbol Page

Timer Y, Z mode register Prescaler Y Timer Y secondary Timer Y Primary Timer Y, Z waveform output control register Prescaler Z Timer Z secondary Timer Z Primary Prescaler 1 Timer 1 Timer Y, Z output control register Timer X mode register Prescaler X Timer X Timer count source setting register Clock prescaler reset flag Timer C External input enable register Key input enable register Timer C control register 0 Timer C control register 1 Timer measurement register UART0 transmit/receve mode register UART0 bit rate generator UART0 transmit buffer register UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 bit rate generator UART1 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 UART1 receive buffer register UART transmit/receive control register 2 TYZMR PREY TYSC TYPR PUM PREZ TZSC TZPR PRE1 TYZOC TXMR PREX TX TCSS CPSRF TC INTEN KIEN TCC0 TCC1 TM U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON 82, 86, 88, 91, 96, 98, 100, 103 84, 86, 88, 93, 96, 98, 100, 103 83, 94 62, 73, 75-78, 80 72, 74, 84, 93 106 60, 94 63, 106 106 111, 114, 119 110 111 112 110 111, 114, 119 110 111 112 110 112 Note 1: The blank areas are reserved. Address Register Symbol Page 00C016 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 00EB16 00EC16 00ED16 00EE16 00EF16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA16 00FB16 00FC16 00FD16 00FE16 00FF16 A/D register A/D control register 2 A/D control register 0 A/D control register 1 D/A register D/A control register Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P2 register Port P3 register Port P2 direction register Port P3 direction register Port P4 register Port P5 register Port P4 direction register Port P5 direction register CAN0 I/O pin select register Pull-up control register 0 Pull-up control register 1 Port P1 drive capacity control register AD ADCON2 ADCON0 ADCON1 DA DACON PD0 PD1 PD2 PD3 PD4 PD5 CIOSR PUR0 PUR1 DRR 125 125 124, 126, 127 130 130 160 162 161 Address Register Symbol Page

Flash memory control register 4 Flash memory control register 1 Flash memory control register 0 CAN0 message control register 0 CAN0 message control register 1 CAN0 message control register 2 CAN0 message control register 3 CAN0 message control register 4 CAN0 message control register 5 CAN0 message control register 6 CAN0 message control register 7 CAN0 message control register 8 CAN0 message control register 9 CAN0 message control register 10 CAN0 message control register 11 CAN0 message control register 12 CAN0 message control register 13 CAN0 message control register 14 CAN0 message control register 15 CAN0 control register CAN0 status register CAN0 slot status register CAN0 interrupt control register CAN0 extended ID register CAN0 configuration register CAN0 reception error count register CAN0 transmission error count register FMR4 FMR1 FMR0 C0MCTL0 C0MCTL1 C0MCTL2 C0MCTL3 C0MCTL4 C0MCTL5 C0MCTL6 C0MCTL7 C0MCTL8 C0MCTL9 C0MCTL10 C0MCTL11 C0MCTL12 C0MCTL13 C0MCTL14 C0MCTL15 C0CTLR C0STR C0SSTR C0ICR C0IDR C0CONR C0RECR C0TECR 182 182 181 136 137 138 139 140 140 141 142 Note 1: The blank areas are reserved. Address Register symbol Page 024016 024116 024216 024316 024416 024516 024616 024716 024816 024916 024A16 024B16 024C16 024D16 024E16 024F16 025016 025116 025216 025316 025416 025516 025616 025716 025816 025916 025A16 025B16 025C16 025D16 025E16 025F16 026016 026116 026216 026316 026416 026516 026616 026716 026816 026916 026A16 026B16 026C16 026D16 026E16 026F16 027016 027116 027216 027316 027416 027516 027616 027716 027816 027916 027A16 027B16 027C16 027D16 027E16 027F16 CAN0 acceptance filer support register CAN0 clock select register CAN0 message box 0: Identifier/DLC CAN0 message box 0: Data field CAN0 message box 0: Time stamp CAN0 message box 1: Identifier/DLC CAN0 message box 1: Data field CAN0 message box 1: Time stamp C0AFS CCLKR 143 133 134 Address Register Symbol Page

CAN0 message box 2: Identifier/DLC CAN0 message box 2: Data field CAN0 message box 2: Time stamp CAN0 message box 3: Identifier/DLC CAN0 message box 3: Data field CAN0 message box 3: Time stamp CAN0 message box 4: Identifier/DLC CAN0 message box 4: Data field CAN0 message box 4: Time stamp CAN0 message box 5: Identifier/DLC CAN0 message box 5: Data field CAN0 message box 5: Time stamp Note 1: The blank areas are reserved. Address Register Symbol Page 02C016 02C116 02C216 02C316 02C416 02C516 02C616 02C716 02C816 02C916 02CA16 02CB16 02CC16 02CD16 02CE16 02CF16 02D016 02D116 02D216 02D316 02D416 02D516 02D616 02D716 02D816 02D916 02DA16 02DB16 02DC16 02DD16 02DE16 02DF16 02E016 02E116 02E216 02E316 02E416 02E516 02E616 02E716 02E816 02E916 02EA16 02EB16 02EC16 02ED16 02EE16 02EF16 02F016 02F116 02F216 02F316 02F416 02F516 02F616 02F716 02F816 02F916 02FA16 02FB16 02FC16 02FD16 02FE16 02FF16 CAN0 message box 6: Identifier/DLC CAN0 message box 6: Data field CAN0 message box 6: Time stamp CAN0 message box 7: Identifier/DLC CAN0 message box 7: Data field CAN0 message box 7: Time stamp CAN0 message box 8: Identifier/DLC CAN0 message box 8: Data field CAN0 message box 8: Time stamp CAN0 message box 9: Identifier/DLC CAN0 message box 9: Data field CAN0 message box 9: Time stamp 133 134 Address Register Symbol Page

CAN0 message box 10: Identifier/DLC CAN0 message box 10: Data field CAN0 message box 10: Time stamp CAN0 message box 11: Identifier/DLC CAN0 message box 11: Data field CAN0 message box 11: Time stamp CAN0 message box 12: Identifier/DLC CAN0 message box 12: Data field CAN0 message box 12: Time stamp CAN0 message box 13: Identifier/DLC CAN0 message box 13: Data field CAN0 message box 13: Time stamp Note 1: The blank areas are reserved. 133 134 Address Register Symbol Page 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16 037016 037116 03B416 03B516 03B616 03B716 03B816 03B916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16 CAN0 message box 14: Identifier/DLC CAN0 message box 14: Data field CAN0 message box 14: Time stamp CAN0 message box 15: Identifier/DLC CAN0 message box 15: Data field CAN0 message box 15: Time stamp CAN0 global mask register CAN0 local mask A register CAN0 local mask B register 133 134 135 Address Register Symbol Page

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.00 Oct 20, 2004 page 1 of 222 REJ09B0007-0100Z 1. Overview The M16C/1N group consists of single-chip microcomputers that use high-performance silicon gate CMOS processes and have a on-chip M16C/60 series CPU core. The microcomputers are housed in 48-pin plastic mold QFP package. These single-chip microcomputers have both high function instructions and high in- struction efficiency and feature a one-megabyte address space and the capability to execute instructions at high speed.

1.1 Applications

Automotive and industrial control systems, other automobile, other

Rev.1.00 Oct 20, 2004 page 2 of 222 M16C/1N Group 1. Overview REJ09B0007-0100Z Item Performance Number of basic instructions 91 instructions Shortest instruction execution time 62.5 ns (when f(X IN)=16MHz) Memory ROM See Table 1.2 Performance overview size RAM See Table 1.2 Performance overview I/O port P0 to P5: 37 lines Multifunction T1 8 bits x 1 timer TX, TY, TZ 8 bits x 3 TC 16 bits x 1 Serial I/O (UART or clock synchronous) x 2 A/D converter x 12 channels (maximum resolution: 10 bits) (Expandable up to 14 channels) D/A converter 8 bits x 1 CAN controller 1 channel, 2.0B active Watchdog timer 15 bits x 1 (with prescaler) Interrupts 15 internal causes, 8 external causes, 4 software causes Clock generating circuits 3 internal circuits Power supply voltage 4.2 V to 5.5V (when f(X IN)=16MHz) Power consumption 70mW(V CC=5.0V, f(XIN)=16MHz) I/O I/O withstand voltage 5V characteristics Output current 5mA (10mA:LED drive port) Device configuration CMOS silicon gate Package 48-pin LQFP Table 1.1 Performance overview

1.2 Performance Overview

Table 1.1 gives an overview of the M16C/1N group performance specification.

Rev.1.00 Oct 20, 2004 page 3 of 222 M16C/1N Group 1. Overview REJ09B0007-0100Z R0LR0H R0LR0H R1H R1L FB SB ISP USP INTB FLG PC Timer Timer 1 (8 bits) Timer X (8 bits) Timer Y (8 bits) Timer Z (8 bits) Timer C (16 bits) Internal peripheral functions Watchdog timer (15 bits) A/D converter (10 bits X 12 channels, expandable to 14 channels) UART/clock synchronous SI/O (8 bits X 2 channels) System clock generator XIN-XOUT XCIN-XCOUT On-chip oscillation M16C/60 series 16-bit CPU core I/O ports Port P0 Port P1 Port P2 Port P4 Registers Stack pointers Vector table Multiplier Memory ROM (Note 1) RAM (Note 2) Program counter Note 1: ROM size depends on MCU type. Note 2: RAM size depends on MCU type. D/A converter (8 bits X 1 channel) Flag register Port P3 Port P5 CAN controller (1 channel)

1.3 Block Diagram

Figure 1.1 shows block diagram of the M16C/1N group. Figure 1.1 Block diagram

Rev.1.00 Oct 20, 2004 page 4 of 222 M16C/1N Group 1. Overview REJ09B0007-0100Z Type No. ROM RAM Package Remarks M301N2M4T-XXXFP(D) 32Kbytes 1Kbytes Mask ROMM301N2M8T-XXXFP(D) 48P6Q-AM301N2F8TFP(D) 64Kbytes 3Kbytes Flash memoryM301N2F8FP(D) (D): Under development Type No. M30 1N 2 M 4 T - XXX FP Package type: FP: Package 48P6Q-A ROM No. Omitted for flash memory version Indicates differences in characteristics and usage etc: Nothing: Common T: Automobiles Memory type: M: Mask ROM version F: Flash memory version M16C/1N Group M16C Family ROM size: 4: 32 Kbytes 8: 64 Kbytes Indicates pin count, etc (The value itself has no specific meaning) Figure 1.2 Type No., memory size, and package Table 1.2 Performance overview As of June 2004

1.4 Performance Overview

Table 1.2 shows performance overview.

Rev.1.00 Oct 20, 2004 page 5 of 222 M16C/1N Group 1. Overview REJ09B0007-0100Z Note 1: Either P02, P03 or P50, P51 can be selected as CAN0 I/O ports by software. Package: 48P6Q-A 6/CLK1 P35/RxD1 P34/CLKS1/DA CNVSS P47/XCIN P46/XCOUT RESET XOUT VSS XIN VCC P17/CNTR0 P44/INT2 P45/INT0 P10/KI0/AN8 P11/KI1/AN9 P12/KI2/AN10 P20 NC P13/KI3/AN11 P14/TxD0 P15/RxD0 P16/CLK0 6/AN1 P05/AN2 P04/AN3 VREF P52 P51(CRx)(Note 1) P50(CTx)(Note 1) P03/AN4/CRx(Note 1) P02/AN5/CTx(Note 1) P01/AN6 P00/AN7 P37/TxD1/RxD1 M16C/1N Group P07/AN0 IVCC P30/TXOUT VSS P31/TZOUT VCC P40/ANEX0 P41/ANEX1 P42/INT3 P43/INT1 P32/TYOUT P33/TCIN

1.5 Pin Configuration

Figure 1.3 shows pin configurations (top view) of the M16C/1N group. Figure 1.3 Pin configuration diagram (top view)

Rev.1.00 Oct 20, 2004 page 6 of 222 M16C/1N Group 1. Overview REJ09B0007-0100Z VCC, VSS CNVSS XIN VREF P00 to P07 P10 to P17 P30 to P37 P40 to P47 Signal name Power supply input CNVSS Reset input Clock input Reference voltage input I/O port P0 I/O port P1 I/O port P3 I/O port P4 FunctionPin name Input Input Input Input XOUT Clock output Output Input Input Input/output Input/output I/O type Input/output Input/output RESET P20 to P21 IVCC IVCC I/O port P2 Input/output P50 to P52 I/O port P5 Input/output This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When set for input, the user can specify in units of four bits via software whether or not they are tied to a pull-up resistor. These pins are shared with analog input pins. 2 and P03 function as CAN0 I/O pins by using software. This is a 3-bit I/O port equivalent to P0. P50 and P51 function as CAN0 I/O pins by using software. Supply 4.2 to 5.5 V to the VCC pin. Supply 0 V to the VSS pin. Connect a capacitor (0.1 µF) between this pin and VSS. A "L" on this input resets the microcomputer. This is a 2-bit I/O port equivalent to P0. This pin is a reference voltage input for the A/D converter. This is an 8-bit I/O port equivalent to P0. P10 to P13 are shared with analog inputs and key input interrupts. P14 to P16 are shared with serial I/O pins. P17 is shared with timer input. Can be used as an LED drive port. This is a 8-bit I/O port equivalent to P0. P40 to 41 are shared with analog inputs. P42 to P45 are shared with interrupt inputs. P46 to P47 are shared with the I/O pin of the clock oscillation circuit for the clock. This is a 8-bit I/O port equivalent to P0. P30 to P33 are shared with timer input/output. P34 to P37 are shared with serial I/O. P34 is shared with analog outputs. These pins are provided for the main clock oscillation circuit. Connect a ceramic resonator or crystal between the XIN and XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. Connect it to the VSS pin via resistance (about 5 kΩ).

1.6 Pin Description

Table 1.3 shows the pin description. Table 1.3 Pin Description

Rev.1.00 Oct 20, 2004 page 7 of 222 M16C/1N Group 2. Central Processing Unit (CPU) REJ09B0007-0100Z

2.1 Data Registers (R0, R1, R2, and R3)

The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are the same as R0. The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers. R1H and R1L are the same as R0H and R0L. Conversely R2 and R0 can be combined for use as a 32-bit data register (R2R0). R3R1 is the same as R2R0.

2.2 Address Registers (A0 and A1)

The A0 register consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the same as A0. In some instructions, A1 and A0 can be combined for use as a 32-bit address register (A1A0). Figure 2.1 CPU Registers 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks. SB USP ISP b15 b0 Static base register User stack pointer Interrupt stack pointer b19 INTBLINTBH The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL. Interrupt table register b19 PC Program counter R0H (R0's high bits) R0L (R0's low bits) R1H (R1's high bits) R1L (R1's low bits) b31 b15 b8 b7 b0 FB Data registers (Note 1) Address registers (Note 1) Frame base registers (Note 1) Note 1: These registers comprise a register bank. There are two register banks. b15 b0 Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area b15 b0 FLG Flag register IPL U I O B S Z D C b7b8

Rev.1.00 Oct 20, 2004 page 8 of 222 M16C/1N Group 2. Central Processing Unit (CPU) REJ09B0007-0100Z

2.3 Frame Base Register (FB)

FB is configured with 16 bits, and is used for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB is configured with 20 bits, indicating the start address of an interrupt vector table.

2.5 Program Counter (PC)

PC is configured with 20 bits, indicating the address of an instruction to be executed.

2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)

Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.

2.7 Static Base Register (SB)

SB is configured with 16 bits, and is used for SB relative addressing.

2.8 Flag Register (FLG)

FLG consists of 11 bits, indicating the CPU status.

2.8.1 Carry Flag (C Flag)

This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.

2.8.2 Debug Flag (D Flag)

This flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.

2.8.3 Zero Flag (Z Flag)

This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.

2.8.4 Sign Flag (S Flag)

This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.

2.8.5 Register Bank Select Flag (B Flag)

Register bank 0 is selected when this flag is “0”; register bank 1 is selected when this flag is “1”.

2.8.6 Overflow Flag (O Flag)

This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.

2.8.7 Interrupt Enable Flag (I Flag)

This flag enables a maskable interrupt. Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag is set to “0” when the interrupt request is accepted.

2.8.8 Stack Pointer Select Flag (U Flag)

ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”. The U flag is set to “0” when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than IPL, the interrupt request is enabled.

2.8.10 Reserved Area

When white to this bit, write “0”. When read, its content is indeterminate.

Rev.1.00 Oct 20, 2004 page 9 of 222 M16C/1N Group 3. Memory REJ09B0007-0100Z 3. Memory Figure 3.1 is a memory map. The address space extends the 1M bytes from address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M301N2M4T-XXXFP, there is 32K bytes of internal ROM from F800016 to FFFFF16. The vector table for fixed interrupts such as the reset are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the section on interrupts for details. From 00400 16 up is RAM. For example, in the M301N2M4T-XXXFP, there is 1K byte of internal RAM from 0040016 to 007FF16. In addition to storing data, the RAM also stores the stack used when calling subrou- tines and when interrupts are generated. The SFR area is mapped to 00000 16 to 003FF16. This area accommodates the control registers for periph- eral devices such as I/O ports, A/D converter, serial I/O, and timers, etc. Any part of the SFR area that is not occupied is reserved and cannot be used for other purposes. The special page vector table is mapped to FFE00 16 to FFFDB16. If the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps. Figure 3.1 Memory map Special page vector table Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer DBC UART0 reception Reset FFE00 16 FFFDC 16 FFFFF 16 SFR area (For details, refer to 4. SFR) Internal RAM area Internal ROM area 0000016 0040016 XXXXX16 YYYYY16 FFFFF16 Type No. Internal RAM Internal ROM Size Address YYYYY16 Size Address XXXXX16 M301N2M4T M301N2M8T M301N2F8TFP M301N2F8FP

32 Kbytes

64 Kbytes

1 Kbytes

3 Kbytes

Rev.1.00 Oct 20, 2004 page 10 of 222 M16C/1N Group 4. Special Function Registers (SFR) REJ09B0007-0100Z 4. Special Function Registers (SFR) 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 PM0 PM1 CM0 CM1 AIER PRCR CM2 WDTS WDC RMAD0 RMAD1 INT0F XXXX0X00 00XXX0X02 4816 2016 XXXXXX002 XXXXX0002 0416 XX16 000XXXXX2 000000002 000000002 XXXX00002 000000002 000000002 XXXX00002 XXXXX0002 Address Register Symbol After reset Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. X : Undefined Processor mode register 0 Processor mode register 1 System clock control register 0 System clock control register 1 Address match interrupt enable register Protect register Oscillation stop detection register Watchdog timer start register Watchdog timer control register Address match interrupt register 0 Address match interrupt register 1 INT0 input filter select register

Rev.1.00 Oct 20, 2004 page 11 of 222 M16C/1N Group 4. Special Function Registers (SFR) REJ09B0007-0100Z 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 007016 007116 007216 007316 007416 007516 007616 007716 007816 007916 007A16 007B16 007C16 007D16 007E16 007F16 C01WKIC C01ERRIC C0RECIC C0TRMIC KUPIC ADIC S0TIC S0RIC S1TIC S1RIC T1IC TXIC TYIC TZIC CNTR0IC TCINIC TCIC INT3IC INT0IC INT1IC INT2IC XXXXX000 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XX00X0002 XX00X0002 XX00X0002 Address Register Symbol After reset Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. X : Undefined CAN0 wakeup interrupt control register CAN0 state/error interrupt control register CAN0 reception successful interrupt control register CAN0 transmission successful interrupt control register Key input interrupt control register A/D conversion interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer 1 interrupt control register Timer X interrupt control register Timer Y interrupt control register Timer Z interrupt control register CNTR0 interrupt control register TCIN interrupt control register Timer C interrupt control register INT3 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register

Rev.1.00 Oct 20, 2004 page 12 of 222 M16C/1N Group 4. Special Function Registers (SFR) REJ09B0007-0100Z 008016 008116 008216 008316 008416 008516 008616 008716 008816 008916 008A16 008B16 008C16 008D16 008E16 008F16 009016 009116 009216 009316 009416 009516 009616 009716 009816 009916 009A16 009B16 009C16 009D16 009E16 009F16 00A016 00A116 00A216 00A316 00A416 00A516 00A616 00A716 00A816 00A916 00AA16 00AB16 00AC16 00AD16 00AE16 00AF16 00B016 00B116 00B216 00B316 00B416 00B516 00B616 00B716 00B816 00B916 00BA16 00BB16 00BC16 00BD16 00BE16 00BF16 TYZMR PREY TYSC TYPR PUM PREZ TZSC TZPR PRE1 TYZOC TXMR PREX TX TCSS CPSRF TC INTEN KIEN TCC0 TCC1 TM U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON 000000X0 FF16 FF16 FF16 0016 FF16 FF16 FF16 XX16 XX16 XXXXX0002 000000002 FF16 FF16 0016 0XXXXXXX2 XX16 XX16 0016 0016 0XX000002 XXXXXX112 XX16 XX16 0016 XX16 XX16 XX16 0816 XXXX00102 XX16 XX16 0016 XX16 XX16 XX16 0816 XXXX00102 XX16 XX16 X00000002 Address Register Symbol After reset Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. X : Undefined Timer Y, Z mode register Prescaler Y Timer Y secondary Timer Y primary Timer Y, Z waveform output control register Prescaler Z Timer Z secondary Timer Z primary Prescaler 1 Timer 1 Timer Y, Z output control register Timer X mode register Prescaler X Timer X Timer count source set register Clock prescaler reset flag Timer C counter External input enable register Key input enable register Timer C control register 0 Timer C control register 1 Time measurement register UART0 transmit/receive mode register UART0 bit rate generator UART0 transmit buffer register UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 bit rate generator UART1 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 UART1 receive buffer register UART transmit/receive control register 2

Rev.1.00 Oct 20, 2004 page 13 of 222 M16C/1N Group 4. Special Function Registers (SFR) REJ09B0007-0100Z 00C016 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 00EB16 00EC16 00ED16 00EE16 00EF16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA16 00FB16 00FC16 00FD16 00FE16 00FF16 AD ADCON2 ADCON0 ADCON1 DA DACON PD0 PD1 PD2 PD3 PD4 PD5 CIOSR PUR0 PUR1 DRR XX XX16 XXXX00002 00000XXX2 0016 XX16 XXXXX0X02 XX16 XX16 0016 0016 XX16 XX16 XXXXXX002 0016 XX16 XX16 0016 XXXXX0002 XXXXXXX02 00X000002 XXXXX0002 0016 Address Register Symbol After reset Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. X : Undefined A/D register A/D control register 2 A/D control register 0 A/D control register 1 D/A register D/A control register Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P2 register Port P3 register Port P2 direction register Port P3 direction register Port P4 register Port P5 register Port P4 direction register Port P5 direction register CAN0 I/O port select register Pull-up control register 0 Pull-up control register 1 Port P1 drive capacity control register

Rev.1.00 Oct 20, 2004 page 14 of 222 M16C/1N Group 4. Special Function Registers (SFR) REJ09B0007-0100Z 010016 010116 010216 010316 010416 01B016 01B116 01B216 01B316 01B416 01B516 01B616 01B716 01B816 01B916 01BA16 01BB16 01BC16 01BD16 01BE16 01BF16 021516 021616 021716 021816 021916 021A16 021B16 021C16 021D16 021E16 021F16 022016 022116 022216 022316 022416 022516 022616 022716 022816 022916 022A16 022B16 022C16 022D16 022E16 022F16 023016 023116 023216 023316 023416 023516 023616 023716 023816 023916 023A16 023B16 023C16 023D16 023E16 023F16 FMR4 FMR1 FMR0 C0MCTL0 C0MCTL1 C0MCTL2 C0MCTL3 C0MCTL4 C0MCTL5 C0MCTL6 C0MCTL7 C0MCTL8 C0MCTL9 C0MCTL10 C0MCTL11 C0MCTL12 C0MCTL13 C0MCTL14 C0MCTL15 C0CTLR C0STR C0SSTR C0ICR C0IDR C0CONR C0RECR C0TECR 01000000 0000XX0X2 XX0000012 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 X00000012 XX0X00002 0016 X00000012 000016 000016 000016 000016 000016 000016 XX16 XX16 0016 0016 Address Register Symbol After reset Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. Note 2: These registers are available on flash memory versions only. X : Undefined Flash memory control register 4 (Note 2) Flash memory control register 1 (Note 2) Flash memory control register 0 (Note 2) CAN0 message control register 0 CAN0 message control register 1 CAN0 message control register 2 CAN0 message control register 3 CAN0 message control register 4 CAN0 message control register 5 CAN0 message control register 6 CAN0 message control register 7 CAN0 message control register 8 CAN0 message control register 9 CAN0 message control register 10 CAN0 message control register 11 CAN0 message control register 12 CAN0 message control register 13 CAN0 message control register 14 CAN0 message control register 15 CAN0 control register CAN0 status register CAN0 slot status register CAN0 interrupt control register CAN0 extended ID register CAN0 configuration register CAN0 receive error count register CAN0 transmit error count register

Rev.1.00 Oct 20, 2004 page 15 of 222 M16C/1N Group 4. Special Function Registers (SFR) REJ09B0007-0100Z 024016 024116 024216 024316 024416 024516 024616 024716 024816 024916 024A16 024B16 024C16 024D16 024E16 024F16 025016 025116 025216 025316 025416 025516 025616 025716 025816 025916 025A16 025B16 025C16 025D16 025E16 025F16 026016 026116 026216 026316 026416 026516 026616 026716 026816 026916 026A16 026B16 026C16 026D16 026E16 026F16 027016 027116 027216 027316 027416 027516 027616 027716 027816 027916 027A16 027B16 027C16 027D16 027E16 027F16 C0AFS CCLKR XX16 XX16 X000XXXX2 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 Address Register Symbol After reset Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. X : Undefined CAN0 acceptance filter support register CAN0 clock select register CAN0 slot 0: Identifier / DLC CAN0 slot 0: Data Field CAN0 slot 0: Time Stamp CAN0 slot 1: Identifier / DLC CAN0 slot 1: Data Field CAN0 slot 1: Time Stamp

Rev.1.00 Oct 20, 2004 page 16 of 222 M16C/1N Group 4. Special Function Registers (SFR) REJ09B0007-0100Z 028016 028116 028216 028316 028416 028516 028616 028716 028816 028916 028A16 028B16 028C16 028D16 028E16 028F16 029016 029116 029216 029316 029416 029516 029616 029716 029816 029916 029A16 029B16 029C16 029D16 029E16 029F16 02A016 02A116 02A216 02A316 02A416 02A516 02A616 02A716 02A816 02A916 02AA16 02AB16 02AC16 02AD16 02AE16 02AF16 02B016 02B116 02B216 02B316 02B416 02B516 02B616 02B716 02B816 02B916 02BA16 02BB16 02BC16 02BD16 02BE16 02BF16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 Address Register Symbol After reset Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. X : Undefined CAN0 slot 2: Identifier / DLC CAN0 slot 2: Data Field CAN0 slot 2: Time Stamp CAN0 slot 3: Identifier / DLC CAN0 slot 3: Data Field CAN0 slot 3: Time Stamp CAN0 slot 4: Identifier / DLC CAN0 slot 4: Data Field CAN0 slot 4: Time Stamp CAN0 slot 5: Identifier / DLC CAN0 slot 5: Data Field CAN0 slot 5: Time Stamp

Rev.1.00 Oct 20, 2004 page 17 of 222 M16C/1N Group 4. Special Function Registers (SFR) REJ09B0007-0100Z 02C016 02C116 02C216 02C316 02C416 02C516 02C616 02C716 02C816 02C916 02CA16 02CB16 02CC16 02CD16 02CE16 02CF16 02D016 02D116 02D216 02D316 02D416 02D516 02D616 02D716 02D816 02D916 02DA16 02DB16 02DC16 02DD16 02DE16 02DF16 02E016 02E116 02E216 02E316 02E416 02E516 02E616 02E716 02E816 02E916 02EA16 02EB16 02EC16 02ED16 02EE16 02EF16 02F016 02F116 02F216 02F316 02F416 02F516 02F616 02F716 02F816 02F916 02FA16 02FB16 02FC16 02FD16 02FE16 02FF16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 Address Register Symbol After reset Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. X : Undefined CAN0 slot 6: Identifier / DLC CAN0 slot 6: Data Field CAN0 slot 6: Time Stamp CAN0 slot 7: Identifier / DLC CAN0 slot 7: Data Field CAN0 slot 7: Time Stamp CAN0 slot 8: Identifier / DLC CAN0 slot 8: Data Field CAN0 slot 8: Time Stamp CAN0 slot 9: Identifier / DLC CAN0 slot 9: Data Field CAN0 slot 9: Time Stamp

Rev.1.00 Oct 20, 2004 page 18 of 222 M16C/1N Group 4. Special Function Registers (SFR) REJ09B0007-0100Z 030016 030116 030216 030316 030416 030516 030616 030716 030816 030916 030A16 030B16 030C16 030D16 030E16 030F16 031016 031116 031216 031316 031416 031516 031616 031716 031816 031916 031A16 031B16 031C16 031D16 031E16 031F16 032016 032116 032216 032316 032416 032516 032616 032716 032816 032916 032A16 032B16 032C16 032D16 032E16 032F16 033016 033116 033216 033316 033416 033516 033616 033716 033816 033916 033A16 033B16 033C16 033D16 033E16 033F16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 Address Register Symbol After reset Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. X : Undefined CAN0 slot 10: Identifier / DLC CAN0 slot 10: Data Field CAN0 slot 10: Time Stamp CAN0 slot 11: Identifier / DLC CAN0 slot 11: Data Field CAN0 slot 11: Time Stamp CAN0 slot 12: Identifier / DLC CAN0 slot 12: Data Field CAN0 slot 12: Time Stamp CAN0 slot 13: Identifier / DLC CAN0 slot 13: Data Field CAN0 slot 13: Time Stamp

Rev.1.00 Oct 20, 2004 page 19 of 222 M16C/1N Group 4. Special Function Registers (SFR) REJ09B0007-0100Z 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16 037016 037116 03B416 03B516 03B616 03B716 03B816 03B916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16 C0GMR C0LMAR C0LMBR XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 Address Register Symbol After reset Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. X : Undefined CAN0 slot 14: Identifier / DLC CAN0 slot 14: Data Field CAN0 slot 14: Time Stamp CAN0 slot 15: Identifier / DLC CAN0 slot 15: Data Field CAN0 slot 15: Time Stamp CAN0 Global mask CAN0 local mask A CAN0 local mask B

Rev.1.00 Oct 20, 2004 page 20 of 222 M16C/1N Group 5. Reset REJ09B0007-0100Z 5. Reset There are two types of resets; hardware and software. In both cases, operation is the same after the reset.

5.1 Hardware Reset

A reset is applied using the RESET pin. When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level "L" (0.2VCC max.). When the RESET pin level is then returned to the "H" level, the reset status is cancelled and program execution resumes from the address in the reset vector table. Since the value of RAM is indeterminate when power is applied, the initial values must be set. Also, if a reset signal is input during write to RAM, the access to the RAM will be interrupted. Consequently, the value of the RAM being written may change to an unintended value due to the interruption. Note 1: M16C/1N group is delayed more than 2ms until the execution of the program after reset clear in comparison with M16C/10 group products.

5.1.1 When the power supply is stable

(1)Apply a "L" signal to the RESET pin for at least 200µs. (2)Apply a "H" signal to the RESET pin.

5.1.2 Power on

(1)Apply a "L" signal to the RESET pin. (2)Let the power supply voltage increase until it meets the recommended operating condition. (3)Wait for td(P-R) + 200µs or more until the internal power supply stabilizes. (4)Apply a "H" signal to the RESET pin.

Rev.1.00 Oct 20, 2004 page 22 of 222 M16C/1N Group 5. Reset REJ09B0007-0100Z

5.2 Software Reset

Writing "1" to bit 3 of the processor mode register 0 (address 0004 16) applies a (software) reset to the microcomputer. Set the PM03 bit to "1" after selecting on-chip oscillator for CPU's operating clock source. A software reset has almost the same effect as a hardware reset. The contents of internal RAM are preserved. Figure 5.4 shows the processor mode register 0 and 1. Figure 5.4 Processor mode register 0 and 1 b7 b6 b5 b4 b3 b2 b1 b0 Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. The device is reset when this bit is set to "1". The value of this bit is "0" when read. Note 1: Set bit 1 of the protect register (address 000A 16) to "1" when writing new values to this register. b7 b6 b5 b4 b3 b2 b1 b0 PM12 WDT interrupt/reset switching bit DATAROM area access bit (Note 2) Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. 0 : Watchdog timer interrupt 1 : Reset (Note 3) Processor mode register 1 (Note 1) Note 1: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register. Note 2: This bit is valid for the flash memory version. For the mask ROM version, this bit must be set to "0". Note 3: After setting this bit to "1", can not change to "0" by software. PM17 Wait bit 0 : No wait 1 : Wait 0 : Disabled 1 : Enabled Processor mode register 0 (Note 1) Reserved bit PM03 Software reset bit Set to "0" PM10 Reserved bit Set to "0" Symbol PM0 Address 000416 When reset XXXX0X002 Symbol PM1 Address 000516 When reset 00XXX0X02 RW RW RW RW RW RW RW RW FunctionBit nameBit symbol FunctionBit nameBit symbol

Rev.1.00 Oct 20, 2004 page 23 of 222 M16C/1N Group 6. Clock Generation Circuit REJ09B0007-0100Z Main clock oscillation circuit Sub clock oscillation circuit On-chip oscillator circuit Use of clock • CPU’s operating clock source • CPU’s operating clock source • CPU’s operating clock source

• Internal peripheral unit’s • Timer 1/X/Y/Z’s count • Internal peripheral unit’s operating clock source clock source operating clock source
• Timer Y’s count clock source Usable oscillator • Ceramic oscillator • Crystal oscillator – connectable (Note 1) • Crystal oscillator Oscillator connect pins X IN, XOUT XCIN, XCOUT None (has internal pins) Oscillation stop/restart functionAvailable Available Available Oscillator status immediately Oscillating Stopped Oscillating after reset Other Externally generated clock can be input – 6. Clock Generation Circuit The clock regeneration circuit contains three circuits as follows: - Main clock oscillation circuit - Sub clock oscillation circuit - On-chip oscillator Table 6.1 lists Clock Generation Circuit Specifications. Figure 6.1 shows a Clock Generation Circuit. Figure C32 block diagram. Table 6.1 Main clock, sub-clock, and on-chip oscillator circuits Note 1: When not using the main clock generating circuit, pull up the X IN pin and leave the XOUT pin open. Also, set the main clock stop bit (bit 5 at address 000616) to "1" (stop).

Rev.1.00 Oct 20, 2004 page 24 of 222 M16C/1N Group 6. Clock Generation Circuit REJ09B0007-0100Z Sub clock CM0i : Bit i at address 000616 CM1i : Bit i at address 000716 CM2i : Bit i at address 000C16 WDCi : Bit i at address 000F16 CM10 "1" Write signal WAIT instruction Main clock Interrupt request level judgment output RESET Software reset Details of divider CM04 fC32 XCIN XCOUT QS R QS R XOUT CM05 fC XIN 1/2 1/2 1/2 1/2 CM06=0 CM17, CM16=00 CM06=0 CM17, CM16=01 CM06=0 CM17, CM16=10 CM06=1 CM06=0 CM17, CM16=11 d a b c CM20 Main clock switching circuit On-chip oscillator oscillation circuit Oscillation stop detection CM22 By CCLK4, 5, 6 fC CM07=0 fAD fCAN0 a d f32 cb BCLK CM07=1 CM02 fRING Divider Divider fMAIN Figure 6.1 Block diagram of clock generating circuit

Rev.1.00 Oct 20, 2004 page 25 of 222 M16C/1N Group 6. Clock Generation Circuit REJ09B0007-0100Z Note 1:Set bit 0 of the protect register (address 000A16) to "1" before writing to this register. Note 2:fc32 is not included. Do not set to "1" when using low-speed, low power dissipation or on-chip oscillator mode. Note 3:Changes to "1" when shifting to stop mode. Note 4:This bit is used to stop the main clock when placing the device in a low-power mode. If you want to operate with XIN after exiting from the stop mode, set this bit to "0". When operating with a self-excited oscillator, set the system clock select bit (CM07) to "1" before setting this bit to "1". Note 5:When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. Note 6:If this bit is set to "1", XOUT turns "H". The built-in feedback resistor remains being ON, so XIN turns pulled up to XOUT ("H") via the feedback resistor. Note 7:This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Note 8:Set port Xc select bit (CM04) to "1" before setting this bit to "1". Can not write to both bits at the same time. Note 1:Set bit 0 of the protect register (address 000A16) to "1" before writing to this register. Note 2:The mode of power control cannot be shifted on the stop mode directly from the on-chip oscillator. If this bit is set to "1", XOUT turns "H", and the built-in feedback resistor is ineffective. Note 3:This bit can be set to "1" only when both the main clock switch bit (CM22) and clock monitor bit (CM23) are set to "0". Moreover, this bit is automatically set to "0" if the main clock switch bit (CM22) is set to "1". Note 4:This bit changes to "1" when shifting from high-speed/middle-speed mode to stop mode or at reset. When shifting from low- speed/low power dissipation mode to stop mode, the value before stop mode is retained. Note 5:Can be selected when bit 6 of the system clock control register 0 (address 000616) is "0". If "1", division mode is fixed at 8. b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 000 CM07 CM05 CM04 CM03 CM02 CM06 Reserved bit WAIT peripheral function clock stop bit XCIN-XCOUT drive capacity select bit (Note 3) Port XC select bit System clock select bit (Note 8) Main clock division select bit 0 (Note 7) Main clock (XIN-XOUT) stop bit (Note 4,5,6) 0 : Do not stop peripheral function clock in wait mode 1 : Stop peripheral function clock in wait mode (Note 2) 0 : LOW 1 : HIGH All clock stop control bit (Note 2) 0 : Clock on 1 : All clocks off (stop mode) 0 : I/O port 1 : XCIN-XCOUT generation 0 : On 1 : Off 0 : CM16 and CM17 valid 1 : Division by 8 mode Set to "0" Reserved bit Set to "0" 0 : XIN, XOUT 1 : XCIN, XCOUT CM10 On-chip oscillation stop bit 0 : Oscillation enabled 1 : Oscillation stopped (Note 3) CM14 XIN-XOUT drive capacity select bit (Note 4) 0 : LOW 1 : HIGH CM15 Main clock division select bit 1 (Note 5) CM16 CM17 System clock control register 0 (Note 1) Symbol CM0 Address 000616 When reset 010010002 RW RW RW RW RW RW RW RW FunctionBit nameBit symbol System clock control register 1 (Note 1) Symbol CM1 Address 000716 When reset 001000002 RW RW RW RW RW RW FunctionBit nameBit symbol 0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode b7 b6 Figure 6.2 System clock control registers 0 and 1

Rev.1.00 Oct 20, 2004 page 27 of 222 M16C/1N Group 6. Clock Generation Circuit REJ09B0007-0100Z Figure 6.5 CAN0 clock select register b7 b6 b5 b4 b3 b2 b1 b0 CCLK4 CCLK5 CCLK6 CAN0 clock select bit Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. Note 1: Set bit 0 of the protect register (address 000A 16) to "1" before writing in this register. Note 2: Change the register value only when the CAN module is in Reset/Initialization mode (the bit 0 of the CAN Control Register (address 023016) is "1"). Reserved bit CAN0 clock select register (Note 1, 2) Symbol CCLKR Address 025F16 When reset X000XXXX2 RW RW RW RW RW FunctionBit nameBit symbol 0 0 0 : No division mode 0 0 1 : Division by 2 mode 0 1 0 : Division by 4 mode 0 1 1 : Division by 8 mode 1 0 0 : Division by 16 mode 1 0 1 : Inhibited 1 1 0 : Inhibited 1 1 1 : Inhibited Set to "0" b6 b5 b4

Rev.1.00 Oct 20, 2004 page 28 of 222 M16C/1N Group 6. Clock Generation Circuit REJ09B0007-0100Z The following describes the clocks generated by the clock generation circuit.

6.1 Main Clock

The main clock is generated by the main clock oscillation circuit. After reset, oscillation starts. The clock can be stopped using the main clock stop bit (bit 5 at address 0006 16). Stopping the clock reduces the power dissipation. After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the X OUT pin can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the XOUT pin reduces the power dissipation. This bit changes to "1" when shifting from high- speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissi- pation mode to stop mode, the value before stop mode is retained. Figure 6.5 shows the examples of main clock connection circuit. XIN XOUT Externally derived clock Open Vcc Vss Microcomputer (Built-in feedback resistor) XIN XOUT Rd CIN COUT (Note 1) Microcomputer (Built-in feedback resistor) External ceramic oscillator External clock input Note 1: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer’s data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between X IN and XOUT following the instruction. Figure 6.6 Examples of main clock connection circuit

Rev.1.00 Oct 20, 2004 page 29 of 222 M16C/1N Group 6. Clock Generation Circuit REJ09B0007-0100Z Microcomputer (Built-in feedback resistor) XCIN XCOUT Externally derived clock Open Vcc Vss Microcomputer (Built-in feedback resistor) XCIN XCOUT (Note 1) CCIN CCOUT RCd Note 1: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable.

6.2 Sub-clock

The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset. After oscillation is started using the port Xc select bit (bit 4 at address 0006 16), the sub-clock can be selected as BCLK by using the system clock select bit (bit 7 at address 0006 16). However, be sure that the sub-clock oscillation has fully stabilized before switching. After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the X COUT pin can be reduced using the X CIN-XCOUT drive capacity select bit (bit 3 at address 0006 16). Reducing the drive capacity of the X COUT pin reduces the power dissipation. This bit changes to "1" when shifting to stop mode and at a reset. Figure 6.7 shows the examples of sub-clock connection circuit. Figure 6.7 Examples of sub-clock connection circuit

6.3 On-chip Oscillator Clock

This clock by supplied by a on-chip oscillator. The oscillation of the on-ship oscillator can be used as BCLK by setting the main clock selected bit (bit 2 at address 000C16. Lower power consumption can be realized because the oscillating frequency of the on-chip oscillator is much lower compared to that of XIN. The frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. The application products must be designed with sufficient margin to accommodate the frequency range.

Rev.1.00 Oct 20, 2004 page 30 of 222 M16C/1N Group 6. Clock Generation Circuit REJ09B0007-0100Z

6.4 CPU Clock and Peripheral Function Clock

6.4.1 BCLK

The BCLK is the clock that drives the CPU. The clock source for BCLK is as follows: (1) the clock derived by dividing the main clock by 1, 2, 4, 8, or 16, (2) fc, or (3) the clock derived by dividing the clock supplied by the on-chip oscillator circuit (f RING) by 1, 2, 4, 8 or 16. After reset, the BCLK is derived by dividing the fRING by 8. The main clock division select bit 0 (bit 6 at address 000616) changes to "1" when shifting from high- speed/medium-speed mode to stop mode and at reset. When shifting from low-speed/low power dis- sipation mode to stop mode, the value before stop mode is retained.

6.4.2 Peripheral Function Clock

6.4.2.1 f 1, f8, f32 The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at address 0006 16) to "1" and then executing a WAIT instruction. 6.4.2.2 fAD This clock has the same frequency as the main clock and is used in A/D conversion. 6.4.2.3 fCAN0 This clock is derived by dividing the main clock by 1, 2, 4, 8, 16 by setting the CAN0 clock select register. It is used for the corresponding CAN module. This clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at address 0006 16) to "1" and then executing a WAIT instruction. 6.4.2.4 fC32 This clock is derived by dividing the sub-clock by 32. It is used for the timer 1, timer X, timer Y and timer X counts. 6.4.2.5 f C This clock has the same frequency as the sub-clock. It is used for BCLK and for the watchdog timer. 6.4.3 f RING This clock is supplied by the on-chip oscillator circuit. In the on-chip oscillator mode, the clock divided by the division ratio selected with the main clock division select bit 0 and bit 1 (bit 6 at address 000616, and bit 6 and bit 7 at address 000716) is supplied as BCLK. Immediately after reset, 8 divisions of this clock is supplied as BCLK. The on-chip oscillator oscillation can be set to BCLK when oscillation stop is detected or with the main clock switching bit (bit 2 at address 000C 16).

Rev.1.00 Oct 20, 2004 page 31 of 222 M16C/1N Group 6. Clock Generation Circuit REJ09B0007-0100Z

6.5 Power Control

There are three power control modes. All modes other than wait and stop modes are referred to as normal operation mode.

6.5.1 Normal Operating Modes

Normal operation mode is further separated into five modes. In normal operation mode, the CPU clock and the peripheral function clock are supplied to operate the CPU and the peripheral function. Power consumption control is enabled by controlling the CPU clock frequency. The higher the CPU clock frequency, the more processing power increases. The lower the CPU clock frequency, the more power consumption decreased. When unnecessary oscillator circuits stop, power consumption is fur- ther reduced. Before the clock sources for the CPU clock can be switched over, the new clock source after switching needs to be stabilized and oscillated. If the new clock source is the main clock, allow sufficient wait time in a program until an oscillation is stabilized. When the clock source for the CPU clock is changed from the one-chip oscillator to the main clock, change the operation mode to the medium-speed mode (divided-by-8 mode) after the clock was divided by 8 in on-chip oscillator mode.

6.5.1.1 High-speed Mode

The main clock divided-by-1 (undivided) provides the CPU clock. The peripheral functions operate on the clocks specified for each respective function.

6.5.1.2 Medium-speed Mode

The main clock divided-by-2, -4, -8 or -16 provides the CPU clock. The peripheral functions oper- ated on the clocks specified for each respective function. The main clock must be oscillating stably before transferring from the main clock divided-by-8 to divided-by-1, -2 or -4 and the sub-clock must be oscillating stably before transferring to low-speed or lower power-dissipation mode.

6.5.1.3 Low-speed Mode

The sub-clock provides the CPU clock. The peripheral functions operate on the clocks specified for each respective function. Note that oscillation of both the main and sub-clocks must have stabi- lized before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub-clock status. Therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled.

6.5.1.4 Low Power-dissipation Mode

In this mode, the main clock is turned off after being placed in low speed mode. The sub-clock provides the CPU clock. Only the peripheral functions for which the sub-clock was selected as the count source continue to operate.

6.5.1.5 On-chip Oscillator Mode

The on-chip oscillator clock divided-by-1(undivided) -2,-4,-8, or -16 provides the CPU clock. The on-chip oscillator clock is also the clock source for the peripheral function clocks. The higher divi- sion and the main clock is turned off after being placed in on-chip oscillator mode, power consump- tion is reduced further. Table 6.2 lists the setting and mode of clock associated bit.

Rev.1.00 Oct 20, 2004 page 32 of 222 M16C/1N Group 6. Clock Generation Circuit REJ09B0007-0100Z Table 6.2 Setting and mode of clock associated bit Mode CM2 register CM1 register CM0 regiser CM22 CM17, CM16 CM07 CM06 CM05 CM04 0High-speed mode 00 2 000 _ 0Divide-by-2 012 000 _ 0Divide-by-4 102 000 _ 0Divide-by-8 _ 010 _ 0Divide-by-16 112 000 _ 0Low-speed mode _ 1 _ 01 0Low power-dissipation mode _ 1 _ 11 1Undivided Medium-speed mode On-chip oscillator mode 002 00 __ 1Divide-by-2 012 00 __ 1Divide-by-4 102 00 __ 1Divide-by-8 _ 01 __ 1Divide-by-16 112 00 __

Rev.1.00 Oct 20, 2004 page 33 of 222 M16C/1N Group 6. Clock Generation Circuit REJ09B0007-0100Z Pin States Port Retains status before stop mode

6.5.3 Stop Mode

Writing "1" to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the micro- computer enters stop mode. In stop mode, the content of the internal RAM is retained provided that V CC remains above 2V. Because the oscillation of BCLK, f1 to f32, fc, fc32, fAD and fCAN0 stop in stop mode, peripheral func- tions such as the A/D converter and watchdog timer do not function. However, timer X operate pro- vided that the event counter mode is set to an external pulse, and UART0 and UART1 function pro- vided an external clock is selected. Table 6.4 lists the status of the ports in stop mode. Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled, and the priority level of the interrupt which is not used to cancel must have been changed to 0 before shifting to stop mode. If returning by an interrupt, that interrupt routine is executed. If only a hardware reset is used to cancel stop mode, change the priority level of all interrupt to 0, then shift to stop mode. When shifting from high-speed/medium-speed mode to stop mode or at a reset, the main clock divi- sion select bit 0 (bit 6 at address 0006 16) is set to "1". When shifting from low-speed/low power dissi- pation mode to stop mode, the value before stop mode is retained. Stop mode must not be use while operating in on-chip oscillator mode.

6.5.2 Wait Mode

When a WAIT instruction is executed, BCLK stops and the microcomputer enters wait mode. In this mode, oscillation continues but BCLKand watchdog timer stop. Writing "1" to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. Table 6.3 lists the status of the ports in wait mode. Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, the microcomputer restarts using as BCLK, the clock that had been selected when the WAIT instruc- tion was executed. Table 6.4 Port status during stop mode Table 6.3 Port status during wait mode Pin States Port Retains status before wait mode

Rev.1.00 Oct 20, 2004 page 35 of 222 M16C/1N Group 6. Clock Generation Circuit REJ09B0007-0100Z CM07="0" (Note 1) CM06="1" CM04="0" CM04="1" (Notes 1, 3) CM04="0" BCLK: f(XIN)/8 CM07="0" CM06="1" CM22="0" CM06="1" BCLK: f(RING)/8 BCLK: f(RING)/8 CM07="0" CM06="1" CM05="1" CM22="1" CM07="0" CM06="1" CM05="0" CM22="1" BCLK: f(RING)/2BCLK: f(RING) CM07="0" CM06="0" CM05="1" CM22="1" CM16="0" CM17="0" CM22="1" CM22="0" (Note 1) BCLK: f(RING)/16BCLK: f(RING)/4 Transition of normal operation mode Main clock is oscillating Sub clock is stopped Medium-speed mode (divided-by-8 mode) Low-speed modeHigh-speed mode Main clock is oscillating Sub clock is stopped Main clock is stopped Sub clock is oscillating Main clock is oscillating Sub clock is oscillating Low power dissipation mode BCLK : f(XIN)/2 Medium-speed mode (divided-by-2 mode) BCLK : f(XIN)/16 Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/4 Medium-speed mode (divided-by-4 mode) BCLK : f(XIN) CM17 = "0" CM16 = "0" BCLK : f(XIN)/8 Medium-speed mode (divided-by-8 mode) CM07 = "0" CM06 = "1" High-speed mode BCLK : f(XIN)/2 Medium-speed mod (divided-by-2 mode) BCLK : f(XIN)/16 Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/4 Medium-speed mode (divided-by-4 mode) BCLK : f(XIN) BCLK : f(XCIN) CM07 = "1" CM06 = "1" BCLK : f(XCIN) CM07 = "1" CM06 = "1" Main clock is oscillating Sub clock is oscillating CM07 = "0" (Notes 1, 3) CM07 = "1" CM06 = "1" (Note 2, 5) CM07 = "0" (Note 1) CM06 = "0" (Note 3) CM04 = "1" CM06 = "0" (Notes 1, 3) Main clock is oscillating Sub clock is stopped On-chip oscillator mode (divided-by-8 mode) Main clock is stopped Sub clock is stopped On-chip oscillator mode 8-division mode 1-division mode (Note 3) 2-division mode (Note 3) 16-division mode (Note 3)4-division mode (Note 3) CM07="0" CM06="0" CM05="1" CM22="1" CM16="1" CM17="0" CM07="0" CM06="0" CM05="1" CM22="1" CM16="1" CM17="1" CM07="0" CM06="0" CM05="1" CM22="1" CM16="0" CM17="1" Note 1:Switch clock after oscillation of main clock is sufficiently stable. Note 2:Switch clock after oscillation of sub clock is sufficiently stable. Note 3:Change CM17 and CM16 before changing CM06. Note 4:Transit in accordance with arrow. Note 5: Before switching BCLK to other from the main clock, divide the main clock by 8 for safety purposes to switch BCLK to the main clock again. Figure 6.9 State transition in normal operation mode

Rev.1.00 Oct 20, 2004 page 36 of 222 M16C/1N Group 6. Clock Generation Circuit REJ09B0007-0100Z

6.6 Oscillation Stop Detection Function

The oscillation stop detection function detects abnormal stopping of the main clock by causes such as opening and shorting of the X IN oscillation circuit. When oscillation stop is detected, an oscillation stop detection interrupt is issued. When an oscillation stop detection interrupt is issued, the on-chip oscillator in the microcomputer operates automatically and is used as the main clock in place of the X IN clock. This allows interrupt processing. The oscillation stop detection function can be enabled/disabled with bit 0 and bit 1 of the oscillation stop detection register. When this bit is set to "11 2", the function is enabled. After the reset is released, the oscillation stop detection function becomes disabled because the bit value is "002". Table 6.5 lists the specification of oscillation stop detection function, Figure 6.10 shows a configuration diagram of the oscillation stop detection circuit and Figure 6.11 shows the configuration of the oscillation stop detection register. Table 6.5 Specification overview of the oscillation stop detection function Item Specification Oscillation stop detectable clock and X IN ≥ 2 MHz frequency bandwidth Enabling condition for oscillation stop When the oscillation stop detection bit (bit 0 at address 000C 16) detection function and the oscillation stop detection interrupt enable bit (bit 1 at address 000C16) are set to "1" Operation at oscillation stop detection • Oscillation stop detection interrupt occurs Notes on STOP mode, low power Before stopping the main clock (X IN-XOUT), set the dissipation mode, and on-chip oscillation stop detection enable bit to "0" to disable the oscillator mode oscillation stop detection function. Enable main clock IN-XOUT) oscillation and after the oscillation stabilizes, set the bit to "1" again. Notes on WAIT mode If the peripheral function clock is stopped in WAIT mode with the WAIT mode peripheral function clock stop bit (bit 2 at address 0006 16), oscillation stop will be detected. Do not stop the peripheral function clock in WAIT mode.

Rev.1.00 Oct 20, 2004 page 38 of 222 M16C/1N Group 6. Clock Generation Circuit REJ09B0007-0100Z

6.6.1 Oscillation Stop Detection Bit (CM20)

You can start the oscillation stop detection by setting this bit to "1" and CM21=1 (oscillation stop detection interrupt enabled). The detection is not executed when this bit is set to "0" or in reset status. Be sure to set this bit to "0" before setting for the stop-mode. Set this bit again to "1" after release from stop-mode. Set this bit to "0" also before setting the main clock stop bit (bit 5 at address 0006 16) to "1". Do not set this bit to "1" if the frequency of XIN is lower than 2 MHz. An oscillation stop is detected if CM02="1" (peripheral function clock has been set for stop in wait mode) and the mode is shifted to wait.

6.6.2 Oscillation Stop Detection Interrupt Enable Bit (CM21)

When CM20=1 and CM21=1, an oscillation stop detection interrupt is generated if an abnormal stop of X IN is detected. The on-chip oscillator starts operation instead of the XIN clock which stopped abnor- mally. The operation goes further with the main clock supplied from the on-chip oscillator. For the oscillation stop detection interrupt, judgment on the interrupt condition is necessary, because this interrupt shares the vector table with watchdog timer interrupt. Figure 6.12 shows flow of the judgment with oscillation stop detection interrupt processing program.

6.6.3 Main Clock Switch Bit (CM22)

When setting this bit to "1", the on-chip oscillator is selected as main clock. At this time, the on-chip oscillator starts simultaneously if it has been stopped (CM14=1). This bit is cleared only when CM23 is "0" (when X IN is oscillating). If an oscillation stop is detected while both CM20 and CM21 are "1", this bit automatically switches to "1". When this bit is set to "1", the on-chip oscillation stop bit (bit 4 at address 0007 16) is automatically set to "0".

6.6.4 Clock Monitor Bit (CM23)

You can see the operation status of the XIN clock. When this bit is "0", XIN is operating correctly. You can check the oscillation status of XIN when an oscillation stop detection interrupt is generated or after reset. When oscillation stop detection is invalid (CM20="0"), the clock monitor bit is "0".

Rev.1.00 Oct 20, 2004 page 40 of 222 M16C/1N Group 7. Protection REJ09B0007-0100Z 7. Protection The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 7.1 shows the protect register. The values in the processor mode register 0 (address 0004 16), processor mode register 1 (address 000516), system clock control reg- ister 0 (address 0006 16), system clock control register 1 (address 0007 16) and port P0 direction register (address 00E216) can only be changed when the respective bit in the protect register is set to "1". There- fore, important outputs can be allocated to port P0. If, after "1" (write-enabled) has been written to bit "enables writing to port P0 direction register" (bit 2 at address 000A 16), a value is written to any address, the bit automatically reverts to "0" (write-inhibited). Make sure no interrupts will generate between the instruction in which the PRC2 bit to "1" and the next instruction. The system clock control registers 0 and 1 and oscillation stop detection register write-enable bit (bit 0 at address 000A 16) and processor mode register 0 and 1 write-enable bit (bit 1 at address 000A16) do not automatically return to "0" after a value has been written to an address. The program must therefore be written to return these bits to "0". b7 b6 b5 b4 b3 b2 b1 b0 Enables writing to system clock control registers 0 and 1 (addresses 0006 16 and 000716), oscillation stop detection register (address 000C16) and CAN0 clock select register (address 025F 16) Enables writing to processor mode registers 0 and 1 (addresses 000416 and 000516) Enables writing to port P0 direction register (address 00E216) and CAN0 I/O port select register (address 00F816) (Note 1) Note 1: Writing a value to an address after "1" is written to this bit returns the bit to "0". Other bits do not automatically return to "0" and they must therefore be reset by the program. Protect register Symbol PRCR Address 000A16 When reset XXXXX0002 RW RW RW RW RW FunctionBit nameBit symbol PRC0 0 : Write-inhibited 1 : Write-enabled PRC1 0 : Write-inhibited 1 : Write-enabled PRC2 0 : Write-inhibited 1 : Write-enabled Reserved bit Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. Set to "0" 000 Figure 7.1 Protect register

Rev.1.00 Oct 20, 2004 page 41 of 222 M16C/1N Group 8. Processor Mode REJ09B0007-0100Z 8. Processor Mode

8.1 Types of Processor Mode

The processor mode is single-chip mode. Table 8.1 lists features of processor mode. Figure 8.1 shows the processor mode register 0 and 1. Figure 8.1 Processor mode register 0 and 1 b7 b6 b5 b4 b3 b2 b1 b0 Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. The device is reset when this bit is set to "1". The value of this bit is "0" when read. Note 1: Set bit 1 of the protect register (address 000A 16) to "1" when writing new values to this register. b7 b6 b5 b4 b3 b2 b1 b0 PM12 WDT interrupt/reset switching bit DATAROM area access bit (Note 2) Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. 0 : Watchdog timer interrupt 1 : Reset (Note 3) Processor mode register 1 (Note 1) Note 1: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register. Note 2: This bit is valid for the flash memory version. For the mask ROM version, this bit must be set to "0". Note 3: After setting this bit to "1", can not change to "0" by software. PM17 Wait bit 0 : No wait 1 : Wait 0 : Disabled 1 : Enabled Processor mode register 0 (Note 1) Reserved bit PM03 Software reset bit Set to "0" PM10 Reserved bit Set to "0" Symbol PM0 Address 000416 When reset XXXX0X002 Symbol PM1 Address 000516 When reset 00XXX0X02 RW RW RW RW RW RW RW RW FunctionBit nameBit symbol FunctionBit nameBit symbol Table 8.1 Features of processor mode Processor mode Access space Pins to which I/O ports are assigned Single chip mode SFR, Internal RAM, Internal ROM All pins are I/O ports or peripheral function I/O pins.

Rev.1.00 Oct 20, 2004 page 42 of 222 M16C/1N Group 9. Bus Control REJ09B0007-0100Z 9. Bus Control During access, the memory areas (ROM, RAM, FLASH, etc.) and the SFR area have different bus cycles. The memory areas can be accessed in one cycle of the CPU operation clock BCLK. The SFR area can be accessed in two cycles of BCLK. Software wait states can be inserted to the memory areas by using the PM17 bit of the processor mode register 1 (bit 7 at address 0005 16) (Note 1). When the PM17 bit is set to "0", the memory areas are accessed in one cycle of BCLK. When the PM17 bit is set to "1", the memory areas are accessed in two cycles of BCLK. The PM17 bit is "0" after the reset status is cancelled. The SFR area is not influenced by the PM17 bit and is always accessed in two cycles of BCLK. The Table 9.1 lists bus cycle for access areas. Figure 9.1 shows SFR area and memory areas. Note 1: When rewriting the processor mode register 1, set the PRC1 bit of the protect register (bit 1 at address 000A 16) to "1". 0000016 XXXXX16 FFFFF16 0040016 YYYYY16 Internal ROM area SFR area (For details, refer to 4. SFR) Internal RAM area SFR area Memory area Table 9.1 Bus cycle for access areas Figure 9.1 SFR area and memory areas Area SFR Internal ROM/RAM PM17 Bus cycle

2 BCLK cycles

1 BCLK cycle

12 BCLK cycles

Rev.1.00 Oct 20, 2004 page 43 of 222 M16C/1N Group 9. Bus Control REJ09B0007-0100Z The memory areas and the SFR area also have different bus widths. The memory areas have a 16-bit bus width, while the SFR area has an 8-bit bus width. Consequently, different operations are used when the areas are accessed in word (16 bits) units. Table 9.2 lists access unit and bus operation. Space Even address byte access BCLK Data BCLK BCLK BCLK BCLK BCLK BCLK BCLK Address SFR ROM/RAM (No wait setting) Even Odd Data Data Data Data Word Data Data Data Data Data Data Data Odd Odd Odd+1 Odd Odd+1 Even Even Even+1 Even/even+1 Data Address Data Address Data Address Data Address Data Address Data Address Data Address Odd address byte access Even address word access Odd address word access Table 9.2 Access unit and bus operation

Rev.1.00 Oct 20, 2004 page 44 of 222 M16C/1N Group 10. Interrupt REJ09B0007-0100Z Reset DBC Oscillation stop detection/watchdog timer Single step Address matched Special Peripheral I/O (Note 1) Figure 10.1 Classification of interrupts Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Software Hardware Interrupt Note 1: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system. 10. Interrupt

10.1 Overview of Interrupt

10.1.1 Type of Interrupts

Figure 10.1 lists the types of interrupts.

• Maskable interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level. (Non-maskable interrupt) (Non-maskable interrupt)

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10.1.2 Software Interrupts

A software interrupt is generated when an instruction is executed. The software interrupts are non- maskable interrupts.

10.1.2.1 Undefined Instruction Interrupt

The undefined instruction interrupt is generated when the UND instruction is executed.

10.1.2.2 Overflow Interrupt

The overflow interrupt is generated when the INTO instruction is executed with the overflow flag (O flag) set to "1". The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB

10.1.2.3 BRK Interrupt

A BRK interrupt is generated when the BRK instruction is executed.

10.1.2.4 INT instruction Interrupt

An INT instruction interrupt is generated when the INT instruction is executed. The INT instruction can select the software interrupt numbers 0 to 63. The software interrupt numbers 0 to 31 are assigned to the peripheral function interrupt. Therefore, the microcomputer executes the same interrupt routine when the INT instruction interrupt is executed as when a peripheral function inter- rupt is generated. The stack pointer (SP) used for the INT instruction interrupt is dependent on which software inter- rupt number is involved. So far as software interrupt numbers 0 to 31 are concerned, the microcomputer saves the stack pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to "0" and select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the interrupt routine, the U flag is returned to the state it was before the acceptance of inter- rupt request. So far as software numbers 32 to 63 are concerned, the stack pointer does not make a shift.

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10.1.3 Hardware Interrupts

Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.

10.1.3.1 Special Interrupts

Special interrupts are non-maskable interrupts.

• Reset Reset occurs if an "L" is input to the RESET pin.
• UART0 reception interrupt UART0 reception interrupt occurs when UART0 is received. This interrupt can be enabled with bit 2 of the INT 0 input filter select register (address 001E16). This interrupt is exclusively for the debugger, do not use it in other circumstances.
• DBC interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Oscillation stop detection/watchdog timer interrupt Generated by the oscillation stop detection or watchdog timer.
• Single-step interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag) set to "1", a single-step interrupt occurs after one instruction is executed.
• Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to "1". If an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs.

10.1.3.2 Peripheral I/O Interrupts

A peripheral I/O interrupt is generated by one of built-in peripheral functions. The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.

• CAN0 error interrupt Tis is an interrupt that CAN error generates.
• CAN0 wake up interrupt CAN0 wake up interrupt occurs if a falling edge is input to the CRx pin.
• CAN0 successful reception interrupt This is an interrupt that the CAN reception generates.
• CAN0 successful transmission interrupt This is an interrupt that the CAN transmission generates.
• Key-input interrupt ___ A key-input interrupt occurs if a falling or rising edge is input to the KI pin.
• A/D conversion interrupt This is an interrupt that the A/D converter generates.
• UART0 and UART1 transmission interrupt These are interrupts that the serial I/O transmission generates.
• UART0 and UART1 reception interrupt These are interrupts that the serial I/O reception generates.
• Timer 1 interrupt This is an interrupt that timer 1 generates.

Rev.1.00 Oct 20, 2004 page 47 of 222 M16C/1N Group 10. Interrupt REJ09B0007-0100Z

• Timer X interrupt This is an interrupt that timer X generates.
• Timer Y interrupt This is an interrupt that timer Y generates.
• Timer Z interrupt This is an interrupt that timer Z generates.
• Timer C interrupt This is an interrupt that timer C generates.
• CNTR0 interrupt This interrupt occurs if either a falling edge or a rising edge is input to the CNTR0 pin.
• TCIN interrupt This interrupt occurs if any one of a falling edge, a rising edge or both edges is input to the TCIN pin. This interrupt also occurs with the f RING256.
• INT0 to INT3 interrupt INT0 to INT2 interrupts occur if any one of a falling edge, a rising edge or both edges is input to the INT pin. INT3 interrupt occurs if either a falling edge or both edges is input to the INT pin.

Rev.1.00 Oct 20, 2004 page 48 of 222 M16C/1N Group 10. Interrupt REJ09B0007-0100Z Interrupt source Vector table addresses Remarks Address (L) to address (H) Undefined instruction FFFDC 16 to FFFDF16 Interrupt on UND instruction Overflow FFFE0 16 to FFFE316 Interrupt on INTO instruction BRK instruction FFFE4 16 to FFFE716 If the vector is filled with FF16, program execution starts from the address shown by the vector in the variable vector table Address match FFFE8 16 to FFFEB16 There is an address-matching interrupt enable bit Single step (Note 1) FFFEC 16 to FFFEF16 Do not use Oscillation stop detection/ FFFF016 to FFFF316 Watchdog timer DBC (Note 1) FFFF4 16 to FFFF716 Do not use UART0 reception (Note 1) FFFF816 to FFFFB16 Do not use Reset FFFFC 16 to FFFFF16 Note 1: Interrupts used for debugging purposes only. Mid address Low address 0 0 0 0 High address 0 0 0 0 0 0 0 0 Vector address + 0 Vector address + 1 Vector address + 2 Vector address + 3 LSBMSB

10.1.4 Interrupts and Interrupt Vector Tables

If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Figure 10.2 shows format for specifying interrupt vector addresses. Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting. Figure 10.2 Format for specifying interrupt vector addresses

10.1.4.1 Fixed Vector Tables

The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFDC 16 to FFFFF16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table 10.1 lists the interrupts assigned to the fixed vector tables and addresses of vector tables. Table 10.1 Interrupt and fixed vector address

Rev.1.00 Oct 20, 2004 page 49 of 222 M16C/1N Group 10. Interrupt REJ09B0007-0100Z Software interrupt number Interrupt sourceVector table address (Note 1) Address (L) to address (H) Remarks Note 1: Address relative to address in interrupt table register (INTB). to +0to +3 +4to +7 +8to +11 +12to +15 +16to +19 +20to +23 +24to +27 +28to +31 +32to +35 +36to +39 +40to +43 +44to +47 +48to +51 +52to +55 +56to +59 +60to +63 +64to +67 +68to +71 +72to +75 +76to +79 +80to +83 +84to +87 +88to +91 +92to +95 +96to +99 +100to+103 +104to+107 +108to+111 + 1 12to+115 + 1 16to+119 +120to+123 +124to+127 +128to+131 to +252to+255 BRK instruction CAN0 wake up CAN0 error CAN0 successful reception CAN0 successful transmission Key input A/D UART0 transmission UART0 reception UART1 transmission UART1 reception Timer 1 Timer X Timer Y Timer Z CNTR TCIN Timer C INT3 INT0 INT1 INT2 software interrupt Cannot be masked by I flag Cannot be masked by I flag

10.1.4.2 Variable Vector Tables

The addresses in the variable vector table can be modified, according to the user’s settings. Indi- cate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the address the INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 10.2 lists the interrupts assigned to the variable vector tables and addresses of vector tables. Table 10.2 Interrupt causes (variable interrupt vector addresses)

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10.1.5 Interrupt Control

Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level select bit, and processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selec- tion bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are located in the flag register (FLG). Figure 10.3 shows the interrupt control registers.

Rev.1.00 Oct 20, 2004 page 51 of 222 M16C/1N Group 10. Interrupt REJ09B0007-0100Z b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see 10.7 the precautions for interrupts. Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts. Interrupt control register Symbol C01WKIC C01ERRIC C0RECIC C0TRMIC KUPIC ADIC SiTIC(i=0,1) SiRIC(i=0,1) T1IC TXIC TYIC TZIC CNTR0IC TCINIC TCIC INT3IC Address 004516 004616 004816 004916 004D16 004E16 005116, 005316 005216, 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 When reset XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 RW RW RW RW RW FunctionBit nameBit symbol RW RW RW RW RW RW RW FunctionBit nameBit symbol ILVL0 ILVL1 ILVL2 Interrupt priority level select bit IR Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. Interrupt request bit 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : Interrupt not requested 1 : Interrupt requested b2 b1 b0 (Note 1) ILVL0 ILVL1 ILVL2 Interrupt priority level select bit IR Interrupt request bit 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : Interrupt not requested 1 : Interrupt requested POL Polarity select bit 0 : Selects falling edge 1 : Selects rising edge Reserved bit Set to "0" b2 b1 b0 (Note 1) Symbol INTiIC(i=0, 1, 2) Address 005D16, 005E16, 005F16 When reset XX00X0002 XX00X0002 Figure 10.3 Interrupt control register

Rev.1.00 Oct 20, 2004 page 52 of 222 M16C/1N Group 10. Interrupt REJ09B0007-0100Z Interrupt priority level select bit Interrupt priority level Priority order Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Low High b2 b1 b0 Enabled interrupt priority levels Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 4 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled IPL2 IPL1IPL0 IPL 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111

10.1.5.1 Interrupt Enable Flag (I flag)

The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to "1" enables all maskable interrupts; setting it to "0" disables all maskable interrupts. This flag is set to "0" after reset.

10.1.5.2 Interrupt Request Bit

The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hard- ware. The interrupt request bit can also be set to "0" by software (Do not set this bit to "1").

10.1.5.3 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)

Set the interrupt priority level using the interrupt priority level select bit, which is one of the compo- nent bits of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt priority level to "0" disables the interrupt. Table 10.3 lists the settings of interrupt priority levels and Table 10.4 lists the interrupt levels en- abled, according to the consist of the IPL. The following are conditions under which an interrupt is accepted:

• interrupt enable flag (I flag) = 1
• interrupt request bit = 1
• interrupt priority level > IPL The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are independent, and they are not affected by one another. Table 10.3 Settings of interrupt priority levels Table 10.4 Interrupt levels enabled according to the contents of the IPL

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10.1.5.4 Rewrite the Interrupt Control Register

To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow: Example 1: INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear T1IC int. priority level and int. request bit. NOP ; NOP FSET I ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear T1IC int. priority level and int. request bit. MOV.W MEM, R0 ; Dummy read. FSET I ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG ; Push Flag register onto stack FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear T1IC int. priority level and int. request bit. POPC FLG ; Enable interrupts. The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET Changing the interrupt request bit When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit is not cleared sometimes. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : MOV

Rev.1.00 Oct 20, 2004 page 54 of 222 M16C/1N Group 10. Interrupt REJ09B0007-0100Z

10.1.5.5 Interrupt Sequence

An interrupt sequence — what are performed over a period from the instant an interrupt is ac- cepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and trans- fers control to the interrupt sequence. In the interrupt sequence, the processor carries out the following in sequence given: (1) CPUgets the interrupt information (the interrupt number and interrupt request level) by reading address 00000 16. After this, the corresponding interrupt request bit becomes "0". (2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note 1) within the CPU. (3) Sets the interrupt enable flag (I flag), the debug flag (Dflag), and the stack pointer select flag (U flag) to "0" (the U flag, however, does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed). (4) Saves the content of the temporary register (Note 1) within the CPU in the stack area. (5) Saves the content of the program counter (PC) in the stack area. (6) Sets the interrupt priority level of the accepted instruction in the IPL. After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. Note 1: This register cannot be utilized by the user. Figure 10.4 shows the time required for executing interrupt sequence. Indeterminate 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs. Indeterminate SP-2

contents

0000016 Indeterminate SP-2 SP-4 vec vec+2 PC

W R Figure 10.4 Time required for executing interrupt sequence

Rev.1.00 Oct 20, 2004 page 55 of 222 M16C/1N Group 10. Interrupt REJ09B0007-0100Z Instruction Interrupt sequence Instruction in interrupt routine Time Interrupt response time (a) (b) Interrupt request acknowledgedInterrupt request generated (a)A time from when an interrupt request is generated till when the instruction then executing is completed. The length of this time varies with the instruction being executed. The DIVX instruction requires the longest time, which is equal to 30 cycles (without wait state, the divisor being a register). (b)A time during which the interrupt sequence is executed. For details, see the table below. Note, however, that the values in this table must be increased 2 cycles for the DBC interrupt and 1 cycle for the address match and single-step interrupts. Locate an interrupt vector address in an even address, if possible. Interrupt vector address Without wait Even Even Odd Odd Even Odd Even Odd 18 cycles 19 cycles 19 cycles 20 cycles Stack pointer (SP) value

10.1.5.6 Interrupt Response Time

'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). Figure 10.5 shows the interrupt response time. Figure 10.5 Interrupt response time

Rev.1.00 Oct 20, 2004 page 56 of 222 M16C/1N Group 10. Interrupt REJ09B0007-0100Z Address Content of previous stack Stack area [SP] Stack pointer value before interrupt occurs m m - 1 m - 2 m - 3 m - 4 Stack status before interrupt request is acknowledged Stack status after interrupt request is acknowledged Content of previous stackm + 1 MSB LSB m m - 1 m - 2 m - 3 m - 4 Address Flag register (FLG Content of previous stack Stack area Flag register (FLGH) Program counter (PCH) [SP] New stack pointer value Content of previous stackm + 1 MSB LSB Program counter (PC Program counter (PCM)

10.1.5.8 Saving Registers

In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the stack area. First, the processor saves the 4 high-order bits of the program counter, and 4 high-order bits and 8 low-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 low-order bits of the program counter. Figure 10.6 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM instruction alone can save all the registers except the stack pointer (SP). Figure 10.6 State of stack before and after acceptance of interrupt request Interrupt sources without priority levels Watchdog timer Reset Other Value set in the IPL Not changed

10.1.5.7 Variation of IPL when Interrupt Request is Accepted

If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in Table 10.6 is set in the IPL. Table 10.6 Relationship between interrupts without interrupt priority levels and IPL

Rev.1.00 Oct 20, 2004 page 57 of 222 M16C/1N Group 10. Interrupt REJ09B0007-0100Z (2) Stack pointer (SP) contains odd number [SP] (Odd) [SP] - 1(Even) [SP] - 2 (Odd) [SP] - 3 (Even) [SP] - 4 (Odd) [SP] - 5 (Even) Address Sequence in which order registers are saved (2) (1) Finished saving registers in four operations. (3) (4) (1) Stack pointer (SP) contains even number [SP] (Even) [SP] - 1 (Odd) [SP] - 2 (Even) [SP] - 3 (Odd) [SP] - 4 (Even) [SP] - 5 (Odd) Address Program counter (PC Stack area Flag register (FLGL) Program counter (PCL) Sequence in which order registers are saved Finished saving registers in two operations. Program counter (PCM) Stack area Flag register (FLG Program counter (PCL) Saved simultaneously, all 8 bits Flag register (FLGH) Program counter (PCH) Flag register (FLGH) Program counter (PCH) (2) Saved simultaneously, all 16 bits (1) Saved simultaneously, all 16 bits Note 1: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer (Note 1), at the time of acceptance of an interrupt request, is even or odd. If the content of the stack pointer (Note 1) is even, the content of the flag register (FLG) and the content of the program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Figure 10.7 shows the operation of the saving registers. Note 1: This is the stack pointer indicated by the U flag. Figure 10.7 Operation of saving registers

Rev.1.00 Oct 20, 2004 page 58 of 222 M16C/1N Group 10. Interrupt REJ09B0007-0100Z Figure 10.8 Hardware interrupts priorities

10.1.5.9 Returning from an Interrupt Routine

Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter (PC), both of which have been saved in the stack area. Then control returns to the program that was being executed before the acceptance of the interrupt request, so that the sus- pended process resumes. Return the other registers saved by software within the interrupt routine using the POPM or similar instruction before executing the REIT instruction.

10.1.5.10 Interrupt Priority

If there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is ac- cepted. Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level select bit. If the same interrupt priority level is assigned, however, the interrupt as- signed a higher hardware priority is accepted. Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. Figure 10.8 shows the priorities of hardware interrupts. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine.

10.1.5.11 Interrupt Priority Level Judge Circuit

This circuit selects the interrupt with the highest priority level when two or more interrupts are generated simultaneously. Figure 10.9 shows the interrupt resolution circuit. Reset UART0 reception DBC Watchdog timer/Oscillation stop detection Peripheral function Single step Address match High Low

Rev.1.00 Oct 20, 2004 page 59 of 222 M16C/1N Group 10. Interrupt REJ09B0007-0100Z INT1 INT3 TCIN Timer Z Timer X CAN0 error INT2 INT0 Timer C CNTR0 Timer Y CAN0 wake up UART1 reception UART0 reception A/D conversion CAN0 successful reception Timer 1 UART1 transmission UART0 transmission Key input CAN0 successful transmission Processor interrupt priority level (IPL) Interrupt enable flag (I flag) Address match Oscillation stop detection/Watchdog timer DBC (Note 1) High Low Level 0 (initial value)Priority level of each interrupt Interrupt request accepted UART0 receive hardware interrupt enable bit Note 1: Interrupts used for debugging purposes only. Priority of peripheral I/O interrupts (if priority levels are same) Interrupt request level judgment output signal UART0 reception (Note 1) Reset Figure 10.9 Interrupt resolution circuit

Rev.1.00 Oct 20, 2004 page 60 of 222 M16C/1N Group 10. Interrupt REJ09B0007-0100Z b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 External input enable register INT0EN INT 0 input enable bit (Note 1) 0 : Disabled 1 : Enabled INT0F0 INT0F1 INT0 input filter select bit INT0PL INT 0 input polarity select bit (Note 1) 0 : One edge 1 : Two edges INT1EN INT 1 input enable bit 0 : Disabled 1 : Enabled INT1PL INT 1 input polarity select bit 0 : One edge 1 : Two edges INT2EN INT 2 input enable bit 0 : Disabled 1 : Enabled INT2PL INT 2 input polarity select bit 0 : One edge 1 : Two edges INT3EN INT 3 input enable bit 0 : Disabled 1 : Enabled INT0F2 UART0 receive hardware interrupt enable bit (Note 1) 0 : Disabled 1 : Enabled INT3PL INT 3 input polarity select bit 0 : One edge 1 : Two edges Nothing is assigned. When write, nothing can be written. When read, their contents are indeterminate. Symbol INTEN Address 009616 When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol INT0 input filter select register Symbol INT0F Address 001E16 When reset XXXXX0002 RW RW RW RW FunctionBit nameBit symbol 0 0 : No filter 0 1 : Filter with f1 sampling 1 0 : Filter with f8 sampling 1 1 : Filter with f32 sampling b1 b0 Note 1: Interrupts used for debugging purposes only. Be sure to set "0" to this bit. Note 1: This bit must be set in condition of the INT0 pin one-shot trigger control bit (bit 6 at address 008416)="0" (INT0 pin one-shot trigger invalid).

10.2 INT Interrupt

10.2.1 INT0 Interrupt

INT0 to INT3 are triggered by the edges of external inputs. The edge polarity of INT0 to INT2 is selected using the polarity select bit (bit 4 at addresses 005D16, 005E16 and 005F16). Input to INT0 is available via filter with three different sampling frequencies. As to external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge by setting the INTi (i=0 to 3) input polarity select bit of the external input enable register (address 0096 16) to "1". To select both edges, set the polarity switching bit of the corresponding interrupt con- trol register to "0" (falling edge). To select one edge, set the polarity switching bit of the corresponding interrupt control register to either "1" (raising edge) or "0" (falling edge). Please note that when one edge is selected using INT 3, the polarity will be a falling edge. After setting the external input enable register, clear the interrupt request bit, and then enable the corresponding input interrupt. Moreover, you should write to the external input enable bit only under conditions where the corresponding input interrupt is disabled. Figure 10.10 shows the external input related registers. Figure 10.10 External input related registers

Rev.1.00 Oct 20, 2004 page 61 of 222 M16C/1N Group 10. Interrupt REJ09B0007-0100Z Digital filter (input level matches 3x) INT0 interrupt requestINT0 f32 INT0 input filter select bit Port P45 direction register INT0 input enable bit

10.2.2 INT0 Input Filter

The INT0 input has a digital filter which can be sampled by one of three sampling clocks. You select the sampling clock using the INT0 Input Filter Select bits, bits 1 and 0. INT0 interrupt request occurs when the sampled input level matches three times. When selecting "Sampling with filter", the value of the port P45, if read, will be the value after filtering. Figure 10.11 shows the INT0 input filter. Figure 10.11 INT0 input filter

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10.3 CNTR0 Interrupt

A CNTR0 interrupt is generated from the selected edge polarity, a rising or a falling edge, of the CNTR0 input signal. The edge polarity is selected using the CNTR0 polarity select bit (bit 2 at address 008B16). When using the CNTR0 interrupt, the port P17 direction register should be set to input. When the pulse output mode of timer X is selected, the CNTR0 pin functions as a pulse output pin. In this case, a CNTR 0 interrupt occurs by a falling or rising edge output from the CNTR 0 pin. The port P1 7 direction register should else be set to input at this time. Figure 10.12 shows the timer X mode register. Note 1: In the pulse output mode, the direction register of port P17 should be set to input. Note 2: This bit should rewrite with inhibiting the CNTR0 interrupt. To use all interrupt, enable an interrupt after the CNTR0 interrupt request bit is cleared with the MOV instruction. Note 3: Nothing is assigned to the pod probe for M16C/1N group (M301N2T-PRB). b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register TXMOD0 TXMOD1 Operation mode select bit 0, 1 (Note 2) R0EDG CNTR 0 polarity switching bit (Note 2) TXS Timer X count start flag 0 : Stops counting 1 : Starts counting 0 : Rising edge 1 : Falling edge TXOCNT P3 0/TXOUT select bit Function varies with each operation mode TXMOD2 Operation mode select bit 2 0 : Except in pulse period measurement mode 1 : Pulse period measurement mode TXEDG Effectual edge reception flag (Note 3) Function varies with each operation mode TXUND Timer X under flow flag (Note 3) Function varies with each operation mode Symbol TXMR Address 008B16 When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol b1 b0 0 0 : Timer mode or pulse period measurement mode 0 1 : Pulse output mode (Note 1) 1 0 : Event counter mode 1 1 : Pulse width measurement mode Figure 10.12 Timer X mode register

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10.4 TCIN Interrupt

A TCIN interrupt is generated from edges of a TCIN input signal or after 256 divisions of fRING. To use TCIN input signal, set the time measurement input source switching bit (bit 7 at address 009A16) of timer C control register 0 to "0" (TCIN). The level of input to TCIN pin is sampled by one of three sampling clocks, f1, f8 or f32, selected with the digital filter clock select bit (bits 0 and 1 at address 009B 16). The input level is determined when the sampled input level matches three times. (However, if the port P33 is read, the value will be the unfiltered value.) The edge polarity of an interrupt can be a rising edge, a falling edge, or both edges using the time measurement edge trigger select bits (bits 3 and 4 at address 009A 16). When triggered after 256 divisions of fRING, set the time measurement input source switching bit (bit 7 at address 009A16) to "1" (fRING256). Figure 10.13 shows the timer C control registers 0 and 1. Figure 10.13 Timer C control registers 0 and 1 Note 1: Change this bit when time measurement is disabled. Note 2: Set the ring oscillation stop bit (CM14) to "0" before setting this bit to "1". Note 3: Inhibit an interrupt when changing the time measurement input source switching bit. The TCIN interrupt may be generated after changing the time measurement input source switching bit. An interrupt should be enabled after the interrupt request bit is cleared. b7 b6 b5 b4 b3 b2 b1 b0 Timer C control register 0 TCC00 Time measurement control bit 0 : Time measurement disabled 1 : Time measurement enabled TCC07 Time measurement input source switching bit (Note 1 to 3) 0 : TCIN 1 : f RING256 TCC01 Timer C clock select bit (Note 1) TCC02 Symbol TCC0 Address 009A16 When reset 0XX000002 FunctionBit nameBit symbol RW RW RW RW RW RW RW 0 0 : f 0 1 : f8 1 0 : f32 1 1 : Inhibited b2 b1 TCC03 Nothing is assigned. When write, set "0". When read, their contents are "0". Nothing is assigned. When write, set "0". When read, their contents are "0". b7 b6 b5 b4 b3 b2 b1 b0 Timer C control register 1 TCC10 Digital filter clock select bit (Note 1) TCC11 Symbol TCC1 Address 009B16 When reset XXXXXX112 FunctionBit nameBit symbol RW RW RW 0 0 : Inhibited 0 1 : f1 1 0 : f8 1 1 : f32 b1 b0 Time measurement input edge trigger bit (Note 1) TCC04 0 0 : Rising edge 0 1 : Falling edge 1 0 : Both edges 1 1 : Inhibited b4 b3 Note 1: Input edge becomes active when the same value from TCIN pin is sampled three times in succession.

Rev.1.00 Oct 20, 2004 page 64 of 222 M16C/1N Group 10. Interrupt REJ09B0007-0100Z (address 004D16) Key input interrupt request Port P10-P13 pull-up select bit Pull-up transistor Port P10 direction register Pull-up transistor Pull-up transistor Pull-up transistor 3/KI3 P12/KI2 P11/KI1 P10/KI0 Interrupt control circuit Key input interrupt control register KI0 input enable bit KI0 input polarity select bit Port P1 direction register KI1 input enable bit KI1 input polarity select bit Port P1 direction register KI2 input enable bit KI2 input polarity select bit Port P1 direction register KI3 input enable bit KI3 input polarity select bit Port P13 direction register b7 b6 b5 b4 b3 b2 b1 b0 Key input enable register KI0EN KI 0 input enable bit 0 : Disabled 1 : Enabled KI0PL KI 0 input polarity select bit 0 : Falling edge 1 : Rising edges KI1EN KI 1 input enable bit 0 : Disabled 1 : Enabled KI1PL KI 1 input polarity select bit 0 : Falling edge 1 : Rising edges KI2EN KI 2 input enable bit 0 : Disabled 1 : Enabled KI2PL KI 2 input polarity select bit 0 : Falling edge 1 : Rising edges KI3EN KI 3 input enable bit 0 : Disabled 1 : Enabled KI3PL KI 3 input polarity select bit 0 : Falling edge 1 : Rising edges Symbol KIEN Address 009816 When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol

10.5 Key Input Interrupt

When the direction register of any of P10 to P13 is set for input and the KIi (i=0 to 3) input enable bit of this port is set for enabled, if a falling or rising edge is input to that port, a key input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. Figure 10.14 shows the block diagram of the key input interrupts. When the appropriate signal ("L" for a pin that has falling edge selected and "H" for a pin that has rising edge selected) is input to a pin for the input inhibit process has not been executed, inputs to the other pins are not detected as interrupts. You should overwrite the KIi (i=0 to 3) input polarity select bit or the KIi (i =0 to 3) input enable bit only under conditions where the key input interrupt is disabled. After overwriting the KIi (i=0 to 3) input polarity select bit or the KIi (i=0 to 3) input enable bit, clear the interrupt request bit, and then enable the key input interrupt. Figure 10.14 Block diagram of key input interrupt Figure 10.15 Key input enable register

Rev.1.00 Oct 20, 2004 page 65 of 222 M16C/1N Group 10. Interrupt REJ09B0007-0100Z Address match interrupt enable register Symbol AIER Address 000916 When reset XXXXXX002 RW RW RW FunctionBit nameBit symbol AIER0 Address match interrupt register i (i = 0, 1) Symbol RMAD0 RMAD1 When reset XXXX0000 2, 000000002, 000000002 Address 001216 to 001016 001616 to 001416 RW RW Function Values that can be set Address setting register for address match interrupt Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. 0000016 to FFFFF16 Address match interrupt 0 enable bit 0 : Interrupt disabled 1 : Interrupt enabled AIER1 Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. Address match interrupt 1 enable bit 0 : Interrupt disabled 1 : Interrupt enabled b0 b7 b0b3 (b19) (b16) b7 b0 (b15) (b8) (b23) b7 b6 b5 b4 b3 b2 b1 b0

10.6 Address Match Interrupt

An address match interrupt is generated immediately before the instruction at the address indicated by the address match interrupt register is executed. Two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). The value of the program counter (PC) for an address match interrupt varies depending on the instruction being executed. Figure 10.16 shows the address match interrupt-related registers. Figure 10.16 Address match interrupt-related registers

Rev.1.00 Oct 20, 2004 page 66 of 222 M16C/1N Group 10. Interrupt REJ09B0007-0100Z Set the interrupt priority level to level 0 (Disable interrupt) Set the polarity select bit Clear the interrupt request bit to "0" Set the interrupt priority level to level 1 to 7 (Enable the accepting of interrupt request) Clear the interrupt enable flag to "0" (Disable interrupt) Set the interrupt enable flag to "1" (Enable interrupt)

10.7 Precautions for Interrupts

10.7.1 Reading Address 0000016

When maskable interrupt is occurred, CPU reads the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 00000 16 will then be set to "0". Even if the address 0000016 is read out by software, "0" is set to the enabled highest priority interrupt source request bit. Therefore, interrupt can be canceled and unexpected interrupt can occur. Do not read address 00000 16 by software.

10.7.2 Setting the Stack Pointer

The value of the stack pointer immediately after reset is initialized to address 0000 16. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the stack pointer before accepting an interrupt. Concerning the first instruction immediately after reset, generating any interrupts is prohibited.

10.7.3 External Interrupt

Either an "L" level or an "H" level of at least 250 ns width is necessary for the signal input to pins INT0 to INT3 regardless of the CPU operation clock. When changing a polarity of pins INT0 to INT3 and CNTR0, the interrupt request bit may become "1". Clear the interrupt request bit after changing the polarity. Figure 10.17 shows the switching condition of external interrupt request. Figure 10.17 Switching condition of external interrupt request

Rev.1.00 Oct 20, 2004 page 67 of 222 M16C/1N Group 10. Interrupt REJ09B0007-0100Z

10.7.4 Changing Interrupt Control Register

See "10.1.5.4 Rewrite the Interrupt Control Register".

Rev.1.00 Oct 20, 2004 page 69 of 222 M16C/1N Group 11. Watchdog Timer REJ09B0007-0100Z b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer control register Symbol WDC Address 000F16 When reset 000XXXXX2 RW RO RW RW FunctionBit nameBit symbol High-order bit of watchdog timer Reserved bit WDC7 Set to "0" 0 : Divided by 16 1 : Divided by 128 Prescaler select bit b7 b0 Watchdog timer start register Symbol WDTS Address 000E16 When reset Indeterminate RW WO Function The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to "7FFF16" regardless of whatever value is written. b7 b6 b5 b4 b3 b2 b1 b0 PM12 WDT interrupt/reset switching bit DATAROM area access bit (Note 2) Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. 0 : Watchdog timer interrupt 1 : Reset (Note 3) Processor mode register 1 (Note 1) Note 1: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register. Note 2: This bit is valid for the flash memory version. For the mask ROM version, this bit must be set to "0". Note 3: After setting this bit to "1", can not change to "0" by software. PM17 Wait bit 0 : No wait 1 : Wait 0 : Disabled 1 : Enabled PM10 Reserved bit Set to "0" Symbol PM1 Address 0005 When reset 00XXX0X02 RW RW RW RW RW FunctionBit nameBit symbol Figure 11.2 Watchdog timer control and start registers

Rev.1.00 Oct 20, 2004 page 70 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z Timer1 TimerX TimerY TimerZ TimerC Configuration 8-bit timer 8-bit timer 8-bit timer 8-bit timer 16-bit with 8-bit with 8-bit with 8-bit with 8-bit free-run prescaler prescaler prescaler prescaler timer Count Down Down Down Down Up Count source •f 1 •f1 •f1 •f1 •f1

• f32 •f32 •fRING •TmrY underflow •f32
• fc32 •fc32 •fc32 •fc32 Function Timer mode √√ √√ − Pulse output mode −√ −− − Event counter mode −√ −− − Pulse width −√ −− −measurement mode Pulse period −√ −− −measurement mode Programmable waveform −− √√ −generation mode Programmable one-shot −− −√ −generation mode Programmable wait −− −√ −one-shot generation mode Input pin − CNTR0 − INT0 TCIN CNTR0Output pin − TYOUT TZOUT −TXOUT TmrX int TmrC intRelated interrupt Tmr1 int TmrY int TmrZ int CNTR0 int TCIN int 12. Timers The microcomputer has four 8-bit timers and one 16-bit timer. The four 8-bit timers are Timer 1, Timer X, Timer Y, and Timer Z and each one has an 8-bit prescaler. The 16-bit timer is Timer C and has time measurement function. All these timers function independently. The count source for each timer is the operating clock that regulates the timing of timer operations such as counting and reloading. Table 12.1 shows functional comparison. Table 12.1 Functional comparison

Rev.1.00 Oct 20, 2004 page 71 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z Item Specification Count source f 1, f8, f32, fC32 Count operation • Down count

• When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio n: Set value of Prescaler 1, m: Set value of Timer 1 Count start condition After reset Count stop condition Disable to stop counting Interrupt request generation timing When Timer 1 underflows Read from timer Count value can be read out by reading Timer 1 register. Same applies to Prescaler 1 register. Write to timer When a value is written to Timer 1 register, it is written to both reload register and counter. Same applies to Prescaler 1 register. Clock source selection f32 fC32 Prescaler 1 (address 008816) Peripheral data bus Reload register (8) Counter (8) Reload register (8) Counter (8) Timer 1 (address 008916) Timer 1 interrupt request bit fP1 (n+1) X (m+1)

12.1 Timer 1

Timer 1 is an 8-bit timer with an 8-bit prescaler. Figure 12.1 shows the block diagram of Timer 1. The timer constantly counts an internally generated count source (clock source). The count source after reset is set to f 1. The timer cannot stop counting. Table 12.2 shows the specifications of Timer 1 and Figure 12.2 shows Timer 1 related registers. Figure 12.1 Block diagram of Timer 1 Table 12.2 Specifications of Timer 1 (Timer mode)

Rev.1.00 Oct 20, 2004 page 72 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z b7 b6 b5 b4 b3 b2 b1 b0 Timer count source setting register TXCK0 TXCK1 Timer X count source select bit (Note 1) Symbol TCSS Address 008E16 When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b1 b0 TYCK0 TYCK1 Timer Y count source select bit (Note 1, 2) 0 0 : f1 0 1 : f8 1 0 : On-chip oscillator output (Note 3) 1 1 : fC32 b3 b2 TZCK0 TZCK1 Timer Z count source select bit (Note 1, 4) 0 0 : f1 0 1 : f8 1 0 : Timer Y underflow 1 1 : fC32 b5 b4 T1CK0 T1CK1 Timer 1 count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Note 1: Avoid switching a count source, while a counter is in progress. Timer counter should be stopped before switching a count source. Note 2: The waveform extend function cannot be used when selecting f1 for count source. Note 3: When attempting to select on-chip oscillator output, set the on-chip oscillation enable bit (CM14) of the system clock control register (address 000716) for oscillation enabled. Note 4: The waveform extend function cannot be used when selecting Timer Y underflow and f1 for count source. Both the Timer Y primary underflow and the Timer Y secondary underflow are counted when selecting the Timer Y underflow for count source. b7 b0 Prescaler 1 Symbol PRE1 Address 008816 When reset Indeterminate RW RW Function Values that can be set When set value = n, Prescaler 1 divides the internal count source by n+1 0016 to FF16 b7 b0 Timer 1 Symbol Address 008916 When reset Indeterminate RW RW Function Values that can be set When set value = m, Timer 1 divides the underflow of Prescaler 1 by m+1 0016 to FF16 Figure 12.2 Timer 1-related register

Rev.1.00 Oct 20, 2004 page 73 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z Clock source selection Timer Pulse period measurement Pulse output f32 Event counter fC32 Toggle flip-flop Polarity switchingCNTR0 Q Q T CNTR0 interrupt request bit P30/TXOUT select bit TXOUT CNTR0 polarity switching bit "1" "0" R Pulse width measurement Pulse output Counter (8) Reload register (8) Counter (8) Reload register (8) Timer X count start flag Prescaler X (address 008C16) Timer X (address 008D16) Pulse output mode Timer X latch write Timer X interrupt request bit Peripheral data bus fPX Note 1: In the pulse output mode, the direction register of port P17 should be set to input. Note 2: This bit should rewrite with inhibiting the CNTR0 interrupt. To use all interrupt, enable an interrupt after the CNTR0 interrupt request bit is cleared with the MOV instruction. Note 3: Nothing is assigned to the pod probe for M16C/1N group (M301N2T-PRB). b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register TXMOD0 TXMOD1 Operation mode select bit 0, 1 (Note 2) R0EDG CNTR 0 polarity switching bit (Note 2) TXS Timer X count start flag 0 : Stops counting 1 : Starts counting 0 : Rising edge 1 : Falling edge TXOCNT P3 0/TXOUT select bit Function varies with each operation mode TXMOD2 Operation mode select bit 2 0 : Except in pulse period measurement mode 1 : Pulse period measurement mode TXEDG Effectual edge reception flag (Note 3) Function varies with each operation mode TXUND Timer X under flow flag (Note 3) Function varies with each operation mode Symbol TXMR Address 008B16 When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol b1 b0 0 0 : Timer mode or pulse period measurement mode 0 1 : Pulse output mode (Note 1) 1 0 : Event counter mode 1 1 : Pulse width measurement mode

12.2 Timer X

Timer X is an 8-bit timer with an 8-bit prescaler. Timer X has the five operation modes listed as follows:

• Timer mode: The timer counts an internal count source (clock source).
• Pulse output mode: The timer counts an internal count source and outputs the pulses whose polarity is inverted at the timer the timer underflows.
• Event counter mode: The timer counts pulses from an external source.
• Pulse width measurement mode: The timer measures an external pulse's pulse width.
• Pulse period measurement mode: The timer measures an external pulse's period. Figure 12.3 shows the block diagram of Timer X. Figures 12.4 and 12.5 shows the Timer X-related registers. Figure 12.3 Block diagram of Timer X Figure 12.4 Timer X-related registers (1)

Rev.1.00 Oct 20, 2004 page 74 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z b7 b6 b5 b4 b3 b2 b1 b0 Timer count source setting register TXCK0 TXCK1 Timer X count source select bit (Note 1) Symbol TCSS Address 008E16 When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b1 b0 TYCK0 TYCK1 Timer Y count source select bit (Note 1, 2) 0 0 : f1 0 1 : f8 1 0 : On-chip oscillator output (Note 3) 1 1 : fC32 b3 b2 TZCK0 TZCK1 Timer Z count source select bit (Note 1, 4) 0 0 : f1 0 1 : f8 1 0 : Timer Y underflow 1 1 : fC32 b5 b4 T1CK0 T1CK1 Timer 1 count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Note 1: Avoid switching a count source, while a counter is in progress. Timer counter should be stopped before switching a count source. Note 2: The waveform extend function cannot be used when selecting f1 for count source. Note 3: When attempting to select on-chip oscillator output, set the on-chip oscillation enable bit (CM14) of the system clock control register (address 000716) for oscillation enabled. Note 4: The waveform extend function cannot be used when selecting Timer Y underflow and f1 for count source. Both the Timer Y primary underflow and the Timer Y secondary underflow are counted when selecting the Timer Y underflow for count source. b7 b0 Prescaler X Symbol PREX Address 008C16 When reset FF16 RW RW RW RW RW RW Function Values that can be set Timer mode Internal count source is counted 0016 to FF16 Pulse output mode Internal count source is counted 0016 to FF16 Event counter mode Externally input pulses are counted 0016 to FF16 Pulse period measurement mode Underflow of prescaler X is counted 0116 to FF16 Pulse width measurement mode Pulse width of externally input pulses is measured (Internal count source is counted) 16 to FF16 Timer mode, Pulse output mode, Event counter mode, Pulse width measurement mode Underflow of prescaler X is counted 16 to FF16 Pulse period measurement mode Pulse period of externally input pulses is measured (Internal count source is counted) 16 to FF16 b7 b0 Timer X Symbol TX Address 008D16 When reset FF16 RW RW RW Function Values that can be set Figure 12.5 Timer X-related registers (2)

Rev.1.00 Oct 20, 2004 page 75 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z Item Specification Count source f 1, f8, f32, fC32 Count operation • Down count

• When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio n: Set value of Prescaler X, m: Set value of Timer X Count start condition Count start flag is set (=1) Count stop condition Count start flag is reset (=0) Interrupt request generation timing When Timer X underflows [Timer X interruption] CNTR0 pin function Programmable I/O port or CNTR 0 interrupt input pin TXOUT pin function Programmable I/O port Read from timer Count value can be read out by reading Timer X register. Same applies to Prescaler X register. Write to timer When a value is written to Timer X register, it is written to both reload register and counter. Same applies to Prescaler X register. Table 12.3 Specifications of timer mode b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register TXMOD0 TXMOD1 Operation mode select bit 0, 1 (Note 1) R0EDG CNTR 0 polarity switching bit (Note 1) TXS Timer X count start flag P30/TXOUT select bit Operation mode select bit 2 0 : Stops counting 1 : Starts counting 0 : Rising edge 1 : Falling edge TXOCNT 0 : In timer mode, set to "0" TXMOD2 0 : In timer mode, set to "0" TXEDG Effectual edge reception flag TXUND Timer X under flow flag Invalid in timer mode. When write, set "0". When read, this contents is indeterminate. Invalid in timer mode. When write, set "0". When read, this contents is indeterminate. Symbol TXMR Address 008B When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol b1 b0 00 00 0 0 : Timer mode Note 1: This bit should rewrite with inhibiting the CNTR0 interrupt. When using the interrupt, the interrupt must be enabled after clearing the CNTR0 interrupt request bit to "0" using a MOV instruction. (n+1) X (m+1) Figure 12.6 Timer X mode register in timer mode

12.2.1 Timer Mode

In this mode, the timer counts an internally generated count source. (See Table 12.3) Figure 12.6 shows the Timer X mode register in timer mode.

Rev.1.00 Oct 20, 2004 page 76 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z 100 Note 1: In the pulse output mode, the direction register of port P17 must be set to input. Note 2: This bit should rewrite with inhibiting the CNTR0 interrupt. To use this interrupt, enable an interrupt after the CNTR0 interrupt request bit is cleared with the MOV instruction. Note 3: Output is set regardless of the setting of the direction register of port P30. b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register TXMOD0 TXMOD1 Operation mode select bit 0, 1 (Note 2) 0 1 : Pulse output mode (Note 1) R0EDG CNTR 0 polarity switching bit (Note 2) 0 : Output starts at "H" (Interrupt at rising edge) 1 : Output starts at "L" (Interrupt at falling edge) TXS Timer X count start flag 0 : Stops counting 1 : Starts counting TXOCNT P3 0/TXOUT select bit Operation mode select bit 2 TXMOD2 0 : Set to "0" in pulse output mode 0 : Port P30 1 : TXOUT output (Note 3) Symbol TXMR Address 008B16 When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol b1 b0 TXEDG Effectual edge reception flag TXUND Timer X under flow flag Invalid in pulse output mode. When write, set "0". When read, this contents is indeterminate. Invalid in pulse output mode. When write, set "0". When read, this contents is indeterminate. (n+1) X (m+1) Item Specification Count source f 1, f8, f32, fC32 Count operation • Down count

• When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio n: Set value of Prescaler X, m: Set value of Timer X Count start condition Count start flag is set (=1) Count stop condition Count start flag is reset (=0) Interrupt request generation timing • When Timer X underflows [Timer X interruption]
• Rising (R0EDG=0) or falling (R0EDG=1) of CNTR 0 output [CNTR0 interruption] CNTR0 pin function Pulse output TXOUT pin function Programmable I/O port or pulse output (Inverted waveform of the pulse output from the CNTR0 pin) Read from timer Count value can be read out by reading Timer X register. Same applies to Prescaler X register. Write to timer When a value is written to Timer X register, it is written to both reload register and counter. Same applies to Prescaler X register. Select function • Pulse output function Each time the timer underflows, the TXOUT pin’s polarity is reversed
• CNTR0 polarity switching function The polarity level at starting of pulse output can be selected to be "High" or "Low" with software.

12.2.2 Pulse Output Mode

In this mode, the timer counts an internally generated count source, and outputs from the CNTR0 pin a pulse whose polarity is inverted each time the timer underflows. (See Table 12.4) Figure 12.7 shows Timer X mode register in pulse output mode. Table 12.4 Specifications of pulse output mode Figure 12.7 Timer X mode register in pulse output mode

Rev.1.00 Oct 20, 2004 page 77 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z 0100 b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register TXMOD0 TXMOD1 Operation mode select bit 0, 1 (Note 1) 1 0 : Event counter mode R0EDG CNTR 0 polarity switching bit (Note 1) 0 : Counts at rising edge (Interrupt at rising edge) 1 : Counts at falling edge (Interrupt at falling edge) TXS Timer X count start flag 0 : Stops counting 1 : Starts counting TXMOD2 0 : Set to "0" in event counter mode TXOCNT 0 : Set to "0" in event counter mode Symbol TXMR Address 008B16 When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol b1 b0 P30/TXOUT select bit Operation mode select bit 2 TXEDG Effectual edge reception flag TXUND Timer X under flow flag Invalid in event counter mode. When write, set "0". When read, this contents is indeterminate. Invalid in event counter mode. When write, set "0". When read, this contents is indeterminate. Note 1: This bit should rewrite with inhibiting the CNTR 0 interrupt. When using the interrupt, the interrupt must be enabled after clearing the CNTR0 interrupt request bit to "0" using a MOV instruction. Table 12.5 Specifications of event counter mode (n+1) X (m+1) Item Specification Count source External signals fed to CNTR 0 pin (Active edge is selected by software) Count operation • Down count

• When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio n: Set value of Prescaler X, m: Set value of Timer X Count start condition Count start flag is set (=1) Count stop condition Count start flag is reset (=0) Interrupt request generation timing • When Timer X underflows [Timer X interruption]
• Rising (R0EDG=0) or falling (R0EDG=1) of CNTR 0 input [CNTR0 interruption] CNTR0 pin function Count source input TXOUT pin function Programmable I/O port Read from timer Count value can be read out by reading Timer X register. Same applies to Prescaler X register. Write to timer When a value is written to Timer X register, it is written to both reload register and counter. Same applies to Prescaler X register. Select function • CNTR 0 polarity switching function The active edge of count source can be selected to be the rising or the falling edge with software. Figure 12.8 Timer X mode register in event counter mode

12.2.3 Event Counter Mode

In this mode, the timer counts an external signal fed to CNTR 0 pin. (See Table 12.5) Figure 12.8 shows Timer X mode register in event counter mode.

Rev.1.00 Oct 20, 2004 page 78 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z 1100 b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register TXMOD0 TXMOD1 Operation mode select bit 0, 1 (Note 1) 1 1 : Pulse width measurement mode R0EDG CNTR 0 polarity switching bit (Note 1) 0 : Measures "L" level width (Interrupt at rising edge) 1 : Measures "H" level width (Interrupt at falling edge) TXS Timer X count start flag 0 : Stops counting 1 : Starts counting TXMOD2 0 : Set to "0" in pulse width measurement mode TXOCNT 0 : Set to "0" in pulse width measurement mode Symbol TXMR Address 008B16 When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol b1 b0 P30/TXOUT select bit Operation mode select bit 2 TXEDG Effectual edge reception flag TXUND Timer X under flow flag Invalid in pulse width measurement mode. When write, set "0". When read, this contents is indeterminate. Invalid in pulse width measurement mode. When write, set "0". When read, this contents is indeterminate. Note 1: This bit should rewrite with inhibiting the CNTR 0 interrupt. When using the interrupt, the interrupt must be enabled after clearing the CNTR0 interrupt request bit to "0" using a MOV instruction. Item Specification Count source f 1, f8, f32, fC32 Count operation • Down count

• Continuously counts the selected signal only when the measurement pulse is "H" level, or conversely only "L" level.
• When the timer underflows, it reloads the reload register contents before continuing counting Count start condition Count start flag is set (=1) Count stop condition Count start flag is reset (=0) Interrupt request generation timing • When Timer X underflows [Timer X interruption]
• Rising (R0EDG=0) or falling (R0EDG=1) of CNTR 0 input [CNTR0 interruption] CNTR0 pin function Measurement pulse input TXOUT pin function Programmable I/O port Read from timer Count value can be read out by reading Timer X register. Same applies to Prescaler X register. Write to timer When a value is written to Timer X register, it is written to both reload register and counter. Same applies to Prescaler X register. Select function • CNTR 0 polarity switching function The measurement pulse input can be selected to be "H" level width or "L" level width by software. Table 12.6 Specifications of pulse width measurement mode

12.2.4 Pulse Width Measurement Mode

In this mode, the timer measures the pulse width of an external signal fed to CNTR0 pin. (See Table 12.6) Figure 12.9 shows the Timer X mode register in pulse width measurement mode. Figure 12.10 shows an operation example in pulse width measurement mode. Figure 12.9 Timer X mode register in pulse width measurement mode

Rev.1.00 Oct 20, 2004 page 79 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z FFFF16 n 000016 Counter contents n = high-level: the contents of Timer X reload register, low-level: the contents of Prescaler X reload register Count stop Set to "1" by software Count start Underflow Count start flag Measurement pulse (CNTR0 pin input) CNTR0 interrupt request bit Conditions: "H" level width of measurement pulse is measured. (R0EDG=1) "1" "0" Timer X interrupt request bit Cleared to "0" when interrupt request is accepted, or cleared by software "H" "L" "1" "0" "1" "0" Count stop Count restart Time Cleared to "0" when interrupt request is accepted, or cleared by software Figure 12.10 Operation example in pulse width measurement mode

Rev.1.00 Oct 20, 2004 page 80 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z Table 12.7 Specifications of pulse period measurement mode 0010 b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register TXMOD0 TXMOD1 Operation mode select bit 0, 1 (Note 1) 0 0 : Pulse period measurement mode 1 : Pulse period measurement mode R0EDG CNTR 0 polarity switching bit (Note 1) TXS Operation mode select bit 2 (Note 1) Timer X count start flag (Note 3) 0 : Stops counting 1 : Starts counting 0 : No effectual edge 1 : Effectual edge found 0 : No under flow 1 : Under flow found TXMOD2 TXOCNT 0 : In pulse period measurement mode, set to "0" Symbol TXMR Address 008B When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol b1 b0 0 : Measures a measurement pulse from one rising edge to the next rising edge (Interrupt at rising edge) 1 : Measures a measurement pulse from one falling edge to the next falling edge (Interrupt at falling edge) 0/TXOUT select bit TXEDG Effectual edge reception flag (Note 2) TXUND Timer X under flow flag (Note 2) Note 1: This bit should rewrite with inhibiting the CNTR0 interrupt. When using the interrupt, the interrupt must be enabled after clearing the CNTR0 interrupt request bit to "0" using a MOV instruction. Note 2: These bits are set to "0" by writing a "0" in a program. (Writing a "1" has no effect.) Nothing is assigned to the pod probe for M16C/1N group (M301N2T-PRB). Note 3: Execute the MOV instruction when stopping the timer X while pulse period measurement mode. Note 1: Avoid a shorter period pulse input than double prescaler X period. Longer pulse for H width and L width than the prescaler X period should be input to the CNTR0 pin. If shorter pulse than the period is input to the CNTR0 pin, the input may be disabled. Item Specification Count source f 1, f8, f32, fC32 Count operation • Down count

• After valid edge of measurement pulse is input, the timer X reloads contents in the reload register and continues counting in underflow of the second prescaler X. Count start condition Count start flag is set (=1) Count stop condition Count start flag is reset (=0) Interrupt request generation timing • When Timer X underflows [Timer X interruption]
• Rising (R0EDG=0) or falling (R0EDG=1) of CNTR0 input [CNTR0 interruption or timer X interrupt] CNTR0 pin function Measurement pulse input (Note 1) TXOUT pin function Programmable I/O port Read from timer When reading Timer X register, the count value of buffer for read purpose can be read out. The buffer of read purpose retains the content of Timer X register upon an active edge of measurement pulse, and starts to read the content of Timer X register by reading Timer X. Write to timer When a value is written to Timer X register, it is written to both reload register and counter. Same applies to Prescaler X register. Select function • CNTR 0 polarity switching function The measurement period of pulse input can be selected to be a period from one rising edge to the next rising edge or from one falling edge to the next falling edge by software.

12.2.5 Pulse Period Measurement Mode

In this mode, the timer measures the pulse period of an external signal fed to CNTR0 pin. Table 12.7 lists specifications of pulse period measurement mode. Figure 12.11 shows the Timer X mode register in pulse period measurement mode. Figure 12.12 shows the operation example. Figure 12.11 Timer X mode register in pulse period measurement mode

Rev.1.00 Oct 20, 2004 page 81 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z Figure 12.12 Operation example in pulse width measurement mode Count start flag "1" Measurement pulse (CNTR0 pin input) "0" "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software Conditions: A period from one rising edge to the next rising edge of measurement pulse is measured. (R0EDG=0) Cleared to "0" when interrupt request is accepted, or cleared by software Timer X=0F16 fPX Timer X contents 0F16 0D16 0F16 0E16 0D16 0C16 0B16 0916 0F16 0E16 0116 0016 0F16 0E16 Contents of read purpose buffer (Note 1) XX16 0B16 0916 Timer X reloads Timer X reloads Timer X reloads 0D16 0116 0F16 0E16 Timer X Read by software (Note 3) Effectual edge reception flag "1" "0" (Note 2) (Note 2) Cleared to "0" by software (Note 4) Timer X underflow flag "1" "0" Cleared to "0" by software (Note 5) (Note 6) Timer X interrupt request bit "1" "0" CNTR0 interrupt request bit "1" "0" 0A16 0A16 0016 0E16 Hold Note 1: If timer X is read out in pulse period measurement mode, the contents of the read purpose buffer can be read. Note 2: After an active edge of measurement pulse is input, effectual edge reception flag (TXEDG) is set to "1" when the prescaler X underflows for the second time. Note 3: The timer X should be read out before the next active edge is input after TXEDG is set to "1". If the timer X is not read before the next active edge is input, the value in the read purpose buffer remains unchanged and therefore is not updated on an active edge. Note 4: When set to "0" by software, use a MOV instruction to write "0" to the bit 6 (TXEDG) in the timer X mode register (008B 16). At the same time, write "1" to the bit 7 (TXUND). Note 5: When set to "0" by software, use a MOV instruction to write "0" to the bit 7 (TXUND) in the timer X more register (008B16). At the same time, write "1" to the bit 6 (TXEDG). Note 6: If the timer X underflow flag (TXUND) and TXEDG are both set to "1". In this case, the validity of TXUND should be judged by the contents of the read purpose buffer. Note 7: When setting the timer X count start flag to "1", the timer X interrupt request bit and the effectual edge reception flag may become "1". Thus, the timer X interrupt must be enabled after setting the timer X count flag to "1" and clearing the timer X interrupt request bit and the effectual edge reception flag to "0" with inhibiting the timer X interrupt. Set to "1" by software (Note 7) Count start Timer X Dummy read (Note 3)

Rev.1.00 Oct 20, 2004 page 82 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z

12.3 Timer Y

Timer Y is an 8-bit timer with an 8-bit prescaler and has two reload registers - Timer Y Primary and Timer Y Secondary. Timer Y has the two operation modes listed as follows:

• Timer mode: The timer counts an internal count source (clock source).
• Programmable waveform generation mode: The timer outputs pulses of a given width successively. Figure 12.13 shows the block diagram of Timer Y. Figures 12.14 to 12.16 show the Timer Y-related registers. Timer Y primary (address 008316) Clock source selection fRING fC32 Toggle flip-flop Port P32 register Timer Y programmable waveform output switching bit Timer Y output level latch Programmable waveform generation mode Timer Y count start flag Timer Y (address 0083 16) Timer Y interrupt request bit TYOUT Q T "1" "1" Q "0" "0" Timer Y secondary (address 008216) Counter (8) Reload register (8)Reload register (8) Counter (8) Reload register (8) Prescaler Y (address 008116) fPY Peripheral data bus Note 1: In programmable waveform generation mode, port P32 is set for output regardless of the value of the direction register. Note 2: When this bit is cleared to "0", the timer reloads the content of the reload register before it stops. Read out the count value before you stop the timer. Note 3: When timer Z operation mode bit is set for "01", "10" or "11", port P31 is set for output regardless of the value of the direction register. b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z mode register TYMOD0 Timer Y operation mode bit 0 : Timer mode 1 : Programmable waveform generation mode (Note 1) Nothing is assigned. When write, set "0". When read, the content is "0". TYWC Timer Y write control bit Function varies depending on the operation mode TYS Timer Y count start flag 0 : Stops counting (Note 2) 1 : Starts counting TZMOD0 Timer Z operation mode bit (Note 3) TZMOD1 TZWC Timer Z write control bit Function varies depending on the operation mode TZS Timer Z count start flag 0 : Stops counting (Note 2) 1 : Starts counting Symbol TYZMR Address 0080 When reset 000000X02 RW RW RW RW RW RW RW RW FunctionBit nameBit symbol b5 b4 0 0 : Timer mode 0 1 : Programmable waveform generation mode 1 0 : Programmable one-shot generation mode 1 1 : Programmable wait one-shot generation mode Figure 12.13 Block diagram of Timer Y Figure 12.14 Timer Y-related registers (1)

Rev.1.00 Oct 20, 2004 page 83 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z output control register TZOS Timer Z one-shot start bit (Note 1) TYOCNT Timer Y programmable waveform generation output switching bit (Note 2) 0 : Outputs programmable waveform 1 : Outputs the value of P3 2 port register TZOCNT Timer Z programmable waveform generation output switching bit (Note 2) 0 : Outputs programmable waveform 1 : Outputs the value of P3 1 port register 0 : Stops one-shot 1 : Starts one-shot Nothing is assigned. When write, set "0". When read, their contents are "0". Symbol TYZOC Address 008A16 When reset XXXXX0002 RW RW RW RW FunctionBit nameBit symbol Note 1: This bit is automatically cleared to "0" when the output of one-shot waveform is completed. This bit should be set to "0" by program when the one-shot waveform output is terminated by setting the count start flag to "0" during the waveform output. Note 2: This bit is valid only when operating in programmable waveform generation mode. (Note 2) b7 b0 Prescaler Y Symbol PREY Address 008116 When reset FF16 RW RW RW Function Values that can be set 0016 to FF16 0016 to FF16 (Note 1) Note 1: When using the waveform extend function, set the value "0016" for the Prescaler Y. b7 b0 Timer Y Primary Symbol TYPR Address 008316 When reset FF16 RW RW RW Function Values that can be set 0016 to FF16 0016 to FF16 Note 1: The values of Timer Y Primary and Timer Y Secondary are reloaded to the Timer Y alternately for counting. b7 b0 Timer Y Secondary Symbol TYSC Address 008216 When reset FF16 RW WO Function Values that can be set 0016 to FF16 Note 1: The values of Timer Y Primary and Timer Y Secondary are reloaded to the Timer Y alternately for counting. Note 2: The count value can be read out by reading the Timer Y Primary even when the secondary period is being counted. Timer mode Internal count source is counted Programmable waveform generation mode Internal count source is counted Timer mode Invalid Programmable waveform generation mode Underflow of Prescaler Y is counted (Note 1) Timer mode Underflow of Prescaler Y is counted Programmable waveform generation mode Underflow of Prescaler Y is counted (Note 1) Figure 12.15 Timer Y-related registers (2)

Rev.1.00 Oct 20, 2004 page 84 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z Note 1: When setting this bit to "1", the prescaler Y register must be set to "0016". Note 2: When setting this bit to "1", the prescaler Z register must be set to "0016". Note 3: When setting this bit to "1", this bit must be set to "1" after setting the INT0 input enable bit (bit 0 at address 009616), the INT0 input polarity select bit (bit 1 at address 009616), the INT0 input filter select bits (bits 0 and 1 at address 001E16) and the INT0 pin one-shot trigger polarity select bit. Note 4: This bit is valid only when the INT0 input polarity select bit (bit 1 at address 009616) is "0" (one-edge). b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z waveform output control register TYPUM0 Timer Y primary waveform extension control bit 0 : No waveform extension 1 : Waveform extension (Note 1) TYPUM1 Timer Y secondary waveform extension control bit 0 : No waveform extension 1 : Waveform extension (Note 1) TZPUM0 Timer Z primary waveform extension control bit 0 : No waveform extension 1 : Waveform extension (Note 2) TZPUM1 Timer Z secondary waveform extension control bit 0 : No waveform extension 1 : Waveform extension (Note 2) TYOPL Timer Y output level latch Function varies depending on the operation mode TZOPL Timer Z output level latch Function varies depending on the operation mode INOSTG INT 0 pin one-shot trigger control bit (Timer Z) 0 : INT 0 pin one-shot trigger invalid 1 : INT0 pin one-shot trigger valid (Note 3) INOSEG INT 0 pin one-shot trigger polarity select bit (Note 4) (Timer Z) 0 : Edge trigger at falling edge 1 : Edge trigger at rising edge Symbol PUM Address 0084 When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol Note 1: Avoid switching a count source, while a counter is in progress. Timer counter should be stopped before switching a counter source. Note 2: The waveform extend function cannot be used when selecting f1 for count source. Note 3: When attempting to select on-chip oscillator output, set the on-chip oscillation enable bit (CM14) of the system clock control register (address 000716) for oscillation enabled. Note 4: The waveform extend function cannot be used when selecting Timer Y underflow and f1 for count source. Both the Timer Y primary underflow and the Timer Y secondary underflow are counted when selecting the Timer Y underflow for count source. b7 b6 b5 b4 b3 b2 b1 b0 Timer count source setting register TXCK0 TXCK1 Timer X count source select bit (Note 1) Symbol TCSS Address 008E16 When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b1 b0 TYCK0 TYCK1 Timer Y count source select bit (Note 1, 2) 0 0 : f1 0 1 : f8 1 0 : On-chip oscillator output (Note 3) 1 1 : fC32 b3 b2 TZCK0 TZCK1 Timer Z count source select bit (Note 1, 4) 0 0 : f1 0 1 : f8 1 0 : Timer Y underflow 1 1 : fC32 b5 b4 T1CK0 T1CK1 Timer 1 count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Figure 12.16 Timer Y-related registers (3)

Rev.1.00 Oct 20, 2004 page 85 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z Table 12.8 Specifications of timer mode (n+1) X (m+1) Note 1: When the count is stopped, the Timer Y interrupt request bit becomes "1" and an interrupt may occur. Thus, interrupts must be disabled before the count is stopped. Furthermore, set the Timer Y interrupt request bit to "0" before starting counting again. Note 2: If writing to the Timer Y or prescaler Y under the following conditions being filled at the same time the Timer Y interrupt request bit becomes "1" and an interrupt occurs. <Conditions>

• Timer Y write control bit (bit 2 at address 0080 16) is "0" (write to timer and reload register simultaneously)
• Timer Y count start flag (bit 3 at address 008016) is "1" (count start) To write to the Timer Y or prescaler Y in the above state, disable interrupts before writing. Item Specification Count source f 1, f8, on-chip oscillator output, fC32 Count operation • Down count
• When the timer underflows, it reloads the reload register contents before continuing counting (When the Timer Y underflows, the contents of the Timer Y primary reload register is reloaded.)
• When a counting stops, the timer reloads the content of the reload register before it stops. Divide ratio n: Set value of Prescaler Y, m: Set value of Timer Y primary Count start condition Count start flag is set (=1) Count stop condition Count start flag is reset (=0) (Note 1) Interrupt request generation timing When Timer Y underflows TYOUT pin function Programmable I/O port Read from timer Count value can be read out by reading Timer Y primary register. Same applies to Prescaler Y register. Write to timer When a value is written to Timer Y Primary register, it is written to both reload register and counter or written to only reload register. Selected by software. Same applies to Prescaler Y register. Select function • Timer Y write control function (Note 2) When a value is written to Timer Y Primary register, it can be selected that the value is written to both reload register and counter or written to only reload register. Same applies to Prescaler Z register.

12.3.1 Timer Mode

In this mode, the timer counts an internally generated count source. (See Table 12.8) The Timer Y secondary is unused in this mode. Figure 12.17 shows the Timer Y, Z mode register and Timer Y, Z waveform output control register in timer mode.

Rev.1.00 Oct 20, 2004 page 86 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z Note 1: When this bit is "0", when you write in the prescaler Y while the timer Y is counting, the timer Y reloads the content of the timer Y reload register. Note 2: When this bit is cleared to "0", the timer reloads the content of the reload register before it stops. Read out the count value before you stop the timer. b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z mode register TYMOD0 Timer Y operation mode bit Symbol TYZMR Address 008016 When reset 000000X02 RW RW RW RW RW RW RW RW FunctionBit nameBit symbol 0 : Timer mode TYWC Nothing is assigned. When write, set "0". When read, the content is indeterminate. Timer Y write control bit TYS Timer Y count start flag TZMOD0 TZMOD1 TZWC TZS Timer Z-related bit 0 : Stops counting (Note 2) 1 : Starts counting 0 : Write to timer and reload register simultaneously (Note 1) 1 : Write to reload register b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z waveform output control register TYPUM0 Timer Y primary waveform extension control bit Symbol PUM Address 0084 When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol Invalid in timer mode TZPUM0 Timer Z-related bits TZPUM1 TYPUM1 Timer Y secondary waveform extension control bit Invalid in timer mode TZOPL Timer Z-related bits INOSEG INOSTG TYOPL Timer Y output level latch Invalid in timer mode Figure 12.17 Timer Y, Z mode register in timer mode and Timer Y, Z waveform output control register

Rev.1.00 Oct 20, 2004 page 87 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z fi Note 1: When the count is stopped, the Timer Y interrupt request bit becomes "1" and an interrupt may occur. Thus, interrupts must be disabled before the count is stopped. Furthermore, set the Timer Y interrupt request bit to "0" before starting counting again. Note 2: When the counting stopped, the pin is the secondary period output level. Note 3: Even when counting the secondary period, read out the Timer Y primary register. Note 4: The set value of Timer Y secondary register and waveform extension control bits as well as Timer Y primary register are made effective by writing a value to the Timer Y primary register. The written values are reflected to the waveform output from the next primary period after writing to the Timer Y primary register. Note 5: The output is switched in sync with Timer Y secondary underflow. Note 6: When using the waveform extend function, the Prescaler Y register must be set to "00 16". Item Specification Count source f 1, f8, on-chip oscillator output, fC32 Count operation • Down count

• When the timer underflows, it reloads the contents of primary reload register and sec- ondary reload register alternately before continuing counting.
• When a counting stops, the timer reloads the content of the reload register before it stops. Divide ratio n: Set value of Prescaler Y, m: Set value of Timer Y primary, l: Set value of Timer Y secondary Count start condition Count start flag is set (=1) Count stop condition Count start flag is reset (=0) (Note 1) Interrupt request generation timing When Timer Y underflows during secondary period TYOUT pin function Pulse output (Note 2) Read from timer Count value can be read out by reading Timer Y primary register. Same applies to Prescaler Y register. (Note 3) Write to timer When a value is written to Timer Y primary register, it is written to only reload register. Same applies to Timer Y secondary register and Prescaler Y register. (Note 4) Select function • Output level latch select function The output level of a waveform being counted during primary and secondary periods is selectable.
• Programmable waveform generation output switching function (Note 5) Can select either programmable waveform or the value of port P32 register for output.
• Waveform extend function (Note 6) The waveform output primary period and secondary period can each be extended 0.5 cycles of the count source. Frequency when waveform extended: 2xfi/((2x(m+1))+(2x(l+1))+TYPUM0+TYPUM1) Duty: (2x(m+1)+TYPUM0)/((2x(m+1)+TYPUM0)+(2x(l+1)+TYPUM1)) m: set value of Timer Y primary, l: set value of Timer Y secondary TYPUM0: Timer Y primary waveform extension control bit TYPUM1: Timer Y secondary waveform extension control bit

12.3.2 Programmable Waveform Generation Mode

In this mode, the microcontroller, while counting the set values of Timer Y primary and Timer Y sec- ondary alternately, outputs from the TY OUT pin a waveform whose polarity is inverted each time Timer Y secondary underflows. (See Table 12.9) A counting starts by counting the set value in the Timer Y primary. Figure 12.18 shows Timer Y, Z mode register in programmable waveform generation mode. Figure 12.19 shows the operation example. Table 12.9 Specifications of programmable waveform generation mode

Rev.1.00 Oct 20, 2004 page 88 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z mode register TYMOD0 Nothing is assigned. When write, set "0". When read, the content is indeterminate. Timer Y operation mode bit Timer Y write control bit TYWC Symbol TYZMR Address 008016 When reset 000000X02 RW RW RW RW RW RW RW RW FunctionBit nameBit symbol 1 : Programmable waveform generation mode (Note 1) TYS Timer Y count start flag TZMOD0 TZMOD1 TZWC TZS Timer Z-related bit 0 : Stops counting (Note 2) 1 : Starts counting Note 1: Output is set for Port P32 regardless of the value of the direction register. Note 2: When this bit is cleared to "0", the timer reloads the content of the reload register before it stops. Read out the count value before you stop the timer. 1 : Set to "1" in programmable waveform generation mode b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z waveform output control register TYPUM0 Timer Y primary waveform extension control bit Symbol PUM Address 0084 When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol 0 : No waveform extension 1 : Waveform extension (Note 1, 2) TYPUM1 Timer Y secondary waveform extension control bit TZPUM0 Timer Z-related bits TZOPL Timer Z-related bits INOSTG INOSEG TZPUM1 0 : No waveform extension 1 : Waveform extension (Note 1, 2) TYOPL Timer Y output level latch Note 1: When setting this bit to "1", the Prescaler Y Register must be set to "00 16". Note 2: The waveform extend function cannot be used when selecting f1 for count source. 0 : Outputs "H" for the period set by Timer Y primary and "L" for the period set by Timer Y secondary. "L" is outputted when the timer is stopped. 1 : Outputs "L" for the period set by Timer Y primary and "H" for the period set by Timer Y secondary. "H" is outputted when the timer is stopped. Figure 12.18 Timer Y, Z mode register and Timer Y, Z waveform output control register in programmable waveform generation mode

Rev.1.00 Oct 20, 2004 page 89 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z Set to "1" by software Count start flag The contents of Timer Y TYOUT pin output "1" "0" Timer Y interrupt request bit "H" "L" "1" "0" "1" "0" 02160316 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 Count start fPY Timer Y output level latch Cleared to "0" by software Timer Y secondary reload Timer Y primary reload Timer Y secondary reload Cleared to "0" when interrupt request is accepted, or cleared by software Waveform output started Waveform output inverted Waveform output inverted (Note 1) Waveform output inverted Initialized to "L" Secondary waveform extended Note 1: The waveform output in the secondary period is inverted after 0.5 clock (1 clock when secondary waveform extended) of f PY from occurrence of Timer Y interrupt request. Conditions: Timer Y primary=0316, Timer Y primary waveform not extended, Timer Y secondary=0216, Timer Y secondary waveform extended, Timer Y output level latch [TYOPL]=0 Figure 12.19 Timer Y operation example in programmable waveform generation mode Programmable waveform generation output switching function When the Timer Y programmable waveform generation output switching bit (bit 1 at address 008A16) is set to 0, the output from TYOUT is inverted synchronously when the Timer Y secondary underflows. And when set to 1, the Port P32 register value is output from TYOUT synchronously when the Timer Y secondary underflows.

Rev.1.00 Oct 20, 2004 page 90 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z Timer Z primary (address 008716) Clock source selection Timer Y underflow fC32 Toggle flip-flop Port P31 register Timer Z programmable waveform output switchin g bit Timer Z output level latch Timer Z count start flag Timer Z interrupt request bit Timer Z secondary (address 008616) TZOUT INT0 Q T"0" "1" "1" Q"0" Peripheral data bus Reload register (8)Reload register (8)Reload register (8) Timer Z (address 008716) Counter (8)Counter (8) Prescaler Z (address 008516) Programmable one-shot generation mode Programmable wait one-shot generation mode Timer Z one-shot start bit INT0 input enable bit INT0 input polarity select bit One edge/ both edges input polarity select Digital filter Polarity select INT0 one-shot trigger polarity select bit fPZ Programmable waveform generation mode Programmable one-shot generation mode Programmable wait one-shot generation mode

12.4 Timer Z

Timer Z is an 8-bit timer with an 8-bit prescaler and has two reload registers - Timer Z Primary and Timer Z Secondary. Timer Z has the four operation modes listed as follows:

• Timer mode: The timer counts an internal count source (clock source) or Timer Y underflow.
• Programmable waveform generation mode: The timer outputs pulses of a given width successively.
• Programmable one-shot generation mode: The timer outputs one-shot pulse.
• Programmable wait one-shot generation mode: The timer outputs delayed one-shot pulse. Figure 12.20 shows the block diagram of Timer Z. Figures 12.21 to 12.24 show the Timer Z-related registers. Figure 12.20 Block diagram of Timer Z

Rev.1.00 Oct 20, 2004 page 91 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z Note 1: In programmable waveform generation mode, port P32 is set for output regardless of the value of the direction register. Note 2: When this bit is cleared to "0", the timer reloads the content of the reload register before it stops. Read out the count value before you stop the timer. Note 3: When timer Z operation mode bit is set for "01", "10" or "11", port P31 is set for output regardless of the value of the direction register. b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z mode register TYMOD0 Timer Y operation mode bit 0 : Timer mode 1 : Programmable waveform generation mode (Note 1) Nothing is assigned. When write, set "0". When read, the content is "0". TYWC Timer Y write control bit Function varies depending on the operation mode TYS Timer Y count start flag 0 : Stops counting (Note 2) 1 : Starts counting TZMOD0 Timer Z operation mode bit (Note 3) TZMOD1 TZWC Timer Z write control bit Function varies depending on the operation mode TZS Timer Z count start flag 0 : Stops counting (Note 2) 1 : Starts counting Symbol TYZMR Address 0080 When reset 000000X02 RW RW RW RW RW RW RW RW FunctionBit nameBit symbol b5 b4 0 0 : Timer mode 0 1 : Programmable waveform generation mode 1 0 : Programmable one-shot generation mode 1 1 : Programmable wait one-shot generation modeFigure 12.21 Timer Z-related registers (1)

Rev.1.00 Oct 20, 2004 page 92 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z (Note 1) (Note 1) (Note 1) b7 b0 Prescaler Z Symbol PREZ Address 008516 When reset FF16 RW RW RW RW RW Function Values that can be set Timer mode Internal count source or Timer Y underflow is counted 0016 to FF16 Programmable waveform generation mode Internal count source or Timer Y underflow is counted 0016 to FF16 Programmable one-shot generation mode Internal count source or Timer Y underflow is counted 0016 to FF16 Programmable wait one-shot generation mode Internal count source or Timer Y underflow is counted 0016 to FF16 Note 1: When using the waveform extend function, set the value "0016" for the Prescaler Z. b7 b0 Timer Z Primary Symbol TZPR Address 008716 When reset FF16 RW RW RW RW RW Function Values that can be set 0016 to FF16 0016 to FF16 Note 1: Each value of Timer Z Primary and Timer Z Secondary is reloaded to the Timer Z alternately for counting. b7 b0 Timer Z Secondary Symbol TZSC Address 008616 When reset FF16 RW WO WO Function Values that can be set Timer mode Invalid Programmable waveform generation mode Underflow of Prescaler Z is counted (Note 1) 0016 to FF16 Programmable one-shot generation mode Invalid Programmable wait one-shot generation mode Underflow of Prescaler Z is counted (One-shot width is counted) 16 to FF16 0016 to FF16 0016 to FF16 Note 1: Each value of Timer Z Primary and Timer Z Secondary is reloaded to the Timer Z alternately for counting. Note 2: The count value can be read out by reading the Timer Z Primary even when the secondary period is being counted. Timer mode Underflow of Prescaler Z is counted Programmable waveform generation mode Underflow of Prescaler Z is counted (Note 1) Programmable one-shot generation mode Underflow of Prescaler Z is counted (One-shot width is counted) Programmable wait one-shot generation mode Underflow of Prescaler Z is counted (Wait period is counted) (Note 2) Figure 12.22 Timer Z-related registers (2)

Rev.1.00 Oct 20, 2004 page 93 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z Note 1: When setting this bit to "1", the prescaler Y register must be set to "0016". Note 2: When setting this bit to "1", the prescaler Z register must be set to "0016". Note 3: When setting this bit to "1", this bit must be set to "1" after setting the INT0 input enable bit (bit 0 at address 009616), the INT0 input polarity select bit (bit 1 at address 009616), the INT0 input filter select bits (bits 0 and 1 at address 001E16) and the INT0 pin one-shot trigger polarity select bit. Note 4: This bit is valid only when the INT0 input polarity select bit (bit 1 at address 009616) is "0" (one-edge). b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z waveform output control register TYPUM0 Timer Y primary waveform extension control bit 0 : No waveform extension 1 : Waveform extension (Note 1) TYPUM1 Timer Y secondary waveform extension control bit 0 : No waveform extension 1 : Waveform extension (Note 1) TZPUM0 Timer Z primary waveform extension control bit 0 : No waveform extension 1 : Waveform extension (Note 2) TZPUM1 Timer Z secondary waveform extension control bit 0 : No waveform extension 1 : Waveform extension (Note 2) TYOPL Timer Y output level latch Function varies depending on the operation mode TZOPL Timer Z output level latch Function varies depending on the operation mode INOSTG INT 0 pin one-shot trigger control bit (Timer Z) 0 : INT 0 pin one-shot trigger invalid 1 : INT0 pin one-shot trigger valid (Note 3) INOSEG INT 0 pin one-shot trigger polarity select bit (Note 4) (Timer Z) 0 : Edge trigger at falling edge 1 : Edge trigger at rising edge Symbol PUM Address 0084 When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol Note 1: Avoid switching a count source, while a counter is in progress. Timer counter should be stopped before switching a counter source. Note 2: The waveform extend function cannot be used when selecting f1 for count source. Note 3: When attempting to select on-chip oscillator output, set the on-chip oscillation enable bit (CM14) of the system clock control register (address 000716) for oscillation enabled. Note 4: The waveform extend function cannot be used when selecting Timer Y underflow and f1 for count source. Both the Timer Y primary underflow and the Timer Y secondary underflow are counted when selecting the Timer Y underflow for count source. b7 b6 b5 b4 b3 b2 b1 b0 Timer count source setting register TXCK0 TXCK1 Timer X count source select bit (Note 1) Symbol TCSS Address 008E16 When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b1 b0 TYCK0 TYCK1 Timer Y count source select bit (Note 1, 2) 0 0 : f1 0 1 : f8 1 0 : On-chip oscillator output (Note 3) 1 1 : fC32 b3 b2 TZCK0 TZCK1 Timer Z count source select bit (Note 1, 4) 0 0 : f1 0 1 : f8 1 0 : Timer Y underflow 1 1 : fC32 b5 b4 T1CK0 T1CK1 Timer 1 count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Figure 12.23 Timer Z-related registers (3)

Rev.1.00 Oct 20, 2004 page 94 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z output control register TZOS Timer Z one-shot start bit (Note 1) TYOCNT Timer Y programmable waveform generation output switching bit (Note 2) 0 : Outputs programmable waveform 1 : Outputs the value of P3 2 port register TZOCNT Timer Z programmable waveform generation output switching bit (Note 2) 0 : Outputs programmable waveform 1 : Outputs the value of P3 1 port register 0 : Stops one-shot 1 : Starts one-shot Nothing is assigned. When write, set "0". When read, their contents are "0". Symbol TYZOC Address 008A16 When reset XXXXX0002 RW RW RW RW FunctionBit nameBit symbol Note 1: This bit is automatically cleared to "0" when the output of one-shot waveform is completed. This bit should be set to "0" by program when the one-shot waveform output is terminated by setting the count start flag to "0" during the waveform output. Note 2: This bit is valid only when operating in programmable waveform generation mode. b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 External input enable register INT0EN INT 0 input enable bit (Note 1) 0 : Disabled 1 : Enabled INT0F0 INT0F1 INT0 input filter select bit INT0PL INT 0 input polarity select bit (Note 1) 0 : One edge 1 : Two edges INT1EN INT 1 input enable bit 0 : Disabled 1 : Enabled INT1PL INT 1 input polarity select bit 0 : One edge 1 : Two edges INT2EN INT 2 input enable bit 0 : Disabled 1 : Enabled INT2PL INT 2 input polarity select bit 0 : One edge 1 : Two edges INT3EN INT 3 input enable bit 0 : Disabled 1 : Enabled INT0F2 UART0 receive hardware interrupt enable bit (Note 1) 0 : Disabled 1 : Enabled INT3PL INT 3 input polarity select bit 0 : One edge 1 : Two edges Nothing is assigned. When write, nothing can be written. When read, their contents are indeterminate. Symbol INTEN Address 009616 When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol INT0 input filter select register Symbol INT0F Address 001E16 When reset XXXXX0002 RW RW RW RW FunctionBit nameBit symbol 0 0 : No filter 0 1 : Filter with f1 sampling 1 0 : Filter with f8 sampling 1 1 : Filter with f32 sampling b1 b0 Note 1: Interrupts used for debugging purposes only. Be sure to set "0" to this bit. Note 1: This bit must be set in condition of the INT0 pin one-shot trigger control bit (bit 6 at address 008416)="0" (INT0 pin one-shot trigger invalid). Figure 12.24 Timer Z-related registers (4)

Rev.1.00 Oct 20, 2004 page 95 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z (n+1) X (m+1) Note 1: When the count is stopped, the Timer Z interrupt request bit becomes "1" and an interrupt may occur. Thus, interrupts must be disabled before the count is stopped. Furthermore, set the Timer Z interrupt request bit to "0" before starting counting again. Note 2: If writing to the Timer Z or prescaler Z under the following conditions being filled at the same time the Timer Z interrupt request bit becomes "1" and an interrupt occurs. <Conditions>

• Timer Z write control bit (bit 6 at address 0080 16) is "0" (write to timer and reload register simultaneously)
• Timer Z count start flag (bit 7 at address 008016) is "1" (count start) To write to the Timer Z or prescaler Z in the above state, disable interrupts before writing. Item Specification Count source f 1, f8, Timer Y underflow, fC32 Count operation • Down count
• When the timer underflows, it reloads the reload register contents before continuing counting (When the Timer Z underflows, the contents of the Timer Z primary reload register is reloaded.)
• When a counting stops, the timer reloads the content of the reload register before stopping counting. Divide ratio n: Set value of Prescaler Z, m: Set value of Timer Z primary Count start condition Count start flag is set (=1) Count stop condition Count start flag is reset (=0) (Note 1) Interrupt request generation timing When Timer Z underflows TYOUT pin function Programmable I/O port INT0 pin function Programmable I/O port, or external interrupt input pin Read from timer Count value can be read out by reading Timer Z primary register. Same applies to Prescaler Z register. Write to timer When a value is written to Timer Z Primary register, it is written to both reload register and counter or written to only reload register. Selected by software. Same applies to Prescaler Z register. Select function • Timer Z write control function (Note 2) When a value is written to Timer Z Primary register, it can be selected that the value is written to both reload register and counter or written to only reload register. Same applies to Prescaler Z register.

12.4.1 Timer Mode

In this mode, the timer counts an internally generated count source or Timer Y underflow. (See Table 12.10) The Timer Z secondary is unused in this mode. Figure 12.25 shows the Timer Y, Z mode register and Timer Y, Z waveform output control register in timer mode. Table 12.10 Specifications of timer mode

Rev.1.00 Oct 20, 2004 page 96 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z mode register TYMOD0 Nothing is assigned. When write, set "0". When read, the content is "0". Timer Y-related bit TYWC Timer Y-related bits Symbol TYZMR Address 008016 When reset 000000X02 RW RW RW RW RW RW RW RW FunctionBit nameBit symbol TYS Timer Z count start flag Timer Z write control bit TZMOD0 TZMOD1 TZWC TZS Timer Z operation mode bit 0 : Stops counting (Note 2) 1 : Starts counting Note 1: At this bit is "0", when you write in the prescaler Z while the timer Z is counting, the timer Z reloads content of the timer Z reload register. Note 2: When this bit is cleared to "0", the timer reloads the content of the reload register before it stops. Read out the count value before you stop the timer. 0 : Write to timer and reload register simultaneously (Note 1) 1 : Write to reload register 0 0 : Timer mode b5 b4 b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z waveform output control register TYPUM0 TYPUM1 Timer Y-related bits Timer Y-related bit Timer Z primary waveform extension control bit Invalid in timer mode Timer Z secondary waveform extension control bit Invalid in timer mode Timer Z output level latch Invalid in timer mode INT 0 pin one-shot trigger control bit Invalid in timer mode INT0 pin one-shot trigger polarity select bit Invalid in timer mode TZPUM0 Symbol PUM Address 008416 When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol TZPUM1 TYOPL TZOPL INOSTG INOSEG Figure 12.25 Timer Y, Z mode register and Timer Y, Z waveform output control register in timer mode

Rev.1.00 Oct 20, 2004 page 97 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z fi Note 1: When the count is stopped, the Timer Z interrupt request bit becomes "1" and an interrupt may occur. Thus, interrupts must be disabled before the count is stopped. Furthermore, set the Timer Z interrupt request bit to "0" before starting counting again. Note 2: When the counting stopped, the pin is the secondary period output level. Note 3: Even when counting the secondary period, read out the Timer Z primary register. Note 4: The set value of Timer Z secondary register and waveform extension control bits as well as Timer Z primary register are made effective by writing a value to the Timer Z primary register. The written values are reflected to the waveform output from the next primary period after writing to the Timer Z primary register. Note 5: The output is switched in sync with Timer Z secondary underflow. Note 6: When using the waveform extend function, the Prescaler Z register must be set to "00 16". When selecting Timer Y underflow and f1 for the count source, the waveform extend function cannot be used. Item Specification Count source f 1, f8, Timer Y underflow, fC32 Count operation • Down count

• When the timer underflows, it reloads the contents of primary reload register and sec- ondary reload register alternately before continuing counting.
• When a counting stops, the timer reloads the content of the reload register before it stops. Divide ratio n: Set value of Prescaler Z, m: Set value of Timer Z primary, l: Set value of Timer Z secondary Count start condition Count start flag is set (=1) Count stop condition Count start flag is reset (=0) (Note 1) Interrupt request generation timing When Timer Z underflows during secondary period TZOUT pin function Pulse output (Note 2) INT0 pin function Programmable I/O port, or external interrupt input pin Read from timer Count value can be read out by reading Timer Z primary register. Same applies to Prescaler Z register. (Note 3) Write to timer When a value is written to Timer Z primary register, it is written to only reload register. Same applies to Timer Z secondary register and Prescaler Z register. (Note 4) Select function • Output level latch select function The output level of an waveform being counted during primary and secondary periods is selectable.
• Programmable waveform generation output switching function (Note 5) Can select either programmable waveform or the value of port P31 register for output.
• Waveform extend function (Note 6) The waveform output primary and secondary periods can each be extended 0.5 cycles of the count source. Frequency when waveform extended: 2xfi/((2x(m+1))+(2x(l+1))+TZPUM0+TZPUM1) Duty: (2x(m+1)+TZPUM0)/((2x(m+1)+TZPUM0)+(2x(l+1)+TZPUM1)) m: set value of Timer Z primary, l: set value of Timer Z secondary TZPUM0: Timer Z primary waveform extension control bit TZPUM1: Timer Z secondary waveform extension control bit

12.4.2 Programmable Waveform Generation Mode

In this mode, the microcontroller, while counting the set values of Timer Z primary and Timer Z sec- ondary alternately, outputs from the TZ OUT pin a waveform whose polarity is inverted each time Timer Z secondary underflows. (See Table 12.11) A counting starts by counting the value set in the Timer Z primary. Figure 12.26 shows Timer Y, Z mode register and Timer Y, Z waveform output control regis- ter in this mode. The Timer Z operates in the same way as the Timer Y in this mode. See Figure 12.19 shown the Timer Y operating example in programmable waveform generation mode. Table 12.11 Specifications of programmable waveform generating mode

Rev.1.00 Oct 20, 2004 page 98 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z mode register TYMOD0 Nothing is assigned. When write, set "0". When read, the content is "0". Timer Y-related bit Timer Z operation mode bit Timer Y-related bits Timer Z count start flag Timer Z write control bit TYWC Symbol TYZMR Address 008016 When reset 000000X02 RW RW RW RW RW RW RW RW FunctionBit nameBit symbol TYS TZMOD0 TZWC TZS TZMOD1 101 Note 1: When selecting programmable waveform generation mode, output is set for Port P31 regardless of the value of the direction register. Note 2: When this bit is cleared to "0", the timer reloads the content of the reload register before it stops. Read out the count value before you stop the timer. 0 : Stops counting (Note 2) 1 : Starts counting 0 1 : Programmable waveform generation mode (Note 1) b5 b4 1 : Set to "1" in programmable waveform generation mode b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z waveform output control register TYPUM0 Symbol PUM Address 008416 When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol 0 : No waveform extension 1 : Waveform extension (Note 1) Invalid in programmable waveform generation mode Invalid in programmable waveform generation mode TYPUM1 TZPUM0 Timer Z primary waveform extension control bit Timer Y-related bits Timer Y-related bit TZOPL Timer Z output level latch INT 0 pin one-shot trigger control bit INT0 pin one-shot trigger polarity select bit INOSTG INOSEG TZPUM1 0 : No waveform extension 1 : Waveform extension (Note 1) TYOPL Timer Z secondary waveform extension control bit 0 : Outputs "H" for the period set by Timer Z primary and "L" for the period set by Timer Z secondary. "L" is outputted when the timer is stopped. 1 : Outputs "L" for the period set by Timer Z primary and "H" for the period set by Timer Z secondary. "H" is outputted when the timer is stopped. Note 1: When setting this bit to "1", the Prescaler Z Register must be set to "0016". Figure 12.26 Timer Y, Z mode register and Timer Y, Z waveform output control register in programmable waveform generation mode

Rev.1.00 Oct 20, 2004 page 99 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z Item Specification Count source f 1, f8, Timer Y underflow, fC32 Count operation • Down counts the set value of Timer Z primary

• When the timer underflows, it reloads the contents of reload register before stopping counting.
• When a counting stops, the timer reloads the contents of the reload register before it stops. Divide ratio n: Set value of Prescaler Z, m: Set value of Timer Z primary Count start condition • Timer Z one-shot start bit is set (=1) (Note 1)
• Valid trigger is input to INT0 pin (Note 2) Count stop condition • When reloading is completed after count value was set to "00 16"
• When Count start flag is reset (=0)
• Timer Z one-shot start bit is reset (=0) (Note 3) Interrupt request generation timing When count value becomes "0016" TZOUT pin function Pulse output INT0 pin function Programmable I/O port, external interrupt input pin, or external trigger input pin Read from timer Count value can be read out by reading Timer Z primary register. Same applies to Prescaler Z register. Write to timer When a value is written to Timer Z primary register, it is written to only reload register. Same applies to Prescaler Z register. (Note 4) Select function • Output level latch select function The output level of one-shot pulse waveform is selectable.
• INT0 pin one-shot trigger control function and polarity select function The trigger input from the INT0 pin can be set to valid or invalid. Also, the valid trigger's polarity can be chosen to be the rising edge, falling edge, or rising and falling both edges.
• Waveform extend function (Note 5) The one-shot pulse waveform can be extended 0.5 cycles of the count source. Frequency when waveform extended: 2xfi/(n+1)/(2x(m+1)+TZPUM0) n: set value of Prescaler Z, m: set value of Timer Z primary TZPUM0: Timer Z primary waveform extension control bit (n+1) X (m+1) Note 2: Count start flag must have been set to "1", INT0 input enable bit [INT0EN] to "1", and INT0 pin one-shot trigger control bit to "1". Note 3: When the count is stopped by writing "0" to the count start flag or Timer Z one-shot start bit, the Timer Z interrupt request bit becomes "1" and an interrupt may occur. Thus, interrupts must be disabled before the count is stopped. Furthermore, set the Timer Z interrupt request bit to "0" before starting counting again. Note 4: Each set value becomes effective by writing to the Timer Z primary register. And the set values are reflected collectively beginning with the next one-shot pulse after writing to the Timer Z primary. Note 5: When using the waveform extend function, the Prescaler Z register must be set to "00 16". When selecting Timer Y underflow and f1 for the count source, the waveform extend function cannot be used.

12.4.3 Programmable One-shot Generation Mode

In this mode, upon software command or external trigger input (input to the INT0 pin), the microcom- puter outputs the one-shot pulse from the TZ OUT pin. (See Table 12.12) When a trigger occurs, the timer starts operating from the point only once for a given period equal to the set value of the Timer Z primary. Timer Z secondary is unused in this mode. Table 12.12 lists specifications of programmable one-shot generating mode. Figure 12.27 shows the Timer Y, Z mode register and Timer Y, Z waveform output control register in this mode. Figure 12.28 shows the Timer Z operation example in this mode. Table 12.12 Specifications of programmable one-shot generating mode

Rev.1.00 Oct 20, 2004 page 100 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z 101 Note 1: When selecting programmable one-shot generation mode, output is set for Port P31 regardless of the value of the direction register. Note 2: When this bit is cleared to "0", the timer reloads the content of the reload register before it stops. Read out the count value before you stop the timer. b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z mode register TYMOD0 Nothing is assigned. When write, set "0". When read, the content is "0". Timer Y-related bit 0 : Stops counting (Note 2) 1 : Starts counting TYWC Timer Y-related bits TZMOD0 Timer Z operation mode bit Timer Z count start flag Timer Z write control bit TZMOD1 TZWC TZS TYS Symbol TYZMR Address 008016 When reset 000000X02 RW RW RW RW RW RW RW RW FunctionBit nameBit symbol b5 b4 1 0 : Programmable one-shot generation mode (Note 1) 1 : Set to "1" in programmable one-shot generation mode Note 1: When setting this bit to "1", the Prescaler Z Register must be set to "0016". Note 2: When changing this bit to "1", set the INT0 input filter select bit (bit 0 at address 009616), the INT0 input polarity select bit ( bit 1 at address 009616), the INT0 input filter select bit (bits 0 and 1 at address 001E16) and the INT0 pin one-shot trigger polarity select bit. Note 3: This bit is valid only when the INT0 input polarity select bit (bit 1 at address 009616) is "0" (one-edge). b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z waveform output control register TYPUM0 Timer Y-related bits 0 : INT0 pin one-shot trigger invalid 1 : INT0 pin one-shot trigger valid (Note 2) 0 : No waveform extension 1 : Waveform extension (Note 1) TYOPL Timer Y-related bit TZPUM0 Timer Z primary waveform extension control bit TZOPL Timer Z output level latch INOSTG INT 0 pin one-shot trigger control bit Invalid in programmable one-shot generation mode TZPUM1 Timer Z secondary waveform extension control bit 0 : Edge trigger at falling edge 1 : Edge trigger at rising edge INOSEG INT 0 pin one-shot trigger polarity select bit (Note 3) TYPUM1 Symbol PUM Address 0084 When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol 0 : Outputs "H" level one-shot pulse. "L" is outputted when the timer is stopped. 1 : Outputs "L" level one-shot pulse "H" is outputted when the timer is stopped. Figure 12.27 Timer Y, Z mode register and Timer Y, Z waveform output control register in programmable one-shot generation mode

Rev.1.00 Oct 20, 2004 page 101 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z Count start flag The contents of Timer Z TZOUT pin output "1" "0" Timer Z interrupt request bit "H" "L" "1" "0" "1" "0" fPZ Timer Z output level latch Initialized to "L" Primary waveform extended 02160316 0116 0016 0316 0216 0116 0016 Set to "1" by software Set to "1" by software Count start One-shot start bit "1" "0" INT 0 pin input "1" "0" Timer Z primary reload Timer Z primary reload Count start Cleared to "0" when counting completed Set to "1" by INT 0 pin input trigger Cleared to "0" when interrupt request is accepted, or cleared by software Cleared to "0" by software Primary waveform extended Waveform output ends Waveform output starts Waveform output starts Waveform output ends Conditions: Timer Z primary=0316, Timer Z primary waveform extended, Timer Z output level latch [TZOPL]=0, INT0 one-shot trigger is valid at rising edge, INT0 input filter select bit [INT0F0, INT0F1]=002 (No filter) Figure 12.28 Operation example in programmable one-shot generation mode

Rev.1.00 Oct 20, 2004 page 102 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z Note 2: Count start flag must have been set to "1", INT0 input enable bit [INT0EN] to "1", and INT0 pin one-shot trigger control bit to "1". Note 3: When the count is stopped by writing "0" to the count start flag or Timer Z one-shot start bit, the Timer Z interrupt request bit becomes "1" and an interrupt may occur. Thus, interrupts must be disabled before the count is stopped. Furthermore, set the Timer Z interrupt request bit to "0" before starting counting again. Note 4: Each set value becomes effective by writing to the Timer Z primary register. And the set values are reflected collectively beginning with the next one-shot pulse after writing to the Timer Z primary. Note 5: When using the waveform extend function, the Prescaler Z register must be set to "0016". When selecting Timer Y underflow and f1 for the count source, the waveform extend function cannot be used. Item Specification Count source f 1, f8, Timer Y underflow, fC32 Count operation • Down counts the set value of Timer Z primary

• When Timer Z primary underflows, the contents of Timer Z secondary is reloaded be- fore continuing counting.
• When Timer Z secondary underflows, the contents of Timer Z primary is reloaded be- fore stopping counting.
• When a counting stops, the timer reloads the contents of the reload register before it stops. Wait time (n+1) x (m+1)/fi, n: Set value of Prescaler Z, m: Set value of Timer Z primary One-shot pulse output time (n+1) x (l+1))/fi, n: Set value of Prescaler Z, l: Set value of Timer Z secondary Count start condition • Timer Z one-shot start bit is set (=1) (Note 1)
• Valid trigger is input to INT0 pin (Note 2) Count stop condition • When reloading is completed after count value at counting Timer Z secondary was set to "0016"
• When Count start flag is reset (=0)
• Timer Z one-shot start bit is reset (=0) (Note 3) Interrupt request generation timing When count value at counting Timer Z secondary becomes "0016" TZOUT pin function Pulse output INT0 pin function Programmable I/O port, external interrupt input pin, or external trigger input pin Read from timer Count value can be read out by reading Timer Z primary register. Same applies to Prescaler Z register. Write to timer When a value is written to Timer Z primary register, it is written to only reload register. Same applies to Prescaler Z register. (Note 4) Select function • Output level latch select function The output level of one-shot pulse waveform is selectable.
• INT0 pin one-shot trigger control function and polarity select function The trigger input from the INT0 pin can be set to valid or invalid. Also, the valid trigger's polarity is selectable: rising edge, falling edge, or rising and falling both edges.
• Waveform extend function (Note 5) Waiting time and one-shot pulse waveform can each be extended 0.5 cycles of the count source. Waiting time when waveform extended: (n+1) x (2x(m+1)+TZPUM0)/2fi One-shot pulse output time when waveform extended: (n+1) x (2x(l+1)+TZPUM1)/2fi n: set value of Prescaler Z, m: set value of Timer Z primary, l: set value of Timer Z secondary TZPUM0: Timer Z primary waveform extension control bit, TZPUM1: Timer Z secondary waveform extension control bit

12.4.4 Programmable Wait One-shot Generation Mode

In this mode, upon software command or external trigger input (input to the INT0 pin), the microcom- puter outputs the one-shot pulse from the TZOUT pin after waiting for a given length of time. (See Table 12.13) When a trigger occurs, from this point, the timer starts outputting pulses only once for a given length of time equal to the Timer Z primary set value after waiting for a given length of time equal to the Timer Z primary set value. Figure 16.29 shows the Timer Y, Z mode register and Timer Y, Z waveform output control register in this mode. Figure 12.30 shows the Timer Z operation example in this mode. Table 12.13 Specifications of programmable wait one-shot generating mode

Rev.1.00 Oct 20, 2004 page 103 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z Note 1: When selecting programmable wait one-shot generation mode, output is set for Port P31 regardless of the value of the direction register. Note 2: When this bit is cleared to "0", the timer reloads the content of the reload register before it stops. Read out the count value before you stop the timer. b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z mode register TYMOD0 Nothing is assigned. When write, set "0". When read, the content is "0". Timer Y-related bit 0 : Stops counting (Note 2) 1 : Starts counting TZMOD0 Timer Z operation mode bit TZWC Timer Z write control bit TZS Timer Z count start flag TZMOD1 TYWC Timer Y-related bits TYS Symbol TYZMR Address 008016 When reset 000000X02 RW RW RW RW RW RW RW RW FunctionBit nameBit symbol 111 b5 b4 1 1 : Programmable wait one-shot generation mode (Note 1) 1 : Set to "1" in programmable wait one-shot generation mode b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z waveform output control register TYPUM0 Timer Y-related bits TYOPL Timer Y-related bit TZPUM0 Timer Z primary waveform extension control bit 0 : No waveform extension 1 : Waveform extension (Note 1) TZPUM1 Timer Z secondary waveform extension control bit 0 : No waveform extension 1 : Waveform extension (Note 1) INOSTG INT 0 pin one-shot trigger control bit 0 : INT0 pin one-shot trigger invalid 1 : INT0 pin one-shot trigger valid (Note 2) INOSEG INT 0 pin one-shot trigger polarity select bit (Note 3) 0 : Edge trigger at falling edge 1 : Edge trigger at rising edge TZOPL Timer Z output level latch TYPUM1 Symbol PUM Address 0084 When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol 0 : Outputs "H" level one-shot pulse. "L" is outputted when the timer is stopped. 1 : Outputs "L" level one-shot pulse. "H" is outputted when the timer is stopped. Note 1: When setting this bit to "1", the Prescaler Z Register must be set to "0016". Note 2: When changing this bit to "1", set the INT0 input filter select bit (bit 0 at address 009616), the INT0 input polarity select bit (bit 1 at address 009616), the INT0 input filter select bit (bits 0 and 1 at address 001E16) and the INT0 pin one-shot trigger polarity select bit. Note 3: This bit is valid only when the INT0 input polarity select bit (bit 1 at address 009616) is "0" (one-edge). Figure 12.29 Timer Y, Z mode register and Timer Y, Z waveform output control register in programmable wait one-shot generation mode

Rev.1.00 Oct 20, 2004 page 104 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z Figure 12.30 Operation example in programmable wait one-shot generation mode Initialized to "L" Count start flag The contents of Timer Z TZOUT pin output "1" "0" Timer Z interrupt request bit "H" "L" "1" "0" "1" "0" fPZ Timer Z output level latch One-shot start bit "1" "0" INT0 pin input "1" "0" 02160316 0116 0016 0416 0216 0116 0016 03160316 Cleared to "0" when interrupt request is accepted, or cleared by software Set to "1" by software Set to "1" by software, or set to "1" by INT 0 pin input trigger Cleared to "0" when counting completed Timer Z primary reload Timer Z secondary reload Count start Cleared to "0" by software Waveform output starts Waveform output ends (Note 1)Wait starts Note 1: The waveform output of one-shot pulse is completed after 0.5 clock (1 clock when primary waveform extended) of fPZ from occurrence of Timer Z interrupt request. Conditions: Timer Z primary=0316, Timer Z primary waveform not extended, Timer Z primary=0416, Timer Z secondary waveform not extended, Timer Z output level latch [TZOPL]=0, INT0 one-shot trigger is valid at rising edge

Rev.1.00 Oct 20, 2004 page 105 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z Time measurement register (16) Upper 8 bits Lower 8 bits Timer C counter (16) f32 Edge detectionTCIN 1/256On-chip oscillation TCIN interrupt Timer C overflow interrupt Time measurement input source switching bit "0" "1" Timer C clock select bit Reload signal Digital filter f f32 Digital filter clock select bit Address 009D16 Address 009C16 Address 009016Address 009116 Data bus Upper 8 bits Lower 8 bits

12.5 Timer C

Timer C is a 16-bit free-running timer. The Timer C uses an edge input to TCIN pin or the output of 256 fRING divisions as trigger to latch the timer count value and generates an interrupt request. The TCIN input has a digital filter and this prevents an error caused by noise or so on from occurring. Figure 12.31 shows the block diagram of Timer C. Table 12.14 shows Timer C specifications. Figure 12.32 shows Timer C-related registers. Figure 12.33 shows an operation example of Timer C and timer measurement register. Figure 12.31 Block diagram of Timer C Table 12.14 Specifications of Timer C Item Specification Count source f 1, f8, f32 Count operation • Up count

• Transfer counter value to time measurement register at active edge of measurement pulse
• When timer C stops counting, the value of timer C is reset to "000016". Count start condition • Time measurement control bit is set (=1) Counter stop condition • Time measurement control bit is reset (=0) Interrupt request generation timing • When active edge of measurement pulse is input [TCIN interrupt]
• When the time underflows [Timer C interrput] TCIN pin function Measurement pulse input Count value reset timing When time measurement control bit is reset (=0) Read from timer (Note 1) • Count value can be read out by reading Timer C.
• Count value at measurement pulse active edge input can be read out by reading time measurement register. Write to timer Cannot write to Timer C and time measurement register Select function • Measurement pulse active edge: selectable (rising edge/falling edge/both edges)
• Measurement pulse: selectable (input from TCIN pin/256 divisions of fRING)
• Digital filter sampling frequency: selectable (f1/f8/f32) Note 1: The Timer C and the timer measurement register must be read in word-size.

Rev.1.00 Oct 20, 2004 page 106 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z b7 b7 b0 b0 (b15) (b8) Timer C Symbol TC Address 009116, 009016 When reset Indeterminate RW RO RO Function Internal count source is counted b7 b7 b0 b0 (b15) (b8) Time measurement register Symbol TM Address 009C16, 009D16 When reset Indeterminate RWFunction When active edge of measurement pulse is input, the count value of Timer C is stored (Note 1) Note 1: When time measurement is disabled, the value is indeterminate. After enabling time measurement, the value is indeterminate until the first trigger is generated. Note 1: Change this bit when time measurement is disabled. Note 2: Set the on-chip oscillation stop bit (CM14) to "0" before setting this bit to "1". Note 3: Change this bit when the interrupt is disabled. When switching the timer measurement input source, the TCIN interrupt may be requested. Therefore, enable the interrupt after setting the interrupt request bit to "0". b7 b6 b5 b4 b3 b2 b1 b0 Timer C control register 0 TCC00 Time measurement control bit 0 : Time measurement disabled 1 : Time measurement enabled TCC07 Time measurement input source switching bit (Note 1 to 3) 0 : TCIN 1 : f RING256 TCC01 Timer C clock select bit (Note 1) TCC02 Symbol TCC0 Address 009A16 When reset 0XX000002 FunctionBit nameBit symbol RW RW RW RW RW RW RW 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : Inhibited b2 b1 TCC03 Nothing is assigned. When write, set "0". When read, their contents are "0". Nothing is assigned. When write, set "0". When read, their contents are "0". b7 b6 b5 b4 b3 b2 b1 b0 Timer C control register 1 TCC10 Digital filter clock select bit (Note 1) TCC11 Symbol TCC1 Address 009B16 When reset XXXXXX112 FunctionBit nameBit symbol RW RW RW 0 0 : Inhibited 0 1 : f1 1 0 : f8 1 1 : f32 b1 b0 Time measurement input edge trigger bit (Note 1) TCC04 0 0 : Rising edge 0 1 : Falling edge 1 0 : Both edges 1 1 : Inhibited b4 b3 Note 1: Input edge becomes active when the same value from TCIN pin is sampled three times in succession. Figure 12.32 Timer C-related register

Rev.1.00 Oct 20, 2004 page 107 of 222 M16C/1N Group 12. Timers REJ09B0007-0100Z Figure 12.33 Operation example of Timer C and time measurement register Counter contents (hex) Time measurement control bit Measurement pulse (TCIN pin input) Time measurement register FFFF16 000016 Conditions: Time measurement input edge trigger is set for falling edge (TCC03="1", TCC04="0") Count start Timer C interrupt request bit "H" "L" "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software Cleared to "0" by software Set to "1" by software Overflow Measurement value 2 Indeterminate Cleared to "0" when interrupt request is accepted, or cleared by software TCIN interrupt request bit Measurement value 1 Transmit timing from Timer C counter to time measurement register Measurement value 1 Measurement value 2 Measurement value 3 Indeterminate Transmit (Measurement value 2) Time Measure- ment value 3 "1" "0" "1" "0" Transmit (Measurement value 1) The delay caused by digital filter Transmit (Measurement value 3)

Rev.1.00 Oct 20, 2004 page 109 of 222 M16C/1N Group 13. Serial I/O REJ09B0007-0100Z SP SP PAR 2SP 1SP UART UART (7 bits) UART (8 bits) UART (7 bits) UART (9 bits) Clock synchronous type Clock synchronous type TxDi UARTi transmit register PAR enabled PAR disabled D8 D7 D6 D5 D4 D3 D2 D1 D0 SP: Stop bit PAR: Parity bit UARTi transmit buffer register MSB/LSB conversion circuit UART (8 bits) UART (9 bits) Clock synchronous type UARTi receive buffer register UARTi receive register 2SP 1SP PAR enabled PAR disabled UART UART (7 bits) UART (9 bits) Clock synchronous type Clock synchronous type UART (7 bits) UART (8 bits) RxDi Clock synchronous type UART (8 bits) UART (9 bits) Data bus low-order bits MSB/LSB conversion circuit D7 D6 D5 D4 D3 D2 D1 D0D80000000 SP SP PAR "0" Data bus high-order bits Figure 13.2 Block diagram of transmit/receive unit

Rev.1.00 Oct 20, 2004 page 110 of 222 M16C/1N Group 13. Serial I/O REJ09B0007-0100Z b7 b7 b0 b0 (b15) (b8) UARTi transmit buffer register Symbol U0TB U1TB Address 00A3 16, 00A216 00AB16, 00AA16 When reset Indeterminate Indeterminate RW WO Function Transmit data (Note 1) Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. Note 1: When transfer data length is 9-bit long, write high-byte first then low-byte with byte-size. b7 b0 UARTi bit rate generator Symbol U0BRG U1BRG Address 00A1 00A916 When reset Indeterminate Indeterminate RW WO Function Values that can be set Assuming that set value = n, BRGi divides the count source by n + 1 OER FER PER SUM Overrun error flag (Note 1) Framing error flag (Note 1) Parity error flag (Note 1) Error sum flag (Note 1) 0 : No overrun error 1 : Overrun error found 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found 0 : No overrun error 1 : Overrun error found Receive dataReceive data Invalid Invalid Invalid Note 1: Bits 15 to 12 are set to "0" when the serial I/O mode select bits (bit 2 to 0 at addresses 00A0 16 and 00A816) are set to "0002" or receive enable bit to "0". (Bit 15 is set to "0" when bits 14 to 12 all are set to "0".) Bits 14 and 13 are also set to "0" when the lower byte of the UARTi receive buffer register (addresses 00A616, and 00AE16) is read out or when this register is read out in word-size. When reading data from the UARTi receive buffer, data should be read high-byte first then low-byte using byte-size. b7 b7 b0 b0 (b15) (b8) UARTi receive buffer register Symbol U0RB U1RB Address 00A7 16, 00A616 00AF16, 00AE16 When reset Indeterminate Indeterminate RW RO RO RO RO RO Bit symbol Bit name Function (During clock synchronous serial I/O mode) Function (During UART mode) Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. 0016 to FF16 Figure 13.3 Serial I/O-related registers (1)

Rev.1.00 Oct 20, 2004 page 111 of 222 M16C/1N Group 13. Serial I/O REJ09B0007-0100Z Note 1: Set the corresponding port direction register to "0". b7 b6 b5 b4 b3 b2 b1 b0 UARTi transmit/receive mode register Symbol UiMR(i=0,1) Address 00A016, 00A816 When reset 0016 RW RW RW RW RW RW RW RW RW Function (During clock synchronous serial I/O mode) Function (During UART mode) Bit nameBit symbol SMD0 Serial I/O mode select bit Internal/external clock select bit Stop bit length select bit Odd/even parity select bit Parity enable bit 0 : Internal clock 1 : External clock (Note 1) Invalid Invalid Invalid Set to "0" 0 : Internal clock 1 : External clock 0 : One stop bit 1 : Two stop bits Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled Must be fixed to 001 SMD1 SMD2 CKDIR STPS PRY PRYE Reserved bit 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited b2 b1 b0 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 UARTi transmit/receive control register 0 Symbol UiC0(i=0,1) Address 00A416, 00AC16 When reset 0816 RW RW RW RW RO RW RW RW Function (During clock synchronous serial I/O mode) Function (During UART mode) Bit nameBit symbol CLK0 CLK1 Reserved bit TXEPT Nothing is assigned Set to "0" In an attempt to write to this bit, write "0". The value, if read, turn out to be "0". NCH CKPOL UFORM BRG count source select bit Transmit register empty flag Data output select bit CLK polarity select bit Transfer format select bit Set to "0" Set to "0" 0 : LSB first 1 : MSB first 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge 0 : T XDi pin is CMOS output 1 : TXDi pin is N-channel open-drain output 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : fc is selected b1 b0 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open- drain output 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : fc is selected b1 b0 Figure 13.4 Serial I/O-related registers (2)

Rev.1.00 Oct 20, 2004 page 112 of 222 M16C/1N Group 13. Serial I/O REJ09B0007-0100Z b7 b6 b5 b4 b3 b2 b1 b0 UARTi transmit/receive control register 1 TE Transmit enable bit 0 : Transmission disabled 1 : Transmission enabled 0 : Transmission disabled 1 : Transmission enabled TI Transmit buffer empty flag RE Receive enable bit (Note 1) 0 : Reception disabled 1 : Reception enabled 0 : Reception disabled 1 : Reception enabled RI Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". Receive complete flag Symbol UiC1(i=0,1) Address 00A516, 00AD16 When reset XXXX00102 RW RW RO RO RW Function (During clock synchronous serial I/O mode) Function (During UART mode) Bit nameBit symbol b7 b6 b5 b4 b3 b2 b1 b0 UART transmit/receive control register 2 Symbol UCON Address 00B016 When reset 0016 RW RW RW RW RW RW RW RW Function (During clock synchronous serial I/O mode) Function (During UART mode) Bit nameBit symbol Note 1: As for the UART1, set the RXD1 input port select bit before setting this bit to reception enabled. 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register U0IRS UART0 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) U1IRS UART1 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) U0RRM InvalidUART0 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enable CLKMD1 Set to "0"CLK/CLKS select bit 1 (Note 1) 0 : Normal mode (CLK output is CLK0 only) 1 : Transfer clock output from multiple pins function selected U1RRM InvalidUART1 continuous receive mode enable bit CLKMD0 InvalidCLK/CLKS select bit 0 Valid when bit 5 = "1" 0 : Clock output to CLK1 1 : Clock output to CLKS1 RXD1EN Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". R XD1 input port select bit (Note 2) 0 : P37 1 : P35 0 : P37 1 : P35 0 : Continuous receive mode disabled 1 : Continuous receive mode enable 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : No data present in receive buffer register 1 : Data present in receive buffer register Note 1: When using multiple pins to output the transfer clock, the following requirements must be met: UART1 internal/external clock select bit (bit 3 at address 00A816) = "0". Note 2: For P37, select "0" for data receive, and "1" for data transfer. And set the direction register of port P37 to input ("0") when receiving. Figure 13.5 Serial I/O-related registers (3)

Rev.1.00 Oct 20, 2004 page 113 of 222 M16C/1N Group 13. Serial I/O REJ09B0007-0100Z Specification

• Transfer data length: 8 bits
• When internal clock is selected (bit 3 at address 00A016,00A816 = "0"): fi/ 2(n+1) (Note 1) fi = f1, f8, f32, fc
• When external clock is selected (bit 3 at address 00A016,00A816 = "1"): Input from CLKi pin
• To start transmission, the following requirements must be met: _ Transmit enable bit (bit 0 at address 00A516,00AD16) = "1" _ Transmit buffer empty flag (bit 1 at addresses 00A516,00AD16) = "0"
• Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at address 00A416,00AC16) = "0": CLKi input level = "H" _ CLKi polarity select bit (bit 6 at address 00A416,00AC16) = "1": CLKi input level = "L"
• To start reception, the following requirements must be met: _ Receive enable bit (bit 2 at address 00A516,00AD16) = "1" _ Transmit enable bit (bit 0 at address 00A516,00AD16) = "1" _ Transmit buffer empty flag (bit 1 at address 00A516,00AD16) = "0"
• Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at address 00A416,00AC16) = "0": CLKi input level = "H" _ CLKi polarity select bit (bit 6 at address 00A416,00AC16) = "1": CLKi input level = "L"
• When transmitting _ Transmit interrupt cause select bit (bit 0 and bit 1 at address 00B0 16) = "0": Inter- rupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed _ Transmit interrupt cause select bit (bit 0 and bit 1 at address 00B0 16) = "1": Inter- rupts requested when data transmission from UARTi transfer register is completed
• When receiving _ Interrupts requested when data transfer from UARTi receive register to UARTi re- ceive buffer register is completed
• Overrun error (Note 2) This error occurs if the serial I/O started receiving the next data before reading UARTi receive buffer register and received the 7th bit of the next data
• CLK polarity selection Whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected
• LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection UART1 transfer clock can be chosen by software to be output from one of the two pins set
• RxD1 input pin selection UART1 RxD1 can be chosen by software to be input to one of the two pins set Note 1: "n" denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: If an overrun error occurs, the UARTi receive buffer will be indeterminate. Note also that the UARTi receive interrupt request bit does not change. Item Transfer data format Transfer clock Transmission start condition Reception start conditio Interrupt request generation timing Error detection Select function

13.1 Clock Synchronous Serial I/O Mode

The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 13.1 lists specifications of clock synchronous sperial I/O mode. Figure 13.6 shows the UARTi transmit/receive mode register. Table 13.1 Specifications of clock synchronous serial I/O mode

Rev.1.00 Oct 20, 2004 page 114 of 222 M16C/1N Group 13. Serial I/O REJ09B0007-0100Z 1000 b7 b6 b5 b4 b3 b2 b1 b0 UARTi transmit/receive mode registers SMD0 Serial I/O mode select bit Invalid in clock synchronous serial I/O mode 0 : Internal clock 1 : External clock (Note 1) Set to "0" Internal/external clock select bit SMD1 SMD2 STPS PRY PRYE Reserved bit CKDIR Symbol UiMR (i=0,1) Address 00A016, 00A816 When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol Note 1: Set the corresponding port direction register to "0". b2 b1 b0 0 0 1 : Clock synchronous serial I/O mode Function Pin name Method of selection Remarks Serial data output Serial data input Transfer clock output Transfer clock input TxD0 (P14) TxD1 (P37) RxD0 (P15) RxD1 (P35) RxD1 (P37) CLKi (P16, P36) CLKi (P16, P36) RxD1 input pin select bit (bit 6 at address 00B016)="1" Port P15 direction register (bit 5 at address 00E316)="0" Port P35 direction register (bit 5 at address 00E716)="0" RxD1 input pin select bit (bit 6 at address 00B016)="1" Port P37 direction register (bit 7 at address 00E716)="0" RxD1 input pin select bit (bit 6 at address 00B016)="0" Internal/external clock select bit (bit 3 at addresses 00A016 and 00A816)="0" Internal/external clock select bit (bit 3 at address 00A016 and 00A816)="1" Ports P16 and P36 direction register (bit 6 at address 00E316 and 00E716)="0" Port P14 cannot be used as an I/O port even when performing only serial data input but not serial data output. Port P37 cannot be used as an I/O port even when performing only serial data input but not serial data output. Port P15 can be used as an I/O port when performing only serial data output but not serial data input. Port P35 can be used as an I/O port when performing only serial data output but not serial data input. When setting Port P37 as RxD1, serial data output cannot be performed. Port P3 5 can be used as an I/O port. Table 13.2 Input/output pin functions in clock synchronous serial I/O mode Figure 13.6 UARTi transmit/receive mode register in clock synchronous serial I/O mode Table 13.2 lists the functions of the input/output pins during clock synchronous serial I/O mode. This table shows the pin functions when the transfer clock output from multiple pins is not selected. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an "H". (If the N-channel open-drain is selected, this pin is in floating state.)

Rev.1.00 Oct 20, 2004 page 115 of 222 M16C/1N Group 13. Serial I/O REJ09B0007-0100Z

• Example of transmit timing (when internal clock is selected)
• Example of receive timing (when external clock is selected) Tc = TCLK = 2(n + 1) / fi fi: frequency of BRGi count source (f1, f8, f32, fc) n: value set to BRGi Transfer clock Transmit enable bit (TE) Transmit buffer empty flag (Tl) CLKi TxDi Transmit register empty flag (TXEPT) "0" "1" "0" "1" "0" "1" The above timing applies to the following settings: Internal clock is selected. CLK polarity select bit = 0. Transmit interrupt cause select bit = 0. Transmit interrupt request bit (IR) "0" "1" 1 / fEXT Dummy data is set in UARTi transmit buffer register Transmit enable bit (TE) Transmit buffer empty flag (Tl) CLKi RxDi Receive complete flag (Rl) "0" "1" "0" "1" "0" "1" Receive enable bit (RE) "0" "1" Receive data is taken in Transferred from UARTi transmit buffer register to UARTi transmit register Read out from UARTi receive buffer register The above timing applies to the following settings: External clock is selected. CLK polarity select bit = 0. f EXT: frequency of external clock Transferred from UARTi receive register to UARTi receive buffer register Receive interrupt request bit (IR) "0" "1" D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 Shown in ( ) are bit symbols. Meet the following conditions when the CLKi input level before data reception = "H" Transmit enable bit "1" Receive enable bit "1" Dummy data write to UARTi transmit buffer register Shown in ( ) are bit symbols. Cleared to "0" when interrupt request is accepted, or cleared by software Tc TCLK Stopped pulsing because transfer enable bit = "0" Data is set in UARTi transmit buffer register Transferred from UARTi transmit buffer register to UARTi transmit register Cleared to "0" when interrupt request is accepted, or cleared by software D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Figure 13.7 Typical transmit/receive timings in clock synchronous serial I/O mode

Rev.1.00 Oct 20, 2004 page 116 of 222 M16C/1N Group 13. Serial I/O REJ09B0007-0100Z LSB first When transfer format select bit = "0" D1 D2 D3 D4 D5 D6 D7 D1 D2 D3 D4 D5 D6 D7 TXDi RXDi CLKi When transfer format select bit = "1" D6 D5 D4 D3 D2 D1 D0D7 D7 D6 D5 D4 D3 D2 D1 D0 TXDi RXDi CLKi MSB first Note 1: This applies when the CLK polarity select bit = "0". When CLK polarity select bit = "1" D1 D2 D3 D4 D5 D6 D7 D1 D2 D3 D4 D5 D6 D7 TXDi RXDi CLKi When CLK polarity select bit = "0" D1 D2 D3 D4 D5 D6 D7D0 D1 D2 D3 D4 D5 D6 D7D0 TXDi RXDi CLKi Note 1: The CLKi pin level when not transferring data is "H". Note 2: The CLKi pin level when not transferring data is "L".

13.1.1 Polarity Select Function

As shown in Figure 13.8, the CLK polarity select bit (bit 6 at addresses 00A4 16 and 00AC16) allows selection of the polarity of the transfer clock. Figure 13.8 Polarity of transfer clock

13.1.2 LSB First/MSB First Select Function

As shown in Figure 13.9, when the transfer format select bit (bit 7 at addresses 00A416 and 00AC16) = "0", the transfer format is "LSB first"; when the bit = "1", the transfer format is "MSB first". Figure 13.9 Transfer format

Rev.1.00 Oct 20, 2004 page 117 of 222 M16C/1N Group 13. Serial I/O REJ09B0007-0100Z Microcomputer TXD1 (P37) CLKS (P34) CLK1 (P36) IN CLK IN CLK Note 1: This applies when the internal clock is selected and transmission is performed only in clock synchronous serial I/O mode.

13.1.4 Continuous Receive Mode

If the continuous receive mode enable bit (bits 2 and 3 at address 00B0 16) is set to "1", the unit is placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again.

13.1.5 RxD

1 Input Pin Selection Function (UART1)

This function allows the setting two RxD1 input pins and choosing one of the two to input serial data by using the RxD1 input pin select bit (bits 6 at address 00B016). When selecting "1" (P35) for RxD1 input pin select bit, P37 functions as TxD1 output pin. When select- ing "0" (P37), serial data output cannot be performed. However, P3 5 can be used as an input/output port. Figure 13.10 The transfer clock output from the multiple pins function usage

13.1.3 Transfer Clock Output from Multiple Pins Function (UART1)

This function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the CLK and CLKS select bit (bits 4 and 5 at address 00B0 16). The multiple pins function is valid only when the internal clock is selected for UART1. Figure 13.10 shows the transfer clock output from the multiple pins function usage.

Rev.1.00 Oct 20, 2004 page 118 of 222 M16C/1N Group 13. Serial I/O REJ09B0007-0100Z Item Specification

• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
• When internal clock is selected (bit 3 at addresses 00A016, 00A816 = "0"): fi/16(n+1) (Note 1) fi = f1, f8, f32, fC
• When external clock is selected (bit 3 at addresses 00A016 = "1"): fEXT/16(n+1) (Note 1) (Note 2)
• To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 at addresses 00A516, 00AD16) = "1" - Transmit buffer empty flag (bit 1 at addresses 00A516, 00AD16) = "0"
• To start reception, the following requirements must be met: - Receive enable bit (bit 2 at addresses 00A516, 00AD16) = "1" - Start bit detection
• When transmitting - Transmit interrupt cause select bits (bits 0,1 at address 00B016) = "0": Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed - Transmit interrupt cause select bits (bits 0, 1 at address 00B0 16) = "1": Interrupts requested when data transmission from UARTi transfer register is completed
• When receiving - Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed
• Overrun error (Note 3) This error occurs if the serial I/O started receiving the next data before read- ing the UARTi receive buffer register and the bit one before the last stop bit of the next data
• Framing error This error occurs when the number of stop bits set is not detected
• Parity error This error occurs when if parity is enabled, the number of 1’s in parity and character bits does not match the number of 1’s set
• Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
• RxD1 input pin selection UART1 RxD1 can be chosen by software to be input to one of the two pins set

13.2 Clock Asynchronous Serial I/O (UART) Mode

The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Table 13.3 lists the specifications of UART mode. Figure 13.11 shows the UARTi transmit/receive mode register. Transfer data format Transfer clock Transmission start condition Reception start condi- tion Interrupt request gen- eration timing Error detection Select function Table 13.3 Specifications of UART Mode Note 1: "n" denotes the value 0016 to FF16 that is set to the UART bit rate generator. Note 2: fEXT is input from the CLKi pin. Note 3: If an overrun error occurs, the UARTi receive buffer will be indeterminate. Note also that the UARTi receive interrupt request bit does not change.

Rev.1.00 Oct 20, 2004 page 119 of 222 M16C/1N Group 13. Serial I/O REJ09B0007-0100Z Figure 13.11 UARTi transmit/receive mode register in UART mode b7 b6 b5 b4 b3 b2 b1 b0 UARTi transmit/receive mode registers SMD0 Serial I/O mode select bit CKDIR Internal / external clock select bit 0 : Internal clock 1 : External clock (Note 1) STPS Stop bit length select bit 0 : One stop bit 1 : Two stop bits PRYE Parity enable bit 0 : Parity disabled 1 : Parity enabled Reserved bit Set to "0" PRY Odd / even parity select bit Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity SMD1 SMD2 Symbol UiMR (i=0,1) Address 00A0 16, 00A816 When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol Note 1: Set the corresponding port direction register to "0". b2 b1 b0 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long Function Pin name Method of selection Remarks Serial data output Serial data input Transfer clock input TxD0 (P14) TxD1 (P37) RxD0 (P15) RxD1 (P35) RxD1 (P37) CLKi (P16, P36) RxD1 input pin select bit (bit 6 at address 00B016)="1" Port P15 direction register (bit 5 at address 00E316)="0" Port P35 direction register (bit 5 at address 00E716)="0" RxD1 input pin select bit (bit 6 at address 00B016)="1" Port P37 direction register (bit 7 at address 00E716)="0" RxD1 input pin select bit (bit 6 at address 00B016)="0" Internal/external clock select bit (bit 3 at address 00A016 and 00A816)="1" Ports P16 and P36 direction register (bit 6 at address 00E316 and 00E716)="0" Port P14 cannot be used as an I/O port even when performing only serial data input but not serial data output. Port P37 cannot be used as an I/O port even when performing only serial data input but not serial data output. Port P15 can be used as an I/O port when performing only serial data output but not serial data input. Port P35 can be used as an I/O port when performing only serial data output but not serial data input. When setting Port P37 as RxD1, serial data output cannot be performed. Port P3 5 can be used as an I/O port. Ports P16 and P36 can be used as an I/O port when not performing transfer clock input. In this case, set the internal/external clock select bit to "0". Table 13.4 lists the functions of the input/output pins during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a "H". (If the N- channel open-drain is selected, this pin is in floating state.) Table 13.4 Input/output pin functions in UART mode

Rev.1.00 Oct 20, 2004 page 120 of 222 M16C/1N Group 13. Serial I/O REJ09B0007-0100Z

• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) Transmit enable bit (TE) Transmit buffer empty flag (TI) Transmit register empty flag (TXEPT) Start bit Parity bit TxDi The above timing applies to the following settings : Parity is enabled. One stop bit. Transmit interrupt cause select bit = 1. "1" "0" "1" "0" "1" Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32, fc) f EXT : frequency of BRGi count source (external clock) n : value set to BRGi Transmit interrupt request bit (IR) "0" "1" Cleared to "0" when interrupt request is accepted, or cleared by software Transmit enable bit (TE) Transmit buffer empty flag (TI) TxDi Transmit register empty flag (TXEPT) "0" "1" "0" "1" "0" "1" The above timing applies to the following settings : Parity is disabled. Two stop bits. Transmit interrupt cause select bit = 0. Transfer clock Tc Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32, fc) f EXT : frequency of BRGi count source (external clock) n : value set to BRGi Transmit interrupt request bit (IR) "0" "1" Shown in ( ) are bit symbols. Shown in ( ) are bit symbols. Tc Transfer clock D0 D1 D2 D3 D4 D5 D6 D7ST P SP Stop bit Transferred from UARTi transmit buffer register to UARTi transmit register D0 D1 D2 D3 D4 D5 D6 D7ST P SP D 0 D1ST Stopped pulsing because transmit enable bit = "0" Start bit Data is set in UARTi transmit buffer register D0 D1 D2 D3 D4 D5 D6 D7ST SP D8 D0 D1 D2 D3 D4 D5 D6 D7ST D 8 D0 D1STSPSP Transferred from UARTi transmit buffer register to UARTi transmit register Stop bit Stop bit Data is set in UARTi transmit buffer register."0" SP Cleared to "0" when interrupt request is accepted, or cleared by software Figure 13.12 Typical transmit timings in UART mode

Rev.1.00 Oct 20, 2004 page 121 of 222 M16C/1N Group 13. Serial I/O REJ09B0007-0100Z

• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) D0Start bit Sampled "L" BRGi count source Receive enable bit RxDi Transfer clock Receive complete flag Stop bit "1" "0" "0" "1" The above timing applies to the following settings: Parity is disabled. One stop bit. Receive interrupt request bit "0" "1" Reception triggered when transfer clock is generated by falling edge of start bit Cleared to "0" when interrupt request is accepted, or cleared by software Receive data taken in Transferred from UARTi receive register to UARTi receive buffer register D7D1

13.2.1 RxD1 Input pin Selection Function (UART1)

This function allows the setting two RxD1 input pins and choosing one of the two to input serial data by using the RxD1 input pin select bit (bits 6 at address 00B016). When selecting "1" (P35) for RxD1 input pin select bit, P37 functions as TxD1 output pin. When select- ing "0" (P37), serial data output cannot be performed. However, P3 5 can be used as an input/output port. Figure 13.13 Typical receive timing in UART mode

Rev.1.00 Oct 20, 2004 page 122 of 222 M16C/1N Group 14. A/D Converter REJ09B0007-0100Z Item Performance Method of A/D conversion Successive approximation(capacitive coupling amplifier) Analog input voltage (Note 1) 0V to VCC Operating clock ØAD (Note 2) VCC = 5V f AD, divide-by-2 of fAD, divide-by-4 of fAD, fAD=f(XIN) Resolution 8-bit or 10-bit (selectable) Absolute precision V CC = 5V • Without sample and hold function ±3LSB

• With sample and hold function (8-bit resolution) ±2LSB
• With sample and hold function (10-bit resolution) AN0 to AN11 input: ±3LSB ANEX0 and ANEX1 input (including mode in which external operation amp is connected): ±7LSB Operating modes One-shot mode and repeat mode (Note 3) Analog input pins 12 pins (AN 0 to AN11) + 2 pins (ANEX0 to ANEX1) A/D conversion start condition •Software trigger A/D conversion starts when the A/D conversion start flag changes to "1" Conversion speed per pin • Without sample and hold function 8-bit resolution: 49 ØAD cycles, 10-bit resolution: 59 ØAD cycles
• With sample and hold function 8-bit resolution: 28 ØAD cycles, 10-bit resolution: 33 ØAD cycles Note 1: Does not depend on use of sample and hold function. Note 2: Divide f AD if (XIN) exceeds 10MHz, and make ØAD equal to or lower than 10MHz. Also if Vcc is less than 4.2V, divide fAD and make ØAD equal to or lower than fAD/2. Without sample and hold function, set the ØAD frequency to 250kHz min. With the sample and hold function, set the ØAD frequency to 1MHz min. Note 3: In repeat mode, only 8-bit mode can be used. 14. A/D Converter The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling amplifier. Pins P0 0 to P07, P10 to P13, P40 and P41 also function as the analog signal input pins. The direction registers of these pins for A/D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 00D7 16) can be used to isolate the resistance ladder of the A/D converter from the refer- ence voltage input pin (VREF) when the A/D converter is not used. Doing so stops any current flowing into the resistance ladder from VREF, reducing the power dissipation. When using the A/D converter, start A/D conversion only after connecting to VREF. The result of A/D conversion is stored in the A/D registers. When set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses. Table 14.1 shows the performance of the A/D converter. Figure 14.1 shows the block diagram of the A/D converter, and Figures 14.2 and 14.3 show the A/D converter-related registers. Table 14.1 Performance of A/D converter

Rev.1.00 Oct 20, 2004 page 123 of 222 M16C/1N Group 14. A/D Converter REJ09B0007-0100Z VREF VSS 1/2 1/2 A/D conversion rate selection CKS1=1 CKS0=0 CKS0=1 CKS1=0 Resistor ladder Successive conversion register A/D control register 0 (address 00D616) A/D control register 1 (address 00D716) VCUT=0 VCUT=1 (00C116, 00C016) A/D register (16) Vref VIN Data bus low-order Decoder Comparator Addresses CH2,CH1,CH0=000 CH2,CH1,CH0=001 CH2,CH1,CH0=010 CH2,CH1,CH0=011 CH2,CH1,CH0=100 CH2,CH1,CH0=101 CH2,CH1,CH0=110 CH2,CH1,CH0=111 OPA1, OPA0=0, 0 Port P0 group P07/AN0 P06/AN1 P05/AN2 P04/AN3 P02/AN5 P01/AN6 P00/AN7 P03/AN4 CH2,CH1,CH0=100 CH2,CH1,CH0=101 CH2,CH1,CH0=110 CH2,CH1,CH0=111 Port P1 group P10/AN8 P12/AN10 P13/AN11 P11/AN9 OPA1=1 OPA1,OPA0=1,1 P40/ANEX0 P41/ANEX1 OPA1,OPA0=0,1OPA0=1 ADGSEL0=1 ADGSEL0=0 fAD flAD Figure 14.1 Block diagram of A/D converter

Rev.1.00 Oct 20, 2004 page 124 of 222 M16C/1N Group 14. A/D Converter REJ09B0007-0100Z Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. Note 2: In repeat mode, only 8-bit mode can be used. Note 3: When f(X IN) is over 10 MHz, the flAD frequency must be under 10 MHz by dividing. b7 b6 b5 b4 b3 b2 b1 b0 A/D control register 0 (Note 1) CH0 Analog input pin select bit MD A/D operation mode select bit 0 0 : One-shot mode 1 : Repeat mode (Note 2) ADGSEL0 A/D input group select bit 0 : Port P0 group is selected 1 : Port P1 group is selected ADST A/D conversion start flag 0 : A/D conversion disabled 1 : A/D conversion started CKS0 Frequency select bit 0 0 : f AD/4 is selected 1 : fAD/2 is selected CH1 CH2 Reserved bit Set to "0" Reserved bit Set to "0" Symbol ADCON0 Address 00D616 When reset 00000XXX2 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol 000 b7 b6 b5 b4 b3 b2 b1 b0 A/D control register 1 (Note 1) OPA0 OPA1 BITS 8/10-bit mode select bit (Note 2) 0 : 8-bit mode 1 : 10-bit mode CKS1 Frequency select bit 1 (Note 3) 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected VCUT V REF connect bit External op-amp connection mode bit 0 : VREF not connected 1 : VREF connected Symbol ADCON1 Address 00D716 When reset 0016 RW RW RW RW RW RW RW FunctionBit nameBit symbol 0 0 0 : AN 0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4, AN8 are selected 1 0 1 : AN5, AN9 are selected 1 1 0 : AN6, AN10 are selected 1 1 1 : AN7, AN11 are selected (Note 2, 3) b2 b1 b0 Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. Note 2: When changing A/D operation mode, set analog input pin again. Note 3: AN 4 to AN7 and AN8 to AN11 are selected by the A/D input group select bit. 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A/D converted 1 0 : ANEX1 input is A/D converted 1 1 : External op-amp connection mode b7 b6 Figure 14.2 A/D converter-related registers (1)

Rev.1.00 Oct 20, 2004 page 125 of 222 M16C/1N Group 14. A/D Converter REJ09B0007-0100Z b7 b7 b0 b0 (b15) (b8) A/D register Symbol AD Address 00C016 00C116 When reset Indeterminate Indeterminate RW RO RO Function Eight low-order bits of A/D conversion result Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". During 10-bit mode Two high-order bits of A/D conversion result During 8-bit mode The value, if read, turns out to be indeterminate. 000 b7 b6 b5 b4 b3 b2 b1 b0 A/D control register 2 (Note 1) SMP A/D conversion method select bit 0 : Without sample and hold 1 : With sample and hold Reserved bit Set to "0" Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". Symbol ADCON2 Address 00D4 When reset XXXX00002 RW RW RW FunctionBit nameBit symbol Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. Figure 14.3 A/D converter-related registers (2)

Rev.1.00 Oct 20, 2004 page 126 of 222 M16C/1N Group 14. A/D Converter REJ09B0007-0100Z b7 b6 b5 b4 b3 b2 b1 b0 A/D control register 0 (Note 1) CH0 CH1 CH2 Analog input pin select bit ADGSEL0 A/D input group select bit 0 : Port P0 group is selected 1 : Port P1 group is selected MD0 A/D operation mode select bit 0 0 : One-shot mode (Note 2) ADST Reserved bit Set to "0" A/D conversion start flag 0 : A/D conversion disabled 1 : A/D conversion started CKS0 Frequency select bit 0 0 : f AD/4 is selected 1 : fAD/2 is selected Symbol ADCON0 Address 00D616 When reset 00000XXX2 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol 0 0 0 : AN 0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4, AN8 are selected 1 0 1 : AN5, AN9 are selected 1 1 0 : AN6, AN10 are selected 1 1 1 : AN7, AN11 are selected (Note 2, 3) b2 b1 b0 Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. Note 2: When changing A/D operation mode, set analog input pin again. Note 3: AN 4 to AN7 and AN8 to AN11 are selected by the A/D input group select bit. 0001 b7 b6 b5 b4 b3 b2 b1 b0 A/D control register 1 (Note 1) Reserved bit Set to "0" VCUT V REF connect bit OPA0 External op-amp connection mode bit OPA1 CKS1 Frequency select bit 1 (Note 2) 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : VREF connected BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Symbol ADCON1 Address 00D716 When reset 0016 RW RW RW RW RW RW RW FunctionBit nameBit symbol Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. Note 2: When f(XIN) is over 10 MHz, the flAD frequency must be under 10 MHz by dividing. 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A/D converted 1 0 : ANEX1 input is A/D converted 1 1 : External op-amp connection mode b7 b6 Item Specification Function The pin selected by the analog input pin select bit is used for one A/D conversion Start condition Writing "1" to A/D conversion start flag Stop condition •End of A/D conversion (A/D conversion start flag changes to "0")

• Writing "0" to A/D conversion start flag Interrupt request generation timing End of A/D conversion Input pin One of AN 0 to AN11, as selected Reading of result of A/D converter Read A/D register

14.1 One-shot Mode

In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A/D conver- sion. (See Table 14.2.) Figure 14.4 shows the A/D control register in one-shot mode. Table 14.2 One-shot mode specifications Figure 14.4 A/D conversion register in one-shot mode

Rev.1.00 Oct 20, 2004 page 127 of 222 M16C/1N Group 14. A/D Converter REJ09B0007-0100Z b7 b6 b5 b4 b3 b2 b1 b0 A/D control register 0 (Note 1) CH0 CH1 CH2 Analog input pin select bit ADGSEL0 A/D input group select bit 0 : Port P0 group is selected 1 : Port P1 group is selected MD A/D operation mode select bit 0 1 : Repeat mode (Note 2) ADST Reserved bit Set to "0" A/D conversion start flag 0 : A/D conversion disabled 1 : A/D conversion started CKS0 Frequency select bit 0 0 : f AD/4 is selected 1 : fAD/2 is selected Symbol ADCON0 Address 00D616 When reset 00000XXX2 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol 0 0 0 : AN 0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4, AN8 are selected 1 0 1 : AN5, AN9 are selected 1 1 0 : AN6, AN10 are selected 1 1 1 : AN7, AN11 are selected (Note 2, 3) b2 b1 b0 00001 b7 b6 b5 b4 b3 b2 b1 b0 A/D control register 1 (Note 1) Reserved bit Set to "0" VCUT V REF connect bit OPA0 External op-amp connection mode bit OPA1 CKS1 Frequency select bit 1 (Note 3) 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : VREF connected BITS 8/10-bit mode select bit (Note 2) 0 : 8-bit mode Symbol ADCON1 Address 00D716 When reset 0016 RW RW RW RW RW RW RW FunctionBit nameBit symbol 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A/D converted 1 0 : ANEX1 input is A/D converted 1 1 : External op-amp connection mode b7 b6 Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. Note 2: When changing A/D operation mode, set analog input pin again. Note 3: AN 4 to AN7 and AN8 to AN11 are selected by the A/D input group select bit. Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate. Note 2: In repeat mode, only 8-bit mode can be used. Note 3: When f(X IN) is over 10 MHz, the flAD frequency must be under 10 MHz by dividing. Item Specification Function The pin selected by the analog input pin select bit is used for repeated A/D conversion Start condition Writing "1" to A/D conversion start flag Stop condition Writing "0" to A/D conversion start flag Interrupt request generation timing None generated Input pin One of AN 0 to AN11, as selected (Note 1) Reading of result of A/D converter Read A/D register (at any time) Note 1: AN4 to AN7 can be used in the same way as for AN8 to AN11. Table 14.3 Repeat mode specifications

14.2 Repeat Mode

In repeat mode, the pin selected using the analog input pin select bit is used for repeated A/D conversion. (See Table 14.3.) Figure 14.5 shows the A/D control register in repeat mode. Figure 14.5 A/D conversion register in repeat mode

Rev.1.00 Oct 20, 2004 page 128 of 222 M16C/1N Group 14. A/D Converter REJ09B0007-0100Z External op-amp Analog input AN0 AN7 AN1 AN2 AN3 AN4 AN5 AN6 ANEX1 ANEX0 Resistance ladder Successive conversion register Comparator AN11 AN8 AN9 AN10 ADGSEL0=1 ADGSEL0=0 Figure 14.6 Example of external op-amp connection mode

14.3 Sample and Hold

Sample and hold is selected by setting bit 0 of the A/D control register 2 (address 00D416) to "1". When sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 ØAD cycle is achieved with 8-bit resolution and 33 ØAD with 10-bit resolution. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before starting A/D conversion whether sample and hold is to be used.

14.4 Extended Analog Input Pins

In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can also be converted from analog to digital. When bit 6 of the A/D control register 1 (address 00D7 16) is "1" and bit 7 is "0", input via ANEX 0 is converted from analog to digital. When bit 6 of the A/D control register 1 (address 00D7 16) is "0" and bit 7 is "1", input via ANEX 1 is converted from analog to digital.

14.5 External Operation Amp Connection Mode

In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1, can be amplified together by just one operation amp and used as the input for A/D conversion. When bit 6 of the A/D control register 1 (address 00D7 16) is "1" and bit 7 is "1", input via AN0 to AN11 is output from ANEX0. The input from ANEX1 is converted from analog to digital and the result stored in the A/D register. The speed of A/D conversion depends on the response of the external operation amp. Do not connect the ANEX 0 and ANEX1 pins directly. Figure 14.6 is an example of how to connect the pins in external operation amp mode.

Rev.1.00 Oct 20, 2004 page 129 of 222 M16C/1N Group 15. D/A Converter REJ09B0007-0100Z 15. D/A Converter This is an 8-bit, R-2R type D/A converter. The microcomputer contains one independent D/A converter of this type. D/A conversion is performed when a value is written to the corresponding D/A register. Bit 0 (D/A output enable bit) of the D/A control register decide if the result of conversion is to be output. Do not set the target port to output mode if D/A conversion is to be performed. When D/A output is set for enabled, the corre- sponding port is inhibited to be pulled up. Output analog voltage (V) is determined by a set value (n: decimal) in the D/A register. V = V REF X n/ 256 (n = 0 to 255) VREF: reference voltage Table 15.1 lists the performance of the D/A converter. Figure 15.1 shows the block diagram of the D/A converter, Figure 15.2 shows the D/A control register and Figure 15.3 shows D/A converter equivalent circuit. D/A register (8) R-2R resistance ladder (Address 00D816) D/A output enable bit P34 / CLKS1 / DA Table 15.1 Performance of D/A converter Item Performance Conversion method R-2R method Resolution 8 bits Analog output pin 1 channel Figure 15.1 Block diagram of D/A converter

Rev.1.00 Oct 20, 2004 page 132 of 222 M16C/1N Group 16. CAN Module REJ09B0007-0100Z

16.1 CAN Module-Related Registers

The CAN0 module has the following registers. (1) CAN Message Box A CAN module is equipped with 16 slots (16 bytes or 8 words each). Slots 14 and 15 can be used as Basic CAN.

• Priority of the slots: The smaller the number of the slot, the higher the priority, in both transmission and reception.
• A program can define whether a slot is defined as transmitter or receiver. (2) Acceptance Mask Registers A CAN module is equipped with 3 masks for the acceptance filter.
• CAN0 global mask register (C0GMR register: 6 bytes) Configuration of the masking condition for acceptance filtering processing to slots 0 to 13
• CAN0 local mask A register (C0LMAR register: 6 bytes) Configuration of the masking condition for acceptance filtering processing to slot 14
• CAN0 local mask B register (C0LMBR register: 6 bytes) Configuration of the masking condition for acceptance filtering processing to slot 15 (3) CAN SFR Registers
• CAN0 message control register i (C0MCTLi register: 8 bits X 16) (i = 0 to 15) Control of transmission and reception of a corresponding slot
• CAN0 control register (C0CTLR register: 16 bits) Control of the CAN protocol
• CAN0 status register (C0STR register: 16 bits) Indication of the protocol status
• CAN0 slot status register (C0SSTR register: 16 bits) Indication of the status of contents of each slot
• CAN0 interrupt control register (C0ICR register: 16 bits) Selection of interrupt enabled or disabled for each slot
• CAN0 extended ID register (C0IDR register: 16 bits) Selection of ID format (standard or extended) for each slot
• CAN0 configuration register (C0CONR register: 16 bits) Configuration of the bus timing
• CAN0 receive error count register (C0RECR register: 8 bits) Indication of the error status of the CAN module in reception: the counter value is incremented or decremented according to the error occurrence.
• CAN0 transmit error count register (C0TECR register: 8 bits) Indication of the error status of the CAN module in transmission: the counter value is incremented or decremented according to the error occurrence.
• CAN0 acceptance filter support register (C0AFS register: 16 bits) Decoding the received ID for use by the acceptance filter support unit Explanation of each register is given below.

Rev.1.00 Oct 20, 2004 page 133 of 222 M16C/1N Group 16. CAN Module REJ09B0007-0100Z

16.2 CAN0 Message Box

Table 16.1 shows the memory mapping of the CAN0 message box. It is possible to access to the message box in byte or word. Mapping of the message contents differs from byte access to word access. Byte access or word access can be selected by the MsgOrder bit of the C0CTLR register. Table 16.1 Memory Mapping of CAN0 Message Box (n = 0 to 15: the number of the slot) Message content (Memory mapping) Byte access (8 bits) Word access (16 bits) 026016 + n • 16 + 0 SID 10 to SID 6 SID5 to SID 0 026016 + n • 16 + 1 SID 5 to SID 0 SID10 to SID 6 026016 + n • 16 + 2 EID 17 to EID 14 EID13 to EID 6 026016 + n • 16 + 3 EID 13 to EID 6 EID17 to EID 14 026016 + n • 16 + 4 EID 5 to EID 0 Data Length Code (DLC) 026016 + n • 16 + 5 Data Length Code (DLC) EID 5 to EID 0 026016 + n • 16 + 6 Data byte 0 Data byte 1 026016 + n • 16 + 7 Data byte 1 Data byte 0

• • •
• • •
• • • 026016 + n • 16 + 13 Data byte 7 Data byte 6 026016 + n • 16 + 14 Time stamp high-order byte Time stamp low-order byte 026016 + n • 16 + 15 Time stamp low-order byte Time stamp high-order byte Address

Rev.1.00 Oct 20, 2004 page 135 of 222 M16C/1N Group 16. CAN Module REJ09B0007-0100Z Figure 16.4 Bit Mapping of Mask Registers in Byte Access

16.3 Acceptance Mask Registers

Figures 16.4 and 16.5 show the C0GMR register, the C0LMAR register, and the C0LMBR register, in which bit mapping in byte access and word access are shown. Figure 16.5 Bit Mapping of Mask Registers in Word Access Bit 7 Bit 0 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 C0GMR register C0LMAR register C0LMBR register 036016 036116 036216 036316 036416 036616 036716 036816 036916 036A16 036C16 036D16 036E16 036F16 037016 Addresses CAN0 Note 1: is indeterminate. Note 2: These registers can be written in CAN reset/initialization mode of the CAN module. Bit 15 Bit 0 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 Bit 8 Bit 7 EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 C0GMR register C0LMAR register C0LMBR register 036016 036216 036416 036616 036816 036A16 036C16 036E16 037016 Addresses CAN0 Note 1: is indeterminate. Note 2: These registers can be written in CAN reset/initialization mode of the CAN module.

Rev.1.00 Oct 20, 2004 page 136 of 222 M16C/1N Group 16. CAN Module REJ09B0007-0100Z

16.4 CAN SFR Registers

16.4.1 C0MCTLi Register (i = 0 to 15)

Figure 16.6 shows the C0MCTLi register. Figure 16.6 C0MCTLi Register b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol Function RW RO (Note 1) RO (Note 1) RO RO RO (Note 1) NewData Successful reception flag SentData Successful transmission flag When set to reception slot 0 : The message is valid. 1 : The message is invalid. (The message is being updated.) When set to transmission slot 0 : Transmission is not started or completed yet. 1 : Transmission is successfully completed. When set to transmission slot 0 : Waiting for bus idle or completion of arbitration. 1 : Transmitting InvalData TrmActive "Under reception" flag "Under transmission" flag MsgLost Overwrite flag Remote frame transmission/ reception status flag (Note 2) 0 : Data frame transmission/reception status 1 : Remote frame automatic transfer status RemActive RspLock Transmission/ reception auto response lock mode select bit Remote frame corresponding slot select bit 0 : Slot not corresponding to remote frame 1 : Slot corresponding to remote frame Remote 0 : Not reception slot 1 : Reception slot RecReq Reception slot request bit (Note 3) 0 : Not transmission slot 1 : Transmission slot TrmReq Transmission slot request bit (Note 3) CAN0 message control register i (i = 0 to 15) (Note 4) Symbol C0MCTL0 to C0MCTL15 to 022F16022016 0016 After resetAddress RW RW RW RW RW Note 1: As for write, only writing "0" is possible. The value of each bit is written when the CAN module enters the respective state. Note 2: In Basic CAN mode, this bit serves as data format identification flag. When receiving a data frame, this bit is set to "0" and when receiving a remote frame, this bit is set to "1". Note 3: One slot cannot be defined as reception slot and transmission slot at the same time. Note 4: This register can not be set in CAN reset/initialization mode of the CAN module. When set to reception slot 0 : The content of the slot is read or still under processing by the CPU. 1 : The CAN module has stored new data in the slot. When set to reception slot 0 : No message has been overwritten in this slot. 1 : This slot already contained a message, but it has been overwritten by a new one. When set to reception remote frame slot 0 : After a remote frame is received, it will be answered automatically. 1 : After a remote frame is received, no transmission will be started as long as this bit is set to "1". (Not responding)

Rev.1.00 Oct 20, 2004 page 137 of 222 M16C/1N Group 16. CAN Module REJ09B0007-0100Z Figure 16.7 C0CTLR Register

16.4.2 C0CTLR Register

Figures 16.7 shows the C0CTLR register. Reset CAN module reset bit (Note 2) LoopBack Loop back mode select bit (Note 3) MsgOrder Message order select bit (Note 3) BasicCAN Basic CAN mode select bit (Note 3) BusErrEn Bus error interrupt enable bit (Note 3) Sleep Sleep mode select bit (Note 3, 4) PortEn CAN port enable bit (b7) CAN0 control register Symbol Address After reset Symbol Address After reset C0CTLR X0000001 2023016 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 (b15) (b8) RW RW RW RW RW RW RW RW 0 : Operation mode 1 : Reset/initialization mode 0 : Word access 1 : Byte access 0 : Normal operation mode 1 : Basic CAN mode 0 : Normal operation mode 1 : Loop back mode 0 : Bus error interrupt disabled 1 : Bus error interrupt enabled 0 : Sleep mode disabled 1 : Sleep mode enabled; clock supply stopped 0 : I/O port function 1 : CTx/CRx function (Note 1) Bit symbol Bit name Function Bit symbol Bit name Function Bit1, Bit0 TSReset RXOnly RetBusOff Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. XX0X0000 2C0CTLR 0231 16 b1 b0 RW RW RW RW RW 0 0 : Period of 1 bit time 0 1 : Period of 1/2 bit time 1 0 : Period of 1/4 bit time 1 1 : Period of 1/8 bit time 0 : Normal operation mode 1 : Force reset of the time stamp counter 0 : Normal operation mode 1 : Listen-only mode (Note 4) 0 : Normal operation mode 1 : Force return from bus off Time stamp prescaler (Note 3) Time stamp counter reset bit (Note 1) Return from bus off command bit (Note 2) Listen-only mode select bit (Note 3) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. (b4) (b7-b6) Note 1: Irrespective of setting of PD0 and PD5 registers. Note 2: When the Reset bit is set to "1" (CAN reset/initialization mode), check that the State_Reset bit of the C0STR register is set to "1" (Reset mode). Note 3: Set these bits only in CAN reset/initialization mode. Note 4: When using CAN0 wake up interrupt, set this bit to "1" (Sleep mode disabled). Note 1: When the TSReset bit = 1, the C0TSR register is set to "0000 16". After this, the bit is automatically set to "0". Note 2: When the RetBusOff bit = 1, the C0RECR register and the C0TECR register are set to "0016". After this, the bit is automatically set to "0". Note 3: Set these bits only in CAN reset/initialization mode. Note 4: When listen-only mode is selected, do not request a transmission.

Rev.1.00 Oct 20, 2004 page 138 of 222 M16C/1N Group 16. CAN Module REJ09B0007-0100Z Figure 16.8 C0STR Register

16.4.3 C0STR Register

Figure 16.8 shows the C0STR register. State_Reset Reset state flag State_ LoopBack Loop back state flag State_ MsgOrder Message order state flag State_ BasicCAN Basic CAN mode state flag State_ BusError Bus error state flag State_ ErrPass Error passive state flag State_ BusOff (b7) Error bus off state flag 0 : Operation mode 1 : Reset mode 0 : Word access 1 : Byte access 0 : Normal operation mode 1 : Basic CAN mode 0 : No error has occurred. 1 : A CAN bus error has occurred. 0 : Normal operation mode 1 : Loop back mode 0 : The CAN module is not in error passive state. 1 : The CAN module is in error passive state. 0 : The CAN module is not in error bus off state. 1 : The CAN module is in error bus off state. Nothing is assigned. When write, set to "0". When read, its content is indeterminate. RO RO RO RO RO RO RO C0STR 0233 16 X00000012 After reset CAN0 status register (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 (b15) (b8) Bit symbol Bit name Function MBox Active slot bits (Note 2) b3 b2 b1 b0 RW Bit symbol Bit name Function RW RO RO RO RO RO Successful reception flag Transmission flag (Transmitter) Reception flag (Receiver) 0 0 0 0 : Slot 0 0 0 0 1 : Slot 1 0 0 1 0 : Slot 2. 1 1 1 0 : Slot 14 1 1 1 1 : Slot 15 0 : No [successful] reception 1 : CAN module received a message successfully. 0 : CAN module is idle or receiver. 1 : CAN module is transmitter. 0 : CAN module is idle or transmitter. 1 : CAN module is receiver. TrmSucc Successful transmission flag RecSucc TrmState RecState Symbol Address After resetSymbol Address C0STR 0232 16 0016 Note 1: These bits can not be set in CAN reset/initialization mode of the CAN module. Note 2: These bits change when a slot enabled interrupt has transmitted or received successfully. 0 : No [successful] transmission 1 : The CAN module has transmitted a message successfully.

Rev.1.00 Oct 20, 2004 page 139 of 222 M16C/1N Group 16. CAN Module REJ09B0007-0100Z Figure 16.9 C0SSTR Register

16.4.4 C0SSTR Register

Figure 16.9 shows the C0SSTR register. b7 b0 (b15) (b8) b7 b0 Function Slot status bits Each bit corresponds to the slot with the same number. CAN0 slot status register RW RO Symbol Address After reset C0SSTR 023516, 023416 000016 Setting values 0 : Reception slot The message has been read. Transmission slot Transmission is not completed. 1 : Reception slot The message has not been read. Transmission slot Transmission is completed.

Rev.1.00 Oct 20, 2004 page 140 of 222 M16C/1N Group 16. CAN Module REJ09B0007-0100Z Figure 16.10 C0ICR Register

16.4.6 C0IDR Register

Figure 16.11 shows the C0IDR register.

16.4.5 C0ICR Register

Figure 16.10 shows the C0ICR register. Figure 16.11 C0IDR Register CAN0 interrupt control register (Note 1) b0b0 b7b7 (b8)(b15) Function Setting values Interrupt enable bits: Each bit corresponds with a slot with the same number. Enabled/disabled of successful transmission inter- rupt or successful reception interrupt can be selected. 0 : Interrupt disabled 1 : Interrupt enabled RW RW Symbol Address After reset C0ICR 0237 16, 023616 000016 Note 1: These bits can not be set in CAN reset/initialization mode of the CAN module. CAN0 extended ID register (Note 1) Symbol Address After reset C0IDR 0239 16, 023816 000016 Function Setting values b0b0 b7b7 (b8)(b15) RW RW Extended ID bits: Each bit corresponds with a slot with the same number. Selection of the ID format that each slot handles. 0 : Standard ID 1 : Extended ID Note 1: These bits can not be set in CAN reset/initialization mode of the CAN module.

Rev.1.00 Oct 20, 2004 page 141 of 222 M16C/1N Group 16. CAN Module REJ09B0007-0100Z Figure 16.12 C0CONR Register

16.4.7 C0CONR Register

Figure 16.12 shows the C0CONR register. C0CONR b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 (b15) (b8) Bit symbol Bi t name Function Bit symbol Bi t name Function BRP SAM PTS 0 : One time sampling 1 : Three times sampling 0 0 0 0 : Divide-by-1 of fCAN 0 0 0 1 : Divide-by-2 of fCAN 0 0 1 0 : Divide-by-3 of fCAN 1 1 1 0 : Divide-by-15 of fCAN 1 1 1 1 : Divide-by-16 of fCAN 0 0 0 : 1Tq 0 0 1 : 2Tq 0 1 0 : 2Tq 1 1 0 : 7Tq 1 1 1 : 8Tq RW RW RW RW PBS1 Phase buffer segment 1 control bits PBS2 Phase buffer segment 2 control bits SJW Re synchronization jump width control bits CAN0 configuration register C0CONR b3 b2 b1 b0 b7 b6 b5 b2 b1b0 b5 b4 b3 b7 b6 023A16 Note 1: fCAN serves for the CAN clock. The period is decided by configuration of the CCLKi bits (i = 4 to 6). Symbol Address Symbol Address Sampling control bit Prescaler division ratio select bits Propagation time segment control bits RW RW RW RW 023B16 0 0 0 : Inhibited 0 0 1 : 2Tq 0 1 0 : 3Tq 1 1 0 : 7Tq 1 1 1 : 8Tq 0 0 0 : Inhibited 0 0 1 : 2Tq 0 1 0 : 3Tq 1 1 0 : 7Tq 1 1 1 : 8Tq 0 0 : 1Tq 0 1 : 2Tq 1 0 : 3Tq 1 1 : 4Tq After reset After reset Indeterminate Indeterminate (Note 1)

Rev.1.00 Oct 20, 2004 page 142 of 222 M16C/1N Group 16. CAN Module REJ09B0007-0100Z Figure 16.13 C0RECR Register

16.4.9 C0TECR Register

Figure 16.14 shows the C0TECR register. Figure 16.14 C0TECR Register

16.4.8 C0RECR Register

Figure 16.13 shows the C0RECR register. Reception error counting function The value is incremented or decremented according to the CAN module’s error status. 16 to FF16(Note 1) CAN0 receive error count register (Note 2) AddressSymbol After reset C0RECR 023C 16 0016 b7 b0 Function Counter value Note 1: The value is indeterminate in bus off state. Note 2: These bits can not be set in CAN reset/initialization mode of the CAN module. RW RO C0TECR 023D 16 0016 CAN0 transmit error count register (Note 1) b7 b0 Function 0016 to FF16 Counter value RW RO Symbol Address After reset Transmission error counting function The value is incremented or decremented according to the CAN module’s error status. Note 1: These bits can not be set in CAN reset/initialization mode of the CAN module.

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16.4.10 C0AFS Register

Figure 16.15 shows the C0AFS register. Figure 16.15 C0AFS Register (b15) (b8) b0 b7 b0 Function Setting values CAN0 acceptance filter support register C0AFS , 024416024516 RW RW Symbol Address Write the content equivalent to the standard frame ID of the received message. The value is "converted standard frame ID" when read. Standard frame ID Indeterminate After reset

Rev.1.00 Oct 20, 2004 page 144 of 222 M16C/1N Group 16. CAN Module REJ09B0007-0100Z

16.5 Operational Modes

The CAN module has the following three operational modes.

• CAN Reset/Initialization Mode
• CAN Sleep Mode
• CAN Operation Mode Figure 16.16 shows transition between operational modes. Figure 16.16 Transition Between Operational Modes

16.5.1 CAN Reset/Initialization Mode

CAN reset/initialization mode is activated upon MCU reset or by setting the Reset bit of the C0CTLR register. When setting the Reset bit to "1", check that the State_Reset bit of C0STR register is set to "1". Entering CAN reset/initialization mode, the module initiates the following functions:

• Suspend all communication functions. When the CAN reset/initialization mode is activated during an ongoing transmission in operation mode, the module suspends the mode transition until completion of the transmission (successful, arbitration loss, or error detection) and then sets the State_Reset bit.
• The C0IDR, C0MCTLi (i = 0 to 15), C0ICR, C0STR, C0RECR and C0TECR registers are initial- ized. All these registers are locked to prevent CPU modification.
• The C0CTLR, C0CONR, C0GMR, C0LMAR and C0LMBR registers and the CAN0 message box retain their contents and are available for CPU access. MCU Reset CAN Reset/initialization mode (State_Reset = 1) CAN Operation mode (State_Reset = 0) CAN Sleep mode Bus off state (State_Bus off = 1) Reset = 0 Reset = 1 Reset = 1 Reset, Sleep, RetBusOff : C0CTLR register’s bits State_Reset, State_BusOFF : C0STR register’s bits Sleep = 1 and Reset = 0 Sleep = 0 and Reset = 1 TEC > 255 When 11 consecutive recessive bits are monitored 128 times on the bus or RetBusOff = 1

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16.5.2 CAN Operation Mode

CAN operation mode is activated by setting the Reset bit of the C0CTLR register to “0”. When setting the Reset bit to "0", check that the State_reset bit of C0STR register is set to "0". In CAN operation mode, the CAN module becomes the following status after having detected 11 consecutive recessive bits on the bus.

• The module's communication functions are released and it becomes an active node on the net- work and may transmit and receive CAN messages.
• Release the internal fault confinement logic including receive and transmit error counters. The module may leave CAN operation mode depending on the error counts. Within CAN operation mode, the module may be in three different sub modes, depending on which type of communication functions are performed:
• Module idle: The modules receive and transmit sections are inactive.
• Module receives: The module receives a CAN message sent by another node.
• Module transmits: The module transmits a CAN message. The module may receive its own message simultaneously when the looback function is enabled. Figure 16.17 shows sub modes of CAN operation mode. Figure 16.17 Sub Modes of CAN Operation Mode

16.5.3 CAN Sleep Mode

CAN sleep mode is activated by setting the Sleep bit of the C0CTLR register to “1” and Reset bit to “0”. It should never be activated from CAN operation mode but only via CAN reset/initialization mode. Entering CAN sleep mode instantly stops the modules clock supply and thereby reduces power dissi- pation.

16.5.4 Bus Off State

The bus off sate is entered according to the fault confinement rules of the CAN specification. When returning to CAN operation mode from the bus off state, the module has the following two cases. In this time, the value of any CAN registers, except C0STR, C0RECR and C0TECR registers, does not change. (1) When 11 consecutive recessive bits are monitored 128 times The module enters instantly into error active state and the CAN communication becomes possible immediately. (2) When the RetBus Off bit in the CiCTLR register = 1 (Force return form buss off) The module enters instantly into error active state, and the CAN communication becomes pos- sible again after 11 consecutive recessive bits are monitored. Lost in arbitration TrmState, RecState : C0STR register’s bit Transmission start A SOF detected Transmission finished Reception finished Module idle TrmState = 0 RecState = 0 Module transmits TrmState = 1 RecState = 0 Module receives TrmState = 0 RecState = 1

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16.6 Configuration of the CAN Module System Clock

The M16C/1N group has a CAN module system clock select circuit. Configuration of the CAN module system clock can be done through manipulating the CCLKR register and the BRP bit of the C0CONR register. For the CCLKR register, refer to clock generation circuit. Figure 16.18 shows a block diagram of the clock generation circuit of the CAN module system. Figure 16.18 Block Diagram of CAN Module System Clock Generation Circuit

16.6.1 Bit Timing Configuration

The bit time consists of the following four segments:

• Synchronization segment (SS) This serves for monitoring a falling edge for synchronization.
• Propagation time segment (PTS) This segment absorbs physical delay on the CAN network which amounts to double the total sum of delay on the CAN bus, the input comparator delay, and the output driver delay.
• Phase buffer segment 1 (PBS1) This serves for compensating the phase error. When the falling edge of the bit falls later than expected, the segment can become longer by the maximum of the value defined in SJW.
• Phase buffer segment 2 (PBS2) This segment has the same function as the phase buffer segment 1. When the falling edge of the bit falls earlier than expected, the segment can become shorter by the maximum of the value defined in SJW. Figure 16.19 shows the bit timing. Figure 16.19 Bit Timing Divide-by-1 of XIN (undivided) Divide-by-2 of XIN Divide-by-4 of XIN Divide-by-8 of XIN Divide-by-16 of XIN Prescaler CAN module Prescaler for baud rate Division by (P + 1) fCAN fCANCLK fCAN: CAN module system clock P: The value written in the BRP bit of the C0CONR register. P = 0 to 15 f CANCLK:CAN communication clock fCANCLK = fCAN/2(P + 1) Divider CCLKR register Value: 1, 2, 4, 8, 16 The range of each segment: Bit time = 8 to 25Tq SS = 1Tq PTS = 1Tq to 8Tq PBS1 = 2Tq to 8Tq PBS2 = 2Tq to 8Tq SJW = 1Tq to 4Tq Configuration of PBS1 and PBS2: PBS1 ≥ PBS2 PBS1 ≥ SJW PBS2 ≥ 2 when SJW = 1 PBS2 ≥ SJW when 2 ≤ SJW ≤ 4 Bit time SS PTS PBS1 SJW Sampling point PBS2 SJW

Rev.1.00 Oct 20, 2004 page 147 of 222 M16C/1N Group 16. CAN Module REJ09B0007-0100Z

16.6.2 Baud Rate

Baud rate depends on XIN, the division value of the CAN module system clock, the division value of the prescaler for baud rate, and the number of Tq of one bit. Table 16.2 shows the examples of baud rate. Table 16.2 Examples of Baud Rate Calculation of Baud Rate Note 1: f CAN division value = 1, 2, 4, 8, 16 fCAN division value: a value selected in the CCLKR register Note 2: Division value of prescaler for baud rate = P + 1 (P: 0 to 15) P: a value selected in the BRP bit of the C0CONR register 2 X fCAN division value (Note 1) X division value of prescaler for baud rate (Note 2) X number of Tq of one bit XIN Baud rate 16 MHz 10 MHz 8 MHz

1 Mbps 8Tq (1) --

500 kbps 8Tq (2) 10Tq (1) 8Tq (1) 16Tq (1) -- 125 kbps 8Tq (8) 10Tq (4) 8Tq (4) 16Tq (4) 20Tq (2) 16Tq (2) 83.3 kbps 8Tq (12) 10Tq (6) 8Tq (6) 16Tq (6) 20Tq (3) 16Tq (3) 33.3 kbps 8Tq (30) 10Tq (15) 8Tq (15) 16Tq (15) -- Note 1: The number in ( ) indicates a value of fCAN division value multiplied by division value of the prescaler for baud rate.

Rev.1.00 Oct 20, 2004 page 148 of 222 M16C/1N Group 16. CAN Module REJ09B0007-0100Z Figure 16.20 Correspondence of Mask Registers to Slots Figure 16.21 Acceptance Function When using the acceptance function, note the following points. (1) When one ID is defined in two slots, the one with a smaller number alone is valid. (2) When it is configured that slots 14 and 15 receive all IDs with Basic CAN mode, slots 14 and 15 receive all IDs which are not stored into slots 0 to 13.

16.7 Acceptance Filtering Function and Masking Function

These functions serve the users to select and receive a facultative message. The C0GMR register, the C0LMAR register, and the C0LMBR register can perform masking to the standard ID and the extended ID of 29 bits. The C0GMR register corresponds to slots 0 to 13, the C0LMAR register corresponds to slot 14, and the C0LMBR register corresponds to slot 15. The masking function becomes valid to 11 bits or 29 bits of a received ID according to the value in the corresponding slot of the C0IDR register upon acceptance filtering operation. When the masking function is employed, it is possible to receive a certain range of IDs. Figure 16.20 shows correspondence of the mask registers and slots, Figure 16.21 shows the acceptance function. Slot #0 Slot #1 Slot #2 Slot #3 Slot #4 Slot #5 Slot #6 Slot #7 Slot #8 Slot #9 Slot #10 Slot #11 Slot #12 Slot #14 Slot #15 C0GMR register Slot #13 C0LMAR register C0LMBR register ID of the received message ID stored in the slot The value of the mask register Acceptance Signal Mask Bit Values Acceptance judge signal 0: The CAN module ignores the current incoming message. (Not stored in any slot) 1: The CAN module stores the current incoming message in a slot of which ID matches. 0: ID (to which the received message corresponds) match is handled as "Don’t care". 1: ID (to which the received message corresponds) match is checked.

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16.8 Acceptance Filter Support Unit (ASU)

The acceptance filter support unit has a function to judge valid/invalid of a received ID through table search. The IDs to receive are registered in the data table; a received ID is stored in the C0AFS register, and table search is performed with a decoded received ID. The acceptance filter support unit can be used for the IDs of the standard frame only. The acceptance filter support unit is valid in the following cases.

• When the ID to receive cannot be masked by the acceptance filter. (Example) IDs to receive: 078 16, 08716, 11116
• When there are too many IDs to receive; it would take too much time to filter them by software. Figure 16.22 shows the write and read of C0AFS register in word access. Figure 16.22 Write/read of CiAFS Register in Word Access Bit 15 Bit 0Bit 8 Bit 7 When read SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 Bit 15 Bit 0 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 Bit 8 Bit 7 When write 3/8 Decoder 024516, 024416 024516, 024416 Address

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16.10 Return from Bus off Function

When the protocol controller enters bus off state, it is possible to make it forced return from bus off state by the return from bus off function of the C0CTLR register. At this time, the error state changes from bus off state to error active state. Implementation of this function initializes the protocol controller. However, registers of the CAN module such as C0CONR register and the content of each slot are not initialized.

16.11 Listen-Only Mode

When the RXOnly bit of the C0CTLR register is set to "1", the module enters listen-only mode. Listen-only mode is not allowed to have any influence on the bus. It shall not send any frames nor send acknowledgement, error frames, overload frames. When setting the CAN module to Listen-only mode, do not request a transmission.

16.9 Basic CAN Mode

When the BasicCAN bit in the C0CTLR register is set to "1", slots 14 and 15 correspond to Basic CAN mode. In normal operation mode, each slot can handle only one type message at a time, either a data frame or a remote frame by setting C0MCTLi register (i = 0 to 15). However, in Basic CAN mode, slots 14 and 15 can receive both types of message at the same time. When slots 14 and 15 are defined as reception slots in Basic CAN mode, received messages are stored in slots 14 and 15 alternately. Which type of message has been received can be checked by the RemActive bit in the C0MCTLi register. Figure 16.23 shows the operation of slots 14 and 15 in Basic CAN mode. Figure 16.23 Operation of Slots 14 and 15 in Basic CAN Mode When using Basic CAN mode, note the following points. (1) Setting of Basic CAN mode has to be done in CAN reset/initialization mode. (2) Select the same ID for slots 14 and 15. Also, setting of the C0LMAR and C0LMBR registers has to be the same. (3) Define slots 14 and 15 as reception slot only. (4) There is no protection available against message overwrite. A message can be overwritten by a new message. (5) Slots 0 to 13 can be used in the same way as in normal CAN operation mode. Slot 14 Slot 15 Msg. n Msg. n+2 Msg. n+1 Empty Locked (empty) Locked (empty) Msg. n Locked (Msg. n) Msg. n + 1 Msg. n+2 (Msg. n lost) Locked (Msg. n+1)

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16.12 Reception and Transmission

Configuration of CAN Reception and Transmission Mode Table 16.3 shows configuration of CAN reception and transmission mode. Table 16.3 Configuration of CAN Reception and Transmission Mode When configuring a slot as a reception slot, note the following points. (1) Before configuring a slot as a reception slot, be sure to set the C0MCTLi registers (i = 0 to 15) to "0016". (2) A received message is stored in a slot that matches the condition first according to the result of reception mode configuration and acceptance filtering operation. Upon deciding in which slot to store, the smaller the number of the slot is, the higher priority it has. (3) In normal CAN operation mode, when a CAN module transmits a message of which ID matches, the CAN module never receives the transmitted data. In loop back mode, however, the CAN mod- ule receives back the transmitted data. In this case, the module does not return ACK. When configuring a slot as a transmission slot, note the following points. (1) Before configuring a slot as a transmission slot, be sure to set the C0MCTLi registers to "00 16". (2) Set the TrmReq bit to "0" (not transmission slot) before rewriting a transmission slot. (3) A transmission slot should not be rewritten when the TrmActive bit is "1" (transmitting). If it is rewritten, an indeterminate data will be transmitted. TrmReq

00 Communication environment configuration mode: configure the commu-

nication mode of the slot. RecReq Remote RspLock Communication mode of the slot 0 100 Configured as a reception slot for a data frame. 1 010 Configured as a transmission slot for a remote frame. (At this time the RemActive bit is "1".) After completion of transmission, this functions as a reception slot for a data frame. (At this time the RemActive bit is "0".) However, when an ID that matches on the CAN bus is detected before remote frame transmission, this immediately functions as a reception slot for a data frame. 1 000 Configured as a transmission slot for a data frame. 01 1 1/0 Configured as a reception slot for a remote frame. (At this time the RemActive bit is "1".) After completion of reception, this functions as a transmission slot for a data frame. (At this time the RemActive bit is "0".) However, transmission does not start as long as RspLock bit remains "1"; thus no automatic remote frame response. Response (transmission) starts when RspLock bit is set to "0". TrmReq, RecReq, Remote, RspLock, RemActive, RspLock: C0MCTLi register’s bit

Rev.1.00 Oct 20, 2004 page 152 of 222 M16C/1N Group 16. CAN Module REJ09B0007-0100Z

16.12.1 Reception

Figure 16.24 shows the behavior of the module when receiving two consecutive CAN messages. Figure 16.24 Timing of Receive Data Frame Sequence (1) On monitoring a SOF on the bus the RecState bit becomes active immediately, given the module has no transmission pending (see section "16.12.2 Transmission" below). (2) After successful reception of the message the NewData bit of the receiving slot becomes active. The InvalData bit becomes active at the same time and becomes inactive again after the complete message was transferred to the slot. (3) When the bit in the C0ICR register of the receiving slot is active the receive successful interrupt is requested and the C0STR register changes. It shows the slot number where the message was stored and the RecSucc bit is active. (4) Read the message out of the slot after setting the New Data bit to “0” by a program. (5) If the NewData bit is set to "0" by a program or the next CAN message is received successfully before the reception request for the slot is canceled, the MsgLost bit is set to "1". The new received message is transferred to the slot. The interrupt request and the C0STR register change like (3). CANbus RecReq InvalData Succ.Rec Int. RecState RecSucc MBOX NewData SOF ACK ACK EOF EOF IFS IFSSOF Receive slot No. MsgLost CAN0 message control registerCAN0 status register (1) (2) (2) (3) (4) (5) (5) (5)

Rev.1.00 Oct 20, 2004 page 153 of 222 M16C/1N Group 16. CAN Module REJ09B0007-0100Z

16.12.2 Transmission

Figure 16.25 shows the timing of the transmit sequence. TrmActive CANbus TrmReq Succ. Xmit Int. MBOX TrmSucc TrmState SentData SOF SOF Transmission slot No. B(4) CAN0 message control registerCAN0 status register ACK EOF IFS (1) (3) (3) (3) (2) (2)(1) (1) i=0 to15 Figure 16.25 Timing of Transmit Sequence (1) If the TrmReq bit of the C0MCTLi register (i=0 to 15) is set to "1" (Transmission slot) in bus idle state, the TrmActive bit of the C0MCTLi register and the TrmState bit of the C0STR register are set to "1" (Transmitting/Transmitter), and the CAN module starts transmitting. (2) If the arbitration is lost after the CAN module starts transmitting, the TrmActive and TrmState bits are set to "0". (3) If the transmission is successful without lost arbitration, the SentData bit of the C0MCTLi register is set to "1" (Transmission is successfully completed) and TrmActive bit of the C0MCTLj register is set to "0" (Waiting for bus idle or completion of arbitration). And when the interrupt enable bits of the C0ICR register = 1 (Interrupt enabled), CAN0 successful transmission interrupt request is gen- erated and the MBOX (the slot number which transmitted the message) and TrmSucc bits of the C0STR register are changed. (4) When starting the next transmission, set the SentData and TrmReq bits to "0", then set the TrmReq bit to "1" after checking that the SentData and TrmReq bits are set to "0".

Rev.1.00 Oct 20, 2004 page 154 of 222 M16C/1N Group 16. CAN Module REJ09B0007-0100Z

16.13 CAN Interrupts

The CAN module provides the following CAN interrupts.

• CAN0 Successful Reception Interrupt
• CAN0 Successful Transmission Interrupt
• CAN0 Error Interrupt Error Passive State Error BusOff State Bus Error (this feature can be disabled separately)
• CAN0 Wake Up Interrupt When the CPU detects a successful reception/transmission interrupt, the C0STR register must be read to determine which slot has issued the interrupt.

Rev.1.00 Oct 20, 2004 page 155 of 222 M16C/1N Group 17. Programmable I/O Ports REJ09B0007-0100Z 17. Programmable I/O Ports

17.1 Description

There are 37 programmable I/O ports: P0 to P5. Each port can be set independently for input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. The port P1 allows the drive capacity of its N-channel output transistor to be set as necessary. The port P1 can be used as LED drive port if the drive capacity is set to "HIGH". Figures 17.1 to 17.4 show the programmable I/O ports. Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices. To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D/A converter), they function as outputs regardless of the contents of the direction registers. When a pin is to be used as the output for the D/A converter, do not set the direction register to output mode. See the descriptions of the respective functions for how to set up the built-in peripheral devices.

17.1.1 Direction registers

Figure 17.5 shows the direction registers. These registers are used to choose the direction of the programmable I/O ports. Each bit in these registers corresponds one for one to each I/O pin.

17.1.2 Port registers

Figure 17.6 shows the port registers. These registers are used to write and read data for input and output to and from an external device. A port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit in port registers corresponds one for one to each I/O pin.

17.1.3 Pull-up control registers

Figure 17.7 shows the pull-up control registers. The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input.

17.1.4 Port P1 drive capacity control register

Figure 17.7 shows a structure of the port P1 drive capacity control register. This register is used to control the drive capacity of the port P1's N-channel output transistor. Each bit in this register corresponds one for one to the port pins.

17.1.5 CAN0 I/O port selected register

Figure 17.8 shows the CAN0 I/O port selected register. This register is used to select I/O port for CAN0.

Rev.1.00 Oct 20, 2004 page 156 of 222 M16C/1N Group 17. Programmable I/O Ports REJ09B0007-0100Z P14 Data bus Port latch output "1" Direction register Pull-up selection P14 driving capacity P15 Data bus Port latch Input to respective peripheral functions Direction register Pull-up selection P15 driving capacity Input to respective peripheral functions Direction register Pull-up selection A/D input P10 to P13 Data bus Port latch P1X driving capacity Input to respective peripheral functions P03 only P00 to P07, P40, P41 Data bus Direction register Port latch Pull-up selection A/D input (Note 1) (Note 1) (Note 1) (Note 1) Note 1: Do not apply a voltage higher than Vcc to each port. Figure 17.1 Programmable I/O ports (1)

Rev.1.00 Oct 20, 2004 page 157 of 222 M16C/1N Group 17. Programmable I/O Ports REJ09B0007-0100Z P20, P21 P52 Data bus Pull-up selection Direction register Port latch P34 Data bus Pull-up selection Analog input D/A output enable output "1" D/A output enable Direction register Port latch P16, P17 Data bus Direction register Port latch Pull-up selection output Input to respective peripheral functions "1" P1x driving capacity (Note 1) (Note 1) (Note 1) Note 1: Do not apply a voltage higher than Vcc to each port. Figure 17.2 Programmable I/O ports (2)

Rev.1.00 Oct 20, 2004 page 158 of 222 M16C/1N Group 17. Programmable I/O Ports REJ09B0007-0100Z P33, P35, P42 to P44 P51 Input to respective peripheral functions Data bus Direction register Port latch Pull-up selection P30, P31, P32 P50 Data bus Direction register Port latch Pull-up selection output "1" output "1" P36, P37 Data bus Pull-up selection Direction register Port latch Input to respective peripheral functions (Note 1) (Note 1) (Note 1) Note 1: Do not apply a voltage higher than Vcc to each port. Figure 17.3 Programmable I/O ports (3)

Rev.1.00 Oct 20, 2004 page 159 of 222 M16C/1N Group 17. Programmable I/O Ports REJ09B0007-0100Z P45 Input to respective peripheral functions Data bus Direction register Port latch Digital filter Pull-up selection Note 1: symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. P47 (Note 1) (Note 1) P46 output "1" fc Rf Rd (Note 1) Data bus Data bus Direction register Direction register Port latch Port latch Pull-up selection Pull-up selection Figure 17.4 Programmable I/O ports (4)

Rev.1.00 Oct 20, 2004 page 161 of 222 M16C/1N Group 17. Programmable I/O Ports REJ09B0007-0100Z b7 b6 b5 b4 b3 b2 b1 b0 Pull-up control register 0 PU00 P0 0 to P03 pull-up PU01 P0 4 to P07 pull-up PU02 P1 0 to P13 pull-up PU03 P1 4 to P17 pull-up PU04 P2 0 to P21 pull-up PU06 P3 0 to P33 pull-up PU07 P3 4 to P37 pull-up Symbol PUR0 Address 00FC16 When reset 00X000002 RW RW RW RW RW RW RW RW FunctionBit nameBit symbol The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 Pull-up control register 1 PU10 P4 0 to P43 pull-up PU11 P4 4 to P47 pull-up PU12 P5 0 to P52 pull-up Symbol PUR1 Address 00FD16 When reset XXXXX0002 RW RW RW RW FunctionBit nameBit symbol The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 Port P1 drive capacity control register DRR0 Port P1 0 drive capacity DRR1 Port P1 1 drive capacity DRR2 Port P1 2 drive capacity DRR3 Port P1 3 drive capacity DRR4 Port P1 4 drive capacity DRR5 Port P1 5 drive capacity DRR6 Port P1 6 drive capacity DRR7 Port P1 7 drive capacity Symbol DRR Address 00FE16 When reset 0016 RW RW RW RW RW RW RW RW RW FunctionBit nameBit symbol Set P1 N-channel output transistor drive capacity 0 : LOW 1 : HIGH Figure 17.7 Pull-up control register 0, Pull-up control register 1 and Port P1 drive capacity control register

Rev.1.00 Oct 20, 2004 page 162 of 222 M16C/1N Group 17. Programmable I/O Ports REJ09B0007-0100Z Figure 17.8 CAN0 I/O pin select register b7 b6 b5 b4 b3 b2 b1 b0 CAN0 I/O pin select register (Note 1) CIO0C CAN0 I/O pin Symbol CIOSR Address 00F816 When reset XXXXXXX02 FunctionBit nameBit symbol 0 : CTx= P02 pin CRx= P03 pin 1 : CTx= P50 pin CRx= P51 pin Note 1: Set bit 2 of protect register (address 000A16) to "1" before rewriting to this register. RW RW

Rev.1.00 Oct 20, 2004 page 163 of 222 M16C/1N Group 17. Programmable I/O Ports REJ09B0007-0100Z Pin name Connection Ports P0 to P5 (Note 1) XOUT (Note 2) VREF After setting for input mode, connect every pin to VSS (pull-down); or after setting for output mode, leave these pins open. Open XIN (Note 3) Connect to V CC (pull-up) via a resistor Connect to VSS Note 1: Connect unused pins as described above. If connected otherwise, power supply current may increase due to flow-through current on Schmitt circuit in the port. Note 2: With external clock input to XIN pin. Note 3: When the main clock oscillation circuit isn’t used, connect XIN pin to VCC (pull-up), leave XOUT pin open and set the main clock stop bit (bit 5 at address 000616) to "1" (STOP). Table 17.1 Example connection of unused pins

17.2 Example connection of unused pins

Table 17.1 shows example connection of unused pins.

Rev.1.00 Oct 20, 2004 page 164 of 222 M16C/1N Group 18. Electrical Characteristics REJ09B0007-0100Z Table 18.1 Absolute maximum ratings Note 1: CNVSS pin of flash memory version: -0.3 to 6.5 V Note 2: When flash memory version is program/erase mode: 0 to 60 °C VO - 0.3 to Vcc + 0.3 Pd Topr = 25 ˚C - 0.3 to 6.5 V Vcc Tstg Topr mW V - 65 to 150 300 - 40 to 85 (Note 2) P40 to P47, P50 to P52, XOUT P00 to P07, P10 to P17, P20, P21, P30 to P37, Parameter Unit Rated valueConditionSymbol Operating ambient temperature - 0.3 to Vcc + 0.3 V VI Input voltage Supply voltage Output voltage Power dissipation Storage temperature IVCC - 0.3 to 2.8V V RESET, VREF, XIN P00 to P07, P10 to P17, P20, P21, P30 to P37, P40 to P47, P50 to P52, CNVss (Note 1) 18. Electrical Characteristics

Rev.1.00 Oct 20, 2004 page 165 of 222 M16C/1N Group 18. Electrical Characteristics REJ09B0007-0100Z 4.2 5.5Vcc 5.0 V0Vss 0.8Vcc V V Vcc 0.2Vcc0 - 10.0 5.0 MHz mA kHz5032.768 V Vcc=4.2V to 5.5V VIH VIL mA 10.0 mA HIGH POWER LOW POWER 5.0 Typ. Max. UnitParameterSymbol Min Standard Supply voltage Supply voltage LOW input voltage HIGH input voltage - 5.0 mAHIGH average output current HIGH peak output current 10.0 mALOW peak output current Main clock input oscillation frequency (Note 3) LOW average output current Subclock oscillation frequency mA20.0 10.0 HIGH POWER LOW POWER IOH (peak) IOL (peak) IOL (avg) f (XIN) f (XcIN) IOH (avg) P10 to P17 P10 to P17 P00 to P07, P20, P21, P30 to P37, P40 to P47, P50 to P52 P00 to P07, P20, P21, P30 to P37, P40 to P47, P50 to P52 P00 to P07, P10 to P17, P20, P21, P30 to P37, P40 to P47, P50 to P52 P00 to P07, P10 to P17, P20, P21, P30 to P37, P40 to P47, P50 to P52 P00 to P07, P10 to P17, P20, P21, P30 to P37, P40 to P47, P50 to P52, XIN, RESET, CNVSS P00 to P07, P10 to P17, P20, P21, P30 to P37, P40 to P47, P50 to P52, XIN, RESET, CNVSS Note 1: The average output current is an average value measured over 100ms. Note 2: Keep output current as follows: The sum of port P00 to P03, P13 to P17, P21, P34 to P37, P46, P47, P50 to P52 IOL (peak) is under 60 mA. The sum of port P0 0 to P03, P13 to P17, P21, P34 to P37, P46, P47, P50 to P52 IOH (peak) is under 60 mA. The sum of port P04 to P07, P10 to P12, P20, P30 to P33, P40 to P45 IOL (peak) is under 60 mA. The sum of port P04 to P07, P10 to P12, P20, P30 to P33, P40 to P45 IOH (peak) is under 60 mA. Note 3: Relationship between main clock oscillation frequency and supply voltage is shown as below. Table 18.2 Recommended operating conditions (Unless otherwise noted: VCC = 4.2V to 5.5V, Topr = -40 to 85 oC) 0.0 16.0 5.54.2 Power supply voltage [V] (Main clock: no division) Main clock input oscillation frequency Highest operation frequency [MHz]

Rev.1.00 Oct 20, 2004 page 166 of 222 M16C/1N Group 18. Electrical Characteristics REJ09B0007-0100Z VOH VOH VOH VOL VOL VOL V 4.7 V2.0 3.0IOH = - 5 mA IOH = - 0.5 mA IOH = - 1 mA IOH = 0.5 mA IOH = 1 mA IOH = - 200 µA IOL = 5 mA IOL = 200 µA 0.45 V 3.0 3.0 HIGH output voltage LOW output voltage V 2.5 1.6 No load No load HIGH output voltage IIH VRAM VT+ -VT- VT+ -VT- 0.2 0.8 V 0.2 1.8 V 5.0 When clock is stopped 2.0 V RESET VI = 5V VI = 0V VI = 0V -5.0 IIL V 2.0 2.0 kΩ167.050.030.0 Hysteresis Hysteresis HIGH input current LOW input current RAM retention voltage LOW output voltage HIGH POWER LOW POWER HIGH POWER LOW POWER HIGH POWER LOW POWER VOL IOL = 5 mA IOL = 10 mA V 2.0 2.0 LOW output voltage HIGH POWER LOW POWER ROSC kHz1200600300 Oscillation frequency of On-chip oscillator Mask ROM Flash memory HIGH POWER LOW POWER V LOW output voltage RPULLUP Pull-up resistor MΩ1.0RfXIN XINFeedback resistor MΩ15.0RfXCIN XCINFeedback resistor µA µA No load No load HIGH output voltage P00 to P07,P10 to P17,P20 to P21, P30 to P37,P40 to P47,P50 to P52 P00 to P07,P20,P21,P30 to P37, P40 to P47,P50 to P52 XOUT XCOUT XOUT XCOUT P10 to P17 P00 to P07,P10 to P17,P20,P21, P30 to P37,P40 to P47,P50 to P52 CNTR0,TCIN, INT0 to INT3,CLK0,CLK1,P45 RxD0,RxD1,KI0 to KI3,CRX0 P00 to P07,P10 to P17,P20,P21, P30 to P37,P40 to P47,P50 to P52, XIN,RESET,CNVss P00 to P07,P10 to P17,P20,P21, P30 to P37,P40 to P47,P50 to P52, XIN,RESET,CNVss Symbol Standard Typ. UnitMeasuring condition Min. Max.Parameter Table 18.3 Electrical characteristics (1) (Unless otherwise noted: VCC = 5V, VSS = 0V at Topr = -40 to 85oC, f(XIN) = 16MHz)

Rev.1.00 Oct 20, 2004 page 167 of 222 M16C/1N Group 18. Electrical Characteristics REJ09B0007-0100Z Table 18.4 Electrical characteristics (2) (Unless otherwise noted: VCC = 5V, VSS = 0V at Topr = 25oC, f(XIN) = 16MHz) Symbol Standard Typ. UnitMeasuring condition Min. Max.Parameter Icc 22.0 24.0 mA 300 14.0 12.0Power supply current I/O pin has no load µA mA Mask ROM Flash memory Mask ROM Mask ROM Mask ROM f(X IN) = 16 MHz Square wave, no division On-chip oscillator mode No division 800Flash memory On-chip oscillator mode When a WAIT instruction is executed Flash memory 100 2 µA µA µA µA µA µA Mask ROM Mask ROM 0.8 f(X CIN) = 32 kHz Square wave 450 µAFlash memory f(XCIN) = 32 kHz When a WAIT instruction is executed µA Flash memory 0.8 f(X CIN) = 32 kHz When a WAIT instruction is executed Topr = 25 ˚C when clock is stopped 3 µAFlash memory Table 18.5 Power supply timing circuit characteristics td(R-S) td(W-S) Interrupt for stop or wait mode release CPU clock Min. Typ. Max. td(W-S) td(M-L) td(P-R) td(R-S) Stop release time VCC = 4.2 to 5.5 V ms µs µs 150 150 Symbol Parameter Measuring condition Unit 150 µs Standard Timer for internal power supply stabili- zation during powering-on Timer for internal power supply stabili- zation when main clock oscillation starts Wait release time during low power dis- sipation mode

Rev.1.00 Oct 20, 2004 page 168 of 222 M16C/1N Group 18. Electrical Characteristics REJ09B0007-0100Z Table 18.6 Flash memory version electrical characteristics (Unless otherwise noted: Vcc = 4.2 to 5.5 V, Topr= 0 to 60 oC) Block erasing time 2Kbyte block 8Kbyte block µs s s 600 0.2 cycle100 (Note 3) year10 0.4 16Kbyte block s90.7 32Kbyte block s91.2 Word programming time Data retention Erase/write cycle (Note 2) td(SR-ES) Erasure-suspend request (Interrupt request) FMR46 Min. Typ. (Note 1) Max. td(SR-ES) ms20 Symbol Parameter Unit Standard Transition time from erasure operation to erase-suspend Note1: Vcc=5.0V, Topr=25˚C Note2: Definition of Programming and erasure times The Programming and erasure times are defined to be per-block erasure times. For example a case where a 2K- byte block is programmed in 1,024 operations by writing one word at a time and erased thereafter. Performing multiple programs to the same address before an erase operation is prohibited. Note 3: Minimum number of programming/erasure for which operation is guaranteed.

Rev.1.00 Oct 20, 2004 page 169 of 222 M16C/1N Group 18. Electrical Characteristics REJ09B0007-0100Z Bits LSB±3 RLADDER tCONV k µs µs µs V VIA VREF VCC VREF 3.3 2.8tCONV tSAMP 0.3 LSB±3 ±2 LSB Symbol Standard Typ. UnitMeasuring condition Min. Max.Parameter Resolution Absolute accuracy Ladder resistance Conversion time(10bit) Reference voltage Analog input voltage Conversion time(8bit) Sampling time Sample & hold function not available Sample & hold function available(10bit) Sample & hold function available(8bit) ±7 LSB VREF =VCC VREF =VCC = 5V VREF =VCC = 5V VREF =VCC = 5V VREF =VCC f(XIN)=10MHz, ØAD=fAD=10MHz f(XIN)=10MHz, ØAD=fAD=10MHz f(XIN)=10MHz, ØAD=fAD=10MHz f(XIN)=10MHz, ØAD=fAD=10MHz f(XIN)=10MHz, ØAD=fAD=10MHz AN0 to AN11 input ANEX0, ANEX1 input, external op-amp connected mode Note 1: Divide the fAD if f(XIN) exceeds 10MHz, and make AD operation clock frequency (Ø AD) equal to or lower than 10MHz. Min. Typ. Max. tsu RO Resolution Absolute accuracy Setup time Output resistance Reference power supply input current Bits k mAIVREF 1.0 1.5 Symbol Parameter Measuring condition Unit 20104 µs (Note 1) Standard Note 1: The A/D converter's ladder resistance is not included. When D/A register contents are not "00 16", the current IVREF always flows even though V REF may have been set to be unconnected by the A/D control register. Table 18.7 A/D conversion characteristics (Unless otherwise noted: VCC = VREF = 5V, VSS = 0V at Topr = 25oC, f(XIN) = 16MHz) Table 18.8 D/A conversion characteristics (Unless otherwise noted: VCC = VREF = 5V, VSS = 0V at Topr = 25oC, f(XIN) = 16MHz)

Rev.1.00 Oct 20, 2004 page 170 of 222 M16C/1N Group 18. Electrical Characteristics REJ09B0007-0100Z

18.1 Timing requirements

(Unless otherwise noted: VCC = 5V, VSS = 0V at Topr = -40 to 85oC) Table 18.9 XIN input ns ns ns tc(CNTR0) twH(CNTR0) twL(CNTR0) 100 40CNTR0 input LOW pulse width CNTR0 input HIGH pulse width ParameterSymbol CNTR0 input cycle time Standard UnitMin. Max. ns ns ns tc(XIN) twH(XIN) twL(XIN) 62.5 30XIN input LOW pulse width XIN input HIGH pulse width ParameterSymbol XIN input cycle time Standard UnitMin. Max. ns ns ns tc(TCIN) twH(TCIN) twL(TCIN) 400(Note 1) 200(Note 2) 200(Note 2)TCIN input LOW pulse width TCIN input HIGH pulse width ParameterSymbol TCIN input cycle time Standard UnitMin. Max. Table 18.10 CNTR0 input Table 18.11 TCIN input ns nstw(INH) tw(INL) 250(Note 1) 250(Note 2)INTi input LOW pulse width ParameterSymbol INTi input HIGH pulse width Standard UnitMin. Max. ns ns ns tc(CK) tw(CKH) tw(CKL) 200 100 100CLKi input LOW pulse width CLKi input HIGH pulse width ns nstd(C-Q) th(C-Q) TxDi hold time TxDi output delay time ns nst su(D-C) th(C-D) RxDi input hold time RxDi input setup time ParameterSymbol CLKi input cycle time Standard UnitMin. Max. Table 18.12 Serial I/O Table 18.13 External interrupt INTi input Note 1: Use the greater value, either (1/digital filter clock frequency X 6) or min. value. Note 2: Use the greater value, either (1/digital filter clock frequency X 3) or min. value. Note 1: When the INT0 input filter select bit selects the digital filter, use the INT0 input HIGH pulse width to the greater value, either (1/digital filter clock frequency X 3) or min. value. Note 2: When the INT0 input filter select bit selects the digital filter, use the INT0 input LOW pulse width to the greater value, either (1/digital filter clock frequency X 3) or min. value.

Rev.1.00 Oct 20, 2004 page 171 of 222 M16C/1N Group 18. Electrical Characteristics REJ09B0007-0100Z 30pF Figure 18.1 Port P0 to P5 measurement circuit

Rev.1.00 Oct 20, 2004 page 172 of 222 M16C/1N Group 18. Electrical Characteristics REJ09B0007-0100Z CNTR0 input TCIN input tc(CNTR0) tWH(CNTR0) tWL(CNTR0) tc(TCIN) tWH(TCIN) tWL(TCIN) tsu(D-C) CLKi TxDi RxDi tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) INTi input td(C-Q) th(C-D) th(C-Q) XIN input tc(XIN) tWH(XIN) tWL(XIN) Figure 18.2 Vcc=5V timing diagram

Rev.1.00 Oct 20, 2004 page 173 of 222 M16C/1N Group 19. Flash Memory Version REJ09B0007-0100Z Table 19.1 Outline performance of flash memory version 19. Flash Memory Version

19.1 Overview

The flash memory version has four modes—CPU rewrite, standard serial input/output (hereinafter re- ferred to as standard serial I/O), parallel input/output (hereinafter referred to as parallel I/O), and CAN input/output (hereinafter referred to as CAN I/O) modes—in which its internal flash memory can be oper- ated on. Table 19.1 shows the outline performance of flash memory version and Table 19.2 shows the outline of flash memory rewrite mode. (see Table 1.1 Performance outline for the items not listed in Table 19.1). Item Flash memory operation mode Erase block division Program method Erase method Program, erase control method Protect method Number of commands Program, erase count Block 0 to 3 Block A and B (Data area) ROM code protect Performance Four modes (CPU rewrite, parallel I/O, standard serial I/O and CAN I/O) See Figure 19.1 Outline performance of flash memory version In units of word, in units of byte (Note 1) Block erase Program and erase controlled by software command Block 0 and 1 are protected by register rewrite (FMR02) Block 0 to 3 are protected by register rewrite enable bit (FMR16) 5 commands 100 times 100 times Parallel I/O, standard serial I/O and CAN I/O modes are supported Note 1: Can be programmed in byte units in only parallel I/O mode. Data retention 10 years Table 19.2 Outline of flash memory rewrite mode The user ROM area is rewritten by executing software commands from the CPU. EW0 mode: Can be rewritten in any area other than the flash memory EW1 mode: Can be rewritten in the flash memory User ROM area Single chip mode None The user ROM area is rewritten by using a dedicated serial pro- grammer. Standard serial I/O mode 1: Clock sync. serial I/O Standard serial I/O mode 2 (Note 1): UART User ROM area Boot mode Serial programmer The user ROM area is rewritten by using a dedicated parallel pro- grammer. User ROM area, Boot ROM area Parallel I/O mode Parallel programmer The user ROM area is rewritten by using a dedicated CAN pro- grammer. User ROM area Boot mode CAN programmer Function Areas which can be rewritten Operation mode ROM programmer Flash memory rewrite mode CPU rewrite mode Standard serial I/O modeParallel I/O mode CAN I/O mode Note 1: When using the standard serial I/O mode 2, make sure a main clock input oscillation frequency is set to 10 or 16 MHz.

Rev.1.00 Oct 20, 2004 page 174 of 222 M16C/1N Group 19. Flash Memory Version REJ09B0007-0100Z

19.2 Flash Memory

The ROM in the flash memory version is separated between a user ROM area and a boot ROM area. Figure 19.1 shows the block diagram of flash memory. The user ROM area has 2K-byte block A and B, in addition to the area that stores a program for microcomputer operation during singe-chip mode. The user ROM area is divided into several blocks. The user ROM area can be rewritten in all of CPU rewrite, standard serial I/O, parallel I/O and CAN I/O modes. Block 0 and 1 can be rewritten by setting FMR0 register's FMR02 bit to "1" and the FMR1 register's FMR16 bit to "1" in CPU rewrite mode only. Block 2 and 3 can be rewriting by setting the FMR 1 register's FMR 16 bit to "1". Block A and B are enabled for use by setting the PM1 register's PM10 bit to "1". The boot ROM area is reserved area. A rewrite control program for standard serial I/O and CAN I/O modes is written into the boot ROM area when the device is shipped from the factory. The boot ROM area can be rewritten in parallel I/O mode. Figure 19.1 Block diagram of flash memory 4K bytes (Note 4) 0FFFFF16 Boot ROM area (Reserved area) 0F000016 Block 0 : 8K bytes (Note 3) Block 1 : 8K bytes (Note 3) 00FFFF16 Block A : 2K bytes (Note 2) 0FFFFF16 00F00016 0FF00016 User ROM area (Note 1) Data ROM area Block B : 2K bytes (Note 2) Block 3 : 32K bytes (Note 5) Block 2 : 16K bytes (Note 5) 0F7FFF16 0F800016 0FBFFF16 0FC00016 0FDFFF16 0FE00016 Note 1: To specify a block, use an even address in that block. Note 2: Block A and B can be mode usable by setting the PM1 register’s PM10 bit to "1". Note 3: Block 0 and 1 can be rewritten by setting FMR0 register’s FMR02 bit to "1" and the FMR 1 register’s FMR16 bit to "1" in CPU rewrite mode only. Block 2 and 3 can be rewriting by setting the FMR1 register’s FMR16 bit to "1". Note 4: The boot ROM area is reserved area. This area can be rewritten in parallel I/O mode. Note 5: Block 2 and 3 can be rewriting by setting the FMR1 register’s FMR16 bit to "1" (in CPU rewrite mode only).

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19.3 Functions to Inhibit Rewriting Flash Memory Version

To prevent the flash memory from being read or rewritten easily, parallel I/O mode has a ROM code protect and standard serial I/O and CAN I/O modes have an ID code check function.

19.3.1 ROM code protect function

The ROM code protect function inhibits the flash memory from being read or rewritten during parallel I/O mode. Figure 19.2 shows the ROMCP register. The ROMCP register is located in the user ROM area. The ROMCP1 bit consists of two bits. The ROM code protect function is enabled by clearing one or both of two ROMCP1 bits to "0" when the ROMCR bits are not '00 2,' with the flash memory thereby protected against reading or rewriting. Conversely, when the ROMCR bits are '00 2' (ROM code protect removed), the flash memory can be read or rewritten. Once the ROM code protect function is enabled, the ROMCR bits cannot be changed during parallel I/O mode. Therefore, use standard serial I/O or other modes to rewrite the flash memory.

19.3.2 ID code check function

Use this function in standard serial I/O and CAN I/O modes. Unless the flash memory is blank, the ID codes sent from the programmer and the ID codes written in the flash memory are compared to see if they match. If the ID codes do not match, the commands sent from the programmer are not accepted. The ID code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFDF 16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. Prepare a program in which the ID codes are preset at these addresses and write it in the flash memory. Figure 19.3 shows ID code store addresses.

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19.4 Boot Mode

When the microcomputer is reset by applying a high-level signal to the CNVSS and CE pins, it is placed in boot mode, thereby executing the program in the boot ROM area. During boot mode, the boot ROM and user ROM areas are switched over by the FMR0 register's FMR05 bit.

Rev.1.00 Oct 20, 2004 page 178 of 222 M16C/1N Group 19. Flash Memory Version REJ09B0007-0100Z Table 19.3 Differences between EW0 mode and EW1 mode Item EW0 mode EW1 mode Operation mode • Single chip mode Single chip mode Areas in which a • User ROM area User ROM area rewrite control program can be located Areas in which a Must be transferred to any area other Can be executed directly in the user rewrite control than the flash memory (e.g., RAM) ROM area program can be executed before being executed Areas which can be User ROM area (Note 1) User ROM area (Note 1) rewritten However, this does not include the area in which a rewrite control program exists Software command None • Program, Block Erase command limitations Cannot be executed on any block in which a rewrite control program exists

• Read Status Register command Cannot be executed Modes after Program or Read Status Register mode Read Array mode Erase CPU status during Auto Operating Hold state (I/O ports retain the state in Write and Auto Erase which they were before the command was executed)(Note 2) Flash memory status • Read the FMR0 register's FMR00, Read the FMR0 register's FMR00, detection FMR06, and FMR07 bits in a FMR06, and FMR07 bits in a program program
• Execute the Read Status Register command to read the status register's SR7, SR5, and SR4 flags. The shift conditions to Set the FMR4 register's FMR40 and The FMR register's FMR40 bit is "1" and erasure-suspend (Note 3) RMR41 bits to "1" by program. generated the interrupt request of enabled interrupt. Note 1: Can be rewritten block 0 and 1 when setting the FMR0 register's FMR02 bit to "1" and the FMR1 register's FMR16 bit to "1". Block 2 and 3 can be rewriting by setting the FMR1 register's FMR16 bit to "1". Note 2: Make sure no interrupts will occur. Note 3: The conditions are met and it takes a maximum of td(SR-ES) time until a flash memory can be read after shifting to erasure-suspend.

19.5 CPU Rewrite Mode

In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU. Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on- board without having to use a ROM programmer, etc. Make sure the program and the block erase commands are executed only on each block in the user ROM area. When generating an interrupt request during erasure operation in CPU mode, the M16C/1N Group flash memory can offer the erasure-suspend feature which allows erasure operation to be suspended and to process the interrupt. User ROM area can be read in a program during erasure-suspend. During CPU rewrite mode, the user ROM area be operated on in either Erase Write 0 (EW0) mode or Erase Write 1 (EW1) mode. Table 19.3 lists the differences between Erase Write 0 (EW0) and Erase Write 1 (EW1) modes.

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19.5.1 EW0 mode

The microcomputer is placed in CPU rewrite mode by setting the FMR0 register's FMR01 bit to "1" (CPU rewrite mode enabled), ready to accept commands. In this case, because the FMR1 register's FMR11 bit = 0, EW0 mode is selected. The FMR01 bit can be set to "1" by writing "0" and then "1" in succession. Use software commands to control program and erase operations. Read the FMR0 register or status register to check the status of program or erase operation at completion. When shifting to erasure-suspend during auto erasing, set the FMR40 bit to "1" (Suspend enable) and the FMR41 bit to "1" (Suspend request). After waiting for td (SR-ES) time, access user ROM area after confirming that the FMR46bit has been set to "1" (Erase inactive). Setting the FMR41 bit to "0" (Erase restart), the erasure operation is resumed.

19.5.2 EW1 mode

EW1 mode is selected by setting FMR11 bit to "1" (by writing "0" and then "1" in succession) after setting the FMR01 bit to "1" (by writing "0" and then "1" in succession). Read the FMR0 register to check the status of program or erase operation at completion. The status register cannot be read during EW1 mode. When enabling the erasure-suspend feature, execute the block erase command after setting the FMR40 bit to "1" (Suspend enable). In addition, the interrupt for shifting to erasure suspend has to have been enabled beforehand. When shifting to erasure-suspend after td (SR-ES) time from interrupt request, the interrupt request is accepted. When the interrupt request occurs, the FMR41bit is set to "1" (Suspend request) automatically and erasure operation is suspended. After processing the interrupt, when the FM00 bit is "0" (Busy (being erased)), set the FMR41 bit to "0" and re-execute the block erase command.

Rev.1.00 Oct 20, 2004 page 181 of 222 M16C/1N Group 19. Flash Memory Version REJ09B0007-0100Z Flash memory control register 0 Symbol Address After reset FMR0 01B7 16 XX0000012 b7 b6 b5 b4 b3 b2 b1 b0 FMR00 Bit symbol Bit name RW 0 : Busy (being written or erased) 1 : Ready CPU rewrite mode select bit (Note 1) 0 : Disables CPU rewrite mode 1 : Enables CPU rewrite mode FMR01 Block 0, 1 rewrite-enable bit (Note 2) 0 : Disables rewriting 1 : Enables rewriting Flash memory stop bit (Note 3, 4) FMR02 FMSTP RY/BY status flag Reserved bit Set to "0" 0 : Terminated normally 1 : Terminated in error Program status flag (Note 5)FMR06 0 : Terminated normally 1 : Terminated in error Erase status flag (Note 5)FMR07 Function RW RW RW RW RO RO 0 : Boot ROM area is accessed 1 : User ROM area is accessed User ROM area select bit (Effective in only boot mode) (Note 3) FMR05 RW RO (b4) 0 : Enables flash memory operation 1 : Stops flash memory operation (placed in low power mode, flash memory initialized) Note 1: When setting this bit to "1", write a "0" and then a "1" in to it in succession. Make sure no interrupts will occur before completion of these two write operations. In EW0 mode, write this bit by a program placed to an area other than internal flash memory. Set this bit to "0" after placing in read array mode. Note 2: When setting this bit to "1", write a "0" and then a "1" in to it in succession while the FMR01 bit is "1". Make sure no interrupts will occur before completion of these two write operations. Note 3: Write this bit by a program placed to an area other than internal flash memory. Note 4: This bit is valid when the FMR01 bit is "1" (CPU rewrite mode). When the FMR01 bit is "0", although the FMSTP bit can be set to "1" by writing "1" in a program, the flash memory is not initialized. Note 5: This bit is cleared to "0" by executing the clear status command. Figure 19.4 FMR0 Register (11) FMR 41bit In EW0 mode, when setting the FMR41 bit to "1" by software during auto erasing, the microcomputer shifts to the erasure-suspend mode. In EW1 mode, when occurring the enabled interrupt request, the FMR 41bit changes to "1" (Suspend- request) automatically and the microcomputer shifts to the erasure-suspend mode. Setting the FMR41 bit to "0" (Erase restart), auto erasing is resumed. (12) FMR46bit The FMR46 bit is "0" during auto erasing and is "1" during the erasure-suspend mode. The internal flash memory is banned to access while the FMR41 bit is "0".

Rev.1.00 Oct 20, 2004 page 182 of 222 M16C/1N Group 19. Flash Memory Version REJ09B0007-0100Z Flash memory control register 1 Symbol Address After reset FMR1 01B5 16 0000XX0X2 b7 b6 b5 b4 b3 b2 b1 b0 Bit symbol Bit name Function EW1 mode select bit (Note 1) 0 : EW0 mode 1 : EW1 mode FMR11 Reserved bit Set to "0" Reserved bit The value in this bit when read is indeterminate. Reserved bit Set to "0" RW RO RW Block 0-3 rewrite enable bit (Note 2) 0 : Disables rewriting 1 : Enables rewriting FMR16 RW RW RW (b0) (b5-b4) (b7) Reserved bit The value in this bit when read is indeterminate.(b3-b2) RO Note 1: When setting this bit to "1", write a "0" and then a "1" in succession while the FMR01 bit is "1". Make sure no interrupts will occur before completion of these two write operations. The FMR01 and FMR11 bits both are cleared to "0" by setting the FMR01 bit to "0". Note 2: When setting this bit to "1", write a "0" and then a "1" to it in succession while the FMR01 bit is "1". Make sure no interrupts will occur before completion of these two write operations. Flash memory control register 4 Symbol Address After reset FMR4 01B3 16 010000002 b7 b6 b5 b4 b3 b2 b1 b0 Bit symbol Bit name Function Suspend request bit (Note 2) 0 : Erase restart 1 : Suspend request FMR41 Reserved bit Set to "0" 00 00 RW RW Suspend enable bit (Note 1) 0 : Invalid 1 : Valid FMR40 RW Suspend status 0 : Erase active 1 : Erase inactive (erasure-suspend) FMR46 RO Set to "0" RO RW (b7) Reserved bits(b5-b2) Note 1: When setting this bit to "1", write a "0" and then a "1" to it in succession. Make sure no interrupts will occur before completion of these two write operations. Note 2: This bit is valid only when the FMR40 bit is "1" and can be written in only the period from issuing an erase command until completion of erasing.

• In EW0 mode, this bit can be set to "0" or "1" by program.
• In EW1 mode, this bit is automatically set to "1" when a maskable interrupt occurs during erasure execution while the FMR40 bit is "1". It can not be set to "1" by program. (Writing "0" is available.) Figure 19.5 FMR1 Register, FMR4 Register

Rev.1.00 Oct 20, 2004 page 184 of 222 M16C/1N Group 19. Flash Memory Version REJ09B0007-0100Z Figure 19.7 Setting and resetting of EW1 mode Single-chip mode Set CM0, CM1, and PM1 registers (Note 1) Set the FMR01 bit by writing "0" and then "1" (CPU rewrite mode enabled) Set the FMR11 bit by writing "0" and then "1" (EW1 mode) (Note 2) Program in ROM EW1 mode operation procedure Execute software commands Write "0" to the FMR01 bit (CPU rewrite mode disabled) Note 1: Select 10 MHz or less for CPU clock using the CM0 register’s CM06 bit and CM1 register’s CM17 to 6 bits. Also, set the PM1 register’s PM17 bit to "1" (with wait state). Note 2: To set the FMR01 bit to "1", write "0" and then "1" in succession. Make sure no interrupts will occur before writing "1" after writing "0".

Rev.1.00 Oct 20, 2004 page 185 of 222 M16C/1N Group 19. Flash Memory Version REJ09B0007-0100Z Figure 19.8 Processing before and after low power dissipation mode Turn XIN on Transfer a low power dissipation mode program to any area other than the flash memory Switch the clock source for CPU clock. Turn XIN off. (Note 2) Jump to the low power dissipation mode program which has been transferred to any area other than the flash memory. (The subsequent processing is executed by a program in any area other than the flash memory.) Wait until the flash memory circuit stabilizes (10 µs) (Note 3) Set the FMSTP bit to "0" (flash memory operation) Set FMSTP bit to "1" (flash memory stopped. Low power state) (Note 1) Process of low power dissipation mode or on-chip oscillator low power dissipation mode switch the clock source for CPU clock (Note 2) Low power dissipation mode program Write "0" to the FMR01 bit (CPU rewrite mode disabled) Set the FMR01 bit by writing "0" and then "1" (CPU rewrite mode enabled) Jump to a specified address in the flash memory wait until oscillation stabilizes Note 1: Set the FMSTP bit to "1" after setting the FMR01 bit to "1". Note 2: Before the clock source for CPU clock can be changed, the clock to which to be changed must be stable. Note 3: Insert a 10 µs wait time in a program. The flash memory cannot be accessed during this wait time.

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19.5.3 Precautions on CPU Rewrite Mode

Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation speed Before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or less for BCLK using the CM0 register's CM06 bit and CM1 register's CM17–6 bits. Also, set the PM1 register's PM17 bit to "1" (with wait state). (2) Instructions inhibited against use In EW0 mode, the following instructions cannot be used because the flash memory's internal data is referenced: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruc- tion (3) Interrupts EW0 mode

• Any interrupt which has a vector in the variable vector table can be used providing that its vector is transferred into the RAM area.
• The watchdog timer interrupt can be used because the FMR0 register and FMR1 register are initialized when one of those interrupts occurs. However, it is necessary that the jump addresses for those interrupts are set in the fixed vector table, and that interrupt service routines are available for those interrupts. Because the rewrite operation is halted when a watchdog timer interrupt occurs, the FMR01 bit must be set back to "1" again in order to enable erase or programming operation after exiting the interrupt service routine.
• The address match interrupt cannot be used because the flash memory's internal data is refer- enced. EW1 mode
• Make sure that any interrupt which has a vector in the variable vector table or address match interrupt will not be accepted during the auto program or auto erase period. (4) How to access To set the FMR01, FMR02, or FMR11 bit to "1", write "0" and then "1" in succession. This is necessary to ensure that no interrupts will occur before writing "1" after writing "0". (5) Writing in the user ROM area If the power supply voltage drops while rewriting in EW0 mode any block in which the rewrite control program is stored, a problem may occur that the rewrite control program is not correctly rewritten and, consequently, the flash memory becomes unable to be rewritten thereafter. It is recommended that such a block be rewritten using standard serial I/O, CAN I/O or parallel I/O mode. (6) Writing command and data Write the command code and data at even addresses.

Rev.1.00 Oct 20, 2004 page 187 of 222 M16C/1N Group 19. Flash Memory Version REJ09B0007-0100Z (7) Wait mode When shifting to wait mode, set the FMR01 bit to "0" (CPU rewrite mode disabled) before executing the WAIT instruction. (8) Stop mode When shifting to stop mode, the following settings are required:

• Set the FMR01 bit to "0" (CPU rewrite mode disabled) and setting the CM10 bit to "1" (stop mode).
• Execute the JMP.B instruction subsequent to the instruction which sets the CM10 bit to "1" (stop mode) Example program BSET 0, CM1 ; Stop mode JMP.B L1 L1: Program after returning from stop mode (9) Low power dissipation mode, on-chip oscillator low power dissipation mode If the CM05 bit is set to "1" (main clock stop), the following commands must not be executed.
• Program
• Block erase

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19.5.4 Software Commands

Software commands are described below. The command code and data must be read and written in 16 bit units, to and from even addresses in the user ROM area. When writing command code, the 8 high-order bits (D 15-D8) are ignored. Table 19.4 shows the list of software commands. Table 19.4 List of software commands (1) Read array This command reads the flash memory. Writing 'xxFF 16' in the first bus cycle places the microcomputer in read array mode. Enter the read address in the next or subsequent bus cycles, and the content of the specified address can be read in 16 bit units. Because the microcomputer remains in read array mode until another command is written, the con- tents of multiple addresses can be read in succession. (2) Read status register This command reads the status register. Write 'xx70 16' in the first bus cycle, and the status register can be read in the second bus cycle (refer to 19.5.5 Status Register). When reading the status register too, specify an even address in the user ROM area. Do not execute this command in EW1 mode. (3) Clear status register This command clears the status register to "0". Write 'xx50 16' in the first bus cycle, and the FMR0 register's FMR06 to FMR07 bits and the status register's SR4 to SR5 will be cleared to "0". Software Command Program Clear status register Read array Read status register First bus cycle Second bus cycle Block erase Write Write Write Write Write Mode Read Write Write Mode X WA BA Address SRD WD xxD016 Data (D15-D0) xxFF16 xx7016 xx5016 xx4016 xx2016 Data (D15-D0) X X X WA X Address SRD: Status register data (D7-D0) WA: Write address (even address, however) WD: Write data (16 bits) BA: Uppermost block address (even address, however) X: Any even address in the user ROM area x: High-order 8 bits of command code (ignored)

Rev.1.00 Oct 20, 2004 page 191 of 222 M16C/1N Group 19. Flash Memory Version REJ09B0007-0100Z Figure 19.11 Block erase flowchart (when using the erasure suspend feature) Write ’xxD016’ to uppermost block address (Note1) FMR40=1 FMR41=1 FMR41=0 Start Block erase completed YES NO Write the command code ’xx2016’ (Note 1) Access to flash memory FMR00=1? Full status check (Note 2, 3) Interrupt (Note 4) REIT YES NO FMR46=1? Access to flash memory Interrupt (Note 4) REIT Write ’xxD016’ to the uppermost block address (Note 1) Start (EW1 mode) (EW0 mode) Block erase completed YES NO Write the command code ’xx2016’ (Note 1) FMR00=1? FMR40=1 FMR41=0 Full status check (Note 2, 3) Note 1: Write the command code and data at even number. Note 2: See Figure 19.12 Full status check flowchart, handling each error generated. Note 3: When the erase error occurred, repeat the operation executing the clear status register command and then the block erase command in succession at least 3 times until the error is eliminated. Note 4: In EW0 mode, allocate the interrupt vector table of used interrupt to the internal RAM.

Rev.1.00 Oct 20, 2004 page 192 of 222 M16C/1N Group 19. Flash Memory Version REJ09B0007-0100Z Status register bit SR4 (D4) SR5 (D5) SR7 (D7) SR6 (D6) Status name Contents SR1 (D1) SR2 (D2) SR3 (D3) SR0 (D0) Program status Erase status Sequencer status Reserved Reserved Reserved Reserved "1" Ready Terminated in error Terminated in error "0" Busy Terminated normally Terminated normally -Reserved FMR0 register bit Value after reset FMR00 FMR07 FMR06

19.5.5 Status Register

The status register indicates the operating status of the flash memory and whether an erase or pro- gramming operation terminated normally or in error. The status of the status register can be known by reading the FMR0 register's FMR00, FMR06, and FMR07 bits. Table 19.5 shows the status register. In EW0 mode, the status register can be read in the following cases:

• When a given even address in the user ROM area is read after writing the Read Status Register command
• When a given even address in the user ROM area is read after executing the program, or block erase command but before executing the read array command. (1) Sequencer status (SR7 and FMR00 bits ) The sequence status indicates the operating status of the flash memory. SR7 = 0 (busy) during auto programming and auto erase is set to "1" (ready) at the same time the operation finishes. (2) Erase status (SR5 and FMR07 bits) Refer to 19.5.6 Full status check. (3) Program status (SR4 and FMR06 bits) Refer to 19.5.6 Full status check.
• The FMR07 bit (SR5) and FMR06 bit (SR4) are cleared to "0" by executing the clear status register command.
• When the FMR07 bit (SR5) or FMR06 bit (SR4) = 1, the program, block and erase commands are not accepted.
• D 0-D7: Indicates the data bus which is read out when the read status register command is executed. Table 19.5 Status register

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19.5.6 Full Status Check

When an error occurs, the FMR0 register's FMR06 to FMR07 bits are set to "1", indicating occurrence of each specific error. Therefore, execution results can be verified by checking these status bits (full status check). Table 19.6 lists errors and FMR0 register status. Figure 19.12 shows a full status check flowchart and the action to be taken when each error occurs. Table 19.6 Errors and FMR0 register status FRM00 register (status register) status Error Error occurrence condition FMR07 FMR06 (SR5) (SR4)

11 Command • When any command is not written correctly

sequence error • When invalid data was written other than those that can be writ- ten in the second bus cycle of the block erase command (i.e., other than 'xxD0 16' or 'xxFF16') (Note 1)

10 Erase error • When the block erase command was executed on locked blocks

but the blocks were not automatically erased correctly.

01 Program error • When the program command was executed on unlocked blocks

but the blocks were not automatically programmed correctly. Note 1: Writing 'xxFF16' in the first bus cycle places the microcomputer in read array mode. Simultaneously, the command code written in the first cycle becomes invalid.

Rev.1.00 Oct 20, 2004 page 194 of 222 M16C/1N Group 19. Flash Memory Version REJ09B0007-0100Z Full status check FMR06 =1 and FMR07=1? NO Command sequence error YES FMR07=0? YES Erase error NO FMR06=0? YES Program error NO Full status check completed (1) Execute the clear status register command to clear these status flags to "0". (2) Reexecute the command after checking that it is entered correctly. (1) Execute the clear status register command to clear the erase status flag to "0". (2) Reexecute the block erase command. (3) Repeat the operation executing (1) and (2) at least 3 times until the error is eliminated. Note 1: If the error still occurs, the block in error cannot be used. [During programming] (1) Execute the clear status register command to clear the erase status flag to "0". (2) Reexecute the program command. Note 2: If the error still occurs, the block in error cannot be used. Note 3: If FMR06 or FMR07 = 1, the program, or block erase command is not accepted. Execute the clear status register command before executing those commands. Figure 19.12 Full status check flowchart, handling each error generated

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19.6 Parallel Input/Output Mode

In parallel I/O mode, the user ROM area can be rewritten by using a parallel programmer suitable for the M16C/1N group. For more information about parallel programmers, contact the manufacturer of your parallel programmer. For details on how to use, refer to the user's manual included with your parallel programmer.

19.6.1 ROM code protect function

The ROM code protect function inhibits the flash memory from being read or rewritten. (refer to the description of 19.3 Functions to Inhibit Rewriting Flash Memory Version).

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19.7 Standard Serial Input/Output Mode

In standard serial I/O mode, the user ROM area can be rewritten while the microcomputer is mounted on- board by using a serial programmer suitable for the M16C/1N group. For more information about serial programmers, contact the manufacturer of your serial programmer. For details on how to use, refer to the user's manual included with your serial programmer. There are actually two standard serial I/O modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. Table 19.7 lists pin functions (flash memory standard serial I/O mode). Figure 19.13 shows pin connec- tions for standard serial I/O mode.

19.7.1 ID code check function

This function determines whether the ID codes sent from the serial programmer and those written in the flash memory match (refer to the description of 19.3 Functions to Inhibit Rewriting Flash Memory Version).

Rev.1.00 Oct 20, 2004 page 197 of 222 M16C/1N Group 19. Flash Memory Version REJ09B0007-0100Z Pin DescriptionName I/O Apply the voltage guaranteed for program and erase to Vcc pin and 0 V to Vss pin. Connect a capacitor (0.1µF) to V SS pin. Connect to VCC pin Reset input pin. While RESET pin is "L" level, input a 20 cycle or longer clock to X IN pin. Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin. Enter the reference voltage for AD from this pin. Connect to VCC or VSS pin. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Serial data output pin (Note 1) Serial data input pin Standard serial I/O mode 1: Serial clock input pin. Standard serial I/O mode 2: Input "L" level signal. Standard serial I/O mode 1: BUSY signal output pin Standard serial I/O mode 2: Monitors the boot program operation check signal output pin. Input "H" or "L" level signal or open. SEL signal input pin. Input "L" level signal. CE signal input pin. Input "H" level signal. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. V CC, VSS IVCC CNVSS RESET XIN XOUT VREF P00 to P07 P10 to P13 P14 P15 P16 P17 P20, P21 P30 P31 P32 to P37 P40 to P47 P50 to P52 I I I I I O I I I O I I O I I I I I I Power input IV CC input CNVSS input Reset input Clock input Clock output Reference voltage input Input port P0 Input port P1 T XD output RXD input SCLK input BUSY output Input port P2 SEL input CE input Input port P3 Input port P4 Input port P5 Table 19.7 Pin functions (Flash memory standard serial I/O mode) Note 1: When using standard serial I/O mode 1, the TxD pin must be held high while the RESET pin is low. Therefore, connect this pin to V CC via a resistor. Because this pin is directed for data output after reset, adjust the pull-up resistance value in the system so that data transfers will not be affected.

Rev.1.00 Oct 20, 2004 page 198 of 222 M16C/1N Group 19. Flash Memory Version REJ09B0007-0100Z Figure 19.13 Pin connections for standard serial I/O mode CNVss RESET CE SEL 6/CLK1 P35/RXD1 P34/CLKS1/DA CNVSS P47/XCIN P46/XCOUT RESET XOUT VSS XIN VCC P17/CNTR0 CNVss 4/INT2 P45/INT0 P10/KI0/AN8 P11/KI1/AN9 P12/KI2/AN10 P20 NC P21 P13/KI3/AN11 P14/TXD0 P15/RXD0 P16/CLK0 6/AN1 P05/AN2 P04/AN3 VREF P52 P51/CRx P50/CTx P03/AN4/CRx P02/AN5/CTx P01/AN6 P00/AN7 P37/TXD1/RXD1 M16C/1N Group P07/AN0 IVCC P30/TXOUT VSS P31/TZOUT VCC P40/ANEX0 P41/ANEX1 P42/INT3 P43/INT1 P32/TYOUT P33/TCIN RESET Vss Vcc TxD BUSY RxD SCLK SEL Signal Mode setup method Value Vcc Vss Vcc Vcc Vss CE Package 48P6Q-A

Rev.1.00 Oct 20, 2004 page 200 of 222 M16C/1N Group 19. Flash Memory Version REJ09B0007-0100Z Figure 19.15 Example for processing pins when using standard serial I/O mode 2 Monitor output Data output Data input (P17)BUSY (P16)SCLK (P14)TXD CNVss CE(P31) Microcomputer SEL(P30) CRx CTx CAN transceiver CAN H CAN H CAN LCAN L (P15)RxD (1) In this example, modes are switched between single-chip mode and standard serial I/O mode by controlling the CNVss input with a switch. (2) Make sure a main clock input oscillation frequency is set to 10 or 16MHz. Reset input RESET User reset signal

Rev.1.00 Oct 20, 2004 page 201 of 222 M16C/1N Group 19. Flash Memory Version REJ09B0007-0100Z

19.8 CAN Input/Output Mode

In CAN I/O mode, the user ROM area can be rewritten while the microcomputer is mounted on-board by using a CAN programmer suitable for the M16C/1N group. For more information about CAN program- mers, contact the manufacturer of your CAN programmer. For details on how to use, refer to the user's manual included with your CAN programmer. Table 19.8 lists pin functions (flash memory CAN I/O mode). Figure 19.16 shows pin connections for CAN I/O mode.

19.8.1 ID code check function

This function determines whether the ID codes sent from the CAN programmer and those written in the flash memory match (refer to the description of 19.3 Functions to Inhibit Rewriting Flash Memory Version) Pin DescriptionName I/O Apply the voltage guaranteed for program and erase to Vcc pin and 0 V to Vss pin. Connect a capacitor (0.1µF) to V SS pin. Connect to VCC pin Reset input pin. While RESET pin is "L" level, input a 20 cycle or longer clock to X IN pin. Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin. Enter the reference voltage for AD from this pin. Connect to VCC or VSS pin. Input "H" or "L" level signal or open. CAN output pin. Connect this pin to CAN transceiver. CAN input pin. Connect this pin to CAN transceiver. Input "H" or "L" level signal or open. SCLK signal input pin. Input "L" level signal. Input "H" or "L" level signal or open. SEL signal input pin. Input "H" level signal. CE signal input pin. Input "H" level signal. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. V CC, VSS IVCC CNVSS RESET XIN XOUT VREF P00, P01 P04 to P07 P02 P03 P10 to P15, P17 P16 P20, P21 P30 P31 P32 to P37 P40 to P47 P50 to P52 I I I I I O I I O I I I I I I I I I Power input IV CC input CNVSS input Reset input Clock input Clock output Reference voltage input Input port P0 CT X output CRX input Input port P1 SCLK input Input port P2 SEL input CE input Input port P3 Input port P4 Input port P5 Table 19.8 Pin functions (Flash memory CAN I/O mode)

Rev.1.00 Oct 20, 2004 page 202 of 222 M16C/1N Group 19. Flash Memory Version REJ09B0007-0100Z Figure 19.16 Pin connections for CAN I/O mode CNVss RESET CE SEL SCLK Signal Mode setup method Value Vcc Vss Vcc Vcc Vcc Vss 6/CLK1 P35/RXD1 P34/CLKS1/DA CNVSS P47/XCIN P46/XCOUT RESET XOUT VSS XIN VCC P17/CNTR0 CNVss 4/INT2 P45/INT0 P10/KI0/AN8 P11/KI1/AN9 P12/KI2/AN10 P20 NC P21 P13/KI3/AN11 P14/TXD0 P15/RXD0 P16/CLK0 6/AN1 P05/AN2 P04/AN3 VREF P52 P51/CRx P50/CTx P03/AN4/CRx P02/AN5/CTx P01/AN6 P00/AN7 P37/TXD1/RXD1 M16C/1N Group P07/AN0 IVCC P30/TXOUT VSS P31/TZOUT VCC P40/ANEX0 P41/ANEX1 P42/INT3 P43/INT1 P32/TYOUT P33/TCIN RESET Vss Vcc CRx CTx SEL CE Package 48P6Q-A SCLK

Rev.1.00 Oct 20, 2004 page 204 of 222 M16C/1N Group REJ090007-0100Z 20. Precautionary Notes in Using the Device 20. Precautionary Notes in Using the Device

20.1 Clock

20.1.1 External Clock

Do not stop the external clock when it is connected to the XIN pin and the main clock is selected as the CPU clock.

20.1.2 Power Control

When exiting stop mode by hardware reset, set RESET pin to "L" for at least 200 µs or longer. 2. Insert more than four NOP instructions after an WAIT instruction or a instruction to set the CM10 bit of the CM1 register to "1". When shifting to wait mode or stop mode, an instruction queue reads ahead to the next instruction to halt a program by an WAIT instruction and an instruction to set the CM10 bit to "1" (all clocks stopped). The next instruction may be executed before entering wait mode or stop mode, depending on a combination of instruction and an execution timing. 3. In the main clock oscillation or low power dissipation mode, set the CM02 bit of the CM0 register to "0" (do not stop peripheral function clock in wait mode). 4. Wait until the t d(M-L) elapses or main clock oscillation stabilization time, whichever is longer, be- fore switching the clock source for CPU clock to the main clock. Similarly, wait until the sub clock oscillates stably before switching the clock source for CPU clock to the sub clock. 5. Suggestions to reduce power consumption

• Ports The processor retains the state of each I/O port even when it goes to wait mode or to stop mode. A current flows in active I/O ports. A pass current flows in input ports that high-imped- ance state. When entering wait mode or stop mode, set non-used ports to input and stabilize the potential.
• A/D converter When A/D conversion is not performed, set the VCUT bit of the ADCON1 register to "0" (V REF not connection). When A/D conversion is performed, start the A/D conversion at least 1 µs or longer after setting the VCUT bit to "1" (VREF connection).
• D/A converter When not performing D/A conversion, set the DAE bit of the DACON register to "0" (input inhibited) and DA register to "00 16".
• Switching the oscillation-driving capacity Set the driving capacity to "LOW" when oscillation is stable.
• External clock When using an external clock input for the CPU clock, set the CM05 bit of the CM0 register to "1" (stop). Setting the CM05 bit to "1" disables the X OUT pin from functioning, which helps to reduce the amount of current drawn in the chip. (When using an external clock input, note that the clock remains fed into the chip regardless of how the CM05 bit is set.)

Rev.1.00 Oct 20, 2004 page 205 of 222 M16C/1N Group REJ090007-0100Z 20. Precautionary Notes in Using the Device Example 1. When an interrupt is used to cancel wait mode When canceling wait mode by a hardware reset and an INT0 interrupt. Set the interrupt enable flag (I flag) to "0" Change the INT0 interrupt priority level to 1 or higher Change all other interrupt priority level to 0 Insert 4 NOPs instructions Set the interrupt enable flag (I flag) to "1" WAIT instruction Insert 4 NOPs instructions ; Disable interrupt ; Enable INT0 interrupt In case of processor interrupt priority level = 0 ; Disable all other interrupts ; Prevent irregular interrupt occurring ; Enable interrupts Example 2. When only hardware reset is used to cancel wait mode Set the interrupt enable flag (I flag) to "0" Change all interrupt priority level to 0 WAIT instruction Insert 4 NOPs instructions ; Disable interrupt ; Disable maskable interrupt ; Put at least 4 NOPs after a wait instruction because when switching to a wait mode, 4 instructions are prefetched after the wait instruction. ; Put at least 4 NOPs after a wait instruction because when switching to a wait mode, 4 instructions are prefetched after the wait instruction.

20.1.3 Stop and Wait Modes

When returning from a stop mode by hardware reset, RESET pin must be "L" level until the main- clock has stabilized. 2. When switching to a stop or wait mode, 4 instructions are prefetched after the stop or wait instruc- tion. And so, ensure that at least 4 NOPs follow the stop (the all-clock stop bit to "1") or wait instruction. 3. A Stop or wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel a stop or wait mode, that interrupt must first have been enabled, and the priority level of the interrupt which is not used to cancel must have been changed to 0 before shifting to either mode. If only a hardware reset is used to cancel a stop or wait mode, change the priority level of all interrupt to 0, then shift to either mode.

Rev.1.00 Oct 20, 2004 page 206 of 222 M16C/1N Group REJ090007-0100Z 20. Precautionary Notes in Using the Device 4. After returning from stop mode, an unexpected operation may occur (for example, undefined in- struction interrupt, BRK instruction interrupt, etc.). Execute a JMP.B instruction after an instruction to write data to the all clock stop control bit. A program example is described as follows: Code examples are shown below. Example 1: BSET 0, CM1 ; writing to the all clock stop control bit to "1" (stop mode) JMP.B L1 L1: NOP NOP NOP NOP Example 2: MOV.B:S #21h, CM1 ; writing to the all clock stop control bit to "1" (stop mode) JMP.B L1 L1: NOP NOP NOP NOP

Rev.1.00 Oct 20, 2004 page 207 of 222 M16C/1N Group REJ090007-0100Z 20. Precautionary Notes in Using the Device

20.2 Interrupts

20.2.1 Reading Address 0000016

Do not read the address 00000 16 in a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from the address 00000 16 during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to "0". If the address 0000016 is read in a program, the IR bit for the interrupt which has the highest priority among the enabled interrupts is cleared to "0". This causes a problem that the interrupt is canceled, or an unexpected interrupt is generated.

20.2.2 Stack Pointer

Set the value of the stack pointer before accepting interrupts. Immediately after a reset, the value of the stack pointer is 0000 16. Accepting an interrupt before setting a value of the stack pointer may produce unpredictable results (runaway program, etc.) Make sure that you set the value of the stack pointer before accepting interrupts.

20.2.3 External interrupts

Clear the interrupt request bit to "0" when the INT 0 to INT 3 pins and CNTR 0 pin polarity are changed. The reason being is that an interrupt request may be generated when the polarity is changed.

20.2.4 Rewriting the Interrupt Control Register

When rewriting the Interrupt Control Register, do it at a point where it does not generate an inter- rupt request for that register. If there is a possibility that an interrupt may occur, disable the inter- rupt before rewriting. Examples are shown below. Example 1: INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00H, 0055H ; Clear T1IC int. priority level and int. request bit. NOP ; NOP FSET I ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00H, 0055H ; Clear T1IC int. priority level and int. request bit. MOV.W MEM, R0 ; Dummy read. FSET I ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG ; Push Flag register onto stack FCLR I ; Disable interrupts. AND.B #00H, 0055H ; Clear T1IC int. priority level and int. request bit. POPC FLG ; Enable interrupts. Note 1: The reason why two NOP instructions or dummy read were inserted before the FSET I for ex. 1 & 2 is to prevent interrupt enable flag from being set, due to the effects of instruction queue, before the rewritten value of the interrupt control register takes effect.

Rev.1.00 Oct 20, 2004 page 208 of 222 M16C/1N Group REJ090007-0100Z 20. Precautionary Notes in Using the Device When an instruction to rewrite the interrupt control register is executed while the interrupt is dis- abled, depending on the instruction used for rewriting, there are times the interrupt request bit is not set even if an interrupt request for that register has been generated. If this creates a problem, please use any of the instructions below to rewrite the register. Instructions : AND, OR, BCLR, BSET

20.2.5 Changing the interrupt request bit

When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit is not cleared sometimes. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : MOV

Rev.1.00 Oct 20, 2004 page 209 of 222 M16C/1N Group REJ090007-0100Z 20. Precautionary Notes in Using the Device

20.3 Timer

20.3.1 Timer 1

1. Even if the prescaler 1 and Timer 1 are read out simultaneously in word-size, these registers are read byte-by-byte in the microcomputer. Consequently, the timer value may be updated during the period these two registers are being read.

20.3.2 Timers X, Y and Z

1. These timers stop counting after reset. Therefore, set values to Timer (X, Y, Z) and prescaler (X, Y, Z) before starting counting. 2. Even if prescaler (X, Y, Z) and Timer (X, Y, Z) are read out simultaneously in word-size, these registers are read byte-by-byte in the microcomputer. Consequently, the timer value may be up- dated during the period these two registers are being read.

20.3.3 Timer X

1. Using in the timer X pulse period measurement mode, the effectual edge reception flag and the timer X under flow flag are set to "0" by writing a "0" in a program. Writing a "1" has no effect. Write "1" in the other flag by using the MOV instruction when you make the flag of either one side "0" by program. (The clearance of the flag which isn't intend can be prevented.) Example: MOV.B #10XXXXXXB,008BH 2. When changing to the timer X pulse period measurement mode from other mode, the contents of the effectual edge reception flag and the timer X under flow flag are indetermind. Write "0" in the effectual edge reception flag and the timer X under flow flag before starting the timer. 3. In the timer X pulse period measurement mode, use the MOV instruction to stop the timer. Example: MOV.B #1100X00B,008BH

20.3.4 Timer Y

1. When count is stopped by writing "0" to the timer Y count start flag, the timer reloads the value of reload register and stops. Therefore, the timer count value should be read out before the timer stops. 2. When count is stopped by writing "0" to the timer Y count start flag, the timer Y interrupt request bit becomes "1" and an interrupt may occur. Thus, disable interrupts before the timer stops. Further- more, set the Timer Y interrupt request bit to "0" before starting counting again.

Rev.1.00 Oct 20, 2004 page 210 of 222 M16C/1N Group REJ090007-0100Z 20. Precautionary Notes in Using the Device

20.3.5 Timer Z

1. When count is stopped by writing "0" to the timer Z count start flag, the timer reloads the value of reload register and stops. Therefore, the timer count value should be read out before the timer stops. 2. When count is stopped by writing "0" to the timer Z count start flag (all modes) or by writing "0" to the one-shot start bit (programmable one-shot generation mode/programmable wait one-shot gen- eration mode), the timer Z interrupt request flag becomes "1" and an interrupt occurs. Thus, disable interrupts before the timer stops. Furthermore, set the Timer Z interrupt request bit to "0" before starting counting again.

20.3.6 Timer C

1. Read out the timer C or timer measurement register using in word-size. Even if the Timer C is read out in word-size, the timer value is not updated during the period the high-byte and low-byte are being read. Example: MOV.W 0091H,R0 ;Read out timer C

Rev.1.00 Oct 20, 2004 page 211 of 222 M16C/1N Group REJ090007-0100Z 20. Precautionary Notes in Using the Device

20.4 Serial I/O

1. When reading data from the UARTi receive buffer in the clock asynchronous serial I/O mode, data should be read high-byte first then low-byte using a byte-size. If data is read as low-byte then high- byte or in word-size the framing error and parity error flags are cleared. A code example is shown below. MOV.B 00A7H. R0H ; Read the high-byte of UART0 receive buffer register MOV.B 00A6H. R0L ; Read the low-byte of UART0 receive buffer register 2. When writing data to the UARTi transmit buffer register in the clock asynchronous serial I/O mode with 9-bit transfer data length, data should be written high-byte first then low-byte using a byte-size. A code example is shown below. MOV.B #XXH, 00A3H ; Write the high-byte of UART0 transmit buffer register MOV.B #XXH, 00A2H ; Write the low-byte of UART0 transmit buffer register

Rev.1.00 Oct 20, 2004 page 212 of 222 M16C/1N Group REJ090007-0100Z 20. Precautionary Notes in Using the Device

20.5 A/D Converter

1. Only write to each bit (except bit 6) of the AD Control Register 0, or each bit of the AD Control Register 1, or bit 0 of the AD Control Register 2 when AD conversion is stopped (before a trigger occurs). When the V REF connection bit is changed from "0" to "1", wait 1 µs or longer before starting AD conversion. 2. To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert capacitors between the VCC, VREF, and analog input pins (ANi) each and the VSS pin. Figure 20.1 shows an example connection of each pin. 3. Make sure the port direction bits for those pins that are used as analog inputs are set to "0" (input mode). ____ When setting the KIi input enable bit to "1" (Enabled) to use key input interrupt and using AN 8 to AN11 as analog input pins, be careful about the following points.

• A key input interrupt request is generated when the A/D input voltage goes "LOW".
• If the A/D input voltage approaches 1/2 V CC, power supply current may increase due to pass ____ current on schmitt circuit of key input interrupt. (When setting the KIi input enable bit to "0" (Disabled), pass current doesn't flow.) 5. The Ø AD frequency must be 10 MHz or less. Without sample-and-hold function, limit the Ø AD frequency to 250 kHz or more. With the sample and hold function, limit the ØAD frequency to 1 MHz or more. Figure 20.1 Example connection of each pin Note 1: C1≥0.47µF, C2≥0.47µF, C3≥100pF (reference). Note 2: Use thick and shortest possible wiring to connect capacitors. Microcomputer VREF VCC C1 C2 VSS ANi

Rev.1.00 Oct 20, 2004 page 213 of 222 M16C/1N Group REJ090007-0100Z 20. Precautionary Notes in Using the Device 6. When changing AD operation mode, select an analog pin again. 7. One Shot Mode Read the AD register only after confirming AD conversion is completed, which can be determined by using the AD conversion interrupt. 8. Repeat Mode Use the undivided main clock as the internal CPU clock when using this mode. The main clock can be divided by an internal divider circuit but make sure that you use main clock when using this mode. 9. If A/D conversion is forcibly terminated while in progress by setting the ADST bit of ADCON0 register to "0" (A/D conversion halted), the conversion result of the A/D converter is indeterminate. If the ADST bit is cleared to "0" in a program, ignore the value of A/D register.

Rev.1.00 Oct 20, 2004 page 214 of 222 M16C/1N Group REJ090007-0100Z 20. Precautionary Notes in Using the Device

20.6 CAN Module

20.6.1 Reading C0STR Register

The CAN module on the M16C/1N group updates the status of the C0STR register in a certain period. When the CPU and the CAN module access to the C0STR register at the same time, the CPU has the access priority; the access from the CAN module is disabled. Consequently, when the updating period of the CAN module matches the access period from the CPU, the status of the CAN module cannot be updated. (See Figure 20.2) Accordingly, be careful about the following points so that the access period from the CPU should not match the updating period of the CAN module: 1. There should be a wait time of 3f CAN or longer (see Table 20.1) before the CPU reads the C0STR register. (See Figure 20.3) 2. When the CPU polls the C0STR register, the polling period must be 3f CAN or longer. (See Figure 20.4) Table 20.1 CAN Module Status Updating Period 3fCAN period = 3 X XIN (Original oscillation period) X Division value of the CAN clock (CCLK) (Example 1) Condition XIN 16MHz CCLK: Divided by 1 3f CAN period = 3 X 62.5 ns X 1= 187.5 ns (Example 2) Condition XIN 16MHz CCLK: Divided by 2 3f CAN period = 3 X 62.5 ns X 2= 375 ns (Example 3) Condition XIN 16MHz CCLK: Divided by 4 3f CAN period = 3 X 62.5 ns X 4= 750 ns (Example 4) Condition XIN 16MHz CCLK: Divided by 8 3f CAN period = 3 X 62.5 ns X 8= 1.5 µs (Example 5) Condition XIN 16MHz CCLK: Divided by 16 3f CAN period = 3 X 62.5 ns X 16= 3 µs

Rev.1.00 Oct 20, 2004 page 216 of 222 M16C/1N Group REJ090007-0100Z 20. Precautionary Notes in Using the Device Figure 20.5 CAN Transceiver Connection In case of PCA82C250 (Philips product) Standby mode high-speed mode "H" "L" impossible possible Rs pin (Note 1) CAN communication connection M16C/1N PCA82C250 Switch OFF CTX P02 Port (Note 2) CANHTXD RS CRX P03 CANLRXD M16C/1N PCA82C250 Switch ON CTX P02 Port (Note 2) CANHTXD RS CRX P03 CANLRXD In case of PCA82C252 (Philips product) sleep mode normal operation mode "L" "L" "H" "H" impossible possible STB pin (Note 1) EN pin (Note 1) CAN communication connection MCU PCA82C252 Switch OFF CTX P02 Port (Note 2) CANHTXD STB CRX P03 CANLRXD MCU PCA82C252 Switch ON CTX P02 Port (Note 2) CANHTXD Port (Note 2) Port (Note 2) EN CRX P03 CANLRXD STB EN Note 1: The pin which controls the operation mode of CAN transceiver. Note 2: Connect to enabled port to control CAN transceiver.

20.6.2 CAN Transceiver in Boot Mode

When programming the flash memory in boot mode via CAN bus, the operation mode of CAN transceiver should be set to "high-speed mode" or "normal operation mode". If the operation mode is controlled by the microcomputer, CAN transceiver must be set the operation mode to "high- speed mode" or "normal operation mode" before programming the flash memory by changing the switch etc. Figure 20.5 shows pin connections of CAN transceiver.

Rev.1.00 Oct 20, 2004 page 217 of 222 M16C/1N Group REJ090007-0100Z 20. Precautionary Notes in Using the Device

20.7 Noise

1. Bypass Capacitor between V CC and VSS Pins Insert a bypass capacitor (at least 0.1 µF) between V CC and VSS pins as noise and latch-up countermeasures. In addition, make sure that connecting lines are the shortest and widest pos- sible. 2. Port Control Registers Data Read Error During severe noise testing, mainly power supply system noise, and introduction of external noise, the data of port related registers may changed. As a firmware countermeasure, it is recommended to periodically re-set the port registers, port direction registers and pull-up control registers. How- ever, you should fully examine before introducing the re-set routine as conflicts may be created between this re-set routine and interrupt routines (i. e. ports are switched during interrupts). 3. CNVss pin wiring CNV SS pin functions as a pin to change to shipment examination mode or flash memory rewrite mode in the flash memory version. In order to improve the pin tolerance to noise, insert a pull down resistance (about 5 kΩ) between CNVss and Vss, and placed as close as possible to the CNVss pin.

Rev.1.00 Oct 20, 2004 page 218 of 222 M16C/1N Group REJ090007-0100Z 20. Precautionary Notes in Using the Device

20.8 Electrical Characteristic Differences Between Mask ROM and Flash Memory Ver-

Flash memory version and mask ROM version may have different characteristics, operating margin, noise tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern, etc. When switching to the mask ROM version, conduct equivalent tests as system evaluation tests conducted in the flash memory version.

Rev.1.00 Oct 20, 2004 page 219 of 222 M16C/1N Group REJ090007-0100Z 20. Precautionary Notes in Using the Device

20.9 Flash Memory Version

20.9.1 Functions to Prevent Flash Memory from Rewriting

ID codes are stored in addresses 0FFFDF 16, 0FFFE3 16, 0FFFEB 16, 0FFFEF 16, 0FFFF3 16, 0FFFF716, and 0FFFFB16. If wrong data are written to these addresses, the flash memory cannot be read or written in standard serial I/O mode and CAN I/O mode. The ROMCP register is mapped in address 0FFFFF 16. If wrong data is written to this address, the flash memory cannot be read or written in parallel I/O mode. In the flash memory version of microcomputer, these addresses are allocated to the vector ad- dresses (H) of fixed vectors.

20.9.2 Stop Mode

When entering stop mode, the following settings are required:

• Set the CM10 bit to "1" (stop mode) after setting FMR01 bit to "0" (CPU rewrite mode disable).
• Execute the instruction to set the CM10 bit to "1" (stop mode) and then the JMP.B instruction. Example program BSET 0, CM1 ; Stop mode JMP.B L1 L1: Program after exiting from stop mode

20.9.3 Wait Mode

When entering wait mode, set the FMR01 bit in the FMR0 register to "0" (CPU rewrite mode dis- abled) before executing the WAIT instruction.

20.9.4 Low Power Dissipation Mode and On-Chip Oscillator Low Power Dissipation Mode

If the CM05 bit is set to "1" (main clock stopped), do not execute the following commands:

• Program
• Block erase
• Erase all unlocked blocks
• Lock bit program

20.9.5 Writing Command and Data

Write commands and data to even addresses in the user ROM area.

20.9.6 Program Command

By writing "xx40 16" in the first bus cycle and data to the write address in the second bus cycle, an auto program operation (data program and verify) will start. The address value specified in the first bus cycle must be the same even address as the write address specified in the second bus cycle.

20.9.7 Operation Speed

Set the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register to clock frequency of 10 MHz or less before entering CPU rewrite mode (EW0 or EW1 mode). Also, set the PM17 bit in the PM1 register to "1" (with wait state).

Rev.1.00 Oct 20, 2004 page 220 of 222 M16C/1N Group REJ090007-0100Z 20. Precautionary Notes in Using the Device

20.9.8 Prohibited Instructions

The following instructions cannot be used in EW0 mode because the CPU tries to read data in flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction

20.9.9 Interrupt

To use interrupts having vectors in a relocatable vector table, the vectors must be relocated to the RAM area.

• The watchdog timer interrupt is available since the FMR0 and FMR1 registers are forcibly reset when either interrupt request is generated. Allocate the jump addresses for each interrupt ser- vice routines to the fixed vector table. Flash memory rewrite operation is aborted when the watchdog timer interrupt request is generated. Execute the rewrite program again after exiting the interrupt routine.
• The address match interrupt is not available since the CPU tries to read data in the flash memory. EW1 Mode
• Do not acknowledge any interrupts with vectors in the relocatable vector table or address match interrupt during the auto program or auto erase period.
• Do not use the watchdog timer interrupt.

20.9.10 How to Access

To set the FMR01, FMR02 or FMR11 bit to "1", write "1" after first setting the bit to "0". Do not generate an interrupt between the instruction to set the bit to "0" and the instruction to set the bit to "1".

20.9.11 Rewriting in User ROM Area

The supply voltage drops while rewriting the block where the rewrite control program is stored, the flash memory cannot be rewritten because the rewrite control program is not correctly rewrit- ten. If this error occurs, rewrite the user ROM area while in standard serial I/O mode, parallel I/ O mode, or CAN I/O mode. EW1 Mode Avoid rewriting any block in which the rewrite control program is stored.

Rev.1.00 Oct 20, 2004 page 221 of 222 M16C/1N Group Package Dimension REJ090007-0100Z Package Dimension LQFP48-P-77-0.50 – Weight(g) JEDEC CodeEIAJ Package Code Lead Material Cu Alloy 48P6Q-A Plastic 48pin 7✕7mm body LQFP 0.1 0.2 Symbol Min Nom Max A b c D E HE L y Dimension in Millimeters HD 0.225 ––I2 1.0 ––MD 7.4 ––ME 7.4 8°0° 0.1 1.0 0.650.50.35 9.29.08.8 9.29.08.8 0.5 7.17.06.9 7.17.06.9 0.1750.1250.105 0.270.220.17 1.4 1.7 e e E HE 48 37 HD D MD ME A F y Recommended Mount Pad A1 A2 L Detail F Lp c Lp 0.45 0.6 0.25 0.75 0.08x A3 e b x M Recommended

Rev.1.00 Oct 20, 2004 page 222 of 222 M16C/1N Group Register Index REJ090007-0100Z Register Index A C CAN0/1 SLOT 0 to 15 D F I K P R S T U W

REVISION HISTORY

Rev. Date Description Page Summary M16C/1N Group Hardware Manual

1.00 Oct 20, 2004 – First edition issued (Renesas Technology version)

M16C/1N Group Hardware Manual Publication Data : Rev.1.00 Oct 20, 2004 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.

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