M3004316045NX0ITAY

M3004316 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: Suhail Zain
• PDF pages: 26

Technical content

Features

• Interface  Parallel Asynchronous x16
• Technology  40nm pMTJ STT-MRAM
• Data Retention (see Table 16. Endurance and Data Retention Density)  4Mb, 8Mb, 16Mb, 32Mb
• Operating Voltage Range  VCC: 2.70V – 3.60V
• Operating Temperature Range  Industrial: -40°C to 85°C  Industrial Plus: -40°C to 105°C
• RoHS Compliant & REACH Compliant
• Packages  44-pin TSOP (10mm x 18mm)  54-pin TSOP (10mm x 22mm)  48-ball FBGA (10mm x 10mm)
• Memory Array Organization  4Mbit  262,144 x 16  8Mbit  524,288 x 16  16Mbit  1,048,576 x 16  32Mbit  2,097,152 x 16 Block Diagram Command Control ADDR[20:0] MRAM Array Row Decoder Column Decoder SenseAmps Address Control I/O Control DQ[15:0] UB# LB#

/M3016316/M3032316 Sep.3.21 Page 2

Contents

/M3016316/M3032316 Sep.3.21 Page 3 Performance Device Operation Typical Values Units Read Cycle Time 35.0 (minimum) ns Write Cycle Time 35.0 (minimum) ns Standby Current 1.7 (typical)* mA Read Current 12.0 (typical) mA Write Current 20.0 (typical) mA *Number shown is for 16Mb device

/M3016316/M3032316 Sep.3.21 Page 4 General Description M3xxx316 is a magneto- resistive random -access memory (MRAM). It is offered in density ranging from 4Mbit to 32 Mbit. MRAM technology is analogous to Flash technology with SRAM compatible 35ns/35ns and 45ns/45ns read/write timings (Persistent SRAM, P -SRAM). Data i s always non- volatile. This makes MRAM a very reliable and fast non-volatile memory solution. Table 1: Technology Comparison SRAM Flash EEPROM MRAM Non-Volatility − √ √ √ Write Performance √ − − √ Read Performance √ − − √ Endurance √ − − √ Power − − − √ MRAM is a true random -access memory; allowing both reads and writes to occur randomly in memory. MRAM is ideal for applications that must store and retrieve data without incurring large latency penalties. It offers low latency, low power, infinite endurance, high performance and scalable memory technology. M3xxx316 is available in small footprint 54-pin TSOP (10mm x 22mm) and 48-Ball FBGA (10mm x 10mm) packages supporting densities ranging from 4Mb to 16 Mb. The 48-Ball FBGA also supports the 32Mb. Density of 4Mb is also available in a small footprint 44-pin TSOP (10mm x 18mm). These packages are compatible with similar low-power volatile and non-volatile products. M3xxx316 is offered with industrial ( -40°C to 85°C) and industrial plus (-40°C to 105°C) operating temperature ranges.

/M3016316/M3032316 Sep.3.21 Page 5 Ordering Options The ordering part numbers are formed by a valid combination of the following options: Figure 1: Part Number Ordering System 008 3 16 035N X BC Y Packing Type R: Tape & Reel Y: Tray Temperature Range 0I: -40°C to +85°C 0P: -40°C to +105°C Package Type BC: 48-ball FBGA (up to 32Mb) TA: 44-TSOP (4Mb) TB: 54-TSOP (up to 16Mb) Performance 035N: 35ns Access Time 045N: 45ns Access Time Interface Type 3: Parallel Asynchronous Interface Density 004: 4 Megabit 008: 8 Megabit 016: 16 Megabit 032: 32 Megabit Operational Voltage 3: 3.0V (2.70V to 3.60V) Brand - Product Family M: Renesas - Parallel MRAM M 3 0I Sub-Interface Type 16: x16 Reserved

/M3016316/M3032316 Sep.3.21 Page 6 Valid Combinations — Standard Valid Combinations list includes device configurations currently available. Contact your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. Table 2: Valid Combinations List Valid Combinations – 35ns Base Part Number Temperature Range Package Type Packing Type Part Number M3004316035NX 0I, 0P BC, TA, TB R, Y M3004316035NX0IBCR M3004316035NX0IBCY M3004316035NX0ITAR M3004316035NX0ITAY M3004316035NX0ITBR M3004316035NX0ITBY M3004316035NX0PBCR M3004316035NX0PBCY M3004316035NX0PTAR M3004316035NX0PTAY M3004316035NX0PTBR M3004316035NX0PTBY M3008316035NX 0I, 0P BC, TB R, Y M3008316035NX0IBCR M3008316035NX0IBCY M3008316035NX0ITBR M3008316035NX0ITBY M3008316035NX0PBCR M3008316035NX0PBCY M3008316035NX0PTBR M3008316035NX0PTBY M3016316035NX 0I, 0P BC, TB R, Y M3016316035NX0IBCR M3016316035NX0IBCY M3016316035NX0ITBR M3016316035NX0ITBY M3016316035NX0PBCR M3016316035NX0PBCY M3016316035NX0PTBR M3016316035NX0PTBY M3032316035NX 0I, 0P BC R, Y M3032316035NX0IBCR M3032316035NX0IBCY M3032316035NX0PBCR M3032316035NX0PBCY

/M3016316/M3032316 Sep.3.21 Page 7 Valid Combinations – 45ns Base Part Number Temperature Range Package Type Packing Type Part Number M3004316045NX 0I, 0P BC, TA, TB R, Y M3004316045NX0IBCR M3004316045NX0IBCY M3004316045NX0ITAR M3004316045NX0ITAY M3004316045NX0ITBR M3004316045NX0ITBY M3004316045NX0PBCR M3004316045NX0PBCY M3004316045NX0PTAR M3004316045NX0PTAY M3004316045NX0PTBR M3004316045NX0PTBY M3008316045NX 0I, 0P BC, TB R, Y M3008316045NX0IBCR M3008316045NX0IBCY M3008316045NX0ITBR M3008316045NX0ITBY M3008316045NX0PBCR M3008316045NX0PBCY M3008316045NX0PTBR M3008316045NX0PTBY M3016316045NX 0I, 0P BC, TB R, Y M3016316045NX0IBCR M3016316045NX0IBCY M3016316045NX0ITBR M3016316045NX0ITBY M3016316045NX0PBCR M3016316045NX0PBCY M3016316045NX0PTBR M3016316045NX0PTBY M3032316045NX 0I, 0P BC R, Y M3032316045NX0IBCR M3032316045NX0IBCY M3032316045NX0PBCR M3032316045NX0PBCY

/M3016316/M3032316 Sep.3.21 Page 8 Signal Description and Assignment Figure 2: Device Pinout Renesas MRAM 4Mbit – 32Mbit ADDR[20:0] DQ[15:0] LB# UB# Table 3: Signal Description Signal Type Description E# Input Chip enable: Enables or disables the MRAM. G# Input Output enable: Enables the output drivers in bidirectional data transfer I/Os. W# Input Write enable: Transfers serial data from the host system to the MRAM when Low (Logic ‘0’).Transfers serial data from the MRAM to the host system when High (Logic ‘1’). UB# Input Upper Byte Enable: Enables or disables DQ[15:8]. LB# Input Lower Byte Enable: Enables or disables DQ[7:0]. ADDR[20:0] Input Address: I/Os for address transfer. 04M: ADDR[17:0] – 18 Address pins for 04M devices. 08M: ADDR[18:0] – 19 Address pins for 08M devices. 16M: ADDR[19:0] – 20 Address pins for 16M devices. 32M: ADDR[20:0] – 21 Address pins for 32M devices. DQ[15:0] Input / Output Data inputs/outputs: The bidirectional I/Os transfer data. VCC Supply VCC: Core and I/O power supply. VSS Supply VSS: Core and I/O ground supply. NC No connect: NCs are not internally connected. They can be driven or left unconnected. DNU Do not use: DNUs must be left unconnected.

/M3016316/M3032316 Sep.3.21 Page 9 Package Options 44-Pin TSOP (4Mb) (Top View) 44-Pin TSOP Package (x16) text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text ADDR[4] DQ[0] ADDR[5] ADDR[6] ADDR[7] ADDR[8] ADDR[10] ADDR[11] ADDR[12] ADDR[13] ADDR[15] ADDR[16] VSS DQ[4] VSS VCC ADDR[0] ADDR[1] ADDR[2] ADDR[3] DQ[1] VCC ADDR[9] DQ[5] DQ[10] DQ[9] DQ[8] ADDR[14] NC ADDR[17] DQ[2] DQ[3] DQ[6] DQ[7] DQ[11] DQ[14] DQ[15] DQ[12] DQ[13] UB# LB# 54-Pin TSOP (4-16Mb) (Top View) 54-Pin TSOP Package (x16) text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text text ADDR[4] DQ[0] DQ[6] DQ[7] ADDR[5] ADDR[11] ADDR[13] DNU DQ[9] VCC VSS DQ[12] DNU ADDR[19] ADDR[0] ADDR[1] ADDR[2] ADDR[3] DQ[1] DQ[2] ADDR[6] ADDR[7] DQ[4] DQ[5] ADDR[8] ADDR[9] ADDR[10] ADDR[12] ADDR[14] DQ[8] DQ[10] DQ[15] UB# ADDR[15] ADDR[17] LB# ADDR[16] ADDR[18] VSS VCC DQ[11] DQ[14] DQ[13] text text text DNU DNU DNU text text text NC DNU DNU 15 40 DQ[3] *VSS Note:*VSS pin 1 must be held low, < VIL for the part to function properly.

/M3016316/M3032316 Sep.3.21 Page 10 48-Ball FBGA (4-32Mb) (Balls Down, Top View) 1 2 3 4 5 6 ABCDEFGH DQ1 DQ2 A17 DQ3 VCC A16 DQ4 VSS A14 A15 DQ5 DQ6 A12 A13 DQ7 A10 A11 A19 VCC Power VSS Ground E# Control Signal DQ Data Input / Output Signals DQ0 DQ9 DQ10 VSS DQ11 VCC DQ12 DQ14 DQ13 DQ15 A18 DQ8 UB# LB# A Address Signals NC A20 DNU NC No Connect DNU Do Not Use

/M3016316/M3032316 Sep.3.21 Page 11 Package Drawings 44-Pin TSOP

/M3016316/M3032316 Sep.3.21 Page 12 54-Pin TSOP

/M3016316/M3032316 Sep.3.21 Page 13 48-Ball FBGA

/M3016316/M3032316 Sep.3.21 Page 14 Architecture M3xxx316 is a high performance MRAM device. Writing to and reading from the device as follows: To write to the device, bring Chip Enable (E#) and Write Enable (W#) inputs Low (Logic ‘0’). This enables data on I/O pins ( DQ[0] to DQ[15] ) to be written into the memory location specified by the address pins ADDR[0] through A DDR[20] (48-ball FBGA ), ADDR[0] through ADDR[19] (54- pin TSOP ) and ADDR[0] through ADDR[17] (44-pin TSOP). To read from the device, bring Chip Enable (E#) input Low (Logic ‘0’), Output Enable (G#) input Low (Logic ‘0’) while maintaining Write Enable ( W#) High (Logic ‘1’). This enables data from the memory location specified by the address pins ADDR[0] through ADDR[20] (48-ball FBGA), ADDR[0] through ADDR[19] (54- pin TSOP) and ADDR[0] through ADDR[17] (44-pin TSOP) to appear on I/O pins (DQ[0] to DQ[15]). Figure 3: Functional Block Diagram Command Control ADDR[20:0] MRAM Array Row Decoder Column Decoder SenseAmps Address Control I/O Control DQ[15:0] UB# LB# Table 4: Modes of Operation Mode E# G# W# UB# LB# Current DQ[15:8] DQ[7:0] Not Selected H X X X X ISB Hi-Z Hi-Z Output Disabled L H H X X IREAD Hi-Z Hi-Z Output Disabled L X X H H IREAD Hi-Z Hi-Z Read Upper Byte L L H L H IREAD Dataout Hi-Z Read Lower Byte L L H H L IREAD Hi-Z Dataout Read Word L L H L L IREAD Dataout Dataout Write Upper Byte L X L L H IWRITE Datain Hi-Z Write Lower Byte L X L H L IWRITE Hi-Z Datain Write Word L X L L L IWRITE Datain Datain Notes: H: High (Logic ‘1’) X: Don’t Care L: Low (Logic ‘0’) Hi-Z: High Impedance

/M3016316/M3032316 Sep.3.21 Page 16 Table 5: Device Initialization Timing – 3.0V Parameter Symbol Test Conditions 3.0V Minimum Typical Maximum Units VCC Range All operating voltages and temperatures 2.7 - 3.6 V VCC Power Up to First Instruction tPU All operating voltages and temperatures 1 - - ms

/M3016316/M3032316 Sep.3.21 Page 17 Electrical Specifications Table 6: Recommended Operating Conditions Parameter / Condition Minimum Typical Maximum Units Industrial -40.0 - 85.0 °C Industrial Plus -40.0 - 105.0 °C VCC Supply Voltage 3.0V 2.7 3.0 3.6 V VSS Supply Voltage 0.0 0.0 0.0 V Vwi Write Inhibit Voltage 2.1 2.3 2.5 V Table 7: Pin Capacitance Parameter Symbol Test Conditions Density Maximum Units Input Pin Capacitance CIN TEMP = 25°C; f = 1 MHz; VIN = 0V 4Mb - 16Mb 10.0 pF 32b 20.0 Input / Output Pin Capacitance CINOUT TEMP = 25°C; f = 1 MHz; VIN = 0V 4Mb - 16Mb 10.0 pF 32Mb 20.0 Table 8: DC Characteristics Parameter Symbol Test Conditions 3.0V Device (2.7V-3.6V) Minimum Typical Maximum Units Read Current IREAD VCC (max), IOUT=0mA 4Mb – 32Mb - 12.0 30.0 mA Write Current IWRITE VCC (max) 4Mb – 32Mb - 20.0 30.0 mA Standby Current Industrial (-40°C to 85°C) ISB E#=VIH, VCC (max) 4Mb-16Mb 1.5 2.5 mA 32Mb 3.0 5.0 Standby Current Industrial Extended (-40°C to 105°C) ISB E#=VIH, VCC (max) 4Mb-16Mb 1.7 3.5 mA 32Mb 3.4 7.0 Input Leakage Current ILI VIN=0 to VCC (max) - - ±1.0 µA Output Leakage Current ILO VOUT=0 to VCC (max) - - ±1.0 µA Input High Voltage VIH 0.8xVCC - VCC+0.3 V Input Low Voltage VIL -0.5 - 0.2xVCC V Output High Voltage Level VOH IOH = -1.6mA VCC-0.5 - - V Output Low Voltage Level VOL IOL = 1.6mA - - 0.4 V

/M3016316/M3032316 Sep.3.21 Page 18 Table 9: Magnetic Immunity Characteristics Parameter Symbol Maximum Units Magnetic Field During Write Hmax_write 24000 A/m Magnetic Field During Read Hmax_read 24000 A/m Table 10: AC Test Conditions Parameter Value Input pulse levels 0.0V to VCC Input rise and fall times 5ns Input and output measurement timing levels VCC/2 Output Load CL = 30pF

/M3016316/M3032316 Sep.3.21 Page 19 Write Operation Figure 6: Write Operation (W# Controlled) ADDR[20:0] DQ[15:0] Don’t Care New Address New Address Data tAVWH tWLEH tWLWH tAVWL tDVWH tWHD X tWHAX UB#, LB# Table 11: Write Operation (W# Controlled) Parameter Symbol Minimum Maximum Units 35ns 45ns Write Cycle Time tAVAV 35 45 - ns Address Set-Up Time tAVWL 0 - ns Address Valid to end of Write (G# High) tAVWH 18 28 - ns Address Valid to end of Write (G# Low) tAVWH 20 30 - ns Write Pulse Width (G# High) tWLWH, tWLEH 15 25 - ns Write Pulse Width (G# Low) tWLWH, tWLEH 15 25 - ns Data Valid to end of Write tDVWH 10 15 - ns Data Hold Time tWHDX 0 - ns Write recovery Time tWHAX 12 - ns Notes: G# is High (Logic ‘1’) for Write operation Power supplies must be stable Addresses valid either before or at the same time as E# goes low

/M3016316/M3032316 Sep.3.21 Page 20 Figure 7: Write Operation (E# Controlled) ADDR[20:0] DQ[15:0] Don’t Care New Address New Address Data tAVEH tELWH tELE H tAVEL tDVE H tEH DX tEH AX UB#, LB# Table 12: Write Operation (E# Controlled) Parameter Symbol Minimum Maximum Units 35ns 45ns Write Cycle Time tAVAV 35 45 - ns Address Set-Up Time tAVEL 0 - ns Address Valid to end of Write (G# High) tAVEH 18 28 - ns Address Valid to end of Write (G# Low) tAVEH 20 30 - ns Write Pulse Width (G# High) tELWH, tELEH 15 25 - ns Write Pulse Width (G# Low) tELWH, tELEH 15 25 - ns Data Valid to end of Write tDVEH 10 15 - ns Data Hold Time tEHDX 0 - ns Write recovery Time tEHAX 12 - ns Notes: G# is High (Logic ‘1’) for Write operation Power supplies must be stable Addresses valid either before or at the same time as W# goes low

/M3016316/M3032316 Sep.3.21 Page 21 Bus Turnaround Operation – Read to Write Figure 8: Bus Turnaround Operation ADDR[20:0] DQ[15:0] - Datain Don’t Care New Address New Address Data tAVWH tWLEH tWLWH tAVWL tDVWH tWHD X tWHAX DQ[15:0] - Dataout tWLQZ tWHQX Table 13: Bus Turnaround Parameter Symbol Minimum Maximum Units 35ns 45ns W# Low to Data Hi-Z tWLQZ 0 12 15 ns W# High to Output Active tWHQX 3 - ns Notes: Power supplies must be stable Addresses valid either before or at the same time as E# goes low

/M3016316/M3032316 Sep.3.21 Page 22 Read Operation Figure 9: Read Operation ADDR[20:0] DQ[15:0] tAVAV tAVQV tELQV tGLQV tELQX tGLQX Don’t Care tEH QZ tGH QZ New Address New Address Data Pre vi ous Addre ss Data tAX QX UB#, LB# tB L QX tBHQZ tELQV Table 14: Read Operation Parameter Symbol Minimum Maximum Units 35ns 45ns 35ns 45ns Read Cycle Time tAVAV 35 45 - ns Address Cycle Time tAVQV - 35 45 ns Chip Enable Access Time tELQV - 35 45 ns Output Enable Access Time tGLQV - 15 25 ns Byte Enable Access Time tBLQV - 15 25 ns Output Hold From Address Change tAXQX 3 - ns Chip Enable Low to Output Active tELQX 3 - ns Output Enable Low to Output Active tGLQX 0 - ns Byte Enable Low to Output Active tBLQX 0 - ns Chip Enable High to Output Hi-Z tEHQZ 0 15 ns Output Enable High to Output Hi-Z tGHQZ 0 10 15 ns Byte Enable High to Output Hi-Z tBHQZ 0 10 ns Notes: W# is High (Logic ‘1’) for Read operation Power supplies must be stable Addresses valid either before or at the same time as E# goes low

/M3016316/M3032316 Sep.3.21 Page 23 Endurance and Data Retention Table 15: Endurance and Data Retention Parameter Symbol Test Conditions Minimum Units Write Endurance END - 1014 cycles Data Retention RET 105°C 10 years 85°C 1,000 75°C 10,000 65°C 1,000,000 Notes: W# is High (Logic ‘1’) for Read operation

/M3016316/M3032316 Sep.3.21 Page 24 Thermal Resistance Table 16: Thermal Resistance Specifications Parameter Description Test Conditions 44-pin TSOP 54-pin TSOP (4-16Mb)

48 Ball

(4-16Mb) (32Mb) Unit θJA Thermal resistance (junction to ambient) Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 40.05 52.78 42.67 43.98 oC/ W θJC Thermal resistance (junction to case) 7.02 6.70 11.09 11.82 Notes: 1: These parameters are guaranteed by characterization; not tested in production.

/M3016316/M3032316 Sep.3.21 Page 25

Revision History

Revision Date Change Summary Sept.03.21 Initial release

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