M3000SQ/NOPB

LM3000 TI1 | Alldatasheet

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www.ti.com SNVS612B –JULY 2009–REVISED APRIL 2013 LM3000DualSynchronousEmulatedCurrent-ModeController Check forSamples: LM3000 1FEATURES DESCRIPTION The LM3000 is a dual output synchronous buck 2• VIN Range FROM 3.3Vto18.5V controllerwhichisdesignedtoconvertinputvoltages• Output VoltageFrom 0.6Vto80% ofVIN rangingfrom 3.3V to 18.5V down to outputvoltages

• Remote DifferentialOutput VoltageSensing as low as 0.6V.The two outputsswitchata constant programmablefrequencyof200 kHz to1.5MHz, with• 1% Accuracy atFB Pin thesecond output180 degreesoutofphase fromthe• InterleavedOperationReduces Input firstto minimizethe inputfilterrequirements.TheCapacitors switchingfrequencycan alsobe phase lockedto an
• Frequency Sync/AdjustFrom 200 kHz to1.5 externalfrequency.A CLKOUT providesan external MHz clock90 degreesoutofphase withthemain clockso thata second chipcan be run outofphase withthe• StartupWith Pre-BiasLoad main chip.The emulatedcurrent-modecontrolutilizes• IndependentPower Good, Enable,Soft-Start bottom side FET sensing to providefasttransientand Track response and currentlimitwithoutthe need for
• Programmable CurrentLimitWithoutExternal externalcurrentsense resistorsor RC networks. Separate Enable, Soft-Startand Track pins allowSense Resistor each outputtobe controlledindependentlytoprovide• Hiccup Mode ShortCircuitProtection maximum flexibilityin designing system power sequencing.APPLICATIONS The LM3000 has a fullrange of protectionfeatures• DC Power DistributionSystems which includeinputunder-voltagelock-out(UVLO),
• Graphic Cards -GPU and Memory ICs power good (PGOOD) signalsforeach output,over- voltagecrowbarand hiccupmode duringshortcircuit• FPGA, CPLD, and ASICs events.• Embedded Processor
• 1.8Vand 2.5VI/OSupplies
• Networking Equipment (Routers,Hubs) Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2009–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

EA1_GND FB1 PGOOD1 TRK1 EN1 SS1 HG2 VSW2 LG2 PGND2 EA2_GND PGOOD2 TRK2 EN2 SS2 FREQ/SYNC CLKOUT SGND VIN FB2 R FBT2 R FBB2 C OUT2 Q 4 Q 3 R FBT1 R FBB1 C OUT1 Q 2 Q 1 R FRQ SYNC C SYNC VOUT1 VIN C IN GND1 GND2 VOUT2 C SS2C SS1 LM3000 SNVS612B –JULY 2009–REVISED APRIL 2013 www.ti.com SimplifiedApplication

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DAP (should be tied to SGND on board) VSW2 PGND2 LG2 VIN VDR LG1 PGND1 VSW1 PGOOD2 EN2 SS2 TRK2 SS1 TRK1 EN1 FREQ/SYNC ILIM2 HG2 VCB2 SGND CLKOUT EA2_GND FB2 COMP2 ILIM1 HG1 VCB1 VDD EA1_GND FB1 COMP1 PGOOD1 LM3000 WQFN-32 5x5x0.8mm body size 0.5mm pitch LM3000 www.ti.com SNVS612B –JULY 2009–REVISED APRIL 2013 Connection Diagram Figure1. Top View 32-Lead WQFN Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LM3000

SNVS612B –JULY 2009–REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS Pin No. Name Description 1 VSW2 Switchnode sense forchannel2. 2 PGND2 Power groundforchannel2 low-sidedrivers.(1) 3 LG2 Channel2 low-sidegatedriveforexternalMOSFET. 4 VIN Chipsupplyvoltage,inputtotheVDD and VDR regulators.(3.3Vto18.5V) 5 VDR Supplyforlow-sidegatedrivers. 6 LG1 Channel1 low-sidegatedriveforexternalMOSFET. 7 PGND1 Power groundforchannel1 low-sidedrivers.(1) 8 VSW1 Switchnode sense forchannel1. 9 ILIM1 Currentlimitsettinginputforchannel1. 10 HG1 Channel1 high-sidegatedriveforexternalMOSFET. 11 VCB1 Boostvoltageforchannel1 high-sidedriver. 12 VDD Supplyforcontrolcircuitry. 13 EA1_GND Erroramplifiergroundsense forchannel1.(1) 14 FB1 Erroramplifierinputforchannel1. 15 COMP1 Erroramplifieroutputforchannel1. 16 PGOOD1 Power good signalforchannel1 under-voltageand over-voltage. 17 FREQ/SYNC Frequencyset/synchronizationinputforinternalPLL. 18 EN1 Channel1 enableinput.Used tosettheemulatedcurrentslopeforchannel1. 19 TRK1 Channel1 trackinput. 20 SS1 Channel1 soft-start. 21 TRK2 Channel2 trackinput. 22 SS2 Channel2 soft-start. 23 EN2 Channel2 enableinput.Used tosettheemulatedcurrentslopeforchannel2. 24 PGOOD2 Power good signalforchannel2 under-voltageand over-voltage. 25 COMP2 Erroramplifieroutputforchannel2. 26 FB2 Erroramplifierinputforchannel2. 27 EA2_GND Erroramplifiergroundsense forchannel2.(1) 28 CLKOUT Outputclock.CLKOUT isshifted90 degreesfromSYNC input. 29 SGND Localsignalground.* 30 VCB2 Boostvoltageforchannel2 high-sidedriver. 31 HG2 Channel2 high-sidegatedriveforexternalMOSFET. 32 ILIM2 Currentlimitsettinginputforchannel2. DAP Exposed dieattachpad.ConnecttheDAP directlytoSGND. (1) (1) The LM3000 offerstrueremotegroundsensingtoachieveverytightlineand loadregulation.Forbestlayoutpractice,theEA1_GND, and EA2_GND shouldbe tiedtothegroundend oftheoutputcapacitor(oroutputterminal)forVOUT1 and VOUT2 respectively.Insidethe LM3000, thetwo power groundnodes PGND1 and PGND2 arephysicallyisolatedfromeach otherand alsoisolatedfromtheinternal signalgroundSGND. Inordertoachievethebestcross-channelnoiserejection,itisadvisedtokeep thesethreegroundsisolatedfrom each otherforthemost partintheboardlayoutand onlytiethem togetheratthegroundterminals.

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www.ti.com SNVS612B –JULY 2009–REVISED APRIL 2013 These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings(1)(2) VIN toSGND, PGND -0.3Vto20V VSW1, VSW2 toSGND, PGND -3V to20V VDD, VDR toSGND, PGND (3) -0.3Vto5.5V VCB1, VCB2 toSGND ,PGND 24V VCB1 toVSW1, VCB2 toVSW2 5.5V FB1, FB2 toSGND, PGND -0.3Vto3.0V AllotherinputpinstoSGND, PGND (4) -0.3Vto5.5V JunctionTemperature(TJ-MAX ) 150°C StorageTemperatureRange -65°C to+150°C Maximum Lead Temperature Soldering,5 seconds 260°C ESD Rating HBM (5) 2000V (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur,includinginoperabilityand degradationof devicereliabilityand/orperformance.Functionaloperationofthedeviceand/ornon-degradationattheAbsoluteMaximum Ratingsor otherconditionsbeyond thoseindicatedintheRecommended OperatingConditionsisnotimplied.OperatingRange conditionsindicate theconditionsatwhichthedeviceisfunctionaland thedeviceshouldnotbe operatedbeyond such conditions.Forensured specificationsand conditions,see theElectricalCharacteristicstable. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. (3) VDD and VDR areoutputsoftheinternallinearregulator.Under normaloperatingconditionswhere VIN > 5.5V,theymust notbe tiedto any externalvoltagesource.Inan applicationwhere VIN isbetween 3.3Vto5.5V,itisrecommended totietheVDD, VDR and VIN pins together,especiallywhen VIN may dropbelow4.5V.Inordertohave betternoiserejectionundertheseconditions,a 10Ω,1μF input filtermay be used fortheVDD pin. (4) HG1, HG2, LG1, LG2 and CLKOUT arealloutputpinsand shouldnotbe tiedtoany externalpower supply.COMP1 and COMP2 are alsooutputsand shouldnotbe tiedtoany loweroutputimpedance power source.PGOOD1 and PGOOD2 areopen drainoutputs,with a pull-downresistanceofabout250Ω.Each ofthem may be tiedtoan externalvoltagesourcelessthan5.5Vthroughan external resistergreaterthan3kΩ,although10kΩ and above arepreferredtoreducethenecessarysignalgroundcurrent. (5) Human Body Model (HBM) is100 pF capacitordischargedthrougha 1.5kresistorintoeach pin.ApplicablestandardisJESD22-A114C. OperatingRatings(1) InputVoltageRange VDD = VDR = VIN(2) 3.3Vto5.5V VIN 3.3Vto18.5V JunctionTemperature(TJ)Range −40°C to+125°C (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur,includinginoperabilityand degradationof devicereliabilityand/orperformance.Functionaloperationofthedeviceand/ornon-degradationattheAbsoluteMaximum Ratingsor otherconditionsbeyond thoseindicatedintheRecommended OperatingConditionsisnotimplied.OperatingRange conditionsindicate theconditionsatwhichthedeviceisfunctionaland thedeviceshouldnotbe operatedbeyond such conditions.Forensured specificationsand conditions,see theElectricalCharacteristicstable. (2) VDD and VDR areoutputsoftheinternallinearregulator.Under normaloperatingconditionswhere VIN > 5.5V,theymust notbe tiedto any externalvoltagesource.Inan applicationwhere VIN isbetween 3.3Vto5.5V,itisrecommended totietheVDD, VDR and VIN pins together,especiallywhen VIN may dropbelow4.5V.Inordertohave betternoiserejectionundertheseconditions,a 10Ω,1μF input filtermay be used fortheVDD pin. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LM3000

SNVS612B –JULY 2009–REVISED APRIL 2013 www.ti.com ElectricalCharacteristics LimitsinstandardtypeareforTJ = 25°C only;limitsinboldfacetypeapplyoverthejunctiontemperature(TJ)rangeof-40°C to+125°C. Minimum and Maximum limitsareensuredthroughtest,design,orstatisticalcorrelation.Typicalvaluesrepresent themost likelyparametricnorm atTJ = 25°C, and areprovidedforreferencepurposesonly.Unlessotherwisenoted,VIN = 12.0V,IEN1 = IEN2 = 40 µA. Symbol Parameter Condition Min Typ Max Units VFB FB PinVoltageFB1, FB2 (LM3000A) -20°C to+85°C 0.594 0.6 0.606 V 0.591 0.6 0.609 VFB FB PinVoltageFB1, FB2 (LM3000) -20°C to+85°C 0.591 0.6 0.609 V 0.588 0.6 0.612 ΔVFB /VFB LineRegulationVDD = VIN = VDR 3.3V< VIN < 5.5,COMP = 1.5V 0.15 % LineRegulationVIN > 6V 6V < VIN < 18.5V,COMP = 1.5V 0.3 % Load Regulation VIN = 12.0V,1.0V< COMP < 1.4V 0.1 % Iq VIN OperatingCurrent 5 mA ISD VIN Shutdown Current IEN1 ,IEN2 < 5 µA 50 µA IEN EN InputThresholdCurrent IEN Rising 15 35 µA Hysteresis 10 ILIM SourceCurrentILIM1,ILIM2 VILIM1,VILIM2= 0V 17 20 23 µA ISS Soft-StartPull-UpCurrent VSS = 0.5V 5.5 8.5 11.5 µA VHICCUP COMP PinHiccupThresholds COMP ThresholdHigh 2.85 V Hysteresis 50 mV tDELAY HiccupDelay 16 Cycles tCOOL Cool-Down Time UntilRestart 4096 Cycles VOVP Over-VoltageProtectionThreshold As a % ofNominalOutputVoltage 110 115 120 % Hysteresis 3 VUVP Under-VoltageProtectionThreshold As a % ofREF1, REF2 (seeBlock 85 % Diagram) GATE DRIVE ICB VCB PinLeakage Current VCB -VSW = 5.5V 250 nA R DS1 Top FET DrivePull-UpOn-Resistance VCB -VSW = 4.5V,VCB -HG = 100 3 Ω mV R DS2 Top FET DrivePull-DownOn-Resistance VCB -VSW = 4.5V,HG -VSW = 100 2 Ω mV R DS3 BottomFET DrivePull-UpOn-Resistance VDR -PGND = 5V,VDR -LG = 100 2 Ω mV R DS4 BottomFET DrivePull-DownOn- VDR -PGND = 5V,LG -PGND = 100 1 Ω Resistance mV OSCILLATOR fSW SwitchingFrequency R FRQ = 100 kΩ 230 kHz R FRQ = 42.2kΩ 425 500 575 kHz R FRQ = 10 kΩ 1550 kHz VSYNC ThresholdforSynchronizationatthe Rising 2.2 V FREQ/SYNC Pin Falling 0.6 fSYNC SYNC Range 200 1500 kHz tSYNC SYNC PulseWidth 100 ns tSYNC-TRS SYNC Rise/FallTime 10 ns D MAX Maximum Dutycycle 85 % ERROR AMPLIFIER IFB FB PinBiasCurrent FB = 0.6V 20 nA ISOURCE COMP PinSourceCurrent FB = 0.5V,COMP = 1.0V 80 µA ISINK COMP PinSinkCurrent FB = 0.7V,COMP = 0.7V 80 µA

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www.ti.com SNVS612B –JULY 2009–REVISED APRIL 2013 ElectricalCharacteristics(continued) LimitsinstandardtypeareforTJ = 25°C only;limitsinboldfacetypeapplyoverthejunctiontemperature(TJ)rangeof-40°C to+125°C. Minimum and Maximum limitsareensuredthroughtest,design,orstatisticalcorrelation.Typicalvaluesrepresent themost likelyparametricnorm atTJ = 25°C, and areprovidedforreferencepurposesonly.Unlessotherwisenoted,VIN = 12.0V,IEN1 = IEN2 = 40 µA. Symbol Parameter Condition Min Typ Max Units VCOMP-HI COMP PinVoltageHighClamp 2.80 3.0 3.2 V VCOMP-LO COMP PinVoltageLow Clamp 0.48 V VOS-TRK OffsetUsingTRK Pin TRK = 0.45V -9.0 0 9.0 mV gm Transconductance 1400 µS fBW UnityGain BandwidthFrequency 10 MHz INTERNAL VOLTAGE REGULATOR VVDD InternalCore RegulatorVoltage No ExternalLoad 5.15 V VVDD-ON UVLO Thresholds VDD Rising 2.12 V Hysteresis 0.14 VVDD-DO InternalCore RegulatorDropoutVoltage No ExternalLoad 1.1 V IVDD-ILIM InternalCore RegulatorCurrentLimit VDD ShorttoGround 80 mA VVDR RegulatorforExternalMOSFET Drivers IVDR = 100 mA 5.2 V VVDR-DO DriverRegulatorDropoutVoltage IVDR = 100 mA 1.0 V IVDR-ILIM DriverRegulatorCurrentLimit VDR ShorttoGround 450 mA PGOOD OUTPUT R PG-ON PGOOD On-Resistance FB1 = FB2 = 0.47V 250 Ω IOH PGOOD HighLeakage Current VPGOOD = 5V 100 nA THERMAL RESISTANCE θJA Junction-to-AmbientThermalResistance WQFN-32 Package(1) 26.4 °C/W (1) Testedon a fourlayerJEDEC board.Fourviasprovidedundertheexposed pad.See JEDEC standardsJESD51-5 and JESD51-7. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LM3000

SNVS612B –JULY 2009–REVISED APRIL 2013 www.ti.com TypicalPerformance Characteristics 3.3VOutput Efficiencyat500 kHz 1.2VOutput Efficiencyat500 kHz Figure2. Figure3. 3.3VOutput Load and LineRegulation 1.2VOutput Load and LineRegulation Figure4. Figure5. FB1, FB2 Referencevs Temperature VDD Voltagevs Temperature Figure6. Figure7.

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VOUT1 (1V/DIV) VEN1 and VEN2 (5V/DIV) VOUT2 (0.5V/DIV) 1 ms/DIV IL2 (10A/DIV) SW2 (5V/DIV) VOUT2 (1V/DIV) 5 ms/DIV VOUT1 (1V/DIV) VEN1 and VEN2 (5V/DIV) VOUT2 (0.5V/DIV) 1 ms/DIV VOUT1 (1V/DIV) SW1 (10V/DIV) 5 ms/DIV VOUT1 (2V/DIV) VEN1 and VEN2 (5V/DIV) VOUT2 (1V/DIV) 1 ms/DIV IL1 (5A/DIV) SW1 (5V/DIV)

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www.ti.com SNVS612B –JULY 2009–REVISED APRIL 2013 TypicalPerformance Characteristics(continued) Soft-StartwithoutLoad Pulse SkippingduringOver-CurrentCondition Figure8. Figure9. No Load Soft-StartwithPre-Bias Output ShortCircuitHiccup Figure10. Figure11. Soft-StartwithLoad Switch Node ShortCircuitHiccup Figure12. Figure13. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LM3000

VOUT1 (2V/DIV) SW1 (10V/DIV) External Clock (1V/DIV) FB1 (1V/DIV) VOUT1 (2V/DIV) TRK1 (1V/DIV) 20 ms/DIV LM3000 SNVS612B –JULY 2009–REVISED APRIL 2013 www.ti.com TypicalPerformance Characteristics(continued) ExternalClock Synchronization ExternalTracking Figure14. Figure15. ErrorAmplifierTransconductance vs Temperature Enable CurrentThresholdvs Temperature Figure16. Figure17. SwitchingFrequency vs Temperature R FRQ vs SwitchingFrequency Figure18. Figure19.

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5.2V REGS VDD VDR gm BIAS EN1 EN2 VBG 0.6V CLOCK/ PLL FREQ/ SYNC CLKOUT VSW1 20 éA 8.5 éA SS2 TRK2TRK1 SS1 RAMP1 RAMP2 ILIM1 ILIM2 PGND2 PGND1 VSW2 IFREQ IVIN ISLOPE1 ISLOPE2 CURRENT EMULATION AND SLOPE COMPENSATION REF1 REF2 SYSTEM_CLOCK VSW1 VSW2 PWM LOGIC DUTY CYCLE AND DRIVER CONTROL EN1 EN2 SYSTEM_REF REF1 REF2 VOUT1, VOUT2 MONITOR EN1 EN2 SYSTEM_REF VCB1 HG1 LG1 VSW1 PGND1COMP1 FB1 FB1 EA1_GND EA2_GND FB2 FB2 COMP2 PGOOD1 PGOOD2 VCB2 HG2 VDR LG2 3011 10 31 VSW2VDR R DSON SENSING ASEN (s) EN1 or FAULT EN2 or FAULT 20 éA PGND2 OC1 OC2 R DSON SENSING ASEN (s) LG2 LG2 LG1 LG1 FAULT 8.5 éA 250Ö 250Ö SGND 29 1 kÖ 1 kÖ gmn FB2FB1 gm gm REF2REF1 LM3000 www.ti.com SNVS612B –JULY 2009–REVISED APRIL 2013 BLOCK DIAGRAM Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LM3000

tSS > VOUT x COUT ILIMIT ± IOUT tSS = C SS x 0.6V 8.5 éA LM3000 SNVS612B –JULY 2009–REVISED APRIL 2013 www.ti.com FUNCTIONAL DESCRIPTION THEORY OF OPERATION The LM3000 isa dualemulatedcurrent-modePWM synchronouscontroller.Unliketraditionalpeak current-mode controllerswhichsense thecurrentwhilethehigh-sideFET ison,theLM3000 senses currentwhilethelow-side FET ison.Itthenemulatesthepeak currentwaveform and uses thatinformationtoregulatetheoutputvoltage. The blankingtimewhen thehigh-sideFET firstturnson thatisnormallyassociatedwithhigh-sidesensingisnot needed,allowinghigh-sideON pulsesas low as 50 ns.The LM3000 thereforehas bothexcellentlinetransient responseand theabilitytoregulatelowoutputvoltagesfromhighinputvoltages. STARTUP AftertheEN1 orEN2 currentexceeds theenableON thresholdand thevoltageattheVDD pinreaches2.2V,an internal8.5µA currentsourcechargesthesoft-startcapacitoroftheenabledchannel.Once soft-startiscomplete theconverterenterssteadystateoperation.Currentlimitisenabledduringsoft-startincase ofa shortcircuitat theoutput.The soft-starttimeiscalculatedas: (1) To avoidcurrentlimitduringstartup,thesoft-starttimetSS shouldbe substantiallylongerthanthetimerequired tochargeC OUT toVOUT atthemaximum outputcurrent.To meet thisrequirement: (2) STARTUP INTO OUTPUT PRE-BIAS Ifthe outputcapacitorof the LM3000 has been charged up to some pre-biaslevelbeforethe converteris enabled,thechipwillforcethesoft-startcapacitortothesame voltageas theFB pin.Thiswillcause theoutput toramp up fromtheexistingoutputvoltagewithoutdischargingit.Duringthesoft-startramp,thelow-sideFET is disabledwhenever theCOMP voltageisbelowtheactiveregulationvoltagerange. LOW INPUT VOLTAGE The LM3000 includesan internal5.2V linearregulatorconnectedfrom theVIN pintotheVDD pin.Thislinear regulatorfeedsthelogicand FET drivecircuitry.For inputvoltageslessthan5.5V,theVIN,VDD and VDR pins can be tiedtogetherexternally.Thisallowsthefullinputvoltagetobe used fordrivingthepower FETs and also minimizesconductionlossintheLM3000. TRACKING The LM3000 has individualtrackinginputswhich controleach outputduringsoft-start.Thisallowsthe output voltageslew ratestobe controlledforloadsthatrequireprecisesequencing.When thetrackingfunctionisnot beingused theTRK1 orTRK2 pinsshouldbe connecteddirectlytotheVDD pin. Duringstart-up,theerroramplifierwillfollowtheloweroftheSS or TRK voltages.For designmargin,thesoft- starttimetSS shouldbe setto75% oftheminimum expectedrisetimeofthecontrollingsupply.Intheeventthat theLM3000 isenabledwitha pre-biasedmastersupplycontrollingtrack,thesoft-startcapacitorwillcontrolthe trackingoutputvoltagerisetime.PullingTRK down aftera normalstartupwillcause theoutputvoltagetofollow thetracksignal.

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VOUT2 = VOUT1 x R T1 R T1 + RT2 VOUT1 VOUT2 3.3V 1.2V 0.8 x 3.3V 0.75 = VOUT1 x R T1 R T1 + RT2 R T2 R T1 TRK2 FB2 LM3000 VOUT1 R FBT1 R FBB1 VOUT2 R FBT2 R FBB2 TRK1 FB1VDD LM3000 www.ti.com SNVS612B –JULY 2009–REVISED APRIL 2013 Figure20. TrackingwithVOUT1 ControllingVOUT2 Figure20 shows a trackingexample withthehighestoutputvoltageatVOUT1 controllingVOUT2 .Trackingmay be setso thatVOUT1 and VOUT2 bothrisetogether.For thiscase,theequationgoverningthevaluesofthetracking dividerresistorsR T1 and R T2 is: (3) A valueof10 kΩ 1% isrecommended forR T1 as a good compromise between highprecisionand low quiescent A timingdiagramforVOUT1 controllingVOUT2 isshown inFigure21.Note thattheTRK pinmust finishatleast100 mV higherthan the 0.6V referenceto achieve the fullaccuracy of the LM3000 regulation.To meet this requirementthetrackingvoltageisoffsetby 150 mV. The trackingoutputvoltagewillreachitsfinalvalueat80% ofthecontrollingoutputvoltage. Figure21. TrackingwithVOUT1 ControllingVOUT2 Alternatively,thetrackingfeaturecan be used tocreateequalslewratesfortheoutputvoltages.Inordertotrack properly,use the highestoutputvoltageto controlthe slew rate.In thiscase,the trackingresistorsare found from: (4) Again,a valueof10 kΩ 1% isrecommended forR T1.For theexample case ofVOUT1 = 5V and VOUT2 = 1.8V,R T2 is17.8kΩ 1%. A timingdiagramforthecase ofequalslewratesisshown inFigure22. Eithermethod ensuresthattheoutputvoltageofthetrackingsupplyalwaysreachesregulationbeforetheoutput voltageofthecontrollingsupply. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LM3000

1.2V VOUT1 3.3V 0.8 x 5V MASTER POWER SUPPLY VMASTER R T2 R T1 TRK2 FB2 LM3000 VOUT1 R FBT1 R FBB1 VOUT2 R FBT2 R FBB2 TRK1 FB1 0.75 = VMASTER x R T1 R T1 + RT2 VOUT1 VOUT2 1.8V 1.8V LM3000 SNVS612B –JULY 2009–REVISED APRIL 2013 www.ti.com Figure22. TrackingwithEqual Slew Rates The LM3000 can tracktheoutputofa masterpower supplyby connectinga resistordividertotheTRK pinsas shown inFigure23.Forequalstarttimes,thetrackingresistorsaredeterminedby: (5) Figure23. Trackinga Master Supply withEqual StartTime Figure24. Trackinga Master Supply withEqual StartTime Forequalslewrates,thecircuitofFigure25 isused.The relationshipforthetrackingdividerissetby:

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VOUT = 0.6 x R FBB R FBB + RFBT VMASTER VOUT2 1.2V 1.2V VOUT1 3.3V 3.3V MASTER POWER SUPPLY VMASTER R T2 R T1 TRK2 FB2 LM3000 VOUT1 R FBT1 R FBB1 VOUT2 R FBT2 R FBB2 TRK1 FB1R T3 VOUT1 = VMASTER x R T1 + RT2 R T1 + RT2 + RT3 VOUT2 = VMASTER x R T1 R T1 + RT2 + RT3 LM3000 www.ti.com SNVS612B –JULY 2009–REVISED APRIL 2013 (6) Figure25. Trackinga Master Supply withEqual Slew Rates Figure26. Trackinga Master Supply withEqual Slew Rates Continuous Conduction Mode The LM3000 controlstheoutputvoltageby adjustingthedutycycleofthepower MOSFETs withtrailingedge pulse widthmodulation.The outputinductorand capacitorfilterthe square wave produced as the power MOSFETs switchthe inputvoltage,therebycreatinga regulatedoutputvoltage.The dc levelof the output voltageisdeterminedby feedbackresistorsusingthefollowingequation: (7) The outputinductorcurrentcan flowfrom the drainto the sourceof the low-sideMOSFET, which keeps the converterin continuous-conduction-mode(CCM). CCM has the advantage of constantfrequencyand nearly constantdutycycle(D = VOUT /VIN)overallloadconditions,and alsoallowstheconvertertosinkcurrentatthe outputifneeded. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LM3000

R FRQ = 2.48 x 1010 fSW 3.4 x 106 - 1000 fSW x LM3000 SNVS612B –JULY 2009–REVISED APRIL 2013 www.ti.com FREQUENCY SETTING The switchingfrequencyoftheinternaloscillatorissetby a resistor,R FRQ ,connectedfromtheFREQ/SYNC pin to SGND. The properresistorfora desiredswitchingfrequencyfSW can be selectedfrom the curvesin the TypicalPerformanceCharacteristicssectionlabeled“R FRQ vs SwitchingFrequency” or by usingthe following equation: where

• fSW istheswitchingfrequencyinHz (8) FREQUENCY SYNCHRONIZATION The switchingfrequencyoftheLM3000 can be synchronizedby an externalclockorotherfixedfrequencysignal intherangeof200 kHz to1.5MHz. The externalclockshouldbe appliedthrougha 100 pF couplingcapacitoras shown inFigure27. In orderforthe oscillatorto synchronizeproperly,the minimum amplitudeof the SYNC signalis2.2V and themaximum amplitudeisVDD. The minimum pulsewidthbothpositiveand negativeis100 ns.The nominaldc voltageattheFREQ/SYNC pinis0.6V,which isalsotheclamp voltagelevelforthefalling edge of the SYNC pulse.Depending on the pulsewidthand frequency,C SYNC may be adjustedto provide sufficientamplitudeofthesignalattheFREQ/SYNC. Itispossibletodrivethispindirectlyfroma 0 to2.2V logic output,thoughnotrecommended forthetypicalapplication. Circuitsthatuse an externalclockshouldstillhave a resistorR FRQ connectedfrom the FREQ/SYNC pin to ground.R FRQ isselectedusingthe equationfrom the FREQUENCY SETTING sectionto match the external clockfrequency.Thisallowsthecontrollertocontinueoperatingatapproximatelythesame switchingfrequencyif theexternalclockfailsand thecouplingcapacitoron theclocksideisgroundedorpulledtologichigh. In the case of no externalclockedges at startup,the internaloscillatorwillbe controlledby the externalset resistoruntilthefirstclockedge isdetected.Afterthefirstedge,thePLL willlockwithina few clockcycles,after whichany missingedges willcause theoscillatortobe programmed by R FRQ .IfR FRQ ischosen toprogram the oscillatorverycloseto the externalclockfrequency,the PLL willlockveryquicklyand therewillbe verylittle disturbanceintheswitchingfrequency. Care must be takentopreventerrantpulsesfromtriggeringthesynchronizationcircuitry.Incircuitsthatwillnot synchronizeto an externalclock,C SYNC shouldbe connectedfrom the FREQ/SYNC pinto SGND as a noise filter.When a clockpulseisfirstdetected,theLM3000 beginsswitchingattheexternalclockfrequency.Noiseor a shortburstofclockpulsesmay resultinvariationsoftheswitchingfrequencydue tolossoflockby thePLL. Figure27. Clock SynchronizationCircuit In the case where two LM3000 controllersare used, the CLKOUT of the firstcontrollercan be used as a synchronizationinputforthesecond controller.Note thattheCLKOUT is90 degreesoutofphase withthemain controllerclock,so thatthefourphases ofthetwo controllersareseparatedforminimum inputripplecurrent.

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R LIM = 20 éA ILIMIT x RDS(on)_LO HG SW LG C BOOTVDR LM3000 VINVCB VOUT LM3000 www.ti.com SNVS612B –JULY 2009–REVISED APRIL 2013 MOSFET GATE DRIVE The LM3000 has two setsof gate driversdesignedfordrivingN-channelMOSFETs ina synchronousmode. Power forthehigh-sidedriverissuppliedthroughtheVCB pin.For thehigh-sidegateHG toturnon thetopFET, theVCB voltagemust be atleastone VGS(th)greaterthanVIN.Thisvoltageissuppliedfroma localchargepump whichconsistsofa Schottkydiodeand bootstrapcapacitor,shown inFigure28.For theSchottky,a ratingofat least250 mA and 30V isrecommended. A dualpackage may be used tosupplybothVCB1 and VCB2. Both the bootstrapand the low-sideFET driverare fed from VDR, which isthe outputof a 5V internallinear regulator.Thisregulatorhas a dropoutvoltageofapproximately1V. The drivevoltageforthetopFET driveris aboutVDR -0.5atlightloadconditionand aboutVDR atnormaltofullloadcondition.Thisinformationisneeded toselectthetypeofMOSFETs used,as wellas calculatethelossesindrivingthem. Figure28. BootstrapCircuit UVLO For thecase where VIN is> VDD, theVIN UVLO thresholdsaredeterminedby theVDD UVLO comparatorand theVDD dropoutvoltage.ThissetstherisingthresholdforVIN atapproximately3V,with30 mV ofhysteresis. For thecase where VIN is< 5.5V and tiedtoVDD and VDR, theUVLO trippointis2.12V rising.UVLO consists ofturningoffthetopand bottomFETs and remaininginthatconditionuntilVDD risesabove 2.12V.The falling trippointis140 mV belowtherisingtrippoint. CURRENT LIMIT The currentlimitoftheLM3000 isrealizedby sensingthecurrentinthelow-sideFET whiletheoutputcurrent circulatesthroughit.Thisvoltage(IOUT x R DS(on)_LO) iscompared againstthevoltageofa fixed,internal20 µA currentsourceand a user-selectedresistor,R LIM,connectedbetween theswitchnode and theILIMpin.Once a currentlimiteventissensed,thehigh-sideswitchisdisabledforthefollowingcycleand thelow-sideFET iskept on duringthistime.Ifsixteenconsecutivecurrentlimitcyclesoccur,thepartentershiccupmode. The valueofR LIM fora desiredcurrentlimitIILIMITcan be selectedby thefollowingequation: (9) HICCUP MODE Duringhiccupmode theLM3000 disablesboththehigh-sideand low-sideMOSFETs, and remainsinthisstate for4096 switchingcycles.Afterthiscooldown periodthe circuitrestartsagainthroughthe normal soft-start sequence.Iftheshortedfaultconditionpersists,hiccupwillretriggeronce thesoft-starthas finished.Thisoccurs when theSS voltageisgreaterthan0.7Vand switchinghas reachedthecontinuousconductionmode state. There isa coarsehigh-sidecurrentlimitwhichsenses thevoltageacrossthehigh-sideMOSFET. The threshold is approximately0.5V, which may providesome levelof protectionfor a catastrophicfault.Hiccup will immediatelytriggeraftertwo consecutivehigh-sidecurrentlimitfaultevents. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LM3000

D =VOUT VIN x 1 K LM3000 SNVS612B –JULY 2009–REVISED APRIL 2013 www.ti.com POWER GOOD Power good pins PGOOD1 and PGOOD2 are availableto monitorthe outputstatusof the two channels independently.The PGOOD1 pinconnectstotheoutputofan open drainMOSFET, whichwillremainopen while Channel 1 is withinthe normal operatingrange.PGOOD1 goes low (lowimpedance to ground)under the followingthreeconditions: 1.Channel1 isturnedoff. 2.OVP on Channel1. 3.UVP on Channel1. PGOOD2 functionsina similarmanner. UVP tracksREF1, REF2 as shown intheblockdiagram.OVP setsa faultwhichturnsoffthehighgateand turnson thelow gate.Thisdischargestheoutputvoltageuntilithas fallen 3% belowtheOVP threshold. PGOOD may be pulledup througha resistortoany voltagewhich is< 5.5V.When usingVDD forthepull-up voltage,a typicalvalueof100 kΩ isused tominimizeloadingon VDD. ENABLE A fixedexternalvoltagesourceand resistorstoEN1 and EN2 are used toindependentlyenableeach output. The LM3000 can be put intoa low power shutdown mode by pullingthe EN1 and EN2 pinsto ground,or by applying0V totheenableresistors.Duringshutdown boththehigh-sideand low-sideFETs are disabled.The quiescentcurrentduringshutdownisapproximately30 µA. The enablepinsalsocontrolthe emulatedcurrentramp amplitudeby programming the currentintoEN1 and EN2. The recommended range forIEN is 40 μA to 160 μA. See the ApplicationInformationsectionunder CONTROL LOOP COMPENSATION forthecompletedesignmethod.

APPLICATION INFORMATION

The most common circuitcontrolledby the LM3000 isa non-isolated,synchronousbuck regulator.The buck regulatorstepsdown theinputvoltageand has a dutyratioD of: where

• η istheestimatedconverterefficiency (10) The followingisa designexample selectingcomponents fortheTypicalApplicationSchematicofFigure43.The circuitisdesignedfortwo outputsof3.3V at8A and 1.2V at15A froman inputvoltageof6V to18V. Thiscircuit istypicalofa ‘brick’module and has a heightrequirementof6.5mm or less.Otherassumptionsused toaidin circuitdesignarethattheexpectedloadisa smallmicroprocessororASIC withfastloadtransients,and thatthe typeofMOSFETs used areinSO-8 oritsequivalentpackagessuch as PowerPAK ® ,PQFN and LFPAK (LFPAK- i). SWITCHING FREQUENCY The selectionof switchingfrequencyisbased on the tradeoffbetween size,costand efficiency.In general,a lowerfrequencymeans larger,more expensiveinductorsand capacitors.A higherswitchingfrequencygenerally resultsina smallerbutlessefficientsolution,because thepower MOSFET gatecapacitancesmust be charged and dischargedmore oftenina givenamount oftime.For thisapplicationa frequencyof500 kHz isselected. 500 kHz is a good compromise between the sizeof the inductorand MOSFETs, transientresponse and efficiency.FollowingtheequationgivenforR FRQ intheFREQUENCY SETTING section,for500 kHz operationa 42.2kΩ 1% resistorisused. MOSFETS Selectionofthepower MOSFETs isgovernedby a tradeoffbetween size,costand efficiency.Buck regulators thatuse a controllerIC and discreteMOSFETs tendtobe most efficientforoutputcurrentsof4A to20A.

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IL_PK gmFET_HI VPLT2 VTH + IL_VL gmFET_HI VPLT1 VTH + PSW_OFF = VIN x IL_PK x E x RG_OFF Q GD + CISS x Ln VTH VPLT2 VPLT2 x PSW_ON = VIN x IL_VL x D x RG_ON Q GD + CISS x Ln VDR - VTH VDR - VPLT2 VDR ± VPLT1 x LM3000 www.ti.com SNVS612B –JULY 2009–REVISED APRIL 2013 Losses inthe high-sideFET can be broken down intoconductionloss,gate charge lossand switchingloss. Conduction,orI2R lossisapproximately: PCOND_HI = D x (IOUT 2 x R DS(on)_HI x 1.3)(High-sideFET) (11) PCOND_LO = D x (IOUT 2 x R DS(on)_LO x 1.3)(Low-sideFET) (12) In the above equationsthe factor1.3 accountsforthe increasein MOSFET R DS(on) due to selfheating. Alternatively,the1.3can be ignoredand theR DS(on) oftheMOSFET estimatedusingtheR DS(on) vs.Temperature curvesintheMOSFET datasheets. The gate charge lossresultsfrom the currentdrivingthe gate capacitanceof the power MOSFETs, and is approximatedas: PDR = VIN x (QG_HI + Q G_LO )x fSW (13) Where Q G_HI and Q G_LO are thetotalgatechargeofthehigh-sideand low-sideFETs respectivelyatthetypical 5V drivervoltage.Gate chargelossdiffersfromconductionand switchinglossesinthatthemajorityofdissipation occursintheLM3000. The switchinglossoccursduringthebrieftransitionperiodas theFET turnson and off,duringwhichbothcurrent and voltagearepresentinthechanneloftheFET. Thiscan be approximatedas thefollowing: (14) (15) Where Q GD isthehigh-sideFET Millerchargewitha VDS swingbetween 0 toVIN;C ISS istheinputcapacitanceof thehigh-sideMOSFET initsoffstatewithVDS = VIN.α and β are fittingcoefficientnumbers,which are usually between 0.5to1,dependingon theboardlevelparasiticinductancesand reverserecoveryofthelow-sidepower MOSFET body diode.Under idealcondition,settingα = β = 0.5 isa good startingpoint.Other variablesare definedas: IL_VL = IOUT -0.5x ΔIL (16) IL_PK = IOUT + 0.5x ΔIL (17) (18) (19) R G_ON = 8.5+ R G_INT + R G_EXT (20) R G_OFF = 2.8+ R G_INT + R G_EXT (21) Switchinglossiscalculatedforthe high-sideFET only.8.5 and 2.8 representthe LM3000 high-sidedriver resistanceinthetransientregion.R G_INT isthegateresistanceofthehigh-sideFET, and R G_EXT istheexternal gateresistanceifapplicable.R G_EXT may be used todamp outexcessiveparasiticringingattheswitchnode. For thisexample,themaximum drain-to-sourcevoltageappliedtoeitherMOSFET is18V. The maximum drive voltageatthegateofthehigh-sideMOSFET is5V, and themaximum drivevoltageforthelow-sideMOSFET is 5V. The selectedMOSFET must be abletowithstand18V plusany ringingfromdraintosource,and be ableto handleatleast5V plusringingfromgatetosource.Ifthedutycycleoftheconverterissmall,thenthehigh-side MOSFET shouldbe selectedwitha low gate charge inorderto minimizeswitchinglosswhereas the bottom MOSFET shouldhave a lowR DSON tominimizeconductionloss. For a typicalinputvoltageof 12V and outputcurrentsof 8A and 12A, the MOSFET selectionsforthe design example areHAT2168 forthehigh-sideMOSFET and RJK0330DPB forthelow-sideMOSFET. A 3Ω resistorforR CBT isadded inserieswiththeVDR regulatoroutput,as shown inFigure43.Thishelpsto controltheMOSFET turn-onand ringingattheswitchnode,withoutaffectingtheMOSFET turn-off. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LM3000

'VO = 'IL x 8 x fSW x CO R C 2 + 'IL = VIN(MAX) - VOUT fSW x LACTUAL x D LMIN = VIN(MAX) - VOUT fSW x 'IL x D LM3000 SNVS612B –JULY 2009–REVISED APRIL 2013 www.ti.com To improveefficiency,3A, 40V Schottkydiodesareplacedacrossthelow-sideMOSFETs. The externalSchottky diodeshave a much lowerforwardvoltagethantheMOSFET body diode,and helptominimizethelossdue to thebody dioderecoverycharacteristic. OUTPUT INDUCTORS The firstcriterionforselectingan outputinductoristheinductanceitself.Inmost buck converters,thisvalueis based on thedesiredpeak-to-peakripplecurrent,ΔIL thatflowsintheinductoralongwiththeloadcurrent.As withswitchingfrequency,the selectionof the inductorisa tradeoffbetween sizeand cost.Higherinductance means lowerripplecurrentand hence loweroutputvoltageripple.Lower inductanceresultsin smaller,less expensivedevices.An inductancethatgivesa ripplecurrentof1/6to1/3ofthemaximum outputcurrentisa good startingpoint.(ΔIL = (1/6to 1/3)x IOUT ).Minimum inductanceiscalculatedfrom thisvalue,usingthe maximum inputvoltageas: (22) By calculatingintermsofamperes,volts,and megahertz,theinductancevaluewillcome outinmicrohenries. The inductorripplecurrentisfoundfromtheminimum inductanceequation: (23) The second criterionisinductorsaturationcurrentrating.The LM3000 has an accuratelyprogrammed valley currentlimit.Duringan instantaneousshort,the peak inductorcurrentcan be veryhighdue to a momentary increaseindutycycle.Sincethisislimitedby thecoarsehigh-sideswitchcurrentlimit,itisadvisedtoselectan inductorwitha largercore saturationmargin and preferablya softerrolloffof the inductancevalueover load current. For thedesignexample,standardvaluesof1.2μH forthe1.2V,15A outputand 2.7μH forthe3.3V,8A output arechosen tofallwithintheΔIL = (1/6to1/3)x IOUT range. The dc lossintheinductorisdeterminedby itsseriesresistanceR L.The dc power dissipationisfoundfrom: PDC = IOUT 2 x R L (24) The ac losscan be estimatedfromtheinductormanufacturer’s data,ifavailable.The ac lossissetby thepeak- to-peakripplecurrentΔIL and theswitchingfrequencyfSW . OUTPUT CAPACITORS The outputcapacitorsfilterthe inductorripplecurrentand providea source of charge fortransientload conditions.A wide rangeofoutputcapacitorsmay be used withtheLM3000 thatprovideexcellentperformance. The best performanceis typicallyobtainedusing aluminum electrolytic,tantalum,polymer,solidaluminum, organicor niobium type chemistriesin parallelwith a ceramic capacitor.The ceramic capacitorprovides extremelylow impedance to reduce the outputripplevoltageand noisespikes,whilethe aluminum or other capacitorsprovidea largerbulkcapacitancefortransientloadingand seriesresistanceforstability. When selectingthevaluefortheoutputcapacitorthetwo performancecharacteristicstoconsideraretheoutput voltagerippleand transientresponse.The outputvoltageripplecan be approximatedas: where

• ΔVO (V)isthepeak topeak outputvoltageripple
• ΔIL (A)isthepeak topeak inductorripplecurrent
• R C (Ω)istheequivalentseriesresistanceorESR oftheoutputcapacitor
• fSW (Hz)istheswitchingfrequency
• C O (F)istheoutputcapacitance (25)

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L x 'IO C O t VP x VL L x 'IO C O t 1 + 1 - R C x 'IO VP 2VP x VL L x 'IO x 1C O t R C d VP 'IO 'IL PCO = RC x VP = L x 'IO 2 x CO x VL R C 2 x CO x VL 2 x L LM3000 www.ti.com SNVS612B –JULY 2009–REVISED APRIL 2013 The amount ofoutputripplethatcan be toleratedisapplicationspecific.A generalrecommendationistokeep the outputripplelessthan 1% of the ratedoutputvoltage.The outputcapacitorselectionwillalsoaffectthe outputvoltagedroop and overshootduringa loadtransient.The peak transientof the outputvoltageduringa loadcurrentstepisdependenton many factors.Given sufficientcontrolloopbandwidthan approximationofthe transientvoltagecan be obtainedfrom: where

• VP (V)istheoutputvoltagetransient
• ΔIO (A)istheloadcurrentstepchange (26) C O (F)istheoutputcapacitance,L (H)isthevalueoftheinductorand R C (Ω) istheseriesresistanceofthe outputcapacitor.VL (V)istheminimum inductorvoltage,whichisdutycycledependent. ForD < 0.5,VL = VOUT ForD > 0.5,VL = VIN -VOUT This shows thatas the inputvoltageapproaches VOUT , the transientdroop willget worse. The recovery overshootremainsfairlyconstant. The lossassociatedwiththeoutputcapacitorseriesresistancecan be estimatedas: (27) Output CapacitorDesign Procedure For thedesignexample VIN = 12V, VOUT = 3.3V,D = VOUT /VIN = 0.275,L = 2.7μH, ΔIL = 1.8A,ΔIO = 8A and VP = 0.15V. To meet thetransientvoltagespecification,themaximum R C is: (28) Forthedesignexample,themaximum R C is18.75m Ω.Choose R C = 15 m Ω as thedesignlimit. From theequationforVP,theminimum valueofC O is: (29) ForD < 0.5,VL = VOUT ForD > 0.5,VL = VIN -VOUT WithR C = VP /ΔIO thisreducesto: (30) WithR C = 0 thisreducesto: (31) SinceD < 0.5,VL = VOUT .WithR C = 15 m Ω,theminimum valueforC O is218 μF. The minimum controlloopbandwidthfC isgivenby: Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:LM3000

ICIN(RMS)MAX | 0.5 x MAX(I1 , I2) D3 = MAX(MIN(D1 ± 0.5 , D2) , 0) + MAX(MIN(D2 ± 0.5 , D1) , 0) (I12 x D1) + (I22 x D2) + (2 x I1 x I2 x D3) ± (I1 x D1 + I2 x D2)2 ICIN(RMS) | IO x D x (1 ± D) IO + 'IL 2 x RCIN'VIN ± x fSW C IN t 'VIN = IO x D x (1 ± D) C IN x fSW IO ++ 'IL 2 x RCIN ICIN(RMS) | IO x D x (1 ± D) PCIN | IO 2 x D x (1 ± D) x RCIN 2 x S x CO x VP 'IO fC t LM3000 SNVS612B –JULY 2009–REVISED APRIL 2013 www.ti.com (32) For thedesignexample,theminimum valueforfC is39 kHz.A 220 μF,15 m Ω polymercapacitorinparallelwith a 22 μF,3 m Ω ceramicwillmeet thetargetoutputvoltagerippleand transientspecification. For the1.2V,15A output,two 220 μF, 15 m Ω polymercapacitorsinparallelwitha 22 μF, 3 m Ω ceramicare chosen tomeet thetargetdesignspecifications. INPUT CAPACITORS The inputcapacitorsfora buck regulatorareused tosmooth thelargecurrentpulsesdrawn by theinductorand loadwhen thehigh-sideMOSFET ison.Due tothislargeac stress,inputcapacitorsareusuallyselectedon the basisoftheirac rms currentratingratherthanbulkcapacitance.Low ESR isbeneficialbecause itreducesthe power dissipationin the capacitors.Although any of the capacitortypes mentioned in the OUTPUT CAPACITORS sectioncan be used,ceramiccapacitorsare common because oftheirlow seriesresistance.In generaltheinputtoa buck converterdoes notrequireas much bulkcapacitanceas theoutput. The inputcapacitorsshouldbe selectedforrms currentratingand minimum ripplevoltage.The equationforthe rms currentand power lossoftheinputcapacitorina singlephase can be estimatedas: where

• IO (A)istheoutputloadcurrent
• R CIN (Ω)istheseriesresistanceoftheinputcapacitor (33) Sincethemaximum valuesoccuratD = 0.5,a good estimateoftheinputcapacitorrms currentratingina single phase isone-halfofthemaximum outputcurrent. Neglectingthe seriesinductanceof the inputcapacitance,the inputvoltageripplefora singlephase can be estimatedas: (34) By definingthe maximum inputvoltageripple,the minimum requirementforthe inputcapacitancecan be calculatedas: (35) For thedualoutputdesignoperating180° outofphase,thegeneralequationfortheinputcapacitorrms current isapproximatedas: (36) Where theoutputcurrentsareI1,I2and thedutycyclesareD1, D2 respectively.D3 representstheoverlapping effectivedutycycle,whichadds totheRMS current. (37) IfD > 0.5forbothorD < 0.5forboth,theworstcase rms currentoccurswithone outputatfullloadand theother atno load.The maximum rms currentcan be approximatedas: (38)

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C1 = CIN1 R1 = RCIN1 C2 = CIN2 R2 = RCIN2 2.2 x S x fSW x C1 2.2 x S x fSW x C2 ICIN1(RMS) = ICIN(RMS) x R2 2 + X22 ICIN2(RMS) = ICIN(RMS) x R1 2 + X12 X2 | X1 | á = x R LIN + RCIN ZS ZS ZIN ZIN = VIN POUT fS = 2 x S x LIN x CIN 1ZS = LIN C IN ICIN(RMS)MAX | 0.707 x I12 + I22 LM3000 www.ti.com SNVS612B –JULY 2009–REVISED APRIL 2013 IfD > 0.5forone and D < 0.5fortheother,theworstcase rms currentbecomes: (39) In most applicationsforpoint-of-loadpower supplies,the inputvoltageis the outputof anotherswitching converter.Thisoutputoftenhas a lotofbulkcapacitance,whichmay provideadequatedamping. When theconverterisconnectedtoa remoteinputpower sourcethrougha wiringharness,a resonantcircuitis formed by the lineimpedance and the inputcapacitors.Ifstepinputvoltagetransientsare expectednear the maximum ratingoftheLM3000, a carefulevaluationoftheringingand possibleovershootatthedeviceVIN pin shouldbe completed.To minimizeovershootmake C IN > 10 x LIN. The characteristicsourceimpedance and resonantfrequencyare: (40) The converterexhibitsa negativeinputimpedance whichislowestattheminimum inputvoltage: (41) The damping factorfortheinputfilterisgivenby: where

• R LIN istheinputwiringresistance
• R CIN istheseriesresistanceoftheinputcapacitors (42) The termZS /ZIN willalwaysbe negativedue toZIN. When δ = 1,theinputfilteriscriticallydamped. Thismay be difficulttoachievewithpracticalcomponent values. Withδ < 0.2,theinputfilterwillexhibitsignificantringing.Ifδ iszeroornegative,thereisnotenough resistance inthecircuitand theinputfilterwillsustainan oscillation. When operatingnear theminimum inputvoltage,an aluminum electrolyticcapacitoracrossC IN may be needed todamp theinputfora typicalbench testsetup.Any parallelcapacitorshouldbe evaluatedforitsrms current rating.The currentwillsplitbetween theceramicand aluminum capacitorsbased on therelativeimpedance at theswitchingfrequency.Usinga squarewave approximation,therms currentineach capacitorisfoundfrom: (43) InputCapacitorDesign Procedure Ceramic capacitorsare sizedtosupporttherequiredrms current.Aluminum electrolyticcapacitorsare used for damping.Treatingeach phase separately,findtheminimum valuefortheceramiccapacitorfrom: Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:LM3000

2.2 x S x fSW x RCIN2 x CIN1 ICIN(RMS) ICIN2(RMS) | D x (1 ± D) ICIN(RMS) | IO x IO x D x (1 ± D) 'VIN x fSW C IN t LM3000 SNVS612B –JULY 2009–REVISED APRIL 2013 www.ti.com (44) For thedesignexample allowing0.25V inputvoltageripple,theworstcase occursforthe3.3V,8A outputatD = 4.8μF.Findtherms currentratingforeach from: (45) Usingthesame criteria,resultsare4A rms forthe3.3Vphase and 3A rms forthe1.2Vphase.Manufacturerdata for10 μF, 25V, X5R capacitorsina 1206 package allowsfor3A rms witha 20°C temperaturerise.For the designexample,usingtwo ceramiccapacitorsforeach phase willmeet both the inputvoltagerippleand rms currenttarget.Sincetheseriesresistanceisso low atabout5 m Ω percapacitor,a parallelaluminum electrolytic isused fordamping.A good generalruleistomake thedamping capacitoratleastfivetimesthevalueofthe ceramic.By sizingthealuminum such thatitisprimarilyresistiveattheswitchingfrequency,thedesignisgreatly simplifiedsincethe ceramicis primarilyreactive.In thiscase the approximationforthe rms currentin the damping capacitoris: where

• C IN2 isthedamping capacitance
• R CIN2 isitsseriesresistance
• C IN1 istheceramiccapacitance (46) A 150 μF, 50V, 0.18Ω,670 mA capacitorina 10 mm x 10.2mm package ischosen foreach input.Calculated rms currentforthe3.3Vphase is322 mA, with242 mA calculatedforthe1.2Vphase. CURRENT LIMIT For thedesignexample,thedesiredcurrentlimitsetpointischosen tobe 150% ofthemaximum loadcurrent. To accountforthetoleranceoftheinternalcurrentsourceand allowingR DS(on) = 4 m Ω forthelow-sideMOSFET atelevatedtemperature,a targetof23A isused forthe1.2V output,with13A forthe3.3V output.Followingthe equationfromtheCURRENT LIMITsectionthevaluesforR LIM are4.64kΩ,1% forthe1.2V outputand 2.67kΩ, 1% forthe3.3Voutput. TRACK Trackingforthedesignexample isconfiguredsuch thatVOUT1 iscontrollingVOUT2 .The dividervaluesaresetso thatbothoutputswillrisetogether,withVOUT2 reachingitsfinalvaluejustbeforeVOUT1 .Followingthemethod in theTRACKING sectionand allowingfora 120 mV offsetbetween FB and TRK, standard1% valuesareselected forR T1 = 10 kΩ and R T2 = 35.7kΩ. SOFT START To preventover-shoot,the softstarttimeissetto be longerthan the timeitwould taketo charge the output voltageatcurrentlimit.FollowingtheequationsintheSTARTUP sectionforVOUT1 and VOUT2 : tSS1(MIN) = (3.3Vx 242 μF)/(13A -8A) = 160 μs (47) tSS2(MIN) = (1.2Vx 462 μF)/(23A -15A) = 69 μs (48) Choosinga valueofC SS1 = 27 nF,thesoftstarttimeis: tSS1 = (27nF x 0.6V)/8.5μA = 1.9ms (49) To ensurethatVOUT2 tracksVOUT1 ,tSS2 issetattwo-thirdsoftSS1 by making C SS2 = 18 nF. VDD, VDR and VCB CAPACITORS VDD isused as thesupplyfortheinternalcontroland logiccircuitry.A 1 μF ceramiccapacitorprovidessufficient filteringforVDD.

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Ð + + R COMP C COMP C HF A R S = RDS(on) L R L C O1 R C1 C O2 R O gm C FF R FBB R FBT COMP PWM FB VOUT LG HG R C2 DRIVERS 0.75V Clamped to 0.5V min 3V max - + VREF EA_GND VSW PGND Q G_HI 'VVCB C BOOT t Q G_HI + QG_LO 'VVDR C VDR t LM3000 www.ti.com SNVS612B –JULY 2009–REVISED APRIL 2013 VDR providespower forboth the high-sideand low-sideMOSGET gate drives,and issizedto meet the total gatedrivecurrent.AllowingforΔVVDR = 100 mV ofripple,theminimum valueforC VDR isfoundfrom: (50) UsingQ G_HI = 15 nC and Q G_LO = 30 nC witha 5V gatedrive,theminimum valueforC VDR = 0.45μF. VCB providespower forthehigh-sidegatedrive,and issizedtomeet therequiredgatedrivecurrent.Allowing forΔVVCB = 100 mV ofripple,theminimum valueforC BOOT isfoundfrom: (51) To use theminimum number ofdifferentcomponents,C VDR and C BOOT arealsoselectedas 1 μF ceramicforthe designexample. CONTROL LOOP COMPENSATION The LM3000 uses emulatedpeak current-modePWM controltocorrectchanges inoutputvoltagedue tolineand loadtransients.Thisuniquearchitecturecombines thefastlinetransientresponseofpeak current-modecontrol withtheabilitytoregulateatverylow dutycycles.Inordertofacilitatetheuse ofMOSFET R DS(on) sensing,the controlramp issetby theenablevoltageand a resistortotheenablepin.Thisstabilizesthemodulatorgainfrom variationsinMOSFET resistanceovertemperature,providinga robustdesignsolution. The controlloop is comprisedof two parts.The firstis the power stage,which consistsof the duty cycle modulator,outputfilterand load.The second partistheerroramplifier,which isa transconductanceamplifier witha typicalgm of1400 μmho (or1400 μS).Figure29 shows thepower stageand erroramplifiercomponents. Figure29. Power Stage and ErrorAmplifier The power stagetransferfunction(alsocalledthecontrol-to-outputtransferfunction)ina buck convertercan be writtenas: Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:LM3000

3.2k SAMPLE VSW 104k 104k CS AMPLIFIER TO RAMP GENERATOR 11k 2.6 pF 5.6 pF PGND 0.75V 3.2k 31k 15.5k11k 20 pF R i = A x RS T = 1 fSW D = VO VIN KD = 1 + Km x Ri R O AVP = Km KD öZ =C O x RC Km = (D ± 0.5) x Ri xT L + KSL öP x QP = + CO x (Km x Ri + RC ) KD L R O öP 2 =L x CO KD vO vC = AVP x 1 + s öZ 1 + s öP x QP öP LM3000 SNVS612B –JULY 2009–REVISED APRIL 2013 www.ti.com (52) Where: (53) With: (54) For theemulatedpeak current-modecontrol,Km isthedc modulatorgainand R iisthecurrent-sensegain.KSL is theproportionalslopecompensation,whichissetby theenableresistorR EN and enablevoltageVEN . Figure30 shows a more detailedview of the currentsense amplifier,which includesa threestage filterfor increasednoiseimmunity.The effectivegainand phase are shown inFigure31 and Figure32.The equivalent currentsense gainA = 7. Figure30. CurrentSense Amplifierand Filter

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VEN ± 0.75 IEN = R EN + 2000 KSL = ISL x KSW IEN ISL = 8.05 éA KSW = 1 + fSW 3400000 LM3000 www.ti.com SNVS612B –JULY 2009–REVISED APRIL 2013 Figure31.CurrentSense AmplifierGain Figure32.CurrentSense AmplifierPhase A relativelyhighvalueofslopecompensatingramp isused tostabilizethegain.Thisminimizestheeffectofthe currentsense filteron the controlloopand swamps out the need fora sampling-gainterm.When designing withintherecommended operatingrange,thereisno tendencytowardsub-harmonicoscillation.The proportional slopecompensationisdefinedas: (55) ISL isthe internalcurrentsourcescalefactor,KSW isthe switchingfrequencycorrectionfactorand IEN isthe externalenablecurrent.The recommended rangeforIEN is40 μA to160 μA. WithVEN = 5V, thiscorrespondsto a rangeforR EN of25 kΩ to100 kΩ.For operationbelow 4.2V input,themaximum enablecurrentislimited,as shown inFigure33.At theminimum inputof3.3V,a valueof80 μA maximum correspondstoR EN = 50 kΩ with VEN = 5V. The minimum enablecurrentissetby the enablebiascircuitto ensure properturn-onabove the threshold.A minimum enablevoltageof 3V isrecommended to keep the temperaturecoefficientof the 0.75V internalVBE frombecoming a significanterrorterm. Figure33. Maximum Enable Currentvs.InputVoltage Typicalfrequencyresponseofthegainand thephase forthepower stageareshown inFigure34 and Figure35. ItisdesignedforVIN = 12V, VOUT = 3.3V,IOUT = 8A, VEN = 5V and a switchingfrequencyof500 kHz.The power stagecomponent valuesare: Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:LM3000

4.2k C BW COMP FB + 12.75k 10 pF PWM gm R EA COMPF 15M 22 pF 3 pF 5 pF EA_GND VREF + COMP FB + PWM gm 15M EA_GND LM3000 SNVS612B –JULY 2009–REVISED APRIL 2013 www.ti.com L = 2.7μH, R L = 3.4m Ω,C O1 = 220 μF,R C1 = 15 m Ω,C O2 = 22 μF,R C2 = 3 m Ω,R O = VOUT /IOUT = 0.41Ω,R S = R DS(on) = 4 m Ω and R EN = 43 kΩ. Figure34.Power Stage Gain Figure35.Power Stage Phase The effectivetotalPWM ramp heightiscontrolledby R EN .HigherR EN createsa higherramp voltage,providing more noiseimmunityand lessvariationinthe modulatorgainover temperature.Lower R EN requireslessR C (outputcapacitorESR) forthedesiredphase marginand a more idealcurrent-modebehavior. Figure36 shows thetransconductanceamplifiernetwork,whichtakestheoutputimpedance oftheamplifierand theinternalfilterintoaccount.To simplifytheanalysis,the12.75kΩ and 10 pF internalfilterisabsorbedintothe transconductanceamplifier.Thisproducesan equivalentR EA = 15 M Ω and C BW = 22 pF foran effective10 MHz unitygainbandwidth. Figure36. EquivalentTransconductance Amplifierand COMP Filter

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R FBT = RFBB x VOUT VREF - 1 AVM = KFB x gm x RCOMP öFP = 1 C FF x KFB x RFBT KHF = 1 + C HF + CBW C COMP öHF =(CHF + CBW ) x CCOMP x RCOMP C HF + CBW + CCOMP öZEA = 1 C COMP x RCOMP öFZ = 1 C FF x RFBT R FBB KFB = R FBB + RFBT vC vO AVM KHF - x 1 + s öFZ 1 + s öFP 1 + s öHF x 1 + s öZEA LM3000 www.ti.com SNVS612B –JULY 2009–REVISED APRIL 2013 Figure37.Transconductance AmplifierOpen Loop Figure38.Transconductance AmplifierOpen Loop Gain Phase Assuming a poleattheorigin,thesimplifiedequationfortheerroramplifiertransferfunctioncan be writtenin termsofthemid-bandgainas: (56) Where: (57) Ingeneral,thegoalofthecompensationcircuitistogivehighdc gain,a bandwidththatisbetween one-fifthand one-tenthoftheswitchingfrequency,and atleast45° ofphase margin. ControlLoop Design Procedure Once the power stage designiscomplete,the power stage components are used to determinethe proper frequencycompensation.By equatingthe power stagetransferfunctionto the erroramplifiertransferfunction termby term,thecontrolloopdesignproceduretargetsan idealsingle-polesystemresponse. The compensationcomponents willscalefrom thefeedbackdividerratioand selectionofthebottomfeedback dividerresistor.A maximum valueforthedividercurrentistypicallysetat1 mA. Using a dividercurrentof200 μA willallowfora reasonablerange ofvalues.For thebottomfeedbackresistorR FBB = VREF /200 μA = 3 kΩ. Choosinga standard1% valueof2.94kΩ,thetopfeedbackresistorisfoundfrom: (58) ForVOUT = 3.3Vand VREF = 0.6V,R FBT = 13.2kΩ. Based on thepreviouslydefinedpower stagevalues,calculategeneralterms: Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:LM3000

VEN ± 0.75 R EN = IEN - 2000 IEN = ISL x KSW x x KFB R C - 1 R O + RC xL C O - 1KFB R i x R C R O x KFB 1 - R1 = RC1C1 = CO1 R2 = RC2C2 = CO2 R C = Z x COS(A) X2 = 1 öC x C2X1 = 1 öC x C1 öC x Z x SIN(A)C O = 1 A = TAN-1 + TAN-1 X2 R2 - TAN-1 X1 + X2 R1 + R2 R1 2 + X12 R2 2 + X22x Z = öBW = 2 x S x fBW öC = 2 x S x fC öSW = 2 x S x fSW R FBB R FBB R FBT+ R i = A x RS T = 1 fSW D = VO VIN KSW = 1 + fSW 3400000 KFB = LM3000 SNVS612B –JULY 2009–REVISED APRIL 2013 www.ti.com (59) Choose a targetcrossoverfrequencyfC greaterthan the minimum controlloopbandwidthfrom the OUTPUT INDUCTORS section.Thisistypicallysetbetween 1/10and 1/5oftheswitchingfrequency. (60) ChoosingfC = 100 kHz forthedesignexample ωC = 628 krad/sec.The switchingfrequencyωSW = 3.14Mrad/sec and theerroramplifierbandwidthωBW = 62.8Mrad/sec. CalculatetheparallelequivalentC O and R C atthetargetcrossoverfrequency: (61) 183 μF and R C = 11.9m Ω. Findtheoptimalvalueoftheenablecurrent: (62) IfIEN isnotwithintherangeof40μA to160μA use eithertheminimum ormaximum limit.FindR EN from: (63) Calculateothergeneralterms:

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C BW = gm öBW C FF = C O x RC KFB x RFBT C HF = gm x Km x RC öC x öSW x L- CBW R COMP = KFB x L KD x RC x CCOMP C COMP = KFB x gm x Km öC x KD - (CHF + CBW ) R C = KFB x L Km x Ri x CO Km = (D ± 0.5) x Ri xT L + KSL KSL = ISL x KSW IEN KD = 1 + Km x Ri R O LM3000 www.ti.com SNVS612B –JULY 2009–REVISED APRIL 2013 (64) Forthedesignexample KSL = 0.0978,Km = 10.7and KD = 1.73. Iftheenableresistorhas been adjustedfrom thenominalvaluetoprovidemore noiseimmunityor tomeet the minimum inputvoltagelimit,calculatetheoptimalvalueofR C .The minimum valueofR C tomaintainadequate phase marginforstabilityisabouthalfthisvalue. (65) Checkingforthedesignexample R C = 9.1m Ω. Calculatethecompensationcomponents: (66) For thedesignexample,thecalculatedvaluesareC BW = 22 pF,C FF = 904 pF,C HF = 11 pF,C COMP = 2505 pF and R COMP = 9523Ω. UsingstandardvaluesofC FF = 820 pF,C HF = 10 pF,C COMP = 2200 pF and R COMP = 10 kΩ,theerroramplifier plotsofgainand phase areshown inFigure39 and Figure40. Figure39.ErrorAmplifierGain Figure40.ErrorAmplifierPhase Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:LM3000

K = POUT POUT + PTOTAL_LOSS LM3000 SNVS612B –JULY 2009–REVISED APRIL 2013 www.ti.com The completecontrollooptransferfunctionisequaltotheproductofthepower stagetransferfunctionand error amplifiertransferfunction.For theBode plots,theoverallloopgainistheequaltothesum indB and theoverall phase isequaltothesum indegrees.Resultsareshown inFigure41 and Figure42.The crossoverfrequencyis 100 kHz witha phase marginof75°. Figure41.ControlLoop Gain Figure42.ControlLoop Phase Compensator designforthe1.2V outputissimilar.With VREF = 0.6V,thefeedbackdividerresistorsare chosen as R FBB = R FBT = 22.6 kΩ. This resultsin a dividercurrentof about 25 μA, which isconsideredto be the minimum acceptablelevel.WithVEN = 5V, theneareststandardvaluetomeet theoptimalenablecurrentisR EN = 62 kΩ.For a targetcrossoverfrequencyof100 kHz,standardvaluesareC FF = 220 pF,C HF = 10 pF,C COMP = 2200 pF and R COMP = 10 kΩ. For thesmall-signalanalysis,itisassumed thatthecontrolvoltageattheCOMP pinisdc.Inpractice,theoutput ripplevoltageisamplifiedby theerroramplifiergainattheswitchingfrequency,whichappearsattheCOMP pin addingto the controlramp. Thistendsto reduce the modulatorgain,which may lowerthe actualcontrolloop crossoverfrequency. Efficiencyand Thermal Considerations The totalpower dissipatedinthepower components can be obtainedby addingtogetherthelossas mentioned intheMOSFET, inputcapacitor,outputcapacitorand outputinductorsections. The efficiencyisdefinedas: (67) The highestpower dissipatingcomponents are thepower MOSFETs. The easiestway todeterminethepower dissipatedintheMOSFETs istomeasure thetotalconversionloss(PIN -POUT ),thensubtractthepower lossin thecapacitors,inductorsand LM3000. The resultingpower lossisprimarilyintheswitchingMOSFETs. Selecting MOSFETs withexposed pads willaidthepower dissipationofthesedevices.CarefulattentiontoR DS(on) athigh temperatureshouldbe observed. LM3000 OPERATING LOSS This term accountsforthe currentdrawn at the VIN pin,used fordrivingthe logiccircuitryand the power MOSFETs. For theLM3000, thiscurrentisequaltothesteadystateoperatingcurrentIq plustheMOSFET gate chargecurrentIGC ,whichisdefinedas: IGC = (QG_HI + Q G_LO )x fSW (68) PD = VIN x (Iq + IGC ) where

• PD representsthetotalpower dissipatedintheLM3000 (69)

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www.ti.com SNVS612B –JULY 2009–REVISED APRIL 2013 Iq isabout5 mA fromtheElectricalCharacteristicstable.The LM3000 has an exposed thermalpad toaidpower dissipation. Layout Considerations To producean optimalpower solutionwitha switchingconverter,as much caremust be takenwiththelayout and designoftheprintedcircuitboard as withthecomponent selection.The followingare severalguidelinesto aidincreatinga good layout. KELVIN TRACES FOR GATE DRIVE AND SENSE LINES The HG and SW pinsprovidethegatedriveand returnforthehigh-sideMOSFET. LikewisetheLG and PGND pinsprovidethegatedriveand returnforthelow-sideMOSFET. These linesshouldrunas parallelpairstoeach MOSFET, beingconnectedas closeas possibletotherespectiveMOSFET gateand source.Althoughitmay be difficultina compact design,theselinesshouldstayaway from the outputinductorifpossible,to avoidstray coupling. The EA_GND pinsshouldalsobe connectedwitha separateKelvintrace,runningfromtheoutputgroundsense point.The sense output,which isconnectingtothetopofthefeedbackresistordivider,shouldalsorun witha dedicatedKelvintracetogetherwiththe EA_GND. Keep these linesaway from the switchnode and output inductortoavoidstraycoupling.Ifpossible,theFB and EA_GND tracesshouldbe shieldedfromtheswitchnode by groundplanes.Ifnecessary,thefeedbackdividerimpedance may be loweredtoimprovenoiseimmunity. SEPARATE PGND AND SGND Good layouttechniquesincludea dedicatedsignalground plane,usuallyon an internallayeradjacentto the LM3000 and signalcomponent sideoftheboard.Signallevelcomponents likethecompensationand feedback resistorsshouldbe connectedtothisinternalplane.The SGND pinshouldconnectdirectlytotheDAP, withvias fromtheDAP tothesignalgroundplane.Separatepower groundplaneareasforeach phase shouldbe made on thepower component sideoftheboard,as wellas otherlayers.Thisallowsseparatelinesforeach PGND pinto connecttoitsrespectivepower groundplaneareaateach low-sideMOSFET source.The signalgroundplaneis thenconnectedtoa quietpointon each power groundplanearea.These connectionsaretypicallymade atthe common input/outputpower terminalsor capacitorreturns.An equivalentschematicrepresentationisshown in theTypicalApplicationSchematicofFigure43. MINIMIZE THE SWITCH NODE The copperarea thatconnectsthepower MOSFETs and outputinductortogetherradiatesmore EMI as itgets larger.Use justenough copper to givelow impedance forthe switchingcurrentsand provideadequate heat spreadingfortheMOSFETs. LOW IMPEDANCE POWER PATH In a buck regulatorthe primaryswitchingloop consistsof the inputcapacitorconnectionto the MOSFETs. Minimizingthe area of thisloop reduces the strayinductance,which minimizesnoise and possibleerratic operation.The ceramicinputcapacitorsshouldbe placedas closeas possibletotheMOSFETs, withtheVIN sideofthecapacitorsconnecteddirectlytothehigh-sideMOSFET drain,and thePGND sideofthecapacitors connectedas closeas possibletothelow-sidesource.The completepower pathincludestheinputcapacitors, power MOSFETs, outputinductor,and outputcapacitors.Keep thesecomponents on thesame sideoftheboard and connectthem withthicktracesorcopperplanes.Avoidconnectingthesecomponents throughviaswhenever possible,as viasadd inductanceand resistance.In general,the power components should be kept close together,minimizingthecircuitboardlosses. Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:LM3000

EA1_GND FB1 COMP1 PGOOD1 TRK1 EN1 SS1 HG2 VCB2 VSW2 ILIM2 LG2 PGND2 EA2_GND PGOOD2 TRK2 EN2 SS2 FREQ/ SYNCCLKOUTSGND COMP2 VDR VIN VDD FB2 C FF2 C HF2 R LIM2 C BOOT2 R FBT2 R FBB2 C OUT2 Q 4 Q 3 D 4 C COMP2 R COMP2 VDDPGOOD2 R PG2 R LIM1 C BOOT1 R FBT1 R FBB1 C OUT1 Q 2 Q 1 D 3 C COMP1 R COMP1 VDD PGOOD1R PG1 C HF1 C FF1 VDD R EN1 VEN1 (5V) VEN2 (5V) R EN2 VOUT1 R T1 R T2 C SS1 C SS2 R FRQCLKOUT SYNC C SYNC R CBT PGND1 PGND2 SGND VOUT1 3.3V, 8A VOUT2 1.2V, 15A VIN 6V TO 18V C IN1 C IN2D 1A D 1B VDD VDD VDR VDR C VDR2C VDR1 C VDD PGND1 PGND2GND1 GND2 PGND1 PGND2 GND1 GND2 LM3000 SNVS612B –JULY 2009–REVISED APRIL 2013 www.ti.com TypicalApplication Figure43. TypicalApplicationSchematic

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REVISION HISTORY

Changes from RevisionA (April2013)toRevisionB Page Copyright© 2009–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:LM3000

www.ti.com 8-Oct-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM3000SQ/NOPB ACTIVE WQFN RTV 32 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 3000 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 8-Oct-2015 Addendum-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM3000SQ/NOPB WQFN RTV 32 1000 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 Pack Materials-Page 2

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