M3000

M3000 UTC | Alldatasheet

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UNISONIC TECHNOLOGIES CO., LTD M3000 Preliminary LINEAR INTEGRATED CIRCUIT w w w . u n i s o n i c . c o m . t w 1 of 6 Copyright © 2010 Unisonic Technologies Co., Ltd QW-R502-473.a PIR INFRARED REMOTE CONTROL CIRCUIT „ DESCRIPTION The M3000 is a passive infra-red controller using analog mixing digital design technique and is manufactured by CMOS process. The M3000 needs only few external components in application circuit. It can be applied in controll er of light, electric switching, burglar alarm, and so on. „ FEATURES * Low Power CMOS Technology * CMOS High Input Impedance Operational Amplifiers * Bi-Directional Level Detector / Excellent noise Immunity * Built-in Power up Disable & Output Pulse Control Logic * Dual Mode : Retriggerable & Non-Retriggerable „ ORDERING INFORMATION Ordering Number Package Packing M3000G-S16-R SOP-16 Tape Reel

UNISONIC TECHNOLOGIES CO., LTD 2 of 6 www.unisonic.com.tw Q W - R 5 0 2 - 4 7 3 . a „ PIN CONFIGURATIONS A VOUT RR1 RC1 RR2 RC2 1OUT 1IN- 1IN+ 2IN- 2OUT V DD VSS IB VC 8 9VRF/RESET „ PIN DESCRIPTIONS PIN NO. PIN NAME I/O PIN DESCRIPTION

1 A I Retriggerable & non-retriggerable mode select

2 V OUT O Detector output pin (active high)

3 RR1 Output pulse width control (Tx)

4 RC1 Output pulse width control (Tx)

5 RC2 Trigger inhibit control (Ti)

6 RR2 Trigger inhibit control (Ti)

7 V SS Ground

8 VRF I RESET & voltage reference input

(normally high. Low=reset)

9 VC I Trigger disable input

(VC>0.2Vdd=enable; VC<0.2Vdd=disable)

10 IB Op-amp input bias current setting

11 V DD Supply voltage

12 2OUT O 2 nd stage Op-amp output 13 2IN- I 2 nd stage Op-amp inverting input 14 1IN+ I 1 st stage Op-amp non-inverting input 15 1IN- I 1 st stage Op-amp inverting input 16 1OUT O 1 st stage Op-amp output

UNISONIC TECHNOLOGIES CO., LTD 3 of 6 www.unisonic.com.tw Q W - R 5 0 2 - 4 7 3 . a „ BLOCK DIAGRAM STATES CONTROL Tx Ti VH VM VL VR VR VH VL VM VS VDD IB VOUT RR1 RC1 RR2 RC2 Vss A 1IN+ 1IN- 1OUT 2IN- 2OUT VC VREF/RESET OP1 OP2 COP1 COP2 COP3

UNISONIC TECHNOLOGIES CO., LTD 4 of 6 www.unisonic.com.tw Q W - R 5 0 2 - 4 7 3 . a „ ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATINGS UNIT DC Supply Voltage V DD -0.3~6.0 V Input/ Output Voltage V IN /VOUT V SS-0.3~VDD+0.3 V Max. Output Current (VDD=5.0V) IOUT 10 mA Operating Temperature TOPR -20~+70 °C Storage Temperature TSTG -40~+125 °C „ DC ELECTRICAL CHARACTERISTICS (TA =+25°C,unless otherwise specified) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DC Supply Voltage V DD 3 5 V VDD=3V 50 Average Supply Current I DD No Load VDD=5V 100 μA Op-Amp Input Offset Voltage V OS VDD=5V 50 mV Op-Amp Input Offset Current I OS VDD=5V 50 nA Op-Amp Gain A VO VDD=5V, RL=1.5MΩ 60 dB Op-Amp Common Mode Rejection Ration CMRR VDD=5V, RL=1.5MΩ 60 dB Op-Amp HIGH Level Output Voltage V YH 4.25 V Op-Amp LOW Level Output Voltage V YL VDD=5V, RL=500KΩ connect to 1/2VDD 0.75 V VC High Level Input Voltage V RH 1.1 V VC Low Level Input Voltage V RL VRF＝VDD=5V 0.9 V VOUT High Level Output Voltage V OH V DD=5V, IOH=0.5mA 4 V VOUT Low Level Output Voltage V OL V DD=5V, IOH=0.1mA 0.4 V Pin A High Level Input Voltage V AH V DD=5V 3.5 V Pin A Low Level Input Voltage V AL V DD=5V 1.5 V

UNISONIC TECHNOLOGIES CO., LTD 5 of 6 www.unisonic.com.tw Q W - R 5 0 2 - 4 7 3 . a „ FUNCTIONAL DESCRIPTIONS 1. Re-Triggerable Mode Re-Triggerable Waveform Operational amplifier OP1 composed sensor signal pre-processing circuit. The amplified signal coupled to the operational amplifier OP2, and elevated DC level to VM (≈0.5VDD), The output signal V2 input to Bi-directional level detector(COP1&COP2), detected the effective signal Vs. As the VH≈0.7VDD, VL≈0.3VDD, while VDD=5V, it is immune to the ±1V noise interference and can improve system reliability. COP3 is a condition comparator. When the input voltage Vc<VR(≈0.2VDD), COP3 output is low, it disabled the Vs transmission to State Control circuit; When Vc>VR, COP3 output is high, chip access to extension time period. When pin A connect to "0", any change of V2 have been ignored until the end of Tx period, which called non-retriggerable mode. When the Tx period ended, Vo jump back to the low level, chip access to the lock period Ti. During the Ti period, any changes of V2 can not make Vo jumping to valid state (high level), it can inhibit a variety of interference when the load changed. 2. Non-Retriggerable mode VS A VC VOUT VH VL Tx Ti Tx Ti Non-Retriggerable Waveform During the time of Vc="0", A="0"，signal Vs can not trigger Vo to a valid state; When Vc="1", A="1", Vs can repeatable trigger Vo to the valid state, and keep the state in Tx period. In the Tx period, if Vs jump to "1", then Vo extend to an another Tx; if Vs keep "1" state, Vo maintains the valid state; if Vs keep "0 "state, after the period of Tx, Vo change to invalid state, and in the Ti time, any change of Vs can not trigger Vo to a valid state.

UNISONIC TECHNOLOGIES CO., LTD 6 of 6 www.unisonic.com.tw Q W - R 5 0 2 - 4 7 3 . a „ TYPICAL APPLICATIONS CIRCUIT 105 473 NOTE: R3 is a light dependent resistor which has low resistance under strong ambient light. This cause the detector to be operational only when the detection area is sufficient dark. UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.