M29W008ET STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 43
Technical content
Datasheet sections
- 1 Summary description
- 2 Signal descriptions
- 2.1 Address Inputs (A0-A19)
- 2.2 Data Input/Outputs (DQ0-DQ7)
- 2.3 Chip Enable (E)
- 2.4 Output Enable (G)
- 2.5 Write Enable (W)
- 2.6 Ready/Busy Output (RB)
- 2.7 Reset/Block Temporary Unprotect Input (RP)
- 2.9 V SS Ground
- 3 Bus Operations
- 3.1 Standard bus operations
- 3.1.1 Bus Read
- 3.1.2 Bus Write
- 3.1.3 Output Disable
- 3.1.4 Standby
- 3.1.5 Automatic Standby
- 3.2 Special bus operations
- 3.2.1 Read Electronic Signature
- 3.2.2 Block Protection and Unprotection
- 4 Command interface
- 4.1 Read/Reset command
- 4.2 Auto Select command
- 4.3 Program command
- 4.4 Unlock Bypass command
- 4.5 Unlock Bypass Program command
- 4.6 Unlock Bypass Reset command
- 4.7 Block Erase command
8 Mbit (1Mb x 8, Boot Block)
Figure 1. Package
M29W008ET, M29W008EB
Table 14. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data . . . 32
1 Summary description M29W008ET, M29W008EB
1 Summary description
standard programming equipment. temporarily suspended in order to read from or program in blocks that are not being erased. Each block can be programmed and erased over 100,000 cycles. from modifying the memory. All previously protected blocks can be temporarily unprotected. specifications are available at: www.st.com. The device is offered in package and supplied with all the bits erased (set to ’1’). Table 1. Signal Names
Figure 4. Block Addresses (Top Boot Block)
64 KByte Blocks
64 KByte MAIN BLOCK
64 KByte MAIN BLOCK4FFFFh
16 KByte BOOT BLOCK
8 KByte PARAMETER BLOCK
32 KByte MAIN BLOCK
Figure 5. Block Addresses (Bottom Boot Block)
2 Signal descriptions M29W008ET, M29W008EB
2 Signal descriptions
See Figure 2: Logic diagram and Table 1: Signal Names, for a brief overview of the signals connected to this device.
2.1 Address Inputs (A0-A19)
The address inputs for the memory array are latched during a Bus Write operation on the falling edge of Chip Enable, E or Write Enable, W. When A9 is raised to VID, either a Read Electronic Signature Manufacturer or Device Code, Block Protection Status or a Write Block Protection or Block Unprotection is enabled depending on the combination of levels on A0, A1 A6, A12 and A15.
2.2 Data Input/Outputs (DQ0-DQ7)
During Bus Write operations, the Data Inputs/Outputs input the data to be programmed in the memory array or a command to be written to the Command Interface. Both are latched on the rising edge of Chip Enable, E or Write Enable, W. The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation, the Electronic Signature (Manufacturer or Device codes), the Block Protection Status or the Data Polling bit (DQ7), Toggle Bits (DQ6) and DQ2), Error bit (DQ5) or Erase Timer bit (DQ3) of the Status Register. Outputs are valid when Chip Enable, E and Output Enable, G are active. The output is high impedance when the chip is deselected or the outputs are disabled and when RP is Low.
2.3 Chip Enable (E)
The Chip Enable, E, activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is High, VIH, the memory is deselected and the power consumption is reduced to the Standby level. The Chip Enable, E, can also be used to control Write operations to the command register and to the memory array, while W remains Low. The Chip Enable must be forced to VID during Block Unprotection operations.
2.4 Output Enable (G )
The Output Enable, G, gates the outputs through the data buffers during a Bus Read operation. When G is High, VIH, the outputs are high impedance. G must be forced to VID during Block Protection and Unprotection operations.
2.5 Write Enable (W)
This Write Enable, W, controls write operations of the memory’s Command Interface.
M29W008ET, M29W008EB 2 Signal descriptions
2.6 Ready/Busy Output (RB )
The Ready/Busy pin is an open-drain output that can be used to identify when the memory array can be read. Ready/Busy is high impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high impedance. See Table 13: Reset/Block Temporary Unprotect AC Characteristics and Figure 13: Reset/Block Temporary Unprotect AC Waveforms. During Program or Erase operations Ready/Busy is Low, VOL . Ready/Busy will remain Low during Read/Reset commands or Hardware Resets until the memory is ready to enter Read mode.
2.7 Reset/Block Temporary Unprotect Input (RP)
The Reset/Block Temporary Unprotect input, RP , can be used to apply a Hardware Reset to the memory or to temporarily unprotect all blocks that have been previously protected. A Hardware Reset is achieved by holding RP Low, VIL for at least tPLPX . After Reset/Block Temporary Unprotect goes High, VIH, if the device is in Read or Standby mode, it will be ready for new operations tPHEL after the rising edge of RP. If the device is in Erase, Erase Suspend or Program mode, the Hardware Reset will last tPLYH during which the RB signal will be held at VIL. The end of the memory Hardware Reset will be indicated by the rising edge of RB. A Hardware Reset during an Erase or Program operation will corrupt the data being programmed or the blocks being erased. See Table 13: Reset/Block Temporary Unprotect AC Characteristics and Figure 13: Reset/Block Temporary Unprotect AC Waveforms. Holding RP at VID will temporarily unprotect the previously protected blocks in the memory. Program and Erase operations on all blocks will be possible. The transition of RP from VIH to VID must slower than tPHPHH . When RP is returned from VID to VIH all blocks temporarily unprotected will be again protected.
2.8 V CC Supply Voltage
The power supply for all operations (Read, Program and Erase). A 0.1µF capacitor should be connected between the V CC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, I CC3
2.9 V SS Ground
VSS is the reference for all voltage measurements.
3 Bus Operations M29W008ET, M29W008EB
3 Bus Operations
There are 5 standard bus operations that control the device. These are Bus Read, us Write, Output Disable, Standby and Automatic Standby. See Table 2: Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect the bus operations.
3.1 Standard bus operations
3.1.1 Bus Read
Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register or the Block Protection Status. Both Chip Enable E and Output Enable G must be Low in order to read the output of the memory. A new Bus Read operation is initiated either on the falling edge of Chip Enable, E, or on any address transition with E at VIL. See Figure 10: Read Mode AC Waveforms, and Table 10: Read AC Characteristics for details of the timing requirements.
3.1.2 Bus Write
Bus Write operations are used to write to the Command Interface or to latch input data to be programmed. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V IH, during the whole Bus Write operation. See Figures 11 and 12, Write AC Waveforms and Tables 11 and 12, Write AC Characteristics, for details of the timing requirements.
3.1.3 Output Disable
The data outputs are high impedance when the Output Enable G is High with Write Enable W High.
3.1.4 Standby
The memory is in Standby mode when Chip Enable, E, is High and the Program/Erase Controller is idle. The Supply Current is reduced to the Standby Supply Current, ICC2 , and the outputs are high impedance, independent of the Output Enable G or Write Enable W inputs.
3.1.5 Automatic Standby
If CMOS levels (VCC ± 0.2V) are used to drive the bus and if the bus is inactive (no address transition, E = VIL) during 150ns or more, the memory automatically enters a Automatic Standby mode where the Supply Current is reduced to the Standby Supply Current, ICC2 . The Inputs/Outputs will still output data if a Bus Read operation is in progress.
3.2 Special bus operations
3.2.1 Read Electronic Signature
interface to the characteristics of the M29W008E. Operations or by issuing an Auto Select command (see Section 4.2: Auto Select command).
3.2.2 Block Protection and Unprotection
programming equipment. Protected blocks can be unprotected to allow data to be changed. Table 2. Bus Operations
4 Command interface M29W008ET, M29W008EB
4 Command interface
All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. All commands start with two coded cycles which unlock the Command Interface. Seven commands are available: Read/Reset, Auto Select (to read the Electronic Signature and the Block Protection Status), Program, Block Erase, Chip Erase, Erase Suspend and Erase Resume (see Table 3: Commands).
4.1 Read/Reset command
The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM, unless otherwise stated. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. The Read/Reset Command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to read mode. Once the program or erase operation has started the Read/Reset command is no longer accepted. The Read/Reset command will not abort an Erase operation when issued while in Erase Suspend.
4.2 Auto Select command
The Auto Select command is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until another command is issued. From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, and A13-A19 specifying the address of the block. The other address bits may be set to either VIL or VIH. If the addressed block is protected then 01h is output on Data Inputs/ Outputs DQ0-DQ7, otherwise 00h is output.
4.3 Program command
The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data and starts the Program/Erase Controller. If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given.
M29W008ET, M29W008EB 4 Command interface During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 4: Program, Erase Times and Program, Erase Endurance Cycles. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See Section 5: Status register for more details. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.
4.4 Unlock Bypass command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode.
4.5 Unlock Bypass Program command
The Unlock Bypass Program command can be used to program one address in memory at a time. The command requires two Bus Write operations, the final write operation latches the address and data and starts the Program/Erase Controller. The Program operation using the Unlock Bypass Program command behaves identically to the Program operation using the Program command. A protected block cannot be programmed; the operation cannot be aborted and the Status Register is read. Errors must be reset using the Read/Reset command, which leaves the device in Unlock Bypass Mode. See the Program command for details on the behavior.
4.6 Unlock Bypass Reset command
The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Read/Reset command does not exit from Unlock Bypass Mode.
4.7 Block Erase command
The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller about 50µs after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more
blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register for details on how to identify if the Program/ Erase Controller has started the Block Erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the Block Erase operation the memory will ignore all commands except the Erase Suspend command. Typical program times are given in Table 4: Program, Erase Times and Program, Erase Endurance Cycles. All Bus Read operations during the Block Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is lost.
4.8 Chip Erase command
The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands. It is not possible to issue any command to abort the operation. Typical program times are given in Table 4: Program, Erase Times and Program, Erase Endurance Cycles. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost.
4.9 Erase Suspend command
The Erase Suspend Command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus Write operation. The Program/Erase Controller will suspend within the Erase Suspend Latency Time after the Erase Suspend Command is issued (see Table 4: Program, Erase Times and Program, Erase
M29W008ET, M29W008EB 4 Command interface Endurance Cycles). Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume Command is issued. It is not possible to select any further blocks to erase after the Erase Resume. During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. If any attempt is made to program in a protected block or in the suspended block then the Program command is ignored and the data remains unchanged. The Status Register is not read and no error condition is given. Reading from blocks that are being erased will output the Status Register. It is also possible to issue the Auto Select, during an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command will be accepted.
4.10 Erase Resume Command
The Erase Resume command must be used to restart the Program/Erase Controller from Erase Suspend. An erase can be suspended and resumed more than once.
Table 3. Commands
- Commands not interpreted in this table will default to read array mode.
- X = Don't Care. PA = Program Address, PD = Program Data, BA = Block Address, AB = Additional Block.
- For Coded cycles address inputs A15-A19 are don't care.
- A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase or Program mode before starting
any new operation (see Table 10: Read AC Characteristics).
- The first cycles of the Read/Reset and Auto Select commands are followed by read operations. Any number of read cycles
can occur after the command cycles. + X F0h Read Memory Array until a new write cycle is initiated.
- Signature Address bits A0, A1, at VIL will output the Manufacturer Code (20h). Address bits A0 at VIH and A1, at VIL will
- Block Protection Address: A0, at VIL, A1 at VIH and A13-A19 within the Block will output the Block Protection status.
- Read Data Polling, Toggle bits or RB until Erase completes.
- Optional, Additional Block (AB) addresses must be entered within the erase time-out delay after last write entry, time-out
Polling or Toggle bit until Erase has completed or is suspended.
- During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.
being erased then Resume Erase.
Table 4. Program, Erase Times and Program, Erase Endurance Cycles
- Typical values measured at room temperature and nominal voltages.
- Sampled, but not 100% tested.
- Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles.
- Maximum value measured at worst case conditions for both temperature and VCC .
5 Status register M29W008ET, M29W008EB
5 Status register
The status of the Program/Erase Controller during command execution is indicated by bit DQ7 (Data Polling bit), Toggle bits DQ6 and DQ2 and Error bits DQ3 and DQ5. Any attempt to read the memory array during Program or Erase command execution will automatically output these five Status Register bits. The Program/Erase Controller automatically sets bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits (DQ0, DQ1 and DQ4) are reserved for future use and should be masked (see Table 5: Status Register Bits).
5.1 Data Polling Bit (DQ7)
The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling Bit is output on DQ7 when the Status Register is read. During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the address just programmed output DQ7, not its complement. During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode. In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the Program/ Erase Controller has suspended the Erase operation. Figure 6: Data Polling Flowchart gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an address within the block being erased.
5.2 Toggle Bit (DQ6)
The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is output on DQ6 when the Status Register is read. During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode. During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has suspended the Erase operation. If any attempt is made to erase a protected block, the operation is aborted, no error is signalled and DQ6 toggles for approximately 100µs. If any attempt is made to program a protected block or a suspended block, the operation is aborted, no error is signalled and DQ6 toggles for approximately 1µs. Figure 7: Data Toggle Flowchart gives an example of how to use the Data Toggle bit.
M29W008ET, M29W008EB 5 Status register
5.3 Error Bit (DQ5)
The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’. One of the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’
5.4 Erase Timer Bit (DQ3)
The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit is set to ’0’ and additional blocks to be erased may be written to the Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is read.
5.5 Alternative Toggle Bit (DQ2)
The Alternative Toggle Bit can be used to monitor the Program/Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory cell data as if in Read mode. After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle Bit does not change if the addressed block has erased correctly.
Table 5. Status Register Bits Note: Unspecified data bits should be ignored. Figure 6. Data Polling Flowchart
Figure 7. Data Toggle Flowchart
6 Maximum rating M29W008ET, M29W008EB
6 Maximum rating
Table 6. Absolute Maximum Ratings
- Compliant with the ST 7191395 specification for Lead-free soldering processes.
- Not exceeding 250°C for more than 30s, and peaking at 260°C.
- V ID and VIO may undershoot to –2V during transition and for less than 20ns during transitions.
7 DC and AC characteristics
Table 7. Operating and AC Measurement Conditions Figure 8. AC Testing Input Output Waveform
7 DC and AC characteristics M29W008ET, M29W008EB
Figure 9. AC Testing Load Circuit Table 8. Device Capacitance Note: Sampled only, not 100% tested. Table 9. DC Characteristics
- Sampled only, not 100% tested.
Figure 10. Read Mode AC Waveforms Table 10. Read AC Characteristics
- Address are latched on the falling edge of W, Data is latched on the rising edge of W.
- Sampled only, not 100% tested.
Figure 11. Write AC Waveforms, W Controlled Table 11. Write AC Characteristics, W Controlled
- Sampled only, not 100% tested.
Figure 12. Write AC Waveforms, E Controlled Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E.
Table 12. Write AC Characteristics, E Controlled
- Sampled only, not 100% tested.
Figure 13. Reset/Block Temporary Unprotect AC Waveforms Table 13. Reset/Block Temporary Unprotect AC Characteristics
- Sampled only, not 100% tested.
8 Package mechanical M29W008ET, M29W008EB
8 Package mechanical
Figure 14. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline Note: Drawing is not to scale. Table 14. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data
9 Part numbering
Table 15. Ordering Information Scheme Devices are shipped from the factory with the memory content bits erased to ’1’. this device, please contact the ST Sales Office nearest to you.
9 Part numbering M29W008ET, M29W008EB
Table 16. Top Boot Block Addresses, M29W008ET Table 17. Bottom Boot Block Addresses, M29W008EB
M29W008ET, M29W008EB 9 Part numbering 9 64 60000h-6FFFFh 8 64 50000h-5FFFFh 7 64 40000h-4FFFFh 6 64 30000h-3FFFFh 5 64 20000h-2FFFFh 4 64 10000h-1FFFFh 3 32 08000h-0FFFFh 2 8 06000h-07FFFh 1 8 04000h-05FFFh 0 16 00000h-03FFFh
Appendix B Block protection Block protection can be used to prevent any operation from modifying the data stored in the Flash. Each Block can be protected individually. Once protected, Program and Erase operations on the block fail to change the data. There are three techniques that can be used to control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP ; this is described in the Signal Descriptions section. Unlike the Command Interface of the Program/Erase Controller, the techniques for protecting and unprotecting blocks change between different Flash memory suppliers. For example, the techniques for AMD parts will not work on STMicroelectronics parts. Care should be taken when changing drivers for one part to work on another.
9.1 Programmer technique
The Programmer technique uses high (VID) voltage levels on some of the bus pins. These cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in Programming Equipment. To protect a block follow the flowchart in Figure 15: Programmer Equipment Block Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the blocks first, then all blocks can be unprotected at the same time. To unprotect the chip follow Figure 16: Programmer Equipment Chip Unprotect Flowchart. Table 18: Programmer Technique Bus Operations, gives a summary of each operation. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing.
9.2 In-System technique
The In-System technique requires a high voltage level on the Reset/Blocks Temporary Unprotect pin, RP . This can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the Flash has been fitted to the system. To protect a block follow the flowchart in Figure 17: In-System Equipment Block Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the blocks first, then all the blocks can be unprotected at the same time. To unprotect the chip follow Figure 18: In- System Equipment Chip Unprotect Flowchart. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not allow the microprocessor to service interrupts that will upset the timing and do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing.
Table 18. Programmer Technique Bus Operations
Figure 15. Programmer Equipment Block Protect Flowchart
Figure 16. Programmer Equipment Chip Unprotect Flowchart
Figure 17. In-System Equipment Block Protect Flowchart
Figure 18. In-System Equipment Chip Unprotect Flowchart
Table 19. Document Revision History 21-Jun-2005 0.1 First Issue.
M29W008ET, M29W008EB Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America