M29W008AT STMICROELECTRONICS | Alldatasheet
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Technical content
8 Mbit (1Mb x8, Boot Block)
Figure 1. Logic Diagram
M29W008AT, M29W008AB Figure 2. TSOP Connections Table 1. Signal Names of 32 Kbytes and fifteen Main Blocks of 64 Kbytes. tions are managed automatically by the P/E.C.
DESCRIPTION
The M29W008A is a non-volatile memory that may be erased electrically at the block or chip level and programmed in-system on a Byte-by-Byte basis using only a single 2.7V to 3.6V V CC supply. For Program and Erase operations the necessary high voltages are generated internally. The device can also be programmed in standard programmers. The array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. Blocks can be protected against pro- graming and erase on programming equipment, and temporarily unprotected to make changes in the application. Each block can be programmed and erased over 100,000 cycles. Instructions for Read/Reset, Auto Select for read- ing the Electronic Signature or Block Protection status, Programming, Block and Chip Erase, Erase Suspend and Resume are written to the de- vice in cycles of commands to a Command Inter- face using standard microprocessor write timings. The device is offered in TSOP40 (10 x 20mm) package.
monitor the progress of the operation. other block, and then resumed. KO , the command interface is reset to Read Array. ing erased, and then resumed. Block protection provides additional data security. temporarily unprotected in the application. tection Verify and Block Temporary Unprotection. quence will reset the device to Read Array mode. Table 2. Absolute Maximum Ratings
- Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
Table 3. Top Boot Block Addresses, Table 4. Bottom Boot Block Addresses,
M29W008AT, M29W008AB SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs (A0-A19).The address inputs for the memory array are latched during a write op- eration on the falling edge of Chip Enable E or Write Enable W. When A9 is raised to VID, either a Read Electronic Signature Manufacturer or Device Code, Block Protection Status or a Write Block Protection or Block Unprotection is enabled de- pending on the combination of levels on A0, A1 A6, A12 and A15. Data Input/Outputs (DQ0-DQ7).The input is data to be programmed in the memory array or a command to be written to the C.I. Both are latched on the rising edge of Chip Enable E or Write En- able W. The output is data from the Memory Array, the Electronic Signature Manufacturer or Device codes, the Block Protection Status or the Status register Data Polling bit DQ7, the Toggle Bits DQ6 and DQ2, the Error bit DQ5 or the Erase Timer bit DQ3. Outputs are valid when Chip Enable E and Output Enable G are active. The output is high im- pedance when the chip is deselected or the out- puts are disabled and when RP is at a Low level. Chip Enable (E).The Chip Enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. E High deselects the memory and reduces the power consumption to the stand-by level. E can also be used to control writing to the command register and to the memo- ry array, while W remains at a low level. The Chip Enable must be forced to VID during the Block Un- protection operation. Output Enable (G).The Output Enable gates the outputs through the data buffers during a read op- eration. When G is High the outputs are High im- pedance. G m u s t b e f o r c e d t o VID level during Block Protection and Unprotection operations. Write Enable (W).This input controls writing to the Command Register and Address and Data latches. Ready/Busy Output (RB ).Ready/Busy is an open-drain output and gives the internal state of the P/E.C. of the device. When RB is Low, the de- vice is Busy with a Program or Erase operation and it will not accept any additional program or erase instructions except the Erase Suspend in- struction. When RB is High, the device is ready for any Read, Program or Erase operation. The RB will also be High when the memory is put in Erase Suspend or Stand-by modes. Reset/Block Temporary Unprotect Input (RP The RP Input provides hardware reset and pro- tected block(s) temporary unprotection functions. Reset of the memory is achieved by pulling RP to VIL for at least tPLPX . When the reset pulse is giv- en, if the memory is in Read or Stand-by modes, it will be available for new operations in tPHEL after the rising edge of RP. If the memory is in Erase, Erase Suspend or Pro- gram modes the reset will take tPLYH during which the RB signal will be held at VIL. The end of the memory reset will be indicated by the rising edge of RB . A hardware reset during an Erase or Pro- gram operation will corrupt the data being pro- grammed or the sector(s) being erased. See Tables 15, 16 and Figure 8. Temporary block unprotection is made by holding RP at VID. In this condition previously protected blocks can be programmed or erased. The transi- tion of RP from VIH to VID must slower than tPH- PHH . (See Tables 17, 18 and Figure 8). When RP is returned from VID to VIH all blocks temporarily unprotected will be again protected. VCC Supply Voltage.The power supply for all operations (Read, Program and Erase). VSS Ground. VSS is the reference for all voltage measurements.
M29W008AT, M29W008AB DEVICE OPERATIONS See Tables 5, 6 and 7. Read. Read operations are used to output the contents of the Memory Array, the Electronic Sig- nature, the Status Register or the Block Protection Status. Both Chip Enable E and Output Enable G must be low in order to read the output of the mem- ory. A new read operation is initiated either on the falling edge of Chip, Enable E, or on any address transition with E at VIL. Write.Write operations are used to give Instruc- tion Commands to the memory or to latch input data to be programmed. A write operation is initi- ated when Chip Enable E is Low and Write Enable W is Low with Output Enable G High. Addresses are latched on the falling edge of W or E whichever occurs last. Commands and Input Data are latched on the rising edge of W or E whichever oc- curs first. Output Disable.The data outputs are high im- pedance when the Output Enable G is High with Write Enable W High. Stand-by. The memory is in stand-by when Chip Enable E is High and the P/E.C. is idle. The power consumption is reduced to the stand-by level and the outputs are high impedance, independent of the Output Enable G or Write Enable W inputs. Automatic Stand-by.After 150ns of bus inactivi- ty (no address transition, E = VIL) and when CMOS levels are driving the addresses, the chip automat- ically enters a pseudo-stand-by mode where con- sumption is reduced to the CMOS stand-by value, while outputs still drive the bus (if G = VIL). Electronic Signature.Two codes identifying the manufacturer and the device can be read from the memory. The manufacturer's code for STMicro- electronics is 20h, the device code is D2h for the M29W008AT (Top Boot) and DCh for the M29W008AB (Bottom Boot). These codes allow programming equipment or applications to auto- matically match their interface to the characteris- tics of the M29W008A. The Electronic Signature is output by a Read operation when the voltage ap- plied to A9 is at V ID and address inputs A1 is Low. The manufacturer code is output when the Ad- dress input A0 is Low and the device code when this input is High. Other Address inputs are ig- nored. The Electronic Signature can also be read, without raising A9 to V ID, by giving the memory the Instruction AS. Block Protection.Each block can be separately protected against Program or Erase on program- ming equipment. Block protection provides addi- tional data security, as it disables all program or erase operations. This mode is activated when both A9 and G are raised to VID and an address in the block is applied on A13-A19. Block protection is initiated on the edge of W falling to VIL. Then af- ter a delay of 100µs, the edge of W rising to VIH ends the protection operations. Block protection verify is achieved by bringing G , E, A0 and A6 to VIL and A1 to VIH, while W is at VIH and A9 at VID. Under these conditions, reading the data output will yield 01h if the block defined by the inputs on A13-A19 is protected. Any attempt to program or erase a protected block will be ignored by the de- vice. Block Temporary Unprotection.Any previously protected block can be temporarily unprotected in order to change stored data. The temporary un- protection mode is activated by bringing RP to VID. During the temporary unprotection mode the pre- viously protected blocks are unprotected. A block can be selected and data can be modified by exe- cuting the Erase or Program instruction with the RP signal held at VID. When RP is returned to VIH, all the previously protected blocks are again pro- tected. Block Unprotection.All protected blocks can be unprotected on programming equipment to allow updating of bit contents. All blocks must first be protected before the unprotection operation. Block unprotection is activated when A9, G and E are at VID and A12, A15 at VIH. Unprotection is initiated by the edge of W falling to VIL. After a delay of 10ms, the unprotection operation will end. Unpro- tection verify is achieved by bringing G and E to VIL while A0 is at VIL, A6 and A1 are at VIH and A9 remains at VID. In these conditions, reading the output data will yield 00h if the block defined by the inputs A13-A19 has been successfully unprotect- ed. Each block must be separately verified by giv- ing its address in order to ensure that it has been unprotected.
Table 5. User Bus Operations (1)
- Block Address must be given an A13-A19 bits.
- Operation performed on programming equipment.
Table 6. Read Electronic Signature (following AS instruction or with A9 = VID) Table 7. Read Block Protection with AS Instruction
Table 8. Commands DQ2, or Error on DQ5 and Erase Timer DQ3 bits. use and should be masked. See Tables 10 and 11. plement of the bit being programmed on DQ7.
Table 9. Instructions (1) Note: 1. Commands not interpreted in this table will default to read array mode.
- A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase or Program mode before starting any new
operation (see Tables 15, 16 and Figure 9).
- The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the com-
- Signature Address bits A0, A1, at V
- Block Protection Address: A0, at VIL, A1 at VIH and A13-A19 within the Block will output the Block Protection status.
- For Coded cycles address inputs A15-A19 are don't care.
- Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout statuscan be
until Erase is completed or suspended.
- Read Data Polling, Toggle bits or RB until Erase completes.
- During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.
Read Memory Array until a new write cycle is initiated.
Table 10. Status Register Bits Note: Logic level '1' is High, '0' is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
7 Data
6 Toggle Bit
5 Error Bit
4 Reserved
3 Erase
can be entered to the P/E.C.
2 Toggle Bit
1 Reserved
0 Reserved
not accepted during Erase and Erase Suspend. Boot is output when A0 is High with A1 Low. A19 define the address of the block to be verified. Table 11. Polling and Toggle Bits Note: 1. Toggle if the address is within a block being erased. '1' if the address is within a block not being erased. Error Bit (DQ5).This bit is set to '1' by the P/E.C. of Program or Erase, the error bit will be set to '0'.
Table 15. Read AC Characteristics Note: 1. Sampled only, not 100% tested.
- G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV .
- To be considered only if the Reset pulse is given while the memory is in Erase or Program mode.
Table 16. Read AC Characteristics Note: 1. Sampled only, not 100% tested.
- G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV .
- To be considered only if the Reset pulse is given while the memory is in Erase or Program mode.
Figure 5. Read Mode AC Waveforms Note: Write Enable (W) = High.
Table 17. Write AC Characteristics, W Controlled Note: 1. Sampled only, not 100% tested.
- This timing is for Temporary Block Unprotection operation.
tion aborts, and the device is reset to Read Array.
Table 18. Write AC Characteristics, W Controlled Note: 1. Sampled only, not 100% tested.
- This timing is for Temporary Block Unprotection operation.
if there has been an Erase Failure.
Figure 6. Write AC Waveforms, W Controlled Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W. sult in invalid data in the blocks being erased.
Table 19. Write AC Characteristics, E Controlled Note: 1. Sampled only, not 100% tested.
- This timing is for Temporary Block Unprotection operation.
and E are at VIL with G at VIH during power-up. gram and erase currents required.
Table 20. Write AC Characteristics, E Controlled Note: 1. Sampled only, not 100% tested.
- This timing is for Temporary Block Unprotection operation.
Table 21. Data Polling and Toggle Bit AC Characteristics (1) Note: 1. All other timings are defined in Read AC Characteristics table. Table 22. Data Polling and Toggle Bit AC Characteristics (1) Note: 1. All other timings are defined in Read AC Characteristics table.
Figure 9. Data Polling DQ7 AC Waveforms
Figure 12. Data Toggle DQ6, DQ2 AC Waveforms Note: All other timings are as a normal Read cycle.
Table 24. Security Block Instruction Note: 1. Address bits A10-A19 are don't care for coded address inputs.
- Data bits DQ8-DQ15 are don't care for coded address inputs.
Read OTP Data until a new write cycle is initiated. Figure 13. Security Block Address Table rity byte until a new write cycle is initiated.
Table 25. Ordering Information Scheme Devices are shipped from the factory with the memory content bits erased to ’1’. vice, please contact the ST Sales Office nearest to you.
Table 26. Revision History
Table 27. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data Figure 14. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline
M29W008AT, M29W008AB Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com