M29W004B-120N1TR

M29W004T STMICROELECTRONICS | Alldatasheet

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Technical content

W DQ0-DQ7 VCC M29W004T M29W004BE VSS G RP RB Figure 1. Logic Diagram

4 Mbit (512Kb x8, Boot Block)

20 YEARS DATA RETENTION

DESCRIPTION

The M29W004 is a non-volatile memory that may be erased electrically at the block or chip level and programmed in-system on a Byte-by-Byte basis using only a single 2.7V to 3.6V V CC supply. For Program and Erase operations the necessary high voltages are generated internally. The device can also be programmed in standard programmers. The array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. Blocks can be protected against pro- graming and erase on programming equipment, and temporarily unprotected to make changes in June 1999 1/30 This is information on a product still in production but not recommended for new designs. TSOP40 (N) 10 x 20 mm

Figure 2. TSOP Pin Connections Warning: NC = Not Connected. and erased over 100,000 cycles. standard microprocessor write timings. indicates the completion of the internal algorithms.

1. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.

Table 2. Absolute Maximum Ratings (1) Table 1. Signal Names

The devices feature asymmetrically blocked archi- tecture providing system memory integration. Both M29W004T and M29W004B devices have an array of 11 blocks, one Boot Block of 16K Bytes, two Parameter Blocks of 8K Bytes, one Main Block of 32K Bytes and seven Main Blocks of 64K Bytes. The M29W004T has the Boot Block at the top of the memory address space and the M29W004B locates the Boot Block starting at the bottom. The memory maps are showed in Figure 3. Each block can be erased separately, any combination of blocks can be specified for multi-block erase or the entire chip may be erased. The Erase operations are managed automatically by the P/E.C. The block erase operation can be suspended in order to read from or program to any block not being ersased, and then resumed. Block protection provides additional data security. Each block can be separately protected or unpro- tected against Program or Erase on programming equipment. All previously protected blocks can be temporarily unprotected in the application. Bus Operations The following operations can be performed using the appropriate bus cycles: Read (Array, Electronic Signature, Block Protection Status), Write com- mand, Output Disable, Standby, Reset, Block Pro- tection, Unprotection, Protection Verify, Unprotection Verify and Block Temporary Unpro- tection. See Tables 4 and 5. Command Interface Instructions, made up of commands written in cy- cles, can be given to the Program/Erase Controller through a Command Interface (C.I.). For added data protection, program or erase execution starts after 4 or 6 cycles. The first, second, fourth and fifth cycles are used to input Coded cycles to the C.I. This Coded sequence is the same for all Pro- gram/Erase Controller instructions. The ’Com- mand’ itself and its confirmation, when applicable, are given on the third, fourth or sixth cycles. Any incorrect command or any improper command se- quence will reset the device to Read Array mode. Instructions Seven instructions are defined to perform Read Array, Auto Select (to read the Electronic Signature or Block Protection Status), Program, Block Erase, Chip Erase, Erase Suspend and Erase Resume. The internal P/E.C. automatically handles all tim- ing and verification of the Program and Erase operations. The Status Register Data Polling, Tog- gle, Error bits and the R B output may be read at any time, during programming or erase, to monitor the progress of the operation. Instructions are composed of up to six cycles. The first two cycles input a Coded sequence to the Command Interface which is common to all instruc- tions (see Table 8). The third cycle inputs the instruction set-up command. Subsequent cycles output the addressed data, Electronic Signature or Block Protection Status for Read operations. In order to give additional data protection, the instruc- tions for Program and Block or Chip Erase require further command inputs. For a Program instruction, the fourth command cycle inputs the address and data to be programmed. For an Erase instruction (Block or Chip), the fourth and fifth cycles input a further Coded sequence before the Erase confirm command on the sixth cycle. Erasure of a memory block may be suspended, in order to read data from another block or to program data in another block, and then resumed. When power is first applied or if Vcc falls below V LKO , the command interface is reset to Read Array. SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs (A0-A18). The address inputs for the memory array are latched during a write opera- tion on the falling edge of Chip Enable E or Write Enable W. In Word-wide organisation the address lines are A0-A18. When A9 is raised to VID, either a Read Electronic Signature Manufacturer or De- vice Code, Block Protection Status or a Write Block Protection or Block Unprotection is enabled de- pending on the combination of levels on A0, A1, A6, A12 and A15. Data Input/Outputs (DQ0-DQ7). The input is data to be programmed in the memory array or a com- mand to be written to the C.I. Both are latched on the rising edge of Chip Enable E or Write Enable W. The output is data from the Memory Array, the Electronic Signature Manufacturer or Device codes, the Block Protection Status or the Status register Data Polling bit DQ7, the Toggle Bits DQ6 and DQ2, the Error bit DQ5 or the Erase Timer bit DQ3. Outputs are valid when Chip Enable E and Output Enable G are active. The output is high impedance when the chip is deselected or the outputs are disabled and when RP is at a Low level. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. E High deselects the memory and reduces the power consumption to the standby level. E can also be used to control writing to the command register and to the memory array, while W remains at a low level. The Chip Enable must be forced to V ID during the Block Unprotection opera- tion. M29W004T, M29W004B

Figure 3. Memory Map and Block Address Table (x8) Block Protection and Unprotection operations. Command Register and Address and Data latches. instructions except the Erase Suspend instruction. Reset/Block Temporary Unprotect Input (RP). tected block(s) temporary unprotection functions. tPLYH during which the RB signal will be held at VIL. being programmed or the sector(s) being erased. RP from VIH to VID must slower than tPHPHH . temporarily unprotected will be again protected. operations (Read, Program and Erase).

Address Range A18 A17 A16 A15 A14 A13 00000h-03FFFh 00000X 04000h-05FFFh 000010 06000h-07FFFh 000011 08000h-0FFFFh 0001XX 10000h-1FFFFh 0 0 1 X X X 20000h-2FFFFh 0 1 0 X X X 30000h-3FFFFh 0 1 1 X X X 40000h-4FFFFh 1 0 0 X X X 50000h-5FFFFh 1 0 1 X X X 60000h-6FFFFh 1 1 0 X X X 70000h-7FFFFh 1 1 1 X X X Table 3B. M29W004B Block Address Table Address Range A18 A17 A16 A15 A14 A13 00000h-0FFFFh 0 0 0 X X X 10000h-1FFFFh 0 0 1 X X X 20000h-2FFFFh 0 1 0 X X X 30000h-3FFFFh 0 1 1 X X X 40000h-4FFFFh 1 0 0 X X X 50000h-5FFFFh 1 0 1 X X X 60000h-6FFFFh 1 1 0 X X X 70000h-77FFFh 1110XX 78000h-79FFFh 111100 7A000h-7BFFFh 111101 7C000h-7FFFFh 11111X Table 3A. M29W004T Block Address Table M29W004T, M29W004B

See Tables 4, 5 and 6. Read. Read operations are used to output the contents of the Memory Array, the Electronic Sig- nature, the Status Register or the Block Protection Status. Both Chip Enable E and Output Enable G must be low in order to read the output of the memory. Write. Write operations are used to give Instruction Commands to the memory or to latch input data to be programmed. A write operation is initiated when Chip Enable E is Low and Write Enable W is Low with Output Enable G High. Addresses are latched on the falling edge of W or E whichever occurs last. Commands and Input Data are latched on the rising edge of W or E whichever occurs first. Output Disable. The data outputs are high imped- ance when the Output Enable G is High with Write Enable W High. Standby. The memory is in standby when Chip Enable E is High and the P/E.C. is idle. The power consumption is reduced to the standby level and the outputs are high impedance, independent of the Output Enable G or Write Enable W inputs. Automatic Standby. After 150ns of bus inactivity and when CMOS levels are driving the addresses, the chip automatically enters a pseudo-standby mode where consumption is reduced to the CMOS standby value, while outputs still drive the bus. Electronic Signature. Two codes identifying the manufacturer and the device can be read from the memory. The manufacturer’s code for STMi- croelectronics is 20h, the device code is EAh for the M29W004T (Top Boot) and EBh for the M29W004B (Bottom Boot). These codes allow pro- gramming equipment or applications to automat- ically match their interface to the characteristics of the M29W004. The Electronic Signature is output by a Read operation when the voltage applied to A9 is at V ID and address input A1 is Low. The manufacturer code is output when the Address input A0 is Low and the device code when this input is High. Other Address inputs are ignored. The Electronic Signature can also be read, without raising A9 to V ID, by giving the memory the Instruc- tion AS. Block Protection. Each block can be separately protected against Program or Erase on program- ming equipment. Block protection provides addi- tional data security, as it disables all program or erase operations. This mode is activated when both A9 and G are raised to VID and an address in the block is applied on A13-A18. The Block Protection algorithm is shown in Figure 14. Block protection is initiated on the edge of W falling to VIL. Then after a delay of 100µs, the edge of W rising to VIH ends the protection operations. Block protection verify is achieved by bringing G, E, A0 and A6 to VIL and A1 to VIH, while W is at VIH and A9 at VID. Under these conditions, reading the data output will yield 01h if the block defined by the inputs on A13-A18 is protected. Any attempt to program or erase a pro- tected block will be ignored by the device. Block Temporary Unprotection. Any previously protected block can be temporarily unprotected in order to change stored data. The temporary unpro- tection mode is activated by bringing RP to VID. During the temporary unprotection mode the pre- viously protected blocks are unprotected. A block can be selected and data can be modified by executing the Erase or Program instruction with the RP signal held at VID. When RP is returned to VIH, all the previously protected blocks are again pro- tected. Block Unprotection. All protected blocks can be unprotected on programming equipment to allow updating of bit contents. All blocks must first be protected before the unprotection operation. Block unprotection is activated when A9, G and E are at VID and A12, A15 at VIH. The Block Unprotection algorithm is shown in Figure 15. Unprotection is initiated by the edge of W falling to VIL. After a delay of 10ms, the unprotection operation will end. Un- protection verify is achieved by bringing G and E to VIL while A0 is at VIL, A6 and A1 are at VIH and A9 remains at VID. In these conditions, reading the output data will yield 00h if the block defined by the inputs A13-A18 has been succesfully unprotected. Each block must be separately verified by giving its address in order to ensure that it has been unpro- tected. M29W004T, M29W004B

1. Block Address must be given on A13-A18 bits.
2. Operation performed on programming equipment.

Table 4. User Bus Operations (1) Table 5. Read Electronic Signature (following AS instruction or with A9 = VID) Table 6. Read Block Protection with AS Instruction

been chosen to assure maximum data security. preceded by the two Coded cycles. DQ2, or Error on DQ5 and Erase Timer DQ3 bits. and should be masked. See Tables 9 and 10. plement of the bit being programmed on DQ7. operation is attempted on an Erase Suspend block. flowchart and Figure 13 for Toggle Bit waveforms. Table 7. Commands

(3,7) X Read Memory Array until a new write cycle is initiated. Notes:1. Commands not interpreted in this table will default to read array mode.

1. A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase or Program mode

before starting any new operation (See Table 14 and Figure 9).

1. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after
2. Signature Address bits A0, A1 at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1 at VIL will output
3. Block Protection Address: A0 at VIL, A1 at VIH and A13-A18 within the Block will output the Block Protection status.
4. For Coded cycles address inputs A15-A18 are don’t care.
5. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout status

or Toggle bit until Erase is completed or suspended.

1. Read Data Polling, Toggle bits or R

10.During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased. Table 8. Instructions (1)

7 Data

6 Toggle Bit

5 Error Bit ’1’ Program or Erase Error This bit is set to ’1’ in the case of

4 Reserved

3 Erase

can be entered to the P/E.C.

2 Toggle Bit

1 Reserved

0 Reserved

Notes:Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations. Table 9. Status Register Bits

Error Bit (DQ5). This bit is set to ’1’ by the P/E.C. Erase, the error bit will be set to ’0’ . Boot is output when A0 is High with A1 Low. protected and a 00h if the block is not protected. Note: 1. Toggle if the address is within a block being erased. ’1’ if the address is within a block not being erased. Table 10. Polling and Toggle Bits

VCC = 3.0V to 3.6V C L = 30pF VCC = 2.7V to 3.6V C L = 30pF Min Max Min Max tAVAV tRC Address Valid to Next Address ValidE = VIL, G = VIL 90 100 ns tAVQV tACC Address Valid to Output Valid E = VIL, G = VIL 90 100 ns tELQX (1) tLZ Chip Enable Low to Output TransitionG = VIL 00 n s tELQV (2) tCE Chip Enable Low to Output Valid G = VIL 90 100 ns tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL 00 n s tGLQV (2) tOE Output Enable Low to Output ValidE = VIL 35 40 ns tEHQX tOH Chip Enable High to Output TransitionG = VIL 00 n s tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL 30 30 ns tGHQX tOH Output Enable High to Output Transition E = VIL 00 n s tGHQZ (1) tDF Output Enable High to Output Hi-ZE = VIL 30 30 ns tAXQX tOH Address Transition to Output Transition E = VIL, G = VIL 00 n s tPLYH (1,3) tRRB tREADY RP Low to Read Mode 10 10 µs tPHEL tRH RP High to Chip Enable Low 50 50 ns tPLPX tRP RP Pulse Width 500 500 ns Notes:1. Sampled only, not 100% tested. 2.G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV . 3. To be considered only if the Reset pulse is given while the memory is in Erase mode. Table 14A. Read AC Characteristics (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) M29W004T, M29W004B

VCC = 2.7V to 3.6V VCC = 2.7V to 3.6V Min Max Min Max tAVAV tRC Address Valid to Next Address ValidE = VIL, G = VIL 120 150 ns tAVQV tACC Address Valid to Output Valid E = VIL, G = VIL 120 150 ns tELQX (1) tLZ Chip Enable Low to Output TransitionG = VIL 00 n s tELQV (2) tCE Chip Enable Low to Output Valid G = VIL 120 150 ns tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL 00 n s tGLQV (2) tOE Output Enable Low to Output ValidE = VIL 50 55 ns tEHQX tOH Chip Enable High to Output TransitionG = VIL 00 n s tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL 30 40 ns tGHQX tOH Output Enable High to Output Transition E = VIL 00 n s tGHQZ (1) tDF Output Enable High to Output Hi-ZE = VIL 30 40 ns tAXQX tOH Address Transition to Output Transition E = VIL, G = VIL 00 n s tPLYH (1,3) tRRB tREADY RP Low to Read Mode 10 10 µs tPHEL tRH RP High to Chip Enable Low 50 50 ns tPLPX tRP RP Pulse Width 500 500 ns Notes:1. Sampled only, not 100% tested. 2.G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV . 3. To be considered only if the Reset pulse is given while the memory is in Erase mode. Table 14B. Read AC Characteristics (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) M29W004T, M29W004B

Figure 6. Read Mode AC Waveforms Note: Write Enable (W) = High.

VCC = 3.0V to 3.6V C L = 30pF VCC = 2.7V to 3.6V C L = 30pF Min Max Min Max tAVAV tWC Address Valid to Next Address Valid 90 100 ns tELWL tCS Chip Enable Low to Write Enable Low 0 0 ns tWLWH tWP Write Enable Low to Write Enable High 45 50 ns tDVWH tDS Input Valid to Write Enable High 45 50 ns tWHDX tDH Write Enable High to Input Transition 0 0 ns tWHEH tCH Write Enable High to Chip Enable High 0 0 ns tWHWL tWPH Write Enable High to Write Enable Low 30 30 ns tAVWL tAS Address Valid to Write Enable Low 0 0 ns tWLAX tAH Write Enable Low to Address Transition 45 50 ns tGHWL Output Enable High to Write Enable Low 0 0 ns tVCHEL tVCS VCC High to Chip Enable Low 50 50 µs tWHGL t OEH Write Enable High to Output Enable Low 0 0 ns tPHPHH (1,2) tVIDR RP Rise Time to VID 500 500 ns tPLPX tRP RP Pulse Width 500 500 ns tWHRL (1) tBUSY Program Erase Valid to RB Delay 90 90 ns tPHWL (1) tRSP RP High to Write Enable Low 4 4 µs Notes:1. Sample only, not 100% tested. 2. This timing is for Temporary Block Unprotection operation. Table 15A. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) Block Erase (BE) Instruction. This instruction uses a minimum of six write cycles. The Erase Set-up command 80h is written to address 5555h on third cycle after the two Coded cycles. The Block Erase Confirm command 30h is similarly written on the sixth cycle after another two Coded cycles. During the input of the second command an ad- dress within the block to be erased is given and latched into the memory. Additional block Erase Confirm commands and block addresses can be written subsequently to erase other blocks in par- allel, without further Coded cycles. The erase will start after the erase timeout period (see Erase Timer Bit DQ3 description). Thus, additional Erase Confirm commands for other blocks must be given within this delay. The input of a new Erase Confirm command will restart the timeout period. The status of the internal timer can be monitored through the level of DQ3, if DQ3 is ’0’ the Block Erase Com- mand has been given and the timeout is running, if DQ3 is ’1’, the timeout has expired and the P/E.C. is erasing the Block(s). If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts, and the device is reset to Read Array. It is not necessary to program the block with 00h as the P/E.C. will do this auto- matically before to erasing to FFh. Read operations M29W004T, M29W004B

VCC = 2.7V to 3.6V V CC = 2.7V to 3.6V Min Max Min Max tAVAV tWC Address Valid to Next Address Valid 120 150 ns tELWL tCS Chip Enable Low to Write Enable Low 0 0 ns tWLWH tWP Write Enable Low to Write Enable High 50 65 ns tDVWH tDS Input Valid to Write Enable High 50 65 ns tWHDX tDH Write Enable High to Input Transition 0 0 ns tWHEH tCH Write Enable High to Chip Enable High 0 0 ns tWHWL tWPH Write Enable High to Write Enable Low 30 35 ns tAVWL tAS Address Valid to Write Enable Low 0 0 ns tWLAX tAH Write Enable Low to Address Transition 50 65 ns tGHWL Output Enable High to Write Enable Low 0 0 ns tVCHEL tVCS VCC High to Chip Enable Low 50 50 µs tWHGL t OEH Write Enable High to Output Enable Low 0 0 ns tPHPHH (1,2) tVIDR RP Rise Time to VID 500 500 ns tPLPX tRP RP Pulse Width 500 500 ns tWHRL (1) tBUSY Program Erase Valid to RB Delay 90 90 ns tPHWL (1) tRSP RP High to Write Enable Low 4 4 µs Notes:1. Sample only, not 100% tested. 2. This timing is for Temporary Block Unprotection operation. Table 15B. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) after the sixth rising edge of W or E output the status register status bits. During the execution of the erase by the P/E.C., the memory accepts only the Erase Suspend ES and Read/Reset RD instructions. Data Polling bit DQ7 returns ’0’ while the erasure is in progress and ’1’ when it has completed. The Toggle bit DQ2 and DQ6 toggle during the erase operation. They stop when erase is completed. After completion the Status Register bit DQ5 returns ’1’ if there has been an erase failure. In such a situation, the Toggle bit DQ2 can be used to determine which block is not correctly erased. In the case of erase failure, a Read/Reset RD instruction is necessary in order to reset the P/E.C. Chip Erase (CE) Instruction. This instruction uses six write cycles. The Erase Set-up command 80h is written to address 5555h on the third cycle after the two Coded cycles. The Chip Erase Confirm command 10h is similarly written on the sixth cycle after another two Coded cycles. If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts and the device is reset to Read Array. It is not necessary to program the array with 00h first as the P/E.C. will automatically do this before erasing it to FFh. Read operations after the sixth rising edge of W or E output the Status Register bits. During the execu- tion of the erase by the P/E.C., Data Polling bit DQ7 returns ’0’, then ’1’ on completion. The Toggle bits DQ2 and DQ6 toggle during erase operation and M29W004T, M29W004B

Figure 7. Write AC Waveforms, W Controlled Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W. in invalid data in the blocks being erased.

VCC = 3.0V to 3.6V C L = 30pF VCC = 2.7V to 3.6V C L = 30pF Min Max Min Max tAVAV tWC Address Valid to Next Address Valid 90 100 ns tWLEL tWS Write Enable Low to Chip Enable Low 0 0 ns tELEH tCP Chip Enable Low to Chip Enable High 45 50 ns tDVEH tDS Input Valid to Chip Enable High 45 5 ns tEHDX tDH Chip Enable High to Input Transition 0 0 ns tEHWH tWH Chip Enable High to Write Enable High 0 0 ns tEHEL tCPH Chip Enable High to Chip Enable Low 20 20 ns tAVEL tAS Address Valid to Chip Enable Low 0 0 ns tELAX tAH Chip Enable Low to Address Transition 45 50 ns tGHEL Output Enable High Chip Enable Low 0 0 ns tVCHWL tVCS VCC High to Write Enable Low 50 50 µs tEHGL tOEH Chip Enable High to Output Enable Low 0 0 ns tPHPHH (1,2) tVIDR RP Rise TIme to VID 500 500 ns tPLPX tRP RP Pulse Width 500 500 ns tEHRL (1) tBUSY Program Erase Valid to RB Delay 90 90 ns tPHWL (1) tRSP RP High to Write Enable Low 4 4 µs Notes:1. Sample only, not 100% tested. 2. This timing is for Temporary Block Unprotection operation. Table 16A. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) Erase Resume (ER) Instruction. If an Erase Sus- pend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at any address, and without any Coded cycles. POWER SUPPLY Power Up The memory Command Interface is reset on power up to Read Array. Either E or W must be tied to VIH during Power Up to allow maximum security and the possibility to write a command on the first rising edge of E and W. Any write cycle initiation is blocked when Vcc is below VLKO . Supply Rails Normal precautions must be taken for supply volt- age decoupling; each device in a system should have the V CC rail decoupled with a 0.1µF capacitor close to the VCC and VSS pins. The PCB trace widths should be sufficient to carry the VCC pro- gram and erase currents required. M29W004T, M29W004B

VCC = 2.7V to 3.6V VCC = 2.7V to 3.6V Min Max Min Max tAVAV tWC Address Valid to Next Address Valid 120 150 ns tWLEL tWS Write Enable Low to Chip Enable Low 0 0 ns tELEH tCP Chip Enable Low to Chip Enable High 50 50 ns tDVEH tDS Input Valid to Chip Enable High 50 50 ns tEHDX tDH Chip Enable High to Input Transition 0 0 ns tEHWH tWH Chip Enable High to Write Enable High 0 0 ns tEHEL tCPH Chip Enable High to Chip Enable Low 20 20 ns tAVEL tAS Address Valid to Chip Enable Low 0 0 ns tELAX tAH Chip Enable Low to Address Transition 50 50 ns tGHEL Output Enable High Chip Enable Low 0 0 ns tVCHWL tVCS VCC High to Write Enable Low 50 50 µs tEHGL tOEH Chip Enable High to Output Enable Low 0 0 ns tPHPHH (1,2) tVIDR RP Rise TIme to VID 500 500 ns tPLPX tRP RP Pulse Width 500 500 ns tEHRL (1) tBUSY Program Erase Valid to RB Delay 90 90 ns tPHWL (1) tRSP RP High to Write Enable Low 4 4 µs Notes:1. Sample only, not 100% tested. 2. This timing is for Temporary Block Unprotection operation. Table 16B. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) M29W004T, M29W004B

VCC = 3.0V to 3.6V C L = 30pF VCC = 2.7V to 3.6V C L = 30pF Min Max Min Max tWHQ7V Write Enable High to DQ7 Valid (Program, W Controlled) 10 2400 10 2400 ms Write Enable High to DQ7 Valid (Chip Erase, W Controlled) 1.0 30 1.0 30 sec tEHQ7V Chip Enable High to DQ7 Valid (Program, E Controlled) 10 2400 10 2400 µs Chip Enable High to DQ7 Valid (Chip Erase, E Controlled) 1.0 30 1.0 30 sec tQ7VQV Q7 Valid to Output Valid (Data Polling) 35 40 ns tWHQV Write Enable High to Output Valid (Program) 10 2400 10 2400 µs Write Enable High to Output Valid (Chip Erase) 1.0 30 1.0 30 sec tEHQV Chip Enable High to Output Valid (Program) 10 2400 10 2400 µs Chip Enable High to Output Valid (Chip Erase) 1.0 30 1.0 30 sec Note: 1. All other timings are defined in Read AC Characteristics table. Table 17A. Data Polling and Toggle Bit AC Characteristics (1) (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) Sym- bol Parameter M29W004T / M29W004B Unit-120 -150 VCC = 2.7V to 3.6V V CC = 2.7V to 3.6V Min Max Min Max tWHQ7V Write Enable High to DQ7 Valid (Program, W Controlled) 10 2400 10 2400 ms Write Enable High to DQ7 Valid (Chip Erase, W Controlled) 1.0 30 1.0 30 sec tEHQ7V Chip Enable High to DQ7 Valid (Program, E Controlled) 10 2400 10 2400 µs Chip Enable High to DQ7 Valid (Chip Erase, E Controlled) 1.0 30 1.0 30 sec tQ7VQV Q7 Valid to Output Valid (Data Polling) 50 55 ns tWHQV Write Enable High to Output Valid (Program) 10 2400 10 2400 µs Write Enable High to Output Valid (Chip Erase) 1.0 30 1.0 30 sec tEHQV Chip Enable High to Output Valid (Program) 10 2400 10 2400 µs Chip Enable High to Output Valid (Chip Erase) 1.0 30 1.0 30 sec Note: 1. All other timings are defined in Read AC Characteristics table. Table 17B. Data Polling and Toggle Bit AC Characteristics (1) (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) M29W004T, M29W004B

Figure 10. Data Polling DQ7 AC Waveforms

Figure 13. Data Toggle DQ6, DQ2 AC Waveforms Note: All other timings are as a normal Read cycle.

Figure 14. Block Protection Flowchart

Figure 15. All Blocks Unprotecting Flowchart

ORDERING INFORMATION SCHEME M29W004T and M29W004B are replaced respectively by the new version M29W004BT and M29W004BB Devices are shipped from the factory with the memory content erased (to FFh). For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. Operating Voltage W 2.7V to 3.6V Array Matrix T Top Boot B Bottom Boot Speed -90 90ns -100 100ns -120 120ns -150 150ns Package N TSOP40 10 x 20mm Option TR Tape & Reel Packing Temp. Range 1 0 to 70 °C 5 –20 to 85 °C 6 –40 to 85 °C Example: M29W004T -90 N 1 TR M29W004T, M29W004B

E 1 N CP B e A N/2 D DIE C LA1 α Symb mm inches Typ Min Max Typ Min Max A 1.20 0.047 A1 0.05 0.15 0.002 0.006 A2 0.95 1.05 0.037 0.041 B 0.17 0.27 0.007 0.011 C 0.10 0.21 0.004 0.008 D 19.80 20.20 0.780 0.795 D1 18.30 18.50 0.720 0.728 E 9.90 10.10 0.390 0.398 e0 . 5 0– – 0 . 0 2 0 – – L 0.50 0.70 0.020 0.028 α 0° 5° 0° 5° N4 0 4 0 CP 0.10 0.004 Drawing is not to scale. TSOP40 Normal Pinout - 40 lead Plastic Thin Small Outline, 10 x 20mm M29W004T, M29W004B

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 1999 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com M29W004T, M29W004B