M29W002BT STMICROELECTRONICS | Alldatasheet
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
2 Mbit (256Kb x8, Boot Block)
Figure 1. Logic Diagram
Figure 2. TSOP Connections Table 1. Signal Names ranged, see Tables 3A and 3B, Block Addresses. the application may be stored. nals control the bus operation of the memory. cessors, often without additional logic.
Table 2. Absolute Maximum Ratings (1)
- Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
Table 3. Top Boot Block Addresses Table 4. Bottom Boot Block Addresses
M29W002BT, M29W002BB SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A17).The Address Inputs select the cells in the memory array to access dur- ing Bus Read operations. During Bus Write opera- tions they control the commands sent to the Command Interface of the internal state machine. Data Inputs/Outputs (DQ0-DQ7).The Data In- puts/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. Chip Enable (E ).The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write op- erations to be performed. When Chip Enable is High, VIH, all other pins are ignored. Output Enable (G).The Output Enable, G, con- trols the Bus Read operation of the memory. Write Enable (W).The Write Enable, W, controls the Bus Write operation of the memory’s Com- mand Interface. Reset/Block Temporary Unprotect (RP).The Re- set/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to tem- porarily unprotect all Blocks that have been pro- tected. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, V IL, for at least tPLPX . After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL , whichever occurs last. See the Ready/Busy Output section, Table 15 and Figure 10, Reset/ Temporary Unprotect AC Characteristics for more details. Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from V IH to VID must be slower than tPHPHH . Ready/Busy Output (RB).The Ready/Busy pin is an open-drain output that can be used to identify when the memory array can be read. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy be- comes high-impedance. See Table 15 and Figure 10, Reset/Temporary Unprotect AC Characteris- tics. During Program or Erase operations Ready/Busy is Low, V OL . Ready/Busy will remain Low during Read/Reset commands or Hardware Resets until the memory is ready to enter Read mode. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. VCC Supply Voltage.The V CC Supply Voltage supplies the power for all operations (Read, Pro- gram, Erase etc.). The Command Interface is disabled when the V CC Supply Voltage is less than the Lockout Voltage, VLKO . This prevents Bus Write operations from ac- cidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memo- ry contents being altered will be invalid. A 0.1µF capacitor should be connected between the V CC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, I CC3 . VSS Ground. The VSS Ground is the reference for all voltage measurements.
Table 5. Bus Operations of when the output becomes valid. Enable or Write Enable, whichever occurs last. level see Table 11, DC Characteristics. til the operation completes. Read operation is in progress. ment and are not usually used in applications. ID to be applied to some pins. code, that can be read to identify the memory. listed in Table 5, Bus Operations. unprotected to allow data to be changed.
M29W002BT, M29W002BB COMMAND INTERFACE All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. Failure to observe a valid sequence of Bus Write operations will result in the memory return- ing to Read mode. The long command sequences are imposed to maximize data security. The commands are summarized in Table 6, Com- mands. Refer to Table 6 in conjunction with the text descriptions below. Read/Reset Command. The Read/Reset com- mand returns the memory to its Read mode where it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. If the Read/Reset command is issued during a Block Erase operation or following a Programming or Erase error then the memory will take up to 10 µs to abort. During the abort period no valid data can be read from the memory. Issuing a Read/Reset command during a Block Erase operation will leave invalid data in the memory. Auto Select Command. The Auto Select com- mand is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are re- quired to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until another com- mand is issued. From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = V IL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Manufacturer Code for STMicroelectronics is 20h. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. The Device Code for the M29W002BT is 40h and the M29W002BB is C2h. The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, and A13-A17 specifying the address of the block. The other address bits may be set to ei- ther VIL or VIH. If the addressed block is protected then 01h is output on the Data Inputs/Outputs, oth- erwise 00h is output. Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command re- quires four Bus Write operations, the final write op- eration latches the address and data in the internal state machine and starts the Program/Erase Con- troller. If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. During the program operation the memory will ig- nore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 7. Bus Read op- erations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Regis- ter. A Read/Reset command must be issued to re- set the error condition and return to Read mode. Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase Com- mands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. Unlock Bypass Command. The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memo- ry. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these com- mands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been is- sued the memory will only accept the Unlock By- pass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode. Unlock Bypass Program Command. The Un- lock Bypass Program command can be used to program one address in memory at a time. The command requires two Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Pro- gram/Erase Controller. The Program operation using the Unlock Bypass Program command behaves identically to the Pro- gram operation using the Program command. A protected block cannot be programmed; the oper- ation cannot be aborted and the Status Register is read. Errors must be reset using the Read/Reset command, which leaves the device in Unlock By- pass Mode. See the Program command for details on the behavior.
Table 6. Commands Note:X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The Command Interface only uses address bits A0-A10 to verify the commands, the upper address bits are Don’t Care. Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued. Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status. Operations until the Timeout Bit is set. Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands. Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued. on non-erasing blocks as normal. Erase Controller completes and the memory returns to Read Mode. Read/Reset mode from Unlock Bypass Mode. Unlock Bypass Reset command. given when protected blocks are ignored. the Status Register on the Data Inputs/Outputs. set the error condition and return to Read Mode.
timer restarts when an additional block is selected. Controller has started the Block Erase operation. the Status Register on the Data Inputs/Outputs. set the error condition and return to Read mode. data in the selected blocks is lost. blocks for erasure after the Erase Resume. memory to Erase Suspend mode. can be suspended and resumed more than once. Table 7. Program, Erase Times and Program, Erase Endurance Cycles
Table 11. DC Characteristics Note: 1. Sampled only, not 100% tested.
Figure 7. Read Mode AC Waveforms Table 12. Read AC Characteristics Note: 1. Sampled only, not 100% tested.
Figure 8. Write AC Waveforms, Write Enable Controlled Table 13. Write AC Characteristics, Write Enable Controlled Note: 1. Sampled only, not 100% tested.
Table 14. Write AC Characteristics, Chip Enable Controlled Note: 1. Sampled only, not 100% tested. Figure 9. Write AC Waveforms, Chip Enable Controlled
Table 15. Reset/Block Temporary Unprotect AC Characteristics Note: 1. Sampled only, not 100% tested. Figure 10. Reset/Block Temporary Unprotect AC Waveforms
Table 16. Ordering Information Scheme parts, otherwise devices are shipped from the factory with the memory content bits erased to ’1’. vice, please contact the ST Sales Office nearest to you.
Table 17. Revision History
Figure 11. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline Table 18. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data
M29W002BT, M29W002BB Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com