M29F002BT STMICROELECTRONICS | Alldatasheet
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Technical content
2 Mbit (256Kb x8, Boot Block) Single Supply Flash Memory
Figure 1. Logic Diagram
Figure 2. PLCC Connections
1 A16
Table 1. Signal Names Figure 3. TSOP Connections Figure 4. PDIP Connections
Table 2. Absolute Maximum Ratings
- Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
Table 4. Bottom Boot Block Addresses, ranged, see Tables 3A and 3B, Block Addresses. nals control the bus operation of the memory. cessors, often without additional logic. with all the bits erased (set to ’1’). Table 3. Top Boot Block Addresses,
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A17).The Address Inputs select the cells in the memory array to access dur- ing Bus Read operations. During Bus Write opera- tions they control the commands sent to the Command Interface of the internal state machine. Data Inputs/Outputs (DQ0-DQ7).The Data In- puts/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. Chip Enable (E ).The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write op- erations to be performed. When Chip Enable is High, VIH, all other pins are ignored. Output Enable (G).The Output Enable, G, con- trols the Bus Read operation of the memory. Write Enable (W).The Write Enable, W, controls the Bus Write operation of the memory’s Com- mand Interface. Reset/Block Temporary Unprotect (RP).The Re- set/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to tem- porarily unprotect all blocks that have been pro- tected. On the M29F002BNT the pin is not connected internally and this feature is not avail- able. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, V IL, for at least tPLPX . After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tPLYH , whichever occurs last. See Table 15 and Figure 12, Reset/Temporary Unprotect AC Char- acteristics for more details. Holding RP at VID will temporarily unprotect the protected blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from V IH to VID must be slower than tPHPHH . Reset/Block Temporary Unprotect can be left un- connected. A weak internal pull-up resistor en- sures that the memory always operates correctly. V CC Supply Voltage.The V CC Supply Voltage supplies the power for all operations (Read, Pro- gram, Erase etc.). The Command Interface is disabled when the V CC Supply Voltage is less than the Lockout Voltage, VLKO . This prevents Bus Write operations from ac- cidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memo- ry contents being altered will be invalid. A 0.1µF capacitor should be connected between the V CC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, I CC4 . VSS Ground. The VSS Ground is the reference for all voltage measurements.
Table 5. Bus Operations of when the output becomes valid. Enable or Write Enable, whichever occurs last. reduced to the TTL Standby Supply Current, ICC2 . levels see Table 11, DC Characteristics. til the operation completes. Bus Read operation is in progress. ment and are not usually used in applications. ID to be applied to some pins. code, that can be read to identify the memory. listed in Table 5, Bus Operations. unprotected to allow data to be changed.
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB COMMAND INTERFACE All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. Failure to observe a valid sequence of Bus Write operations will result in the memory return- ing to Read mode. The long command sequences are imposed to maximize data security. The commands are summarized in Table 6, Com- mands. Refer to Table 6 in conjunction with the text descriptions below. Read/Reset Command. The Read/Reset com- mand returns the memory to its Read mode where it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. If the Read/Reset command is issued during a Block Erase operation or following a Programming or Erase error then the memory will take upto 10 µs to abort. During the abort period no valid data can be read from the memory. Issuing a Read/Reset command during a Block Erase operation will leave invalid data in the memory. Auto Select Command. The Auto Select com- mand is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are re- quired to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until another com- mand is issued. From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = V IL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Manufacturer Code for STMicroelectronics is 20h. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. The Device Code for the M29F002BT is B0h, the M29F002BNT is B0h and the M29F002BB is 34h. The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, and A13-A17 specifying the address of the block. The other address bits may be set to ei- ther VIL or VIH. If the addressed block is protected then 01h is output on the Data Inputs/Outputs, oth- erwise 00h is output. Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command re- quires four Bus Write operations, the final write op- eration latches the address and data in the internal state machine and starts the Program/Erase Con- troller. If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. During the program operation the memory will ig- nore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 7. Bus Read op- erations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Regis- ter. A Read/Reset command must be issued to re- set the error condition and return to Read mode. Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase Com- mands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. Unlock Bypass Command. The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memo- ry. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these com- mands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been is- sued the memory will only accept the Unlock By- pass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode. Unlock Bypass Program Command. The Un- lock Bypass Program command can be used to program one address in memory at a time. The command requires two Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Pro- gram/Erase Controller. The Program operation using the Unlock Bypass Program command behaves identically to the Pro- gram operation using the Program command. A protected block cannot be programmed; the oper- ation cannot be aborted and the Status Register is read. Errors must be reset using the Read/Reset command, which leaves the device in Unlock By- pass Mode. See the Program command for details on the behavior.
Table 6. Commands Note:X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The Command Interface only uses address bits A0-A10 to verify the commands, the upper address bits are Don’t Care. Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued. Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status. Operations until the Timeout Bit is set. Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands. Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued. on non-erasing blocks as normal. Erase Controller completes and the memory returns to Read Mode. Read/Reset mode from Unlock Bypass Mode. Unlock Bypass Reset command. given when protected blocks are ignored. the Status Register on the Data Inputs/Outputs. set the error condition and return to Read Mode.
timer restarts when an additional block is selected. Controller has started the Block Erase operation. the Status Register on the Data Inputs/Outputs. set the error condition and return to Read mode. data in the selected blocks is lost. blocks for erasure after the Erase Resume. memory to Erase Suspend mode. can be suspended and resumed more than once. Table 7. Program, Erase Times and Program, Erase Endurance Cycles
Table 11. DC Characteristics Note: 1. Excluding the RP input.
- Sampled only, not 100% tested.
Figure 9. Read Mode AC Waveforms Table 12. Read AC Characteristics Note: 1. Sampled only, not 100% tested.
Figure 10. Write AC Waveforms, Write Enable Controlled Table 13. Write AC Characteristics, Write Enable Controlled
Table 14. Write AC Characteristics, Chip Enable Controlled Figure 11. Write AC Waveforms, Chip Enable Controlled
Table 15. Reset/Block Temporary Unprotect AC Characteristics Note: 1. Sampled only, not 100% tested. Figure 12. Reset/Block Temporary Unprotect AC Waveforms
Table 16. Ordering Information Scheme parts, otherwise devices are shipped from the factory with the memory content bits erased to ’1’. vice, please contact the ST Sales Office nearest to you.
Table 17. Revision History
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Outline Note: Drawing is not to scale. PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data Symbol millimeters inches Typ Min Max Typ Min Max A 3.18 3.56 0.125 0.140 A1 1.53 2.41 0.060 0.095 A2 0.38 – 0.015 – B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 CP 0.10 0.004 D 12.32 12.57 0.485 0.495 D1 11.35 11.51 0.447 0.453 D2 4.78 5.66 0.188 0.223 E 14.86 15.11 0.585 0.595 E1 13.89 14.05 0.547 0.553 E2 6.05 6.93 0.238 0.273 F 0.00 0.13 0.000 0.005 N3 2 3 2 PLCC-A D E3 E1 E 1 N CP B e A R 0.51 (.020) 1.14 (.045) F D2 D2
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Outline Note: Drawing is not to scale. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data Symbol millimeters inches Typ Min Max Typ Min Max A 1.20 0.0472 A1 0.05 0.15 0.0020 0.0059 A2 0.95 1.05 0.0374 0.0413 B 0.15 0.27 0.0059 0.0106 C 0.10 0.21 0.0039 0.0083 D 19.80 20.20 0.7795 0.7953 D1 18.30 18.50 0.7205 0.7283 E 7.90 8.10 0.3110 0.3189 L 0.50 0.70 0.0197 0.0276 α 0° 5° 0° 5° N3 2 3 2 CP 0.10 0.0039 TSOP-a E 1 N CP B e A N/2 D DIE C LA1 α
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Outline Note: 1. Drawing is not to scale. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Mechanical Data Symb. mm inches A – 5.08 – 0.2000 A1 0.38 – 0.0150 – A2 3.56 4.06 0.1402 0.1598 B 0.38 0.51 0.0150 0.0201 C 0.20 0.30 0.0079 0.0118 D 41.78 42.04 1.6449 1.6551 E1 13.59 13.84 0.5350 0.5449 eB 15.24 17.78 0.6000 0.7000 L 3.18 3.43 0.1252 0.1350 S 1.78 2.03 0.0701 0.0799 α 0° 10° 0° 10° N3 2 3 2 PDIP A L B1 B e1 D S E1 E N C α eA eBD2
M29F002BT, M29F002BB, M29F002BNT, M29F002BNB Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners © 2002 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.