M29F-200FB

M29F800FT5AN6E2 NUMONYX | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1 Description
• 2 Signal Descriptions
• 2.1 Address Inputs (A0-A19)
• 2.2 Data Inputs/Outputs (DQ0-DQ7)
• 2.3 Data Inputs/Outputs (DQ8-DQ14)
• 2.4 Data Input/Output or Address Input (DQ15A-1)
• 2.5 Chip Enable
• 2.6 Output Enable
• 2.7 Write Enable
• 2.8 Reset/Block Temporary Unprotect
• 2.9 Ready/Busy Output
• 2.10 Byte/Word Organization Select
• 2.12 V SS Ground
• 3 Bus Operations
• 3.1 Bus Read
• 3.2 Bus Write
• 3.3 Output Disable
• 3.4 Standby
• 3.5 Automatic Standby
• 3.6 Special Bus Operations
• 3.7 Electronic Signature
• 3.8 Block Protection and Block Unprotection
• 4 Command Interface
• 4.1 Read/Reset Command
• 4.2 Auto Select Command
• 4.3 Program Command
• 4.4 Unlock Bypass Command
• 4.5 Unlock Bypass Program Command

Features

„ Supply voltage –V CC = 5 V „ Access time: 55 ns „ Program / Erase controller – Embedded byte/word program algorithms „ Erase Suspend and Resume modes „ Low power consumption – Standby and Automatic Standby „ 100,000 Program/Erase cycles per block „ Electronic signature – Manufacturer code: 0x01 – Top Device codes: – M29F200FT: 0x2251 – M29F400FT: 0x2223 – M29F800FT: 0x22D6 – M29F160FT: 0x22D2 – Bottom Device codes: – M29F200FB: 0x2257 – M29F400FB: 0x22AB – M29F800FB: 0x2258 – M29F160FB: 0x22D8 „ RoHS packages available –S O 4 4 – TSOP48 – TFBGA „ Automotive device grade 3: – Temperature: –40 to 125 °C „ Automotive device grade 6: – Temperature: –40 to 85 °C „ Automotive grade certified (AEC-Q100) FBGA TSOP48 (N) 12 x 20 mm SO44 (M) TFBGA48 (ZA) 6 x 8 mm www.numonyx.com

M29FxxxFT, M29FxxxFB Contents

Table 19. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data. . . 45 Table 20. SO44 - 44 lead Plastic Small Outline, 500 mils body width, package mechanical data . . . 46 Table 37. Programmer Technique Bus Operations, BYTE = V

Description M29FxxxFT, M29FxxxFB

1 Description

The following overview of the Numonyx® Axcell™ M29F 5 V Flash Memory device (M29W160F) refers to the 16-Mbit device. However, the information can also apply to lower densities of the M29F device. The M29F160F is a 16 Mbit (2 Mbit x8 or 1 Mbit x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (4.5 to 5.5 V) supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The blocks in the memory are asymmetrically arranged, as shown in Figure 10.: Block Addresses, M29F160 (x8) and Figure 11.: Block Addresses, M29F160 (x16). The first or last 64 KBytes have been divided into four additional blocks. The 16 KByte Boot Block can be used for small initialization code to start the microprocessor, the two 8 KByte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the application may be stored. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered in TSOP48 (12 x 20mm), SO44 , and TFBGA48 (0.8 mm pitch) packages. The memory is supplied with all the bits erased (set to ’1’).

Figure 1. Logic Diagram Table 1. Signal Names

Figure 2. TSOP Connections, M29F160F

Figure 3. TSOP Connections, M29F800F

Figure 4. TSOP Connections, M29F400F

Figure 5. TSOP Connections, M29F200F

Figure 6. SO Connections, M29F800

Figure 7. SO Connections, M29F400

Figure 8. SO Connections, M29F200

Figure 9. TFBGA connections (top view through package)

1. On the M29F800FT/B, A19 is NC (no connect); on the M29F400FT/B, A19-A18 are NC; on M29F200FT/B,

Figure 10. Block Addresses, M29F160 (x8) Also see Appendix Appendix A: Block Address Table for a full listing of the Block Addresses. Figure 11. Block Addresses, M29F160 (x16) Also see Appendix Appendix A: Block Address Table for a full listing of the Block Addresses.

16 KByte

64 KByte

32 KByte

64 KByt e Bl ocks

8 KByt e

8 KWord

32 KWord

16 KWord

32 KWord Bl ocks

4 KWord

Figure 12. Block Addresses, M29F800 (x8) Also see Appendix Appendix A: Block Address Table for a full listing of the Block Addresses. Figure 13. Block Addresses, M29F800 (x16) Also see Appendix Appendix A: Block Address Table for a full listing of the Block Addresses.

Figure 14. Block Addresses, M29F400 (x8) Also see Appendix Appendix A: Block Address Table for a full listing of the Block Addresses. Figure 15. Block Addresses, M29F400 (x16) Also see Appendix Appendix A: Block Address Table for a full listing of the Block Addresses.

Figure 16. Block Addresses, M29F200 (x8) Also see Appendix Appendix A: Block Address Table for a full listing of the Block Addresses. Figure 17. Block Addresses, M29F200 (x16) Also see Appendix Appendix A: Block Address Table for a full listing of the Block Addresses.

Signal Descriptions M29FxxxFT, M29FxxxFB

2 Signal Descriptions

See Figure 1.: Logic Diagram and Table 1.: Signal Names, for a brief overview of the signals connected to this device.

2.1 Address Inputs (A0-A19)

The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller.

2.2 Data Inputs/O utputs (DQ0-DQ7)

The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the Program/Erase Controller.

2.3 Data Inputs/Outputs (DQ8-DQ14)

The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored.

2.4 Data Input/Output or Address Input (DQ15A-1)

When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of the Word on the other addresses, DQ15A–1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except when stated explicitly otherwise.

2.5 Chip Enable

The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored.

2.6 Output Enable

The Output Enable, G, controls the Bus Read operation of the memory.

M29FxxxFT, M29FxxxFB Signal Descriptions

2.7 Write Enable

The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.

2.8 Reset/Block Te mporary Unprotect

The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected. A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See the Ready/Busy Output section, Table 18.: Reset/Block Temporary Unprotect AC Characteristics and Figure 23.: Reset/Block Temporary Unprotect AC Waveforms. Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH.

2.9 Ready/Busy Output

The Ready/Busy pin is an open-drain output that can be used to identify when the device is performing a Program or Erase operation. During Program or Erase operations Ready/Busy is Low, V OL. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 18.: Reset/Block Temporary Unprotect AC Characteristics and Figure 23.: Reset/Block Temporary Unprotect AC Waveforms. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy.

2.10 Byte/Word Organization Select

The Byte/Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus modes of the memory. When Byte/Word Organization Select is Low, V IL, the memory is in 8- bit mode, when it is High, VIH, the memory is in 16-bit mode.

2.11 V CC Supply Voltage

The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid.

Signal Descriptions M29FxxxFT, M29FxxxFB A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, I CC3.

2.12 V SS Ground

The VSS Ground is the reference for all voltage measurements. The two VSS pins of the device must be connected to the system ground.

M29FxxxFT, M29FxxxFB Bus Operations

3 Bus Operations

There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See Table 2.: Bus Operations, BYTE = VIL and Table 3.: Bus Operations, BYTE = VIH for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.

3.1 Bus Read

Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, V IL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 20.: Read Mode AC Waveforms and Table 15.: Read AC Characteristics, for details of when the output becomes valid.

3.2 Bus Write

Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V IH, during the whole Bus Write operation. See the following figures and tables: „ Figure 21.: Write AC Waveforms, Write Enable Controlled „ Figure 22.: Write AC Waveforms, Chip Enable Controlled, „ Table 16.: Write AC Characteristics, Write Enable Controlled „ Table 17.: Write AC Characteristics, Chip Enable Controlled.

3.3 Output Disable

The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.

3.4 Standby

When Chip Enable is High, VIH, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the Standby Supply Current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the Standby current level see Table 14.: DC Characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations until the operation completes.

Bus Operations M29FxxxFT, M29FxxxFB

3.5 Automatic Standby

If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress.

3.6 Special Bus Operations

Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins.

3.7 Electronic Signature

The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Table 2.: Bus Operations, BYTE = VIL and Table 3.: Bus Operations, BYTE = VIH.

3.8 Block Protection and Block Unprotection

Each block can be separately protected against accidental Program or Erase. Protected blocks can be unprotected to allow data to be changed. There are two methods available for protecting and unprotecting the blocks, one for use on programming equipment and the other for in-system use. Block Protect and Blocks Unprotect operations are described in Appendix C: Block protection.

Table 2. Bus Operations, BYTE = VIL Table 3. Bus Operations, BYTE = VIH

Command Interface M29FxxxFT, M29FxxxFB

4 Command Interface

All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. The address used for the commands changes depending on whether the memory is in 16- bit or 8-bit mode. See either Table 4.: Commands, 16-bit mode, BYTE = VIH, or Table 5.: Commands, 8-bit mode, BYTE = VIL, depending on the configuration that is being used, for a summary of the commands.

4.1 Read/Reset Command

The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM, unless otherwise stated. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. The Read/Reset Command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to read mode. Once the program or erase operation has started the Read/Reset command is no longer accepted. The Read/Reset command will not abort an Erase operation when issued while in Erase Suspend.

4.2 Auto Select Command

The Auto Select command is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until a Read/Reset command is issued. Read CFI Query and Read/Reset commands are accepted in Auto Select mode, all other commands are ignored. From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = V IL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Manufacturer Code for Numonyx is 0001h. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, and A12-A19 specifying the address of the block. The other address bits may be set to either VIL or VIH. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output.

4.3 Program Command

The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data, and starts the Program/Erase Controller. If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given.

M29FxxxFT, M29FxxxFB Command Interface During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 6.: Program/Erase Times and Program/Erase Endurance Cycles, M29F160F. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the program operation has completed the memory returns to the Read mode, unless an error has occurred. When an error occurs the memory continues to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

4.4 Unlock Bypass Command

The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode.

4.5 Unlock Bypass Program Command

The Unlock Bypass Program command can be used to program one address in memory at a time. The command requires two Bus Write operations, the final write operation latches the address and data, and starts the Program/Erase Controller. The Program operation using the Unlock Bypass Program command behaves identically to the Program operation using the Program command. A protected block cannot be programmed; the operation cannot be aborted and the Status Register is read. Errors must be reset using the Read/Reset command, which leaves the device in Unlock Bypass Mode. See the Program command for details on the behavior.

4.6 Unlock Bypass Reset Command

The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Read/Reset command does not exit from Unlock Bypass Mode.

4.7 Chip Erase Command

The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate

Command Interface M29FxxxFT, M29FxxxFB within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 6.: Program/Erase Times and Program/Erase Endurance Cycles, M29F160F. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost.

4.8 Block Erase Command

The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller about 50µs after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register section for details on how to identify if the Program/Erase Controller has started the Block Erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the Block Erase operation the memory will ignore all commands except the Erase Suspend command. Typical block erase times are given in Table 6.: Program/Erase Times and Program/Erase Endurance Cycles, M29F160F. All Bus Read operations during the Block Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is lost.

4.9 Erase Suspend Command

The Erase Suspend Command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus Write operation.

M29FxxxFT, M29FxxxFB Command Interface The Program/Erase Controller will suspend within the Erase Suspend Latency Time (refer to Table 6.: Program/Erase Times and Program/Erase Endurance Cycles, M29F160F for value) of the Erase Suspend Command being issued. Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume Command is issued. It is not possible to select any further blocks to erase after the Erase Resume. During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. If any attempt is made to program in a protected block or in the suspended block then the Program command is ignored and the data remains unchanged. The Status Register is not read and no error condition is given. Reading from blocks that are being erased will output the Status Register. It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands during an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command will be accepted.

4.10 Erase Resume Command

The Erase Resume command must be used to restart the Program/Erase Controller from Erase Suspend. An erase can be suspended and resumed more than once.

4.11 Read CFI Query Command

The Read CFI Query Command is used to read data from the Common Flash Interface (CFI) Memory Area. This command is valid when the device is in the Read Array mode, or when the device is in Auto Select mode. One Bus Write cycle is required to issue the Read CFI Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. The Read/Reset command must be issued to return the device to the previous mode (the Read Array mode or Auto Select mode). A second Read/Reset command would be needed if the device is to be put in the Read Array mode from Auto Select mode. See Appendix B: Common Flash Interface (CFI) and the following tables for details on the information contained in the Common Flash Interface (CFI) memory area. „ Table 31.: Query Structure Overview, „ Table 32.: CFI Query Identification String, „ Table 33.: CFI Query System Interface Information, „ Table 34.: Device Geometry Definition, „ Table 35.: Primary Algorithm-Specific Extended Query Table „ Table 36.: Security Code Area

Table 4. Commands, 16-bit mode, BYTE = VIH X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH. Read/Reset: After a Read/Reset command, read the memory as normal until another command is issued. Auto Select: After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status. Command with additional Bus Write Operations until Timeout Bit is set. Unlock Bypass: After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands. Unlock Bypass Reset: After the Unlock Bypass Reset command read the memory as normal until another command is issued. Program commands on non-erasing blocks as normal. Program/Erase Controller completes and the memory returns to Read Mode. CFI Query: Command is valid when device is ready to read array data or when device is in Auto Select mode.

Table 5. Commands, 8-bit mode, BYTE = VIL X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH. Read/Reset: After a Read/Reset command, read the memory as normal until another command is issued. Auto Select: After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status. Command with additional Bus Write Operations until Timeout Bit is set. Unlock Bypass: After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands. Unlock Bypass Reset: After the Unlock Bypass Reset command read the memory as normal until another command is issued. Program commands on non-erasing blocks as normal. Program/Erase Controller completes and the memory returns to Read Mode. CFI Query: Command is valid when device is ready to read array data or when device is in Auto Select mode.

3 AAA AA 555 55 X F0

Table 6. Program/Erase Times and Program/Erase Endurance Cycles, M29F160F and VCC after 100,000 program/erase cycles. Table 7. Program/Erase Times and Program/Erase Endurance Cycles, M29F800F and VCC after 100,000 program/erase cycles.

Table 8. Program/Erase Times and Program/Erase Endurance Cycles, M29F400F and VCC after 100,000 program/erase cycles. Table 9. Program/Erase Times and Program/Erase Endurance Cycles, M29F200F and VCC after 100,000 program/erase cycles.

5 Status Register

The bits in the Status Register are summarized in Table 10.: Status Register Bits.

5.1 Data Polling Bit

Data Polling Bit is output on DQ7 when the Status Register is read. Program/Erase Controller has suspended the Erase operation. Figure 1. Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A

5.2 Toggle Bit

Bit is output on DQ6 when the Status Register is read. operation the memory returns to Read mode. suspended the Erase operation. DQ6 toggles for approximately 1µs. Figure 2. Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit.

M29FxxxFT, M29FxxxFB Status Register

5.3 Error Bit

The Error Bit (DQ5) can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’. One of the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’

5.4 Erase Timer Bit

The Erase Timer Bit (DQ3) can be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit is set to ’0’ and additional blocks to be erased may be written to the Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is read.

5.5 Alternative Toggle Bit

The Alternative Toggle Bit (DQ2) can be used to monitor the Program/Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory cell data as if in Read mode. After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle Bit does not change if the addressed block has erased correctly.

Table 10. Status Register Bits Unspecified data bits should be ignored. Figure 1. Data Polling Flowchart

Figure 2. Data Toggle Flowchart

6 Maximum Rating

Program and other relevant quality documents. Table 11. Absolute Maximum Ratings than 20ns during transitions.

7 DC and AC Parameters

follow, are derived from tests performed under the Measurement Conditions shown here. conditions when relying on the quoted parameters. Table 12. Operating and AC Measurement Conditions Figure 18. AC Measurement I/O Waveform Figure 19. AC Measurement Load Circuit

Table 13. Device Capacitance Sampled only, not 100% tested. Table 14. DC Characteristics Supply Current (Program/Erase) parameter: Sampled only, not 100% tested. Figure 20. Read Mode AC Waveforms

Table 15. Read AC Characteristics tELQX tGLQX tEHQZ and tGHQZ parameters: Sampled only, not 100% tested. Figure 21. Write AC Waveforms, Write Enable Controlled

Table 16. Write AC Characteristics, Write Enable Controlled tWHRL parameter: Sampled only, not 100% tested. Figure 22. Write AC Waveforms, Chip Enable Controlled

Table 17. Write AC Characterist ics, Chip Enable Controlled tEHRL parameter: Sampled only, not 100% tested. Figure 23. Reset/Block Temporary Unprotect AC Waveforms

Table 18. Reset/Block Temporary Unprotect AC Characteristics tPHWL tPHGL tRHWL tRHEL tRHGL tPLYH and tPHPHH parameters: Sampled only, not 100% tested.

8 Package Mechanical

Figure 24. TSOP48 – 48 lead Plastic Thi n Small Outline, 12 x 20mm, Package Table 19. TSOP48 – 48 lead Plastic Thi n Small Outline, 12 x 20mm, Package

Figure 25. SO44 – 44 lead plastic small ou tline, 500 mils body width, package outline Table 20. SO44 - 44 lead Plastic Small Outline, 500 mils body width, package

Figure 26. TFBGA48 6 x 8 mm - 6 x 8 ball array, 0.80 mm pitch, package outline Table 21. TFBGA48 6 x 8 mm - 6 x 8 ball arra y, 0.80 mm pitch, package mechanical

9 Part Numbering

Devices are shipped from the factory with the memory content bits erased to ’1’. of this device, please contact the Numonyx Sales Office nearest to you. Table 22. Information scheme

1. THis package is avail able only in the 8-Mbit, bottom boot configuration.

Table 23. Top Boot Block Addresses, M29F160FT

Table 24. Bottom Boot Block Addresses, M29F160FB

Table 25. Top Boot Block Addresses, M29F800FT

Table 26. Bottom Boot Block Addresses, M29F800FB

Table 27. Top Boot Block Addresses, M29F400FT

Table 28. Bottom Boot Block Addresses, M29F400FB

Table 29. Top Boot Block Addresses, M29F200FT Table 30. Bottom Boot Block Addresses, M29F200FB

software to upgrade itself when necessary. written by Numonyx. Issue a Read command to return to Read mode. Table 31. Query Structure Overview Query data are always presented on the lowest order data outputs. Table 32. CFI Query Identification String

Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’. Table 33. CFI Query System Interface Information Table 34. Device Geometry Definition

2 MByte

Table 35. Primary Algorithm-Specific Extended Query Table Number of Erase Block Regions within the device. contiguous Erase Blocks of the same size.

Table 36. Security Code Area

Block protection M29FxxxFT, M29FxxxFB Appendix C Block protection Block protection can be used to prevent any operation from modifying the data stored in the Flash memory. Each Block can be protected individually. Once protected, Program and Erase operations on the block fail to change the data. There are three techniques that can be used to control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is described in the Signal Descriptions section. Unlike the Command Interface of the Program/Erase Controller, the techniques for protecting and unprotecting blocks could change between different Flash memory suppliers. C.1 Programmer Technique The Programmer technique uses high (VID) voltage levels on some of the bus pins. These cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in Programming Equipment. To protect a block follow the flowchart in Figure 27.: Programmer Equipment Block Protect Flowchart. During the Block Protect algorithm, the A19-A12 Address Inputs indicate the address of the block to be protected. The block will be correctly protected only if A19-A12 remain valid and stable, and if Chip Enable is kept Low, V IL, all along the Protect and Verify phases. The Chip Unprotect algorithm is used to unprotect all the memory blocks at the same time. This algorithm can only be used if all of the blocks are protected first. To unprotect the chip follow Figure 28.: Programmer Equipment Chip Unprotect Flowchart and Table 37.: Programmer Technique Bus Operations, BYTE = VIH or VIL, which give a summary of each operation. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing. C.2 In-System Technique The In-System technique requires a high voltage level on the Reset/Blocks Temporary Unprotect pin, RP . This can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the Flash memory has been fitted to the system. To protect a block follow the flowchart in Figure 29.: In-System Equipment Block Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the blocks first, then all the blocks can be unprotected at the same time. To unprotect the chip follow Figure 30.: In-System Equipment Chip Unprotect Flowchart. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not allow the microprocessor to service interrupts that will upset the timing and do not abort the procedure before reaching

to show that the operation is progressing. Table 37. Programmer Technique Bus Operations, BYTE = VIH or VIL

Figure 27. Programmer Equipment Block Protect Flowchart stable during the operation. During the Protect and Verify phases of the algorithm, Chip Enable E must be kept Low, VIL.

Figure 28. Programmer Equipment Chip Unprotect Flowchart

Figure 29. In-System Equipment Block Protect Flowchart

Figure 30. In-System Equipment Chip Unprotect Flowchart

Table 38. Document Revision History Devices are shipped from the factory with the memory content bits erased to ’1’. of this device, please contact the Numonyx Sales Office nearest to you. 30-March-2009 1 Initial release. Changed read manufacturer code and read device code to TBD. Added 55 ns option to speed option in Ordering Information table. – “inches” from package manufacturing tables. Added additional speed and packing information to Ordering Information. 13-Aug-2009 5 TFBGA48 6 x 8 mm package added. – Added / revised details in Order Information table. – Removed “preliminary data” statement throughout the document. In Table 14.: DC Characteristics, changed VIH from 0.8 V to 0.7 V. 8-Feb-2010 8 Minor text edits. Section 4.2: Auto Select Command on page 26.