M29DW323DT NUMONYX | Alldatasheet

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32 Mbit (4Mb x8 or 2Mb x16, Dual Bank 8:24, Boot Block)

Figure 1. Packages

Banks, A and B, providing Dual Bank operations. erations are possible in Bank B and vice versa. Parameter Blocks starting from the bottom. the protection cannot be undone. memory is consistent with JEDEC standards. nals control the bus operation of the memory. cessors, often without additional logic. Figure 2. Logic Diagram Table 1. Signal Names

Figure 3. TSOP Connections

Figure 4. TFBGA48 Connections (Top view through package) Table 2. Bank Architecture

Figure 5. Block Addresses (x8) Note: Also see APPENDIX A., Table 23. and Table 24. for a full listing of the Block Addresses.

64 KByte or

32 KWord

8 KByte or

4 KWord

Note 1. Used as Extended Block Addresses in Extended Block mode.

Figure 6. Block Addresses (x16) Note: Also see APPENDIX A., Table 23. and Table 24. for a full listing of the Block Addresses. Note 1. Used as Extended Block Addresses in Extended Block mode.

M29DW323DT, M29DW323DB SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram , and Table 1., Signal Names, for a brief overview of the sig- nals connected to this device. Address Inputs (A0-A20). The Address Inputs select the cells in the memory array to access dur- ing Bus Read operations. During Bus Write opera- tions they control the commands sent to the Command Interface of the Program/Erase Con- troller. Data Inputs/Outputs (DQ0-DQ7). The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the Program/Erase Controller. Data Inputs/Outputs (DQ8-DQ14). The Data I/O outputs the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, V IL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. Data Input/Output or Address Input (DQ15A–1). When BYTE is High, V IH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of the ad- dressed Word, DQ15A–1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to in- clude this pin when BYTE is Low except when stated explicitly otherwise. Chip Enable (E). The Chip Enable, E , activates the memory, allowing Bus Read and Bus Write op- erations to be performed. When Chip Enable is High, VIH, all other pins are ignored. Output Enable (G). The Output Enable, G , con- trols the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory’s Com- mand Interface. VPP/Write Protect (VPP/WP). The V PP/Write Protect pin provides two functions. The V PP func- tion allows the memory to use an external high voltage power supply to reduce the time required for Program operations. This is achieved by by- passing the unlock cycles and/or using the Dou- ble Word or Quadruple Byte Program commands. The Write Protect function provides a hardware method of protecting the two outermost boot blocks. When V PP/Write Protect is Low, V IL, the memory protects the two outermost boot blocks; Program and Erase operations in t hese blocks are ignored while VPP/Write Protect is Low, even when RP is at VID. When VPP/Write Protect is High, VIH, the memory reverts to the previous protection status of the two outermost boot blocks. Program and Erase oper- ations can now modify the data in these blocks un- less the blocks are pr otected using Block Protection. When V PP/Write Protect is raised to VPP the mem- ory automatically enters the Unlock Bypass mode. When VPP/Write Protect returns to VIH or VIL nor- mal operation resumes. During Unlock Bypass Program operations the memory draws I PP from the pin to supply the programming circuits. See the description of the Unlock Bypass command in the Command Interface section. The transitions from V IH to V PP and from V PP to V IH must be slower than tVHVPP, see Figure 17. Never raise V PP/Write Protect to V PP from any mode except Read mode, otherwise the memory may be left in an indeterminate state. The VPP/Write Protect pin must not be left floating or unconnected or the device may become unreli- able. A 0.1µF capacitor should be connected be- tween the V PP/Write Protect pin and the V SS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Unlock Bypass Program, I PP. Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected. Note that if V PP/WP is at V IL, then the two outer- most boot blocks will remain protected even if RP is at VID. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, V IL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after t PHEL or tRHEL, whichever occurs last. See the Ready/Busy Output section, Table 19. and Figure 16., Reset/ Block Temporary Unprotect AC Waveforms , for more details. Holding RP at V ID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all bl ocks will be possible. The transition from V IH to VID must be slower than tPHPHH. Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the device is performing a Program or Erase

M29DW323DT, M29DW323DB operation. During Program or Erase operations Ready/Busy is Low, V OL. Ready/Busy is high-im- pedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy be- comes high-impedance. See Table 19. and Figure 16., Reset/Block Temporary Unprotect AC Wave- forms. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Byte/Word Organization Select (BYTE ). The Byte/Word Organization Select pin is used to switch between the x8 and x16 Bus modes of the memory. When Byte/Word Organization Select is Low, V IL, the memory is in x8 mode, when it is High, VIH, the memory is in x16 mode. VCC Supply Voltage (2.7V to 3.6V). VCC pro- vides the power supply fo r all operations (Read, Program and Erase). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from ac- cidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memo- ry contents being altered will be invalid. A 0.1µF capacitor should be connected between the V CC Supply Voltage pin and the V SS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Program and Erase operations, I CC3. VSS Ground. VSS is the reference for all voltage measurements. The device features two VSS pins which must be both connected to the system ground.

M29DW323DT, M29DW323DB BUS OPERATIONS There are five standard bus operations that control the device. These are Bus Read, Bus Write, Out- put Disable, Standby and Automatic Standby. The Dual Bank architecture of the M29DW323 al- lows read/write operations in Bank A, while read operations are being executed in Bank B or vice versa. Write operations are only allowed in one bank at a time. See Tables 3 and 4, Bus Operations, for a summa- ry. Typically glitches of less than 5ns on Chip En- able or Write Enable are ignored by the memory and do not affect bus operations. Bus Read. Bus Read operations read from the memory cells, or specif ic registers in the Com- mand Interface. A valid Bus Read operation in- volves setting the desired address on the Address Inputs, applying a Low signal, V IL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 11., Read Mode AC Waveforms, and Table 15., Read AC Characteristics , for de- tails of when the output becomes valid. Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Ad- dress Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Com- mand Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output En- able must remain High, V IH, during the whole Bus Write operation. See Figures 12 and 13, Write AC Waveforms, and Tables 16 and 17, Write AC Characteristics, for detai ls of the timing require- ments. Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH. Standby. When Chip Enable is High, V IH, the memory enters Standby mode and the Data In- puts/Outputs pins are placed in the high-imped- ance state. To reduce the Supply Current to the Standby Supply Current, I CC2, Chip Enable should be held within VCC ± 0.2V. For the Standby current level see Table 14., DC Characteristics. During program or eras e operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations un- til the operation completes. Automatic Standby. If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 300ns or more the memory enters Automatic Standby where the internal Supply Current is re- duced to the Standby Supply Current, I CC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Special Bus Operations Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus opera- tions are intended for use by programming equip- ment and are not usually used in applications. They require V ID to be applied to some pins. Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Tables 3 and 4, Bus Operations. Block Protect and Chip Unprotect.Groups of blocks can be protect ed against accidental Pro- gram or Erase. The Protection Groups are shown in APPENDIX A. , Tables 23 and 24, Block Ad- dresses. The whole chip can be unprotected to al- low the data inside the blocks to be changed. The V PP/Write Protect pin can be used to protect the two outermost boot blocks. When V PP/Write Protect is at VIL the two outermost boot blocks are protected and remain protected regardless of the Block Protection Status or the Reset/Block Tem- porary Unprotect pin status. Block Protect and Chip U nprotect operations are described in APPENDIX D.

Table 3. Bus Operations, BYTE = VIL Table 4. Bus Operations, BYTE = VIH

M29DW323DT, M29DW323DB COMMAND INTERFACE All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. Failure to observe a valid sequence of Bus Write operations will result in the memory return- ing to Read mode. The long command sequences are imposed to maximize data security. The address used for the commands changes de- pending on whether the memory is in 16-bit or 8- bit mode. See either Table 5, or 6, depending on the configuration that is being used, for a summary of the commands. Read/Reset Command The Read/Reset command returns the memory to its Read mode. It also resets the errors in the Sta- tus Register. Either one or three Bus Write opera- tions can be used to issue the Read/Reset command. The Read/Reset command can be issued, be- tween Bus Write cycles before the start of a pro- gram or erase operation, to return the device to read mode. If the Read/Reset command is issued during the time-out of a Block erase operation then the memory will take up to 10µs to abort. During the abort period no valid data can be read from the memory. The Read/Reset command will not abort an Erase operation when issued while in Erase Suspend. Auto Select Command The Auto Select command is used to read the Manufacturer Code, the Device Code, the Block Protection Status and the Extended Memory Block Verify Code. It can be addressed to either Bank. Three consecutive Bus Wr ite operations are re- quired to issue the Auto Select command. The fi- nal Write cycle must be addressed to one of the Banks. Once the Auto Select command is issued Bus Read operations to the Bank where the com- mand was issued output the Auto Select data. Bus Read operations to the other Bank will output the contents of the memory array. The memory re- mains in Auto Select mode until a Read/Reset or CFI Query command is issued. In Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = V IL and A1 = V IL and A19-A20 = Bank Address. The other address bits may be set to either VIL or VIH. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL and A19-A20 = Bank Address. The other address bits may be set to either VIL or VIH. The Block Protection Status of each block can be read using a Bus Read operation with A0 = V IL, A1 = VIH, A19-A20 = Bank Address and A12-A18 specifying the address of the block inside the Bank. The other address bits may be set to either VIL or VIH. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output. Read CFI Query Command The Read CFI Query Command is used to read data from the Common Flash Interface (CFI) Memory Area. This command is valid when the de- vice is in the Read Array mode, or when the device is in Auto Select mode. One Bus Write cycle is required to issue the Read CFI Query Command. Once the command is is- sued subsequent Bus Read operations read from the Common Flash Interface Memory Area. The Read/Reset command must be issued to re- turn the device to the previous mode (the Read Ar- ray mode or Auto Select mode). A second Read/ Reset command would be needed if the device is to be put in the Read Array mode from Auto Select mode. See APPENDIX B., Tables 25, 26, 27, 28, 29 and 30 for details on the information contained in the Common Flash Interface (CFI) memory area. Program Command The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write oper- ations, the final write operation latches the ad- dress and data, and starts the Program/Erase Controller. If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. During the program operati on the memory will ig- nore all commands. It is not possible to issue any command to abort or pause the operation. After programming has started, Bus Read operations in the Bank being programmed output the Status Register content, while Bus Read operations to the other Bank output the contents of the memory array. See the section on the Status Register for more details. Typical program times are given in Table 7. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs Bus Read operations to the Bank where the command was issued will continue to output the Status Reg- ister. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase Com- mands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

M29DW323DT, M29DW323DB Fast Program Commands There are two Fast Program commands available to improve the programming throughput, by writing several adjacent words or bytes in parallel. The Quadruple Byte Program command is available for x8 operations, while the Double Word Program command is available for x16 operations. Only one bank can be programmed at any one time. The other bank must be in Read mode or Erase Suspend. Fast Program commands should not be attempted when V PP/WP is not at V PP. Care must be taken because applying a 12V V PP voltage to the VPP/ WP pin will temporarily unprotect any protected block. After programming has started, Bus Read opera- tions in the Bank being programmed output the Status Register content, while Bus Read opera- tions to the other Bank output the contents of the memory array. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs Bus Read operations to the Bank where the command was issued will continue to output the Status Reg- ister. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Fast Program commands cannot change a bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. Typical Program times are given in Table 7., Program, Erase Times and Program, Erase Endurance Cycles. Quadruple Byte Program Command. The Qua- druple Byte Program command is used to write a page of four adjacent Bytes in parallel. The four bytes must differ only for addresses A0, DQ15A-1. Five bus write cycles are necessary to issue the Quadruple Byte Program command. ■ The first bus cycle sets up the Quadruple Byte Program Command. ■ The second bus cycle latches the Address and the Data of the first byte to be written. ■ The third bus cycle latches the Address and the Data of the second byte to be written. ■ The fourth bus cycle latches the Address and the Data of the third byte to be written. ■ The fifth bus cycle latches the Address and the Data of the fourth byte to be written and starts the Program/Erase Controller. Double Word Program Command. The Double Word Program command is used to write a page of two adjacent words in parallel. The two words must differ only for the address A0. Three bus write cycles are necessary to issue the Double Word Program command. ■ The first bus cycle sets up the Double Word Program Command. ■ The second bus cycle latches the Address and the Data of the first word to be written. ■ The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller. Unlock Bypass Command The Unlock Bypass command is used in conjunc- tion with the Unlock Bypass Program command to program the memory faster than with the standard program commands. When the cycle time to the device is long, consider able time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock By- pass command. Once the Unlock Bypass command has been is- sued the bank enters Unlock Bypass mode. When in Unlock Bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. The Unlock Bypass Program command can be issued to program addresses within the bank, and the Unlock Bypass Reset command to return the bank to Read mode. In Unlock Bypass mode the memory can be read as if in Read mode. When V PP is applied to the V PP/Write Protect pin the memory automatically enters the Unlock By- pass mode and the Unlock Bypass Program com- mand can be issued immediately. Care must be taken because applying a 12V V PP voltage to the VPP/WP pin will temporarily unprotect any protect- ed block. Unlock Bypass Program Command The Unlock Bypass Program command can be used to program one address in the memory array at a time. The command requires two Bus Write operations, the final write operation latches the ad- dress and data, and starts the Program/Erase Controller. The Program operation using the Unlock Bypass Program command behaves identically to the Pro- gram operation using the Program command. The operation cannot be aborted, a Bus Read opera- tion to the Bank where the command was issued outputs the Status Register. See the Program command for details on the behavior. Unlock Bypass Reset Command The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Read/ Reset command does not exit from Unlock Bypass Mode.

M29DW323DT, M29DW323DB Chip Erase Command The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are re- quired to issue the Chip Erase Command and start the Program/Erase Controller. If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation ap- pears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands, including the Erase Suspend com- mand. It is not possible to issue any command to abort the operation. Typica l chip erase times are given in Table 7. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the sec- tion on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Regis- ter. A Read/Reset command must be issued to re- set the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in un- protected blocks of the memory to ’1’. All previous data is lost. Block Erase Command The Block Erase command can be used to erase a list of one or more blocks in a Bank. It sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is lost. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. All blocks must belong to the same Bank; if a block belonging to the other Bank is given it will not be erased. The Block Erase operation starts the Program/Erase Controller after a time-out pe- riod of 50µs after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each addition- al block must therefore be selected within 50µs of the last block. The 50µs timer restarts when an ad- ditional block is selected. After the sixth Bus Write operation a Bus Read operation within the same Bank will output the Status Register. See the Sta- tus Register section for details on how to identify if the Program/Erase Controller has started the Block Erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100µs, leaving the data un- changed. No error condition is given when protect- ed blocks are ignored. During the Block Erase operation the memory will ignore all commands except the Erase Suspend command and the Read/Reset command which is only accepted during the 50µs time-out period. Typical block erase times are given in Table 7. After the Erase operation has started all Bus Read operations to the Bank being erased will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs Bus Read operations to the Bank where the command was issued will continue to output the Status Reg- ister. A Read/Reset command must be issued to reset the error condition and return to Read mode. Erase Suspend Command The Erase Suspend Command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus Write operation. The Program/Erase Controller will suspend within the Erase Suspend Latency time of the Erase Sus- pend Command being issued. Once the Program/ Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspend- ed. If the Erase Suspend command is issued dur- ing the period when the memory is waiting for an additional block (before the Program/Erase Con- troller starts) then the Erase is suspended immedi- ately and will start immediately when the Erase Resume Command is issued. It is not possible to select any further blocks to erase after the Erase Resume. During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. If any attempt is made to program in a protected block or in the suspended block then the Program command is ignored and the data remains unchanged. The Status Register is not read and no error co ndition is given. Read- ing from blocks that are being erased will output the Status Register. It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands during an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command will be ac- cepted. During Erase Suspend a Bus Read operation to the Extended Block will output the Extended Block data.

Boot Block addresses access the Extended Block. tended Block command must be issued. once protected the protection cannot be undone. required to issue the command. ations are described in APPENDIX D. Table 5. Commands, 16-bit mode, BYTE Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.

Table 6. Commands, 8-bit mode, BYTE = VIL Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH. Table 7. Program, Erase Times and Program, Erase Endurance Cycles Note: 1. Typical values measured at room temperature and nominal voltages.

  1. Sampled, but not 100% tested.
  2. Maximum value measured at worst case conditions for both temperature and V CC after 100,00 program/erase cycles.
  3. Maximum value measured at worst case conditions for both temperature and V CC.

3 AAA AA 555 55 X F0

Table 8. Status Register Bits Note: Unspecified data bits should be ignored. Figure 7. Data Polling Flowchart Figure 8. Toggle Flowchart Note: BA = Address of Bank being Programmed or Erased.

are possible in the other bank with zero latency. erations are possible at any moment. Table 9. and Table 10. show the dual operations possible in other banks and in the same bank. represented in these tables. Table 9. Dual Operations Allowed In the Other Bank Note: 1. If one bank is involved in a program or erase operat ion, then the other bank is available for dual operations.

  1. Only after an Erase operation in that bank.
  2. Only after an Erase Suspend command in that bank.

Table 10. Dual Operations Allowed In Same Bank Note: 1. Not allowed in the Block or Word that is being erased or programmed.

  1. Only after an Erase operation in that bank.
  2. Only after an Erase Suspend command in that bank.
  3. Read Status Register is not a command. The Status Register can be read during a block program or erase operation.
  4. The Status Register can be read by addressing the block being erase suspended.

gram and other relevant quality documents. Table 11. Absolute Maximum Ratings Hazardous Substances (RoHS) 2002/95/EU.

  1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.
  2. Maximum voltage may overshoot to V CC +2V during transition and for less than 20ns during transitions.
  3. V PP must not remain at 12V for more than a total of 80hrs.

ing on the quoted parameters. Table 12. Operating and AC Measurement Conditions Figure 9. AC Measurement I/O Waveform Figure 10. AC Measurement Load Circuit Table 13. Device Capacitance Note: Sampled only, not 100% tested.

Table 14. DC Characteristics Note: 1. Sampled only, not 100% tested.

  1. In Dual operations the Supply Current will be the sum of ICC1(read) and ICC3 (program/erase).

Figure 11. Read Mode AC Waveforms Table 15. Read AC Characteristics Note: 1. Sampled only, not 100% tested.

Figure 12. Write AC Waveforms, Write Enable Controlled Table 16. Write AC Characteristics, Write Enable Controlled Note: 1. Sampled only, not 100% tested.

Figure 13. Write AC Waveforms, Chip Enable Controlled Table 17. Write AC Characteristics, Chip Enable Controlled Note: 1. Sampled only, not 100% tested.

Figure 18. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View Package Outline Table 20. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data

Figure 19. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline Table 21. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data

Table 22. Ordering Information Scheme information contact your nearest Numonyx sales office. Devices are shipped from the factory with the memory content bits erased to ’1’. please contact the Numonyx Sales Office nearest to you.

Table 23. Top Boot Block Addresses, M29DW323DT

M29DW323DT, M29DW323DB Bank B 32 64/32 Protection Group 200000h–20FFFFh 100000h–107FFFh 33 64/32 210000h–21FFFFh 108000h–10FFFFh 34 64/32 220000h–22FFFFh 110000h–117FFFh 35 64/32 230000h–23FFFFh 118000h–11FFFFh 36 64/32 Protection Group 240000h–24FFFFh 120000h–127FFFh 37 64/32 250000h–25FFFFh 128000h–12FFFFh 38 64/32 260000h–26FFFFh 130000h–137FFFh 39 64/32 270000h–27FFFFh 138000h–13FFFFh 40 64/32 Protection Group 280000h–28FFFFh 140000h–147FFFh 41 64/32 290000h–29FFFFh 148000h–14FFFFh 42 64/32 2A0000h–2AFFFFh 150000h–157FFFh 43 64/32 2B0000h–2BFFFFh 158000h–15FFFFh 44 64/32 Protection Group 2C0000h–2CFFFFh 160000h–167FFFh 45 64/32 2D0000h–2DFFFFh 168000h–16FFFFh 46 64/32 2E0000h–2EFFFFh 170000h–177FFFh 47 64/32 2F0000h–2FFFFFh 178000h–17FFFFh Bank A 48 64/32 Protection Group 300000h–30FFFFh 180000h–187FFFh 49 64/32 310000h–31FFFFh 188000h–18FFFFh 50 64/32 320000h–32FFFFh 190000h–197FFFh 51 64/32 330000h–33FFFFh 198000h–19FFFFh 52 64/32 Protection Group 340000h–34FFFFh 1A0000h–1A7FFFh 53 64/32 350000h–35FFFFh 1A8000h–1AFFFFh 54 64/32 360000h–36FFFFh 1B0000h–1B7FFFh 55 64/32 370000h–37FFFFh 1B8000h–1BFFFFh 56 64/32 Protection Group 380000h–38FFFFh 1C0000h–1C7FFFh 57 64/32 390000h–39FFFFh 1C8000h–1CFFFFh 58 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh 59 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh 60 64/32 Protection Group 3C0000h–3CFFFFh 1E0000h–1E7FFFh 61 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh 62 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh Bank Block (Kbytes/ Kwords) Protection Block Group (x8) (x16)

M29DW323DT, M29DW323DB Note: 1. Used as the Extended Block Addresses in Extended Block mode. Bank A 63 8/4 Protection Group 3F0000h–3F1FFFh(1) 1F8000h–1F8FFFh(1) 64 8/4 Protection Group 3F2000h–3F3FFFh(1) 1F9000h–1F9FFFh(1) 65 8/4 Protection Group 3F4000h–3F5FFFh(1) 1FA000h–1FAFFFh(1) 66 8/4 Protection Group 3F6000h–3F7FFFh(1) 1FB000h–1FBFFFh(1) 67 8/4 Protection Group 3F8000h–3F9FFFh(1) 1FC000h–1FCFFFh(1) 68 8/4 Protection Group 3FA000h–3FBFFFh(1) 1FD000h–1FDFFFh(1) 69 8/4 Protection Group 3FC000h–3FDFFFh(1) 1FE000h–1FEFFFh(1) 70 8/4 Protection Group 3FE000h–3FFFFFh(1) 1FF000h–1FFFFFh(1) Bank Block (Kbytes/ Kwords) Protection Block Group (x8) (x16)

Table 24. Bottom Boot Block Addresses, M29DW323DB

M29DW323DT, M29DW323DB Bank B 31 64/32 Protection Group 180000h-18FFFFh 0C0000h–0C7FFFh 32 64/32 190000h-19FFFFh 0C8000h–0CFFFFh 33 64/32 1A0000h-1AFFFFh 0D0000h–0D7FFFh 34 64/32 1B0000h-1BFFFFh 0D8000h–0DFFFFh 35 64/32 Protection Group 1C0000h-1CFFFFh 0E0000h–0E7FFFh 36 64/32 1D0000h-1DFFFFh 0E8000h–0EFFFFh 37 64/32 1E0000h-1EFFFFh 0F0000h–0F7FFFh 38 64/32 1F0000h-1FFFFFh 0F8000h–0FFFFFh 39 64/32 Protection Group 200000h-20FFFFh 100000h–107FFFh 40 64/32 210000h-21FFFFh 108000h–10FFFFh 41 64/32 220000h-22FFFFh 110000h–117FFFh 42 64/32 230000h-23FFFFh 118000h–11FFFFh 43 64/32 Protection Group 240000h-24FFFFh 120000h–127FFFh 44 64/32 250000h-25FFFFh 128000h–12FFFFh 45 64/32 260000h-26FFFFh 130000h–137FFFh 46 64/32 270000h-27FFFFh 138000h–13FFFFh 47 64/32 Protection Group 280000h-28FFFFh 140000h–147FFFh 48 64/32 290000h-29FFFFh 148000h–14FFFFh 49 64/32 2A0000h-2AFFFFh 150000h–157FFFh 50 64/32 2B0000h-2BFFFFh 158000h–15FFFFh 51 64/32 Protection Group 2C0000h-2CFFFFh 160000h–167FFFh 52 64/32 2D0000h-2DFFFFh 168000h–16FFFFh 53 64/32 2E0000h-2EFFFFh 170000h–177FFFh 54 64/32 2F0000h-2FFFFFh 178000h–17FFFFh 55 64/32 Protection Group 300000h-30FFFFh 180000h–187FFFh 56 64/32 310000h-31FFFFh 188000h–18FFFFh 57 64/32 320000h-32FFFFh 190000h–197FFFh 58 64/32 330000h-33FFFFh 198000h–19FFFFh 59 64/32 Protection Group 340000h-34FFFFh 1A0000h–1A7FFFh 60 64/32 350000h-35FFFFh 1A8000h–1AFFFFh 61 64/32 360000h-36FFFFh 1B0000h–1B7FFFh 62 64/32 370000h-37FFFFh 1B8000h–1BFFFFh Bank Block (Kbytes/ Kwords) Protection Block Group (x8) (x16)

M29DW323DT, M29DW323DB Note: 1. Used as the Extended Block Addresses in Extended Block mode. Bank B 63 64/32 Protection Group 380000h-38FFFFh 1C0000h–1C7FFFh 64 64/32 390000h-39FFFFh 1C8000h–1CFFFFh 65 64/32 3A0000h-3AFFFFh 1D0000h–1D7FFFh 66 64/32 3B0000h-3BFFFFh 1D8000h–1DFFFFh 67 64/32 Protection Group 3C0000h-3CFFFFh 1E0000h–1E7FFFh 68 64/32 3D0000h-3DFFFFh 1E8000h–1EFFFFh 69 64/32 3E0000h-3EFFFFh 1F0000h–1F7FFFh 70 64/32 Protection Group 3F0000h-3FFFFFh 1F8000h–1FFFFFh Bank Block (Kbytes/ Kwords) Protection Block Group (x8) (x16)

ber after it has been written by Numonyx. Table 25. Query Structure Overview Note: Query data are always presented on the lowest order data outputs. Table 26. CFI Query Identification String Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

Table 27. CFI Query System Interface Information Table 28. Device Geometry Definition Note: For the M29DW323DB, Region 1 corresponds to addresses 000000h to 007FFFh and Region 2 to addresses 008000h to 1FFFFFh. For the M29DW323DT, Region 1 corresponds to addresses 1F8000h to 1FFFFFh and Region 2 to addresses 000000h to 1F7FFFh.

Table 29. Primary Algorithm-Specific Extended Query Table Table 30. Security Code Area

tion number) or to store additional information. Block cannot be unprotected. tion of the Extended Block is not reversible. for a detailed explanation of the technique). Table 31. Extended Block Address and Data Note: 1. See Tables 23 and 24, Top and Bottom Boot Block Addresses.

Figure 20. Programmer Equipment Group Protect Flowchart Note: Block Protection Groups are shown in APPENDIX D., Tables 23 and 24.

Figure 21. Programmer Equipment Chip Unprotect Flowchart Note: Block Protection Groups are shown in APPENDIX D., Tables 23 and 24.

Figure 22. In-System Equipment Group Protect Flowchart Note: 1. Block Protection Groups are shown in APPENDIX D., Tables 23 and 24.

  1. RP can be either at VIH or at VID when using the In-System Technique to protect the Extended Block.

Figure 23. In-System Equipment Chip Unprotect Flowchart Note: Block Protection Groups are shown in APPENDIX D., Tables 23 and 24.

M29DW323DT, M29DW323DB

REVISION HISTORY

Table 33. Document Revision History tPL YH (time to reset device) re-specified. When in Extended Block mode, the block at the boot block address can be used as OTP . Revision History moved to end of document. 22., Ordering Information Scheme. to Table 22., Ordering Information Scheme. Figures 14 and 15, Toggle and Alternative Toggle Bits Mechanisms added. Table 18., Toggle and Alternative Toggle Bits AC Characteristics, added. Table 18., Toggle and Alternative Toggle Bits AC Characteristics modified. Figure 8. renamed and flowchart modified; Note added. Table 8., Status Register Bits.

M29DW323DT, M29DW323DB 19-Dec-2003 7.4 VCC minimum value updated in Table 12., Operating and AC Measurement Conditions. VPP and IPP test conditions updated in Table 14., DC Characteristics. Architecture option updated in Table 22. Ordering Information Scheme. Block Protect/Unprotect code updated in APPENDIX B., Table 29. Customer Lockable Extended Block mechanism modified in APPENDIX C., Extended Memory Block. APPENDIX D., Block Protection updated: Note 1 added in the In-System Technique section and Note 2 added below Figure 22., In-System Equipment Group Protect Flowchart. 23-Mar-2004 8.0 Introduction of the STATUS REGISTER chapter clarified. 12-July-2004 9.0 90ns speed class removed from datasheet. 12-Aug-2004 10.0 Section , DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE added. 27-Sep-2004 11.0 TFBGA63 package removed. 10-Dec-2004 12.0 Status of Ready/Busy signal for Program Error, Chip Erase and Block Erase modified in Table 8., Status Register Bits. 14-Mar-2005 13.0 RB updated in Table 8., Status Register Bits. Fast Program Commands restructured and updated. Unlock Bypass Command updated. 27-Mar-2008 14.0 Applied Numonyx branding. Date Version Revision Details