M29DCL3-16T

M29W160DB STMICROELECTRONICS | Alldatasheet

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Technical content

16 Mbit (2Mb x8 or 1Mb x16, Boot Block)

Figure 1. Packages

required to update the memory contents. consistent with JEDEC standards. ranged, see Figures 6 and 7, Block Addresses. nals control the bus operation of the memory. cessors, often without additional logic. 20mm) and TFBGA48 (0.8mm pitch) packages. Figure 2. Logic Diagram Note: RB not available on SO44 package. Table 1. Signal Names

Figure 3. SO Connections Figure 4. TSOP Connections

Figure 5. TFBGA Connections (Top view through package)

Figure 6. Block Addresses (x8) Note: Also see Appendix A, Tables 20 and 21 for a full listing of the Block Addresses.

16 KByte

64 KByte

32 KByte

64 KByte Blocks

8 KByte

Figure 7. Block Addresses (x16) Note: Also see Appendix A, Tables 20 and 21 for a full listing of the Block Addresses.

8 KWord

32 KWord

16 KWord

32 KWord Blocks

4 KWord

M29W160DT, M29W160DB SIGNAL DESCRIPTIONS See Figure 2, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A19).The Address Inputs select the cells in the memory array to access dur- ing Bus Read operations. During Bus Write opera- tions they control the commands sent to the Command Interface of the internal state machine. Data Inputs/Outputs (DQ0-DQ7).The Data In- puts/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. Data Inputs/Outputs (DQ8-DQ14).The Data In- puts/Outputs output the data stored at the selected address during a Bus Read operation when BYTE is High, V IH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. Data Input/Output or Address Input (DQ15A-1). When BYTE is High, V IH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, V IL, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of the Word on the other addresses, DQ15A–1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address In- puts to include this pin when BYTE is Low except when stated explicitly otherwise. Chip Enable (E).The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write op- erations to be performed. When Chip Enable is High, V IH, all other pins are ignored. Output Enable (G).The Output Enable, G, con- trols the Bus Read operation of the memory. Write Enable (W).The Write Enable, W, controls the Bus Write operation of the memory’s Com- mand Interface. Reset/Block Temporary Unprotect (RP).The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, VIL, for at least tPLPX . After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL , whichever occurs last. See the Ready/Busy Output section, Table 15 and Figure 15, Reset/ Temporary Unprotect AC Characteristics for more details. Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from V IH to VID must be slower than tPHPHH . Ready/Busy Output (RB).The Ready/Busy pin is an open-drain output that can be used to identify when the device is performing a Program or Erase operation. During Program or Erase operations Ready/Busy is Low, V OL . Ready/Busy is high-im- pedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy be- comes high-impedance. See Table 15 and Figure 15, Reset/Temporary Unprotect AC Characteris- tics. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Byte/Word Organization Select (BYTE).The Byte/Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus modes of the memory. When Byte/Word Organization Se- lect is Low, V IL, the memory is in 8-bit mode, when it is High, VIH, the memory is in 16-bit mode. VCC Supply Voltage.The V CC Supply Voltage supplies the power for all operations (Read, Pro- gram, Erase etc.). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO . This prevents Bus Write operations from ac- cidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memo- ry contents being altered will be invalid. A 0.1µF capacitor should be connected between the V CC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, I CC3 . Vss Ground. The VSS Ground is the reference for all voltage measurements.

Tables 2 and 3, Bus Operations, for a summary. of when the output becomes valid. Enable or Write Enable, whichever occurs last. level see Table 11, DC Characteristics. til the operation completes. Read operation is in progress. code, that can be read to identify the memory. listed in Tables 2 and 3, Bus Operations. Block Protection and Blocks Unprotection. can be unprotected to allow data to be changed. tions are described in Appendix C. Table 2. Bus Operations, BYTE = V

Table 3. Bus Operations, BYTE = VIH are imposed to maximize data security. can be used to issue the Read/Reset command. Device Code and the Block Protection Status. mode, all other commands are ignored. Code for STMicroelectronics is 0020h. DQ0-DQ7, otherwise 00h is output. no error condition is given. the Status Register on the Data Inputs/Outputs.

M29W160DT, M29W160DB After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Regis- ter. A Read/Reset command must be issued to re- set the error condition and return to Read mode. Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase Com- mands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. Unlock Bypass Command. The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memo- ry. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these com- mands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been is- sued the memory will only accept the Unlock By- pass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode. Unlock Bypass Program Command. The Un- lock Bypass Program command can be used to program one address in memory at a time. The command requires two Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Pro- gram/Erase Controller. The Program operation using the Unlock Bypass Program command behaves identically to the Pro- gram operation using the Program command. A protected block cannot be programmed; the oper- ation cannot be aborted and the Status Register is read. Errors must be reset using the Read/Reset command, which leaves the device in Unlock By- pass Mode. See the Program command for details on the behavior. Unlock Bypass Reset Command. The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Read/Reset command does not exit from Unlock Bypass Mode. Chip Erase Command. The Chip Erase com- mand can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation ap- pears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands. It is not possible to issue any com- mand to abort the operation. Typical chip erase times are given in Table 6. All Bus Read opera- tions during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Regis- ter. A Read/Reset command must be issued to re- set the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in un- protected blocks of the memory to ’1’. All previous data is lost. Block Erase Command. The Block Erase com- mand can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller about 50µs after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register sec- tion for details on how to identify if the Program/ Erase Controller has started the Block Erase oper- ation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100µs, leaving the data un- changed. No error condition is given when protect- ed blocks are ignored. During the Block Erase operation the memory will ignore all commands except the Erase Suspend and Read/Reset commands. Typical block erase times are given in Table 6. All Bus Read opera- tions during the Block Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Regis- ter. A Read/Reset command must be issued to re- set the error condition and return to Read mode.

M29W160DT, M29W160DB The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is lost. Erase Suspend Command. The Erase Suspend Command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus Write operation. The Program/Erase Controller will suspend within 15µs of the Erase Suspend Command being is- sued. Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start im- mediately when the Erase Resume Command is issued. It is not possible to select any further blocks to erase after the Erase Resume. During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. If any attempt is made to program in a protected block or in the suspended block then the Program command is ignored and the data remains unchanged. The Status Register is not read and no error condition is given. Read- ing from blocks that are being erased will output the Status Register. It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands during an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command will be ac- cepted. Erase Resume Command. The Erase Resume command must be used to restart the Program/ Erase Controller from Erase Suspend. An erase can be suspended and resumed more than once. Read CFI Query Command. The Read CFI Query Command is used to read data from the Common Flash Interface (CFI) Memory Area. This command is valid when the device is in the Read Array mode, or when the device is in Autoselected mode. One Bus Write cycle is required to issue the Read CFI Query Command. Once the command is is- sued subsequent Bus Read operations read from the Common Flash Interface Memory Area. The Read/Reset command must be issued to re- turn the device to the previous mode (the Read Ar- ray mode or Autoselected mode). A second Read/ Reset command would be needed if the device is to be put in the Read Array mode from Autoselect- ed mode. See Appendix B, Tables 22, 23, 24, 25, 26 and 27 for details on the information contained in the Common Flash Interface (CFI) memory area.

Table 4. Commands, 16-bit mode, BYTE = VIH Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. Read/Reset.After a Read/Reset command, read the memory as normal until another command is issued. Auto Select.After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status. Bus Write Operations until Timeout Bit is set. Unlock Bypass.After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands. Unlock Bypass Reset.After the Unlock Bypass Reset command read the memory as normal until another command is issued. mands on non-erasing blocks as normal. gram/Erase Controller completes and the memory returns to Read Mode. CFI Query.Command is valid when device is ready to read array data or when device is in autoselected mode.

Table 5. Commands, 8-bit mode, BYTE = VIL Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. Read/Reset.After a Read/Reset command, read the memory as normal until another command is issued. Auto Select.After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status. Bus Write Operations until Timeout Bit is set. Unlock Bypass.After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands. Unlock Bypass Reset.After the Unlock Bypass Reset command read the memory as normal until another command is issued. mands on non-erasing blocks as normal. gram/Erase Controller completes and the memory returns to Read Mode. CFI Query.Command is valid when device is ready to read array data or when device is in autoselected mode.

3 AAA AA 555 55 X F0

is treated the same as a block not being erased. the memory cell data as if in Read mode. Table 7. Status Register Bits Note: Unspecified data bits should be ignored.

Figure 8. Data Polling Flowchart Figure 9. Data Toggle Flowchart Table 8. Absolute Maximum Ratings Note: 1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.

1. Maximum voltage may overshoot to VCC +2V during transition and for less than 20ns during transitions.

Table 9. Operating and AC Measurement Conditions Figure 10. AC Measurement I/O Waveform Figure 11. AC Measurement Load Circuit Table 10. Device Capacitance Note: Sampled only, not 100% tested.

Table 11. DC Characteristics Note: 1. Sampled only, not 100% tested.

Figure 12. Read Mode AC Waveforms Table 12. Read AC Characteristics Note: 1. Sampled only, not 100% tested.

Figure 13. Write AC Waveforms, Write Enable Controlled Table 13. Write AC Characteristics, Write Enable Controlled Note: 1. Sampled only, not 100% tested.

Figure 14. Write AC Waveforms, Chip Enable Controlled Table 14. Write AC Characteristics, Chip Enable Controlled Note: 1. Sampled only, not 100% tested.

Figure 15. Reset/Block Temporary Unprotect AC Waveforms Table 15. Reset/Block Temporary Unprotect AC Characteristics Note: 1. Sampled only, not 100% tested.

M29W160DT, M29W160DB PACKAGE MECHANICAL SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Outline Note: Drawing is not to scale. SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data Symbol millimeters inches Typ Min Max Typ Min Max A 2.80 0.1102 A1 0.10 0.0039 CP 0.08 0.0030 L 0.80 0.0315 N4 4 4 4 α 88 SO-d E N D C LA1 α EH A e CP b

M29W160DT, M29W160DB TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline Note: Drawing is not to scale. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data Symbol mm inches Typ Min Max Typ Min Max A 1.20 0.0472 A1 0.05 0.15 0.0020 0.0059 A2 0.95 1.05 0.0374 0.0413 B 0.17 0.27 0.0067 0.0106 C 0.10 0.21 0.0039 0.0083 D 19.80 20.20 0.7795 0.7953 D1 18.30 18.50 0.7205 0.7283 E 11.90 12.10 0.4685 0.4764 L 0.50 0.70 0.0197 0.0279 α 0° 5° 0° 5° N4 8 4 8 CP 0.10 0.0039 TSOP-a E CP B e A N/2 D DIE C LA1 α

Figure 16. TFBGA48 8x9mm - 6x8 ball array, 0.80 mm pitch, Package Outline Table 16. TFBGA48 8x9mm - 6x8 ball array, 0.80 mm pitch, Package Mechanical Data

Table 17. Ordering Information Scheme Table 18. Daisy Chain Ordering Scheme Devices are shipped from the factory with the memory content bits erased to ’1’. vice, please contact the ST Sales Office nearest to you.

M29W160DT, M29W160DB

REVISION HISTORY

Table 19. Document Revision History

Table 20. Top Boot Block Addresses, Table 21. Bottom Boot Block Addresses,

command to return to Read mode. able for Temperature range 6 (–40 to 85°C). Table 22. Query Structure Overview Note: Query data are always presented on the lowest order data outputs. Table 23. CFI Query Identification String Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

Table 24. CFI Query System Interface Information

Table 25. Device Geometry Definition Number of Erase Block Regions within the device. contiguous Erase Blocks of the same size.

Table 26. Primary Algorithm-Specific Extended Query Table Table 27. Security Code Area

ation from modifying the data stored in the Flash. block fail to change the data. use in Programming Equipment. Programmer Equipment Block Protect Flowchart. not abort the procedure before reaching the end. ure 22, In-System Chip Unprotect Flowchart. Table 28. Programmer Technique Bus Operations, BYTE = V

Figure 19. Programmer Equipment Block Protect Flowchart

Figure 20. Programmer Equipment Chip Unprotect Flowchart

Figure 21. In-System Equipment Block Protect Flowchart

Figure 22. In-System Equipment Chip Unprotect Flowchart

M29W160DT, M29W160DB Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners  2002 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.