M29F002T STMICROELECTRONICS | Alldatasheet
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W DQ0-DQ7 VCC M29F002T M29F002B M29F002NTE VSS G (*) RPNC Figure 1. Logic Diagram
2 Mbit (256Kb x8, Boot Block) Single Supply Flash Memory
20 YEARS DATARETENTION
DESCRIPTION
The M29F002 is a non-volatile memory that may be erased electrically at the block or chip level and programmed in-system on a Byte-by-Byte basis usingonly a single5VV CC supply.For Programand Erase operations the necessary high voltages are generated internally. The device can also be pro- grammed in standard programmers. The array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. Blocks can be protected against pro- graming and erase on programming equipment, and temporarily unprotected to make changes in the application. Each block can be programmed and erased over 100,000 cycles. July 1998 1/29 PLCC32 (K) PDIP32 (P) TSOP32 (N) 8 x 20mm Note: * RPNC function is not available for the M29F002NT
1 A16
32 RPNC
Table 1. Signal Names
- Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
Table 2. Absolute Maximum Ratings(1) able G and Write Enable W inputs. tection. See Tables 4 and 5. cycles are used to input Coded cycles to the C.I. quence will reset the device to Read Array mode.
Figure 3. Memory Map and Block Address Table
Seven instructions are defined to perform Read Array, Auto Select(to read the ElectronicSignature or Block ProtectionStatus), Program, Block Erase, Chip Erase, Erase Suspend and Erase Resume. The internal P/E.C. automatically handles all tim- ing and verification of the Program and Erase operations.The Status Register Data Polling, Tog- gle, Error bits may be read at any time, during programming or erase, to monitor the progress of the operation. Instructions are composed of up to six cycles. The first two cycles input a Coded sequence to the Command Interfacewhich iscommon to all instruc- tions (see Table 8). The third cycle inputs the instruction set-up command. Subsequent cycles output the addressed data, Electronic Signatureor Block Protection Status for Read operations. In order to giveadditional data protection,the instruc- tions for Program and Block or Chip Erase require furthercommandinputs. For a Programinstruction, the fourth command cycle inputs the address and data to be programmed. For an Erase instruction (Block or Chip), the fourth and fifth cycles input a further Coded sequence before the Erase confirm command on the sixth cycle. Erasure of a memory block may be suspended,in orderto readdata from another block or to program data in another block, and then resumed. When power is first applied or if V CC falls below VLKO , the command interface is reset to Read Array. SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs (A0-A17). The address inputs for the memory array are latchedduring a write opera- tion on the falling edge of Chip Enable E or Write EnableW. When A9 is raised to V ID, eithera Read ElectronicSignatureManufactureror DeviceCode, Block Protection Status or a WriteBlock Protection or Block Unprotection is enabled dependingon the combinationof levels on A0, A1, A6, A12 and A15. Data Input/Outputs (DQ0-DQ7).The input is data to be programmed in the memory array or a com- mand to be written to the C.I. Both are latched on the rising edge of Chip Enable E or Write Enable W. The output is data from the Memory Array, the Electronic Signature Manufacturer or Device codes, the Block Protection Status or the Status register Data Polling bit DQ7, the Toggle Bits DQ6 and DQ2, the Error bit DQ5 or the Erase Timer bit DQ3. Outputs are valid when Chip Enable E and Output Enable G are active. The output is high impedance when the chip is deselected or the outputs are disabled and when RPNC is at a Low level. Chip Enable (E).The Chip Enable input activates the memory control logic, input buffers, decoders andsenseamplifiers. E Highdeselectsthe memory andreducesthe power consumptionto the standby level. E can also be used to control writing to the command register and to the memory array, while W remainsat a low level. The Chip Enablemust be forced to V ID during the Block Unprotection opera- tion. Output Enable (G).The Output Enable gates the outputs through the data buffers during a read operation. When G is High the outputs are High impedance. G must be forced to V ID level during Block Protection and Unprotection operations. Write Enable (W).This input controls writing to the Command Registerand Addressand Datalatches. Reset/Block Temporary Unprotect/No Connect Input (RPNC).The RPNC (not available for the M29F002NT) input provides hardware reset and protected block(s) temporary unprotection func- tions. In read or write mode, the RPNC pin can be left open (Not Connected) or held at V IH. Reset of the memory is acheived by pulling RPNC to VILfor at least 500ns. When the reset pulse is given, if the memory is in Read or Standby modes, it will be available for new operations in 50ns after the rising edge of RPNC. If the memory is in Erase, Erase Suspend or Program modes the reset will take 10µs. Ahardwareresetduringan Eraseor Program operation will corrupt the data being programmed or the sector(s) being erased. Temporary block unprotection is made by holding RPNC at V ID. In this conditionpreviously protected blocks can be programmed or erased. The transi- tion of RPNC from VIH to VID must slower than 500ns. When RPNC is returned from VID to VIH all blocks temporarily unprotected will be again pro- tected. VCC Supply Voltage.The power supply for all operations (Read, Program and Erase). VSS Ground. VSS is the reference for all voltage measurements. DEVICE OPERATIONS See Tables 4, 5 and 6. Read. Read operations are used to output the contents of the Memory Array, the Electronic Sig- nature, the Status Register or the Block Protection Status. Both Chip Enable E and Output Enable G must be low in order to read the output of the memory. M29F002T , M29F002NT , M29F002B
- Block Address must be given on A13-A17 bits.
- Operation performed on programming equipment.
IH or left open (Not Connected).
- Not Available on M29F002NT.
Table 4. User Bus Operations(1) Table 5. Read Electronic Signature (following AS instruction or with A9 = VID) Table 6. Read Block Protection with AS Instruction
on the falling edge of W or E whicheveroccurs last. edge of W or E whichever occurs first. the Output Enable G or Write Enable W inputs. standby value, while outputs still drive the bus. interface to the characteristics of the M29F002. VIL and A1 to VIH, while W is at VIH and A9 at VID. tected blocks are again protected. ensure that it has been unprotected. made of address and data sequences. Table 7. Commands
1+ Addr.(3,7) X Read Memory Array until a new write cycle is initiated. Bit until Program completes. Notes:1. Commands not interpreted in this table will default to read array mode.
- A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase or Program mode
before starting any new operation (see Table 14 and Figure 9).
- The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after
- Signature Address bits A0, A1 at VILwill output Manufacturer code (20h). Address bits A0 at VIH and A1 at VILwill output
- Block Protection Address: A0 at VIL,A 1a tVIH and A13-A17 within the Block will output the Block Protection status.
- For Coded cycles address inputs A12-A17 are don’t care.
- Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry,
timeout status can be verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, read Data Polling or Togglebit until Erase is completed or suspended.
- Read Data Polling, Toggle bits or RB until Erase completes.
10.During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased. Table 8. Instructions(1) is again preceded by the two Coded cycles. DQ2, or Error on DQ5 and Erase Timer DQ3 bits. and should be masked. See Tables 9 and 10.
7 Data
6 Toggle Bit
5 Error Bit ’1’ Program or Erase Error This bit is set to ’1’ in the case of
4 Reserved
3 Erase
can be entered to the P/E.C.
2 Toggle Bit
1 Reserved
0 Reserved
Notes:Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations. Table 9. Status Register Bits plement of the bit being programmed on DQ7. previous addressed memory data value.
operationis attemptedon an Erase Suspendblock. flowchart and Figure 13 for Toggle Bit waveforms. Error Bit (DQ5).This bit is set to ’1’ by the P/E.C. Erase, the error bit will be set to ’0’ . write or on the fourth and fifth cycles. Note: 1. Toggle if the address is within a block being erased. ’1’ if the address is within a block not being erased. Table 10. Polling and Toggle Bits
Note: 1. Sampled only, not 100% tested. Table 13. DC Characteristics the sixth cycle after another two Coded cycles. DQ3 is ’1’, the timeout has expired and the P/E.C. status register status bits.
Notes:1. Sampled only, not 100% tested.
- G may be delayed by up to tELQV -tGLQV after the falling edge of E without increasing tELQV .
- To be considered only if the Reset pulse is given while the memory is in Erase mode.
Table 14. Read AC Characteristics
Figure 6. Read Mode AC Waveforms
Notes:1. Sample only, not 100% tested.
- This timing is for Temporary Block Unprotection operation.
Table 15. Write AC Characteristics,Write Enable Controlled
Figure 7. Write AC Waveforms, W Controlled Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W. in invalid data in the blocks being erased. blocked when Vcc is below VLKO . gram and erase currents required.
Notes:1. Sample only, not 100% tested.
- This timing is for Temporary Block Unprotection operation.
Table 16. Write AC Characteristics,Chip Enable Controlled
Note: 1. All other timings are defined in Read AC Characteristics table. Table 17. Data Polling and Toggle Bit AC Characteristics(1)
Figure 10. Data Polling DQ7 AC Waveforms
Figure 13. Data Toggle DQ6, DQ2 AC Waveforms Note: All other timings are as a normal Read cycle.
Figure 14. Block Protection Flowchart
Figure 15. All Blocks Unprotecting Flowchart
ORDERING INFORMATION SCHEME Devices are shipped from the factory with the memory content erased (to FFh). For a list of availableoptions(Speed, Package,etc...)or for furtherinformationon any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. Operating Voltage F5 V Array Matrix T Top Boot B Bottom Boot NT Top Boot without RPNC function Speed -70 70ns -90 90ns -120 120ns Power Supplies blank V CC ± 10% XV CC ± 5% Package P PDIP32 K PLCC32 N TSOP32 (8 x 20 mm) Option TR Tape & Reel Packing Temp. Range 1 0 to 70 °C 6 –40 to 85 °C Example: M29F002T -70 X K 1 TR M29F002T , M29F002NT , M29F002B
A L B1 B e1 D S E1 E N C α eA eBD2 Symb mm inches Typ Min Max Typ Min Max A – 5.08 – 0.200 A1 0.38 – 0.015 – A2 3.56 4.06 0.140 0.160 B 0.38 0.51 0.015 0.020 C 0.20 0.30 0.008 0.012 D 41.78 42.04 1.645 1.655 E1 13.59 13.84 0.535 0.545 eB 15.24 17.78 0.600 0.700 L 3.18 3.43 0.125 0.135 S 1.78 2.03 0.070 0.080 α 0° 10° 0° 10° N3 2 3 2 Drawing is not to scale. PDIP32 - 32 pin Plastic DIP, 600 mils width M29F002T , M29F002NT , M29F002B
D Ne E1 E Nd CP B D2/E2 e A R 0.51 (.020) 1.14 (.045) F Symb mm inches Typ Min Max Typ Min Max A 2.54 3.56 0.100 0.140 A1 1.52 2.41 0.060 0.095 A2 – 0.38 – 0.015 B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 D 12.32 12.57 0.485 0.495 D1 11.35 11.56 0.447 0.455 D2 9.91 10.92 0.390 0.430 E 14.86 15.11 0.585 0.595 E1 13.89 14.10 0.547 0.555 E2 12.45 13.46 0.490 0.530 F 0.00 0.25 0.000 0.010 N3 2 3 2 Nd 7 7 Ne 9 9 CP 0.10 0.004 Drawing is not to scale. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular M29F002T , M29F002NT , M29F002B
TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm TSOP-a E CP B e A N/2 D DIE C LA1 α Symb mm inches Typ Min Max Typ Min Max A 1.20 0.047 A1 0.05 0.15 0.002 0.007 A2 0.95 1.05 0.037 0.041 B 0.15 0.27 0.006 0.011 C 0.10 0.21 0.004 0.008 D 19.80 20.20 0.780 0.795 D1 18.30 18.50 0.720 0.728 E 7.90 8.10 0.311 0.319 L 0.50 0.70 0.020 0.028 α 0° 5° 0° 5° N3 2 3 2 CP 0.10 0.004 Drawing is not to scale. M29F002T , M29F002NT , M29F002B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 1998 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. M29F002T , M29F002NT , M29F002B