M28F101

M28F101 STMICROELECTRONICS | Alldatasheet

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Technical content

1 Mb (128K x 8, Chip Erase) FLASH MEMORY

W DQ0-DQ7 VPPVCC M28F101 G E VSS Figure 1. Logic Diagram

DESCRIPTION

The M28F101 FLASH Memory is a non-volatile memory which may be erased electrically at the chip level and programmed byte-by-byte. It is or- ganised as 128K bytes of 8 bits.It usesa command register architecture to select the operating modes and thus provides a simple microprocessor inter- face. The M28F101 FLASH Memory is suitable for applications where the memory has to be repro- grammed in the equipment. The access time of 70ns makes the device suitable for use in high speed microprocessor systems. A0-A16 Address Inputs DQ0-DQ7 Data Inputs / Outputs E Chip Enable G Output Enable W Write Enable V PP Program Supply VCC Supply Voltage VSS Ground Table 1. Signal Names

W A16 DQ7 A12 A14

32 VPP

G E VSS Figure 2B. LCC Pin Connections DQ0 A13 A10 DQ7 A14 A11 G E DQ5DQ1 DQ2 DQ3VSS DQ4 DQ6 NC WA16 A12 VPP VCC A15 AI00667 M28F1018 Figure 2A. DIP Pin Connections DQ0 A4 A3 A13 A10 DQ7 A14 A11 G E DQ5 DQ1 DQ2 DQ3 DQ4 DQ6 NC W A16 A12 VPP VCC A15 AI00669B M28F101 (Normal) 16 17 VSS Figure 2C. TSOP Pin Connections DQ0 A4A3 A13 A10 DQ7 A14 A11G E DQ5 DQ1 DQ2 DQ3 DQ4 DQ6 NC W A16 A12 VPP VCC A15 AI00670C M28F101 (Reverse) 16 17 VSS Figure 2D. TSOP Reverse Pin Connections Warning: NC = Not Connected. Warning: NC = Not Connected. Warning: NC = Not Connected. Warning: NC = Not Connected. M28F101

periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents . Table 2. Absolute Maximum Ratings able, Electronic Signature Read and Standby). Standby Mode this input is don’t care. independantof the device selection. independantof the Output Enable (G) input. when A0 is High the outputis the device type code. may also be accessed in Read/Write modes. any number of read operations to output data. manufactureror device codes.

1. Refer also to the Electronic Signature table.

Table 5. Commands (1) Table 4. Electronic Signature

1. Refer also to the Command table.

Table 3. Operations(1)

Note: 1. Not 100% tested. Characterisation Data available. Table 8. DC Characteristics

Read Mode. The Read Mode is the default at power up or may be set-up by writing 00h to the command register. Subsequent read operations output datafrom the memory. The memory remains in the Read Mode until a new command is written to the command register. Electronic Signature Mode.In order to select the correct erase and programming algorithms for on- board programming, the manufacturer and device codes may be read directly. It is not neccessary to apply a high voltage to A9 when using the com- mand register. The Electronic Signature Mode is set-up by writing 90h to the command register. The following read cycles, with address inputs 00000h or 00001h, output the manufacturer or device type codes. The command is terminated by writing an- other valid command to the command register (for example Reset). Symbol Alt Parameter Test Condition M28F101 Unit -70 -90 -100 VCC =5V±5% V CC =5V ±10% V CC =5V ±10% SRAM Interface EPROM Interface EPROM Interface Min Max Min Max Min Max tWHGL Write Enable High to Output Enable Low 666 µs tAVA V tRC Read Cycle Time E = V IL,G=V IL 70 90 100 ns tAVQ V tACC Address Valid to Output Valid E=V IL,G=V IL 70 90 100 ns tELQX (1) tLZ Chip Enable Low to Output Transition G=V IL 000 n s tELQV tCE Chip Enable Low to Output Valid G=V IL 70 90 100 ns tGLQX (1) tOLZ Output Enable Low to Output Transition E=V IL 000 n s tGLQV tOE Output Enable Low to Output Valid E=V IL 40 40 45 ns tEHQZ (1) Chip Enable High to Output Hi-Z G=V IL 0 30 0 45 0 45 ns tGHQZ (1) tDF Output Enable High to Output Hi-Z E=V IL 0 30 0 30 0 30 ns tAXQX tOH Address Transition to Output Transition E=V IL,G=V IL 000 n s Note: 1. Sampled only, not 100% tested Table 9A. Read Only Mode AC Characteristics (TA = 0 to 70°C, –40 to 85°C or –40 to 125°C; 0V≤ VPP ≤ 6.5V) M28F101

Symbol Alt Parameter Test Condition M28F101 Unit -120 -150 -200 VCC =5V±10% V CC =5V±10% V CC =5V ±10% EPROM Interface EPROM Interface EPROM Interface Min Max Min Max Min Max tWHGL Write Enable High to Output Enable Low 666 µs tAVAV tRC Read Cycle Time E = V IL,G=V IL 120 150 200 ns tAVQV tACC Address Valid to Output Valid E=V IL,G=V IL 120 150 200 ns tELQX (1) tLZ Chip Enable Low to Output Transition G=V IL 000 n s tELQV tCE Chip Enable Low to Output Valid G=V IL 120 150 200 ns tGLQX (1) tOLZ Output Enable Low to Output Transition E=V IL 000 n s tGLQV tOE Output Enable Low to Output Valid E=V IL 50 55 60 ns tEHQZ (1) Chip Enable High to Output Hi-Z G=V IL 05 505 506 0 n s tGHQZ (1) tDF Output Enable High to Output Hi-Z E=V IL 03 003 504 0 n s tAXQX tOH Address Transition to Output Transition E=V IL,G=V IL 000 n s Note: 1. Sampled only, not 100% tested Table 9B. Read Only Mode AC Characteristics ((TA = 0 to 70°C, –40 to 85°C or –40 to 125°C; 0V≤ VPP ≤ 6.5V) Erase and Erase Verify Modes.The memory is erased by first Programming all bytes to 00h, the Erase command then erases them to FFh. The Erase Verify command is then used to read the memory byte-by-byte for a content of FFh. The Erase Mode is set-up by writing 20h to the com- mand register. The write cycle is then repeated to start the erase operation. Erasure starts on the rising edge of W during this second cycle. Erase is followed by an Erase Verify which reads an ad- dressed byte. Erase Verify Mode is set-up by writing A0h to the command register and at the same time supplying the address of the byte to be verified. The rising edge of W during the set-up of the first Erase Verify Mode stops the Erase operation. The following read cycle is made with an internally generated margin voltage applied; reading FFh indicates that all bits of the addressed byte are fully erased. The whole contents of the memory are verified by re- peating the Erase Verify Operation, first writing the set-up code A0h with the address of the byte to be verified and then reading the byte contents in a second read cycle. M28F101

Figure 7. Electronic Signature Command Waveforms secind cycle starts the programming operation. command register (for example Read).

-70 -90 -100 VCC =5V±5% V CC =5V ±10% V CC =5V±10% SRAM Interface EPROM Interface EPROM Interface Min Max Min Max Min Max tVPHEL VPP High to Chip Enable Low 1 1 1 µs tVPHWL VPP High to Write Enable Low 1 1 1 µs tWHWH3 tWC Write Cycle Time 70 90 100 ns tAVWL tAS Address Valid to Write Enable Low 0 0 0 ns tAVEL Address Valid to Chip Enable Low 0 0 0 ns tWLAX tAH Write Enable Low to Address Transition 40 40 40 ns tELAX Chip Enable Low to Address Transition 50 60 60 ns tELWL tCS Chip Enable Low to Write Enable Low 10 15 15 ns tWLEL Write Enable Low to Chip Enable Low 0 0 0 ns tGHWL Output Enable High to Write Enable Low 000 µs tGHEL Output Enable High to Chip Enable Low 0 0 0 µs tDVWH tDS Input Valid to Write Enable High 30 40 40 ns tDVEH Input Valid to Chip Enable High 30 35 40 ns tWLWH tWP Write Enable Low to Write Enable High (Write Pulse) 35 40 40 ns tELEH Chip Enable Low to Chip Enable High (Write Pulse) 35 45 45 ns tWHDX tDH Write Enable High to Input Transition 10 10 10 ns tEHDX Chip Enable High to Input Transition 10 10 10 ns tWHWH1 Duration of Program Operation 9.5 9.5 9.5 µs tEHEH1 Duration of Program Operation 9.5 9.5 9.5 µs tWHWH2 Duration of Erase Operation 9.5 9.5 9.5 ms tWHEH tCH Write Enable High to Chip Enable High 0 0 0 ns tEHWH Chip Enable High to Write Enable High 0 0 0 ns tWHWL tWPH Write Enable High to Write Enable Low 20 20 20 ns tEHEL Chip Enable High to Chip Enable Low 20 20 20 ns tWHGL Write Enable High to Output Enable Low 666 µs tEHGL Chip Enable High to Output Enable Low 6 6 6 µs tAVQ V tACC Addess Valid to data Output 70 90 100 ns tELQX (1) tLZ Chip Enable Low to Output Transition 0 0 0 ns tELQV tCE Chip Enable Low to Output Valid 70 90 100 ns tGLQX (1) tOLZ Output Enable Low to Output Transition 0 0 0 ns tGLQV tOE Output Enable Low to Output Valid 40 40 45 ns tEHQZ (1) Chip Enable High to Output Hi-Z 30 40 40 ns tGHQZ (1) tDF Output Enable High to Output Hi-Z 30 30 30 ns tAXQX tOH Address Transition to Output Transition 0 0 0 ns Note: 1. Sampled only, not 100% tested. Table 10A. Read/Write Mode AC Characteristics, W and E Controlled (TA = 0 to 70°C, –40 to 85°C or –40 to 125°C) M28F101

-120 -150 -200 VCC =5V ±10% V CC =5V ±10% V CC =5V ±10% EPROM Interface EPROM Interface EPROM Interface Min Max Min Max Min Max tVPHEL VPP High to Chip Enable Low 1 1 1 µs tVPHWL VPP High to Write Enable Low 1 1 1 µs tWHWH3 tWC Write Cycle Time 120 150 200 ns tAVWL tAS Address Valid to Write Enable Low 0 0 0 ns tAVEL Address Valid to Chip Enable Low 0 0 0 ns tWLAX tAH Write Enable Low to Address Transition 60 60 75 ns tELAX Chip Enable Low to Address Transition 80 80 80 ns tELWL tCS Chip Enable Low to Write Enable Low 20 20 20 ns tWLEL Write Enable Low to Chip Enable Low 0 0 0 ns tGHWL Output Enable High to Write Enable Low 000 µs tGHEL Output Enable High to Chip Enable Low 0 0 0 µs tDVWH tDS Input Valid to Write Enable High 50 50 50 ns tDVEH Input Valid to Chip Enable High 50 50 50 ns tWLWH tWP Write Enable Low to Write Enable High (Write Pulse) 60 60 60 ns tELEH Chip Enable Low to Chip Enable High (Write Pulse) 70 70 70 ns tWHDX tDH Write Enable High to Input Transition 10 10 10 ns tEHDX Chip Enable High to Input Transition 10 10 10 ns tWHWH1 Duration of Program Operation 9.5 9.5 9.5 µs tEHEH1 Duration of Program Operation 9.5 9.5 9.5 µs tWHWH2 Duration of Erase Operation 9.5 9.5 9.5 ms tWHEH tCH Write Enable High to Chip Enable High 0 0 0 ns tEHWH Chip Enable High to Write Enable High 0 0 0 ns tWHWL tWPH Write Enable High to Write Enable Low 20 20 20 ns tEHEL Chip Enable High to Chip Enable Low 20 20 20 ns tWHGL Write Enable High to Output Enable Low 666 µs tEHGL Chip Enable High to Output Enable Low 6 6 6 µs tAVQ V tACC Addess Valid to data Output 120 150 200 ns tELQX (1) tLZ Chip Enable Low to Output Transition 0 0 0 ns tELQV tCE Chip Enable Low to Output Valid 120 150 200 ns tGLQX (1) tOLZ Output Enable Low to Output Transition 0 0 0 ns tGLQV tOE Output Enable Low to Output Valid 50 55 60 ns tEHQZ (1) Chip Enable High to Output Hi-Z 50 55 60 ns tGHQZ (1) tDF Output Enable High to Output Hi-Z 30 35 40 ns tAXQX tOH Address Transition to Output Transition 0 0 0 ns Note: 1. Sampled only, not 100% tested. Table 10B. Read/Write Mode AC Characteristics, W and E Controlled (TA = 0 to 70°C, –40 to 85°C or –40 to 125°C) M28F101

Figure 8. Erase Set-up and Erase Verify Commands Waveforms, W Controlled

Figure 9. Erase Set-up and Erase Verify Commands Waveforms, E Controlled

Figure 10. Program Set-up and Program Verify Commands Waveforms, W Controlled

Figure 11. Program Set-up and Program Verify Commands Waveforms, E Controlled

ORDERING INFORMATION SCHEME Operating Voltage F5 V Speed -70 70ns -90 90ns -100 100ns -120 120ns -150 150ns -200 200ns Power Supplies blank V CC ± 10% XV CC ± 5% Package P PDIP32 K PLCC32 N TSOP32 8 x 20mm Option R Reverse Pinout TR Tape & Reel Packing Temp. Range 1 0 to 70°C 3 –40 to 125°C 6 –40 to 85°C Example: M28F101 -70 X N 1 TR Devices are shipped from the factory with the memory content erased (to FFh). For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the SGS-THOMSON Sales Office nearest to you. M28F101

PDIP32 - 32 pin Plastic DIP, 600 mils width PDIP A L B1 B e1 D S E1 E N Cα eA Symb mm inches Typ Min Max Typ Min Max A 4.83 0.190 A1 0.38 – 0.015 – B 0.41 0.51 0.016 0.020 B1 1.14 1.40 0.045 0.055 C 0.20 0.30 0.008 0.012 D 41.78 42.04 1.645 1.655 E 15.24 15.88 0.600 0.625 E1 13.46 13.97 0.530 0.550 L 3.18 3.43 0.125 0.135 S 1.78 2.03 0.070 0.080 α 0° 15° 0° 15° N3 2 3 2 PDIP32 Drawing is not to scale. M28F101

D Ne E1 E Nd CP B D2/E2 e A Symb mm inches Typ Min Max Typ Min Max A 2.54 3.56 0.100 0.140 A1 1.52 2.41 0.060 0.095 B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 D 12.32 12.57 0.485 0.495 D1 11.35 11.56 0.447 0.455 D2 9.91 10.92 0.390 0.430 E 14.86 15.11 0.585 0.595 E1 13.89 14.10 0.547 0.555 E2 12.45 13.46 0.490 0.530 N3 2 3 2 Nd 7 7 Ne 9 9 CP 0.10 0.004 PLCC32 Drawing is not to scale. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular M28F101

E CP B e A N/2 D DIE C LA1 α Symb mm inches Typ Min Max Typ Min Max A 1.04 1.24 0.041 0.049 A1 0.05 0.20 0.002 0.008 A2 0.95 1.06 0.037 0.042 B 0.15 0.27 0.006 0.011 C 0.10 0.21 0.004 0.008 D 19.90 20.12 0.783 0.792 D1 18.24 18.49 0.718 0.728 E 7.90 8.10 0.311 0.319 L 0.30 0.70 0.012 0.028 α 0° 5° 0° 5° N3 2 3 2 CP 0.10 0.004 TSOP32 Drawing is not to scale. TSOP32 Normal Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm M28F101

A 1.04 1.24 0.041 0.049 A1 0.05 0.20 0.002 0.008 A2 0.95 1.06 0.037 0.042 B 0.15 0.27 0.006 0.011 C 0.10 0.21 0.004 0.008 D 19.90 20.12 0.783 0.792 D1 18.24 18.49 0.718 0.728 E 7.90 8.10 0.311 0.319 L 0.30 0.70 0.012 0.028 α 0° 5° 0° 5° N3 2 3 2 CP 0.10 0.004 TSOP32 TSOP32 Reverse Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm TSOP-b E CP B e A N/2 D DIE C LA1 α Drawing is not to scale. M28F101

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics.  1997 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. M28F101