M28010-20NA6T

M28010 STMICROELECTRONICS | Alldatasheet

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Technical content

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. M28010

1 Mbit (128K x 8) Parallel EEPROM

With Software Data Protection n Fast Access Time: 100 ns n Single Supply Voltage: – 4.5 V to 5.5 V for M28010 – 2.7 V to 3.6 V for M28010-W – 1.8 V to 2.4 V for M28010-R n Low Power Consumption n Fast BYTE and PAGE WRITE (up to 128 Bytes) n Enhanced Write Detection and Monitoring: – Data Polling – Toggle Bit – Page Load Timer Status n JEDEC Approved Bytewide Pin-Out n Software Data Protection n Hardware Data Protection n Software Chip Erase n 100000 Erase/Write Cycles (minimum) n Data Retention (minimum): 10 Years

DESCRIPTION

The M28010 devices consist of 128Kx8 bits of low power, parallel EEPROM, fabricated with STMicroelectronics’ proprietary double polysilicon CMOS technology. The devices offer fast access time, with low power dissipation, and require a single voltage supply (5V, 3V or 2V, depending on the option chosen). Figure 1. Logic Diagram Table 1. Signal Names

Figure 2A. DIP Connections Note: 1. DU = Do Not Use Figure 2B. PLCC Connections Note: 1. DU = Do Not Use DQ0 A13 A10 DQ7 A14 A11 G E DQ5DQ1 DQ2 DQ3VSS DQ4 DQ6 A12 DU V CC AI02222 M280108 A15 DU WA16 2 AI02223 DU A10 DQ4 DQ0 DQ1 DQ2 DQ6 DQ3 W

1 A16

G E VSS Figure 2C. TSOP Connections Note: 1. DU = Do Not Use A11 DQ7 G E DQ5 DQ0 DQ1 DQ3 DQ4 DQ6 A13 W A15 A14 VCC A12 AI02224 M280108 16 17 VSS A10 DQ2 DU A16 DU The device has been designed to offer a flexible microcontroller interface, featuring both hardware and software hand-shaking, with Data Polling and Toggle Bit. The device supports a 128 byte Page Write operation. Software Data Protection (SDP) is also supported, using the standard JEDEC algorithm. The M28010 is designed for applications requiring as much as 100,000 write cycles and ten years of data retention. The organization of the data in a 4 byte (32-bit) “word” format leads to significant savings in power consumption. Once a byte has been read, subsequent byte read cycles from the same “word” (with addresses differing only in the two least significant bits) are fetched from the previously loaded Read Buffer, not from the memory array. As a result, the power consumption for these subsequent read cycles is much lower than the power consumption for the first cycle. By careful design of the memory access patterns, a 50% reduction in the power consumption is possible. SIGNAL DESCRIPTION The external connections to the device are summarized in Table 1, and their use in Table 3. Addresses (A0-A16). The address inputs are used to select one byte from the memory array during a read or write operation. Data In/Out (DQ0-DQ7).The contents of the data byte are written to, or read from, the memory array through the Data I/O pins. Chip Enable (E).The chip enable input must be held low to enable read and write operations. When Chip Enable is high, power consumption is reduced. Output Enable (G).The Output Enable input controls the data output buffers, and is used to initiate read operations.

Figure 3. Block Diagram Table 2. Absolute Maximum Ratings1 tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

Table 3. Operating Modes1 specified in Table 4A to Table 4C. inadvertent write operations to the memory. Note: 1. Sampled only, not 100% tested. Note: 1. Sampled only, not 100% tested. Note: 1. Sampled only, not 100% tested.

Figure 4. Software Data Protection Enable Algorithms (with or without Memory Write) addressed location are presented on the I/O pins. revert to their high impedance state. rising edge of W or E (which ever occurs first).

Figure 5. Software Data Protection Disable Algorithms (with or without Memory Write) address (A16-A7 must be the same for all bytes). controlled phase of the Page Write cycle.

The device can be erased (with all bytes set to FFh) by using a six-byte software command code. This operation can be initiated only if the user loads, with a Page Write addressing mode, six specific data bytes to six specific locations (as shown in Figure 6). The complexity of the sequence has been designed to guard against inadvertent use of the command. Status Bits The devices provide five status bits (DQ7, DQ6, DQ5, DQ1 and DQ0) for use during write operations. These allow the application to use the write time latency of the device for getting on with other work. These signals are available on the I/O port bits DQ7, DQ6, DQ5, DQ1 and DQ0 (but only during the internal write cycle, t Q5HQ5X ). Data Polling bit (DQ7).The internally timed write cycle starts as soon as tWLQ5H (defined in Table 9A to Table 9C) has elapsed since the previous byte was latched in to the memory. The value of the DQ7 bit of this last byte, is used as a signal throughout this write operation: it is inverted while the internal write operation is underway, and is inverted back to its original value once the operation is complete. Toggle bit (DQ6).The device offers another way for determining when the internal write cycle is running. During the internal write cycle, DQ6 toggles from ’0’ to ’1’ and ’1’ to ’0’ (the first read value being ’0’) on subsequent attempts to read any byte of the memory. When the internal write cycle is complete, the toggling is stopped, and the values read on DQ7-DQ0 are those of the addressed memory byte. This indicates that the device is again available for new Read and Write operations. Page Load Timer Status bit (DQ5).An internal timer is used to measure the period between successive Write operations, up to t WLQ5H (defined in Table 9A to Table 9C). The DQ5 line is held low to show when this timer is running (hence showing that the device has received one write operation, and is waiting for the next). The DQ5 line is held high when the counter has overflowed (hence showing that the device is now starting the internal write to the memory array). Page Write Abort bit (DQ1).During a page write operation, the A16 to A7 signals should be kept constant. They should not change while successive data bytes are being transferred to the internal latches of the memory device. If a change occurs on any of the pins, A16 to A7, during the page write operation (that is, before the falling edge of W or E, which ever occurs later), the internal write cycle is not started, and the internal circuitry is completely reset. The abort signal can be observed on the DQ1 pin, using a normal read operation. This can be performed at any time during the byte load cycle, t WLQ5H , or while the W input is being held high between two load cycles. The default value of DQ1 is initially set to ’0’ and changes to ’1’ if the internal circuitry has detected a change on any of the address pins A16 to A7. This PWA bit can be checked regardless of whether Software Data Protection is enabled or disabled. Table 5A. Read Mode DC Characteristics for M28010 (5V range) A = –40 to 85°C; VCC = 4.5 to 5.5 V) Note: 1. All inputs and outputs open circuit. Symbol Parameter Test Condition Min. Max. Unit ILI Input Leakage Current 0V ≤ V IN ≤ VCC 5 µA ILO Output Leakage Current 0 V ≤ VOUT ≤ VCC 5 µA ICC 1 Supply Current (CMOS inputs) E=V IL,G=V IL, f = 0.1 MHz 2m A E=V IL,G=V IL, f = 5 MHz 22 mA E=V IL,G=V IL, f = 10 MHz 40 mA ICC1 1 Supply Current (Stand-by) CMOS E > V CC –0 . 3V 5 0 µA V IL Input Low Voltage –0.3 0.8 V V IH Input High Voltage 2 VCC + 0.3 V VOL Output Low Voltage IOL = 2.1 mA 0.4 V VOH Output High Voltage IOH = –400µA 2.4 V

Table 5B. Read Mode DC Characteristics for M28010-W (3V range) (TA = –40 to 85°C; VCC = 2.7 to 3.6 V) Note: 1. All inputs and outputs open circuit. Table 5C. Read Mode DC Characteristics for M28010-R (2V range) (TA = –40 to 85°C; VCC = 1.8 to 2.4 V) Note: 1. All inputs and outputs open circuit. Symbol Parameter Test Condition Min. Max. Unit ILI Input Leakage Current 0V ≤ V IN ≤ VCC 5 µA ILO Output Leakage Current 0V ≤ VOUT ≤ VCC 5 µA ICC 1 Supply Current (CMOS inputs) E=V IL,G=V IL, f = 0.1 MHz 2m A E=V IL,G=V IL,f=5M H z 15 mA E=V IL,G=V IL, f = 10 MHz 26 mA ICC1 1 Supply Current (Stand-by) CMOS E>V CC – 0.3 V 30 µA V IL Input Low Voltage –0.3 0.6 V V IH Input High Voltage 2 VCC + 0.3 V VOL Output Low Voltage IOL = 1.6 mA 0.45 V VOH Output High Voltage IOH = –100µA 2.4 V Symbol Parameter Test Condition Min. Max. Unit ILI Input Leakage Current 0V ≤ VIN ≤ V CC 5 µA ILO Output Leakage Current 0V ≤ VOUT ≤ VCC 5 µA ICC 1 Supply Current (CMOS inputs) E=V IL,G=V IL, f = 0.1 MHz, VCC = 2.4 V 2m A E=V IL,G=V IL, f = 5 MHz, VCC = 2.4 V 12 mA ICC1 1 Supply Current (Stand-by) CMOS E>V CC – 0.3 V 30 µA V IL Input Low Voltage –0.3 0.2 V V IH Input High Voltage VCC –0.3 V CC +0.3 V VOL Output Low Voltage IOL = 0.4 mA 0.15 V VOH Output High Voltage IOH = –100µAV CC –0.15 V Software Data Protection bit (DQ0).Reading the SDP bit (DQ0) allows the user to determine whether the Software Data Protection mode has been enabled (SDP=1) or disabled (SDP=0). The SDP bit (DQ0) can be read by using a dedicated algorithm (as shown in Figure 8), or can be combined with the reading of the DP bit (DQ7), TB bit (DQ6) and PLTS bit (DQ5).

Table 8B. Read Mode AC Characteristics for M28010-W (3V range) (TA = –40 to 85°C; VCC = 2.7 to 3.6 V) Note: 1. Output Hi-Z is defined as the point at which data is no longer driven. Table 8C. Read Mode AC Characteristics for M28010-R (2V range) (TA = –40 to 85°C; VCC = 1.8 to 2.4 V) Note: 1. Output Hi-Z is defined as the point at which data is no longer driven. Symbol Alt. Parameter Test Condit ion M28010-W Unit–10 –12 –15 Min Max Min Max Min Max tAVQV tACC Address Valid to Output Valid E=V IL, G=V IL 100 120 150 ns tELQV tCE Chip Enable Low to Output ValidG=V IL 100 120 150 ns tGLQV tOE Output Enable Low to Output Valid E = VIL 70 80 100 ns tEHQZ 1 tDF Chip Enable High to Output Hi-Z G = VIL 05 006 007 0 n s tGHQZ 1 tDF Output Enable High to Output Hi-ZE=V IL 05 006 007 0 n s tAXQX tOH Address Transition to Output Transition E=V IL, G=V IL 000 n s Symbol Alt. Parameter Test Condit ion M28010-R Unit–20 –25 Min Max Min Max tAVQV tACC Address Valid to Output Valid E=V IL, G=V IL 200 250 ns tELQV tCE Chip Enable Low to Output ValidG=V IL 200 250 ns tGLQV tOE Output Enable Low to Output Valid E = VIL 80 90 ns tEHQZ 1 tDF Chip Enable High to Output Hi-Z G = VIL 0 50 0 60 ns tGHQZ 1 tDF Output Enable High to Output Hi-ZE=V IL 0 50 0 60 ns tAXQX tOH Address Transition to Output Transition E=V IL, G=V IL 00 n s

Figure 11. Read Mode AC Waveforms (with Write Enable, W, high)

Table 9B. Write Mode AC Characteristics for M28010-W (3V range) (TA = –40 to 85°C; VCC = 2.7 to 3.6 V) Symbol Alt. Parameter Test Condition M28010-W Unit Min Max tAVWL tAS Address Valid to Write Enable Low E=V IL,G=V IH 0n s tAVEL tAS Address Valid to Chip Enable Low G=V IH,W =V IL 0n s tELWL tCES Chip Enable Low to Write Enable Low G=V IH 0n s tGHWL tOES Output Enable High to Write Enable Low E = V IL 0n s tGHEL tOES Output Enable High to Chip Enable Low W=V IL 0n s tWLEL tWES Write Enable Low to Chip Enable Low G = V IH 0n s tWLAX tAH Write Enable Low to Address Transition 70 ns tELAX tAH Chip Enable Low to Address Transition 70 ns tELEH tWP Chip Enable Low to Chip Enable High 100 ns tWHEH tCEH Write Enable High to Chip Enable High 0 ns tWHGL tOEH Write Enable High to Output Enable Low 0 ns tEHWH tWEH Chip Enable High to Write Enable High 0 ns tWHDX tDH Write Enable High to Input Transition 0 ns tEHDX tDH Chip Enable High to Input Transition 0 ns tWHWL tWPH Write Enable High to Write Enable Low 50 ns tWLWH tWP Write Enable Low to Write Enable High 100 ns tWLQ5H tBLC Time-out after the last byte write 150 µs tQ5HQ5X tWC Byte Write Cycle time 5 ms Page Write Cycle time (up to 128 bytes) 10 ms tDVWH tDS Data Valid before Write Enable High 80 ns tDVEH tDS Data Valid before Chip Enable High 80 ns

Table 9C. Write Mode AC Characteristics for M28010-R (2V range) (TA = –40 to 85°C; VCC = 1.8 to 2.4 V) Symbol Alt. Parameter Test Condition M28010-R Unit Min Max tAVWL tAS Address Valid to Write Enable Low E=V IL,G=V IH 0n s tAVEL tAS Address Valid to Chip Enable Low G=V IH,W =V IL 0n s tELWL tCES Chip Enable Low to Write Enable Low G=V IH 0n s tGHWL tOES Output Enable High to Write Enable Low E=V IL 0n s tGHEL tOES Output Enable High to Chip Enable Low W=V IL 0n s tWLEL tWES Write Enable Low to Chip Enable Low G=V IH 0n s tWLAX tAH Write Enable Low to Address Transition 120 ns tELAX tAH Chip Enable Low to Address Transition 120 ns tELEH tWP Chip Enable Low to Chip Enable High 120 ns tWHEH tCEH Write Enable High to Chip Enable High 0 ns tWHGL tOEH Write Enable High to Output Enable Low 0 ns tEHWH tWEH Chip Enable High to Write Enable High 0 ns tWHDX tDH Write Enable High to Input Transition 0 ns tEHDX tDH Chip Enable High to Input Transition 0 ns tWHWL tWPH Write Enable High to Write Enable Low 100 ns tWLWH tWP Write Enable Low to Write Enable High 120 ns tWLQ5H tBLC Time-out after the last byte write 150 µs tWHRH tWC Byte Write Cycle time 5 ms Page Write Cycle time (up to 128 bytes) 10 ms tDVWH tDS Data Valid before Write Enable High 120 ns tDVEH tDS Data Valid before Chip Enable High 120 ns

Table 10. Ordering Information Scheme Note: 1. This temperature range on request only.

ORDERING INFORMATION

Devices are shipped from the factory with the memory content set at all ‘1’s (FFh). The notation used for the device number is as shown in Table 10. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.

Figure 18. PDIP32 (BA) Note: 1. Drawing is not to scale. Table 11. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Mechanical Data

Table 12. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular Figure 19. PLCC32 (KA) Note: 1. Drawing is not to scale.

Table 13. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data Figure 20. TSOP32 (NS) Note: 1. Drawing is not to scale.

Table 14. Revision History 15-Feb-2000 I CC1 (max), in Read Mode DC Char table for 5V, changed from 30µAt o5 0µA.

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