M27W016 STMICROELECTRONICS | Alldatasheet
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16 Mbit (1Mb x16) 3V Supply FlexibleROM™ Memory
Figure 1. Packages
memory is supplied with all the bits set to ’1’. Figure 2. Logic Diagram Table 1. Signal Names
Figure 3. PDIP Connections Figure 4. SDIP Connections
Figure 5. SO Connections Figure 6. TSOP Connections
See Figure 2, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A19).The Address Inputs select the cells in the memory array to access dur- ing Bus Read operations. During Bus Write opera- tions they control the commands sent to the Command Interface of the Program Controller. Data Inputs/Outputs (DQ0-DQ7).The Data In- puts/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the command sent to the Command Interface of the Program Controller. When reading the Status Register they report the status of the ongoing algorithm. Data Inputs/Outputs (DQ8-DQ15).The Data In- puts/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations the Command Interface does not use these bits. When reading the Status Register these bits should be ignored. Chip Enable (E ).The Chip Enable, E, activates the memory, allowing Bus Read operations to be performed. It also controls the Bus Write opera- tions, when V PP is in the VHH range. Output Enable (G).The Output Enable, G, con- trols the Bus Read operations of the memory. It also allows Bus Write operations, when VPP is in the VHH range. VCC Supply Voltage.The V CC Supply Voltage supplies the power for Read operations. A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program opera- tions, I CC3 . V PP Program Supply Voltage. VPP is both a power supply and Write Protect pin. The two func- tions are selected by the voltage range applied to the pin. When the V PP is in the VHH range (see Table 10, DC Characteristic, for the relevant values) the Pro- gram operation is enabled. During such opera- tions the V PP must be stable in the VHH range. If the VPP is kept under the VHH range, particularly in the voltage range 0 to 3.6V, any Program oper- ation is disabled or stopped. Note that VPP must not be left floating or uncon- nected as the device may become unreliable. Vss Ground. The V SS Ground is the reference for all voltage measurements.
tics, for details of when the output becomes valid. level see Table 10, DC Characteristics. Program operation until the operation completes. Read operation is in progress. code, that can be read to identify the memory. Table 2. Bus Operations
- When reading Status Register during Program algorithm execution VPP must be kept at VHH .
All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. Failure to observe a valid sequence of Bus Write operations will result in the memory return- ing to Read mode. The long command sequences are imposed to maximize data security. Refer to Tables 3 and 4, for a summary of the com- mands. Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM, unless otherwise stated. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. V PP must be set to VHH during the Read/Reset command. If VPP is set to either VIL or VIH the com- mand will be ignored. The command can be is- sued, between Bus Write cycles before the start of a program operation, to return the device to read mode. Once the program operation has started the Read/Reset command is no longer accepted. Auto Select Command. The Auto Select command is used to read the Manufacturer Code and the Device Code. V PP must be set to VHH during the Auto Select com- mand. If VPP is set to either VIL or VIH the com- mand will be ignored. Three consecutive Bus Write operations are required to issue the Auto Se- lect command. Once the Auto Select command is issued the memory remains in Auto Select mode until a Read/Reset command is issued, all other commands are ignored. From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = V IL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. Word Program Command. The Word Program command can be used to pro- gram a Word to the memory array. V PP must be set to VHH during Word Program. If VPP is set to ei- ther VIL or VIH the command will be ignored, the data will remain unchanged and the device will re- vert to Read/Reset mode. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the PC. During the program operation the memory will ig- nore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 5. Bus Read op- erations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Regis- ter. A Read/Reset command must be issued to re- set the error condition and return to Read mode. Note that the Program command cannot change a bit set at ’0’ back to ’1’. Multiple Word Program Command The Multiple Word Program command can be used to program large streams of data. It greatly reduces the total programming time when a large number of Words are written in the memory at once. V PP must be set to VHH during Multiple Word Program. If VPP is set either VIL or VIH the com- mand will be ignored, the data will remain un- changed and the device will revert to Read mode. It has four phases: the Setup Phase to initiate the command, the Program Phase to program the data to the memory, the Verify Phase to check that the data has been correctly programmed and re- program if necessary and the Exit Phase. Setup Phase. The Multiple Word Program com- mand requires three Bus Write operations to ini- tiate the command (refer to Table 4, Multiple Word Program Command and Figure 8, Multiple Word Program Flowchart). The Status Register must be read in order to check that the PC has started (see Table 6 and Figure 8). Program Phase. The Program Phase requires n+1 Bus Write operations, where n is the number of Words, to execute the programming phase (re- fer to Table 4, Multiple Word Program and Figure 7, Multiple Word Program Flowchart). Before any Bus Write operation of the Program Phase, the Status Register must be read in order to check that the PC is ready to accept the opera- tion (see Table 6 and Figure 8). The Program Phase is executed in three different sub-phases: 1. The first Bus Write operation of the Program Phase (the 4th of the command) latches the Start Address and the first Word to be programmed. 2. Each subsequent Bus Write operation latches the next Word to be programmed and automatically increments the internal Address Bus. It is not necessary to provide the address of the location to be programmed but only a Continue Address, CA (A17 to A19 equal to the
Start Address), that indicates to the PC that the Program Phase has to continue. A0 to A16 are ‘don’t care’. 3. Finally, after all Words have been programmed, a Bus Write operation (the (n+1)th) with a Final Address, FA (A17 or a higher address pin different from the Start Address), ends the Program Phase. The memory is now set to enter the Verify Phase. Verify Phase.The Verify Phase is similar to the Program Phase in that all Words must be resent to the memory for them to be checked against the programmed data. Before any Bus Write Operation of the Verify Phase, the Status Register must be read in order to check that the PC is ready for the next operation or if the reprogram of the location has failed (see Table 6 and Figure 8). Three successive steps are required to execute the Verify Phase of the command: 1. The first Bus Write operation of the Verify Phase latches the Start Address and the Word to be verified. 2. Each subsequent Bus Write operation latches the next Word to be verified and automatically increments the internal Address Bus. As in the Program Phase, it is not necessary to provide the address of the location to be programmed but only a Continue Address, CA (A17 to A19 equal to the Start Address). 3. Finally, after all Words have been verified, a Bus Write cycle with a Final Address, FA (A17 or a higher address pin different from the Start Address) ends the Verify Phase. Exit Phase.After the Verify Phase ends, the Sta- tus Register must be read to check if the command has successfully completed or not (see Table 6 and Figure 8). If the Verify Phase is successful, the memory re- turns to Read mode and DQ6 stops toggling. If the PC fails to reprogram a given location, the Verify Phase terminates, DQ6 continues toggling and error bit DQ5 is set in the Status Register. If the error is due to a V PP failure DQ4 is also set. When the operation fails a Read/Reset command must be issued to return the device to Read mode. During the Multiple Word Program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the oper- ation. Typical program times are given in Table 5. Bus Read operations during the program opera- tion will output the Status Register on the Data In- puts/Outputs. See the section on the Status Register for more details. Note that the Multiple Word Program command cannot change a bit set to ’0’ back to ’1’.
Table 3. Standard Commands A0-A10 and DQ0-DQ7 to verify the commands; A11-A19, DQ8-DQ15 are Don’t Care. Table 4. Multiple Word Program Command Care, n = number of Words to be programmed. Table 5. Program Times
Figure 7. Multiple Word Program Flowchart
Table 6. Status Register Bits Note: 1. Unspecified data bits should be ignored.
- DQ4 = 0 if VPP ≥ VHH during Program algorithm execution; DQ4 = 1 if VPP < VHH during Program algorithm execution.
Figure 8. Data Polling Flowchart Figure 9. Data Toggle Flowchart
Table 7. Absolute Maximum Ratings Note: 1. Minimum voltage may undershoot to –2V for less than 20ns during transitions.
- Maximum voltage may overshoot to VCC +2V for less than 20ns during transitions.
- Maximum voltage may overshoot to 14.0V for less than 20ns during transitions. VPP must not remain at VHH for more than a total
Table 8. Operating and AC Measurement Conditions Figure 10. AC Measurement I/O Waveform Figure 11. AC Measurement Load Circuit Table 9. Device Capacitance Note: Sampled only, not 100% tested.
Table 10. DC Characteristics Note: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP .
Figure 12. Read AC Waveforms Table 11. Read AC Characteristics Note: 1. VPP must be applied after VCC and with the Chip Enable (E) at VIH.
- Sampled only, not 100% tested.
Figure 13. Chip Enable Controlled, Write AC Waveforms Table 12. Chip Enable Controlled, Write AC Characteristics VPP must be applied after VCC and with the Chip Enable (E) at VIH. Sampled only, not 100% tested.
- Not required in Auto Select or Read/Reset command sequences.
Figure 14. SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Outline Note: Drawing is not to scale. Table 13. SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Mechanical Data
Figure 15. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline Note: Drawing is not to scale. Table 14. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
Figure 16. PDIP42 - 42 pin Plastic DIP, 600 mils width, Bottom View Package Outline Note: Drawing is not to scale. Table 15. PDIP42 - 42 pin Plastic DIP, 600 mils width, Package Mechanical Data
Figure 17. SDIP42 - 42 pin Shrink Plastic DIP, 600 mils width, Package Outline Note: Drawing is not to scale. Table 16. SDIP42 - 42 pin Shrink Plastic DIP, 600 mils width, Package Mechanical Data
Table 17. Ordering Information Scheme Note: 1. This speed also guarantees 90ns access time at VCC = 3.0 to 3.6V. Devices are shipped from the factory with all the bits set to ’1’. vice, please contact the ST Sales Office nearest to you.
REVISION HISTORY
Table 18. Document Revision History
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics FlexibleROM is a pending trademark of STMicroelectronics All other names are the property of their respective owners © 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States