M27C4001-10F1 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 24
Technical content
Datasheet sections
- 1 Summary description
- 2 Device operation
- 2.1 Read Mode
- 2.2 Standby Mode
- 2.3 Two Line Output Control
- 2.4 System Considerations
- 2.5 Programming
- 2.6 PRESTO II Programming Algorithm
- 2.7 Program Inhibit
- 2.8 Program Verify
- 2.9 Electronic Signature
- 2.10 Erasure operation (applies to UV EPROM)
- 3 Maximum rating
- 4 DC and AC parameters
- 5 Package mechanical
- 6 Part numbering
- 7 Revision history
4 Mbit (512Kb x 8) UV EPROM and OTP EPROM
■ 5V ± 10% supply voltage in Read operation ■ Access time: 35ns ■ Low power consumption: – Active Current 30mA at 5MHz – Standby Current 100µA ■ Programming voltage: 12.75V ± 0.25V ■ Programming time: 100µs/Word ■ Electronic signature – Manufacturer Code: 20h – Device Code: 41h ■ Packages – ECOPACK® compliant versions FDIP32W (F) PLCC32 (C) TSOP32 (N) 8 x 20 mm PDIP32 (B) Obsolete Product(s) - Obsolete Product(s)
1 Summary description
large programs and is organised as 524,288 by 8 bits. written to the device by following the programming procedure. required, the M27C4001 is offered in PDIP32, PLCC32 and TSOP32 (8 x 20 mm) packages. on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 1. Logic Diagram Table 1. Signal names
Figure 2. DIP Connections Figure 3. LCC Connections
1 A16
32 VPP
Figure 4. TSOP Connections
2 Device operation
The operating modes of the M27C4001 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for VPP and 12V on A9 for Electronic Signature.
2.1 Read Mode
The M27C4001 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E ) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time (t AVQV ) is equal to the delay from E to output (tELQV ). Data is available at the output after a delay of tGLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV -tGLQV .
2.2 Standby Mode
The M27C4001 has a standby mode which reduces the supply current from 30mA to 100µA. The M27C4001 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input.
2.3 Two Line Output Control
Because EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows: a) the lowest possible memory power dissipation, b) complete assurance that output bus contention will not occur. For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device. Obsolete Product(s) - Obsolete Product(s)
2.4 System Considerations
The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, ICC , has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E . The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic capacitor be used on every device between V CC and VSS . This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used between VCC and VSS for every eight devices. The bulk capacitor should be located near the power supply connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.
2.5 Programming
When delivered (and after each erasure for UV EPROM), all bits of the M27C4001 are in the '1' state. Data is introduced by selectively programming '0's into the desired bit locations. Although only '0's will be programmed, both '1's and '0's can be present in the data word. The only way to change a '0' to a '1' is by die exposure to ultraviolet light (UV EPROM). The M27C4001 is in the programming mode when V PP input is at 12.75V, G is at VIH and E is pulsed to VIL. The data to be programmed is applied to 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. VCC is specified to be 6.25V ± 0.25V.
2.6 PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows the whole array to be programmed with a guaranteed margin, in a typical time of 52.5 seconds. Programming with PRESTO II consists of applying a sequence of 100µs program pulses to each byte until a correct verify occurs (see Figure 5). During programming and verify operation, a MARGIN MODE circuit is automatically activated in order to guarantee that each cell is programmed with enough margin. No overprogram pulse is applied since the verify in MARGIN MODE provides the necessary margin to each programmed cell. Obsolete Product(s) - Obsolete Product(s)
Figure 5. Programming Flowchart
2.7 Program Inhibit
2.8 Program Verify
2.9 Electronic Signature
2.10 Erasure operation (applies to UV EPROM)
- The erasure time with this dosage is approximately
have a filter on their tubes which should be removed before erasure. Table 2. Operating Modes (1) Table 3. Electronic Signature
3 Maximum rating
Program and other relevant quality documents. Table 4. Absolute Maximum Ratings
- Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period
+2V for a period less than 20ns.
4 DC and AC parameters
match the measurement conditions when relying on the quoted parameters. Figure 6. AC Testing Input Output Waveform Figure 7. AC Testing Load Circuit Table 5. AC Measurement Conditions
Table 6. Capacitance (1) (2)
- Sampled only, not 100% tested.
Table 7. Read Mode DC Characteristics(1) (2)
- V CC must be applied simultaneously with or before VPP and removed simultaneously or after VPP..
- Maximum DC voltage on Output is VCC +0.5V.
Table 8. Programming Mode DC Characteristics (1) (2)
- V CC must be applied simultaneously with or before VPP and removed simultaneously or after VPP .
Figure 8. Read Mode AC Waveforms Table 9. Read Mode AC Characteristics(1) (2)
- V CC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
- Speed obtained with High Speed AC measurement conditions.
- Sampled only, not 100% tested.
Table 10. Read Mode AC Characteristics(1) (2)
- V CC must be applied simultaneously with or before VPP and removed simultaneously or after VPP .
- Sampled only, not 100% tested.
Figure 9. Programming and Verify Modes AC Waveforms Table 11. Programming Mode AC Characteristics(1) (2) (3)
- V CC must be applied simultaneously with or before VPP and removed simultaneously or after VPP .
- Sampled only, not 100% tested.
5 Package mechanical
Figure 10. FDIP32W - 32 pin Ceramic Frit-seal DIP with window, Package Outline Table 12. FDIP32W - 32 pin Ceramic Frit-seal DIP with window, package mechanical
Figure 11. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Outline Table 13. PDIP32 - 32 lead Plastic DIP, 600 mils width, package mechanical data
Figure 12. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Outline Table 14. PLCC32 - 32 lead Plastic Leaded Chip Carrier, package mechanical data
Figure 13. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Outline Table 15. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package
6 Part numbering
aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. Table 16. Ordering Information Scheme
- High Speed, see AC Characteristics section for further information.
7 Revision history
Table 17. Document revision history Ordering Information Scheme.