M24M02-DR STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Description
- 2 Signal description
- 2.1 Serial Clock (SCL)
- 2.2 Serial Data (SDA)
- 2.3 Chip Enable (E2)
- 2.4 Write Control (WC
- 2.5 V SS (ground)
- 2.6 Supply voltage (V CC)
- 2.6.1 Operating supply voltage (V CC)
- 2.6.2 Power-up conditions
- 2.6.3 Device reset
- 2.6.4 Power-down conditions
- 3 Memory organization
- 4 Device operation
- 4.1 Start condition
- 4.2 Stop condition
- 4.3 Data input
- 4.4 Acknowledge bit (ACK)
- 4.5 Device addressing
- 5 Instructions
- 5.1 Write operations
- 5.1.1 Byte Write
- 5.1.2 Page Write
- 5.1.3 Write Identification Page
- 5.1.4 Lock Identification Page
- 5.1.5 ECC (Error Correction Code) and Write cycling
- 5.1.6 Minimizing Write delays by polling on ACK
- 5.2 Read operations
- 5.2.1 Random Address Read
Features
- Compatible with all I2C bus modes: –1 M H z – 400 kHz – 100 kHz
- Memory array: – 2 Mbit (256 Kbyte) of EEPROM – Page size: 256 byte – Additional Write lockable page
- Single supply voltage: – 1.8 V to 5.5 V over –40 °C / +85 °C
- Write: – Byte Write within 10 ms – Page Write within 10 ms
- Random and sequential Read modes
- Write protect of the whole memory array
- Enhanced ESD/Latch-Up protection
- More than 4 million Write cycles
- More than 200-years data retention Packages
- SO8 ECOPACK2®
- WLCSP ECOPACK2®
Table 15. SO8N – 8-lead plastic small outline, 150 mils body width, Table 16. WLCSP- 8-bump, 3.556 x 2.011 mm, wafer level chip scale
1 Description
PROgrammable Memory) organized as 256 K × 8 bits. temperature range of –40 °C / +85 °C. (later) permanently locked in Read-only mode. Figure 1. Logic diagram Figure 2. SO8 connections, top view
- DU: Don’t use (no signal should be applied on th is pin; if connected, must be connected to VSS)
- See Section 9: Package mechanical data for package dimensions, and how to identify pin 1
Table 1. Signal names
Figure 3. WLCSP connections
- DU: Don’t use (no signal should be applied on th is pin; if connected, must be connected to Vss)
- See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.
Table 2. Signals vs. bump position
2 Signal description
2.1 Serial Clock (SCL)
output the data on SDA(out).
2.2 Serial Data (SDA)
value of the pull-up resistor).
2.3 Chip Enable (E2)
Figure 4. Chip enable inputs connection
2.4 Write Control (WC )
driven low or left floating. acknowledged, Data bytes are not acknowledged.
2.5 V SS (ground)
VSS is the reference for the VCC supply voltage.
M24M02-DR Signal description
2.6 Supply voltage (V CC)
2.6.1 Operating supply voltage (V CC)
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (tW).
2.6.2 Power-up conditions
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage (see Operating conditions in Section 8: DC and AC parameters).
2.6.3 Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC has reached the internal reset threshold voltage. This threshold is lower than the minimum VCC operating voltage (see Operating conditions in Section 8: DC and AC parameters). When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode; however, the device must not be accessed until VCC reaches a valid and stable DC voltage within the specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8: DC and AC parameters). In a similar way, during power-down (continuous decrease in VCC), the device must not be accessed when VCC drops below VCC(min). When VCC drops below the power-on-reset threshold voltage, the device stops responding to any instruction sent to it.
2.6.4 Power-down conditions
During power-down (continuous decrease in VCC), the device must be in the Standby Power mode (mode reached after decoding a Stop condition, assuming that there is no internal write cycle in progress).
3 Memory organization
The memory is organized as shown below. Figure 5. Block diagram
4 Device operation
Figure 6. I2C bus protocol
Device operation M24M02-DR
4.1 Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition.
4.2 Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Read instruction that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode. A Stop condition at the end of a Write instruction triggers the internal Write cycle.
4.3 Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low.
4.4 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits.
4.5 Device addressing
in Table 3 (most significant bit first). Address is the same as the value on the Chip Enable (E2) input. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. the device select code, it deselects itself from the bus, and goes into Standby mode. Table 3. Device select code
- The most significant bit, b7, is sent first.
1010 E 2 (2)
- E2 bit value is compared to the logic level applied on the input pin E2.
1011 E 2
5 Instructions
5.1 Write operations
included in the Device Select code (see Table 4). not respond to any requests. accompanying data bytes are not acknowledged, as shown in Figure 8. Table 4. Most significant address byte Table 5. Least significant address byte
5.1.1 Byte Write
Figure 7. Write mode sequences with WC = 0 (data write enabled)
5.1.2 Page Write
The transfer is terminated by the bus master generating a Stop condition. Figure 8. Write mode sequences with WC = 1 (data write inhibited)
5.1.3 Write Identification Page
The Identification Page (256 byte) is an additional page which can be written and (later) permanently locked in Read-only mode. It is written by issuing the Write Identification Page instruction. This instruction uses the same protocol and format as Page Write (into memory array), except for the following differences:
- Device type identifier = 1011b
- MSB address bits A17/A8 are don't care except for address bit A10 which must be ‘0’. LSB address bits A7/A0 define the byte address inside the Identification page. If the Identification page is locked, the data bytes transferred during the Write Identification Page instruction are not acknowledged (NoAck).
5.1.4 Lock Identification Page
The Lock Identification Page instruction (Lock ID) permanently locks the Identification page in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with the following specific conditions:
- Device type identifier = 1011b
- Address bit A10 must be ‘1’; all other address bits are don't care
- The data byte must be equal to the binary value xxxx xx1x, where x is don't care
5.1.5 ECC (Error Correction Code) and Write cycling
The Error Correction Code (ECC) is an internal logic function which is transparent for the I2C communication protocol. The ECC logic is implemented on each group of four EEPROM bytes(1). Inside a group, if a single bit out of the four bytes happens to be erroneous during a Read operation, the ECC detects this bit and replaces it with the correct value. The read reliability is therefore much improved. Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently. In this case, the ECC function also writes/cycles the three other bytes located in the same group(1). As a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the 4 bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined Table 10: Cycling performance. 1. A group of four bytes is located at addresses [4 *N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.
5.1.6 Minimizing Write delays by polling on ACK
is shorter. To make use of this, a polling sequence can be used by the bus master.
- Initial condition: a Write cycle is in progress.
- Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction).
- Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 9. Write cycle polling flowchart using ACK
- The seven most significant bits of the Device Se lect code of a Random Read (bottom right box in the
5.2 Read operations
Read operations are performed independently of the state of the Write Control (WC) signal. incremented by one, to point to the next byte address. Figure 10. Read mode sequences
5.2.1 Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in Figure 10) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition.
5.2.2 Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only sends a device select code with the R/W bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 10, without acknowledging the byte. Note that the address counter value is defined by instructions accessing either the memory or the Identification page. When accessing the Identification page, the address counter value is loaded with the byte location in the Identification page, therefore the next Current Address Read in the memory uses this new address counter value. When accessing the memory, it is safer to always use the Random Address Read instruction (this instruction loads the address counter with the byte location to read in the memory, see Section 5.2.1) instead of the Current Address Read instruction.
5.2.3 Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 10. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter “rolls-over”, and the device continues to output data from memory address 00h.
5.2.4 Read Identification Page
The Identification Page (256 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. The Identification Page can be read by issuing an Read Identification Page instruction. This instruction uses the same protocol and format as the Random Address Read (from memory array) with device type identifier defined as 1011b. The MSB address bits A17/A8 are don't care, the LSB address bits A7/A0 define the byte address inside the Identification Page. The number of bytes to read in the ID page must not exceed the page boundary (e.g.: when reading the Identification Page from location 100d, the number of bytes should be less than or equal to 156, as the ID page boundary is 256 bytes).
5.2.5 Read the lock status
The locked/unlocked status of the Identification page can be checked by transmitting a specific truncated command [Identification Page Write instruction + one data byte] to the device. The device returns an acknowledge bit if the Identification page is unlocked, otherwise a NoAck bit if the Identification page is locked. Right after this, it is recommended to transmit to the device a Start condition followed by a Stop condition, so that:
- Start: the truncated command is not executed because the Start condition resets the device internal logic,
- Stop: the device is then set back into Standby mode by the Stop condition.
Initial delivery state M24M02-DR
6 Initial delivery state
The device is delivered with all the memory array bits and Identification page bits set to 1 (each byte contains FFh).
7 Maximum rating
Table 6. Absolute maximum ratings
- Compliant with JEDEC Std J-STD-020D (for small b ody, Sn-Pb or Pb-free assembly), the ST ECOPACK®
directive 2011/65/EU of July 2011).
- Positive and negative pulses applied on different co mbinations of pin connections, according to AEC-
Q100-002 (compliant with ANSI/ESDA/JEDEC JS-001-2012 standard, C1=100 pF, R1=1500 Ω).
8 DC and AC parameters
characteristics of the device. Figure 11. AC measurement I/O waveform Table 7. Operating conditions Table 8. AC measurement conditions Table 9. Input parameters
- Characterized only, not tested in production.
- input impedance when the memory is selected (after a Start condition).
Table 10. Cycling performance
- The write cycle endurance is defined for group of four bytes located at addresses [4*N, 4*N+1, 4*N+2,
4*N+3] where N is an integer. The Write cycle endurance is defined by characterization and qualification.
- A Write cycle is executed when either a Page Write, a Byte write, a Write Identification Page or a Lock
Table 11. Memory cell data retention
- For products identified by process letter K. The data retention behavior is checked in production, while the
200-year limit is defined from characterization and qualification results.
Table 12. DC characteristics
- Characterized only, not tested in production.
- The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
Table 13. 400 kHz AC characteristics
- Test conditions (in addition to t hose specified under Operating conditions and AC test measurement
conditions in Section 8: DC and AC parameters).
- Characterized only, not tested in production.
- There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
- The min value for t CLQX (Data out hold time) of the M24xxx devices offers a safe timing to bridge the
undefined region of the falling edge SCL.
- t CLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
0.7 VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 12.
- WC =0 set up time condition to enable the execution of a WRITE command.
- WC =0 hold time condition to enable the execution of a WRITE command.
Table 14. 1 MHz AC characteristics
- There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be less than 120 ns when fC < 1 MHz.
- Characterized only, not tested in production.
- To avoid spurious Start and Stop conditions, a mini mum delay is placed between SCL=1 and the falling or
- t CLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 13.
- WC =0 set up time condition to enable the execution of a WRITE command.
- WC =0 hold time condition to enable the execution of a WRITE command.
Figure 14. AC waveforms
9 Package mechanical data
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
9.1 SO8N package information
Figure 15. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
- Values in inches are converted fr om mm and rounded to four decimal digits.
Figure 16. SO8N – 8-lead plastic small outline, 150 mils body width,
- Dimensions are expr essed in millimeters.
9.2 WLCSP package information
Figure 17. WLCSP- 8-bump, 3.556 x 2.011 mm, wafer level chip scale
- Primary datum Z and seating plane are defined by the spherical crowns of the bump.
Figure 18. WLCSP- 8-bump, 3.556 x 2.011 mm, wafer level chip scale
- Dimensions are expr essed in millimeters.
- Values in inches are converted from mm and rounded to 4 decimal digits.
- Dimension is measured at the maximum bum p diameter parallel to primary datum Z.
10 Part numbering
Table 17. Ordering information scheme
- All packages are ECOPACK2® (RoHS compliant and free of brominated, chlorinated and antimony-oxide
- The process letters apply to WL CSP device only. These process letters appear on the device package
(marking) and on the shipment box. Please contact your nearest ST Sales Office for further information.
Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity.
Table 18. Document revision history 22-Dec-2010 1 Initial release. frequency, temperature grade)”. and Table 11: DC characteristics. – Table 4: Least significant address byte. Updated document template and text (minor changes). Removed information related to thin WLCSP package. (1) under Table 6: Absolute maximum ratings.
removed note on page 7, Updated Table 3: Device select code, updated section numbering for Section 5.2.4 and Section 5.2.5, updated note 1 on Table 11: Memory cell data retention, updated Figure 18: WLCSP- 8-bump, 3.556 x 2.011 mm, wafer level chip scale package recommended footprint. 27-Jul-2015 8 Updated: – Figure 3 with note 1. – Table 2 – Section 9.1: SO8N package information and Section 9.2: WLCSP
package information
Table 18. Document revision history (continued)