M24M01 STMICROELECTRONICS | Alldatasheet
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1 Mbit Serial I²C Bus EEPROM
Figure 1. Packages
CC or VSS , to establish the Device Select Code. Data bytes are not acknowledged. Figure 4. Maximum RL Value versus Bus Capacitance (CBUS ) for an I2C Bus
the bus master, and the other as the slave device. and will not respond unless one is given. (SDA) on the rising edge of Serial Clock (SCL). (on Serial Data (SDA), most significant bit first). Device Type Identifier is 1010b. set to 1 for Read and 0 for Write operations. Table 2. Device Select Code Note: 1. The most significant bit, b7, is sent first.
Figure 5. I2C Bus Protocol Table 3. Operating Modes
1 X reSTART, Device Select, RW = 1
Figure 6. Write Mode Sequences with WC=1 (data write inhibited) a Device Select Code with the RW bit reset to 0. bit, and then waits for the data byte. not acknowledged, as shown in Figure 6. Write, the internal memory Write cycle is triggered. trigger the internal Write cycle.
dition, as shown in Figure 7. Figure 7. Write Mode Sequences with WC
Figure 8. Write Cycle Polling Flowchart using ACK data from its internal latches to the memory cells. – Initial condition: a Write cycle is in progress.
Figure 9. Read Mode Sequences Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 4th bytes) must be identical. the state of the Write Control (WC) signal. the transfer with a Stop condition.
transfer with a Stop condition, as shown in Figure 9, without acknowledging the byte. Sequential Read This operation can be used after a Current Ad- dress Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the de- vice continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 9. The output data comes from consecutive address- es, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter ‘rolls-over’, and the device continues to output data from memory address 00h. Acknowledge in Read Mode For all Read commands, the device waits, after each byte read, for an acknowledgment during the th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device termi- nates the data transfer and switches to its Stand- by mode.
Table 4. Absolute Maximum Ratings
Table 5. Operating Conditions (M24M01-V) Table 6. Operating Conditions (M24M01-S) Table 7. AC Measurement Conditions Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. Figure 10. AC Measurement I/O Waveform Table 8. Capacitance
- Sampled only, not 100% tested.
Table 9. Power-Up Timing and Vth Threshold Note: 1. These parameters are characterized only. Table 10. DC Characteristics (M24M01-V) Table 11. DC Characteristics (M24M01-S)
Table 12. AC Characteristics Note: 1. For a reSTART condition, or following a Write cycle.
- Sampled only, not 100% tested.
- To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
Figure 11. AC Waveforms
LGA8 - 8 lead Land Grid Array, Package Outline Notes: 1. Drawing is not to scale. LGA8 - 8 lead Land Grid Array, Package Mechanical Data D E A2A1 T3D1 LGA-Z01B CONTACT 1 A ddd k Symb. mm inches ddd 0.100 – – 0.0039 – –
Table 13. Ordering Information Scheme
REVISION HISTORY
Table 14. Document Revision History
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