M24M01-R STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 30
Technical content
Datasheet sections
- 1 Description
- 2 Signal description
- 2.1 Serial Clock (SCL)
- 2.2 Serial Data (SDA)
- 2.3 Chip Enable (E1, E2)
- 2.4 Write Control (WC
- 2.5 V SS ground
- 2.6 Supply voltage (V CC)
- 2.6.1 Operating supply voltage V CC
- 2.6.2 Power-up conditions
- 2.6.3 Device reset
- 2.6.4 Power-down conditions
- 3 Device operation
- 3.1 Start condition
- 3.2 Stop condition
- 3.3 Acknowledge bit (ACK)
- 3.4 Data input
- 3.5 Memory addressing
- 3.6 Write operations
- 3.7 Byte Write
- 3.8 Page Write
- 3.9 ECC (error correction code) and Write cycli ng
- 3.10 Minimizing system delays by polling on ACK
- 3.11 Read operations
- 3.12 Random Address Read
- 3.13 Current Address Read
- 3.14 Sequential Read
- 3.15 Acknowledge in Read mode
- 4 Initial delivery state
Features
■ Compatible with I2C extended addressing ■ Two-wire I2C serial interface supports 1 MHz protocol ■ Single supply voltage: – 1.8 V to 5.5 V ■ Hardware write control ■ Byte and Page Write (up to 256 bytes) ■ Random and Sequential Read modes ■ Self-timed programming cycle ■ Automatic address incrementing ■ Enhanced ESD/Latch-Up protection ■ More than 1 million Write cycles ■ More than 40-year data retention ■ Packages – ECOPACK® (RoHS compliant) SO8 (MN) 150 mils width SO8 (MW) 208 mils width
Table 13. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package Table 14. SO8W – 8 lead plastic small outline, 208 mils body width, package
1 Description
(EEPROM) device organized as 128 Kb × 8 bits. bus master acknowledges the receipt of the data byte in the same way. packages. ECOPACK® packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 1. Logic diagram Table 1. Signal names
Figure 2. SO connections
- See Section 7: Package mechanical for package dimensions, and how to identify pin-1.
- NC = Not Connected internally.
2 Signal description
2.1 Serial Clock (SCL)
2.2 Serial Data (SDA)
the value of the pull-up resistor can be calculated).
2.3 Chip Enable (E1, E2)
Figure 3. Device select code
2.4 Write Control (WC )
Write operations are allowed. acknowledged, Data bytes are not acknowledged.
M24M01-R Signal description
2.5 V SS ground
VSS is the reference for the VCC supply voltage.
2.6 Supply voltage (V CC)
2.6.1 Operating supply voltage V CC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 7). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (t W).
2.6.2 Power-up conditions
When the power supply is turned on, VCC rises from VSS to VCC. The VCC rise time must not vary faster than 1 V/µs.
2.6.3 Device reset
In order to prevent inadvertent Write operations during power-up, a power on reset (POR) circuit is included. At power-up (continuous rise of V CC), the device does not respond to any instruction until VCC has reached the power on reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Table 7). When VCC passes over the POR threshold, the device is reset and is in Standby Power mode. In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops below the Power On Reset threshold voltage, the device stops responding to any instruction sent to it.
2.6.4 Power-down conditions
During power-down (continuous decrease in VCC), the device must be in the Standby Power mode (mode reached after decoding a Stop condition, assuming that is there is no internal Write cycle in progress).
Figure 6. I 2C bus protocol Table 2. Device select code
- The most significant bit, b7, is sent first.
- E1 and E2 are compared against the respecti ve external pins on the memory device.
Table 3. Most significant address byte Table 4. Least significant address byte
3 Device operation
The device supports the I2C protocol. This is summarized in Figure 6. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24M01-R device is always a slave in all communication.
3.1 Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given.
3.2 Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode. A Stop condition at the end of a Write command triggers the internal EEPROM Write cycle.
3.3 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9 th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits.
3.4 Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low.
3.5 Memory addressing
in Table 2 (on Serial Data (SDA), most significant bit first). “Address” (E2, E1). To address the memory array, the 4-bit device type identifier is 1010b. the Chip Enable (E1, E2) inputs. th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. the device select code, it deselects itself from the bus, and goes into Standby mode. Table 5. Operating modes
1 X reStart, device select, RW = 1
Figure 7. Write mode sequences with WC = 1 (data write inhibited)
3.6 Write operations
Following a Start condition the bus master sends a device select code with the R/W bit (RW) reset to 0. The device acknowledges this, as shown in Figure 8, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Writing to the memory may be inhibited if Write Control (WC ) is driven high. Any Write instruction with Write Control (WC) driven high (during a period of time from the Start condition until the end of the two address bytes) will not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in Figure 7. Each data byte in the memory has a 17-bit address (the most significant bit b16 is in the device select code and the Least Significant Bits b15-b0 are defined in two address bytes). The most significant byte (Table 3) is sent first, followed by the least significant byte (Table 4). When the bus master generates a Stop condition immediately after the Ack bit (in the “10 th bit” time slot), either at the end of a Byte Write or a Page Write, the internal memory Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. After the Stop condition, the delay t W, and the successful completion of a Write operation, the device’s internal address counter is incremented automatically, to point to the next byte address after the last one that was modified. During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests.
3.7 Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC ) being driven high, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 8.
3.8 Page Write
The Page Write mode allows up to 256 bytes to be written in a single Write cycle, provided that they are all located in the same ’row’ in the memory: that is, the most significant memory address bits, b15-b6, are the same. If more bytes are sent than will fit up to the end of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 256 bytes of data, each of which is acknowledged by the device if Write Control (WC ) is low. If Write Control (WC) is high, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck. After each byte is transferred, the internal byte address counter (the 6 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition.
Figure 8. Write mode sequences with WC = 0 (data write enabled)
3.9 ECC (error correction code) and Write cycling
benefit from the larger amount of Write cycles. routine that writes to the device by multiples of 4-byte words.
Figure 9. Write cycle polling flowchart using ACK
3.10 Minimizing system delays by polling on ACK
can be used by the bus master.
- Initial condition: a Write cycle is in progress.
- Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction).
- Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 10. Read mode sequences
- The seven most significant bits of the dev ice select code of a Random Read (in the 1st and 4th bytes) must
3.11 Read operations
Read operations are performed independently of the state of the Write Control (WC) signal. After the successful completion of a Read operation, the device’s internal address counter is incremented by one, to point to the next byte address.
3.12 Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in Figure 10) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition.
3.13 Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only sends a device select code with the R/W bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 10, without acknowledging the byte.
3.14 Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 10. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter ‘rolls-over’, and the device continues to output data from memory address 00h.
3.15 Acknowledge in Read mode
For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9 th bit time. If the bus master does not drive Serial Data (SDA) low during this time, the device terminates the data transfer and switches to its Standby mode.
4 Initial delivery state
The device is delivered with all the memory array bits set to 1 (each byte contains FFh).
5 Maximum rating
Table 6. Absolute maximum ratings
- Compliant with JEDEC Std J-STD- 020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
6 DC and AC parameters
match the measurement conditions when relying on the quoted parameters. Figure 11. AC measurement I/O waveform Table 7. Operating conditions Table 8. AC measurement conditions Table 9. Input parameters
- Sampled only, not 100% tested.
Table 10. DC characteristics
- Characterized value, not tested in production.
Table 11. AC characteristics at 400 kHz
- Values recommended by the I²C- bus Fast-Mode specification.
- To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
- t CLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC in a
× Cbus time constant is less than 500 ns (as specified in Figure 4).
- For a reStart condition, or following a Write cycle.
- Characterized only, not tested in production.
Table 12. AC characteristics at 1 MHz (preliminary data)
- Values recommended by the I²C- bus Fast-Mode specification.
- Characterized only, not tested in production.
- To avoid spurious Start and St op conditions, a minimum delay is placed between SCL=1 and the falling or
- t CLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC, assuming
that the Rbus × Cbus time constant is less than 150 ns (as specified in Figure 4).
- For a reStart condition, or following a Write cycle.
Figure 12. AC waveforms
7 Package mechanical
Figure 13. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package
- Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 14. SO8W – 8 lead plastic small outline, 208 mils body width, package outline
- The ‘1’ that appears in the top view of the package shows the position of pin 1 and the ‘N’ indicates the total
- Values in inches are converted from mm and rounded to 4 decimal digits.
8 Part numbering
of this device, please contact your nearest ST sales office. soldering conditions are also marked on the inner box label. Table 15. Ordering information scheme 6 = Industrial temperature range, –40 to 85 °C.
9 Revision history
Table 16. Document revision history 07-Dec-2006 1 Initial release. Document status promoted from Preliminary Data to full Datasheet. Section 2.6: Supply voltage (VCC) updated. Table 10: DC characteristics. Section 7: Package mechanical.
1 MHz maximum clock frequency added:
– Table 12: AC characteristics at 1 MHz (preliminary data) added. tDL1DL2 max modified, notes modified. (Cbus) for an I2C bus at maximum frequency fC = 400 kHz modified. Figure 12: AC waveforms modified. Small text changes.