M24LR64-R

M24LR64-R_12 STMICROELECTRONICS | Alldatasheet

Document overview

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• PDF pages: 128

Technical content

Datasheet sections

• 1 Description
• 2 Signal description
• 2.1 Serial Clock (SCL)
• 2.2 Serial Data (SDA)
• 2.3 Chip Enable (E0, E1)
• 2.4 Antenna coil (AC0, AC1)
• 2.6 Supply voltage (V CC)
• 2.6.1 Operating supply voltage V CC
• 2.6.2 Power-up conditions
• 2.6.3 Device reset
• 2.6.4 Power-down conditions
• 3 User memory organization
• 4 System memory area
• 4.1 M24LR64-R RF block security
• 4.2 Example of the M24LR64-R security protection
• 4.3 I2C_Write_Lock bit area
• 4.4 System parameters
• 4.5 M24LR64-R I
• 4.5.1 I 2C Present Password command description
• 4.5.2 I 2C Write Password command description
• 5.1 Start condition
• 5.2 Stop condition
• 5.3 Acknowledge bit (ACK)
• 5.4 Data Input
• 5.5 Memory addressing
• 5.6 Write operations
• 5.7 Byte Write

Datasheet sections

• 11.4 Low data rate
• 12 M24LR64-R to VCD frames
• 12.1 SOF when using one subcarrier
• 12.2 High data rate
• 12.3 Low data rate
• 12.4 SOF when using two subcarriers
• 12.5 High data rate
• 12.6 Low data rate
• 12.7 EOF when using one subcarrier
• 12.8 High data rate
• 12.9 Low data rate
• 12.10 EOF when using two subcarriers
• 12.11 High data rate
• 12.12 Low data rate
• 13 Unique identifier (UID)
• 14 Application family identifier (A FI)
• 15 Data storage format identifier (DSFID)
• 15.1 CRC
• 16 M24LR64-R protocol description
• 17 M24LR64-R states
• 17.1 Power-off state
• 17.2 Ready state
• 17.3 Quiet state
• 17.4 Selected state
• 18 Modes
• 18.1 Addressed mode
• 18.2 Non-addressed mode (general request)
• 18.3 Select mode

Datasheet sections

• 26.14 Write-sector Password
• 26.15 Lock-sector Password
• 26.16 Present-sector Password
• 26.17 Fast Read Single Block
• 26.18 Fast Inventory Initiated
• 26.19 Fast Initiate
• 26.20 Fast Read Multiple Block
• 26.21 Inventory Initiated
• 26.22 Initiate
• 27 Maximum rating
• 28 I 2C DC and AC parameters
• 29 RF electrical parameters
• 30 Package mechanical data
• 31 Part numbering

Features

■ Two-wire I2C serial interface supports 400 kHz protocol ■ Single supply voltage: – 1.8 V to 5.5 V ■ Byte and Page Write (up to 4 bytes) ■ Random and Sequential Read modes ■ Self-timed programming cycle ■ Automatic address incrementing ■ Enhanced ESD/latch-up protection Contactless interface ■ ISO 15693 and ISO 18000-3 mode 1 compatible ■ 13.56 MHz ±7k Hz carrier frequency ■ To tag: 10% or 100% ASK modulation using 1/4 (26 Kbit/s) or 1/256 (1.6 Kbit/s) pulse position coding ■ From tag: load modulation using Manchester coding with 423 kHz and 484 kHz subcarriers in low (6.6 kbit/s) or high (26 kbit/s) data rate mode. Supports the 53 kbit/s data rate with Fast commands ■ Internal tuning capacitance: 27.5 pF ■ 64-bit unique identifier (UID) ■ Read Block & Write (32-bit Blocks) Memory ■ 64 Kbit EEPROM organized into: – 8192 bytes in I 2C mode – 2048 blocks of 32 bits in RF mode ■ Write time 2C: 5 ms (Max.) – RF: 5.75 ms including the internal Verify time ■ More than 1 Million write cycles ■ Multiple password protection in RF mode ■ Single password protection in I2C mode ■ More than 40-year data retention ■ Package – ECOPACK2 ® (RoHS compliant and Halogen-free) SO8 (MN) 150 mils width UFDFPN8 (MB) 2 × 3 mm TSSOP8 (DW) Sawn wafer on UV tape

25.3 t 3: VCD new request delay in the absence of a response from

Table 100. I

Table 108. UFDFPN8 (MLP8) – Ultra thin fine pitch dual flat package no lead

1 Description

Figure 1. Logic diagram bit (RW) (as described in Table 2), terminated by an acknowledge bit. terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.

13.56 MHz carrier electromagnetic wave on which incoming data are demodulated from the

or a data rate of 26 Kbit/s using the 1/4 pulse coding mode. radio-frequency power and signal interface.

Figure 2. 8-pin package connections

1. See Package mechanical data section for package dimensions, and how to identify pin-1.

Table 1. Signal names

2 Signal description

2.1 Serial Clock (SCL)

2.2 Serial Data (SDA)

the value of the pull-up resistor can be calculated).

2.3 Chip Enable (E0, E1)

floating), these inputs are read as low (0,0). Figure 3. Device select code

2.4 Antenna coil (AC0, AC1)

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2.5 V SS ground

VSS is the reference for the VCC supply voltage.

2.6 Supply voltage (V CC)

This pin can be connected to an external DC supply voltage. Note: An internal voltage regulator allo ws the external voltage applied on VCC to supply the M24LR64-R, while preventing the internal power supply (rectified RF waveforms) to output a DC voltage on the V CC pin.

2.6.1 Operating supply voltage V CC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 100). To maintain a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal I²C write cycle (tW).

2.6.2 Power-up conditions

When the power supply is turned on, VCC rises from VSS to VCC. The VCC rise time must not vary faster than 1V/µs.

2.6.3 Device reset

In order to prevent inadvertent write operations during power-up, a power-on reset (POR) circuit is included. At power-up (continuous rise of V CC), the device does not respond to any instruction until VCC has reached the power-on reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Table 100). When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode, however, the device must not be accessed until V CC has reached a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range. In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops below the power-on reset threshold voltage, the device stops responding to any instruction sent to it.

2.6.4 Power-down conditions

During power-down (continuous decay of VCC), the device must be in Standby Power mode (mode reached after decoding a Stop condition, assuming that there is no internal write cycle in progress).

Table 2. Device select code

1. The most significant bit, b7, is sent first.
2. E0 and E1 are compared against the respecti ve external pins on the memory device.
3. E2 is not connected to any external pin. It is however used to address the M24LR64-R as described in

Table 3. Address most significant byte Table 4. Address least significant byte

3 User memory organization

The M24LR64-R is divided into 64 sectors of 32 blocks of 32 bits as shown in Table 5. possible if the addressed data are not in a protected sector. written by ST on the production line. Figure 6. Block diagram

Figure 7. Memory sector organization The M24LR64-R user memory is divided into 64 sectors. Each sector contains 1024 bits. The protection scheme is described in Section 4: System memory area. protected, a Write command updates the complete 32 bits of the selected block. must have the E2 Chip Enable address at 0.

Table 5. Sector details

Table 5. Sector details (continued)

4 System memory area

4.1 M24LR64-R RF block security

passwords, and each sector can also have Read/Write access conditions set. On delivery, the default value of the SSS bytes is reset to 00h. the sector as described in Table 8. Table 6. Sector Security Status Byte area Table 7. Sector security status byte organization

value these two bits is used to link a password to the sector as defined in Table 9. system area is described in Table 10.

• Write-sector Password: The Write-sector Password command is used to write a 32-bit block into the password system area. This command must be used to update password values. After the write cycle, the new password value is automatically activated. It is possible to modify a password value after issuing a valid Present-sector Password command. On delivery, the three default password values are set to 0000 0000h and are activated.
• Lock-sector Password: The Lock-sector Password command is used to set the Sector security status byte of the selected sector. Bits b4 to b1 of the Sector security status byte are affected by the Lock-sector Password command. The Sector Lock bit, b0, is set to ‘1’ automatically. After issuing a Lock-sector Password command, the protection settings of the selected sector are activated. The protection of a locked block cannot be changed in RF mode. A Lock-sector Password command sent to a locked sector returns an error code.

Table 8. Read / Write protection bit setting Table 9. Password Control bits

00 The sector is not protected by a Password

01 The sector is protected by the Password 1

10 The sector is protected by the Password 2

11 The sector is protected by the Password 3

Table 10. Password system area

1 Password 1

2 Password 2

3 Password 3

• Present-sector Password: The Present-sector Password command is used to present one of the three passwords to the M24LR64-R in order to modify the access rights of all the memory sectors linked to that password (Table 8) including the password itself. If the presented password is correct, the access rights remain activated until the tag is powered off or until a new Present-sector Password command is issued. If the presented password value is not correct, all the access rights of all the memory sectors are deactivated.
• Sector security status byte area access conditions in I2C mode: In I2C mode, read access to the Sector security status byte area is always allowed. Write access depends on the correct presentation of the I2C password (see I2C Present Password command description on page 27). To access the Sector security status byte area, the device select code used for any I2C command must have the E2 Chip Enable address at 1. An I2C write access to a Sector security status byte re-initializes the RF access condition to the given memory sector.

4.2 Example of the M24LR64-R security protection

sector access is changed as shown in Table 12. Table 11. M24LR64-R sector security protection after power-up

0 P r o t e c t i o n : S t a n d a r d R e a d N o W r i t e x x x 00001

1 P r o t e c t i o n : P s w d 1 R e a d N o W r i t e x x x 01001

2 P r o t e c t i o n : P s w d 1 R e a d W r i t e x x x 01011

3 P r o t e c t i o n : P s w d 1 N o R e a d N o W r i t e x x x 01101

4 P r o t e c t i o n : P s w d 1 N o R e a d N o W r i t e x x x 01111

Table 12. M24LR64-R sector security protection after a valid presentation of

0 Protection: Standard Read No Write xxx 0 0 0 0 1

1 Protection: Pswd 1 Read Write xxx 0 1 0 0 1

2 Protection: Pswd 1 Read Write xxx 0 1 0 1 1

3 Protection: Pswd 1 Read Write xxx 0 1 1 0 1

4 Protection: Pswd 1 Read No Write xxx 0 1 1 1 1

4.3 I2C_Write_Lock bit area

In the I2C mode only, it is possible to protect individual sectors against Write operations. it is possible to write-protect all the 64 sectors of the M24LR64-R memory. depends on the correct presentation of the I2C password. must have the E2 Chip Enable address at 1. On delivery, the default value of the 8 bytes of the I2C_Write_Lock bit area is reset to 00h.

4.4 System parameters

password using the I2C Write Password command described in Figure 9. read- nor write- accessible in the I2C mode. Table 13. I2C_Write_Lock bit

4.5 M24LR64-R I 2C password security

commands: I2C Present Password and I2C Write Password.

4.5.1 I 2C Present Password command description

Present Password command is issued. significant byte of the password is sent first, followed by the least significant bytes. not start the internal comparison. internal delay. If the values do not match, the protected sectors remains protected. Table 14. System parameter sector

1. Delivery state: I 2C password= 0000 0000h, RF password = 0000 0000h,

Figure 8. I 2C Present Password command

4.5.2 I 2C Write Password command description

after issuing a valid I2C Present Password command. On delivery, the I2C default password value is set to 0000 0000h and is activated. significant byte of the password is sent first, followed by the least significant bytes. does not trigger the internal write cycle. not respond to any requests. Ack generated during 9th bit time slot.

Figure 9. I 2C Write Password command Ack generated during 9th bit time slot.

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5 I 2C device operation

The device supports the I2C protocol. This is summarized in Figure 5. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24LR64-R device is always a slave in all communications.

5.1 Start condition

Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer command. The device continuously monitors (except during a write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given.

5.2 Stop condition

Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode. A Stop condition at the end of a Write command triggers the internal write cycle.

5.3 Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9 th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits.

5.4 Data Input

During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low.

5.5 Memory addressing

in Table 2 (on Serial Data (SDA), most significant bit first). the Chip Enable (E0, E1) inputs. th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. the device select code, it deselects itself from the bus, and goes into Standby mode. Figure 10. Write mode sequences with I2C_Write_Lock bit = 1 (data write inhibited) Table 15. Operating modes

I2C device operation M24LR64-R 32/128 Doc ID 15170 Rev 14

5.6 Write operations

Following a Start condition the bus master sends a device select code with the Read/Write bit (RW) reset to 0. The device acknowledges this, as shown in Figure 11, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Writing to the memory may be inhibited if the I2C_Write_Lock bit = 1. A Write instruction issued with the I2C_Write_Lock bit = 1 and with no I2C_Password presented, does not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in Figure 10. Each data byte in the memory has a 16-bit (two byte wide) address. The most significant byte (Table 3) is sent first, followed by the least significant byte (Table 4). Bits b15 to b0 form the address of the byte in memory. When the bus master generates a Stop condition immediately after the Ack bit (in the “10 th bit” time slot), either at the end of a Byte Write or a Page Write, the internal write cycle is triggered. A Stop condition at any other time slot does not trigger the internal write cycle. After the Stop condition, the delay t W, and the successful completion of a Write operation, the device’s internal address counter is incremented automatically, to point to the next byte address after the last one that was modified. During the internal write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests.

5.7 Byte Write

After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is write-protected by the I2C_Write_Lock bit (= 1), the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Write- protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 11.

5.8 Page Write

The Page Write mode allows up to 4 bytes to be written in a single Write cycle, provided that they are all located in the same “row” in the memory: that is, the most significant memory address bits (b12-b2) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 4 bytes of data, each of which is acknowledged by the device if the I2C_Write_Lock bit = 0 or the I2C_Password was correctly presented. If the I2C_Write_Lock_bit = 1 and the I2C_password is not presented, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck. After each byte is transferred, the internal byte address counter (inside the page) is incremented. The transfer is terminated by the bus master generating a Stop condition.

I2C device operation M24LR64-R 34/128 Doc ID 15170 Rev 14

5.9 Minimizing system delays by polling on ACK

During the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum I²C write time (tw) is shown in Table 104, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 12, is: 1. Initial condition: a write cycle is in progress. 2. Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction). 3. Step 2: if the device is busy with the in ternal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).

Figure 13. Read mode sequences

1. The seven most significant bits of the dev ice select code of a Random Read (in the 1st and 4th bytes) must

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5.10 Read operations

Read operations are performed independently of the state of the I2C_Write_Lock bit. After the successful completion of a Read operation, the device’s internal address counter is incremented by one, to point to the next byte address.

5.11 Random Address Read

A dummy Write is first performed to load the address into this address counter (as shown in Figure 13) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition.

5.12 Current Address Read

For the Current Address Read operation, following a Start condition, the bus master only sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 13, without acknowledging the byte.

5.13 Sequential Read

This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 13. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter ‘rolls-over’, and the device continues to output data from memory address 00h.

5.14 Acknowledge in Read mode

For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9 th bit time. If the bus master does not drive Serial Data (SDA) low during this time, the device terminates the data transfer and switches to its Standby mode.

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6 User memory initial state

The device is delivered with all bits in the user memory array set to 1 (each byte contains FFh).

7 RF device operation

The M24LR64-R is divided into 64 sectors of 32 blocks of 32 bits as shown in Table 5. Each sector can be individually read- and/or write-protected using a specific lock or password command. Read and Write operations are possible if the addressed block is not protected. During a Write, the 32 bits of the block are replaced by the new 32-bit value. The M24LR64-R also has a 64-bit block that is used to store the 64-bit unique identifier (UID). The UID is compliant with the ISO 15963 description, and its value is used during the anticollision sequence (Inventory). This block is not accessible by the user and its value is written by ST on the production line. The M24LR64-R also includes an AFI register in which the application family identifier is stored, and a DSFID register in which the data storage family identifier used in the anticollision algorithm is stored. The M24LR64-R has three additional 32-bit blocks in which the password codes are stored.

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7.1 Commands

The M24LR64-R supports the following commands:

• Inventory, used to perform the anticollision sequence.
• Stay Quiet, used to put the M24LR64-R in quiet mode, where it does not respond to any inventory command.
• Select, used to select the M24LR64-R. After this command, the M24LR64-R processes all Read/Write commands with Select_flag set.
• Reset To Ready, used to put the M24LR64-R in the ready state.
• Read Block, used to output the 32 bits of the selected block and its locking status.
• Write Block, used to write the 32-bit value in the selected block, provided that it is not locked.
• Read Multiple Blocks, used to read the selected blocks and send back their value.
• Write AFI, used to write the 8-bit value in the AFI register.
• Lock AFI, used to lock the AFI register.
• Write DSFID, used to write the 8-bit value in the DSFID register.
• Lock DSFID, used to lock the DSFID register.
• Get System Info, used to provide the system information value
• Get Multiple Block Security Status, used to send the security status of the selected block.
• Initiate, used to trigger the tag response to the Inventory Initiated sequence.
• Inventory Initiated, used to perform the anticollision sequence triggered by the Initiate command.
• Write-sector Password, used to write the 32 bits of the selected password.
• Lock-sector Password, used to write the Sector security status bits of the selected sector.
• Present-sector Password, enables the user to present a password to unprotect the user blocks linked to this password.
• Fast Initiate, used to trigger the tag response to the Inventory Initiated sequence.
• Fast Inventory Initiated, used to perform the anticollision sequence triggered by the Initiate command.
• Fast Read Single Block, used to output the 32 bits of the selected block and its locking status.
• Fast Read Multiple Blocks, used to read the selected blocks and send back their value.

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7.2 Initial dialog for vicinity cards

The dialog between the vicinity coupling device or VCD (commonly the “RF reader”) and the vicinity integrated circuit card or VICC (M24LR64-R) takes place as follows:

• activation of the M24LR64-R by the RF operating field of the VCD
• transmission of a command by the VCD
• transmission of a response by the M24LR64-R These operations use the RF power transfer and communication signal interface described below (see Power transfer, Frequency and Operating field). This technique is called RTF (Reader Talk First).

7.2.1 Power transfer

Power is transferred to the M24LR64-R by radio frequency at 13.56 MHz via coupling antennas in the M24LR64-R and the VCD. The RF operating field of the VCD is transformed on the M24LR64-R antenna to an AC Voltage which is rectified, filtered and internally regulated. The amplitude modulation (ASK) on this received signal is demodulated by the ASK demodulator.

7.2.2 Frequency

The ISO 15693 standard defines the carrier frequency (fC) of the operating field as 13.56 MHz ±7 kHz.

7.2.3 Operating field

The M24LR64-R operates continuously between the minimum and maximum values of the electromagnetic field H defined in Table 105. The VCD has to generate a field within these limits.

8 Communication signal from VCD to M24LR64-R

100%. The M24LR64-R decodes both. The VCD determines which index is used. b, the minimum signal amplitude of the carrier frequency. Figure 14. 100% modulation waveform The clock recovery shall be operational after t4 max.

Figure 15. 10% modulation waveform Table 16. 10% modulation parameters The VICC shall be operational for any value of modulation index between 10 % and 30 %.

9 Data rate and data coding

9.1 Data coding mode: 1 out of 256

1.65 Kbits/s (f

decimal) is sent by the VCD to the M24LR64-R. the value, as shown in Figure 17. transmit the data value FFh (255 decimal). Figure 16. 1 out of 256 coding mode

Figure 17. Detail of a time period

9.2 Data coding mode: 1 out of 4

successive pairs of bits form a byte, where the least significant pair of bits is transmitted first. Kbits/s (fC/512). Figure 18 illustrates the 1 out of 4 pulse position technique and coding. Figure 19 shows the transmission of E1h (225d - 1110 0001b) by the VCD.

9.3 VCD to M24LR64-R frames

implemented using code violation. Unused options are reserved for future use. sending a response frame to the VCD. The M24LR64-R takes a power-up time of 0.1 ms after being activated by the powering field. After this delay, the M24LR64-R is ready to receive a command frame from the VCD.

9.4 Start of frame (SOF)

The SOF defines the data coding mode the VCD is to use for the following command frame. sequence for either coding mode is described in Figure 22. Figure 20. SOF to select 1 out of 256 data coding mode Figure 21. SOF to select 1 out of 4 data coding mode

Figure 22. EOF for either data coding mode

10 Communications signal from M24LR64-R to VCD

operate in different noise environments and meet different application requirements.

10.1 Load modulation

generated by switching a load in the M24LR64-R.

10.2 Subcarrier

S1 of the subcarrier load modulation is 423.75 kHz (fC/32). continuous phase relationship between fS1 and fS2.

10.3 Data rates

rates produced by the M24LR64-R using the different response format combinations. Table 17. Response data rates

11 Bit representation and coding

commands using one subcarrier, all pulse numbers and times are divided by 2.

11.1 Bit coding using one subcarrier

11.1.1 High data rate

18.88 µs as shown in Figure 23. Figure 23. Logic 0, high data rate unmodulated time of 9.44 µs as shown in Figure 24. Figure 24. Logic 0, high data rate x2 (fC/32) as shown in Figure 25. Figure 25. Logic 1, high data rate pulses of 423.75 kHz (fC/32) as shown in Figure 26. Figure 26. Logic 1, high data rate x2

11.1.2 Low data rate

75.52 µs as shown in Figure 27. Figure 27. Logic 0, low data rate unmodulated time of 37.76 µs as shown in Figure 28. Figure 28. Logic 0, low data rate x2 (fC/32) as shown in Figure 29. Figure 29. Logic 1, low data rate 16 pulses at 423.75 kHz (fC/32) as shown in Figure 29. Figure 30. Logic 1, low data rate x2

11.2 Bit coding using two subcarriers

11.3 High data rate

(fC/28) as shown in Figure 31. For the Fast commands, the x2 mode is not available. Figure 31. Logic 0, high data rate (fC/32) as shown in Figure 32. For the Fast commands, the x2 mode is not available. Figure 32. Logic 1, high data rate

11.4 Low data rate

(fC/28) as shown in Figure 33. For the Fast commands, the x2 mode is not available. Figure 33. Logic 0, low data rate (fC/32) as shown in Figure 34. For the Fast commands, the x2 mode is not available. Figure 34. Logic 1, low data rate

12 M24LR64-R to VCD frames

Frames are delimited by an SOF and an EOF . They are implemented using code violation. frequency or frequencies is/are used. In this case the number of pulses is multiplied by 4. For the Fast commands using one subcarrier, all pulse numbers and times are divided by 2.

12.1 SOF when using one subcarrier

12.2 High data rate

at 423.75 kHz as shown in Figure 35. Figure 35. Start of frame, high data rate, one subcarrier 9.44µs followed by 4 pulses at 423.75 kHz as shown in Figure 36. Figure 36. Start of frame, high data rate, one subcarrier x2

12.3 Low data rate

at 423.75 kHz as shown in Figure 37. Figure 37. Start of frame, low data rate, one subcarrier

followed by 16 pulses at 423.75 kHz as shown in Figure 38. Figure 38. Start of frame, low data rate, one subcarrier x2

12.4 SOF when using two subcarriers

12.5 High data rate

423.75 kHz as shown in Figure 39. For the Fast commands, the x2 mode is not available. Figure 39. Start of frame, high data rate, two subcarriers

12.6 Low data rate

423.75 kHz as shown in Figure 40. For the Fast commands, the x2 mode is not available. Figure 40. Start of frame, low data rate, two subcarriers

12.7 EOF when using one subcarrier

12.8 High data rate

56.64 µs as shown in Figure 41. Figure 41. End of frame, high data rate, one subcarriers unmodulated time of 37.76 µs as shown in Figure 42. Figure 42. End of frame, high data rate, one subcarriers x2

12.9 Low data rate

226.56 µs as shown in Figure 43. Figure 43. End of frame, low data rate, one subcarriers unmodulated time of 113.28 µs as shown in Figure 44. Figure 44. End of frame, low data rate, one subcarriers x2

12.10 EOF when using two subcarriers

12.11 High data rate

(fC/28) as shown in Figure 45. For the Fast commands, the x2 mode is not available. Figure 45. End of frame, high data rate, two subcarriers

12.12 Low data rate

(fC/28) as shown in Figure 46. For the Fast commands, the x2 mode is not available. Figure 46. End of frame, low data rate, two subcarriers

13 Unique identifier (UID)

• 8 MSBs with a value of E0h
• The IC manufacturer code of ST 02h, on 8 bits (ISO/IEC 7816-6/AM1)
• a unique serial number on 48 bits With the UID each M24LR64-R can be addressed uniquely and individually during the anticollision loop and for one-to-one exchanges between a VCD and an M24LR64-R.

Table 18. UID format

the required application criteria. Figure 47. M24LR64-R decision tree for AFI programmed and Locked, it can no longer be modified. The most significant nibble of the AFI is used to code one specific or all application families. subfamilies. Subfamily codes different from 0 are proprietary.

15 Data storage format identifier (DSFID)

programmed and locked using the Write DSFID and Lock DSFID commands.

15.1 CRC

initial register contents are all ones: “FFFF”. the EOF . The CRC is calculated on all the bytes after the SOF up to the CRC field. valid. If it is invalid, the M24LR64-R discards the frame and does not answer to the VCD. discretion of the VCD designer. Table 19. CRC transmission rules

16 M24LR64-R protocol description

on the concept of “VCD talks first”.

• a request from the VCD to the M24LR64-R
• a response from the M24LR64-R to the VCD Each request and each response are contained in a frame. The frame delimiters (SOF , EOF) are described in Section 12: M24LR64-R to VCD frames. Each request consists of:
• a request SOF (see Figure 20 and Figure 21)
• flags
• a command code
• parameters, depending on the command
• application data
• a 2-byte CRC
• a request EOF (see Figure 22) Each response consists of:
• an answer SOF (see Figure 35 to Figure 40)
• flags
• parameters, depending on the command
• application data
• a 2-byte CRC
• an answer EOF (see Figure 41 to Figure 46) The protocol is bit-oriented. The number of bits transmitted in a frame is a multiple of eight (8), that is an integer number of bytes. A single-byte field is transmitted least significant bit (LSBit) first. A multiple-byte field is transmitted least significant byte (LSByte) first, each byte is transmitted least significant bit (LSBit) first. The setting of the flags indicates the presence of the optional fields. When the flag is set (to one), the field is present. When the flag is reset (to zero), the field is absent.

Table 20. VCD request frame format Table 21. M24LR64-R Response frame format

Figure 48. M24LR64-R protocol timing

M24LR64-R states M24LR64-R 60/128 Doc ID 15170 Rev 14

17 M24LR64-R states

An M24LR64-R can be in one of 4 states:

• Power-off
• Ready
• Quiet
• Selected Transitions between these states are specified in Figure 49: M24LR64-R state transition diagram and Table 22: M24LR64-R response depending on Request_flags.

17.1 Power-off state

The M24LR64-R is in the Power-off state when it does not receive enough energy from the VCD.

17.2 Ready state

The M24LR64-R is in the Ready state when it receives enough energy from the VCD. When in the Ready state, the M24LR64-R answers any request where the Select_flag is not set.

17.3 Quiet state

When in the Quiet state, the M24LR64-R answers any request except for Inventory requests with the Address_flag set.

17.4 Selected state

In the Selected state, the M24LR64-R answers any request in all modes (see Section 18: Modes):

• Request in Select mode with the Select_flag set
• Request in Addressed mode if the UID matches
• Request in Non-Addressed mode as it is the mode for general requests

Figure 49. M24LR64-R state transition diagram

1. The M24LR64-R returns to the “Power Off” state only when both conditions are met: the VCC pin is not
2. The intention of the state transition method is that only one M24LR64-R should be in the selected state at a

Table 22. M24LR64-R response depending on Request_flags

62/128 Doc ID 15170 Rev 14

18 Modes

The term “mode” refers to the mechanism used in a request to specify the set of M24LR64- Rs that will answer the request.

18.1 Addressed mode

When the Address_flag is set to 1 (Addressed mode), the request contains the Unique ID (UID) of the addressed M24LR64-R. Any M24LR64-R that receives a request with the Address_flag set to 1 compares the received Unique ID to its own. If it matches, then the M24LR64-R executes the request (if possible) and returns a response to the VCD as specified in the command description. If the UID does not match, then it remains silent.

18.2 Non-addressed mode (general request)

When the Address_flag is cleared to 0 (Non-Addressed mode), the request does not contain a Unique ID. Any M24LR64-R receiving a request with the Address_flag cleared to 0 executes it and returns a response to the VCD as specified in the command description.

18.3 Select mode

When the Select_flag is set to 1 (Select mode), the request does not contain an M24LR64- R Unique ID. The M24LR64-R in the Selected state that receives a request with the Select_flag set to 1 executes it and returns a response to the VCD as specified in the command description. Only M24LR64-Rs in the Selected state answer a request where the Select_flag set to 1. The system design ensures in theory that only one M24LR64-R can be in the Select state at a time.

19 Request format

• an SOF
• flags
• a command code
• parameters and data
• a CRC
• an EOF

19.1 Request flags

whether corresponding fields are present or not. Table 23. General request format Table 24. Definition of request flags 1 to 4

1. Subcarrier_flag refers to the M24LR64-R-to-VCD communication.

0 A single subcarrier frequency is used by the M24LR64-R

1 Two subcarrier are used by the M24LR64-R

1. Data_rate_flag refers to the M24LR64-R-to-VCD communication

0 Low data rate is used

1 High data rate is used

0 The meaning of flags 5 to 8 is described in Table 25

1 The meaning of flags 5 to 8 is described in Table 26

0 No Protocol format extension

1 Protocol format extension

Table 25. Request flags 5 to 8 when Bit 3 = 0

1. If the Select_flag is set to 1, the Address_flag is set to 0 and the UID field is not present in the request.

0 Request is executed by any M24LR64-R according to the setting of

1 Request is executed only by the M24LR64-R in Selected state

Table 26. Request flags 5 to 8 when Bit 3 = 1

0 AFI field is not present

1 AFI field is present

20 Response format

• an SOF
• flags
• parameters and data
• a CRC
• an EOF

20.1 Response flags

whether corresponding fields are present or not. The response flags consist of eight bits. Table 27. General response format Table 28. Definitions of response flags 1 to 8

0 No error

1 Error detected. E rror code is in the “Error” field.

20.2 Response error code

provides information about the error that occurred. Error codes not specified in Table 29 are reserved for future use. Table 29. Response error code definition 12h The specified block is locked an d its contents cannot be changed.

21 Anticollision

VCD field using their unique ID (UID). M24LR64-R communication by issuing the Inventory request. The M24LR64-R sends its response in the determined slot or does not respond.

21.1 Request parameters

• sets the Nb_slots_flag as desired
• adds the mask length and the mask value after the command field
• The mask length is the number of significant bits of the mask value.
• The mask value is contained in an integer number of bytes. The mask length indicates the number of significant bits. LSB is transmitted first
• If the mask length is not a multiple of 8 (bits), as many 0-bits as required will be added to the mask value MSB so that the mask value is contained in an integer number of bytes
• The next field starts at the next byte boundary. In the example of the Table 31 and Figure 50, the mask length is 11 bits. Five 0-bits are added to the mask value MSB. The 11-bit Mask and the current slot number are compared to the UID.

Table 30. Inventory request format Table 31. Example of the addition of 0-bits to an 11-bit mask value

Figure 50. Principle of comparison between the mask, the slot number and the UID The AFI field is present if the AFI_flag is set. The pulse is generated according to the definition of the EOF in ISO/IEC 15693-2. slot, the VCD sends an EOF .

• if no M24LR64-R answer is detected, the VCD may switch to the next slot by sending an EOF ,
• if one or more M24LR64-R answers are detected, the VCD waits until the complete frame has been received before sending an EOF for switching to the next slot. AI06682 Mask value received in the Inventory command 0000 0100 1100 1111 b 16 bits The Mask value less the padding 0s is loaded into the Tag comparator 100 1100 1111 b 11 bits The Slot counter is calculated xxxxNb_slots_flags = 0 (16 slots), Slot Counter is 4 bits The Slot counter is concatened to the Mask value xxxx 100 1100 1111 bNb_slots_flags = 0 15 bits The concatenated result is compared with the least significant bits of the Tag UID. LSBMSB b LSBMSB LSBMSB LSBMSB b0b63 CompareBits ignored UID 4 bits

M24LR64-R Request processing by the M24LR64-R Doc ID 15170 Rev 14 69/128

22 Request processing by the M24LR64-R

Upon reception of a valid request, the M24LR64-R performs the following algorithm:

• NbS is the total number of slots (1 or 16)
• SN is the current slot number (0 to 15)
• LSB (value, n) function returns the n Less Significant Bits of value
• MSB (value, n) function returns the n Most Significant Bits of value
• “&” is the concatenation operator
• Slot_Frame is either an SOF or an EOF SN = 0 if (Nb_slots_flag) then NbS = 1 SN_length = 0 endif else NbS = 16 SN_length = 4 endif label1: if LSB(UID, SN_length + Mask_length) = LSB(SN,SN_length)&LSB(Mask,Mask_length) then answer to inventory request endif wait (Slot_Frame) if Slot_Frame = SOF then Stop Anticollision decode/process request exit endif if Slot_Frame = EOF if SN < NbS-1 then SN = SN + 1 goto label1 exit endif endif

Explanation of the possible cases M24LR64-R 70/128 Doc ID 15170 Rev 14

23 Explanation of the possible cases

Figure 51 summarizes the main possible cases that can occur during an anticollision sequence when the slot number is 16. The different steps are:

• The VCD sends an Inventory request, in a frame terminated by an EOF . The number of slots is 16.
• M24LR64-R_1 transmits its response in Slot 0. It is the only one to do so, therefore no collision occurs and its UID is received and registered by the VCD;
• The VCD sends an EOF in order to switch to the next slot.
• In slot 1, two M24LR64-Rs, M24LR64-R_2 and M24LR64-R_3 transmit a response, thus generating a collision. The VCD records the event and remembers that a collision was detected in Slot 1.
• The VCD sends an EOF in order to switch to the next slot.
• In Slot 2, no M24LR64-R transmits a response. Therefore the VCD does not detect any M24LR64-R SOF and decides to switch to the next slot by sending an EOF .
• In slot 3, there is another collision caused by responses from M24LR64-R_4 and M24LR64-R_5
• The VCD then decides to send a request (for instance a Read Block) to M24LR64-R_1 whose UID has already been correctly received.
• All M24LR64-Rs detect an SOF and exit the anticollision sequence. They process this request and since the request is addressed to M24LR64-R_1, only M24LR64-R_1 transmits a response.
• All M24LR64-Rs are ready to receive another request. If it is an Inventory command, the slot numbering sequence restarts from 0. Note: The decision to interrupt the anticollision sequence is made by the VCD. It could have continued to send EOFs until Slot 16 and only then sent the request to M24LR64-R_1.

Figure 51. Description of a possible anticollision sequence

Inventory Initiated command M24LR64-R 72/128 Doc ID 15170 Rev 14

24 Inventory Initiated command

The M24LR64-R provides a special feature to improve the inventory time response of moving tags using the Initiate_flag value. This flag, controlled by the Initiate command, allows tags to answer to Inventory Initiated commands. For applications in which multiple tags are moving in front of a reader, it is possible to miss tags using the standard inventory command. The reason is that the inventory sequence has to be performed on a global tree search. For example, a tag with a particular UID value may have to wait the run of a long tree search before being inventoried. If the delay is too long, the tag may be out of the field before it has been detected. Using the Initiate command, the inventory sequence is optimized. When multiple tags are moving in front of a reader, the ones which are within the reader field will be initiated by the Initiate command. In this case, a small batch of tags will answer to the Inventory Initiated command which will optimize the time necessary to identify all the tags. When finished, the reader has to issue a new Initiate command in order to initiate a new small batch of tags which are new inside the reader field. It is also possible to reduce the inventory sequence time using the Fast Initiate and Fast Inventory Initiated commands. These commands allow the M24LR64-Rs to increase their response data rate by a factor of 2, up to 53 Kbit/s.

25 Timing definition

from the reception of the EOF from the M24LR64-Rs. modulation index used for transmitting the VCD request to the M24LR64-R. described in Table 48: M24LR64-R protocol timing. Values of t2 are given in Table 32. M24LR64-R response has been received. modulation index used for transmitting the VCD request to the M24LR64-R.

• If this EOF is 100% modulated, the VCD waits a time at least equal to t3min before sending a new EOF .
• If this EOF is 10% modulated, the VCD waits a time at least equal to the sum of t3min + the M24LR64-R nominal response time (which depends on the M24LR64-R data rate and subcarrier modulation mode) before sending a new EOF .

Table 32. Timing values (1)

1. The tolerance of specific timings is ± 32/fC.
2. t1max does not apply for write alike requests. Timing conditions for write alike requests are defined in the
3. t SOF is the time taken by the M24LR64-R to transmit an SOF to the VCD. tSOF depends on the current data

rate: High data rate or Low data rate.

26 Commands codes

Table 33. Command codes

26.1 Inventory

• the flags,
• the Inventory command code (see Table 33: Command codes)
• the AFI if the AFI flag is set
• the mask length
• the mask value
• the CRC The M24LR64-R does not generate any answer in case of error. The response contains:
• the flags
• the Unique ID During an Inventory process, if the VCD does not receive an RF M24LR64-R response, it waits a time t3 before sending an EOF to switch to the next slot. t3 starts from the rising edge of the request EOF sent by the VCD.
• If the VCD sends a 100% modulated EOF , the minimum value of t3 is: t3min = 4384/fC (323.3µs) + tSOF
• If the VCD sends a 10% modulated EOF , the minimum value of t3 is: t3min = 4384/fC (323.3µs) + tNRT where:
• tSOF is the time required by the M24LR64-R to transmit an SOF to the VCD
• tNRT is the nominal response time of the M24LR64-R tNRT and tSOF are dependent on the M24LR64-R-to-VCD data rate and subcarrier modulation mode.

Table 34. Inventory request format Table 35. Inventory response format

26.2 Stay Quiet

command even if an error occurs.

• the M24LR64-R does not process any request if the Inventory_flag is set,
• the M24LR64-R processes any Addressed request The M24LR64-R exits the Quiet State when:
• it is reset (power off),
• receiving a Select request. It then goes to the Selected state,
• receiving a Reset to Ready request. It then goes to the Ready state. The Stay Quiet command must always be executed in Addressed mode (Select_flag is reset to 0 and Address_flag is set to 1).

Table 36. Stay Quiet request format Figure 52. Stay Quiet frame exchange between VCD and M24LR64-R

26.3 Read Single Block

M24LR64-R answers with an error code. The Option_flag is supported.

• Option_flag
• UID (optional)
• Block number Response parameters:
• Sector security status if Option_flag is set (see Table 39: Sector security status)
• 4 bytes of block data

Table 37. Read Single Block request format

1. Gray means that t he field is optional.

Table 38. Read Single Block response format when Error_flag is NOT set

1. Gray means that t he field is optional.

Table 39. Sector security status Table 40. Read Single Block response format when Error_flag is set

• Error code as Error_flag is set – 03h: the option is not supported – 0Fh: error with no information given – 10h: the specified block is not available – 15h: the specified block is read-protected

Figure 53. Read Single Block frame exchange between VCD and M24LR64-R

26.4 Write Single Block

error code. The Option_flag is supported. t, there should be no modulation (neither 100% nor 10%). time is equal to t1nom + 18 × 302 µs.

• UID (optional)
• Block number
• Data Response parameter:
• No parameter. The response is send back after the writing cycle. Response parameter:
• Error code as Error_flag is set: – 03h: the option is not supported – 0Fh: error with no information given – 10h: the specified block is not available – 12h: the specified block is locked and its contents cannot be changed. – 13h: the specified block was not successfully programmed

Table 41. Write Single Block request format

1. Gray means that t he field is optional.

Table 42. Write Single Block response format when Error_flag is NOT set Table 43. Write Single Block response format when Error_flag is set

Figure 54. Write Single Block frame exchange between VCD and M24LR64-R

26.5 Read Multiple Block

sector. If the number of blocks overlaps sectors, the M24LR64-R returns an error code. the Protocol_extention_flag is at 0, the M24LR64-R answers with an error code. The Option_flag is supported.

• Option_flag
• UID (optional)
• First block number
• Number of blocks Response parameters:
• Sector security status if Option_flag is set (see Table 46: Sector security status)
• N blocks of data

Table 44. Read Multiple Block request format

1. Gray means that t he field is optional.

Table 45. Read Multiple Block response format when Error_flag is NOT set

1. Gray means that t he field is optional.

Table 46. Sector security status

• Error code as Error_flag is set: – 03h: the option is not supported – 0Fh: error with no information given – 10h: the specified block is not available – 15h: the specified block is read-protected

Table 47. Read Multiple Block response format when Error_flag is set Figure 55. Read Multiple Block frame exchange between VCD and M24LR64-R

26.6 Select

• if the UID is equal to its own UID, the M24LR64-R enters or stays in the Selected state and sends a response.
• if the UID does not match its own, the selected M24LR64-R returns to the Ready state and does not send a response. The M24LR64-R answers an error code only if the UID is equal to its own UID. If not, no response is generated. If an error occurs, the M24LR64-R remains in its current state. Request parameter:
• UID Response parameter:
• No parameter. Response parameter:
• Error code as Error_flag is set: – 03h: the option is not supported – 0Fh: error with no information given

Table 48. Select request format Table 49. Select Block response format when Error_flag is NOT set Table 50. Select response format when Error_flag is set Figure 56. Select frame exchange between VCD and M24LR64-R

26.7 Reset to Ready

is equal to its own UID. If not, no response is generated.

• UID (optional) Response parameter:
• No parameter Response parameter:
• Error code as Error_flag is set: – 03h: the option is not supported – 0Fh: error with no information given

Table 51. Reset to Ready request format

1. Gray means that t he field is optional.

Table 52. Reset to Ready response format when Error_flag is NOT set Table 53. Reset to ready response format when Error_flag is set Figure 57. Reset to Ready frame exchange between VCD and M24LR64-R

26.8 Write AFI

memory. The Option_flag is supported. During the RF write cycle Wt, there should be no modulation (neither 100% nor 10%). time is equal to t1nom + 18 × 302 µs.

• UID (optional)
• AFI Response parameter:
• No parameter. Response parameter:
• Error code as Error_flag is set – 03h: the option is not supported – 0Fh: error with no information given – 12h: the specified block is locked and its contents cannot be changed. – 13h: the specified block was not successfully programmed

Table 54. Write AFI request format

1. Gray means that t he field is optional.

Table 55. Write AFI response format when Error_flag is NOT set Table 56. Write AFI response format when Error_flag is set

Figure 58. Write AFI frame exchange between VCD and M24LR64-R

26.9 Lock AFI

During the RF write cycle Wt, there should be no modulation (neither 100% nor 10%).

• UID (optional) Response parameter:
• No parameter Response parameter:
• Error code as Error_flag is set – 03h: the option is not supported – 0Fh: error with no information given – 11h: the specified block is already locked and thus cannot be locked again – 14h: the specified block was not successfully locked

Table 57. Lock AFI request format

1. Gray means that t he field is optional.

Table 58. Lock AFI response format when Error_flag is NOT set Table 59. Lock AFI response format when Error_flag is set

Figure 59. Lock AFI frame exchange between VCD and M24LR64-R

26.10 Write DSFID

its memory. The Option_flag is supported. During the RF write cycle Wt, there should be no modulation (neither 100% nor 10%). is equal to t1nom + 18 × 302 µs.

• UID (optional)
• DSFID Response parameter:
• No parameter Response parameter:
• Error code as Error_flag is set – 03h: the option is not supported – 0Fh: error with no information given – 12h: the specified block is locked and its contents cannot be changed. – 13h: the specified block was not successfully programmed

Table 60. Write DSFID request format

1. Gray means that t he field is optional.

Table 61. Write DSFID response format when Error_flag is NOT set Table 62. Write DSFID response format when Error_flag is set

Figure 60. Write DSFID frame exchange between VCD and M24LR64-R

26.11 Lock DSFID

On receiving the Lock DSFID request, the M24LR64-R locks the DSFID value permanently. The Option_flag is supported. During the RF write cycle Wt, there should be no modulation (neither 100% nor 10%). is equal to t1nom + 18 × 302 µs.

• UID (optional) Response parameter:
• No parameter. Response parameter:
• Error code as Error_flag is set: – 03h: the option is not supported – 0Fh: error with no information given – 11h: the specified block is already locked and thus cannot be locked again – 14h: the specified block was not successfully locked

Table 63. Lock DSFID request format

1. Gray means that t he field is optional.

Table 64. Lock DSFID response format when Error_flag is NOT set Table 65. Lock DSFID response format when Error_flag is set

Figure 61. Lock DSFID frame exchange between VCD and M24LR64-R

26.12 Get System Info

Info can be issued in both Addressed and Non Addressed modes. the Protocol_extention_flag is at 0, the M24LR64-R answers with an error code.

• UID (optional) Response parameters:
• Information flags set to 0Fh. DSFID, AFI, Memory Size and IC reference fields are present
• UID code on 64 bits
• DSFID value
• AFI value
• Memory size. The M24LR64-R provides 2048 blocks (07FFh) of 4 byte (03h)
• IC reference. Only the 6 MSB are significant. Response parameter:
• Error code as Error_flag is set: – 03h: Option not supported – 0Fh: other error

Table 66. Get System Info request format

1. Gray means that t he field is optional.

Table 67. Get System Info response format when Error_flag is NOT set Table 68. Get System Info response format when Error_flag is set

Figure 62. Get System Info frame exchange between VCD and M24LR64-R

26.13 Get Multiple Bl ock Security Status

blocks” field requests to return the security status of 7 blocks. the Protocol_extention_flag is at 0, the M24LR64-R answers with an error code.

• UID (optional)
• First block number
• Number of blocks Response parameters:
• Sector security status (see Table 71: Sector security status)

Table 69. Get Multiple Block Security Status request format

1. Gray means that t he field is optional.

Table 70. Get Multiple Block Security Status response format when Error_flag is Table 71. Sector security status

• Error code as Error_flag is set: – 03h: the option is not supported – 0Fh: error with no information given – 10h: the specified block is not available

Table 72. Get Multiple Block Security Status response format when Error_flag is Figure 63. Get Multiple Block Security Status frame exchange between VCD and

26.14 Write-sector Password

successful in the response. The Option_flag is supported. value until M24LR64-R power-down.

• UID (optional)
• Password number (01h = Pswd1, 02h = Pswd2, 03h = Pswd3, other = Error)
• Data Response parameter:
• 32-bit password value. The response is sent back after the write cycle. Response parameter:
• Error code as Error_flag is set: – 02h: the command is not recognized, for example: a format error occurred – 03h: the option is not supported – 0Fh: error with no information given – 10h: the specified block is not available – 12h: the specified block is locked and its contents cannot be changed. – 13h: the specified block was not successfully programmed

Table 73. Write-sector Pa ssword request format

1. Gray means that t he field is optional.

Table 74. Write-sector Password response format when Error_flag is NOT set Table 75. Write-sector Password response format when Error_flag is set

Figure 64. Write-sector Password frame exchange between VCD and M24LR64-R

26.15 Lock-sector Password

and permanently locks the selected sector. The Option_flag is supported. automatically locked by a single command. the Protocol_extention_flag is at 0, the M24LR64-R answers with an error code. otherwise, the M24LR64-R may not correctly lock the memory block. t time is equal to t1nom + 18 × 302 µs.

• (optional) UID
• Sector number
• Sector security status (refer to Table 77) Response parameter:
• No parameter.

Table 76. Lock-sector Password request format

1. Gray means that t he field is optional.

Table 77. Sector security status Table 78. Lock-sector Password response format when Error_flag is NOT set Table 79. Lock-sector Password response format when Error_flag is set

• Error code as Error_flag is set: – 02h: the command is not recognized, for example: a format error occurred – 03h: the option is not supported – 0Fh: error with no information given – 10h: the specified block is not available – 11h: the specified block is already locked and thus cannot be locked again – 14h: the specified block was not successfully locked

Figure 65. Lock-sector Password frame exchange between VCD and M24LR64-R

26.16 Present-sector Password

operation has been successful in the response. The Option_flag is supported. 10%) otherwise, the M24LR64-R the Password value may not be correctly compared. t time is equal to t1nom + 18 × 302 µs. changed as described in Section 4.1: M24LR64-R RF block security.

• UID (optional)
• Password Number (0x01 = Pswd1, 0x02 = Pswd2, 0x03 = Pswd3, other = Error)
• Data Response parameter:
• No parameter. The response is send back after the write cycle. Response parameter:
• Error code as Error_flag is set: – 02h: the command is not recognized, for example: a format error occurred – 03h: the option is not supported – 0Fh: error with no information given – 10h: the specified block is not available

Table 80. Present-sector Password request format

1. Gray means that t he field is optional.

Table 81. Present-sector Password response format when Error_flag is NOT set Table 82. Present-sector Password response format when Error_flag is set

Figure 66. Present-sector Password frame exchange between VCD and M24LR64-R

26.17 Fast Read Single Block

data rate of the response is multiplied by 2. the Protocol_extention_flag is at 0, the M24LR64-R answers with an error code.

• Option_flag
• UID (optional)
• Block number Response parameters:
• Sector security status if Option_flag is set (see Table 85)
• 4 bytes of block data

Table 83. Fast Read Single Block request format

1. Gray means that t he field is optional.

Table 84. Fast Read Single Block response format when Error_flag is NOT set

1. Gray means that t he field is optional.

Table 85. Sector security status Table 86. Fast Read Single Block response format when Error_flag is set

• Error code as Error_flag is set: – 02h: the command is not recognized, for example: a format error occurred – 03h: the option is not supported – 0Fh: error with no information given – 10h: the specified block is not available – 15h: the specified block is read protected

Figure 67. Fast Read Single Block frame exchange between VCD and M24LR64-R

26.18 Fast Inventory Initiated

does not answer to the Fast Inventory Initiated command.

• the flags,
• the Inventory command code
• the AFI if the AFI flag is set
• the mask length
• the mask value
• the CRC The M24LR64-R does not generate any answer in case of error. The Response contains:
• the flags
• the Unique ID During an Inventory process, if the VCD does not receive an RF M24LR64-R response, it waits a time t3 before sending an EOF to switch to the next slot. t3 starts from the rising edge of the request EOF sent by the VCD.
• If the VCD sends a 100% modulated EOF , the minimum value of t3 is: t3min = 4384/fC (323.3µs) + tSOF
• If the VCD sends a 10% modulated EOF , the minimum value of t3 is: t3min = 4384/fC (323.3µs) + tNRT where:
• tSOF is the time required by the M24LR64-R to transmit an SOF to the VCD
• tNRT is the nominal response time of the M24LR64-R

Table 87. Fast Inventory Initiated request format Table 88. Fast Inventory Initiated response format

26.19 Fast Initiate

a power off of the M24LR64-R. The data rate of the response is multiplied by 2.

• No data The response contains:
• the flags
• the Unique ID

Table 89. Fast Initiate request format Table 90. Fast Initiate response format Figure 68. Fast Initiate frame exchange between VCD and M24LR64-R

26.20 Fast Read Multiple Block

sector. If the number of blocks overlaps sectors, the M24LR64-R returns an error code. the Protocol_extention_flag is at 0, the M24LR64-R answers with an error code. The Option_flag is supported. The data rate of the response is multiplied by 2.

• Option_flag
• UID (Optional)
• First block number
• Number of blocks Response parameters:
• Sector security status if Option_flag is set (see Table 93: Sector security status if Option_flag is set)
• N block of data

Table 91. Fast Read Multiple Block request format

1. Gray means that t he field is optional.

Table 92. Fast Read Multiple Block response format when Error_flag is NOT set

1. Gray means that t he field is optional.

Table 93. Sector security status if Option_flag is set

• Error code as Error_flag is set: – 0Fh: other error – 10h: block address not available

Table 94. Fast Read Multiple Block response format when Error_flag is set Figure 69. Fast Read Multiple Block frame exchange between VCD and M24LR64-R

26.21 Inventory Initiated

does not answer to the Inventory Initiated command. Table 26: Request flags 5 to 8 when Bit 3 = 1.

• the flags,
• the Inventory Command code
• the AFI if the AFI flag is set
• the mask length
• the mask value
• the CRC The M24LR64-R does not generate any answer in case of error. The response contains:
• the flags
• the Unique ID During an Inventory process, if the VCD does not receive an RF M24LR64-R response, it waits a time t3 before sending an EOF to switch to the next slot. t3 starts from the rising edge of the request EOF sent by the VCD.
• If the VCD sends a 100% modulated EOF , the minimum value of t3 is: t3min = 4384/fC (323.3µs) + tSOF
• If the VCD sends a 10% modulated EOF , the minimum value of t3 is: t3min = 4384/fC (323.3µs) + tNRT where:
• tSOF is the time required by the M24LR64-R to transmit an SOF to the VCD
• tNRT is the nominal response time of the M24LR64-R tNRT and tSOF are dependent on the M24LR64-R-to-VCD data rate and subcarrier modulation mode.

Table 95. Inventory Initiated request format Table 96. Inventory Initiated response format

26.22 Initiate

a power off of the M24LR64-R.

• No data The response contains:
• the flags
• the Unique ID

Table 97. Initiate request format Table 98. Initiate Initiated response format Figure 70. Initiate frame exchange between VCD and M24LR64-R

27 Maximum rating

Program and other relevant quality documents. Table 99. Absolute maximum ratings

1. Counted from ST shipment date.
2. Compliant with JEDEC Std J-STD-020C (for smal l body, Sn-Pb or Pb assembly), the ST ECOPACK®
3. As required by the IEC 61000-4-2 method. M24LR 64-R is mounted on ST’s reference antenna ANT1-

28 I 2C DC and AC parameters

their circuit match the measurement conditions when relying on the quoted parameters. Figure 71. AC test measurement I/O waveform Table 100. I 2C operating conditions Table 101. AC test measurement conditions Table 102. Input parameters

Table 103. I 2C DC characteristics

1. SCL, SDA according to AC input waveform Figure 71. E0, E1 connected to Ground or VCC
2. Characterized value, not tested in production.

Table 104. I 2C AC characteristics

1. Values recommended by the I² C-bus Fast-Mode specification.
2. To avoid spurious Start and St op conditions, a minimum delay is placed between SCL=1 and the falling or
3. t CLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC in a

× Cbus time constant is less than 500 ns (as specified in Figure 4).

1. For a reStart condition, or following a write cycle.

Figure 72. I 2C AC waveforms

29 RF electrical parameters

their circuit match the measurement conditions when relying on the quoted parameters. Table 105. RF characteristics (1) (2)

specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 74. SO8N – 8-lead plastic small outlin e, 150 mils body width, package outline Table 107. SO8N – 8-lead plastic small outline, 150 mils body width, package data

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 75. UFDFPN8 (MLP8) – Ultra thin fine pitch dual flat package no lead

1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from

Figure 76. TSSOP8 – 8-lead thin shrink small outline, package outline Table 109. TSSOP8 – 8-lead thin shrink small outline, package mechanical data

1. Values in inches are converted from mm and rounded to 4 decimal digits.

31 Part numbering

Table 110. Ordering information scheme for packaged devices

Note: 1 Refer to technical note TN0185 for details on the die delivery form. of this device, please contact your nearest ST sales office. Table 111. Ordering information scheme for bare die devices

M24LR64-R Anticollision algorithm (informative) Doc ID 15170 Rev 14 123/128 Appendix A Anticollision algorithm (informative) The following pseudocode describes how anticollision could be implemented on the VCD, using recursivity. A.1 Algorithm for pulsed slots function push (mask, address); pushes on private stack function pop (mask, address); pops from private stack function pulse_next_pause; generates a power pulse function store(M24LR64-R_UID); stores M24LR64-R_UID function poll_loop (sub_address_size as integer) pop (mask, address) mask = address & mask; generates new mask ; send the request mode = anticollision send_Request (Request_cmd, mode, mask length, mask value) for sub_address = 0 to (2^sub_address_size - 1) pulse_next_pause if no_collision_is_detected ; M24LR64-R is inventoried then store (M24LR64-R_UID) else ; remember a collision was detected push(mask,address) endif next sub_address if stack_not_empty ; if some collisions have been detected and then ; not yet processed, the function calls itself poll_loop (sub_address_size); recursively to process the last stored collision endif end poll_loop main_cycle: mask = null address = null push (mask, address) poll_loop(sub_address_size) end_main_cycle

Table 112. CRC definition

M24LR64-R CRC (informative) Doc ID 15170 Rev 14 125/128 number_of_databytes = NUMBER_OF_BYTES; else // check CRC number_of_databytes = NUMBER_OF_BYTES + 2; current_crc_value = PRESET_VALUE; for (i = 0; i < number_of_databytes; i++) current_crc_value = current_crc_value ^ ((unsigned int)array_of_databytes[i]); for (j = 0; j < 8; j++) if (current_crc_value & 0x0001) current_crc_value = (current_crc_value >> 1) ^ POLYNOMIAL; else current_crc_value = (current_crc_value >> 1); if (calculate_or_check_crc == CALC_CRC) current_crc_value = ~current_crc_value; printf ("Generated CRC is 0x%04X\\n", current_crc_value); // current_crc_value is now ready to be appended to the data stream // (first LSByte, then MSByte) else // check CRC if (current_crc_value == CHECK_VALUE) printf ("Checked CRC is ok (0x%04X)\\n", current_crc_value); else printf ("Checked CRC is NOT ok (0x%04X)\\n", current_crc_value);

required application criteria. locked, it cannot be modified. subfamilies. Subfamily codes different from 0 are proprietary. Table 113. AFI coding (1) ‘1 '‘0’, ‘Y’ Transport Mass transit, Bus, Airline,... '2 '‘0’, ‘Y’ Financial IEP , Banking, Retail,... '3 '‘0’, ‘Y’ Identification Access Control,... '4 '‘0’, ‘Y’ Telecommunication Public Telephony, GSM,... '6 '‘0’, ‘Y’ Multimedia Internet services.... 8 '‘0’, ‘Y’ Data Storage Portable Files,...

Doc ID 15170 Rev 14 127/128

Revision history

Table 114. Document revision history 26-Feb-2010 8 Previous revisions: design and engineering phase. Added 8” wafer delivery form and update endurance on cover page. Section 2.6: Supply voltage (VCC). Byte area and Table 14: System parameter sector. Updated hSTG in Table 99: Absolute maximum ratings. Added Table 111: Ordering information scheme for bare die devices. Updated ISO references under Features. maximum ratings and Table 105: RF characteristics. Renamed Section 29 and Table 105. Deleted Table 106 RF DC Characteristics. 27-Oct-2011 13 Updated footnote (2) of Table 105: RF characteristics. 05-Jan-2012 14 Modified Table 10: Password system area on page 24.