M24L816512SA-70BEG

M24L816512SA ESMT | Alldatasheet

Document overview

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Technical content

Features

‧Advanced low-power architecture

• High speed: 55 ns, 70 ns
• Wide voltage range: 2.7V to 3.6V
• Typical active current: 2 mA @ f = 1 MHz
• Typical active current: 11 mA @ f = fMAX
• Low standby power
• Automatic power-down when deselected Functional Description The M24L816512SA is a high-performance CMOS pseudo static RAM (PSRAM) organized as 512K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for portable applications such as cellular telephones. The device can be put into standby mode when deselected ( CE HIGH or both BHE and BLE are HIGH). The input/output pins (I/O0through I/O 15) are placed in a high-impedance state when : deselected ( CE HIGH), outputs are disabled ( OE HIGH), both Byte High Enable and Byte Low Enable are disabled ( BHE , BLE HIGH), or during a write operation ( CE LOW and WE LOW). Writing to the device is accomplished by taking Chip Enable( CE LOW) and Write Enable ( WE ) input LOW. If Byte Low Enable (BLE ) is LOW, then data from I/O pins (I/O0 through I/O 7) is written into the location specified on the address pins(A0 through A 18). If Byte High Enable ( BHE ) is LOW, then data from I/O pins (I/O 8 through I/O 15) is written into the location specified on the address pins (A 0 through A18). Reading from the device is accomplished by taking Chip Enable ( CE LOW) and Output Enable ( OE ) LOW while forcing the Write Enable ( WE ) HIGH. If Byte Low Enable ( BLE ) is LOW, then data from the memory location specified by the address pins will appear on I/O 0 to I/O 7. If Byte High Enable( BHE ) is LOW, then data from memory will appear on I/O8 toI/O15. Refer to the truth table for a complete description of read and write modes. Logic Block Diagram

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jun. 2009 Revision : 1.5 2/14 Pin Configuration[2, 3, 4] 48-ball VFBGA Top View 44-Pin TSOPII(Note*) Top View (Default) (TypeA) CE I/O0 I/O1 I/O2 I/O3 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 V SS VCC I/O11 I/O10 I/O9 I/O8 A18 A10 A11 A17 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A18 A17 A16 A15 A14 V SS VCC I/O11 I/O10 I/O9 I/O8 A10 A11 A12 A13 CE I/O0 I/O1 I/O2 I/O3 Note* : The default pin arrangement of TSOPII package of the device is as ”Default” figure. User also can control pin 18~28 to turn into pin arrangement of “Type A” with software. (The difference in pin arrangement between ”Default” and “Type A” is pin 18~28)

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jun. 2009 Revision : 1.5 3/14 Product Portfolio Product Power Dissipation Operating ICC(mA) VCC Range (V) f = 1MHz f = f MAX Standby, ISB2(µA) Product Min. Typ. Max. Speed(ns) 55 22 M24L816512SA 2.7 3.0 3.6 2 5 11 100 110(for Vcc > 3.3V) Notes: 2.DNU pins are to be left floating or tied to VSS. 3.Ball G2, H6 are the address expansion pins for the 16-Mbit and 32-Mbit densities respectively. 4.NC “no connect”—not connected internally to the die. 5.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ) and TA = 25°C.

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jun. 2009 Revision : 1.5 4/14 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Ambient Temperature with DC Voltage Applied to Outputs (per MIL-STD-883, Method 3015) Operating Range Range Ambient Temperature (TA) VCC Extended −25°C to +85°C 2.7V to 3.6V Industrial −40°C to +85°C 2.7V to 3.6V -55 -70 Parameter Description Test Conditions Min. Typ .[5] Max. Min. Typ. [5] Max. Unit VOH Output HIGH Voltage IOH = −0.1 mA VCC-

0.4 VCC-

0.4 V VOL Output LOW Voltage IOL = 0.1 mA 0.4 0.4 V VIH Input HIGH Voltage 0.8* VCC VCC+ 0.4V 0.8* VCC VCC+0 .4V V VIL Input LOW Voltage f = 0 -0.4 0.4 -0.4 0.4 V IIX Input Leakage Current GND ≤VIN < VCC -1 +1 -1 +1 µA IOZ Output Leakage Current GND ≤ V OUT ≤ V CC, Output Disabled -1 +1 -1 +1 µA f = fMAX = 1/tRC 11 22 11 17 ICC VCC Operating Supply Current f = 1 MHz VCC = 3.6V IOUT = 0mA CMOS level 2 5 2 5 mA ISB1 Automatic CE Power-Down Current —CMOS Inputs CE ≥VCC − 0.2V, VIN ≥ V CC − 0.2V, VIN ≤ 0.2V, f = f MAX (Address and Data Only), f = 0 ( OE , WE , BHE and BLE ) 100 400 100 400 µA VCC = 3.3V 100 100 ISB2 Automatic CE Power-Down Current —CMOS Inputs CE ≥ V CC−0.2V, VIN ≥ V CC − 0.2V or VIN ≤ 0.2V, f = 0 VCC = 3.6V 110 110 µA Capacitance[9] Parameter Description Test Conditions Max. Unit CIN Input Capacitance 8 pF COUT Output Capacitance TA = 25°C, f = 1 MHz VCC = VCC(typ) 8 pF Thermal Resistance[9] Parameter Description Test Conditions BGA Unit ΘJA Thermal Resistance(Junction to Ambient) 55 °C/W ΘJC Thermal Resistance (Junction to Case) Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/ JESD51. 17 °C/W Notes: 6.VIH(MAX) = VCC + 0.5V for pulse durations less than 20 ns. 7.VIL(MIN) = –0.5V for pulse durations less than 20 ns. 8.Overshoot and undershoot specifications are characterized and are not 100% tested. 9.Tested initially and after design or process changes that may affect these parameters.

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jun. 2009 Revision : 1.5 5/14 AC Test Loads and Waveforms Parameters 3.0V V CC Unit R1 22000 Ω R2 22000 Ω RTH 11000 Ω VTH 1.50 V Switching Characteristics Over the Operating Range[10, 11, 12, 13, 14] -55 -70 Parameter Description Min. Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 55[14] 70 ns tAA Address to Data Valid 55 70 ns tOHA Data Hold from Address Change 5 5 ns tACE CE LOW to Data Valid 55 70 ns tDOE OE LOW to Data Valid 25 35 ns tLZOE OE LOW to LOW Z[11, 12] 5 5 ns tHZOE OE HIGH to High Z[11, 12] 25 25 ns tLZCE CE LOW to Low Z[11, 12] 5 5 ns tHZCE CE HIGH to High Z[11, 12] 25 25 ns tDBE BLE / BHE LOW to Data Valid 55 70 ns tLZBE BLE / BHE LOW to Low Z[11, 12] 5 5 ns tHZBE BLE / BHE HIGH to High Z[11, 12] 10 25 ns tSK[14] Address Skew 0 10 ns Notes: 10. Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of V CC(typ)/2, input pulse levels of 0V to V CC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance 11. t HZOE, tHZCE, tHZBE, and tHZWEtransitions are measured when the outputs enter a high-impedance state. 12. High-Z and Low-Z parameters are characterized and are not 100% tested. 13. The internal write time of the memory is defined by the overlap of WE , CE = V IL, BHE and/or BLE = V IL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates write. 14. To achieve 55-ns performance, the read access should be CE controlled. In this case t ACE is the critical parameter and tSK is satisfied when the addresses are stable prior to chip enab le going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle.

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jun. 2009 Revision : 1.5 6/14 Switching Characteristics (Over the Operating Range) (continued)[10, 11, 12, 13, 14] -55 -70 Parameter Description Min. Max. Min. Max. Unit Write Cycle[13] tWC Write Cycle Time 55 70 ns tSCE CE LOW to Write End 45 55 ns tAW Address Set-up to Write End 45 55 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-up to Write Start 0 0 ns tPWE WE Pulse Width 40 55 ns tBW BLE / BHE LOW to Write End 50 55 ns tSD Data Set-up to Write End 42 42 ns tHD Data Hold from Write End 0 0 ns tHZWE WE LOW to High-Z[11, 12] 25 25 ns tLZWE WE HIGH to Low-Z[11, 12] 5 5 ns Switching Waveforms Read Cycle 1 (Address Transition Controlled)[14, 15, 16] Read Cycle 2 ( OE Controlled)[14, 15] Notes: 15. WE is HIGH for Read Cycle. 16. Device is continuously selected. OE , CE = V IL

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jun. 2009 Revision : 1.5 7/14 Switching Waveforms (continued) Write Cycle 1 ( WE Controlled) [12, 13, 17, 18, 19] Write Cycle 2 (CE Controlled) [12, 13, 17, 18, 19] Notes: 17.Data I/O is high impedance if OE ≥ V IH. 18.If Chip Enable goes INACTIVE simultaneously with WE = HIGH, the output remains in a high-impedance state. 19.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jun. 2009 Revision : 1.5 8/14 Switching Waveforms (continued) Write Cycle 3 ( WE Controlled, OE LOW)[18, 19] Write Cycle 4 (BHE /BLE Controlled, OE LOW)[18, 19]

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jun. 2009 Revision : 1.5 9/14 Avoid Timing ESMT Pseudo SRAM has a timing which is not supported at read operation, If your system has multiple invalid address signal shorter than tRC during over 15μs at read operation shown as in Abnormal Timing, it requires a normal read timing at leat during 15μs shown as in Avoidable timing 1 or toggle CE to high ( ≧tRC) one time at least shown as in Avoidable Timing 2. Abnormal Timing Avoidable Timing 1 Avoidable Timing 2 CE ≧15μ s WE Address ＜ tRC CE ≧15μ s WE Address t≧ RC CE ≧15μ s WE Address ＜ tRC t≧ RC

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jun. 2009 Revision : 1.5 10/14 Truth Table[20] CE WE OE BHE BLE Inputs/Outputs Mode Power H X X X X High Z Deselect/Power-Down Standby (I SB) X X X H H High Z Deselect/Power-Down Standby (I SB) L H L L L Data Out (I/O 0–I/O15) Read (Upper Byte and Lower Byte) Active (ICC) L H L H L Data Out (I/O 0–I/O7); (I/O8–I/O15) in High Z Read (Lower Byte only) Active (I CC) L H L L H Data Out (I/O 8–I/O15); (I/O0–I/O7) in High Z Read (Upper Byte only) Active (I CC) L H H L L High Z Output Disabled Active (ICC) L H H H L High Z Output Disabled Active (ICC) L H H L H High Z Output Disabled Active (ICC) L L X L L Data In (I/O 0–I/O15) Write (Upper Byte and Lower Byte) Active (ICC) L L X H L Data In (I/O0–I/O7); (I/O8–I/O15) in High Z Write (Lower Byte Only) Active (ICC) L L X L H Data Out (I/O8–I/O15); (I/O0–I/O7) in High Z Write (Upper Byte Only) Active (ICC)

Ordering Information

Speed (ns) Ordering Code Package Type Operating Range 55 M24L816512SA-55BEG 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.2 mm) (Pb-Free) Extended 70 M24L816512SA -70 BEG 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.2 mm) (Pb-Free) Extended

55 M24L816512SA-55TEG 44-pin TSOPII (Pb-Free) Extended

70 M24L816512SA-70TEG 44-pin TSOPII (Pb-Free) Extended

55 M24L816512SA-55BIG 48-ball Very Fine Pitch BG A (6.0 x 8.0 x 1.2 mm) (Pb-Free) Industrial 70 M24L816512SA-70BIG 48-ball Very Fine Pitch BG A (6.0 x 8.0 x 1.2 mm) (Pb-Free) Industrial

55 M24L816512SA-55TIG 44-pin TSOPII (Pb-Free) Industrial

70 M24L816512SA-70TIG 44-pin TSOPII (Pb-Free) Industrial

Note: 20.H = Logic HIGH, L = Logic LOW, X = Don’t Care.

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jun. 2009 Revision : 1.5 11/14 Package Diagrams 48-Ball (6 mm x 8mm x 1.2 mm) FBGA

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jun. 2009 Revision : 1.5 12/14 44-LEAD TSOP(II) PSRAM(400mil) Symbol Dimension in mm Dimension in inch Min Norm Max Min Norm Max A 1.20 0.047 A1 0.05 0.15 0.002 0.006 B 0.30 0.45 0.012 0.018 C 0.12 0.21 0.005 0.008 C1 0.10 0.16 0.004 0.006 ZD 0.805 REF 0.0317 REF L1 0.80 REF 0.031 REF e 0.80 BSC 0.0315 BSC θ °0 °8 °0 °8

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jun. 2009 Revision : 1.5 13/14

Revision History

1.0 2008.02.27 Original 1.1 2008.03.24 Add I-grade for TSOPII package 1.2 2008.06.23 1. Move Revision History to the last 1.3 2008.07.04 Add Industr ial grade for BGA package 1.4 2009.02.20 1.Correct Logic Block Diagram 2.Correct the ball name of H1 in BGA configuration 1.5 2009.06.22 Correct the ball nam e of D3 in BGA configuration

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jun. 2009 Revision : 1.5 14/14 Important Notice All rights reserved. No part of this document may be rep roduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the produ cts or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patent s, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inher ently a certain rate of failure. To minimize risks associated with cust omer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support device s or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its ow n quality assurance testing appropriate to such applications.