M24L48512DA ESMT | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 12

Technical content

Features

  • Advanced low power architecture
  • High speed: 55 ns, 60 ns and 70 ns
  • Wide voltage range: 2.7V to 3.6V
  • Typical active current: 1mA @ f = 1 MHz
  • Low standby power
  • Automatic power-down when deselected Functional Description The M24L48512DA is a high-performance CMOS pseudo static RAM (PSRAM) organized as 512K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable( 1CE ), an active HIGH Chip Enable (CE2), and active LOW Output Enable ( OE ).This device has an automatic power-down feature that reduces power consumption dramatically when deselected. Writing to the device is accomplished by taking Chip Enable One ( 1CE ) and Write Enable ( WE )inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O 0 through I/O 15) is then written into the location specified on the address pins (A 0 through A18). Reading from the device is accomplished by asserting the Chip Enable One ( 1CE ) and Output Enable ( OE ) inputs LOW while forcing Write Enable ( WE ) HIGH and Chip Enable Two(CE2) HIGH. Under these co nditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O 0 through I/O 7) are placed in a high-impedance state when the device is deselected 1CE HIGH or CE2 LOW), the outputs are disabled ( OE HIGH), or during write operation ( 1CE LOW, CE2 HIGH, and WE LOW).See the Truth Table for a complete description of read and write modes. Logic Block Diagram

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.1 2/12 Pin Configuration[1] Product Portfolio Power Dissipation Operating, ICC (mA) VCC Range(V) f = 1 MHz f = f MAX Standby, ISB2 (µA) Product Min. Typ. Max. Speed (ns) 14 22 M24L48512DA 2.7 3.0 3.6 1 5 8 15 17 40 Notes: 1. NC “no connect”—not connected internally to the die. 2.Typical values are included for reference only and are no t guaranteed or tested. Typical values are measured at V CC = V CC (typ) and TA = 25°C.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.1 3/12 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Ambient Temperature with DC Voltage Applied to Outputs (per MIL-STD-883, Method 3015) Operating Range Range Ambient Temperature (TA) VCC Extended −25°C to +85°C 2.7V to 3.6V Industrial −40°C to +85°C 2.7V to 3.6V Electrical Characteristics (Over the Operating Range) -55, 60, 70 Parameter Description Test Conditions Min. Typ.[2] Max. Unit VCC Supply Voltage 2.7 3.0 3.6 V VOH Output HIGH Voltage IOH = −0.1 mA V CC – 0.4 V VOL Output LOW Voltage IOL = 0.1 mA 0.4 V VIH Input HIGH Voltage 0.8 * V CC V CC + 0.4 V VIL Input LOW Voltage -0.4 0.4 V IIX Input Leakage Current GND ≤ V IN ≤ Vcc -1 +1 µA IOZ Output Leakage Current GND ≤ V OUT ≤ Vcc, Output Disabled -1 +1 µA f = fMAX = 1/tRC 14 for 55ns speed 14 for 60 ns speed 8 for 70 ns speed 22 for 55 ns speed 22 for 60 ns speed 15 for 70 ns speed ICC VCC Operating Supply Current f = 1 MHz VCC = 3.6V, IOUT = 0 mA, CMOS level 1 for all speed 5 for all speeds mA ISB1 Automatic 1CE Power-down Current —CMOS Inputs 1CE ≥ V CC − 0.2V, CE2 ≤ 0.2V, VIN ≥ V CC − 0.2V, VIN ≤ 0.2V, f = fMAX(Address and Data Only), f = 0 150 250 µA ISB2 Automatic 1CE Power-down Current —CMOS Inputs 1CE ≥ V CC − 0.2V, CE2 ≤ 0.2V, VIN ≥ V CC − 0.2V or VIN 17 40 µA Capacitance[6] Parameter Description Test Conditions Max. Unit CIN Input Capacitance 8 pF COUT Output Capacitance TA = 25°C, f = 1 MHz VCC = VCC(typ) 8 pF Notes: 3.VIH(MAX) = VCC + 0.5V for pulse durations less than 20 ns. 4.VIL(MIN) = –0.5V for pulse durations less than 20 ns. 5.Overshoot and undershoot specifications are characterized and are not 100% tested. 6.Tested initially and after design or process changes that may affect these parameters.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.1 4/12 Thermal Resistance[6] Parameter Description Test Conditions VFBGA Unit θJA Thermal Resistance (Junction to Ambient) 55 °C/W θJC Thermal Resistance (Junction to Case) Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 17 °C/W AC Test Loads and Waveforms Parameters 3.0V V CC Unit R1 22000 Ω R2 22000 Ω RTH 11000 Ω VTH 1.50 V Switching Characteristics (Over the Operating Range)[7] Read Cycle tRC Read Cycle Time 55 [11] 60 70 ns tAA Address to Data Valid 55 60 70 ns tOHA Data Hold from Address Change 5 8 10 ns tACE 1CE LOW and CE2 HIGH to Data Valid 55 60 70 ns tDOE OE LOW to Data Valid 25 25 35 ns tLZOE OE LOW to Low Z[8, 9] 5 5 5 ns tHZOE OE HIGH to High Z[8, 9] 25 25 25 ns tLZCE 1CE LOW and CE2 HIGH to Low Z[8, 2 2 5 ns tHZCE 1CE HIGH and CE2 LOW to High Z[8, 25 25 25 ns tSK [11] Address Skew 0 5 10 ns Write Cycle[10] tWC Write Cycle Time 55 60 70 ns tSCE 1CE LOW and CE2 HIGH to Write End 45 45 60 ns tAW Address Set-up to Write End 45 45 55 ns tHA Address Hold from Write End 0 0 0 ns Notes: 7. Test conditions assume signal transition time of 1 V/ns or higher, timing reference levels of V CC(typ)/2, input pulse levels of 0V to VCC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance. 8. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 9. High-Z and Low-Z parameters are characterized and are not 100% tested. 10.The internal write time of the memory is defined by the overlap of WE , 1CE = V IL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these si gnals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates write. 11.To achieve 55-ns performanc e, the read access should be CE controlled. In this case t ACE is the critical parameter and t SK is satisfied when the addresses are stable prior to chip enable go ing active. For the 70-ns cycl e, the addresses must be stable within 10 ns after the start of the read cycle.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.1 5/12 Switching Characteristics (Over the Operating Range)[7] (continued) tSA Address Set-up to Write Start 0 0 0 ns tPWE WE Pulse Width 40 40 45 ns tSD Data Set-up to Write End 25 25 25 ns tHD Data Hold from Write End 0 0 0 ns tHZWE WE LOW to High Z[8, 9] 25 25 25 ns tLZWE WE HIGH to Low Z[8, 9] 5 5 5 ns Switching Waveforms Read Cycle 1 (Address Transition Controlled) [11, 12, 13] Read Cycle 2 ( OE Controlled) [11, 13] Notes: 12.Device is continuously selected. OE , CE = V IL. 13. WE is HIGH for Read Cycle.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.1 6/12 Switching Waveforms (continued) Write Cycle No. 1( WE Controlled) [9, 10, 14, 15, 16] Switching Waveforms (continued) Write Cycle 2 ( 1CE or CE2 Controlled) [9, 10, 14, 15, 16] Notes: 14.Data I/O is high impedance if OE ≥ V IH. 15.If Chip Enable goes INACTIVE simultaneously with WE =HIGH, the output remains in a high-impedance state. 16.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.1 7/12 Switching Waveforms (continued) Write Cycle 3 ( WE Controlled, OE LOW)[15, 16]

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.1 8/12 Avoid Timing ESMT Pseudo SRAM has a timing which is not supported at read operation, If your system has multiple invalid address signal shorter than tRC during over 15μs at read operation shown as in Abnormal Timing, it requires a normal read timing at leat during 15μs shown as in Avoidable timing 1 or toggle 1CE to high ( ≧tRC) one time at least shown as in Avoidable Timing 2. Abnormal Timing Avoidable Timing 1 Avoidable Timing 2 CE1 15μs≧ WE Address ＜ tRC CE1 15μs≧ WE Address t≧ RC CE1 15μs≧ WE Address ＜ tRC t≧ RC

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.1 9/12 Truth Table[17] 1CE CE2 OE WE I/O0–I/O7 Mode Power H X X X High Z Power-down Standby (I SB) X L X X High Z Power-down Standby (I SB) L H L H Data Out Read Active (I CC) L H X L Data in Write Active (I CC) L H H H High Z Selected, Outputs Disabled Active (I CC)

Ordering Information

Speed (ns) Ordering Code Package Type Operating Range

55 M24L48512DA-55BEG 36-Lead VFBGA (6 x 8 x 1 mm) (pb-free) Extended

60 M24L48512DA -60BEG 36-Lead VFBGA (6 x 8 x 1 mm) (pb-free) Extended

70 M24L48512DA -70BEG 36-Lead VFBGA (6 x 8 x 1 mm) (pb-free) Extended

55 M24L48512DA-55BIG 36-Lead VFBGA (6 x 8 x 1 mm) (pb-free) Industrial

60 M24L48512DA-60BIG 36-Lead VFBGA (6 x 8 x 1 mm) (pb-free) Industrial

70 M24L48512DA-70BIG 36-Lead VFBGA (6 x 8 x 1 mm) (pb-free) Industrial

Note: 17.H = Logic HIGH, L = Logic LOW, X = Don’t Care.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.1 10/12 Package Diagram 36-Lead VFBGA (6 x 8 x 1 mm)

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.1 11/12

Revision History

1.0 2007.07.19 Original 1.1 2008.07.04 1. Move Revision History to the last 3. Add Industrial grade 4. Add Avoid timing

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.1 12/12 Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.