M24L416256DA-70BIG

M24L416256DA ESMT | Alldatasheet

Document overview

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Technical content

Features

• Advanced low-power architecture
• High speed: 55 ns, 60 ns and 70 ns
• Wide voltage range: 2.7V to 3.6V
• Typical active current: 1 mA @ f = 1 MHz
• Low standby power
• Automatic power-down when deselected Functional Description The M24L416256DA is a high-performance CMOS pseudo static RAM (PSRAM) organized as 256K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for portable applications such as cellular telephones. The device can be put into standby mode reducing power consumption dramatically when deselected ( 1CE HIGH, CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O 0 through I/O 15) are placed in a high-impedance state when: deselected ( 1CE HIGH, CE2 LOW, OE is HIGH), or during a write operation (Chip Enabled and Write Enable WE LOW). Reading from the device is accomplished by asserting the Chip Enables ( 1CE LOW and CE2 HIGH) and Output Enable( OE ) LOW while forcing the Write Enable ( WE ) HIGH. If Byte Low Enable ( BLE ) is LOW, then data from the memory location specified by the address pins A0 through A17 will appear on I/O 0 to I/O 7. If Byte High Enable ( BHE ) is LOW, then data from memory will appear on I/O 8 to I/O 15. See the Truth Table for a complete description of read and write modes.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.5 2/15 Pin Configuration[3, 4, 5] 44-pin TSOPII Top View CE1 I/O0 I/O1 I/O2 I/O3 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 V SS VCC I/O11 I/O10 I/O9 I/O8 CE2 A10 A11 A17

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.5 3/15 Product Portfolio Power Dissipation Operating, ICC (mA) VCC Range(V) f = 1 MHz f = f MAX Standby, ISB2 (µA)Product Min. Typ. Max. Speed (ns) 14 22 M24L416256DA 2.7 3.0 3.6 1 5 8 15 17 40 Notes: 2.Typical values are included for reference only and are no t guaranteed or tested. Typical values are measured at V CC = V CC (typ) and TA = 25°C. 3.Ball H1, G2, H6 are the address expansion pins for the 8-Mb, 16-Mb, and 32-Mb densities, respectively. 4.NC “no connect”—not connected internally to the die. 5.DNU (Do Not Use) pins have to be left floating or tied to VSS to ensure proper application.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.5 4/15 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Ambient Temperature with DC Voltage Applied to Outputs (per MIL-STD-883, Method 3015) Operating Range Range Ambient Temperature (TA) VCC Extended −25°C to +85°C 2.7V to 3.6V Industrial −40°C to +85°C 2.7V to 3.6V -55, 60, 70 Parameter Description Test Conditions Min. Typ.[2] Max. Unit VCC Supply Voltage 2.7 3.0 3.6 V VOH Output HIGH Voltage IOH = −0.1 mA V CC – 0.4 V VOL Output LOW Voltage IOL = 0.1 mA 0.4 V VIH Input HIGH Voltage 0.8 * V CC V CC + 0.4 V VIL Input LOW Voltage F = 0 -0.4 0.62 V IIX Input Leakage Current GND ≤ V IN ≤ Vcc -1 +1 µA IOZ Output Leakage Current GND ≤ V OUT ≤ Vcc, Output Disabled -1 +1 µA f = fMAX = 1/tRC 14 for –55 14 for –60 08 for –70 22 for –55 22 for –60 15 for –70 ICC VCC Operating Supply Current f = 1 MHz VCC = 3.6V, IOUT = 0 mA, CMOS level 1 for all speeds 5 for all speeds mA ISB1 Automatic 1CE Power-down Current —CMOS Inputs 1CE ≥ V CC − 0.2V, CE2 ≤ 0.2V, VIN ≥ V CC − 0.2V, VIN ≤ 0.2V, f = fMAX(Address and Data Only),f = 0 ( OE , WE , BHE and BLE ) 150 250 µA ISB2 Automatic 1CE Power-down Current —CMOS Inputs 1CE ≥ V CC − 0.2V, CE2 ≤ 0.2V, VIN ≥ V CC − 0.2V or VIN 17 40 µA Capacitance[9] Parameter Description Test Conditions Max. Unit CIN Input Capacitance 8 pF COUT Output Capacitance TA = 25°C, f = 1 MHz VCC = VCC(typ) 8 pF Thermal Resistance[9] Parameter Description Test Conditions VFBGA Unit θJA Thermal Resistance (Junction to Ambient) 55 °C/W θJC Thermal Resistance (Junction to Case) Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 17 °C/W Notes: 6.VIH(MAX) = VCC + 0.5V for pulse durations less than 20 ns. 7.VIL(MIN) = –0.5V for pulse durations less than 20 ns. 8.Overshoot and undershoot specifications are characterized and are not 100% tested. 9.Tested initially and after design or process changes that may affect these parameters.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.5 5/15 AC Test Loads and Waveforms Parameters 3.0V V CC Unit R1 22000 Ω R2 22000 Ω RTH 11000 Ω VTH 1.50 V Switching Characteristics (Over the Operating Range)[10] Read Cycle tRC Read Cycle Time 55 [14] 60 70 ns tAA Address to Data Valid 55 60 70 ns tOHA Data Hold from Address Change 5 8 10 ns tACE 1CE LOW and CE2 HIGH to Data Valid 55 60 70 ns tDOE OE LOW to Data Valid 25 25 35 ns tLZOE OE LOW to Low Z[11, 12] 5 5 5 ns tHZOE OE HIGH to High Z[11, 12] 25 25 25 ns tLZCE 1CE LOW and CE2 HIGH to Low Z[11, 12] 5 5 5 ns tHZCE 1CE HIGH and CE2 LOW to High Z[11, 12] 25 25 25 ns tDBE BLE / BHE LOW to Data Valid 55 60 70 ns tLZBE BLE / BHE LOW to Low Z[11, 12] 5 5 5 ns tHZBE BLE / BHE HIGH to High-Z[11, 12] 10 10 25 ns tSK [14] Address Skew 0 5 10 ns Write Cycle[13] tWC Write Cycle Time 55 60 70 ns tSCE 1CE LOW and CE2 HIGH to Write End 45 45 60 ns tAW Address Set-up to Write End 45 45 55 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-up to Write Start 0 0 0 ns Notes: 10. Test conditions assume signal transition time of 1 V/ns or higher, timing reference levels of V CC(typ)/2, input pulse levels of 0V to VCC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance. 11. t HZOE, tHZCE, tHZBE and tHZWE transitions are measured when the outputs enter a high-impedance state. 12. High-Z and Low-Z parameters are char acterized and are not 100% tested. 13. The internal write time of the memory is defined by the overlap of WE , 1CE = V IL, CE2 = V IH, BHE and/or BLE =V IL. All signals must be ACTIVE to initiate a wr ite and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates write. 14. To achieve 55-ns performance, the read access should be CE controlled. In this case t ACE is the critical parameter and t SK is satisfied when the addresses are stable prior to chip enable goi ng active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.5 6/15 Switching Characteristics (Over the Operating Range)[10] (continued) tPWE WE Pulse Width 40 40 45 ns tBW BLE / BHE LOW to Write End 50 50 55 ns tSD Data Set-up to Write End 25 25 25 ns tHD Data Hold from Write End 0 0 0 ns tHZWE WE LOW to High Z[11, 12] 25 25 25 ns tLZWE WE HIGH to Low Z[11, 12] 5 5 5 ns Switching Waveforms Read Cycle 1 (Address Transition Controlled)[14, 15, 16] Read Cycle 2 ( OE Controlled)[14, 16] Notes: 15.Device is continuously selected. OE , CE = V IL. 16. WE is HIGH for Read Cycle.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.5 7/15 Switching Waveforms (continued) Write Cycle No. 1( WE Controlled)[12, 13, 17, 18, 19] Notes: 17.Data I/O is high impedance if OE > V IH. 18.If Chip Enable goes INACTIVE simultaneously with WE =HIGH, the output remains in a high-impedance state. 19.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.5 8/15 Switching Waveforms (continued) Write Cycle 2 ( 1CE or CE2 Controlled)[12, 13, 17, 18, 19] Write Cycle 3 ( WE Controlled, OE LOW)[18, 19]

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.5 9/15 Switching Waveforms (continued) Write Cycle No. 4 (BHE /BLE Controlled, OE LOW)[18, 19]

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.5 10/15 Avoid Timing ESMT Pseudo SRAM has a timing which is not supported at read operation, If your system has multiple invalid address signal shorter than tRC during over 15μs at read operation shown as in Abnormal Timing, it requires a normal read timing at leat during 15μs shown as in Avoidable timing 1 or toggle 1CE to high ( ≧tRC) one time at least shown as in Avoidable Timing 2. Abnormal Timing Avoidable Timing 1 Avoidable Timing 2 CE1 15μs≧ WE Address ＜ tRC CE1 15μs≧ WE Address t≧ RC CE1 15μs≧ WE Address ＜ tRC t≧ RC

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.5 11/15 Truth Table[20] 1CE CE2 WE OE BHE BLE Inputs/Outputs Mode Power H X X X X X High Z Deselect/Power-down Standby (I SB) X L X X X X High Z Deselect/Power-down Standby (I SB) X X X X H H High Z Deselect/Power-down Standby (I SB) L H H L L L Data Out (I/O 0–I/O15) Read (Upper Byte and Lower Byte) Active (I CC) L H H L H L Data Out (I/O0–I/O7); I/O8–I/O15 in High Z Read (Upper Byte only) Active (I CC) L H H L L H Data Out (I/O8–I/O15); I/O0–I/O7 in High Z Read (Lower Byte only) Active (I CC) L H H H L L High Z Output Disabled Active (I CC) L H H H H L High Z Output Disabled Active (I CC) L H H H L H High Z Output Disabled Active (I CC) L H L X L L Data In (I/O 0–I/O15) Write (Upper Byte and Lower Byte) Active (I CC) L H L X H L Data In (I/O0–I/O7); I/O8–I/O15 in High Z Write (Lower Byte Only) Active (I CC) L H L X L H Data In (I/O8–I/O15); I/O0–I/O7 in High Z Write (Upper Byte Only) Active (I CC) Note: 20.H = Logic HIGH, L = Logic LOW, X = Don’t Care.

Ordering Information

Speed (ns) Ordering Code Package Type Operating Range 55 M24L416256DA-55BEG 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) Extended 60 M24L416256DA-60BEG 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) Extended 70 M24L416256DA-70BEG 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) Extended

55 M24L416256DA-55TEG 44-pin TSOPII (Pb-Free) Extended

60 M24L416256DA-60TEG 44-pin TSOPII (Pb-Free) Extended

70 M24L416256DA-70TEG 44-pin TSOPII (Pb-Free) Extended

55 M24L416256DA-55BIG 48-ball Very Fine Pitch BG A (6.0 x 8.0 x 1.0 mm) (Pb-Free) Industrial 60 M24L416256DA-60BIG 48-ball Very Fine Pitch BG A (6.0 x 8.0 x 1.0 mm) (Pb-Free) Industrial 70 M24L416256DA-70BIG 48-ball Very Fine Pitch BG A (6.0 x 8.0 x 1.0 mm) (Pb-Free) Industrial

55 M24L416256DA-55TIG 44-pin TS OPII (Pb-Free) Industrial

60 M24L416256DA-60TIG 44-pin TS OPII (Pb-Free) Industrial

70 M24L416256DA-70TIG 44-pin TS OPII (Pb-Free) Industrial

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.5 12/15 Package Diagram 48-ball VFBGA (6 x 8 x 1 mm)

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.5 13/15 44-LEAD TSOP(II) PSRAM(400mil) Symbol Dimension in mm Dimension in inch Min Norm Max Min Norm Max A 1.20 0.047 A1 0.05 0.15 0.002 0.006 B 0.30 0.45 0.012 0.018 C 0.12 0.21 0.005 0.008 C1 0.10 0.16 0.004 0.006 ZD 0.805 REF 0.0317 REF L1 0.80 REF 0.031 REF e 0.80 BSC 0.0315 BSC θ °0 °8 °0

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.5 14/15

Revision History

1.0 2007.07.04 Original 1.1 2007.11.20 Modify the descriptive error for standby mode, tHZWE and tLZWE

description

1.2 2007.11.22 Modify tHZBE and tLZBE descriptive and restore tHZWE and tLZWE 1.3 2008.02.27 1.Add 44-pin TSOPII package 2. Add Avoid timing 1.4 2008.03.24 Add I-grade for TSOPII package 1.5 2008.07.04 1. Move Revision History to the last 3. Add Industrial grade for BGA package

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008 R e v i s i o n : 1.5 15/15 Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.