M24L216128SA-70TEG

M24L216128SA ESMT | Alldatasheet

Document overview

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Technical content

Features

• Wide voltage range: 2.7V–3.6V
• Access Time: 55 ns, 70 ns
• Ultra-low active power — Typical active current: 1mA @ f = 1 MHz — Typical active current: 14 mA @ f = fmax (For 55-ns) —Typical active current: 8 mA @ f = fmax (For 70-ns)
• Ultra low standby power
• Automatic power-down when deselected
• CMOS for optimum speed/power Functional Description The M24L216128SA is a high-performance CMOS Pseudo Static RAM organized as 128K words by 16 bits that supports an asynchronous memory interf ace. This device features advanced circuit design to provide ultra-low active current. This is ideal for portable applications such as cellular telephones. The device can be put into standby mode when deselected ( CE HIGH or both BHE and BLE are HIGH). The input/output pins (I/O 0 through I/O 15) are placed in a high-impedance state when the chip is deselected ( CE HIGH), or when the outputs are disabled ( OE HIGH), or when both Byte High Enable and Byte Low Enable are disabled ( BHE , BLE HIGH), or during a write operation ( CE LOW and WE LOW). Writing to the device is accomplished by asserting Chip Enable ( CE LOW) and Write Enable ( WE ) input LOW. If Byte Low Enable (BLE ) is LOW, then data from I/O pins (I/O0 through I/O 7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable ( BHE ) is LOW, then data from I/O pins (I/O 8 through I/O 15) is written into the location specified on the address pins (A 0 through A16). Reading from the device is accomplished by asserting Chip Enable ( CE LOW) and Output Enable ( OE ) LOW while forcing the Write Enable ( WE ) HIGH. If Byte Low Enable ( BLE ) is LOW, then data from the memory location specified by the address pins will appear on I/O 0 to I/O 7. If Byte High Enable( BHE ) is LOW, then data from memory will appear on I/O8 to I/O15. Refer to the truth table for a complete description of read and write modes. Logic Block Diagram

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2008 Revision : 1.2 2/14 Pin Configuration[2, 3, 4] 48-ball VFBGA Top View 44-pin TSOPII Top View CE I/O0 I/O1 I/O2 I/O3 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 V SS VCC I/O11 I/O10 I/O9 I/O8 NC A10 A11 NC

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2008 Revision : 1.2 3/14 Product Portfolio Product Power Dissipation Operating ICC(mA) VCC Range (V) f = 1MHz f = fmax Standby ISB2(µA) Product Min. Typ. Max. Speed(ns) 55 14 22 M24L216128SA 2.7 3.0 3.6 1 5 8 15 9 40 Notes: 2.Ball D3, H1, G2 and ball H6 for the FBGA package can be used to upgrade to a 4-Mbit, 8-Mbit, 16-Mbit and a 32-Mbit density, respectively. 3.NC “no connect”—not connected internally to the die. 4.DNU (Do Not Use) pins have to be left floating or tied to Vss to ensure proper application. 5.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2008 Revision : 1.2 4/14 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Ambient Temperature with DC Voltage Applied to Outputs (per MIL-STD-883, Method 3015) Operating Range Range Ambient Temperature(TA) VCC Extended −25°C to +85°C 2.7V to 3.6V Industrial −40°C to +85°C 2.7V to 3.6V Electrical Characteristics (Over the Operating Range) -55 -70 Parameter Description Test Conditions Min. Typ .[5] Max. Min. Typ. [5] Max. Unit VOH Output HIGH Voltage IOH = −0.1 mA V CC = 2.70V VCC-

0.4 VCC-

0.4 V VOL Output LOW Voltage IOL = 0.1 mA V CC = 2.70V 0.4 0.4 V VIH Input HIGH Voltage VCC = 2.7V to 3.6V 0.8* VCC VCC+ 0.4V 0.8* VCC VCC+ 0.4V V VIL Input LOW Voltage -0.4 0.4 -0.4 0.4 V IIX Input Leakage Current GND ≤VIN ≤ V CC -1 +1 -1 +1 µA IOZ Output Leakage Current GND ≤ V OUT ≤ V CC, Output Disabled -1 +1 -1 +1 µA f = fMAX = 1/tRC 14 22 8 15 mA ICC VCC Operating Supply Current f = 1 MHz VCC = VCCmax IOUT = 0mA CMOS levels 1 5 1 5 mA ISB1 Automatic CE Power-Down Current —CMOS Inputs CE ≥VCC − 0.2V VIN ≥VCC − 0.2V, VIN ≤ 0.2V, f = fMAX (Address and Data Only), f = 0 ( OE , WE , BHE and BLE ), VCC=3.6V 40 250 40 250 µA ISB2 Automatic CE Power-Down Current —CMOS Inputs CE ≥VCC−0.2V VIN ≥ V CC − 0.2V or VIN ≤ 0.2V, f = 0, VCC =3.6V 9 40 9 40 µA Capacitance[9] Parameter Description Test Conditions Max. Unit CIN Input Capacitance 8 pF COUT Output Capacitance TA = 25°C, f = 1 MHz VCC = VCC(typ) 8 pF Thermal Resistance[9] Parameter Description Test Conditions BGA Unit ΘJA Thermal Resistance(Junction to Ambient) Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/ JESD51. 55 °C/W ΘJC Thermal Resistance (Junction to Case) 17 °C/W Notes: 6.VIL(MIN) = –0.5V for pulse durations less than 20 ns. 7.VIH(Max) = VCC + 0.5V for pulse durations less than 20 ns. 8.Overshoot and undershoot specifications are characterized and are not 100% tested. 9.Tested initially and after any design or process changes that may affect these parameters.

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2008 Revision : 1.2 5/14 AC Test Loads and Waveforms Parameters 3.0V V CC Unit R1 22000 Ω R2 22000 Ω RTH 11000 Ω VTH 1.50 V Switching Characteristics Over the Operating Range[10] -55 [14] -70 Parameter Description Min. Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 55[14] 70 ns tAA Address to Data Valid 55 70 ns tOHA Data Hold from Address Change 5 10 ns tACE CE LOW to Data Valid 55 70 ns tDOE OE LOW to Data Valid 25 35 ns tLZOE OE LOW to LOW Z[11, 13] 5 5 ns tHZOE OE HIGH to High Z[11, 13] 25 25 ns tLZCE CE LOW to Low Z[11, 13] 2 5 ns tHZCE CE HIGH to High Z[11, 13] 25 25 ns tDBE BLE / BHE LOW to Data Valid 55 70 ns tLZBE BLE / BHE LOW to Low Z[11, 13] 5 5 ns tHZBE BLE / BHE HIGH to HIGH Z[11, 13] 10 25 ns tSK[14] Address Skew 0 10 ns Write Cycle[12] tWC Write Cycle Time 55 70 ns tSCE CE LOW to Write End 45 60 ns tAW Address Set-Up to Write End 45 60 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 40 45 ns Notes: 10. Test conditions for all parameters other than tri-state para meters assume signal transition time of 1 ns/V, timing referenc e levels of VCC(typ)/2, input pulse levels of 0V to V CC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 11. t HZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs ente r a high impedance state.12.The internal Write time of the memory is defined by the overlap of WE , CE = V IL, BHE and/or BLE = V IL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a writ e by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 13. High-Z and Low-Z parameters are characterized and are not 100% tested. 14. To achieve 55-ns performance, the read access should be CE controlled. In this case t ACE is the critical parameter and tSK is satisfied when the addresses are stable prior to chip enab le going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle.

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2008 Revision : 1.2 6/14 Switching Characteristics Over the Operating Range (continued)[10] -55 [14] -70 Unit Parameter Description Min. Max. Min. Max. tBW BLE/BHE LOW to Write End 50 60 ns tSD Data Set-Up to Write End 25 45 ns tHD Data Hold from Write End 0 0 ns tHZWE WE LOW to High-Z[11, 13] 25 25 ns tLZWE WE HIGH to Low-Z[11, 13] 5 5 ns Switching Waveforms Read Cycle 1 (Address Transition Controlled)[15, 16, 17] Read Cycle 2 ( OE Controlled)[16, 17] Notes: 15. Device is continuously selected. OE , CE = V IL. 16. WE is HIGH for Read Cycle. 17. For the 55-ns Cycle, the addresses must not toggle once the read is started on the device. For the 70-ns Cycle, the addresses must be stable within 10 ns after the start of the read cycle.

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2008 Revision : 1.2 7/14 Switching Waveforms (continued) Write Cycle 1 ( WE Controlled)[12, 13, 18, 19, 20] Write Cycle 2 (CE Controlled)[12, 13, 18, 19, 20] Notes: 18.Data I/O is high impedance if OE ≥ V IH. 19.If Chip Enable goes INACTIVE with WE = V IH, the output remains in a high-impedance state. 20.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2008 Revision : 1.2 8/14 Switching Waveforms (continued) Write Cycle 3 ( WE Controlled, OE LOW)[19, 20] Write Cycle 4 (BHE /BLE Controlled, OE LOW)[19, 20]

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2008 Revision : 1.2 9/14 Avoid Timing ESMT Pseudo SRAM has a timing which is not supported at read operation, If your system has multiple invalid address signal shorter than tRC during over 15μs at read operation shown as in Abnormal Timing, it requires a normal read timing at leat during 15μs shown as in Avoidable timing 1 or toggle CE to high ( ≧tRC) one time at least shown as in Avoidable Timing 2. Abnormal Timing Avoidable Timing 1 Avoidable Timing 2 CE ≧15μ s WE Address ＜ tRC CE ≧15μ s WE Address t≧ RC CE ≧15μ s WE Address ＜ tRC t≧ RC

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2008 Revision : 1.2 10/14 Truth Table[21] CE WE OE BHE BLE Inputs/Outputs Mode Power H X X X X High Z Deselect/Power-Down Standby (I SB) X X X H H High Z Deselect/Power-Down Standby (I SB) L H L L L Data Out (I/O 0–I/O15) Read Active (I CC) L H L H L Data Out (I/O0–I/O7); High Z (I/O8–I/O15) Read Active (I CC) L H L L H High Z (I/O0–I/O7); Data Out (I/O8–I/O15) Read Active (ICC) L H H L H High Z Output Disabled Active (ICC) L H H H L High Z Output Disabled Active (ICC) L H H L L High Z Output Disabled Active (ICC) L L X L L Data In (I/O 0–I/O15) Write Active (ICC) L L X H L Data In (I/O0–I/O7); High Z (I/O8–I/O15) Write Active (ICC) L L X L H High Z (I/O0–I/O7); Data In (I/O8–I/O15) Write Active (ICC) Note: 21.H = Logic HIGH, L = Logic LOW, X = Don’t Care.

Ordering information

Speed(ns) Ordering Code Package Type Operating Range 55 M24L216128SA-55 BEG 48-ball Very Fine Pitch BGA (6 .0x8.0x1.0mm) (Pb-free) Extended 70 M24L216128SA-70 BEG 48-ball Very Fine Pitch BGA (6 .0x8.0x1.0mm) (Pb-free) Extended

55 M24L216128SA-55TEG 44-pin TSOPII (Pb-free) Extended

70 M24L216128SA-70TEG 44-pin TSOPII (Pb-free) Extended

55 M24L216128SA-55BIG 48-ball Very Fine Pitch BGA (6.0x8.0x1.0mm) (Pb-free) Industrial 70 M24L216128SA-70BIG 48-ball Very Fine Pitch BGA (6.0x8.0x1.0mm) (Pb-free) Industrial

55 M24L216128SA-55TIG 44-pin TSOPII (Pb-free) Industrial

70 M24L216128SA-70TIG 44-pin TSOPII (Pb-free) Industrial

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2008 Revision : 1.2 11/14 Package Diagram

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2008 Revision : 1.2 12/14 44-LEAD TSOP(II) PRAM(400mil) Symbol Dimension in mm Dimension in inch Min Norm Max Min Norm Max A 1.20 0.047 A1 0.05 0.15 0.002 0.006 B 0.30 0.45 0.012 0.018 C 0.12 0.21 0.005 0.008 C1 0.10 0.16 0.004 0.006 ZD 0.805 REF 0.0317 REF L1 0.80 REF 0.031 REF e 0.80 BSC 0.0315 BSC θ °0 °8 °0 °8

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2008 Revision : 1.2 13/14

Revision History

1.0 2007.05.11 Original 1.1 2008.02.29 1. Add 44-pin TSOPII package 2. Add Avoid timing 1.2 2008.07.04 1. Move Revision History to the last 3. Add Industrial grade

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2008 Revision : 1.2 14/14 Important Notice All rights reserved. No part of this document may be rep roduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the produ cts or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patent s, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inher ently a certain rate of failure. To minimize risks associated with cust omer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support device s or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its ow n quality assurance testing appropriate to such applications.