M24L16161DA ESMT | Alldatasheet

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Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2007 Revision : 1.0 1/12 Revision History : Revision 1.0 (Jul. 4, 2007) - Original

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2007 Revision : 1.0 2/12 PSRAM 16-Mbit (1M x 16) Pseudo Static RAM

Features

  • Wide voltage range: 2.2V–3.6V
  • Access Time: 70 ns
  • Ultra-low active power — Typical active current: 3 mA @ f = 1 MHz — Typical active current: 18 mA @ f = fmax
  • Ultra low standby power
  • Automatic power-down when deselected
  • CMOS for optimum speed/power ‧Offered in a 48-ball BGA Package
  • Operating Temperature: –40°C to +85°C Functional Description[1] The M24L16161DA is a high-performance CMOS Pseudo Static RAM organized as 1M words by 16 bits that supports an asynchronous memory interf ace. This device features advanced circuit design to provide ultra-low active current. This is ideal for portable applications such as cellular telephones. The device can be put into standby mode when deselected ( 1CE HIGH or CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O 0 through I/O 15) are placed in a high-impedance state when: deselected ( 1CE HIGH or CE2 LOW), outputs are disabled ( OE HIGH), both Byte High Enable and Byte Low Enable are disabled ( BHE , BLE HIGH), or during a write operation ( 1CE LOW and CE2 HIGH and WE LOW). To write to the device, take Chip Enable ( 1CE LOW and CE2 HIGH) and Write Enable ( WE ) input LOW. If Byte Low Enable( BLE ) is LOW, then data from I/O pins (I/O 0 through I/O7), is written into the location specified on the address pins (A0 through A 19). If Byte High Enable ( BHE ) is LOW, then data from I/O pins (I/O 8 through I/O 15) is written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enables ( 1CE LOW and CE2 HIGH) and Output Enable ( OE ) LOW while forcing the Write Enable ( WE ) HIGH. If Byte Low Enable (BLE ) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable ( BHE ) is LOW, then data from memory will appear on I/O 8 to I/O15.Refer to the truth table for a complete description of read and write modes. Logic Block Diagram

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2007 Revision : 1.0 3/12 Pin Configuration[2, 3] 48-ball VFBGA Top View Product Portfolio[4] Power Dissipation Operating ICC(mA) VCC Range (V) Speed(ns) f = 1MHz f = fmax Standby ISB2(µA) Product M24L16161DA 2.2 3.0 3.6 70 3 5 18 25 55 70 Power-up Characteristics The initialization sequence is shown in the figure below. Chip Select should be 1OE HIGH or CE2 LOW for at least 200 µs after V CC has reached a stable value. No access must be attempted during this period of 200 µs. Parameter Description Min. Typ. Max. Unit TPU Chip Enable Low After Stable V CC 200 µs Notes: 2.Ball H6 and E3 can be used to upgrade to a 32-Mbit and a 64-Mbit density, respectively. 3.NC “no connect”-not connected internally to the die. 4.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V CC = VCC (typ) and TA = 25°C. Tested initially and after design changes that may affect the parameters.

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2007 Revision : 1.0 4/12 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Ambient Temperature with Supply Voltage to Ground Potential.–0.3V to V CCMAX + 0.3V DC Voltage Applied to Outputs (per MIL-STD-883, Method 3015) Operating Range Range Ambient Temperature (TA) VCC Industrial −40°C to +85°C 2.2V to 3.6V -70 Parameter Description Test Conditions Min. Typ.[4] Max. Unit VCC Supply Voltage 2.2 3.0 3.6 V VOH Output HIGH Voltage IOH = −0.1 mA VCC = 2.2V to 3.6V VCC-0.2 V VOL Output LOW Voltage I OL = 0.1 mA, VCC = 2.2V to 3.6 0.2 V VIH Input HIGH Voltage VCC = 1.7V to 1.95V 0.8* V CC V CC+0.3V V VIL Input LOW Voltage 2.2V to 3.6 -0.3 0.2* V CC V IIX Input Leakage Current GND ≤VIN ≤ V CC -1 +1 µA IOZ Output Leakage Current GND ≤ V OUT ≤ V CC -1 +1 µA f = fMAX = 1/tRC VCC= VCCmax IOUT = 0mA CMOS levels 18 25 mA ICC VCC Operating Supply Current f = 1 MHz 3 5 mA ISB1 Automatic CE Power-Down Current —CMOS Inputs 1CE ≥ V CC − 0.2V, CE2 ≤ 0.2V, V IN > VCC − 0.2V, VIN < 0.2V, f = f MAX (Address and Data Only), f = 0 ( OE , WE , BHE and BLE ), VCC=3.60V 55 70 µA ISB2 Automatic CE Power-Down Current —CMOS Inputs 1CE ≥ VCC−0.2V, CE2 ≤ 0.2V, V IN ≥ VCC − 0.2V or V IN ≤ 0.2V, f = 0, V CC = VCCMAX, 55 70 µA Capacitance[8] Parameter Description Test Conditions Max. Unit CIN Input Capacitance 8 pF COUT Output Capacitance TA = 25°C, f = 1 MHz, VCC = VCC(typ) 8 pF Thermal Resistance[8] Parameter Description Test Conditions VFBGA Unit ΘJA Thermal Resistance (Junction to Ambient) 56 °C/W ΘJC Thermal Resistance (Junction to Case) Test conditions follow standard test methods and procedures for measuring thermal impedence, per EIA/JESD51. 11 °C/W Notes: 5. V IL(MIN) = –0.5V for pulse durations less than 20 ns. 6.VIH(Max) = VCC + 0.5V for pulse durations less than 20 ns. 7.Overshoot and undershoot specifications are characterized and are not 100% tested. 8.Tested initially and after any design or process changes that may affect these parameters.

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2007 Revision : 1.0 5/12 AC Test Loads and Waveforms Parameters 3.0V V CC Unit R1 26000 Ω R2 26000 Ω RTH 13000 Ω VTH 1.50 V Switching Characteristics Over the Operating Range[9, 10, 11, 14, 15] -70 Parameter Description Min. Max. Unit Read Cycle tRC[13] Read Cycle Time 70 40000 ns tCD Chip Deselect Time 1CE =HIGH or CE2=LOW, BLE / BHE High Pulse Time ns tAA Address to Data Valid 70 ns tOHA Data Hold from Address Change 5 ns tACE CE LOW to Data Valid 70 ns tDOE OE LOW to Data Valid 35 ns tLZOE OE LOW to Low Z[10, 11, 12] 5 ns tHZOE OE HIGH to High Z[10, 11, 12] 25 ns tLZCE CE LOW to Low Z[10, 11, 12] 10 ns tHZCE CE HIGH to High Z[10, 11, 12] 25 ns tDBE BLE / BHE LOW to Data Valid 70 ns tLZBE BLE / BHE LOW to Low Z[10, 11, 12] 5 ns tHZBE BLE / BHE HIGH to High Z[10, 11, 12] 25 ns Notes: 9. Test conditions for all parameters other than tri-state parame ters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ.)/2, input pulse levels of 0V to VCC, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 10. At any given temperature and voltage conditions t HZCE is less than t LZCE, tHZBE is less than t LZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. All low-Z parameters will be measured with a load capacitance of 30 pF (3V). 11. t HZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 12. High-Z and Low-Z parameters are characterized and are not 100% tested. 13 .If invalid address sig nals shorter than min. t RC are continuously repeated for 40 µs, the device needs a normal read timing (tRC) or needs to enter standby state at least once in every 40 µs. 14. In order to achieve 70-ns performance, the read access must be Chip Enable ( 1CE or CE2) controlled. That is, the addresses must be stable prior to Chip Enable going active.

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2007 Revision : 1.0 6/12 Switching Characteristics Over the Operating Range[9, 10, 11, 15, 14] (continued) -70 Parameter Description Min. Max. Unit Write Cycle[15] tWC Write Cycle Time 70 40000 ns tSCE CE LOW to Write End 60 ns tAW Address Set-Up to Write End 60 ns tCD Chip Deselect Time 1CE = HIGH or CE2 = LOW, BLE / BHE High Pulse Time ns tHA Address Hold from Write End 0 ns tSA Address Set-Up to Write Start 0 ns tPWE WE Pulse Width 50 ns tBW BLE / BHE LOW to Write End 60 ns tSD Data Set-Up to Write End 25 ns tHD Data Hold from Write End 0 ns tHZWE WE LOW to High-Z[10, 11, 12] 25 ns tLZWE WE HIGH to Low-Z[10, 11, 12] 10 ns Note: 15. The internal Write time of the memory is defined by the overlap of WE , 1CE = V IL or CE2 = VIH, BHE and/or BLE = V IL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2007 Revision : 1.0 7/12 Switching Wave forms Read Cycle 1 (Address Transition Controlled)[17, 18] Read Cycle 2 ( OE Controlled)[16, 18,19] Notes: 16.Whenever 1CE = HIGH or CE2 = LOW, BHE / BLE are taken inactive, they must remain inactive for a minimum of 5 ns. 17.Device is continuously selected. OE = 1CE = V IL and CE2 = VIH. 18. WE is HIGH for Read Cycle. 19. CE is the Logical AND of 1CE and CE2.

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2007 Revision : 1.0 8/12 Switching Waveforms (continued) Write Cycle 1 ( WE Controlled)[15, 12, 16, 19, 20, 21] Notes: 20.Data I/O is high-impedance if OE ≥ V IH. 21.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2007 Revision : 1.0 9/12 Switching Waveforms (continued) Write Cycle 2 ( 1CE or CE2 Controlled)[15, 12, 16, 20, 21] Write Cycle 3 ( WE Controlled, OE LOW)[16, 21]

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2007 Revision : 1.0 10/12 Switching Waveforms (continued) Write Cycle 4 (BHE /BLE Controlled, OE LOW)[15, 16, 20, 21] Truth Table[22] 1CE CE2 WE OE BHE BLE Inputs/Outputs Mode Power H X X X X X High Z Deselect/Power-Down Standby (I SB) X L X X X X High Z Deselect/Power-Down Standby (I SB) X X X X H H High Z Deselect/Power-Down Standby (I SB) L H H L L L Data Out (I/O 0–I/O15) Read Active (ICC) L H H L H L Data Out (I/O 0–I/O7); (I/O8–I/O15) in High Z Read Active (ICC) L H H L L H Data Out (I/O 8–I/O15); (I/O0–I/O7) in High Z Read Active (ICC) L H H H L L High Z Output Disabled Active (ICC) L H H H H L High Z Output Disabled Active (ICC) L H H H L H High Z Output Disabled Active (ICC) L H L X L L Data In (I/O 0–I/O15) Write (Upper Byte and Lower Byte) Active (ICC) L H L X H L Data In (I/O0–I/O7); (I/O8–I/O15) in High Z Write (Lower Byte Only) Active (ICC) L H L X L H Data Out (I/O8–I/O15); (I/O0–I/O7) in High Z Write (Upper Byte Only) Active (ICC) Notes: 22.H = Logic HIGH, L = Logic LOW, X = Don’t Care.

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2007 Revision : 1.0 11/12

Ordering Information

Speed (ns) Ordering Code Package Type Operating Range

70 M24L16161DA -70BIG 48-ball Very Fine Pitch BGA (6 x 8 x 1 mm) (Pb-Free) Industrial

48-ball VFBGA (6 x 8 x 1 mm)

Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Jul. 2007 Revision : 1.0 12/12 Important Notice All rights reserved. No part of this document may be rep roduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the produ cts or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patent s, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inher ently a certain rate of failure. To minimize risks associated with cust omer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support device s or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its ow n quality assurance testing appropriate to such applications.