M24C01-R

M24C04-FMC5TG STMICROELECTRONICS | Alldatasheet

Document overview

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• PDF pages: 38

Technical content

Datasheet sections

• 1 Description
• 2 Signal description
• 2.1 Serial Clock (SCL)
• 2.2 Serial Data (SDA)
• 2.3 Chip Enable (E0, E1, E2)
• 2.3.1 Write Control (WC)
• 2.4 Supply voltage (V CC)
• 2.4.1 Operating supply voltage V CC
• 2.4.2 Power-up conditions
• 2.4.3 Device reset
• 2.4.4 Power-down conditions
• 3 Device operation
• 3.1 Start condition
• 3.2 Stop condition
• 3.3 Acknowledge bit (ACK)
• 3.4 Data input
• 3.5 Memory addressing
• 3.6 Write operations
• 3.6.1 Byte Write
• 3.6.2 Page Write
• 3.6.3 Minimizing system delays by polling on ACK
• 3.7 Read operations
• 3.7.1 Random Address Read
• 3.7.2 Current Address Read
• 3.7.3 Sequential Read
• 3.7.4 Acknowledge in Read mode
• 4 Initial delivery state
• 5 Maximum rating
• 6 DC and AC parameters

Features

■ Supports both the 100 kHz I2C Standard-mode and the 400 kHz I2C Fast-mode ■ Single supply voltage: – 2.5 V to 5.5 V for M24Cxx-W – 1.8 V to 5.5 V for M24Cxx – 1.7 V to 5.5 V for M24Cxx-F ■ Write Control input ■ Byte and Page Write (up to 16 bytes) ■ Random and Sequential Read modes ■ Self-timed programming cycle ■ Automatic address incrementing ■ Enhanced ESD/latch-up protection ■ More than 1 million write cycles ■ More than 40-year data retention ■ Packages: – SO8, TSSOP8, UFDFPN8: ECOPACK2 (RoHS-compliant and Halogen-free) – PDIP8: ECOPACK1 ® (RoHS-compliant) 1. Only M24C08-F and M24C16-F devices are offered in the WLCSP package. 2. Only M24C08-F devices are offered in the Thin WLCSP package. Table 1. Device summary

M24C16, M24C08, M24C04, M24C02, M24C01 Contents Doc ID 5067 Rev 17 3/38

Table 15. AC characteristics at 400 kHz (I Table 16. AC characteristics at 100 kHz (I 2C Standard-mode) (M24Cxx-W, Table 20. SO8 narrow – 8 lead plastic small outline, 150 mils body width, Table 21. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead

1 Description

Figure 1. Logic diagram bit (RW) (as described in Table 3), terminated by an acknowledge bit. terminated by a Stop condition after an Ack for Write, and after a NoAck for Read. Table 2. Signal names

2 Signal description

2.1 Serial Clock (SCL)

2.2 Serial Data (SDA)

the value of the pull-up resistor can be calculated).

2.3 Chip Enable (E0, E1, E2)

Figure 4. Device select code

2.3.1 Write Control (WC )

Write operations are allowed. acknowledged, data bytes are not acknowledged.

2.4 Supply voltage (V CC)

2.4.1 Operating supply voltage V CC

2.4.2 Power-up conditions

defined in Table 6, Table 7 and Table 8 and the rise time must not vary faster than 1 V/µs.

2.4.3 Device reset

voltage within the specified [VCC(min), VCC(max)] range.

2.4.4 Power-down conditions

Figure 5. Maximum R P value versus bus parasitic capacitance (C) for an I²C bus

Figure 6. I²C bus protocol Table 3. Device select code

1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respec tive external pins on the memory device.
3. A10, A9 and A8 represent most significant bits of the address.

M24C16, M24C08, M24C04, M24C02, M24C01 Device operation Doc ID 5067 Rev 17 11/38

3 Device operation

The device supports the I²C protocol. This is summarized in Figure 6. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The device is always a slave in all communication.

3.1 Start condition

Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition.

3.2 Stop condition

Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode. A Stop condition at the end of a Write command triggers the internal Write cycle.

3.3 Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9 th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits.

3.4 Data input

During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven Low.

3.5 Memory addressing

in Table 3 (on Serial Data (SDA), most significant bit first). Kbits, 2 KBytes (except where M24C01 devices are used). The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. the device select code, it deselects itself from the bus, and goes into Standby mode. Table 4. Operating modes

1 X reStart, Device Select, RW = 1

Figure 7. Write mode sequences with WC = 1 (data write inhibited)

3.6 Write operations

Data (SDA) is disabled internally, and the device does not respond to any request. corresponding data bytes are not acknowledged as shown in Figure 7.

Device operation M24C16, M24C08, M24C04, M24C02, M24C01 14/38 Doc ID 5067 Rev 17

3.6.1 Byte Write

After the device select code and the address byte, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven High, the device replies to the data byte with NoAck, as shown in Figure 7, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 8.

3.6.2 Page Write

The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits are the same. If more bytes are sent than will fit up to the end of the page, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device if Write Control ( WC) is Low. If the addressed location is Write-protected, by Write Control (WC) being driven High, the device replies to the data bytes with NoAck, as shown in Figure 7, and the locations are not modified. After each byte is transferred, the internal byte address counter (the 4 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition.

Figure 8. Write mode sequences with WC = 0 (data write enabled)

Figure 9. Write cycle polling flowchart using ACK

3.6.3 Minimizing system delays by polling on ACK

can be used by the bus master.

• Initial condition: a Write cycle is in progress.
• Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction).
• Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). Write cycle in progress AI01847d Next operation is addressing the memory Start condition Device select with RW = 0 ACK Returned YES NO YESNO ReStart Stop Data for the Write operation Device select with RW = 1 Send Address and Receive ACK First byte of instruction with RW = 0 already decoded by the device YESNO Start condition Continue the Write operation Continue the Random Read operation

Figure 10. Read mode sequences

1. The seven most significant bits of the dev ice select code of a Random Read (in the 1st and 3rd bytes) must

3.7 Read operations

Read operations are performed independently of the state of the Write Control (WC) signal. The device has an internal address counter which is incremented each time a byte is read.

3.7.1 Random Address Read

must not acknowledge the byte, and terminates the transfer with a Stop condition.

Device operation M24C16, M24C08, M24C04, M24C02, M24C01 18/38 Doc ID 5067 Rev 17

3.7.2 Current Address Read

For the Current Address Read operation, following a Start condition, the bus master only sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition , as shown in Figure 10, without acknowledging the byte.

3.7.3 Sequential Read

This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 10. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter ‘rolls-over’, and the device continues to output data from memory address 00h.

3.7.4 Acknowledg e in Read mode

For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device terminates the data transfer and switches to its Standby mode.

4 Initial delivery state

The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).

5 Maximum rating

Table 5. Absolute maximum ratings

1. Compliant with JEDEC Std J-STD-020C (for smal l body, Sn-Pb or Pb assembly), the ST ECOPACK®
2. T LEAD max must not be applied for more than 10 s.

6 DC and AC parameters

match the measurement conditions when relying on the quoted parameters. Table 6. Operating conditions (M24Cxx-W) Table 7. Operating conditions (M24Cxx-R) Table 8. Operating conditions (M24Cxx-F)

Table 9. DC characteristics (M24Cxx-W, device grade 6)

1. The device is not selected after a power-up, after a read command (after the Stop condition), or after the

completion of the internal write cycle tW (tW is triggered by the correct decoding of a write command). Table 10. DC characteristics (M24Cxx-W, device grade 3)

1. The device is not selected after a power-up, after a read command (after the Stop condition), or after the

completion of the internal write cycle tW (tW is triggered by the correct decoding of a write command).

Table 11. DC characteristics (M24Cxx-R)

1. The device is not selected after a power-up, after a read command (after the Stop condition), or after the

completion of the internal write cycle tW (tW is triggered by the correct decoding of a write command).

Figure 11. AC measurement I/O waveform Table 12. DC characteristics (M24Cxx-F)

1. The device is not selected after a power-up, after a read co mmand (after the Stop condition), or after the completion of the

internal write cycle tW (tW is triggered by the correct decoding of a write command). Table 13. AC measurement conditions Table 14. Input parameters

Table 15. AC characteristics at 400 kHz (I 2C Fast-mode) (M24Cxx-W, M24Cxx-R,

1. All values are referred to V IL(max) and VIH(min).
2. Characterized only, not tested in production.
3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
5. t CLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or

0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 5.

Table 16. AC characteristics at 100 kHz (I 2C Standard-mode)(1) (M24Cxx-W,

1. Values recommended by the I 2C bus Standard-mode specification for a robust design of the I2C bus

characteristics at 400 kHz (I2C Fast-mode) (M24Cxx-W, M24Cxx-R, M24Cxx-F).

1. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
2. For a reStart condition, or following a Write cycle.

Figure 12. AC waveforms

7 Package mechanical data

specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 13. WLCSP (0.5 mm) and Thin WLCSP (0.3 mm) 0.4 mm pitch 5 bumps, Table 17. M24C08: WLCSP (0.5 mm height) 0.4 mm pitch, 5 bumps, package data

1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. N is the total number of terminals.

Table 18. M24C08: Thin WLCSP (0.3 mm hei ght), 0.4 mm pitch, 5 bumps, package

1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. N is the total number of terminals.

Table 19. M24C16: WLCSP (0.5 mm height) 0.4 mm pitch, 5 bumps, package data (1)

1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. N is the total number of terminals.

Figure 14. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package

1. The ‘1’ that appears in the top view of the package shows the position of pin 1 and the ‘N’ indicates the total
2. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 15. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead

1. The central pad (the area E2 by D2 in the abov e illustration) is pulled, internally, to VSS. It must not be
2. The circle in the top view of the package indicates the position of pin 1.
3. Values in inches are converted from mm and rounded to 4 decimal digits.
4. Applied for exposed die paddle and terminals. Excludes embedding part of exposed die paddle from

Figure 16. TSSOP8 – 8 lead thin shrink small outline, package outline

1. The circle in the top view of the package indicates the position of pin 1.

Table 22. TSSOP8 – 8 lead thin shrink small outline, package mechanical data

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 17. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package outline Table 23. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package mechanical data

1. Values in inches are converted from mm and rounded to 4 decimal digits.

8 Part numbering

of this device, please contact your nearest ST sales office. Table 24. Ordering information scheme

1. Only M24C08 and M24C16 devices are offered in the WLCSP package.
2. Only M24C08-F devices are offered in the Thin WLCSP package.
3. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.

nearest ST sales office for a copy. 5 = Consumer: device tested with standard test flow over –20 to 85 °C.

1. Used only for device grade 3.

9 Revision history

Table 25. Document revision history 5V voltage range at temperature range 3 (-xx3) no longer preliminary data. -0.45V. tW(max) value for -R voltage range corrected.

Deleted TSSOP8 3x3 mm package from cover page. Deleted Figure and Table relating to TSSOP8 3x3 mm package information. Deleted line and note in Table 24: Ordering information scheme concerning TSSOP8 3x3 mm package. In Table 26: Available M24C08 products (package, voltage range, temperature grade) updated UFDFPN8 (MC) package for M24C08-F range to 5 and deleted line concerning TSSOP8 3x3 mm package. In Table 27: Available M24C04 products (package, voltage range, temperature grade) updated UFDFPN8 (MC) package for M24C08-F range to 5. In Table 28: Available M24C02 products (package, voltage range, temperature grade) updated UFDRPN8 options to MB or MC. 15-Apr-2011 17 Updated: - Text modified in Section 2.3: Chip Enable (E0, E1, E2). - Text modified in Section 3.6: Write operations. - VESD minimum value deleted ofTable 5: Absolute maximum ratings. - Figure 15: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, outline. - E2 (Rev MC): “ddd” has been changed to “eee” and its values modified in Table 21: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data. Added: - Note at the end of the Section 1: Description. - Figure footnote below the Figure 3: WLCSP and thin WLCSP connections (top view, marking side, with balls on the underside). Date Version Changes