M24512-DRE STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Description
- 2 Signal description
- 2.1 Serial Clock (SCL)
- 2.2 Serial Data (SDA)
- 2.3 Chip Enable (E2, E1, E0)
- 2.4 Write Control (WC
- 2.5 V SS (ground)
- 2.6 Supply voltage (V CC)
- 3 Device operation
- 3.1 Start condition
- 3.2 Stop condition
- 3.3 Data input
- 3.4 Acknowledge bit (ACK)
- 3.5 Device addressing
- 3.6 Identification page
- 4 Instructions
- 4.1 Write operations
- 4.1.1 Byte Write
- 4.1.2 Page Write
- 4.1.3 Write Identification Page
- 4.1.4 Lock Identification Page
- 4.1.5 Minimizing Write delays by polling on ACK
- 4.2 Read operations
- 4.2.1 Random Address Read
- 4.2.2 Current Address Read
- 4.2.3 Sequential Read
- 4.2.4 Read Identification Page
- 4.2.5 Read the lock status
- 4.2.6 Acknowledge in Read mode
Features
- Compatible with all I2C bus modes –1 M H z –4 0 0 k H z –1 0 0 k H z
- Memory array – 512 Kbits (64 Kby tes) of EEPROM – Page size: 128 bytes – Additional Write lockable page (Identification page)
- Extended temperature and voltage range – -40 °C to 105 °C; 1.8 V to 5.5 V
- Schmitt trigger inputs for noise filtering
- Short Write cycle time – Byte Write within 4 ms – Page Write within 4 ms
- Write cycle endurance – 4 million Write cycles at 25 °C – 1.2 million Write cycles at 85 °C – 900 k Write cycles at 105 °C
- Data retention – more than 50 years at 105 °C – 200 years at 55 °C
- ESD Protection (Human Body Model) – 4000 V
- Packages – RoHS compliant and halogen-free (ECOPACK2 SO8 (MN) TSSOP8 (DW) WFDFPN8 (MF) 2 x 3 mm 169 mil width 150 mil width
Table 15. WFDFPN8 (MLP8) – 8-lead thin fine pitch dual flat package no lead 2 x 3 mm,
1 Description
M24512-DRE is compliant with the level of reliability defined by the AEC-Q100 grade 2. The device is accessed by a simple serial I2C compatible interface running up to 1 MHz. with an embedded Error Correction Code logic. parameters which can be later permanently locked in read-only mode. Figure 1. Logic diagram
Figure 2. 8-pin package connection
- See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.
Table 1. Signal names
2 Signal description
2.1 Serial Clock (SCL)
2.2 Serial Data (SDA)
indicate how to calculate the value of the pull-up resistor).
2.3 Chip Enable (E2, E1, E0)
Figure 3. Device select code
2.4 Write Control (WC )
driven low or left floating. acknowledged, Data bytes are not acknowledged.
M24512-DRE Signal description
2.5 V SS (ground)
VSS is the reference for the VCC supply voltage.
2.6 Supply voltage (V CC)
VCC is the supply voltage pin.
3 Device operation
The device supports the I2C protocol (see Figure 4). the device (bus master or a slave) is defined as a receiver when reading the data. Figure 4. I2C bus protocol
M24512-DRE Device operation
3.1 Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition.
3.2 Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Stop condition at the end of a Write instruction triggers the internal Write cycle.
3.3 Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low.
3.4 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits.
3.5 Device addressing
value decoded on the E2, E1, E0 inputs. th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. match the device select code, it deselects itself from the bus, and goes into Standby mode. to each address byte with an acknowledge bit. Table 2. Device select code
- The most significant bit, b7, is sent first.
- E0, E1 and E2 bits are compared with the value read on input pins E0,E1,E2.
Note: A: significant address bit. Table 3. Significant address bits
3.6 Identification page
- Device identification code: the first three bytes are programmed by STMicroelectronics with the Device identification code, as shown in Table 4.
- Application parameters: the bytes after the Device identification code are available for application specific data. Note: If the end application does not need to read the Device identification code, this field can be overwritten and used to store application-specific data. Once the application-specific data are written in the Identification page, the whole Identification page should be permanently locked in Read-only mode. The instructions Read, Write and Lock Identification Page are detailed in Section 4: Instructions.
Table 4. Device identification code
4 Instructions
4.1 Write operations
For a Write operation, the bus master sends a Start condition followed by a device select code with the R/W bit reset to 0. The device acknowledges this, as shown in Figure 5, and waits for the master to send two address bytes (most significant address byte sent first, followed by the least significant address byte (Table 3). The device responds to each address byte with an acknowledge bit, and then waits for the data byte. When the bus master generates a Stop condition immediately after a data byte Ack bit (in the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle tW is then triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests. After the successful completion of an internal Write cycle (tW), the device internal address counter is automatically incremented to point to the next byte after the last modified byte. If the Write Control input (WC) is driven High, the Write instruction is not executed and the accompanying data bytes are not acknowledged, as shown in Figure 6.
4.1.1 Byte Write
terminates the transfer by generating a Stop condition, as shown in Figure 5. Figure 5. Write mode sequences with WC
4.1.2 Page Write
Figure 6. Write mode sequences with WC = 1 (data write inhibited)
- N is the number of bytes in a page.
4.1.3 Write Identification Page
The Identification Page (128 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. It is written by issuing the Write Identification Page instruction. This instruction uses the same protocol and format as Page Write (into memory array), except for the following differences:
- Device type identifier = 1011b
- Most significant address bits A15/A7 are don't care, except for address bit A10 which must be “0”. Least significant address bits A6/A0 define the byte location inside the Identification page. If the Identification page is locked, the data bytes transferred during the Write Identification Page instruction are not acknowledged (NoAck).
4.1.4 Lock Identification Page
The Lock Identification Page instruction (Lock ID) permanently locks the Identification page in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with the following specific conditions:
- Device type identifier = 1011b
- Address bit A10 must be ‘1’; all other address bits are don't care
- The data byte must be equal to the binary value xxxx xx1x, where x is don't care
4.1.5 Minimizing Write delays by polling on ACK
- Initial condition: a Write cycle is in progress.
- Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction).
- Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 7. Write cycle polling flowchart using ACK
4.2 Read operations
Read operations are performed independently of the state of the Write Control (WC) signal. incremented by one, to point to the next byte address. Figure 8. Read mode sequences
4.2.1 Random Address Read
define a new address pointer value, see Table 3) followed by a current Read.
4.2.2 Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only sends a device select code with the R/W bit set to 1. The device acknowledges this, and outputs the byte pointed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 8, without acknowledging the byte. Note that the address counter value is defined by instructions accessing either the memory or the Identification page. When accessing the Identification page, the address counter value is loaded with the Identification page byte location, when accessing the memory, it is safer to always use the Random Address Read instruction (this instruction loads the address counter with the byte location to read in the memory) instead of the Current Address Read instruction.
4.2.3 Sequential Read
A sequential Read can be used after a Current Address Read or a Random Address Read. After a Read instruction, the device can continue to output the next byte(s) in sequence if the bus master sends additional clock pulses and if the bus master does acknowledge each transmitted data byte. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 8. The sequential read is controlled with the device internal address counter which is automatically incremented after each byte output. After the last memory address, the address counter “rolls-over”, and the device continues to output data from memory address 00h.
4.2.4 Read Identification Page
The Identification Page can be read by issuing a Read Identification Page instruction. This instruction uses the same protocol and format as the Random Address Read (from memory array) with device type identifier defined as 1011b. The most significant address bits A15/A7 are don't care and the least significant address bits A6/A0 define the byte location inside the Identification page. The number of bytes to read in the ID page must not exceed the page boundary.
4.2.5 Read the lock status
The locked/unlocked status of the Identification page can be checked by transmitting a specific truncated command [Identification Page Write instruction + one data byte] to the device. The device returns an acknowledge bit after the data byte if the Identification page is unlocked, otherwise a NoAck bit if the Identification page is locked. Right after this, it is recommended to transmit to the device a Start condition followed by a Stop condition, so that:
- Start: the truncated command is not executed because the Start condition resets the device internal logic,
- Stop: the device is then set back into Standby mode by the Stop condition.
4.2.6 Acknowledge in Read mode
For all Read instructions, the device waits, after each byte sent out, for an acknowledgment during the “9th bit” time. If the bus master does not send the Acknowledge (the master drives SDA high during the 9th bit time), the device terminates the data transfer and enters its Standby mode.
5 Application design recommendations
5.1 Supply voltage
5.1.1 Operating supply voltage (V CC)
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 7). This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal Write cycle (tW). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.
5.1.2 Power-up conditions
When the power supply is turned on, the VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined in Table 7. In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC reaches the internal threshold voltage (this threshold is defined in the DC characteristic Table 10 as VRES). When VCC passes over the POR threshold, the device is reset and in the following state:
- in the Standby power mode
- deselected As soon as the VCC voltage has reached a stable value within the [VCC(min), VCC(max)] range (defined in Table 7), the device is ready for operation.
5.1.3 Power-down
During power-down (continuous decrease in the VCC supply voltage below the minimum VCC operating voltage defined in Table 7), the device must be in Standby power mode (that is after a STOP condition or after the completion of the Write cycle tW if an internal Write cycle is in progress).
Application design recommendations M24512-DRE
5.2 Cycling with Error Correction Code (ECC)
The error correction code (ECC) is an internal logic function which is transparent for the I2C communication protocol. The ECC logic is implemented on each group of four EEPROM bytes (1). Inside a group, if a single bit out of the four bytes happens to be erroneous during a Read operation, the ECC detects this bit and replaces it with the correct value. The read reliability is therefore much improved. Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently. In this case, the ECC function also writes/cycles the three other bytes located in the same group(1). As a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the 4 bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined in Table 6. Example 1: maximum cycling limit reached with 1 million cycles per byte Each byte of a group can be equally cycled 1 million times (at 25 °C) so that the group cycling budget is 4 million cycles. Example 2: maximum cycling limit reached with unequal byte cycling Inside a group, byte0 can be cycled 2 million times, byte1 can be cycled 1 million times, byte2 and byte3 can be cycled 500,000 times, so that the group cycling budget is 4 million cycles. 1. A group of four bytes is located at addresses [4 *N, 4*N+1, 4*N+2, 4*N+3], where N is an integer
6 Delivery state
The device is delivered as follows:
- The memory array is set to all 1s (each byte = FFh).
- Identification page: the first three bytes define the Device identification code (value defined in Table 4). The content of the following bytes is Don’t Care.
7 Maximum rating
Table 5. Absolute maximum ratings
- Compliant with JEDEC Std J-STD-020D (for sm all body, Sn-Pb or Pb-free assembly), the ST
Substances (RoHS directive 2011/65/EU of July 2011).
- Positive and negative pulses applied on pin pairs, according to AEC-Q100-002 (compliant with
8 DC and AC parameters
characteristics of the device. Table 6. Cycling performance by groups of four bytes
- The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N,
by characterization and qualification.
- A Write cycle is executed when either a Page Write, a Byte Write, a Write Identification Page or
also to Section 5.2: Cycling with Error Correction Code (ECC). Table 7. Operating conditions (voltage range R) Table 8. AC measurement conditions
Figure 9. AC measurement I/O waveform Table 9. Input parameters
- Characterized only, not tested in production.
- E2, E1, E0 input impedance when the memory is selected (after a Start condition).
Table 10. DC characteristics
- The device is not selected after power-up, after a R ead instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
- Characterized only, not 100% tested.
- Ei inputs should be tied to Vss (see Section 2.3).
- Ei inputs should be tied to V CC (see Section 2.3).
Table 11. 400 kHz AC characteristics
- Test conditions (in addition to those in Table 7 and Table 8).
- Characterized value, not tested in production.
- There is no min. or max. values for the input signal rise and fall times. It is however
- To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and
the falling or rising edge of SDA.
- t CLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either
- WC =0 set up time condition to enable the execution of a WRITE command.
- WC =0 hold time condition to enable the execution of a WRITE command.
Table 12. 1 MHz AC characteristics
- Test conditions (in addition to those in Table 7 and Table 8).
- There is no min. or max. values for the input signal rise and fall times. However, it is
20 ns and less than 120 ns when fC <1M H z .
- Characterized only, not tested in production.
- To avoid spurious Start and Stop conditions , a minimum delay is placed between SCL=1 and
the falling or rising edge of SDA.
- t CLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either
- WC =0 set up time condition to enable the execution of a WRITE command.
- WC =0 hold time condition to enable the execution of a WRITE command.
Figure 12. AC waveforms
9 Package mechanical data
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 13. TSSOP8 – 8-lead thin shrink small outline, package outline Table 13. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
- Values in inches are converted from mm and rounded to four decimal digits.
Figure 14. SO8N – 8 lead plastic small outline, 150 mils body width, package outline Table 14. SO8N – 8 lead plastic small outline, 150 mils body width, package data
- Values in inches are converted from mm and rounded to four decimal digits.
Figure 15. WFDFPN8 (MLP8) – 8-lead thin fine pitch dual flat package no lead
- The central pad (the area E2 by D2 in the above illustration) must be either connected to V ss or left floating
(not connected) in the end application.
- Values in inches are converted from mm and rounded to four decimal digits.
- NX is the number of terminals.
- ND is the number of terminals on “D” sides.
- Applied for exposed die paddle and terminal s. Exclude embedding part of exposed die paddle
10 Part numbering
of the devices, please contact your nearest ST sales office. Table 16. Ordering information scheme
- All package are ECOPACK2 ® (RoHS-compliant and free of brominated, chlorinated and
Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity.
Table 17. Document revision history 22-Jan-2015 1 Initial release.