M24512-DFMC6TG NUMONYX | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Description
- 2 Signal description
- 2.1 Serial data output (Q)
- 2.2 Serial data input (D)
- 2.3 Serial clock (C)
- 2.4 Chip Select (S
- 2.5 Hold (HOLD )
- 2.6 Write protect/enhanced program supply voltage (W /VPP)
- 2.7 V CC supply voltage
- 2.8 V SS ground
- 3 SPI modes
- 4 Operating features
- 4.1 Page programming
- 4.2 Sector erase and bulk erase
- 4.3 Polling during a write, program or erase cycle
- 4.4 Fast program/erase mode
- 4.5 Active power and standby power modes
- 4.6 Status register
- 4.7 Protection modes
- 4.8 Hold condition
- 5 Memory organization
- 6 Instructions
- 6.1 Write enable (WREN)
- 6.2 Write disable (WRDI)
- 6.3 Read identification (RDID)
- 6.4 Read status register (RDSR)
- 6.4.1 WIP bit
Features
128-Mbit flash memory 2.7 to 3.6 V single supply voltage SPI bus compatible serial interface 54 MHz clock rate (maximum) for 65 nm devices VPP = 9 V for fast program/erase mode (optional) Page program (up to 256 Bytes): – in 0.5 ms (typical) for 65 nm devices – in 0.4 ms (typical with V PP = 9 V) for 65 nm devices Sector erase (2 Mbit) Bulk erase (128 Mbit) Electronic signature – JEDEC standard two-byte signature (2018h) More than 10,000 erase/program cycles per sector More than 20-year data retention RoHS compliant packages VDFPN8 (ME) 8 x 6 mm (MLP8) SO16 (MF) 300 mils width www.numonyx.com
Table 18. VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8 × 6mm,
1 Description
clock frequency operation up to 54 MHz(1). protect/enhanced program supply voltage pin (W/VPP). using the sector erase instruction. and RoHS compliant packages. number. The new device is backward compatible with the old one. Figure 1. Logic diagram
- 54 MHz operation is available only fo r 65 nm process technology devices, which are identified by the process
identification digit ‘A’ in the device marking and process letter "B" in the part number.
Signal description M25P128
2 Signal description
2.1 Serial data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).
2.2 Serial data input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C).
2.3 Serial clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4 Chip Select (S )
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in the Standby Power mode. Driving Chip Select (S) Low selects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.
2.5 Hold (HOLD )
The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
M25P128 Signal description
2.6 Write protect/enhanced program supply voltage (W/VPP)
W/VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If the W/VPP input is kept in a low voltage range (0V to VCC) the pin is seen as a control input. This input signal is used to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register). If VPP is in the range of VPPH it acts as an additional power supply pin. In this case VPP must be stable until the Program/Erase algorithm is completed.
2.7 V CC supply voltage
VCC is the supply voltage.
2.8 V SS ground
VSS is the reference for the VCC supply voltage.
3 SPI modes
output data is available from the falling edge of Serial Clock (C). Figure 4. Bus master and memory devices on the SPI bus
- The Write Protect (W /VPP) and Hold (HOLD) signals should be driven, High or Low as appropriate.
- These pull-up resistors, R, ensure that the memory dev ices are not selected if the Bus Master leaves the S line in the high-
High at the same time, and so, that the tSHCH requirement is met).
Figure 5. SPI modes supported
Operating features M25P128
4 Operating features
4.1 Page programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration tPP). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted Bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few Bytes (see Section 6.8: Page program (PP), Table 15: AC characteristics for 65 nm devices, and Table 17: AC characteristics for 130 nm devices).
4.2 Sector erase and bulk erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of duration t SE or tBE). The Erase instruction must be preceded by a Write Enable (WREN) instruction.
4.3 Polling during a write, program or erase cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, or tBE). The Write In Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete.
4.4 Fast program/erase mode
The Fast Program/Erase mode is used to speed up programming/erasing. The device enters the Fast Program/Erase mode during the Page Program, Sector Erase or Bulk Erase instruction whenever a voltage equal to VPPH is applied to the W/VPP pin. The use of the Fast Program/Erase mode requires specific operating conditions in addition to the normal ones (VCC must be within the normal operating range): the voltage applied to the W/VPP pin must be equal to VPPH (see Table 11) ambient temperature, TA must be 25 °C ±10 °C, the cumulated time during which W/VPP is at VPPH should be less than 80 hours
M25P128 Operating features
4.5 Active power and standby power modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes in to the Standby Power mode. The device consumption drops to ICC1.
4.6 Status register
The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. See Section 6.4: Read status register (RDSR) for a detailed description of the Status Register bits.
4.7 Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P128 features the following data protection mechanisms: Power On Reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification. Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: –P o w e r - u p – Write Disable (WRDI) instruction completion – Write Status Register (W RSR) instruction completion – Page Program (PP) instruction completion – Sector Erase (SE) instruction completion – Bulk Erase (BE) instruction completion The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only. This is the Software Protected Mode (SPM). The Write Protect (W /VPP) signal allows the Block Protect (BP2, BP1, BP0) bits and Status Register Write Disable (SRWD) bit to be protected. This is the Hardware Protected Mode (HPM).
4.8 Hold condition
Write Status Register, Program or Erase cycle that is currently in progress. coincides with Serial Clock (C) being Low (as shown in Figure 6). coincides with Serial Clock (C) being Low. Low. (This is shown in Figure 6). Input (D) and Serial Clock (C) are Don’t Care. from the moment of entering the Hold condition. the device from going back to the Hold condition. Table 2. Protected area sizes
- The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
Figure 6. Hold condition activation
5 Memory organization
65536 pages (256 bytes each). Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable. Figure 7. Block diagram
256 Byte
256 Bytes (Page Size)
Table 3. Memory organization
63 FC0000h FFFFFFh
62 F80000h FBFFFFh
61 F40000h F7FFFFh
60 F00000h F3FFFFh
59 EC0000h EFFFFFh
58 E80000h EBFFFFh
57 E40000h E7FFFFh
56 E00000h E3FFFFh
55 DC0000h DFFFFFh
54 D80000h DBFFFFh
53 D40000h D7FFFFh
52 D00000h D3FFFFh
51 CC0000h CFFFFFh
50 C80000h CBFFFFh
49 C40000h C7FFFFh
48 C00000h C3FFFFh
47 BC0000h BFFFFFh
46 B80000h BBFFFFh
45 B40000h B7FFFFh
44 B00000h B3FFFFh
43 AC0000h AFFFFFh
42 A80000h ABFFFFh
41 A40000h A7FFFFh
40 A00000h A3FFFFh
Table 3. Memory organization (continued)
6 Instructions
The instruction set is listed in Table 4. instruction, this might be followed by address bytes, or by data bytes, or by both or none. after any bit of the data-out sequence is being shifted out. Chip Select (S) being driven Low is an exact multiple of eight. cycle or Erase cycle continues unaffected. Table 4. Instruction set
6.1 Write enable (WREN)
The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit. Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction. instruction code, and then driving Chip Select (S) High. Figure 8. Write enable (WREN) instruction sequence
6.2 Write disable (WRDI)
The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit. instruction code, and then driving Chip Select (S) High. Figure 9. Write disable (WRDI) instruction sequence
6.3 Read identification (RDID)
and the memory capacity of the device in the second byte (18h). not decoded, and has no effect on the cycle that is in progress. the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 10. any time during data output. Figure 10. Read identification (RDID) instruction sequence and data-out sequence Table 5. Read identification (RDID) data-out sequence
6.4 Read status register (RDSR)
also possible to read the Status Register continuously, as shown in Figure 11.
6.4.1 WIP bit
0 no such cycle is in progress.
6.4.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. Latch is reset and no Write Status Register, Program or Erase instruction is accepted.
6.4.3 BP2, BP1, BP0 bits
6.4.4 SRWD bit
Table 6. Status register format
Figure 11. Read status register (RDSR) instruction sequence and data-out sequence
6.5 Write status register (WRSR)
executed, the device sets the Write Enable Latch (WEL). followed by the instruction code and the data byte on Serial Data Input (D). The instruction sequence is shown in Figure 12. Status Register. b6 and b5 are always read as 0. Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in. bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. Protect (W/VPP) signal allow the device to be put in the Hardware Protected Mode (HPM). Table 7. Protection modes
- As defined by the values in the Block Protect (BP2 , BP1, BP0) bits of the Status Register, as shown in
Table 2: Protected area sizes.
of the whether Write Protect (W/VPP) is driven High or Low. Register, are also hardware protected against data modification. (BP2, BP1, BP0) bits of the Status Register, can be used. Figure 12. Write status register (WRSR) instruction sequence
6.6 Read data bytes (READ)
R, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 13. to be continued indefinitely. any effects on the cycle that is in progress. Figure 13. Read data bytes (READ) instruction sequence and data-out sequence
6.7 Read data bytes at higher speed (FAST_READ)
A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). C, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 14. 000000h, allowing the read sequence to be continued indefinitely. Figure 14. Read data bytes at higher speed (FAST_READ) instruction and data-out
6.8 Page program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving Chip Select (S ) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data Input (D). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 15. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted Bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few Bytes (see Table 15: AC characteristics for 65 nm devices and Table 17: AC characteristics for 130 nm devices). Chip Select (S ) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed.
Figure 15. Page program ( PP) instruction sequence
6.9 Sector erase (SE)
can be accepted, a Write Enable (WREN) instruction must previously have been executed. must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 16. time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. (BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed. Figure 16. Sector erase (SE) instruction sequence
24 Bit Address
6.10 Bulk erase (BE)
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The instruction sequence is shown in Figure 17. completed, the Write Enable Latch (WEL) bit is reset. are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected. Figure 17. Bulk erase (BE) instruction sequence
Power-up and power-down M25P128
7 Power-up and power-down
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on VCC) until VCC reaches the correct value: VCC(min) at Power-up, and then for a further delay of tVSL VSS at Power-down Usually a simple pull-up resistor on Chip Select (S) can be used to ensure safe and proper Power-up and Power-down. To avoid data corruption and inadvertent write operations during Power-up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less than the Power On Reset (POR) threshold voltage, VWI – all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No Write Status Register, Program or Erase instructions should be sent until the later of: tPUW after VCC passed the VWI threshold tVSL after VCC passed the VCC(min) level These values are specified in Table 8. If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be selected for READ instructions even if the tPUW delay is not yet fully elapsed. At Power-up, the device is in the following state: The device is in the Standby Power mode The Write Enable Latch (WEL) bit is reset. Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply. Each device in a system should have the VCC rail decoupled by a suitable capacitor close to the package pins (generally, this capacitor is of the order of 0.1µF). At Power-down, when VCC drops from the operating voltage, to below the Power On Reset (POR) threshold voltage, VWI, all operations are disabled and the device does not respond to any instruction. (The designer needs to be aware that if a Power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption can result.) Power up sequencing for Fast program/erase mode: VCC should attain VCCMIN before VPPH is applied.
Figure 18. Power-up timing
8 Initial delivery state
contains FFh). The Status Register contains 00h (all Status Register bits are 0). Table 8. Power-up timing and V WI threshold for 65 nm devices(1)
- 65 nm technology devices are identif ied by the process identification digit ‘A’ in the device marking and
process letter "B" in the part number.
- These parameters are characterized only.
Table 9. Power-up timing and V WI threshold for 130 nm devices
- These parameters are characterized only.
9 Maximum rating
Table 10. Absolute maximum ratings
10 DC and AC parameters
match the measurement conditions when relying on the quoted parameters.
- Output Hi-Z is defined as the point where data out is no longer driven.
Figure 19. AC measurement I/O waveform
- Sampled only, not 100% tested, at T A=25 °C and a frequency of 20 MHz.
Table 11. Operating conditions Table 12. AC measurement conditions Table 13. Capacitance
Table 14. DC characteristics for 65 nm devices (1)
- 65 nm process technology devices ar e identified by the process identification digit ‘A’ in the device marking
and process letter "B" in the part number. Table 15. AC characteristics for 65 nm devices (1)
- 65 nm process technology devices are identified by the process identification digit ‘A’ in the device marking
and process letter "B" in the part number.
- t CH and tCL must be greater than or equal to 1/fC (max).
- Value is guaranteed by characteriza tion, not 100% tested in production.
- Expressed as a slew-rate.
- Only applicable as a constr aint for WRSR instruction when SRWD is set to 1.
- V PPH should be kept at a valid level until the program or erase operation has completed and its result
(success or failure) is known. Table 15. AC characteristics for 65 nm devices (1) (continued)
- When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are
- int(A) corresponds to the upper integer part of A. For example int(12/8) = 2, int(32/8) = 4, int(15.3) = 16.
Table 16. DC characteristics for 130 nm devices
Table 17. AC characteristics for 130 nm devices
Figure 20. Serial input timing
- t CH and tCL must be greater than or equal to 1/fC (max).
- Value is guaranteed by characteriza tion, not 100% tested in production.
- Expressed as a slew-rate.
- Only applicable as a constr aint for WRSR instruction when SRWD is set to 1.
(success or failure) is known.
- When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are
Table 17. AC characteristics for 130 nm devices (continued)
Figure 25. VDFPN8 (MLP8), 8-lead Very th in Dual Flat Package No lead, 8x6mm,
- The circle in the top view of the package indicates the position of pin 1.
- D2 Max should not exceed (D – K – 2 × L).
Figure 26. SO16 wide – 16 lead Plasti c Small Outline, 300 mils body width Table 19. SO16 wide – 16 l ead Plastic Small Outline, 300 mils body width
of this device, please contact your nearest Numonyx sales office. soldering conditions are also marked on the inner box label. Table 20. Ordering information scheme 6 = Industrial temperature range, –40 to 85 °C.
Table 21. Document revision history 02-May-2005 0.1 First issue. 09-Jun-2005 0.2 Table 2: Protected area sizes updated. Memory capacity modified in Section 6.3: Read identification (RDID). Page programming and Section 6.8: Page program (PP). characteristics for 65 nm devices. Document status promoted from Preliminary Data to full Datasheet. Program/Erase mode in Power-up and power-down section. Dual Flat Package No lead, 8 × 6mm, package mechanical data. VIO max modified in Table 10: Absolute maximum ratings. 10-Dec-2007 3 Applied Numonyx branding. Dual Flat Package No lead, 8 × 6mm, package mechanical data. 17-Dec-2009 5 Added “Process Technology” to Ordering Information table. 65 nm devices as follows: 50 MHz to 54 MHz and 20 MHz to 33 MHz.