M24256-BW STMICROELECTRONICS | Alldatasheet

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Technical content

Table 1. Product List Figure 1. Packages

128 Kbits

256 Kbits

has a push-pull (rather than open drain) output. the value of the pull-up resistor can be calculated). puts are read as Low (0,0,0). Write operations are allowed. Data bytes are not acknowledged. Figure 4. Maximum RP Value versus Bus Parasitic Capacitance (C) for an I2C Bus

Figure 5. I2C Bus Protocol Table 3. Device Select Code Note: 1. The most significant bit, b7, is sent first.

  1. E0, E1 and E2 are compared against the respective external pins on the memory device.

Table 4. Most Significant Byte Table 5. Least Significant Byte

any device that reads the data to be a receiver. ways a slave in all communication. and will not respond unless one is given. (SDA) on the rising edge of Serial Clock (SCL). sends the Device Select Code, shown in Table 3. (on Serial Data (SDA), most significant bit first). bit Device Type Identifier is 1010b. code on the Chip Enable (E0, E1, E2) inputs. set to 1 for Read and 0 for Write operations. Table 6. Operating Modes

1 X reSTART, Device Select, RW = 1

dition, as shown in Figure 7.. Figure 7. Write Mode Sequences with WC

Figure 8. Write Cycle Polling Flowchart using ACK data from its internal latches to the memory cells.

  1. and Table 15., but the typical time is shorter.

– Initial condition: a Write cycle is in progress. byte of the new instruction). having been sent during Step 1).

Figure 9. Read Mode Sequences Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 4th bytes) must be identical. the state of the Write Control (WC) signal. mented by one, to point to the next byte address. nates the transfer with a Stop condition.

M24128-BW, M24128-BR, M24256-BW, M24256-BR Sequential Read This operation can be used after a Current Ad- dress Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the de- vice continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 9.. The output data comes from consecutive address- es, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter ‘rolls-over’, and the device continues to output data from memory address 00h. Acknowledge in Read Mode For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device termi- nates the data transfer and switches to its Stand- by mode. INITIAL DELIVERY STATE The device is delivered with all the memory array bits set to 1 (each byte contains FFh).

Table 7. may cause permanent damage to the de- Table 7. Absolute Maximum Ratings

  1. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)

Table 8. Operating Conditions (M24128-BW, M24256-BW) Table 9. Operating Conditions (M24128-BR, M24256-BR) Table 10. AC Measurement Conditions Figure 10. AC Measurement I/O Waveform

Table 11. Input Parameters

  1. Sampled only, not 100% tested.

Table 12. DC Characteristics (M24128-BW, M24256-BW) Table 13. DC Characteristics (M24128-BR, M24256-BR)

Table 14. AC Characteristics ( M24128-BW, M24256-BW) Note: 1. For a reSTART condition, or following a Write cycle.

  1. Sampled only, not 100% tested.
  2. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

Test conditions specified in Table 8.

Table 15. AC Characteristics (M24128-BR, M24256-BR) Note: 1. For a reSTART condition, or following a Write cycle.

  1. Sampled only, not 100% tested.
  2. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

Test conditions specified in Table 9.

Figure 11. AC Waveforms

Figure 12. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline Note: Drawing is not to scale. Table 16. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data

Figure 13. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline Note: Drawing is not to scale. Table 17. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data

Figure 14. SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Outline Note: Drawing is not to scale. Table 18. SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Mechanical Data

Figure 15. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline Note: Drawing is not to scale. Table 19. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data

Table 20. Ordering Information Scheme please contact your nearest ST Sales Office. 6 = Industrial temperature range, –40 to 85 °C.

M24128-BW, M24128-BR, M24256-BW, M24256-BR

REVISION HISTORY

Table 21. Document Revision History ms write time for M24128-B and M24128-BW products with process letter "B". mechanical data for unavailable package removed. Description, Power-On Reset, Memory Addressing, Write Operations, Read Operations. 16-Apr-2004 5.0 SO8W package added. Absolute Maximum Ratings for VIO(min) and VCC (min) changed. Soldering temperature information clarified for RoHS compliant devices. M24xxx-B, M24xxx-BV and M24xxx-BS removed from the datasheet. Product List summary table added. Power On Reset paragraph updated. Figure 4., Maximum RP Value versus Bus Parasitic Capacitance (C) for an I2C Bus updated. ZL and ZH definition changed. ICC and ICC1 updated in Table 12., DC Characteristics (M24128-BW, M24256-BW). Device Grade information further clarified to Table 20., Ordering Information Scheme.

M24128-BW, M24128-BR, M24256-BW, M24256-BR Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America