M24256-BRDW6G

M24512-W STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1 Summary description
• 2 Signal description
• 2.1 Serial Clock (SCL)
• 2.2 Serial Data (SDA)
• 2.3 Chip Enable (E0, E1, E2)
• 2.4 Write Control (WC
• 2.5 Supply voltage (VCC )
• 2.5.1 Operating supply voltage VCC
• 2.5.2 Internal device reset
• 2.5.3 Power-down
• 3 Device operation
• 3.1 Start Condition
• 3.2 Stop Condition
• 3.3 Acknowledge Bit (ACK)
• 3.4 Data Input
• 3.5 Memory Addressing
• 3.6 Write operations
• 3.7 Byte Write
• 3.8 Page Write
• 3.9 ECC (Error Correction Code) and Write cycling
• 3.10 Minimizing System Delays by Polling On ACK
• 3.11 Read Operations
• 3.12 Random Address Read
• 3.13 Current Address Read
• 3.14 Sequential Read
• 3.15 Acknowledge in Read Mode
• 4 Initial delivery state
• 5 Maximum rating

512 Kbit and 256 Kbit Serial I²C bus EEPROM

with three Chip Enable lines Feature summary ■ Two-wire I2C Serial interface supports 400 kHz Protocol ■ Supply voltage ranges: ■ 1.8 V to 5.5 V (M24xxx-R) ■ 2.5 V to 5.5 V (M24xxx-W) ■ Write Control Input ■ Byte and Page Write ■ Random and sequential read modes ■ Self-timed programming cycle ■ Automatic Address Incrementing ■ Enhanced ESD/Latch-Up Protection ■ More than 1,000,000 Write cycles ■ More than 40-year data retention ■ Packages – ECOPACK® (RoHS compliant) SO8 (MW) 208 mils width TSSOP8 (DW) SO8 (MN) 150 mils width

M24512-W, M24512-R, M24256-BW, M24256-BR Contents

Table 15. SO8W – 8 lead Plastic Small Outline, 208 mils body width, package mechanical data . . . 25 Table 16. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package mechanical data . . . 26

1 Summary description

bits and 32 Kb × 8 bits, respectively. I2C uses a two-wire serial interface, comprising a bi-directional data line and a clock line. bit (RW) (as described in Table 2), terminated by an acknowledge bit. terminated by a Stop condition after an Ack for Write, and after a NoAck for Read. ECOPACK® packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 1. Logic diagram Table 1. Signal names

Figure 2. SO and TSSOP connections

1. See Package mechanical section for package dimensions, and how to identify pin-1.

2 Signal description

2.1 Serial Clock (SCL)

2.2 Serial Data (SDA)

the value of the pull-up resistor can be calculated).

2.3 Chip Enable (E0, E1, E2)

inputs are read as Low (0,0,0). Figure 3. Device Select Code

2.4 Write Control (WC )

Write operations are allowed. acknowledged, Data bytes are not acknowledged.

2.5 Supply voltage (V CC )

2.5.1 Operating supply voltage VCC

within the specified [VCC (min), VCC (max)] range must be applied (see Table 7 and Table 8). and, for a Write instruction, until the completion of the internal write cycle (tW ).

2.5.2 Internal device reset

lower than the minimum VCC operating voltage defined in Table 7 and Table 8).

2.5.3 Power-down

responding to any instruction sent to it. there should be no internal Write cycle in progress). Figure 4. Maximum R

Figure 5. I2C Bus Protocol Table 2. Device Select Code

1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.

Table 3. Most Significant address Byte Table 4. Least Significant address Byte

M24512-W, M24512-R, M24256-BW, M24256-BR Device operation

3 Device operation

The device supports the I2C protocol. This is summarized in Figure 5.. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24512 device is always a slave in all communication.

3.1 Start Condition

Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given.

3.2 Stop Condition

Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal Write cycle.

3.3 Acknowledge Bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9 th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits.

3.4 Data Input

During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven Low.

3.5 Memory Addressing

shown in Table 2. (on Serial Data (SDA), most significant bit first). the Chip Enable (E0, E1, E2) inputs. th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. the Device Select code, it deselects itself from the bus, and goes into Stand-by mode. Table 5. Operating modes

1 X reSTART, Device Select, RW = 1

Figure 6. Write mode sequences with WC = 1 (data write inhibited)

Device operation M24512-W, M24512-R, M24256-BW, M24256-BR

3.6 Write operations

Following a Start condition the bus master sends a Device Select Code with the Read/Write bit (RW) reset to 0. The device acknowledges this, as shown in Figure 7., and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Writing to the memory may be inhibited if Write Control (WC ) is driven High. Any Write instruction with Write Control (WC) driven High (during a period of time from the Start condition until the end of the two address bytes) will not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in Figure 6.. Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant Byte (Table 3.) is sent first, followed by the Least Significant Byte (Table 4.). Bits b15 to b0 form the address of the byte in memory. When the bus master generates a Stop condition immediately after the Ack bit (in the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. After the Stop condition, the delay t W , and the successful completion of a Write operation, the device’s internal address counter is incremented automatically, to point to the next byte address after the last one that was modified. During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests.

3.7 Byte Write

After the Device Select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC ) being driven High, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 7.

3.8 Page Write

The Page Write mode allows up to 64 bytes (for the M24256-BW and M24256-BR) or 128 bytes (for the M24512-W and M24512-R) to be written in a single Write cycle, provided that they are all located in the same ’row’ in the memory: that is, the most significant memory address bits (b15-b6 for the M24256-BW and M24256-BR, and b15-b7 for the M24512-W and M24512-R) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 64 bytes (for the M24256-BW and M24256-BR) or from 1 to 128 bytes (for the M24512-W and M24512-R) of data, each of which is acknowledged by the device if Write Control (WC ) is Low. If Write Control (WC) is High, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck. After each byte is transferred, the internal byte address counter (the 7 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition.

3.9 ECC (Error Correction Code) and Write cycling

reliability is therefore much improved by the use of this feature. benefit from the larger amount of Write cycles. Figure 7. Write Mode sequences with WC

Figure 8. Write Cycle Polling Flowchart using ACK

3.10 Minimizing System De lays by Polling On ACK

can be used by the bus master.

• Initial condition: a Write cycle is in progress.
• Step 1: the bus master issues a Start condition followed by a Device Select Code (the first byte of the new instruction).
• Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). WRITE Cycle in Progress AI01847C Next Operation is Addressing the Memory START Condition DEVICE SELECT with RW = 0 ACK Returned YES NO YESNO ReSTART STOP DATA for the WRITE Operation DEVICE SELECT with RW = 1 Send Address and Receive ACK First byte of instruction with RW = 0 already decoded by the device YESNO START Condition Continue the WRITE Operation Continue the Random READ Operation

M24512-W, M24512-R, M24256-BW, M24256-BR Device operation

3.11 Read Operations

Read operations are performed independently of the state of the Write Control (WC) signal. After the successful completion of a Read operation, the device’s internal address counter is incremented by one, to point to the next byte address.

3.12 Random Address Read

A dummy Write is first performed to load the address into this address counter (as shown in Figure 9.) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the Device Select Code, with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition.

3.13 Current Address Read

For the Current Address Read operation, following a Start condition, the bus master only sends a Device Select Code with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 9., without acknowledging the byte.

3.14 Sequential Read

This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 9. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter ‘rolls-over’, and the device continues to output data from memory address 00h.

Figure 9. Read mode sequences

1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 4th bytes)

3.15 Acknowledge in Read Mode

time, the device terminates the data transfer and switches to its Stand-by mode.

4 Initial delivery state

The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).

5 Maximum rating

Table 6. Absolute maximum ratings

1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)

6 DC and AC parameters

match the measurement conditions when relying on the quoted parameters. Figure 10. AC test measurement I/O waveform Table 7. Operating conditions (M24xxx-W) Table 8. Operating conditions (M24xxx-R) Table 9. AC test measurement conditions

Table 10. Input parameters

1. Sampled only, not 100% tested.
2. E2,E1,E0: Input impedance when the memory is selected (after a Start condition).

Table 11. DC characteristics (M24xxx-W)

1. When the device is selected (after a START condition), the Ei inputs have a different input impedance, as
2. Characterized value, not tested in production.

Table 12. DC characteristics (M24xxx-R)

1. Characterized value, not tested in production.

Table 13. AC characteristics (M24xxx-W, see Table 7 and Table 9)

1. Sampled only, not 100% tested.
2. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the

falling or rising edge of SDA.

1. For a reSTART condition, or following a Write cycle.

Table 14. AC characteristics (M24xxx-R, see Table 8 and Table 9)

1. Sampled only, not 100% tested.
2. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the

falling or rising edge of SDA.

1. For a reSTART condition, or following a Write cycle.

Figure 11. AC Waveforms

7 Package mechanical

Figure 12. SO8W – 8 lead Plastic Small Outline, 208 mils body width, package Table 15. SO8W – 8 lead Plastic Small Outline, 208 mils body width, package

Figure 13. SO8N – 8 lead Plastic Small Outline, 150 mils body width, Package Table 16. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package

Figure 14. TSSOP8 – 8 lead Thin Shrink Small Outline, package outline Table 17. TSSOP8 – 8 lead Thin Shrink Small Outline, package mechanical data

8 Part numbering

of this device, please contact your nearest ST Sales Office. soldering conditions are also marked on the inner box label. Table 18. Ordering information scheme 6 = Industrial temperature range, –40 to 85 °C.

9 Revision history

Table 19. Document revision history Initial delivery state is FFh (not necessarily the same as Erased). Voltage range R (1.8V to 5.5V) also offered. Minor wording changes. Note added to <Blue>Table 11., DC characteristics (M24xxx-W). Power On Reset paragraph specified. changed in <Blue>Table 18., Ordering information scheme. Value versus Bus Parasitic Capacitance (C) for an I2C Bus.

(VCC ). Figure 3: Device Select Code added. M24256-BW and M24256-BR part numbers added. Section 3.9: ECC (Error Correction Code) and Write cycling updated. ICC and ICC1 modified in Table 12: DC characteristics (M24xxx-R). Table 18: Ordering information scheme. Table 19. Document revision history (continued)