M21418

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Document overview

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Technical content

Features

 3G, HD and SD operation (M21428),  HD and SD operation (M21418)  Dual Differential outputs, wi th individual mute control  800 mVp–p single ended output swing (typical)  1600 mVp–p maximum single ended output swing  SD/HD Slew Rate control  2.5 V or 3.3 V Supply  Low P DISS (122 mW @ 2.5 V, 144 mW @ 3.3 V)  Extended temp. range: -10 to 85 °C  RoHS package

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Ordering Information

Part Number Data Rates Supported Package Operating Temperature M21418G-xx* 143–1485 Mbps 3x3 mm MLF—16pins (RoHS compliant) -10 °C to 85 °C M21428G-xx* 143–2970 Mbps 3x3 mm MLF—16pins (RoHS compliant) -10 °C to 85 °C NOTES: * Consult the price list for exact part number when ordering. * The letter ‘G’ designator after the part number indicates a RoHS-compliant package. Refer to www.mindspeed.com for additional information.

Revision History

Revision Level Date Description E Release July 2013 Removed M21408 part. tR/tF maximum in Table 2-7 changed from 180 ps to 135 ps. Added Figure 1-4. Overshoot/Undershoot increased to +/-10% in Table 2-6 and Table 2-7. Removed section on Moisture Sensitivity Level in Section 2.0. D Release May 2007 Modified text in Section 1.1.2 to indicate that RSET must be used. SD/HD changed to pull-up in Table 1-5. C Release February 2007 Updated ordering information. Minor updates to Tables 2-3, 2-6, and 2-7. B Release February 2007 Production Release M21428 added. Characterization data added to Tables 2-3, 2-6, and 2-7. A Advance April 2006 Initial Release.

214x8-DSH-001-E Mindspeed Technologies® 3 Mindspeed Proprietary and Confidential Table of Contents

214x8-DSH-001-E Mindspeed Technologies® 5 Mindspeed Proprietary and Confidential List of Tables

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1.0 Functional Description

1.1 Features

1.1.1 HD-SDI and SD-SDI Slew-rate Selection

The output slew rate of the M21418 and M21428 are selectable to conform with the different SD-SDI and HD-SDI specifications, in the case of the M21428 this includes 3G-SDI. With SD/HD = Low, rise/fall time is typically 100 ps. The slew rate will vary depending on the output matching network and connector used. With SD/HD = High, for standard definition (143 to 540 Mbps) applications, the rise/fall time is typically 600 ps, which is compliant with SMPE 259M and SMPTE 344M.

1.1.2 Output Amplitude Adjustment

For SMPTE compliance, an external 750 Ω ±1% resistor at RSET to AVDD is recommended for a swing level of 800 mV within a tolerance that is less than ±10% which meets SMPTE requirements. The output amplitude can also be adjusted to range from 500 to 1600 mV PP single ended using the following formula: Output Swing = (600/RSET) [RSET in kΩ] (in mVPP, Single Ended) The actual swing is set as a function of the IC supply voltage, the external termination voltage and the limitations are shown in Table 1-1. For a 3.3 V minimum termination voltage, the IC can be SMPTE compliant for all supply voltages. In applications where lossy matching or splitting networks are used, the M21418/M21428 offers additional gain of up to 1600 mVPP swings. When using swings in excess of 1200 mV, there will be an increase in rise and fall times. Table 1-1. Output Swing vs. Supply and Termination Voltage AVDD (V) AVDDTERM (V) Maximum Swing (Single-ended mVp–p) Minimum Swing (Single-ended mVp–p) 2.5–3.3 V 3.3 V 1200 mV 500 mV 2.5–3.3 V 5.0 V 1600 mV 500 mV

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1.2 Pin Definitions

1.2.1 High-speed Inputs

The M21418/M21428 are designed to be operated with input signals as low as 100 mV or up to 2000 mV differential peak to peak. The M21418/M21428 uses external 50 Ω input termination resistors to match 100 Ω differential impedance transmission lines for improved system level performance. The M21418/M21428 recommended input circuits are shown in Figure 1-1. Note that AC-coupling is not required when the M21418/M21428 are driven by Mindspeed Broadcast video devices. Figure 1-1. Typical I nput Circuit—AC-coupled Figure 1-2. Typical Input Circuit—DC-coupled M21418 M21428 Tx Device DDI DDI DDO DDO 100 Ω 4.7 μF 4.7 μF M21418 M21428 Tx Device PCML Output Stage Connected to Same AVDD as Cable Driver DDI DDI DDO DDO 100 Ω

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1.2.2 High-speed Outputs

The M21418/M21428 output buffer is an open collector buffer that is designed for a return loss of 15 dB at SD and HD rates and 10 dB at 3G rates, using standard through-hole BNC connectors as typically employed in broadcast video equipment. A typical output matching circuit is shown in Figure 1-3. The Output Return Loss (ORL) is dependent on many factors such as the value and type of components used, PCB layout, PCB trace lengths, and type of PCB di-electric, therefore, the recommendations in the figure below should be used as starting guidelines only. Different output matching network topologies and different component values will result in different ORL performance. The M21418/M21428 has SD-SDI and HD-SDI rise/fall times that are typically faster than the legacy cable driver devices but within the relevant SMPTE specification for additional margin in most designs. The faster output slew rate results in a more open eye. The actual maximum output of the part depends on the applied IC voltage as well as the external termination voltage for the load termination. The limitations are discussed in Section 1.1. Figure 1-3. Output Matching/Back-termi nation Circuit (Both Outputs Used) Figure 1-4. Output Matching/Back-termina tion Circuit (Only One Output Used) M21418 M21428 SDO SDO AVDD I DD 75 Ω 75 Ω I TERM 10 nF DDTERMAV 4.7 nH 75 Ω 4.7 uF BNC 4.7 nH 75 Ω 4.7 uF BNC M21418 M21428 SDO SDO AVDD I DD 75 Ω 37.5 Ω I TERM 10 nF DDTERMAV 4.7 nH 75 Ω 4.7 uF BNC

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1.2.3 M21418/M21428 Pin List

Table 1-2. Interface Pins Pin Name Pin # Function Default Type RSET 5 Input control signal for setting the single-ended output swing amplitude. Higher output swing levels or reduced variations with a ±1% tolerance external resistor. For 800mVp–p single-ended, a 750 Ω ±1% resistor to AVDD is recommended. — Analog Input Table 1-3. Power Pins Pin Name Pin # Function Type AVSS 3, 8, 15 Chip Ground Power AVDD 2, 7 Positive Supply Power NC 4 Not Connected. Leave these pins floating. Do not connect to any supply, ground or logic level. NC Table 1-4. High-speed Signal Pins Pin Name Pin # Function Default Type DDI/DDI 16, 1 Non-inverting and Inverting serial ext ernally terminated inputs. — I—High-speed SDO2/SDO2 11, 10 Non-inverting and inverting serial untermina ted data outputs to coaxial cable. — O—High-speed SDO1/SDO1 13, 12 Non-inverting and inverting serial untermina ted data outputs to coaxial cable. — O—High-speed Table 1-5. Control Pins Pin Name Pin # Function Default Type MUTE2 6 A high mutes SDO2/SDO2 outputs, low enables SDO2/SDO2. Pull-up I—CMOS MUTE1 14 A high mutes SDO1/SDO1 outputs, low enables SDO1, SDO1. Pull-down I—CMOS SD/HD 9 Input control signal to change the output slew rate. SD/HD = High: Slow output slew rate for SD-SDI rate (143–540 Mbps). SD/HD = Low: Fast output slew rate for HD and 3G-SDI rate. Pull-up I—CMOS NOTES: Internal pull-ups/pull-downs are 100 kΩ.

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2.0 Product Specification

2.1 Absolute Maximum Ratings

2.2 Recommended Operating Conditions

Table 2-1. Absolute Maximum Ratings Symbol Parameter Minimum Maximum Units VDD Power AV SS - 0.5 AV SS + 3.47 V VIOAM Any I/O Pin AV SS - 0.5 AV DD + 0.5 V TSTORE Storage Temperature -65 +150 °C ESDHBML Human Body Model (low-speed) 2000 — V ESDHBMH Human Body Model (high-speed outputs) 2000 — V ESDCDM Charge Device Model 500 — V NOTE: 1. No Damage. Table 2-2. Recommended Operating Conditions Symbol Parameter Notes Minimum Typical Maximum Units AVDD AVDD Power 1 — 2.5/3.3 — V AVSS AVSS Ground — — 0 — V TA Ambient Temperature — -10 — +85 °C θJA Junction to ambient Thermal Resistance 2, 3 — 75 — °C/W AVDD_TERM 75 Ω Output Termination Voltage See Table 1-1. NOTES: 1. ±5% is allowed from nominal supply. 2. Solder exposed underbody paddle with an array of therma l vias to optimize junction to ambient thermal resistance. Refer to Amkor Application Note (see Section A.2.1). 3. Mounted on a multi layer board ( ≥ 4 layers), airflow = 0.0 m/s.

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2.3 DC Electrical Specifications

Table 2-3. Power DC Electrical Specifications Symbol Parameter Notes Minimum Typical Maximum Units IDD Supply Current (one output enabled) 1, 2 — 27 36 mA IDD Supply Current (two outputs enabled) 1, 2 — 48 — mA IDDTERM Current in external termination resistors 1, 2, 3 — 22 — mA PDISSINT1 Power dissipation (AVDD = 2.5 V, AVDDTERM = 3.3 V) 1, 2, 4, 7 — 122 — mW PDISSINT2 Power dissipation (AVDD = 2.5 V, AVDDTERM = 3.3 V) 1, 2, 5, 7 — 156 — mW PDISSINT1 Power dissipation (AVDD = 2.5 V, AVDDTERM = 5.0 V) 1, 2, 4, 7 — 159 — mW PDISSINT2 Power dissipation (AVDD = 2.5 V, AVDDTERM = 5.0 V) 1, 2, 5, 7 — 194 — mW PDISSINT1 Power dissipation (AVDD = 3.3 V, AVDDTERM = 3.3 V) 1, 2, 4, 7 — 144 — mW PDISSINT2 Power dissipation (AVDD = 3.3 V, AVDDTERM = 3.3 V) 1, 2, 5, 7 — 195 — mW PDISSINT1 Power dissipation (AVDD = 3.3 V, AVDDTERM = 5.0 V) 1, 2, 4, 7 — 181 — mW PDISSINT2 Power dissipation (AVDD = 3.3 V, AVDDTERM = 5.0 V) 1, 2, 5, 7 — 232 — mW PDISSTOT1 Power dissipation (AVDD = 2.5 V, AVDDTERM = 3.3 V) 1, 2, 4, 6 — 140 — mW PDISSTOT2 Power dissipation (AVDD = 2.5 V, AVDDTERM = 3.3 V) 1, 2, 5, 6 — 193 — mW PDISSTOT1 Power dissipation (AVDD = 2.5 V, AVDDTERM = 5.0 V) 1, 2, 4, 6 — 177 — mW PDISSTOT2 Power dissipation (AVDD = 2.5 V, AVDDTERM = 5.0 V) 1, 2, 5, 6 — 230 — mW PDISSTOT1 Power dissipation (AVDD = 3.3 V, AVDDTERM = 3.3 V) 1, 2, 4, 6 — 162 — mW PDISSTOT2 Power dissipation (AVDD = 3.3 V, AVDDTERM = 3.3 V) 1, 2, 5, 6 — 231 — mW PDISSTOT1 Power dissipation (AVDD = 3.3 V, AVDDTERM = 5.0 V) 1, 2, 4, 6 — 199 — mW PDISSTOT2 Power dissipation (AVDD = 3.3 V, AVDDTERM = 5.0 V) 1, 2, 5, 6 — 268 — mW NOTES: 1. Recommended operating conditions—see Table 2-2. 2. 800 mV standard SMPTE swing, terminated as in Figure 1-3. 3. A portion of the power will be dissipa ted in the external 75OOhm termination (PEXT = VOD x ITERM). 4. One Output Enabled. 5. Two Outputs Enabled. 6. P DISSTOT = AVDD x IDD + AVDDTERM x ITERM. 7. P DISSINT = PDISSTOT - PEXT.

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2.4 Input/Output Level Specifications

Table 2-4. CMOS Input Electrical Specifications Symbol Parameter Notes Minimum Typical Maximum Units VIH Input Logic High Voltage 1 0.75 x AV DD —A V DD + 0.3 V VIL Input Logic Low Voltage 1 0 — 0.25 x AV DD V IIH Input Current (logic High) 1 -100 — 100 µA IIL Input Current (logic Low) 1 -100 — 100 µA NOTE: 1. Specified at recommended operating condition—see Table 2-2. Table 2-5. High-Speed Input Electrical Specifications Symbol Parameter Notes Minimum Typical Maximum Units DRIN Input Bit Rate (M21418) 1, 2 0 — 1485 Mbps DRIN Input Bit Rate (M21428) 1, 2 0 — 2970 Mbps VID Input Differential Voltage (peak to peak) 1, 3, 4 100 — 2000 mV VCM Input Common-Mode Voltage 1 1200 — AV DD mV VIH Maximum Input High Voltage 1 — — AV DD + 400 mV VIL Minimum Input Low Voltage 1 1.2 — — V RIN Single-ended input impedance 1 — 13.33 20 kΩ NOTES: 1. Specified at recommended operation conditions—see Table 2-2. 2. Part is DC-coupled at the input. 3. Example 1200 mV PP differential = 600 mVPP for each single-ended terminal. 4. Minimum input level defined as BER ≤ 10-12.

214x8-DSH-001-E Mindspeed Technologies® 13 Mindspeed Proprietary and Confidential Table 2-6. Cable Driver Output Electrical Specifications M21418 (SD/HD) Symbol Parameter Notes Minimum Typical Maximum Units DROUT Output Bit Rates 1, 5 — — 1485 Mbps tR/tF SD Rise/Fall Time (20–80%) 1, 3 400 600 800 ps HD Rise/Fall Time (20–80%) 1, 3 — 100 135 ps t R/tfMM Rise/fall mismatch (HD Rate) 1, 2 — 10 30 ps Rise/fall mismatch (SD Rate) 1, 2 — 40 100 ps V OD Single-ended voltage swing range p–p 1, 2, 4, 5 500 800 1600 mV VODTOL Swing Level output variation at 800 mVPP [RSET = 750 Ω ±1%] (Single-Ended) 1, 2, 3 -7 — +7 % VOS Overshoot/Undershoot 1, 2 -10 — +10 % JAOPP Additive Output Jitter (HD rate 1010 pattern) 1, 8 — 20 30 ps Additive Output Jitter (SD rate 1010 pattern) 1, 8 — 40 60 ps DCDO Duty Cycle Distortion (HD Rate) 1, 2, 6, 8 — 15 30 ps Duty Cycle Distortion (SD Rate) 1, 2, 6, 8 — 20 70 ps S 22 Output Return Loss (5 MHz to 1.5 GHz) 1, 2, 7 15 — — dB NOTES: 1. Entire table specified at recommended operating condition with 400 mV P–P differential input—see Table 2-2. 2. Specification verified at 800 mV PP output with 1 m cable on MSPD test board. System results may vary. 3. Rated at nominal SMPTE 800 mV output swing level (using a 750 Ω ±1% resistor at RSET). 4. Output stage is an open collector differential pair, actual sw ing dependant on IC supply voltage and external termination voltage. 5. Into 75 Ω back termination and 75 Ω load and appropriate external termination voltage. 6. Duty Cycle Distortion (D CD) is defined as the difference in the intrinsic jitter at the 50% voltage level and the intrinsic jitter at the rising/falling edge crossing point. If the rising/falling edge crossing point is at the 50% voltage level, then DCD = 0. 7. Measured under DC conditions that simulate AC-coupling, V T = 3.3 V. 8. Measured using a “1010” data pattern.

214x8-DSH-001-E Mindspeed Technologies® 14 Mindspeed Proprietary and Confidential Table 2-7. Cable Driver Output Electrical Specifications M21428 (SD/HD/3G) Symbol Parameter Notes Minimum Typical Maximum Units DROUT Output Bit Rates 1, 5 — — 2970 Mbps tR/tF SD Rise/Fall Time (20–80%) 1, 3, 5 400 600 800 ps HD/3G Rise/Fall Time (20–80%) 1, 3, 5 — 100 135 ps t R/tfMM Rise/fall mismatch (HD/3G Rate) 1, 2, 5 — 10 30 ps Rise/fall mismatch (SD Rate) 1, 2, 5 — 40 100 ps V O Single-ended voltage swing range p–p 1, 2, 4, 5 500 800 1600 mV VOTOL Swing Level output variation at 800 mVPP [RSET = 750 Ω ±1%] (Single-Ended) VOS Overshoot/Undershoot 1, 2, 5 -10 — +10 % JAOPP Additive Output Jitter (HD/3G rate) 1, 5, 8 — 20 30 ps Additive Output Jitter (SD rate) 1, 5, 8 — 40 60 ps DCDO Duty Cycle Distortion (HD/3G Rate) 1, 2, 5, 6, 8 — 15 30 ps Duty Cycle Distortion (SD Rate) 1, 2, 5, 6, 8 — 20 70 ps S 22 Output Return Loss (5 MHz to 1.5 GHz) 1, 2, 5, 7 15 — — dB S22 Output Return Loss (5 MHz to 3.0 GHz) 1, 2, 5, 7 10 — — dB NOTES: 1. Entire table specified at recommended operating condition with 400 mV P–P differential input—see Table 2-2. 2. Specification verified at 800 mV PP output with 1 m cable on MSPD test board. System results may vary. 3. Rated at nominal SMPTE 800 mV output swing level (using a 75 Ω ±1% resistor at RSET). 4. Output stage is an open collector differential pair, actual sw ing dependant on IC supply voltage and external termination voltage. 5. Into 75 Ω back termination and 75 Ω load and appropriate external termination voltage, see Table 1-1, Figure 1-3. 6. Duty Cycle Distortion (D CD) is defined as the difference in the intrinsic jitter at the 50% voltage level and the intrinsic jitter at the rising/falling edge crossing point. If the rising/falling edge crossing point is at the 50% voltage level, then DCD = 0. 7. Measured under DC conditions that simulate AC-coupling, V T = 3.3 V. 8. Measured using a “1010” data pattern.

214x8-DSH-001-E Mindspeed Technologies® 15 Mindspeed Proprietary and Confidential Figure 2-1. Output Symbols Definition VOD tr tf VOH VOL JOPP VOH: Average voltage high level VOL: Average voltage low level VOD: (VOH) – (VOL) VOCM: Common Mode Voltage JOPP: Output Jitter Peak-Peak tr: 20-80% Rise Time tf: 80-20% Fall Time VOCM NOTE: Waveform above is differential.

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2.5 Package Specification

2.5.1 Mechanical Description

2.5.1.1 Package Information

The M21418/M21428 are available in a 16-pin, 3x3 mm MLF IC package. The pin out is shown in Figure 2-2 and the package drawing in Figure 2-3. Figure 2-2. M21418/M21428 Pin Out Top View SDI AVDD AVSS NC SDO1 5 6 7 8 M21418 M21428 16 15 14 13 SD/HD SDO2 SDO2 RSET AVSS MUTE2 AVDD SDI SDO1 AVSS MUTE1

214x8-DSH-001-E Mindspeed Technologies® 17 Mindspeed Proprietary and Confidential Figure 2-3. Package Drawing (3x3 mm MLF Package) 1 Note: View is for a 12 pin package. All dimensions in the tables apply for the 16 pin package 1.50 1.65 1.65 1.501.35 1.35 1. Please see Amkor’s Application Note for PCB footprint (referenced in Section 3.2.1).

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2.6 Manufactureability

The values shown in this section may change; however, these are standard requirements.

2.6.1 Electrostatic Discharge

Tested per JESD22-A114. This device passes 2000 V of ESD Human Body Model (HBM) testing. Tested per JESD22-C101. This device passes 500 V of ESD Charged Device Model (CDM) testing. Tested per EIA/JESD78. This device passes 150 mA of trigger current at 85 °C during Latchup testing.

2.6.2 Peak Reflow Temperature

M21418/M21428G (RoHS compliant package): Peak reflow temperature is 260 °C per JEDEC standards.

2.7 Design Considerations

See Digital Video Interfacing Application Note (212xx-APP-001-A) for guidance on the following:  Component Placement and Layout  Routing Considerations and Thermal Considerations The M21418/M21428 consumes less power than legacy devices, therefore the M21418/M21428 will contribute less thermal energy resulting in a lower operating temperature.

214x8-DSH-001-E Mindspeed Technologies® 19 Mindspeed Proprietary and Confidential Appendix A.1 Glossary of Terms/Acronyms BER Bit Error Rate CD Cable Driver CDA Cable Distribution Amplifier CML Current Mode Logic CMOS Complementary Meta l Oxide Semiconductor DPLL Digital Phase Locked Loop DTV Digital Television DVB Digital Video Broadcast EMI Electro Magnetic Interference EQ Equalizer or Equalization GREEN Environmentally friendly HD High Definition HW Hardware IC Integrated Circuit ID Identifier I/O Input/Output MLF Micro Lead Frame package (also called QFN) PCB Printed Circuit Board ORL Output Return Loss RoHS Restriction of Hazardous Substances SD Standard Definition SDI Serial Digital Input SDO Serial Digital Output SE Single Ended SMPTE Society of Motion Pict ure and Television Engineers

214x8-DSH-001-E Mindspeed Technologies® 20 Mindspeed Proprietary and Confidential A.2 Reference Documents A.2.1 External The following external documents were referenced in this data sheet.  Application Notes for Surface Mount Assembly of Amkor’s MicroLeadFrame (MLF) Packages  Amkor Technology Thermal Test Report TT -00-06 (See http://www.amkor.com for detailed information)  SMPTE 292M, SMPT E 259M, SMPTE 344M  ESI t R101 891 DVB Asynchronous Serial Interface (ASI)

www.mindspeed.com General Information: Telephone: (949) 579-3000 Headquarters - Newport Beach 4000 MacArthur Blvd., East Tower Newport Beach, CA 92660 © 2013 Mindspeed Technologies®, Inc. All rights reserved. Information in this document is provided in connection with Mindspeed Technologies® ("Mindspeed®") products. These materials are provided by Mindspeed as a service to its customers and may be used for informational purposes only. Except as provided in Mindspeed’s Terms and Conditions of Sale for such products or in any separate agreement related to this document, Mindspeed assumes no liability whatsoever. Mindspeed assumes no responsibility for errors or omissions in these materials. Mindspeed may make changes to specifications and product descriptions at any time, without notice. Mindspeed makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its specifications and product descriptions. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE AND/OR USE OF MINDSPEED PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY , OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. MINDSPEED FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. MINDSPEED SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE OF THESE MATERIALS. Mindspeed products are not intended for use in medical, lifesaving or life sustaining applications. Mindspeed customers using or selling Mindspeed products for use in such applications do so at their own risk and agree to fully indemnify Mindspeed for any damages resulting from such improper use or sale. 214x8-DSH-001-E Mindspeed Technologies® 21 Mindspeed Proprietary and Confidential