M21414

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Technical content

Features

 SMPTE/DVB-ASI compliant at SD, HD and 3G (M21424)  SMPTE/DVB-ASI compliant at SD and HD (M21414)  SMPTE/DVB-ASI compliant at SD (M21404)  Dual CML outputs, with se lectable high amplitude  Enable for second CML output  Interchangeable PCB footpr int for all three devices  2.5V or 3.3V Supply  Low Power (175 mW @ 2.5V, 230 mW @ 3.3V)  Extended Temperature range: –10 to 85 °C M21404/M21414/M21424 SD, HD, and 3G Cable Equalizers

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Ordering Information

Part Number Package Operating Data Rate Operating Temperature M21404G-13* 32-pin MLF (RoHS compliant) 143–540 Mbps –10 °C to 85 °C M21414G-13* 32-pin MLF (RoHS compliant) 143–1485 Mbps –10 °C to 85 °C M21424G-13* 32-pin MLF (RoHS compliant) 143–2970 Mbps –10 °C to 85 °C * Consult the price list for exact part number when ordering. * The letter ‘G’ designator after the part number indicates a RoHS-compliant package. Refer to www.mindspeed.com for additional information.

Revision History

Revision Level Date Description D Release March 2010 Revised for -13 part. C Release April 2007 Production release. Correction made to the Functional Block Diagram. Specification changes to Tables 1-3, 1-5, 1-6, and 1-7. B Preliminary February 2007 Combined data sheets for the M21404, M21214 and M21424. Removed 1.8V operation. Removed CLI and MUTE threshold specification. A Advance April 2006 Initial Release.

214x4-DSH-001-D Mindspeed Technologies® 3 Mindspeed Proprietary and Confidential Table of Contents

214x4-DSH-001-D Mindspeed Technologies® 5 Mindspeed Proprietary and Confidential List of Tables

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1.0 Product Specification

1.1 General Specifications

Table 1-1. Absolute Maximum Ratings Symbol Parameter Minimum Maximum Units AVDD Positive Supply AV SS – 0.5 AV SS + 3.6 V VIOAM Any I/O pin AV SS – 0.5 AV DD + 0.5 V TSTORE Storage Temperature – 65 +150 °C ESDHBML Human Body Model (low-speed) 2000 — V ESDHBMH Human Body Model (high-speed) 2000 — V ESDCDM Charge Device Model 500 — V NOTE: 1. No Damage. Table 1-2. Recommended Operating Conditions Symbol Parameter Notes Minimum Typical Maximum Units AVDD Supply Voltage — –5 2.5/3.3 +5 % TAMB Ambient Temperature — –10 — +85 °C θJA Junction to Ambient Thermal Resistance 1, 2 — 40 — °C/W NOTES: 1. Mounted on multi layer board ( ≥ 4 layers). 2. Airflow = 0.0 m/s. Table 1-3. Power DC Electrical Specifications Symbol Parameter Notes Minimum Typical Maximum Units Total IDD Supply Current 1 — 70 90 mA PDISS2.5V Total Power Dissipation (@2.5V) 1, 2, 3 — 175 236 mW PDISS3.3V Total Power Dissipation (@3.3V) 1, 2, 3 — 230 312 mW NOTES: 1. Specified at recommended operating conditions—see Table 1-2. 2. Includes on-chip power dissipation as well as off- chip power dissipated by termination resistors. 3. Typical calculated at nominal supply voltage, maximum calculated at nominal supply voltage + 5%.

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1.2 Input/Output Level Specifications

Table 1-4. CMOS Input Electrical Sp ecifications (Logic Signals Only) Symbol Parameter Notes Minimum Typical Maximum Units VIH Input Logic High Voltage 1 0.75 x AV DD —A V DD + 0.3 V VIL Input Logic Low Voltage 1 0 — 0.25 x AV DD V IIH Input Current (logic high) 1 – 100 — 100 μA IIL Input Current (logic low) 1 – 100 — 100 μA NOTE: 1. Specified at recommended operating conditions—see Table 1-2. Spec is for a max load of 20 pF. Table 1-5. High Speed Input Electrical Specifications Symbol Parameter Notes Minimum Typical Maximum Units DRIN Input Bit Rate (M21404) 1 143 — 540 Mbps Input Bit Rate (M21414) 1 143 — 1485 Mbps Input Bit Rate (M21424) 1 143 — 2970 Mbps V ID Input Voltage Range with 0m of cable, p-p, AVDD = 2.5 or 3.3V 1, 5 700 800 1200 mV VICM Input Common-Mode Voltage (AVDD = 3.3V) 1, 4 — 2.75 — V Input Common-Mode Voltage (AVDD = 2.5V) 1, 4 — 1.95 — V CIN Input capacitance 1, 4 — 0.5 — pF RIN Input resistance 1, 4 — 1.6 — kΩ S11 Input Return Loss (5 MHz to 1.5 GHz) 1, 2, 3 20 30 — dB Input Return Loss (1.5 GHz to 3 GHz) (M21424) 1, 2, 3 — 13 — dB NOTES: 1. Specified at recommended operation conditions—see Table 1-2. 2. Using the recommended input termination shown in Figure 2-1. 3. Measured single ended. 4. Guaranteed by design. 5. This is also the recommended cable launch level (far end).

214x4-DSH-001-D Mindspeed Technologies® 8 Mindspeed Proprietary and Confidential Table 1-6. High Speed Output Electrical Specifications Symbol Parameter Notes Minimum Typical Maximum Units tr/tf Rise/Fall Time (20%–80%), M21404 1, 2, 7 — 500 675 ps Rise/Fall Time (20%–80%), M21414, M21424 1, 2, 7 — 100 120 ps tr/tfmm Rise/Fall Time Mismatch, M21404 1, 2, 7 — 0 70 ps Rise/Fall Time Mismatch, M21414, M21424 1, 2, 7 — 0 30 ps DCD O Duty Cycle Distortion (DCD), M21404 1, 2, 5, 6 — 0 50 ps Duty Cycle Distortion (DCD), M21414, M21424 1, 2, 5, 6 — 0 15 ps V OD Differential Output Voltage p-p HiSwEn = 0 (750mV) 1, 3 600 750 950 mV VOCM Common mode Voltage HiSwEn = 0 (750mV) 1, 3, 4 — AV DD – 0.205 — V VOD Differential Output Voltage p-p HiSwEn = 1 (1050mV) 1, 3 850 1050 1270 mV VOCM Common mode Voltage HiSwEn = 1 (1050mV) 1, 3, 4 — AV DD – 0.290 — V ZO Internal Output Termination Resistance to AVDD 14 0 5 0 6 0 Ω NOTES: 1. Specified at recommended operation conditions—see Table 1-2. 2. With 100 Ω differential termination. 3. With 50 Ω to AVDD termination. 4. Outputs DC-coupled. 5. Duty Cycle Distortion (D CD) is defined as the difference in the intrinsic jitter at the 50% voltage level and the intrinsic jitter at the rising/falling edge crossing point. If the rising/falling edge crossing point is at the 50% voltage level, then DCD = 0. 6. Measured with a 1010 pattern. 7. Measured with a PRBS23 pattern.

214x4-DSH-001-D Mindspeed Technologies® 9 Mindspeed Proprietary and Confidential Figure 1-1. Output Symbols Definition VOD tr tf VOH VOL JOPP VOH: Average voltage high level VOL: Average voltage low level VOD: (VOH) – (VOL) VOCM: Common Mode Voltage JOPP: Output Jitter Peak-Peak tr: 20-80% Rise Time tf: 80-20% Fall Time VOCM NOTE: Waveform above is differential.

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1.3 EQ Specifications

Table 1-7. Cable Equalizer Distance Specifications Symbol Parameter Conditions Notes Minimum Typical Maximum Units LENSD Max Cable Length Belden 1694A 1, 4 — 400 — m Max Cable Length Belden 8281 1, 4 — 300 — m LENHD Max Cable Length Belden 1694A 2, 6 — 200 — m Max Cable Length Belden1694A 2, 5 — 140 — m Max Cable Length Belden 8281 2, 5 — 120 — m LEN 3G Max Cable Length Belden 1694A 3, 7 — 100 — m NOTES: Entire table specified at recommended operating conditions—see Table 1-2. 1. Data Rate = 270 Mbps. 2. Data Rate = 1485 Mbps. 3. Data Rate = 2970 Mbps. 4. Error Free with timing Jitter typically = 0.2 UI, pathological pattern. 5. Error Free with alignment Jitter typically = 0.25 UI, pathological pattern. 6. Error Free with alignment jitter typi cally = 0.3 UI, pathological pattern. 7. Error Free with alignment Jitter typically = 0.35 UI, pathological pattern. Table 1-8. SD /MUTE Specifications Symbol Parameter Notes Minimum Typical Maximum Units VMUT_LO Output voltage when input signal detected 1 — 0.16 x AV DD —V VMUT_HI Output voltage when input signal not detected 1 — 0.95 x AV DD —V NOTE: 1. Specified at recommended operating condition—see Table 1-2.

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1.4 Package Specification

The pin assignment is illustrated in Figure 1-2. The M21404/M21414/M21424 package is RoHS compliant. This package is backwards compatible with the standard soldering techniques as defined in JEDEC-STD-020C (SnPb Process). Figure 1-2. M21404/M21414/M21424 Pin Assignments 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 SDO1 SDO1 NC NC AVSS SDI SDI SDO2_EN SWING_L/H THRESH NC NC EQ_BYP AGC NC NC AV DD CLEN SD/MUTE AVDD AVDD NC M21404/M21414/M21424 x SDO2 SDO2 5 5 32 pin QFN AVSS AVSS AVSS AVDD AVSS AGC NC NC

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1.4.1 Mechanical Description

1.4.1.1 Package Details

The package for the M21404/M21414/M21424 is illustrated in Figure 1-3 below. Please see Amkor’s Application Note for PCB footprint (referenced in the Section A.2.1). Figure 1-3. M21404/M21414/M21424 Packaging Details Note: View is for a 28 pin package. All dimensions in the tables apply for the 32 pin package 3.30 3.30 3.45 3.45 3.15 3.15 0.70 0.90

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1.5 Manufactureability

The values shown in this section may change; however, these are standard requirements.

1.5.1 Electrostatic Discharge

Tested per JESD22-A114. This device passes 2000V of ESD Human Body Model (HBM) testing. Tested per JESD22-C101. This device passes 500V of ESD Charged Device Model (CDM) testing. Tested per EIA/JESD78. This device passes 150mA of trigger current at 85°C during Latchup testing.

1.5.2 Peak Reflow Temperature

M21404G, M21414G, and M21424G (RoHS compliant package): Peak reflow temperature is 260°C per JEDEC standards.

1.5.3 Moisture Sensitivity Level (MSL)

All versions of this device (Std Pb-type and RoHS compliant packages) are Moisture Sensitivity Level (MSL) 3 per J-STD-020B and J-STD-033.

1.6 Design Considerations

See Digital Video Interfacing Application Note (212xx-APP-001-A) for guidance on the following:  Component Placement and Layout  Routing Considerations

1.6.1 Thermal Considerations

The M21404/M21414/M21424 consume less power than legacy devices, therefore they will contribute less thermal energy and should result in a lower operating temperature.

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2.0 Functional Description

2.1 Pin Descriptions

2.1.1 General Nomenclature

Throughout this data sheet, physical pins will be denoted in BOLD print. An array of pins can be called by each

2.1.2 High-Speed Input

Digital video coaxial cables are AC-coupled to the high-speed low-noise inputs, SDI/SDI, which, are designed to operate in both the single-ended or differential mode. The typical application is single-ended into the non-inverting SDI input with the inverting SDI input biased to match the bias on the input used. The M21404/M21414/M21424 do not contain any internal input terminations and require both external input termination as well as the matching circuit to exceed the SMPTE input return loss specifications. The package and IC design of the M21404/M21414/M21424 have been optimized for high-speed performance, allowing them to exceed the SD/HD SMPTE return loss spec by 5 dB to 10 dB, using the recommended external matching/ termination network and commonly employed right-angle, through-hole, or vertical mount 75Ω BNC connectors. For non-inverting single-ended operation, the recommended input circuit is shown in Figure 2-1. For differential operation, the matching/termination circuit on SDI should be duplicated on SDI . The internal pull ups automatically bias SDI/SDI for proper AC coupled operation. Figure 2-1. Single-ended Typical Input Matching/Termination Network 8.2 nH SDI SDI 4.7 μF BNC 4.7 μF 75Ω 37.5Ω 75Ω M21404 M21414 M21424

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2.1.3 High-Speed Outputs

The high-speed CML differential outputs after equalization are made available on the SDO1, SDO1, SDO2, SDO2 pins. By default only the SDO1/SDO1 outputs are enabled, SDO2/ SDO2 are enabled when SDO2_EN = High. Two swing levels are available; 750mV and 1050mV, when SWING_L/H = High, the 1050mV output mode is selected, when SDO2_EN = High, this affects both SDO1 and SDO2.

2.1.4 Adaptive Equalization Selection

In typical operation, the adaptive equalization is enabled with EQ_BYP = Low; however, with EQ_BYP = High, the adaptive equalization and DC restore circuit is bypassed and the input is fed directly to the output.

2.1.5 Cable Length Indicator

When the adaptive equalization is enabled (EQ_BYP = Low), an analog voltage inversely proportional to the cable length is made available on CLEN. The same transfer function applies to all bit rates. When the adaptive equalization is disabled (EQ_BYP = High), the CLEN voltage goes to its highest value (this indicates 0m cable length). During an LOS (Loss Of input Signal) event, the voltage falls to its lowest value.

2.1.6 Output Mute and Signal Detect

When configured as an input by forcing a voltage on SD/MUTE = High (Vdd), the output of the M21404/M21414/ M21424 will be set to logic low (outputs muted). When SD/MUTE = Low (Vss), the output is never muted and the programmable cable length based mute function is disabled. When tied to a high-impedance input or left floating, the programmable inhibit based on signal present is enabled and the pin is defined as an LOS output (logic). In the event of an LOS, the output is muted. The inhibit threshold is set with an analog voltage applied to the THRESH input pin, this threshold will depend on cable type (e.g. Belden 1694A or 8281).

2.1.7 Equalizer Detailed Description

The basic equalizer design consists of interlaced stages of gain and equalization to maximize both the overall equalization gain as well as the input sensitivity for maximum performance with minimum jitter. In order to achieve maximum distance at 270 Mbps, 1485 Mbps and 2970 Mbps with Belden 1694A, the overall equalizer block has over 50 dB of broadband signal boost and maintains an input sensitivity of approximately 10 mV. Since signals are launched with different SMPTE specified rise and fall times which can vary substantially (especially at the receive end after going though a wide dynamic range of valid cable lengths) the equalization routine determines both the bit rate and the resultant signal HF attenuation as opposed to just looking at the launch edge rates. By determining both sets of conditions, it is possible to optimize the equalizer for the different rates. For example, the M21424 maintains the same maximum cable length as optimized SD only equalizers. An SD signal through a short cable can have the same edge rate as a HD signal through a long cable; yet, both conditions require different levels of equalization as well as different optimized inverse-transfer functions. The advanced equalization technology can make the distinction between the two cases for optimal performance. This also leads to proper mute threshold (THRESH) and cable length indicator (CLEN) operation that is independent of the bit rate. In order to accommodate both the SMPTE worst case equalizer pathological patterns as well as some customer derived worst case DC offset patterns, a high-gain slicer is included in the signal path to correct for any eye- crossing wander due to AC coupling of the input. Figure 2-2 shows the test set used by Mindspeed to evaluate the performance of the M21404/M21414/M21424.

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2.2 M21404/M21414/M21424 Common Signals by Interface

Figure 2-2. Test Setup Diagram for Cable Equalizer Evaluation Table 2-1. Power Pins Pin Name Pin Number Function Type AVSS 2, 7, 8, 18, 24 Ground Power AVDD 21, 26, 27, 30 Positive Supply Power Table 2-2. High-speed Signal Pins Pin Name Pin Number Function Type SDI/SDI 3, 4 Non-inverting and Inverting Serial Data Input to the adaptive equalizer I—AC coupled high speed SDO1/SDO1 22, 23 Non-inverting and Inverting Differen tial Serial Data Output O—High speed CML SDO2/SDO2 19, 20 Non-inverting and Inverting Differen tial Serial Data Output O—High speed CML Multi-Rate Video Pattern Generator 75Ω Coaxial Cable M214x4 Cable Equalizer M21428 Cable Driver Multi-Rate Video Monitor

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2.2.1 M21404/M21414/M21424 Pins

Table 2-3. Control/Interface Pins Pin Name Pin Number Function Default Type NC 1 Do not connect to the pin. N/A N/A SDO2_EN 5 Enable Input for SDO2 Outputs: Low = SDO2 output disabled High = SDO2 output enabled Internal pull down I—CMOS SWING_L/H 6 Enable Input for High Swing Output on SDO1/2: Low = 750 mVpp diff. (default) High = 1050 mVpp diff. Internal pull down I—CMOS AGC/AGC 9, 10 External AGC (Automatic Gain Control) capacitor connection points. Use 1.0uF capacitor. Internal pull up Analog EQ_BYP 11 Input control signal that when enabled (High) bypasses the inputs directly to the output stage. Low = Normal operation High = Disables EQ and bypasses input to output Internal pull down I—CMOS NC 12, 13 Do not connect to the pin. N/A N/A THRESH 14 Input control signal voltage. Programmable cable length forced mute threshold. This function is disabled if SD/MUTE = Low Internal pull down Analog NC 15, 16, 17, 25 Do not connect to the pin. N/A N/A SD/MUTE 28 Bidirectional Signal that can be used as an input control signal or as an output status indicator. When configured as an input by forcing a voltage on SD/MUTE = High, the SDO outputs will be inhibited at logic low (outputs muted). See Table 1-4 for levels. When SD/MUTE = Low (Vss), the output is never muted and the programmable cable length based mute function is disabled. When configured as an output (tied to a high-impedance input) or left floating, the programmable inhibit based on cable length is enabled Configured as Output: Low = Input signal detect High = Loss of signal Configured as Input: Low = Never mute High = Force Mute — I/O CLEN 29 Cable length Indicator output — Analog NC 31, 32 Do not connect to the pin. N/A N/A NOTE: Internal pull-up/pull-down is 100 kΩ.

214x4-DSH-001-D Mindspeed Technologies® 18 Mindspeed Proprietary and Confidential Appendix A.1 Glossary of Terms/Acronyms BER Bit Error Rate CD Cable Driver CDA Cable Distribution Amplifier CML Current Mode Logic DDI Differential Data Inputs DTV Digital Television DVB Digital Video Broadcast EMI Electro Magnetic Interference EQ Equalizer or Equalization ESD Electro Static Discharge GREEN Environmentally friendly HD High Definition HW Hardware ID Identifier I/O Input/Output MLF Micro Lead Frame package (also called QFN) RoHS Restriction of Hazardous Substances SD Standard Definition SDI Serial Digital Input SDO Serial Digital Output SE Single Ended SMPTE Society of Motion Pict ure and Television Engineers SW Software

214x4-DSH-001-D Mindspeed Technologies® 19 Mindspeed Proprietary and Confidential A.2 Reference Documents A.2.1 External The following external documents were referenced in this data sheet.  Application Notes for Surface Mount Assembly of Amkor’s QuadFlatNoLead (QFN) Packages  Amkor Technology Thermal Test Report TT -00-06 (See http://www.amkor.com for detailed information)  SMPTE 292, SMPTE 259M, SMPTE 344M, SMPTE424M  ESI TR101 891 DVB Asynchronous Serial Interface (ASI)

www.mindspeed.com General Information: Telephone: (949) 579-3000 Headquarters - Newport Beach 4000 MacArthur Blvd., East Tower Newport Beach, CA 92660 © 2007-2010 Mindspeed Technologies®, Inc. All rights reserved. Information in this document is provided in connection with Mindspeed Technologies® ("Mindspeed®") products. These materials are provided by Mindspeed as a service to its customers and may be used for informational purposes only. Except as provided in Mindspeed’s Terms and Conditions of Sale for such products or in any separate agreement related to this document, Mindspeed assumes no liability whatsoever. Mindspeed assumes no responsibility for errors or omissions in these materials. Mindspeed may make changes to specifications and product descriptions at any time, without notice. Mindspeed makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its specifications and product descriptions. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE AND/OR USE OF MINDSPEED PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY , OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. MINDSPEED FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. MINDSPEED SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE OF THESE MATERIALS. Mindspeed products are not intended for use in medical, lifesaving or life sustaining applications. Mindspeed customers using or selling Mindspeed products for use in such applications do so at their own risk and agree to fully indemnify Mindspeed for any damages resulting from such improper use or sale. 214x4-DSH-001-D Mindspeed Technologies® 20 Mindspeed Proprietary and Confidential