M20948

TDK Electronics

Lowest Power 9-Axis MEMS MotionTracking Device

Manufacturer: TDK Electronics

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World’s Lowest Power 9-Axis MEMS MotionTracking™ Device InvenSense reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. TDK Corporation 1745 Technology Drive, San Jose, CA 95110 U.S.A +1(408) 988–7339 www.invensense.com Document Number: DS-000189 Revision: 1.3 Release Date: 06/02/2017 GENERAL DESCRIPTION The ICM-20948 is the world’s lowest power 9-axis MotionTracking device that is ideally suited for Smartphones, Tablets, Wearable Sensors, and IoT applications.

3-axis gyroscope, 3-axis accelerometer, 3-axis compass, and a Digital Motion Processor™ (DMPTM) in a 3 mm x 3 mm x 1 mm (24-pin QFN) package
DMP offloads computation of motion processing algorithms from the host processor, improving system power performance
Software drivers are fully compliant with Google’s latest Android release
EIS FSYNC support ICM-20948 supports an auxiliary I2C interface to external sensors, on-chip 16-bit ADCs, programmable digital filters, an embedded temperature sensor, and programmable interrupts. The device features an operating voltage range down to 1.71V. Communication ports include I2C and high speed SPI at 7 MHz. Note: ICM-20948 VDDIO range is 1.71V to 1.95V, different than the MPU-9250 9-axis device.

ORDERING INFORMATION

ICM-20948† −40°C to +85°C 24-Pin QFN †Denotes RoHS and Green-Compliant Package BLOCK DIAGRAM

APPLICATIONS

Smartphones and Tablets
Wearable Sensors
IoT Applications

FEATURES

Lowest Power 9-Axis Device at 2.5 mW
3-Axis Gyroscope with Programmable FSR of ±250 dps, ±500 dps, ±1000 dps, and ±2000 dps
3-Axis Accelerometer with Programmable FSR of ±2g, ±4g, ±8g, and ±16g
3-Axis Compass with a wide range to ±4900 µT
Onboard Digital Motion Processor (DMP)
Android support
Auxiliary I2C interface for external sensors
On-Chip 16-bit ADCs and Programmable Filters
7 MHz SPI or 400 kHz Fast Mode I²C
Digital-output temperature sensor
VDD operating range of 1.71V to 3.6V
MEMS structure hermetically sealed and bonded at wafer level
RoHS and Green compliant TYPICAL OPERATING CIRCUIT AUX_CL VDDIO SDO / AD0 REGOUT FSYNC INT1 GND SCL / SCLK nCS RESV VDD SDA / SDI NC 1.71 – 3.6VDC C2, 0.1 µF C3, 0.1 µ F 1.71 – 1.95VDC SCLK SDI AUX_DA SDO C1, 0.1 µF RESV NC NC NC NC NC NC NC NC NC ICM-20948 6 13 nCS

Document Number: DS-000189 Page 2 of 89 Revision: 1.3 TABLE OF CONTENTS

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1 GENERAL DESCRIPTION

1.1 PURPOSE AND SCOPE

This document is a preliminary data sheet, providing a description, specifications, and design related information on the ICM-20948 MotionTracking device. For references to register map and descriptions of individual registers, please refer to the ICM-20948 Register Map and Register Descriptions document.

1.2 PRODUCT OVERVIEW

The ICM-20948 is a multi-chip module (MCM) consisting of two dies integrated into a single QFN package. One die houses a 3-axis gyroscope, a 3-axis accelerometer, and a Digital Motion Processor™ (DMP). The other die h ouses the AK09916 3-axis magnetometer from Asahi Kasei Microdevices Corporation. The ICM -20948 is a 9-axis MotionTracking device all in a small 3x3x1mm QFN package. The device supports th e following features:

FIFO of size 512 bytes (FIFO size will vary depending on DMP feature-set)
Runtime Calibration
Enhanced FSYNC functionality to improve timing for applications l ike EIS ICM-20948 devices, with their 9-axis integration, on-chip DMP, and run-time calibration firmware, enable manufacturers to eliminate the costly and complex selection, qualification, and system level integration of discrete devices, guaranteeing optimal motion performance for consumers. The gyroscope has a programmable full-scale range of ±250 dps, ±500 dps, ±1000 dps, and ±2000 dps. The accelerometer has a user-programmable accelerometer full-scale range of ±2g, ±4g, ±8g, and ±16g. Factory-calibrated initial sensitivity of both sensors reduces production-line calibration requirements. Other key features include on-chip 16-bit ADCs, programmable digital filters, an embedded temperature sensor, and programmable interrupts. The device features I2C and SPI serial interfaces, a VDD operating range of 1.71V to 3.6V, and a separate digital IO supply, VDDIO from 1.71V to 1.95V. Communication with all registers of the device is performed using I2C at up to 100 kHz (standard-mode) or up to 400 kHz (fast-mode), or SPI at up to 7 MHz. By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS wafers with companion CMOS electronics through wafer-level bonding, InvenSense has driven the package size down to a footprint and thickness of 3 mm x 3 mm x 1 mm (24-pin QFN), to provide a very small yet high-performance, low-cost package. The device provides high robustness by supporting 20,000g shock reliability.

1.3 APPLICATIONS

Smartphones and Tablets
Wearable Sensors
IoT Applications
Drones

Document Number: DS-000189 Page 10 of 89 Revision: 1.3

2 FEATURES

2.1 GYROSCOPE FEATURES

The triple-axis MEMS gyroscope in the ICM-20948 includes the following features:

Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with a user-programmable full-scale range of ±250 dps, ±500 dps, ±1000 dps, and ±2000 dps, and integrated 16-bit ADCs
User-selectable ODR; User-selectable low pass filters
Self-test

2.2 ACCELEROMETER FEATURES

The triple-axis MEMS accelerometer in ICM-20948 includes the following features:

Digital-output X-, Y-, and Z-axis accelerometer with a programmable full scale range of ±2g, ±4g, ±8g, and ±16g, and integrated 16-bit ADCs
User-selectable ODR; User-selectable low pass filters
Wake-on-motion interrupt for low power operation of applications processor
Self-test

2.3 MAGNETOMETER FEATURES

The triple-axis MEMS magnetometer in ICM-20948 includes a wide range of features:

3-axis silicon monolithic Hall-effect magnetic sensor with magnetic concentrator
Wide dynamic measurement range and high resolution with lower current consumpt ion.
Output data resolution of 16-bits
Full scale measurement range is ±4900 µT
Self-test function with internal magnetic source to confirm magnetic sensor operation on end products

2.4 DMP FEATURES

The DMP in ICM-20948 includes the following capabilities:

Offloads computation of motion processing algorithms from the host processor. The DMP can be used to minimize power, simplify timing, simplify the software architecture, and save valuable MIPS on the host processor for use in applications.
The DMP enables ultra-low power run-time and background calibration of the accelerometer, gyroscope, and compass, maintaining optimal performance of the sensor data fo r both physical and virtual sensors generated through sensor fusion. This enables the best user experience for all sensor enabled applications for the lifetime of the device.
DMP features simplify the software architecture resulting in quicker time to market.
DMP features are OS, Platform, and Architecture independent, supporting vi rtually any AP, MCU, or other embedded architecture.

2.5 ADDITIONAL FEATURES

The ICM-20948 includes the following additional features:

I2C at up to 100 kHz (standard-mode) or up to 400 kHz (fast-mode) or SPI at up to 7 MHz for communication with registers
Auxiliary master I2C bus for reading data from external sensors (e.g. magnetometer)
Digital-output temperature sensor
20,000g shock tolerant
MEMS structure hermetically sealed and bonded at wafer level
RoHS and Green compliant

3 ELECTRICAL CHARACTERISTICS

3.1 GYROSCOPE SPECIFICATIONS

Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. Table 1. Gyroscope Specifications

Derived from validation or characterization of parts, not guaranteed in production.
Low-noise mode specification.

3.2 ACCELEROMETER SPECIFICATIONS

Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. Table 2. Accelerometer Specifications

Derived from validation or characterization of parts, not guaranteed in production.
Low-noise mode specification.

3.3 MAGNETOMETER SPECIFICATIONS

Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. Table 3. Magnetometer Specifications

Derived from validation or characterization of parts, not guaranteed in production.

3.4 ELECTRICAL SPECIFICATIONS

Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.

8 Hz update rate

Table 4. D.C. Electrical Characteristics

Derived from validation or characterization of parts, not guaranteed in production.

Document Number: DS-000189 Page 14 of 89 Revision: 1.3 A.C. Electrical Characteristics Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES SUPPLIES Supply Ramp Time (TRAMP) Monotonic ramp. Ramp rate is 10% to 90% of the final value. 0.01 20 100 ms 1 TEMPERATURE SENSOR Operating Range Ambient -40 85 °C 1 Sensitivity Untrimmed 333.87 LSB/°C Room Temp Offset 21°C 0 LSB POWER-ON RESET Supply Ramp Time (TRAMP) Valid power-on RESET 0.01 20 100 ms 1 Start-up time for register read/write From power-up 11 100 ms 1 I2C ADDRESS AD0 = 0 AD0 = 1 1101000 1101001 DIGITAL INPUTS (FSYNC, AD0, SCLK, SDI, CS) VIH, High Level Input Voltage 0.7*VDDIO V 1 VIL, Low Level Input Voltage 0.3*VDDIO V CI, Input Capacitance < 10 pF DIGITAL OUTPUT (SDO, INT) VOH, High Level Output Voltage RLOAD=1 MΩ; 0.9*VDDIO V VOL1, LOW-Level Output Voltage RLOAD=1 MΩ; 0.1*VDDIO V VOL.INT1, INT Low-Level Output Voltage OPEN=1, 0.3 mA sink Current 0.1 V Output Leakage Current OPEN=1 100 nA tINT, INT Pulse Width LATCH_INT_EN=0 50 µs I2C I/O (SCL, SDA) VIL, LOW Level Input Voltage -0.5V 0.3*VDDIO V VIH, HIGH-Level Input Voltage 0.7*VDDIO VDDIO + 0.5V V Vhys, Hysteresis 0.1*VDDIO V VOL, LOW-Level Output Voltage 3 mA sink current 0 0.4 V IOL, LOW-Level Output Current VOL=0.4V VOL=0.6V 3 mA mA Output Leakage Current 100 nA tof, Output Fall Time from VIHmax to VILmax Cb bus capacitance in pf 20+0.1C b 250 ns AUXILLIARY I/O (AUX_CL, AUX_DA) VIL, LOW-Level Input Voltage -0.5V 0.3*VDDIO V VIH, HIGH-Level Input Voltage 0.7* VDDIO VDDIO + 0.5V V Vhys, Hysteresis 0.1* VDDIO V VOL1, LOW-Level Output Voltage VDDIO > 2V; 1 mA sink current 0 0.4 V VOL3, LOW-Level Output Voltage VDDIO < 2V; 1 mA sink current 0 0.2* VDDIO V IOL, LOW-Level Output Current VOL = 0.4V VOL = 0.6V mA mA Output Leakage Current 100 nA tof, Output Fall Time from VIHmax to VILmax Cb bus capacitance in pF 20+0.1Cb 250 ns

Table 5. A.C. Electrical Characteristics

Derived from validation or characterization of parts, not guaranteed in production.

Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. Table 6. Other Electrical Specifications

Derived from validation or characterization of parts, not guaranteed in production.

3.5 I2C TIMING CHARACTERIZATION

Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. Table 7. I2C Timing Characteristics

Timing Characteristics apply to both Primary and Auxiliary I2C Bus.
Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets.

Figure 1. I2C Bus Timing Diagram

3.6 SPI TIMING CHARACTERIZATION

Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. Table 8. SPI Timing Characteristics (7 MHz)

Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets

Figure 2. SPI Bus Timing Diagram

3.7 ABSOLUTE MAXIMUM RATINGS

maximum ratings conditions for extended periods may affect device reliability. Table 9. Absolute Maximum Ratings

4 APPLICATIONS INFORMATION

4.1 PIN OUT DIAGRAM AND SIGNAL DESCRIPTION

7 AUX_CL I2C Master serial clock, for connecting to external sensors

8 VDDIO Digital I/O supply voltage

9 AD0 / SDO I2C Slave Address LSB (AD0); SPI serial data output (SDO)

10 REGOUT Regulator filter capacitor connection

12 INT1 Interrupt 1

13 VDD Power supply voltage

18 GND Power supply ground

19 RESV Reserved. Do not connect. 20 RESV Reserved. Connect to GND.

21 AUX_DA I2C master serial data, for connecting to external sensors

23 SCL / SCLK I2C serial clock (SCL); SPI serial clock (SCLK)

24 SDA / SDI I2C serial data (SDA); SPI serial data input (SDI)

Table 10. Signal Descriptions reset is required using the PWR_MGMT_1 register, prior to initialization. Figure 3. Pin out Diagram for ICM-20948 3 mm x 3 mm x 1 mm QFN

4.2 TYPICAL OPERATING CIRCUIT

Figure 4. ICM-20948 Application Schematic (a) I2C operation (b) SPI operation processor from suspend mode. I2C lines are open drain and pullup resistors (e.g. 10 kΩ) are required.

4.3 BILL OF MATERIALS FOR EXTERNAL COMPONENTS

Table 11. Bill of Materials

4.4 EXPOSED DIE PAD PRECAUTIONS

due to package thermo-mechanical stress. There is no electrical connection between the pad a nd the CMOS.

4.5 BLOCK DIAGRAM

Figure 5. ICM-20948 Block Diagram

4.6 OVERVIEW

Three-axis MEMS rate gyroscope sensor with 16-bit ADCs and signal conditioning
Three-axis MEMS accelerometer sensor with 16-bit ADCs and signal conditioning
Three-axis MEMS magnetometer sensor with 16-bit ADCs and signal conditioning
Digital Motion Processor (DMP) engine
Primary I2C and SPI serial communications interfaces
Auxiliary I2C serial interface
Gyroscope, Accelerometer, and Magnetometer Self-Test
Clocking
Sensor Data Registers
FIFO
FSYNC
Interrupts
Digital-Output Temperature Sensor
Bias and LDOs
Charge Pump
Power Modes

Document Number: DS-000189 Page 22 of 89 Revision: 1.3

4.7 THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING

The ICM-20948 consists of three independent vibratory MEMS rate gyroscopes, which detect rotation about the X-, Y-, and Z-Axes. When the gyros are rotated about any of the sense axes, the Coriolis Eff ect causes a vibration that is detected by a capacitive pickoff. The resulting signal is amplified, demodulated, and filtered to produce a voltage that is proportional to the angular rate. This voltage is digitized using individual on-chip 16-bit Analog-to-Digital Converters (ADCs) to sample each axis. The full-scale range of the gyro sensors may be digitally programmed to ±250, ±500, ±1000, or ±2000 degrees per second (dps).

4.8 THREE-AXIS MEMS ACCELEROMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING

The ICM-20948’s 3-Axis accelerometer uses separate proof masses for each axis. Accelerati on along a particular axis induces displacement on the corresponding proof mass, and capacitive sensors detect the displacement diff erentially. The ICM-20948’s architecture reduces the accelerometers’ susceptibility to fabrication variations as well as to thermal drift. When the device is placed on a flat surface, it will measure 0g on the X- and Y-axes and +1g on the Z-axis. The accelerometers’ scale factor is calibrated at the factory and is nominally independent of supply voltage. Each sensor has a dedicated sigma-delta ADC for providing digital outputs. The full scale range of the digital output can be adjusted to ±2g, ±4g, ±8g, or ±16g.

4.9 THREE-AXIS MEMS MAGNETOMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING

The 3-axis magnetometer uses highly sensitive Hall sensor technolo gy. The magnetometer portion of the IC incorporates magnetic sensors for detecting terrestrial magnetism in the X-, Y-, and Z-Axes, a sensor driving circuit, a signal amplifier chain, and an arithmetic circuit for processing the signal from each sensor. Each ADC has a 16-bit resolution and a full scale range of ±4900 µT.

4.10 DIGITAL MOTION PROCESSOR

The embedded Digital Motion Processor (DMP) within the ICM-20948 offloads computation of motion processing algorithms from the host processor. The DMP acquires data from accelerometers, gyroscopes, and additional third party sensors such as magnetometers, and processes the data. The resulting data can be read from the FIFO. The DMP has access to the external pins, which can be used for generating interrupts. The purpose of the DMP is to offload both timing requirements and processing pow er from the host processor. Typically, motion processing algorithms should be run at a high rate, often a round 200 Hz, in order to provide accurate results with low latency. This is required even if the application updates at a much lower rate; for example, a low power user interface may update as slowly as 5 Hz, but the motion processing should still run at 200 Hz. The DMP can be used to minimize power, simplify timing, simplify the software architecture, and save valuable MIPS on the host processor for use in applications.

4.11 PRIMARY I2C AND SPI SERIAL COMMUNICATIONS INTERFACES

The ICM-20948 communicates to a system processor using either a SPI or an I2C serial interface. The ICM-20948 always acts as a slave when communicating to the system processor. The LSB of the of the I2C slave address is set by pin 1 (AD0). ICM-20948 Solution Using I2C Interface In Figure 6, the system processor is an I2C master to the ICM-20948. In addition, the ICM-20948 is an I2C master to the optional external sensor. The ICM-20948 has limited capabilities as an I2C Master, and depends on the system processor to manage the initial configuration of any auxiliary sensors. The ICM-20948 has an interface bypass multiplexer, which connects the system processor I2C bus pins 23 and 24 (SCL and SDA) directly to the auxiliary sensor I2C bus pins 7 and 21 (AUX_CL and AUX_DA).

configuring external sensors (i.e. Figure 6. ICM-20948 Solution Using I2C Interface the external sensor registers.

Figure 7. ICM-20948 Solution Using SPI Interface

4.12 AUXILIARY I2C SERIAL INTERFACE

I2C Master Mode: The ICM-20948 acts as a master to any external sensors connected to the auxiliary I2C bus
Pass-Through Mode: The ICM-20948 directly connects the primary and auxiliary I2C buses together, allowing the system processor to directly communicate with any external sensors. Auxiliary I2C Bus Modes of Operation:
I2C Master Mode: Allows the ICM-20948 to directly access the data registers of external sensors. In this mode, the ICM-20948 directly obtains data from auxiliary sensors without intervention from the system applications processor. The I2C Master can be configured to read up to 24 bytes from up to 4 auxiliary sensors. A fifth sensor can be configured to work single byte read/write mode.
Pass-Through Mode: Allows an external system processor to act as master and directly co mmunicate to the external sensors connected to the auxiliary I2C bus pins (AUX_DA and AUX_CL). In this mode, the auxiliary I2C bus control logic of the ICM-20948 is disabled, and the auxiliary I2C pins AUX_CL and AUX_DA (pins 7 and 21) are connected to the main I2C bus (Pins 23 and 24) through analog switches internally. Pass-Through mode is useful for configuring the external sensors.

4.13 SELF-TEST

measurement axis can be activated by means of the gyroscope and acceleromet er self-test registers. output signal is used to observe the self-test response.

Document Number: DS-000189 Page 25 of 89 Revision: 1.3 The self-test response for each gyroscope axis is defined in the gyroscop e specification table, while that for each accelerometer axis is defined in the accelerometer specification table. When the value of the self-test response is within the specified min/max limits, the part has passed self -test. When the self-test response exceeds the min/max values, the part is deemed to have failed self -test. It is recommended to use InvenSense MotionApps software for executing self-test.

4.14 CLOCKING

The internal system clock sources include: (1) an internal relaxation oscillator, and (2) a PLL with MEMS gyroscope oscillator as the reference clock. With the recommended clock selection setting (CLKSEL = 1), the best clock source for optimum sensor performance and power consumption will be automatically select ed based on the power mode. Specifically, the internal relaxation oscillator will be selected when operating in accelerometer only mode, while the PLL will be selected whenever gyroscope is on, which includes gyroscope and 6-axis modes. As clock accuracy is critical to the preciseness of distance and angle cal culations performed by DMP, it should be noted that the internal relaxation oscillator and PLL show different performan ces in some aspects. The internal relaxation oscillator is trimmed to have a consistent operating frequency at room temperature, while the PLL clock frequency varies from part to part. The PLL frequency deviation from the nominal value in percentage is captured in register TIMEBASE_CORRECTION_PLL (detailed in section 12.5), and users can factor it in during distance and angle calculations to not sacrifice accuracy. Other than that, PLL has better frequency stability and lower frequency variation over temperature than the internal relaxation oscillator.

4.15 SENSOR DATA REGISTERS

The sensor data registers contain the latest gyro, accelerometer, auxiliary sensor, and temperature measurement data. They are read-only registers, and are accessed via the serial interface. Data from these registers may be read anytime.

4.16 FIFO

The ICM-20948 contains a FIFO of size 512 bytes (FIFO size will vary depending on DMP feature-set) that is accessible via the Serial Interface. The FIFO configuration register determines which data is written into the FIFO. Possible choices include gyro data, accelerometer data, temperature readings, auxiliary sensor readings, and FSYNC input. A FIFO counter keeps track of how many bytes of valid data are contained in the F IFO. The FIFO register supports burst reads. The interrupt function may be used to determine when new data is available. For further information regarding the FIFO, please refer to the Section 7.

4.17 FSYNC

The FSYNC pin can be used from an external interrupt source to wake up the device from sleep. It is particularly useful in EIS applications to synchronize the gyroscope ODR with external inputs fro m an imaging sensor. Connecting the VSYNC or HSYNC pin of the image sensor subsystem to FSYNC on ICM-20948 allows timing synchronization between the two otherwise unconnected subsystems. An FSYNC_ODR delay time register is used to capture the delay between an FSYNC pulse and the very next gyroscope data ready pulse.

4.18 INTERRUPTS

Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include the INT pin configuration, the interrupt latching and clearing method, and triggers for the interrupt. Section 5 provides a summary of interrupt sources. The interrupt status can be read from the Interrupt Status register. For further information regarding interrupts, please refer to Section 7.

4.19 DIGITAL-OUTPUT TEMPERATURE SENSOR

ADC can be read from the FIFO or the Sensor Data registers.

4.20 BIAS AND LDOS

Its two inputs are an unregulated VDD and a VDDIO logic reference supply voltage. The LDO output is bypassed

4.21 CHARGE PUMP

An on-chip charge pump generates the high voltage required for the MEMS oscillators.

4.22 POWER MODES

Table 12 lists the user-accessible power modes for ICM-20948.

1 Sleep Mode Off Off Off Off

2 Low-Power Accelerometer Mode Off Duty-Cycled Off On or Off

3 Low-Noise Accelerometer Mode Off On Off On or Off

4 Gyroscope Mode On Off Off On or Off

5 Magnetometer Mode Off Off On On or Off

6 Accel + Gyro Mode On On Off On or Off

7 Accel + Magnetometer Mode Off On On On or Off

Table 12. Power Modes for ICM-20948

5 PROGRAMMABLE INTERRUPTS

Table 13. Interrupt Sources

6 DIGITAL INTERFACE

6.1 I2C AND SPI SERIAL INTERFACES

9 AD0 / SDO I 2C Slave Address LSB (AD0); SPI serial data output (SDO)

Table 14. Serial Interface this bit should be performed immediately after waiting for the time specified by the “Start-Up Time for Register Read/Write” in Section 6.3. For further information regarding the I2C_IF_DIS bit, please refer to Section 7.

6.2 I2C INTERFACE

the master. SDA and SCL lines typically need pull-up resistors to VDD. The maximum bus speed is 400 kHz. other should be b1101001 (pin AD0 is logic high).

6.3 I2C COMMUNICATIONS PROTOCOL

SCL is HIGH (see figure below). Additionally, the bus remains busy if a repeated START (Sr) is generated inste ad of a STOP condition. Figure 8. START and STOP Conditions

and two-byte read sequences.

6.4 I2C TERMS

Table 15. I2C Terms

6.5 SPI INTERFACE

operates as a Slave device during standard Master-Slave SPI operation. are shared among the Slave devices. Each SPI slave device requires its own Chip Select (CS) line from the master.

Data is delivered MSB first and LSB last
Data is latched on the rising edge of SCLK
Data should be transitioned on the falling edge of SCLK
The maximum frequency of SCLK is 7MHz
SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The first byte
Supports Single or Burst Read/Writes.

Figure 11. Typical SPI Master / Slave Configuration

Document Number: DS-000189 Page 32 of 89 Revision: 1.3

7 REGISTER MAP FOR GYROSCOPE AND ACCELEROMETER

The following table lists the register map for the ICM-20948, for user banks 0, 1, 2, 3.

7.1 USER BANK 0 REGISTER MAP

(HEX) ADDR (DEC.) REGISTER NAME SERIAL I/F BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 00 0 WHO_AM_I R WHO_AM_I[7:0] 03 3 USER_CTRL R/W DMP_EN FIFO_EN I2C_MST_EN I2C_IF_DIS DMP_RST SRAM_RST I2C_MST_RST - 05 5 LP_CONFIG R/W I2C_MST_CY CLE ACCEL_CYCLE GYRO_CYCLE - 06 6 PWR_MGMT_1 R/W DEVICE_RESE T SLEEP LP_EN - TEMP_DIS CLKSEL[2:0] 07 7 PWR_MGMT_2 R/W - DISABLE_ACCEL DISABLE_GYRO 0F 15 INT_PIN_CFG R/W INT1_ACTL INT1_OPEN INT1_LATCH_ INT_EN INT_ANYRD_ 2CLEAR ACTL_FSYNC FSYNC_INT_ MODE_EN BYPASS_EN - 10 16 INT_ENABLE R/W REG_WOF_E N - WOM_INT_E N PLL_RDY_EN DMP_INT1_E N I2C_MST_INT _EN 11 17 INT_ENABLE_1 R/W - RAW_DATA_ 0_RDY_EN 12 18 INT_ENABLE_2 R/W - FIFO_OVERFLOW_EN[4:0] 13 19 INT_ENABLE_3 R/W - FIFO_WM_EN[4:0] 17 23 I2C_MST_STATUS R/C PASS_THROU GH I2C_SLV4_DO NE I2C_LOST_AR B I2C_SLV4_NA CK I2C_SLV3_NA CK I2C_SLV2_NA CK I2C_SLV1_NA CK I2C_SLV0_NA CK 19 25 INT_STATUS R/C - WOM_INT PLL_RDY_INT DMP_INT1 I2C_MST_INT 1A 26 INT_STATUS_1 R/C - RAW_DATA_ 0_RDY_INT 1B 27 INT_STATUS_2 R/C - FIFO_OVERFLOW_INT[4:0] 1C 28 INT_STATUS_3 R/C - FIFO_WM_INT[4:0] 28 40 DELAY_TIMEH R DELAY_TIMEH[7:0] 29 41 DELAY_TIMEL R DELAY_TIMEL[7:0] 2D 45 ACCEL_XOUT_H R ACCEL_XOUT_H[7:0] 2E 46 ACCEL_XOUT_L R ACCEL_XOUT_L[7:0] 2F 47 ACCEL_YOUT_H R ACCEL_YOUT_H[7:0] 30 48 ACCEL_YOUT_L R ACCEL_YOUT_L[7:0] 31 49 ACCEL_ZOUT_H R ACCEL_ZOUT_H[7:0] 32 50 ACCEL_ZOUT_L R ACCEL_ZOUT_L[7:0] 33 51 GYRO_XOUT_H R GYRO_XOUT_H[7:0] 34 52 GYRO_XOUT_L R GYRO_XOUT_L[7:0] 35 53 GYRO_YOUT_H R GYRO_YOUT_H[7:0] 36 54 GYRO_YOUT_L R GYRO_YOUT_L[7:0] 37 55 GYRO_ZOUT_H R GYRO_ZOUT_H[7:0] 38 56 GYRO_ZOUT_L R GYRO_ZOUT_L[7:0] 39 57 TEMP_OUT_H R TEMP_OUT_H[7:0] 3A 58 TEMP_OUT_L R TEMP_OUT_L[7:0] 3B 59 EXT_SLV_SENS_DATA_00 R EXT_SLV_SENS_DATA_00[7:0] 3C 60 EXT_SLV_SENS_DATA_01 R EXT_SLV_SENS_DATA_01[7:0] 3D 61 EXT_SLV_SENS_DATA_02 R EXT_SLV_SENS_DATA_02[7:0] 3E 62 EXT_SLV_SENS_DATA_03 R EXT_SLV_SENS_DATA_03[7:0] 3F 63 EXT_SLV_SENS_DATA_04 R EXT_SLV_SENS_DATA_04[7:0] 40 64 EXT_SLV_SENS_DATA_05 R EXT_SLV_SENS_DATA_05[7:0] 41 65 EXT_SLV_SENS_DATA_06 R EXT_SLV_SENS_DATA_06[7:0] 42 66 EXT_SLV_SENS_DATA_07 R EXT_SLV_SENS_DATA_07[7:0] 43 67 EXT_SLV_SENS_DATA_08 R EXT_SLV_SENS_DATA_08[7:0]

Document Number: DS-000189 Page 33 of 89 Revision: 1.3 ADDR (HEX) ADDR (DEC.) REGISTER NAME SERIAL I/F BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 44 68 EXT_SLV_SENS_DATA_09 R EXT_SLV_SENS_DATA_09[7:0] 45 69 EXT_SLV_SENS_DATA_10 R EXT_SLV_SENS_DATA_10[7:0] 46 70 EXT_SLV_SENS_DATA_11 R EXT_SLV_SENS_DATA_11[7:0] 47 71 EXT_SLV_SENS_DATA_12 R EXT_SLV_SENS_DATA_12[7:0] 48 72 EXT_SLV_SENS_DATA_13 R EXT_SLV_SENS_DATA_13[7:0] 49 73 EXT_SLV_SENS_DATA_14 R EXT_SLV_SENS_DATA_14[7:0] 4A 74 EXT_SLV_SENS_DATA_15 R EXT_SLV_SENS_DATA_15[7:0] 4B 75 EXT_SLV_SENS_DATA_16 R EXT_SLV_SENS_DATA_16[7:0] 4C 76 EXT_SLV_SENS_DATA_17 R EXT_SLV_SENS_DATA_17[7:0] 4D 77 EXT_SLV_SENS_DATA_18 R EXT_SLV_SENS_DATA_18[7:0] 4E 78 EXT_SLV_SENS_DATA_19 R EXT_SLV_SENS_DATA_19[7:0] 4F 79 EXT_SLV_SENS_DATA_20 R EXT_SLV_SENS_DATA_20[7:0] 50 80 EXT_SLV_SENS_DATA_21 R EXT_SLV_SENS_DATA_21[7:0] 51 81 EXT_SLV_SENS_DATA_22 R EXT_SLV_SENS_DATA_22[7:0] 52 82 EXT_SLV_SENS_DATA_23 R EXT_SLV_SENS_DATA_23[7:0] 66 102 FIFO_EN_1 R/W - SLV_3_FIFO_ EN SLV_2_FIFO_ EN SLV_1_FIFO_ EN SLV_0_FIFO_ EN 67 103 FIFO_EN_2 R/W - ACCEL_FIFO_ EN GYRO_Z_FIF O_EN GYRO_Y_FIF O_EN GYRO_X_FIF O_EN TEMP_FIFO_ EN 68 104 FIFO_RST R/W - FIFO_RESET[4:0] 69 105 FIFO_MODE R/W - FIFO_MODE[4:0] 70 112 FIFO_COUNTH R - FIFO_CNT[12:8] 71 113 FIFO_COUNTL R FIFO_CNT[7:0] 72 114 FIFO_R_W R/W FIFO_R_W[7:0] 74 116 DATA_RDY_STATUS R/C WOF_STATU S - RAW_DATA_RDY[3:0] 76 118 FIFO_CFG R/W - FIFO_CFG 7F 127 REG_BANK_SEL R/W - USER_BANK[1:0] -

7.2 USER BANK 1 REGISTER MAP

(Hex) Addr (Dec.) Register Name Serial I/F Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 02 2 SELF_TEST_X_GYRO R/W XG_ST_DATA[7:0] 03 3 SELF_TEST_Y_GYRO R/W YG_ST_DATA[7:0] 04 4 SELF_TEST_Z_GYRO R/W ZG_ST_DATA[7:0] 0E 14 SELF_TEST_X_ACCEL R/W XA_ST_DATA[7:0] 0F 15 SELF_TEST_Y_ACCEL R/W YA_ST_DATA[7:0] 10 16 SELF_TEST_Z_ACCEL R/W ZA_ST_DATA[7:0] 14 20 XA_OFFS_H R/W XA_OFFS[14:7] 15 21 XA_OFFS_L R/W XA_OFFS[6:0] - 17 23 YA_OFFS_H R/W YA_OFFS[14:7] 18 24 YA_OFFS_L R/W YA_OFFS[6:0] - 1A 26 ZA_OFFS_H R/W ZA_OFFS[14:7] 1B 27 ZA_OFFS_L R/W ZA_OFFS[6:0] -

Document Number: DS-000189 Page 34 of 89 Revision: 1.3 Addr (Hex) Addr (Dec.) Register Name Serial I/F Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 28 40 TIMEBASE_CORRECTIO N_PLL R/W TBC_PLL[7:0] 7F 127 REG_BANK_SEL R/W - USER_BANK[1:0] -

7.3 USER BANK 2 REGISTER MAP

(HEX) ADDR (DEC.) REGISTER NAME SERIAL I/F BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 00 0 GYRO_SMPLRT_DIV R/W GYRO_SMPLRT_DIV[7:0] 01 1 GYRO_CONFIG_1 R/W - GYRO_DLPFCFG[2:0] GYRO_FS_SEL[1:0] GYRO_FCHOI CE 02 2 GYRO_CONFIG_2 R/W - XGYRO_CTEN YGYRO_CTEN ZGYRO_CTEN GYRO_AVGCFG[2:0] 03 3 XG_OFFS_USRH R/W X_OFFS_USER[15:8] 04 4 XG_OFFS_USRL R/W X_OFFS_USER[7:0] 05 5 YG_OFFS_USRH R/W Y_OFFS_USER[15:8] 06 6 YG_OFFS_USRL R/W Y_OFFS_USER[7:0] 07 7 ZG_OFFS_USRH R/W Z_OFFS_USER[15:8] 08 8 ZG_OFFS_USRL R/W Z_OFFS_USER[7:0] 09 9 ODR_ALIGN_EN R/W - ODR_ALIGN_ EN 10 16 ACCEL_SMPLRT_DIV_1 R/W - ACCEL_SMPLRT_DIV[11:8] 11 17 ACCEL_SMPLRT_DIV_2 R/W ACCEL_SMPLRT_DIV[7:0] 12 18 ACCEL_INTEL_CTRL R/W - ACCEL_INTEL _EN ACCEL_INTEL _MODE_INT 13 19 ACCEL_WOM_THR R/W WOM_THRESHOLD[7:0] 14 20 ACCEL_CONFIG R/W - ACCEL_DLPFCFG[2:0] ACCEL_FS_SEL[1:0] ACCEL_FCHOI CE 15 21 ACCEL_CONFIG_2 R/W - AX_ST_EN_R EG AY_ST_EN_R EG AZ_ST_EN_R EG DEC3_CFG[1:0] 52 82 FSYNC_CONFIG R/W DELAY_TIME _EN - WOF_DEGLIT CH_EN WOF_EDGE_I NT EXT_SYNC_SET[3:0] 53 83 TEMP_CONFIG R/W - TEMP_DLPFCFG[2:0] 54 84 MOD_CTRL_USR R/W - REG_LP_DMP _EN 7F 127 REG_BANK_SEL R/W - USER_BANK[1:0] -

7.4 USER BANK 3 REGISTER MAP

(HEX) ADDR (DEC.) REGISTER NAME SERIAL I/F BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 00 0 I2C_MST_ODR_CONFIG R/W - I2C_MST_ODR_CONFIG[3:0] 01 1 I2C_MST_CTRL R/W MULT_MST_ EN - I2C_MST_P_ NSR I2C_MST_CLK[3:0] 02 2 I2C_MST_DELAY_CTRL R/W DELAY_ES_S HADOW - I2C_SLV4_DE LAY_EN I2C_SLV3_DE LAY_EN I2C_SLV2_DE LAY_EN I2C_SLV1_DE LAY_EN I2C_SLV0_DE LAY_EN 03 3 I2C_SLV0_ADDR R/W I2C_SLV0_RN W I2C_ID_0[6:0] 04 4 I2C_SLV0_REG R/W I2C_SLV0_REG[7:0] 05 5 I2C_SLV0_CTRL R/W I2C_SLV0_EN I2C_SLV0_BY TE_SW I2C_SLV0_RE G_DIS I2C_SLV0_GR P I2C_SLV0_LENG[3:0] 06 6 I2C_SLV0_DO R/W I2C_SLV0_DO[7:0] 07 7 I2C_SLV1_ADDR R/W I2C_SLV1_RN W I2C_ID_1[6:0] 08 8 I2C_SLV1_REG R/W I2C_SLV1_REG[7:0] 09 9 I2C_SLV1_CTRL R/W I2C_SLV1_EN I2C_SLV1_BY TE_SW I2C_SLV1_RE G_DIS I2C_SLV1_GR P I2C_SLV1_LENG[3:0]

Document Number: DS-000189 Page 35 of 89 Revision: 1.3 ADDR (HEX) ADDR (DEC.) REGISTER NAME SERIAL I/F BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 0A 10 I2C_SLV1_DO R/W I2C_SLV1_DO[7:0] 0B 11 I2C_SLV2_ADDR R/W I2C_SLV2_RN W I2C_ID_2[6:0] 0C 12 I2C_SLV2_REG R/W I2C_SLV2_REG[7:0] 0D 13 I2C_SLV2_CTRL R/W I2C_SLV2_EN I2C_SLV2_BY TE_SW I2C_SLV2_RE G_DIS I2C_SLV2_GR P I2C_SLV2_LENG[3:0] 0E 14 I2C_SLV2_DO R/W I2C_SLV2_DO[7:0] 0F 15 I2C_SLV3_ADDR R/W I2C_SLV3_RN W I2C_ID_3[6:0] 10 16 I2C_SLV3_REG R/W I2C_SLV3_REG[7:0] 11 17 I2C_SLV3_CTRL R/W I2C_SLV3_EN I2C_SLV3_BY TE_SW I2C_SLV3_RE G_DIS I2C_SLV3_GR P I2C_SLV3_LENG[3:0] 12 18 I2C_SLV3_DO R/W I2C_SLV3_DO[7:0] 13 19 I2C_SLV4_ADDR R/W I2C_SLV4_RN W I2C_ID_4[6:0] 14 20 I2C_SLV4_REG R/W I2C_SLV4_REG[7:0] 15 21 I2C_SLV4_CTRL R/W I2C_SLV4_EN I2C_SLV4_BY TE_SW I2C_SLV4_RE G_DIS I2C_SLV4_DLY[4:0] 16 22 I2C_SLV4_DO R/W I2C_SLV4_DO[7:0] 17 23 I2C_SLV4_DI R I2C_SLV4_DI[7:0] 7F 127 REG_BANK_SEL R/W - USER_BANK[1:0] -

Document Number: DS-000189 Page 36 of 89 Revision: 1.3

8 USER BANK 0 REGISTER DESCRIPTIONS

This section describes the function and contents of the User Bank 0 Register Map within the ICM-20948. NOTE: The device will come up in sleep mode upon power-up.

8.1 WHO_AM_I

Name: WHO_AM_I Address: 0 (00h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0xEA BIT NAME FUNCTION 7:0 WHO_AM_I[7:0] Register to indicate to user which device is being accessed. The value for ICM-20948 is 0xEA.

8.2 USER_CTRL

Name: USER_CTRL Address: 3 (03h) Type: USR0 Bank: 0 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7 DMP_EN 1 – Enables DMP features. 0 – DMP features are disabled after the current processing round has completed. 6 FIFO_EN 1 – Enable FIFO operation mode. 0 – Disable FIFO access from serial interface. To disable FIFO writes by DMA, use FIFO_EN register. To disable possible FIFO writes from DMP, disable the DMP.

5 I2C_MST_EN 1 – Enable the I2C Master I/F module; pins ES_DA and ES_SCL are isolated from pins

SDA/SDI and SCL/ SCLK. 0 – Disable I2C Master I/F module; pins ES_DA and ES_SCL are logically driven by pins SDA/SDI and SCL/ SCLK. 4 I2C_IF_DIS 1 – Reset I2C Slave module and put the serial interface in SPI mode only. 3 DMP_RST 1 – Reset DMP module. Reset is asynchronous. This bit auto clears after one clock cycle of the internal 20 MHz clock. 2 SRAM_RST 1 – Reset SRAM module. Reset is asynchronous. This bit auto clears after one clock cycle of the internal 20 MHz clock. 1 I2C_MST_RST 1 – Reset I2C Master module. Reset is asynchronous. This bit auto clears after one clock cycle of the internal 20 MHz clock. NOTE: This bit should only be set when the I2C master has hung. If this bit is set during an active I2C master transaction, the I2C slave will hang, which will require the host to reset the slave. 0 - Reserved.

Document Number: DS-000189 Page 37 of 89 Revision: 1.3

8.3 LP_CONFIG

Name: LP_CONFIG Address: 5 (05h) Type: USR0 Bank: 0 Serial IF: R/W Reset Value: 0x40 BIT NAME FUNCTION 7 - Reserved. 6 I2C_MST_CYCLE 1 - Operate I2C master in duty cycled mode. ODR is determined by I2C_MST_ODR_CONFIG register. 0 – Disable I2C master duty cycled mode. 5 ACCEL_CYCLE 1 – Operate ACCEL in duty cycled mode. ODR is determined by ACCEL_SMPLRT_DIV register. 0 – Disable ACCEL duty cycled mode. 4 GYRO_CYCLE 1 – Operate GYRO in duty cycled mode. ODR is determined by GYRO_SMPLRT_DIV register. 0 – Disable GYRO duty cycled mode. 3:0 - Reserved.

8.4 PWR_MGMT_1

Name: PWR_MGMT_1 Address: 6 (06h) Type: USR0 Bank: 0 Serial IF: R/W Reset Value: 0x41 BIT NAME FUNCTION 7 DEVICE_RESET 1 – Reset the internal registers and restores the default settings. Write a 1 to set the reset, the bit will auto clear. 6 SLEEP When set, the chip is set to sleep mode (in sleep mode all analog is powered off). Clearing the bit wakes the chip from sleep mode.

5 LP_EN The LP_EN only affects the digital circuitry, it helps to reduce the digital current when

sensors are in LP mode. Please note that the sensors themselves are set in LP mode by the LP_CONFIG register settings. Sensors in LP mode, and use of LP_EN bit together help to reduce overall current. The bit settings are: 1: Turn on low power feature. 0: Turn off low power feature. LP_EN has no effect when the sensors are in low-noise mode. 4 - Reserved. 3 TEMP_DIS When set to 1, this bit disables the temperature sensor. 2:0 CLKSEL[2:0] Code: Clock Source 0: Internal 20 MHz oscillator 1-5: Auto selects the best available clock source – PLL if ready, else use the Internal oscillator 6: Internal 20 MHz oscillator 7: Stops the clock and keeps timing generator in reset NOTE: CLKSEL[2:0] should be set to 1~5 to achieve full gyroscope performance.

Document Number: DS-000189 Page 38 of 89 Revision: 1.3

8.5 PWR_MGMT_2

Name: PWR_MGMT_2 Address: 7 (07h) Type: USR0 Bank: 0 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:6 - Reserved. 5:3 DISABLE_ACCEL Only the following values are applicable: 111 – Accelerometer (all axes) disabled. 000 – Accelerometer (all axes) on. 2:0 DISABLE_GYRO Only the following values are applicable: 111 – Gyroscope (all axes) disabled. 000 – Gyroscope (all axes) on.

8.6 INT_PIN_CFG

Name: INT_PIN_CFG Address: 15 (0Fh) Type: USR0 Bank: 0 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7 INT1_ACTL 1 – The logic level for INT1 pin is active low. 0 – The logic level for INT1 pin is active high. 6 INT1_OPEN 1 – INT1 pin is configured as open drain. 0 – INT1 pin is configured as push-pull. 5 INT1_LATCH__EN 1 – INT1 pin level held until interrupt status is cleared. 0 – INT1 pin indicates interrupt pulse is width 50 µs.

4 INT_ANYRD_2CLEAR 1 – Interrupt status in INT_STATUS is cleared (set to 0) if any read operation is

performed. 0 – Interrupt status in INT_STATUS is cleared (set to 0) only by reading INT_STATUS register. This bit only affects the interrupt status bits that are contained in the register INT_STATUS, and the corresponding hardware interrupt. This bit does not affect the interrupt status bits that are contained in registers INT_STATUS_1, INT_STATUS_2, INT_STATUS_3, and the corresponding hardware interrupt. 3 ACTL_FSYNC 1 – The logic level for the FSYNC pin as an interrupt to the ICM-20948 is active low. 0 – The logic level for the FSYNC pin as an interrupt to the ICM-20948 is active high. 2 FSYNC_INT_MODE_EN 1 – This enables the FSYNC pin to be used as an interrupt. A transition to the active level described by the ACTL_FSYNC bit will cause an interrupt. The status of the interrupt is read in the I2C Master Status register PASS_THROUGH bit. 0 – This disables the FSYNC pin from causing an interrupt.

1 BYPASS_EN When asserted, the I2C_MASTER interface pins (ES_CL and ES_DA) will go into

‘bypass mode’ when the I 2C master interface is disabled. 0 - Reserved.

Document Number: DS-000189 Page 39 of 89 Revision: 1.3

8.7 INT_ENABLE

Name: INT_ENABLE Address: 16 (10h) Type: USR0 Bank: 0 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7 REG_WOF_EN 1 – Enable wake on FSYNC interrupt. 0 – Function is disabled. 6:4 - Reserved. 3 WOM_INT_EN 1 – Enable interrupt for wake on motion to propagate to interrupt pin 1. 0 – Function is disabled.

2 PLL_RDY_EN 1 – Enable PLL RDY interrupt (PLL RDY means PLL is running and in use as the clock

source for the system) to propagate to interrupt pin 1. 0 – Function is disabled. 1 DMP_INT1_EN 1 – Enable DMP interrupt to propagate to interrupt pin 1. 0 – Function is disabled. 0 I2C_MST_INT_EN 1 – Enable I2C master interrupt to propagate to interrupt pin 1. 0 – Function is disabled.

8.8 INT_ENABLE_1

Name: INT_ENABLE_1 Address: 17 (11h) Type: USR0 Bank: 0 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:1 - Reserved.

0 RAW_DATA_0_RDY_EN 1 – Enable raw data ready interrupt from any sensor to propagate to interrupt

pin 1. 0 – Function is disabled.

8.9 INT_ENABLE_2

Name: INT_ENABLE_2 Address: 18 (12h) Type: USR0 Bank: 0 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:5 - Reserved. 4:0 FIFO_OVERFLOW_EN[4:0] 1 – Enable interrupt for FIFO overflow to propagate to interrupt pin 1. 0 – Function is disabled.

Document Number: DS-000189 Page 40 of 89 Revision: 1.3

8.10 INT_ENABLE_3

Name: INT_ENABLE_3 Address: 19 (13h) Type: USR0 Bank: 0 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:5 - Reserved. 4:0 FIFO_WM_EN[4:0] 1 – Enable interrupt for FIFO watermark to propagate to interrupt pin 1. 0 – Function is disabled.

8.11 I2C_MST_STATUS

Name: I2C_MST_STATUS Address: 23 (17h) Type: USR0 Bank: 0 Serial IF: R/C Reset Value: 0x00 BIT NAME FUNCTION

7 PASS_THROUGH Status of FSYNC interrupt – used as a way to pass an external interrupt through this

chip to the host. If enabled in the INT_PIN_CFG register by asserting bit FSYNC_INT_MODE_EN, this will cause an interrupt. A read of this register clears all status bits in this register.

6 I2C_SLV4_DONE Asserted when I2C slave 4’s transfer is complete, will cause an interrupt if bit

I2C_MST_INT_EN in the INT_ENABLE register is asserted, and if the SLV4_DONE_INT_EN bit is asserted in the I2C_SLV4_CTRL register.

5 I2C_LOST_ARB Asserted when I2C slave loses arbitration of the I2C bus, will cause an interrupt if bit

I2C_MST_INT_EN in the INT_ENABLE register is asserted.

4 I2C_SLV4_NACK Asserted when slave 4 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN

in the INT_ENABLE register is asserted.

3 I2C_SLV3_NACK Asserted when slave 3 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN

in the INT_ENABLE register is asserted.

2 I2C_SLV2_NACK Asserted when slave 2 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN

in the INT_ENABLE register is asserted.

1 I2C_SLV1_NACK Asserted when slave 1 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN

in the INT_ENABLE register is asserted.

0 I2C_SLV0_NACK Asserted when slave 0 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN

in the INT_ENABLE register is asserted.

8.12 INT_STATUS

Name: INT_STATUS Address: 25 (19h) Type: USR0 Bank: 0 Serial IF: R/C Reset Value: 0x00 BIT NAME FUNCTION 7:4 - Reserved. 3 WOM_INT 1 – Wake on motion interrupt occurred. 2 PLL_RDY_INT 1 – Indicates that the PLL has been enabled and is ready (delay of 4 ms ensures lock). 1 DMP_INT1 1 – Indicates the DMP has generated INT1 interrupt. 0 I2C_MST_INT 1 – Indicates I2C master has generated an interrupt.

Document Number: DS-000189 Page 41 of 89 Revision: 1.3

8.13 INT_STATUS_1

Name: INT_STATUS_1 Address: 26 (1Ah) Type: USR0 Bank: 0 Serial IF: R/C Reset Value: 0x00 BIT NAME FUNCTION 7:1 - Reserved. 0 RAW_DATA_0_RDY_INT 1 – Sensor Register Raw Data, from all sensors, is updated and ready to be read.

8.14 INT_STATUS_2

Name: INT_STATUS_2 Address: 27 (1Bh) Type: USR0 Bank: 0 Serial IF: R/C Reset Value: 0x00 BIT NAME FUNCTION 7:5 - Reserved. 4:0 FIFO_OVERFLOW_INT[4:0] 1 – FIFO Overflow interrupt occurred.

8.15 INT_STATUS_3

Name: INT_STATUS_3 Address: 28 (1Ch) Type: USR0 Bank: 0 Serial IF: R/C Reset Value: 0x00 BIT NAME FUNCTION 7:5 - Reserved. 4:0 FIFO_WM_INT[4:0] 1 – Watermark interrupt for FIFO occurred.

8.16 DELAY_TIMEH

Name: DELAY_TIMEH Address: 40 (28h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 DELAY_TIMEH[7:0] High-byte of delay time between FSYNC event and the 1st gyro ODR event (after the FSYNC event). Reading DELAY_TIMEH will lock DELAY_TIMEH and DELAY_TIMEL from the next update. Reading DELAY_TIMEL will unlock DELAY_TIMEH and DELAY_TIMEL to take the next update due to an FSYNC event.

Document Number: DS-000189 Page 42 of 89 Revision: 1.3

8.17 DELAY_TIMEL

Name: DELAY_TIMEL Address: 41 (29h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 DELAY_TIMEL[7:0] Low-byte of delay time between FSYNC event and the 1st gyro ODR event (after the FSYNC event). Reading DELAY_TIMEH will lock DELAY_TIMEH and DELAY_TIMEL from the next update. Reading DELAY_TIMEL will unlock DELAY_TIMEH and DELAY_TIMEL to take the next update due to an FSYNC event. Delay time in µs = (DELAY_TIMEH * 256 + DELAY_TIMEL) * 0.9645

8.18 ACCEL_XOUT_H

Name: ACCEL_XOUT_H Address: 45 (2Dh) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 ACCEL_XOUT_H[7:0] High Byte of Accelerometer X-axis data.

8.19 ACCEL_XOUT_L

Name: ACCEL_XOUT_L Address: 46 (2Eh) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 ACCEL_XOUT_L[7:0] Low Byte of Accelerometer X-axis data. To convert the output of the accelerometer to acceleration measurement use the formula below: X_acceleration = ACCEL_XOUT/Accel_Sensitivity

8.20 ACCEL_YOUT_H

Name: ACCEL_YOUT_H Address: 47 (2Fh) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 ACCEL_YOUT_H[7:0] High Byte of Accelerometer Y-axis data.

Document Number: DS-000189 Page 43 of 89 Revision: 1.3

8.21 ACCEL_YOUT_L

Name: ACCEL_YOUT_L Address: 48 (30h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 ACCEL_YOUT_L[7:0] Low Byte of Accelerometer Y-axis data. To convert the output of the accelerometer to acceleration measurement use the formula below: Y_acceleration = ACCEL_YOUT/Accel_Sensitivity

8.22 ACCEL_ZOUT_H

Name: ACCEL_ZOUT_H Address: 49 (31h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 ACCEL_ZOUT_H[7:0] High Byte of Accelerometer Z-axis data.

8.23 ACCEL_ZOUT_L

Name: ACCEL_ZOUT_L Address: 50 (32h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 ACCEL_ZOUT_L[7:0] Low Byte of Accelerometer Z-axis data. To convert the output of the accelerometer to acceleration measurement use the formula below: Z_acceleration = ACCEL_ZOUT/Accel_Sensitivity

8.24 GYRO_XOUT_H

Name: GYRO_XOUT_H Address: 51 (33h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 GYRO_XOUT_H[7:0] High Byte of Gyroscope X-axis data.

Document Number: DS-000189 Page 44 of 89 Revision: 1.3

8.25 GYRO_XOUT_L

Name: GYRO_XOUT_L Address: 52 (34h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 GYRO_XOUT_L[7:0] Low Byte of Gyroscope X-axis data. To convert the output of the gyroscope to angular rate measurement use the formula below: X_angular_rate = GYRO_XOUT/Gyro_Sensitivity

8.26 GYRO_YOUT_H

Name: GYRO_YOUT_H Address: 53 (35h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 GYRO_YOUT_H[7:0] High Byte of Gyroscope Y-axis data.

8.27 GYRO_YOUT_L

Name: GYRO_YOUT_L Address: 54 (36h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 GYRO_YOUT_L[7:0] Low Byte of Gyroscope Y-axis data. To convert the output of the gyroscope to angular rate measurement use the formula below: Y_angular_rate = GYRO_YOUT/Gyro_Sensitivity

8.28 GYRO_ZOUT_H

Name: GYRO_ZOUT_H Address: 55 (37h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 GYRO_ZOUT_H[7:0] High Byte of Gyroscope Z-axis data.

Document Number: DS-000189 Page 45 of 89 Revision: 1.3

8.29 GYRO_ZOUT_L

Name: GYRO_ZOUT_L Address: 56 (38h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 GYRO_ZOUT_L[7:0] Low Byte of Gyroscope Z-axis data. To convert the output of the gyroscope to angular rate measurement use the formula below: Z_angular_rate = GYRO_ZOUT/Gyro_Sensitivity

8.30 TEMP_OUT_H

Name: TEMP_OUT_H Address: 57 (39h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 TEMP_OUT_H[7:0] High Byte of Temp sensor data.

8.31 TEMP_OUT_L

Name: TEMP_OUT_L Address: 58 (3Ah) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 TEMP_OUT_L[7:0] Low Byte of Temp sensor data. To convert the output of the temperature sensor to degrees C use the following formula: TEMP_degC = ((TEMP_OUT – RoomTemp_Offset)/Temp_Sensitivity) + 21degC

8.32 EXT_SLV_SENS_DATA_00

Name: EXT_SLV_SENS_DATA_00 Address: 59 (3Bh) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 EXT_SLV_SENS_DATA_00[7:0] Sensor data read from external I2C devices via the I2C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- 4)_CTRL registers.

Document Number: DS-000189 Page 46 of 89 Revision: 1.3

8.33 EXT_SLV_SENS_DATA_01

Name: EXT_SLV_SENS_DATA_01 Address: 60 (3Ch) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 EXT_SLV_SENS_DATA_01[7:0] Sensor data read from external I2C devices via the I2C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- 4)_CTRL registers.

8.34 EXT_SLV_SENS_DATA_02

Name: EXT_SLV_SENS_DATA_02 Address: 61 (3Dh) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 EXT_SLV_SENS_DATA_02[7:0] Sensor data read from external I2C devices via the I2C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- 4)_CTRL registers.

8.35 EXT_SLV_SENS_DATA_03

Name: EXT_SLV_SENS_DATA_03 Address: 62 (3Eh) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 EXT_SLV_SENS_DATA_03[7:0] Sensor data read from external I2C devices via the I2C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- 4)_CTRL registers.

8.36 EXT_SLV_SENS_DATA_04

Name: EXT_SLV_SENS_DATA_04 Address: 63 (3Fh) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 EXT_SLV_SENS_DATA_04[7:0] Sensor data read from external I2C devices via the I2C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- 4)_CTRL registers.

Document Number: DS-000189 Page 47 of 89 Revision: 1.3

8.37 EXT_SLV_SENS_DATA_05

Name: EXT_SLV_SENS_DATA_05 Address: 64 (40h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 EXT_SLV_SENS_DATA_05[7:0] Sensor data read from external I2C devices via the I2C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- 4)_CTRL registers.

8.38 EXT_SLV_SENS_DATA_06

Name: EXT_SLV_SENS_DATA_06 Address: 65 (41h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 EXT_SLV_SENS_DATA_06[7:0] Sensor data read from external I2C devices via the I2C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- 4)_CTRL registers.

8.39 EXT_SLV_SENS_DATA_07

Name: EXT_SLV_SENS_DATA_07 Address: 66 (42h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 EXT_SLV_SENS_DATA_07[7:0] Sensor data read from external I2C devices via the I2C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- 4)_CTRL registers.

8.40 EXT_SLV_SENS_DATA_08

Name: EXT_SLV_SENS_DATA_08 Address: 67 (43h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 EXT_SLV_SENS_DATA_08[7:0] Sensor data read from external I2C devices via the I2C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- 4)_CTRL registers.

Document Number: DS-000189 Page 48 of 89 Revision: 1.3

8.41 EXT_SLV_SENS_DATA_09

Name: EXT_SLV_SENS_DATA_09 Address: 68 (44h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 EXT_SLV_SENS_DATA_09[7:0] Sensor data read from external I2C devices via the I2C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- 4)_CTRL registers.

8.42 EXT_SLV_SENS_DATA_10

Name: EXT_SLV_SENS_DATA_10 Address: 69 (45h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 EXT_SLV_SENS_DATA_10[7:0] Sensor data read from external I2C devices via the I2C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- 4)_CTRL registers.

8.43 EXT_SLV_SENS_DATA_11

Name: EXT_SLV_SENS_DATA_11 Address: 70 (46h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 EXT_SLV_SENS_DATA_11[7:0] Sensor data read from external I2C devices via the I2C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- 4)_CTRL registers.

8.44 EXT_SLV_SENS_DATA_12

Name: EXT_SLV_SENS_DATA_12 Address: 71 (47h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 EXT_SLV_SENS_DATA_12[7:0] Sensor data read from external I2C devices via the I2C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- 4)_CTRL registers.

Document Number: DS-000189 Page 49 of 89 Revision: 1.3

8.45 EXT_SLV_SENS_DATA_13

Name: EXT_SLV_SENS_DATA_13 Address: 72 (48h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 EXT_SLV_SENS_DATA_13[7:0] Sensor data read from external I2C devices via the I2C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- 4)_CTRL registers.

8.46 EXT_SLV_SENS_DATA_14

Name: EXT_SLV_SENS_DATA_14 Address: 73 (49h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 EXT_SLV_SENS_DATA_14[7:0] Sensor data read from external I2C devices via the I2C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- 4)_CTRL registers.

8.47 EXT_SLV_SENS_DATA_15

Name: EXT_SLV_SENS_DATA_15 Address: 74 (4Ah) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 EXT_SLV_SENS_DATA_15[7:0] Sensor data read from external I2C devices via the I2C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- 4)_CTRL registers.

8.48 EXT_SLV_SENS_DATA_16

Name: EXT_SLV_SENS_DATA_16 Address: 75 (4Bh) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 EXT_SLV_SENS_DATA_16[7:0] Sensor data read from external I2C devices via the I2C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- 4)_CTRL registers.

Document Number: DS-000189 Page 50 of 89 Revision: 1.3

8.49 EXT_SLV_SENS_DATA_17

Name: EXT_SLV_SENS_DATA_17 Address: 76 (4Ch) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 EXT_SLV_SENS_DATA_17[7:0] Sensor data read from external I2C devices via the I2C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- 4)_CTRL registers.

8.50 EXT_SLV_SENS_DATA_18

Name: EXT_SLV_SENS_DATA_18 Address: 77 (4Dh) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 EXT_SLV_SENS_DATA_18[7:0] Sensor data read from external I2C devices via the I2C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- 4)_CTRL registers.

8.51 EXT_SLV_SENS_DATA_19

Name: EXT_SLV_SENS_DATA_19 Address: 78 (4Eh) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 EXT_SLV_SENS_DATA_19[7:0] Sensor data read from external I2C devices via the I2C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- 4)_CTRL registers.

8.52 EXT_SLV_SENS_DATA_20

Name: EXT_SLV_SENS_DATA_20 Address: 79 (4Fh) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 EXT_SLV_SENS_DATA_20[7:0] Sensor data read from external I2C devices via the I2C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- 4)_CTRL registers.

Document Number: DS-000189 Page 51 of 89 Revision: 1.3

8.53 EXT_SLV_SENS_DATA_21

Name: EXT_SLV_SENS_DATA_21 Address: 80 (50h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 EXT_SLV_SENS_DATA_21[7:0] Sensor data read from external I2C devices via the I2C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- 4)_CTRL registers.

8.54 EXT_SLV_SENS_DATA_22

Name: EXT_SLV_SENS_DATA_22 Address: 81 (51h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 EXT_SLV_SENS_DATA_22[7:0] Sensor data read from external I2C devices via the I2C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- 4)_CTRL registers.

8.55 EXT_SLV_SENS_DATA_23

Name: EXT_SLV_SENS_DATA_23 Address: 82 (52h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 EXT_SLV_SENS_DATA_23[7:0] Sensor data read from external I2C devices via the I2C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- 4)_CTRL registers.

Document Number: DS-000189 Page 52 of 89 Revision: 1.3

8.56 FIFO_EN_1

Name: FIFO_EN_1 Address: 102 (66h) Type: USR0 Bank: 0 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:4 - Reserved.

3 SLV_3_FIFO_EN 1 – Write EXT_SENS_DATA registers associated to SLV_3 (as determined by

I2C_SLV2_CTRL, I2C_SLV1_CTRL, and I2C_SL20_CTRL) to the FIFO at the sample rate; 0 – Function is disabled.

2 SLV_2_FIFO_EN 1 – Write EXT_SENS_DATA registers associated to SLV_2 (as determined by

I2C_SLV0_CTRL, I2C_SLV1_CTRL, and I2C_SL20_CTRL) to the FIFO at the sample rate; 0 – Function is disabled.

1 SLV_1_FIFO_EN 1 – Write EXT_SENS_DATA registers associated to SLV_1 (as determined by

I2C_SLV0_CTRL and I2C_SLV1_CTRL) to the FIFO at the sample rate; 0 – Function is disabled.

0 SLV_0_FIFO_EN 1 – Write EXT_SENS_DATA registers associated to SLV_0 (as determined by

I2C_SLV0_CTRL) to the FIFO at the sample rate; 0 – Function is disabled.

8.57 FIFO_EN_2

Name: FIFO_EN_2 Address: 103 (67h) Type: USR0 Bank: 0 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:5 - Reserved.

4 ACCEL_FIFO_EN 1 – Write ACCEL_XOUT_H, ACCEL_XOUT_L, ACCEL_YOUT_H, ACCEL_YOUT_L,

ACCEL_ZOUT_H, and ACCEL_ZOUT_L to the FIFO at the sample rate; 0 – Function is disabled. 3 GYRO_Z_FIFO_EN 1 – Write GYRO_ZOUT_H and GYRO_ZOUT_L to the FIFO at the sample rate. 0 – Function is disabled. 2 GYRO_Y_FIFO_EN 1 – Write GYRO_YOUT_H and GYRO_YOUT_L to the FIFO at the sample rate. 0 – Function is disabled. 1 GYRO_X_FIFO_EN 1 – Write GYRO_XOUT_H and GYRO_XOUT_L to the FIFO at the sample rate. 0 – Function is disabled. 0 TEMP_FIFO_EN 1 – Write TEMP_OUT_H and TEMP_OUT_L to the FIFO at the sample rate. 0 – Function is disabled.

Document Number: DS-000189 Page 53 of 89 Revision: 1.3

8.58 FIFO_RST

Name: FIFO_RST Address: 104 (68h) Type: USR0 Bank: 0 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:5 - Reserved. 4:0 FIFO_RESET[4:0] S/W FIFO reset. Assert and hold to set FIFO size to 0. Assert and de-assert to reset FIFO.

8.59 FIFO_MODE

Name: FIFO_MODE Address: 105 (69h) Type: USR0 Bank: 0 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:5 - Reserved. 4:0 FIFO_MODE[4:0] 0 – Stream. 1 – Snapshot. When set to ‘1’, when the FIFO is full, additional writes will not be written to FIFO. When set to ‘0’, when the FIFO is full, additional writes will be written to the FIFO, replacing the oldest data.

8.60 FIFO_COUNTH

Name: FIFO_COUNTH Address: 112 (70h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:5 - Reserved. 4:0 FIFO_CNT[12:8] High Bits, count indicates the number of written bytes in the FIFO. Reading this byte latches the data for both FIFO_COUNTH, and FIFO_COUNTL.

8.61 FIFO_COUNTL

Name: FIFO_COUNTL Address: 113 (71h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION 7:0 FIFO_CNT[7:0] Low bits, count indicates the number of written bytes in the FIFO.

Document Number: DS-000189 Page 54 of 89 Revision: 1.3

8.62 FIFO_R_W

Name: FIFO_R_W Address: 114 (72h) Type: USR0 Bank: 0 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:0 FIFO_R_W[7:0] Reading from or writing to this register actually reads/writes the FIFO. For example, to write a byte to the FIFO, write the desired byte value to FIFO_R_W[7:0]. To read a byte from the FIFO, perform a register read operation and access the result in FIFO_R_W[7:0].

8.63 DATA_RDY_STATUS

Name: DATA_RDY_STATUS Address: 116 (74h) Type: USR0 Bank: 0 Serial IF: R/C Reset Value: 0x00 BIT NAME FUNCTION 7 WOF_STATUS Wake on FSYNC interrupt status. Cleared on read. 6:4 - Reserved. 3:0 RAW_DATA_RDY[3:0] Data from sensors is copied to FIFO or SRAM. Set when sequence controller kicks off on a sensor data load. Only bit 0 is relevant in a single FIFO configuration. Cleared on read.

8.64 FIFO_CFG

Name: FIFO_CFG Address: 118 (76h) Type: USR0 Bank: 0 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:1 - Reserved. 0 FIFO_CFG This bit should be set to 1 if interrupt status for each sensor is required.

8.65 REG_BANK_SEL

Name: REG_BANK_SEL Address: 127 (7Fh) Type: ALL Bank: 0 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:6 - Reserved. 5:4 USER_BANK[1:0] Use the following values in this bit-field to select a USER BANK. 0: Select USER BANK 0. 1: Select USER BANK 1. 2: Select USER BANK 2. 3: Select USER BANK 3. 3:0 - Reserved.

Document Number: DS-000189 Page 55 of 89 Revision: 1.3

9 USR BANK 1 REGISTER DESCRIPTIONS

This section describes the function and contents of the User Bank 1 Register Map within the ICM-20948. NOTE: The device will come up in sleep mode upon power-up.

9.1 SELF_TEST_X_GYRO

Name: SELF_TEST_X_GYRO Address: 2 (02h) Type: USR1 Bank: 1 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:0 XG_ST_DATA[7:0] The value in this register indicates the self-test output generated during manufacturing tests. This value is to be used to check against subsequent self-test outputs performed by the end user.

9.2 SELF_TEST_Y_GYRO

Name: SELF_TEST_Y_GYRO Address: 3 (03h) Type: USR1 Bank: 1 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:0 YG_ST_DATA[7:0] The value in this register indicates the self-test output generated during manufacturing tests. This value is to be used to check against subsequent self-test outputs performed by the end user.

9.3 SELF_TEST_Z_GYRO

Name: SELF_TEST_Z_GYRO Address: 4 (04h) Type: USR1 Bank: 1 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:0 ZG_ST_DATA[7:0] The value in this register indicates the self-test output generated during manufacturing tests. This value is to be used to check against subsequent self-test outputs performed by the end user.

9.4 SELF_TEST_X_ACCEL

Name: SELF_TEST_X_ACCEL Address: 14 (0Eh) Type: USR1 Bank: 1 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:0 XA_ST_DATA[7:0] Contains self-test data for the X Accelerometer.

Document Number: DS-000189 Page 56 of 89 Revision: 1.3

9.5 SELF_TEST_Y_ACCEL

Name: SELF_TEST_Y_ACCEL Address: 15 (0Fh) Type: USR1 Bank: 1 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:0 YA_ST_DATA[7:0] Contains self-test data for the Y Accelerometer.

9.6 SELF_TEST_Z_ACCEL

Name: SELF_TEST_Z_ACCEL Address: 16 (10h) Type: USR1 Bank: 1 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:0 ZA_ST_DATA[7:0] Contains self-test data for the Z Accelerometer.

9.7 XA_OFFS_H

Name: XA_OFFS_H Address: 20 (14h) Type: USR1 Bank: 1 Serial IF: R/W Reset Value: Trimmed on a per-part basis for optimal performance BIT NAME FUNCTION 7:0 XA_OFFS[14:7] Upper bits of the X accelerometer offset cancellation.

9.8 XA_OFFS_L

Name: XA_OFFS_L Address: 21 (15h) Type: USR1 Bank: 1 Serial IF: R/W Reset Value: Trimmed on a per-part basis for optimal performance BIT NAME FUNCTION 7:1 XA_OFFS[6:0] Lower bits of the X accelerometer offset cancellation. 0 - Reserved.

9.9 YA_OFFS_H

Name: YA_OFFS_H Address: 23 (17h) Type: USR1 Bank: 1 Serial IF: R/W Reset Value: Trimmed on a per-part basis for optimal performance BIT NAME FUNCTION 7:0 YA_OFFS[14:7] Upper bits of the Y accelerometer offset cancellation.

Document Number: DS-000189 Page 57 of 89 Revision: 1.3

9.10 YA_OFFS_L

Name: YA_OFFS_L Address: 24 (18h) Type: USR1 Bank: 1 Serial IF: R/W Reset Value: Trimmed on a per-part basis for optimal performance BIT NAME FUNCTION 7:1 YA_OFFS[6:0] Lower bits of the Y accelerometer offset cancellation. 0 - Reserved .

9.11 ZA_OFFS_H

Name: ZA_OFFS_H Address: 26 (1Ah) Type: USR1 Bank: 1 Serial IF: R/W Reset Value: Trimmed on a per-part basis for optimal performance BIT NAME FUNCTION 7:0 ZA_OFFS[14:7] Upper bits of the Z accelerometer offset cancellation.

9.12 ZA_OFFS_L

Name: ZA_OFFS_L Address: 27 (1Bh) Type: USR1 Bank: 1 Serial IF: R/W Reset Value: Trimmed on a per-part basis for optimal performance BIT NAME FUNCTION 7:1 ZA_OFFS[6:0] Lower bits of the Z accelerometer offset cancellation. 0 - Reserved.

9.13 TIMEBASE_CORRECTION_PLL

Name: TIMEBASE_CORRECTION_PLL Address: 40 (28h) Type: USR1 Bank: 1 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:0 TBC_PLL[7:0] System PLL clock period error (signed, [-10%, +10%]).

Document Number: DS-000189 Page 58 of 89 Revision: 1.3

9.14 REG_BANK_SEL

Name: REG_BANK_SEL Address: 127 (7Fh) Type: Bank: 1 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:6 - Reserved. 5:4 USER_BANK[1:0] Use the following values in this bit-field to select a USER BANK. 0: Select USER BANK 0. 1: Select USER BANK 1. 2: Select USER BANK 2. 3: Select USER BANK 3. 3:0 - Reserved.

Document Number: DS-000189 Page 59 of 89 Revision: 1.3

10 USR BANK 2 REGISTER MAP

This section describes the function and contents of the User Bank 2 Register Map within the ICM-20948. NOTE: The device will come up in sleep mode upon power-up.

10.1 GYRO_SMPLRT_DIV

Name: GYRO_SMPLRT_DIV Address: 0 (00h) Type: USR2 Bank: 2 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:0 GYRO_SMPLRT_DIV[7:0] Gyro sample rate divider. Divides the internal sample rate to generate the sample rate that controls sensor data output rate, FIFO sample rate, and DMP sequence rate. NOTE: This register is only effective when FCHOICE = 1’b1 (FCHOICE_B register bit is 1’b0), and (0 < DLPF_CFG < 7). ODR is computed as follows: 1.1 kHz/(1+GYRO_SMPLRT_DIV[7:0])

10.2 GYRO_CONFIG_1

Name: GYRO_CONFIG_1 Address: 1 (01h) Type: USR2 Bank: 2 Serial IF: R/W Reset Value: 0x01 BIT NAME FUNCTION 7:6 - Reserved. 5:3 GYRO_DLPFCFG[2:0] Gyro low pass filter configuration as shown in Table 16. 2:1 GYRO_FS_SEL[1:0] Gyro Full Scale Select: 00 = ±250 dps 01= ±500 dps 10 = ±1000 dps 11 = ±2000 dps 0 GYRO_FCHOICE 0 – Bypass gyro DLPF. 1 – Enable gyro DLPF. The gyroscope DLPF is configured by GYRO_DLPFCFG, when GYRO_FCHOICE = 1. The gyroscope data is filtered according to the value of GYRO_DLPFCFG and GYRO_FCHOICE as shown in Table 16.

Table 16. Gyroscope Configuration 1

10.3 GYRO_CONFIG_2

5 XGYRO_CTEN X Gyro self-test enable. 4 YGYRO_CTEN Y Gyro self-test enable. 3 ZGYRO_CTEN Z Gyro self-test enable. 2:0 GYRO_AVGCFG[2:0] Averaging filter configuration settings for low-power mode. of operation, the gyroscope is duty-cycled.

Table 17. Gyroscope Configuration 2 NOTE: Ton is the ON time for motion measurement when the gyroscope is in duty cycle mode.

10.4 XG_OFFS_USRH

7:0 X_OFFS_USER[15:8] Upper byte of X gyro offset cancellation.

Document Number: DS-000189 Page 62 of 89 Revision: 1.3

10.5 XG_OFFS_USRL

Name: XG_OFFS_USRL Address: 4 (04h) Type: USR2 Bank: 2 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:0 X_OFFS_USER[7:0] Lower byte of X gyro offset cancellation.

10.6 YG_OFFS_USRH

Name: YG_OFFS_USRH Address: 5 (05h) Type: USR2 Bank: 2 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:0 Y_OFFS_USER[15:8] Upper byte of Y gyro offset cancellation.

10.7 YG_OFFS_USRL

Name: YG_OFFS_USRL Address: 6 (06h) Type: USR2 Bank: 2 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:0 Y_OFFS_USER[7:0] Lower byte of Y gyro offset cancellation.

10.8 ZG_OFFS_USRH

Name: ZG_OFFS_USRH Address: 7 (07h) Type: USR2 Bank: 2 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:0 Z_OFFS_USER[15:8] Upper byte of Z gyro offset cancellation.

10.9 ZG_OFFS_USRL

Name: ZG_OFFS_USRL Address: 8 (08h) Type: USR2 Bank: 2 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:0 Z_OFFS_USER[7:0] Lower byte of Z gyro offset cancellation.

Document Number: DS-000189 Page 63 of 89 Revision: 1.3

10.10 ODR_ALIGN_EN

Name: ODR_ALIGN_EN Address: 9 (09h) Type: USR2 Bank: 2 OTP: No Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:1 - Reserved. 0 ODR_ALIGN_EN 0: Disables ODR start-time alignment. 1: Enables ODR start-time alignment when any of the following registers is written (with the same value or with different values): GYRO_SMPLRT_DIV, ACCEL_SMPLRT_DIV_1, ACCEL_SMPLRT_DIV_2, I2C_MST_ODR_CONFIG.

10.11 ACCEL_SMPLRT_DIV_1

Name: ACCEL_SMPLRT_DIV_1 Address: 16 (10h) Type: USR2 Bank: 2 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:4 - Reserved. 3:0 ACCEL_SMPLRT_DIV[11:8] MSB for ACCEL sample rate div.

10.12 ACCEL_SMPLRT_DIV_2

Name: ACCEL_SMPLRT_DIV_2 Address: 17 (11h) Type: USR2 Bank: 2 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:0 ACCEL_SMPLRT_DIV[7:0] LSB for ACCEL sample rate div. ODR is computed as follows: 1.125 kHz/(1+ACCEL_SMPLRT_DIV[11:0])

10.13 ACCEL_INTEL_CTRL

Name: ACCEL_INTEL_CTRL Address: 18 (12h) Type: USR2 Bank: 2 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:2 - Reserved. 1 ACCEL_INTEL_EN Enable the WOM logic. 0 ACCEL_INTEL_MODE_INT Selects WOM algorithm. 1 = Compare the current sample with the previous sample. 0 = Initial sample is stored, all future samples are compared to the initial sample.

10.14 ACCEL_WOM_THR

x/y/z axes. LSB = 4 mg. Range is 0 mg to 1020 mg.

10.15 ACCEL_CONFIG

5:3 ACCEL_DLPFCFG[2:0] Accelerometer low pass filter configuration as shown in Table 18. 0 ACCEL_FCHOICE 0: Bypass accel DLPF. Table 18. Accelerator Configuration 1.125 kHz/(1+ACCEL_SMPLRT_DIV[11:0]) where ACCEL_SMPLRT_DIV is a 12-bit integer.

Document Number: DS-000189 Page 65 of 89 Revision: 1.3

10.16 ACCEL_CONFIG_2

Name: ACCEL_CONFIG_2 Address: 21 (15h) Type: USR2 Bank: 2 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:5 - Reserved. 4 AX_ST_EN_REG X Accel self-test enable. 3 AY_ST_EN_REG Y Accel self-test enable. 2 AZ_ST_EN_REG Z Accel self-test enable. 1:0 DEC3_CFG[1:0] Controls the number of samples averaged in the accelerometer decimator: 0: Average 1 or 4 samples depending on ACCEL_FCHOICE (see Table 19). 1: Average 8 samples. 2: Average 16 samples. 3: Average 32 samples. Table 19 lists the accelerometer filter bandwidths available in the low -power mode of operation. In the low-power mode of operation, the accelerometer is duty-cycled. AVERAGES 1X 4X 8X 16X 32X ACCEL_FCHOICE 0 1 1 1 1 ACCEL_DLPFCFG x 7 7 7 7 DEC3_CFG 0 0 1 2 3 RMS NOISE [MG-RMS] TYP (BASED ON ACCELEROMETER NOISE: 190µG/√HZ) ACCEL_SMPLRT_DIV ODR [HZ] CURRENT CONSUMPTION [µA] TYP

Table 19. Accelerator Configuration 2 NOTE: Ton is the ON time for motion measurement when the accelerometer is in duty cycle mode.

10.17 FSYNC_CONFIG

7 DELAY_TIME_EN 0: Disables delay time measurement between FSYNC event and the first ODR event

5 WOF_DEGLITCH_EN Enable digital deglitching of FSYNC input for Wake on FSYNC. 4 WOF_EDGE_INT 0: FSYNC is a level interrupt for Wake on FSYNC. 1: FSYNC is an edge interrupt for Wake on FSYNC. ACTL_FSYNC is used to set the polarity of the interrupt. 3:0 EXT_SYNC_SET[3:0] Enables the FSYNC pin data to be sampled. EXT_SYNC_SET FSYNC bit location.

Document Number: DS-000189 Page 67 of 89 Revision: 1.3

10.18 TEMP_CONFIG

Name: TEMP_CONFIG Address: 83 (53h) Type: USR2 Bank: 2 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 2:0 TEMP_DLPFCFG[2:0] Low pass filter configuration for temperature sensor as shown in the table below: TEMP_DLPCFG<2:0> TEMP SENSOR NBW (HZ) RATE (KHZ) 0 7932.0 9 1 217.9 1.125 2 123.5 1.125 3 65.9 1.125 4 34.1 1.125 5 17.3 1.125 6 8.8 Rate (kHz) 7 7932.0 9

10.19 MOD_CTRL_USR

Name: MOD_CTRL_USR Address: 84 (54h) Type: USR2 Bank: 2 Serial IF: R/W Reset Value: 0x03 BIT NAME FUNCTION 7:1 - Reserved. 0 REG_LP_DMP_EN Enable turning on DMP in Low Power Accelerometer mode.

10.20 REG_BANK_SEL

Name: REG_BANK_SEL Address: 127 (7Fh) Type: USR2 Bank: 2 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:6 - Reserved. 5:4 USER_BANK[1:0] Use the following values in this bit-field to select a USER BANK. 0: Select USER BANK 0. 1: Select USER BANK 1. 2: Select USER BANK 2. 3: Select USER BANK 3. 3:0 - Reserved.

Document Number: DS-000189 Page 68 of 89 Revision: 1.3

11 USR BANK 3 REGISTER MAP

This section describes the function and contents of the User Bank 3 Register Map within the ICM-20948. NOTE: The device will come up in sleep mode upon power-up.

11.1 I2C_MST_ODR_CONFIG

Name: I2C_MST_ODR_CONFIG Address: 0 (00h) Type: USR3 Bank: 3 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7:4 - Reserved 3:0 I2C_MST_ODR_CONFIG[3:0] ODR configuration for external sensor when gyroscope and accelerometer are disabled. ODR is computed as follows: 1.1 kHz/(2^((odr_config[3:0])) ) When gyroscope is enabled, all sensors (including I2C_MASTER) use the gyroscope ODR. If gyroscope is disabled, then all sensors (including I2C_MASTER) use the accelerometer ODR.

11.2 I2C_MST_CTRL

Name: I2C_MST_CTRL Address: 1 (01h) Type: USR3 Bank: 3 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7 MULT_MST_EN Enables multi-master capability. When disabled, clocking to the I2C_MST_IF can be disabled when not in use and the logic to detect lost arbitration is disabled. 6:5 - Reserved.

4 I2C_MST_P_NSR This bit controls the I2C Master’s transition from one slave read to the next slave

read. 0 - There is a restart between reads. 1 - There is a stop between reads. 3:0 I2C_MST_CLK[3:0] Sets I2C master clock frequency as shown in Table 23.

Document Number: DS-000189 Page 69 of 89 Revision: 1.3

11.3 I2C_MST_DELAY_CTRL

Name: I2C_MST_DELAY_CTRL Address: 2 (02h) Type: USR3 Bank: 3 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION 7 DELAY_ES_SHADOW Delays shadowing of external sensor data until all data is received. 6:5 - Reserved.