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SPECIFICATION FOR 5.0x7.0mm LVPECL/LVDS SMT OSCILLATOR Page 1 of 5 The information contained herein is proprietary to MtronPTI and is submitted in confidence. This information may not be copied or divulged without written permission from MtronPTI.

FEATURES

APPLICATIONS

LVPECL/LVDS Differential Output RMS Phase Jitter < 700 fs, 12 kHz to 20 MHz (156.25 MHz, PECL output) Low Phase Noise rd Overtone crystal technology Compliant to RoHS directive

10 Gigabit Ethernet switches/routers

Ordering Information: Product Family (Supply Voltage Option) Temperature Range Stability * Enable/Disable Logic Type Package/Lead Configuration Frequency Code Value Code Value Code Value Code Value Code Value M2075 (3.3V) M2076 (2.5V) 1 0 °C to +70 °C 3 ±100 ppm B Enable High (pad 1) P LVPECL N Leadless XXX.XXXX MHz 2 -40 °C to +85 °C 4 ±50 ppm G Enable High (pad 2) L LVDS 6 -20 °C to +70 °C 6 ±25 ppm U No Enable/Disable 7 0 °C to +85 °C 8 ±20 ppm Example: M207524BPN 156.2500 MHz M2075 2 4 B P N 156.2500 MHz  Stability includes initial tolerance @ +25°C, deviation over operating temperature, variations to supply voltage, load, vibrat ion and shock. Parameter Symbol Min. Typ. Max. Units Conditions Frequency of Operation F O 25 320 MHz Frequency Stability Frequency Stability F/F See ordering information Aging -5 +5 ppm 1 st year RF Output Output Type LVPECL Compatible Output Load 50 Ω to (Vcc-2.0) VDC V Symmetry (duty cycle) V OH 45 55 % Ref. to 50% of waveform Logic Level “1” VOH V cc-1.025 V 0 to +85 °C VOH V cc-1.085 V -40 to 0 °C Logic Level “0” VOL V cc-1.620 V 0 to +85 °C VOL V cc-1.550 V -40 to 0 °C Rise/Fall Time T R/TF 0.3 0.5 ns 20% to 80% of waveform Start-up Time T SU 10 ms T ambient = +25°C Enable Logic 70% VCC or N/C V Pad 1 or Pad 2: Output Enabled Disable Logic 30% V CC V Pad 1 or Pad 2: Output Disabled to high-Z Supply Voltage & Power Consumption Operating Voltage V CC 3.135 3.300 3.465 V Supply Current I CC 100 mA Other Parameters Phase Jitter (RMS) ΦJ 0.700 ps 12 KHz to 20 MHz

156.25 MHz

SPECIFICATION FOR 5.0x7.0mm LVPECL/LVDS SMT OSCILLATOR Page 2 of 5 The information contained herein is proprietary to MtronPTI and is submitted in confidence. This information may not be copied or divulged without written permission from MtronPTI. Parameter Symbol Min. Typ. Max. Units Conditions Frequency of Operation F O 25 320 MHz Frequency Stability Frequency Stability F/F See ordering information Aging -5 +5 ppm 1 st year RF Output Output Type LVDS Compatible Output Load 100 Ω Differential V Symmetry (duty cycle) V OH 45 55 % Ref. to 50% of waveform Differential Output Voltage VDIFF 250 350 450 mV peak-to-peak differential output voltage Output Offset Voltage V OS 1.125 1.250 1.375 V Rise/Fall Time T R/TF 0.3 0.5 ns 20% to 80% of waveform Start-up Time T SU 10 ms T ambient = +25°C Enable Logic 70% VCC or N/C V Pad 1 or Pad 2: Output Enabled Disable Logic 30% V CC V Pad 1 or Pad 2: Output Disabled to high-Z Supply Voltage & Power Consumption Operating Voltage V CC 3.135 3.300 3.465 V Supply Current I CC 60 mA Other Parameters Phase Jitter (RMS) ΦJ 0.700 ps 12 KHz to 20 MHz Environmental & Packaging Requirements: Storage Temperature -55°C to 125 °C Mechanical Shock Per MIL-STD-202, Me thod 213, Condition C (100 g’s, 6 ms) Vibration Per MIL-STD-202, Method 204, Condition C (55 – 2000 Hz, 10 g’s) Aging +85°C ±3°C, 720H (No BIAS) Humidity +40°C ±2°CX90~95%, 96H (NO BIAS) Thermal Cycle Per MIL-STD-883, Method 1010, Condition B (-55 to +125 °C, 10 cycles) Hermeticity Per MIL-STD-202, Method 112 (1 x 10 -8 atm cc/s of Helium) Moisture Sensitivity Level MSL1 Solderability Per EIAJ-STD-002, Method 208 Max. Soldering Conditions See solder profile, Figure 1 Pad Termination Gold, 1 µm maximum thickness Package Type 6-pad 5.0 X 7.0 mm leadless ceramic. RoHS compliant.

SPECIFICATION FOR 5.0x7.0mm LVPECL/LVDS SMT OSCILLATOR Page 3 of 5 The information contained herein is proprietary to MtronPTI and is submitted in confidence. This information may not be copied or divulged without written permission from MtronPTI. Marking, Pin Out: Dimensions: Output Waveform: Pad Function

1 Enable/Disable or N/C

2 Enable/Disable or N/C

3 Ground

4 Output

5 Complementary Output

Line 1 [part designation] Line 2 FFFMFFFF Line 3 M yy ww vv Legend M MtronPTI F Frequency yy Year ww Work Week vv Factory code

SPECIFICATION FOR 5.0x7.0mm LVPECL/LVDS SMT OSCILLATOR Page 4 of 5 The information contained herein is proprietary to MtronPTI and is submitted in confidence. This information may not be copied or divulged without written permission from MtronPTI. Typical LVPECL Test Circuit & Load Circuit Diagrams: Typical LVDS Test Circuit & Load Circuit Diagrams: