M206

M206 STMICROELECTRONICS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 15

Technical content

PLL TV MICROCOMPUTER INTERFACE = HIGHLY INTEGRATED SOLUTION INCLUD- _ parator reference frequency of 0.9765 kHz. Outputs ING PLL SYNTHESIZER, NV MEMORY, D/A are provided to control the division ratio of the pres- CONVERTERS, BAND SELECT OUTPUTS, caler and to signal the out-of-lock condition to the CLOCK OSCILLATOR, IR SIGNAL PRE-PRO- microcomputer. CESSOR AND SERIAL BUS INTERFACE The infrared remote contro! signal pre-processor = 32 x 16 BITS OF NV MEMORY WITH LIFE. consists of a preamplifier, a squarer and a digital fil- MES OF 10* CYCLES/WORD AND MINIMUM si ‘f mM a terto separate noise from signals transmitted by the De AES, RETENTION STORES TUNING M708, M709 and M710 remote control transmitters DATA FOR 30 CHANNELS PLUS PRESET The output ofthis pre-processor is connected to the NACHES FOR THE Six AN aS Hear interrupt input of a mictocomputer programmed to "CONTROL SIGNALS REDUCES compo. [00089 and decode the sonal

7 NENT COUNT The M206 is supplied with two separate 5 V supply

» SIX PWM D/A CONVERTERS WITH 64-STEP _ inputs, each provided with internal power-on reset ) RESOLUTION Circuits. The first, Voo1, supplies the remote control ) = FOUR OPEN-DRAIN BAND SELECT OUT. and clock circuits in both standby and TV set oper- PUTS RATED TO 132 V ation, The second, Vooz, supplies the rest of the cir- = ON-CHIP 4 MHz CLOCK OSCILLATOR WITH Cults and is only active during TV operation. ) BUFFERED OUTPUT The M206 is packaged in a 28-pin dual in-line plas- : = INTEGRATED DIGITAL POWER-ON RESET tic package. « 3-WIRE SERIAL BUS TO LOAD/READ INTER- NAL REGISTERS = TECHNICAL NOTE TN 152 AVAILABLE | DESCRIPTION co | __The M206 is a highly integrated, programmable LSI La integrated circuit for microcomputer controlled TV " ~~ = == applications, realized using an advanced N-channel Wo he, eg _ double polysilicon gate technology (NVMOS) that ta allows the integration of non-volatile memory and i standard logic on the same chip. pipze It contains a phase-locked loop (PLL) synthesizer, six pulse-width modulation (PWM) digitaVanalog converters, a four-bit parallel output butfer, clock os- ORDER CODE : M2061 cillator with buffered output, pre-processor for in- frared remote control signals and a 3-wire serial bus interface. The M206 interfaces with a microcomputer through the three-wire serial bus and is programmed by loading thirteen internal registers - twelve of which are readable to simplify programming. The PLL synthesizer requires an external 64 +15/16 prescaler and divider and works with a phase com- October 1988 15 } 105

[Symbo[__ Parameter ———S*drSSC awe | Unit | Supply Voltage =03t0 7 Vpe__| Memory Supply Voltage = 03 to 28 Vi Input Voltage (except pin 11) =0.3to 7 Vv Pin 11 -03 to 15 v Voor) | Off State Output Voltage 7 Pins 2-3-4-20 to 23-26 to 28 15 v Pin 24 28 v Output Current (except 2-3-4-26-27-28) 5 mA Pins 2-3-4-26-27-28 10 mA [Tox [output Goren pins 15,5) [5 ma | [Pict | Total Package Power Dissipation [1d Ww Operating Temperature 0 to 70 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This isa siress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections ofthis specif Cation is not implied. Exposure to absolute maximum cating conditions for extended periods may atfect device reliably PIN CONNECTIONS BLOCK DIAGRAM Lx] ~ ono 22) one re oa2 3 268i) 046 on fle asf) ms = Og Eo \\ Is 2af) MT se0~ | a {iu} - ie ne | Po cun 7 22) 8s [a }- me en | ccours aif) 8 Taf putt nel 28 | cieurf} 2 20) Bt PHASE come OuTPut|CONTROL Rcout [10 isi} Test v0.0 seo vf) eo [»_] 1s see fa ie) [me _ sees sf] Pco —f anf ” ‘s-saant sare, Ce] POWER ON RESET puns [escxcson] sme | cour me ce ans G57 ScS:THOMSON _ SY imcroaecrRowics 106

DA1-DAS - Digital/Analog converter outputs (open- ‘OL - Out of Lock (output, active low) drain outputs) Signals an out of lock condition. This output is also Output from the six pulse-width modulation D/Acon- —_active during the power on reset sequence. verters. PCO - Phase Comparator Output B0-B3 - Band ative outputs (open-drain outputs) The output of the phase comparator. Connected to Outputs from the four-bit buffer used for band selec- _ the input of a low pass filter used to generate the tion, tuning voltage. SBD - Serial Bus Data (bidirectional) TEST - Test pin (input) Data line for serial communication with a microcom- The test pinis used only to test the device and is not puter. specified for customer use. It must be connected to . oo ground. SBE - Serial Bus Enable (bidirectional, active low) Enables serial bus transmissions. CLIN, CLOUT - Clock oscillator connections ; A4Mbz quartz crystal is connected between these SBC - Serial Bus Clock (input, active low) pins. Clock for serial bus transmissions. ; Vop1, Vooz, GND - Power Supply Connections RCIN - Remote Control signal Input (analog input) pp is the + 5 V standby supply input ; Voo2 is the Input to the infrared remote control signal prepro- main + 5 V supply input. cessor. Connected to the output of the IR preampii- fier. Minimum input level 0.5 V peak-to-peak. MS - Memory Supply Input (input) - Programming pulses for the NV memory are sup- RCOUT - Remote Control signal Output plied to this pin during store cycles. Output from the infrared remote control signal pre- | processor. To be connected to the interrupt input of || MT - Memory Timing (output, active low) a microcomputer. This output supplies the timing for the memory write ; pulses supplied to the MS input during store cycles. PDI - Programmable Divider Input (input) | This pinis the input of the programmable dividerand CLBUF - Clock Buffer (output) is connected to the output of the prescaler. This is a buffered output from the on-chip clock os- cillator and can be used to drive other components PCM - Prescaler Modulo Control (output) (for example the microcomputer) Control signal to set the prescaler division ratio (15 if high, 16 if low). FUNCTIONAL DESCRIPTION | CLOCK a clock output, loaded by a capacitor up to 15 pF. , The minimum extemal clock amplitude is 2 V peak- To use the internal oscillator a 4 MHz quartz crystal ! ___ is connected between the pins CLIN and CLOUT. If (peak A buttered Giock output CLBUE. is Bro: __ anexternal clock is used this must be connected to Vide which can drive up to three HA loads. _ CLINand CLOUT leftunconnectedor, if required as 33pF 2Vpp typ at 4MHz com | CLIN CLeUF a - ——O InF MHz CI M206 Tee capacitance) om | cout , 33) S-S6I6N po Ly SSs:THomson a8 “YF acrossctmomcs _

LOADING AND READING INTERNAL REGISTERS The M206 is programmed by loading a set of internal registers through a 3-wire serial bus. The functions of these registers are summarised in table 1. Table 1 : Summary of internal Registers. Register [Address Number of Number |"as [a2 | at [ao | Bis 0 cfefede 6 D/A Converter n° 1 1 cfe]elu 6 D/A Converter n° 2 2 cfelade 6 D/A Converter n° 3 3 cf ec] Hid 6 D/A Converter n° 4 4 cha} ede 6 D/A Converter n° 5 5 chai ola 6 D/A Converter n° 6 6 ctu} ade 7 PLL Counter (MSB) 7 uc} aH | HH 8 PLL Counter (LSB) 8 Hf} oe}outoe 7 Buffer Outputs/Phase Comp. Output Control

9 H | ttt] u 5 NV Memory Address

10 Ho} tc} H | 8 NV Memory DATA

" HH} oc] HY] 4a 8 NV Memory DATA

12 H}Hi] tte 2 NV Memory Modity Contro/Reset Control

The 3-wire serial bus consists of the signals SBD Data is accepted when the clock is low (active) and (Serial Bus Data), SBE (Serial Bus Enable) and SBC latched into the M206 on the low-high transition of (Serial Bus Clock). The enable and data pins, SBD __ the clock. All bus transfers are controlled by SBE. and SBE, are bidirectional. REGISTER LOADING. Serial data transferred from the microprocessor to the M206 has the following for- mat : seo Les Jor ow To te Te Toto To Tstu to To To Toy = UUurwvuvueuuruuuvruudnlé wv = c— cs Chip Select (always low) PARITY Parity bit (the number of " H " bits transmitted is odd) RW Read/Write. High for Register Load ; Low for Register Read A0-A3 Register Address (see table 1) 00-07 Data to be loaded into register (load operation only). The received data word is checked - length, CS and the microprocessor by forcing the SBE line low for parity - immediately after the low-high transition of 20-24 s. ‘SBE. If the received word is valid this is signalled to | 45 | ae gp SGS-THOMSON ‘YM imcromzcraomes 7 108

2otozus_, 38E s.seat RECEPTION OK REGISTER READING. M206 registers are read by _the contents of the addressed register will be avail- transmitting a 15 bit word as shown in fig. 4 with RW able tobe read. The microprocessor reads this data low and the address of the register to be read in AO, _by sending eight clock pulses. Data is output on the ‘1, A2, A3. Bits DO-D7 can be high or low except —_ low-high transition of SBC and the first data bit is when register 9 is addressed. available before the first clock pulse. If this word is received correctly the SBE line is im- mediately pulled low by the M206 and after 24 ys Seo COT) Te eT a | 0 | | ee | iA —_I necerom OWA READY i | LOADING THE NON-VOLATILE MEMORY. Datais can be read by two register read operations, The stored in the 32 x 16-bit NV memory by loading the _ data is ready 200 us after the address load. new contents into registers 10 and 11 then the ad- dress into register 9. The memory modify cycle be- PLL COUNTER gins when the address has been loaded and suc- The PLL counter consists of a single counter that cessful completion is indicated by a logic "1" in bit acts as the program counter (11 bit) and is swallow | Zero of register 12. counter (4 bit) alternately. Data for the PLL counter |The time for a modify cycle varies from a few mili: _is loaded into registers 6 and 7. Register 6 must be seconds to several hundred milliseconds during the loaded first because the register 7 load operation in- device lifetime and is not internally limited. The stor- itiates the data transfer to the PLL counter. age operation should be aborted after one secondif —_The reference frequency is produced by dividing the it proves unsuccessful. This is done by setting bit clock frequency by 4096. With a 4 MHz clock this zero of register 12. gives a reference frequency of 976.5 Hz. READING THE NON-VOLATILE MEMORY. The An out-of-lock signal is generated (output OL) when NV memory is read by loading the address into reg- the phase error between the reference frequency ister 9. The contents of the addressed word are nd the input frequency exceeds 0.72 (2 us). automatically loaded into registers 10 and 11 and | SGS-THOMSON S15 1n9

The phase comparator output, PCO, has a three. CALCULATING PLL COUNTER VALUES state push pull configuration with a high level of 5 V Fe ie and a low level of 0 V (with zero current sink or 2) = Wide carrier pump). The output impedance (both states) is typi) !F = 38.9 MHz cally 200.2 (400.2 maximum). The phase compara- _c) The frequency to be synthesized is Fs = F + IF tor output can be set to a high impedance state (both —_g) The. ¥ the phi tor i sink and pump transistors off) by setting bit4 of reg. "Ne Ret. frequency of the phase comparator is ister 8. The output is held in the high impedance F,.,- ——0OOMHz _____ 9 a7 656 KHz state until this bit is reset. The phase comparator 4096 Output snould be set to high impedance when 9) Using the prescaler 64 + 15/16 the minimum changing . frequency steps is RECOVERING LOCK. The phase comparator out- Frot x 64 = 62.5 kHz put can also be set to high and low levels to restore —_¢) The modulo of division N is given by the ratio normal operation when the oscillator stops or the between the frequency to be synthesized and prescaler functions incorrectly at high frequency. the reference frequency multiplied by 64. The In the first condition (oscillator off) the prescaler result has to be rounded. sometimes oscillates, at high frequency. The loop Fs reacts by reducing the varicap voltage in an attempt NS = Integer rounded [Sa ] to reduce the frequency, thus worsening the situ- ret ation. This out-of-lock condition is signalled to the —_g) With the 64 + 15/16 prescaler and the particu- microprocessor (by the OL output) which can set the lar counter of the M206 the division by N is phase comparator output to low level, forcing the given by varicap voltage up and restarting the oscillator. The . phase comparator output is forced low by setting bit N= (ls + 1). 18+ (Rs+ 1). 16 5 of register 8. After about 1 ms this bit is automati-. where | (integer part) controls the division by 15 (pro- cally reset and the loop should lock again. ie counte) and : fed contiols tre division by . (swallow counter). For ease of calculation we de- When the out-of lock condition is caused by a failure i 2 of the prescaler to operate correctly at high frequen- crement Ns by one getting No =Ns5 1 cies the loop reacts by increasing the voltage, hence The numbers Ic and Rc are given by : the frequency, again worsening the situation. To re- No = (Ic + 1) #15 + (Ro +1) 016 cover from this condition the phase comparator out- No-31=Ice15+Roe 16 put is set high. This is done by setting bit 6 of regis- | ter 8 which, as in the previous case, resetsitself after using the formulas : ims. Nc-31 Ro = No - 31 - 15 # Integer | "The out-of-lock condition could also be caused by eo 5 unwanted changes in band or PLL counter contents New31—Ree 16 provoked by external interference (spikes on supply i¢= Ne7St— Ree 16 etc.). For this reason it is always advisable to reload 18 the band and PLL counter registers before attempt- Rs = Ro +1 | ing to recover lock as described above. If the phase let ‘comparator output is in the high impedance state, $=! | the OL output signals the reset condition but not the out-of-lock condition, : Example : Channel 21 F = 471.25 MHz Fs =F +IF Fs = 471.25 + 38.9 = 510.15 MHz Ng = Integer rounded [ 510-15 x10" ] = Integer rounded [8162.4] = 8162 62.5 x 10 No =Ns~1= 8161 one by S¢S:THomson SY iaicromscmomes ‘san

Ac = No-31 — 15 « Integer [ News ] = 8161-31 — 156 Integer [ Siero ] = 8130-15 « Integer [542] = 8130 ~ 15 « 542 = 8130 - 8130 =0 Ige Nox S1-Roe 16 7 8161-31 gay 15 15 Rs=Ro+1=0+1=1 R and | have to be translated into binary code. DIGITAL/ANALOG CONVERTERS the pulse generator only if three successive nega- The six pulse-width modulation (PWM) D/Aconver- _tve going pulses (4 edges) are detected. The dis- tance between these pulses must be in the range ters have a resolution of 64 steps and an output re 1368 -27 us (about 37-41 kHz with a4 MHz clock). The quency of 16 kHz (with 4 MHz clock). At power on. ints not tested for the duration of the output pulse reset they are set to a duty cycle of zero. (132-250 ps) POWER ON RESET If this pre-processor is used in conjunction with f igi M709 or M710 remote control transmitters valid sig- Tr egb! and Vooe supplies have an integrated digi 15 can be recognized in the presence of extreme power on reset with a duration of 250 ms. ; ; ‘ ania noise conditions. Separating the signals from the The reset conditions signalled by alowlevelon the —_ngise externally in this way reduces the number of out-of-lock output, OL. The microprocessor can test interrupts that the microcomputer has to handle thus this condition by reading bit 1 of register 12. This bit aliwing it to concentrate on other takes. To take ad- is zero during power on reset and the OL output re- vantage of this section the M708, 709, 710 transmit- mains active unti itis read. Reading this bit auto- ters must operate witha clock frequency in the range matically restores it to a high state. 492-508 kHz. During power on reset time commands rom the mi- The input ean be DC of AC compled to the LR. pre- coprocessor are not acknowledged. Power onveset amplifier. also sets the phase comparator output to a high im- pedance, state. itis restored by resetting bit 4 of reg- 7 case of DC coupling the quiescent input level is ater suggested to be 1.5 V. | REMOTE CONTROL SIGNAL PRE-PROCESSOR | This section contains a preamplifier, squarer, digital "filter and a pulse generator. The digital filter enables tay | Input | J | J l | | ourpur ' || min 192 us max2s6us s.seee G57 SSS-THOMsON IS

57 SSTMSON

| m1

Response of the Digital Filter as a Function of the Input Frequency (in kHz). Tis) >28 28 27 24 © 23 <23 Rejected | ' f ‘Accepted | t besiesrea s-sea9 Undetermined Undetermined M206 PROGRAMMING SUMMARY Registers 0-5 — D/A Convertors 1-6 Register 6 - PLL Program Counter. 5 0 6 o BINARY CODED RO-R5 PROGRAM COUNT 7 bits ANALOG VALUE 6 bits UPPER 7 BITS MSB LSB MSB Register 7 — PLL Program/Swallow Counter. . 7 0 PROGR. COUNT SWALLOW J 9 i LOWER 4 BITS COUNT is (s8_MSB UsB Register 8 - Band Drive Outputs/Phase Comparator Output Control. 6 t) B0-B3 _Band Drive outputs B0-B3 PCOZ Phase Comparator Output High Impedance PCOL Phase Comparator Output Low Level | PCOH Phase Comparator Output High Level | PCOH | Pcot | Pcoz | Phase Comparator Output L U L_ | Normal PLL Operation | L L H High Impedance State | L H L Low for 1 ms then returns automatically to normal PLL operation. : L H H Low for 1 ms then returns to high impedance state. H L L_—_| High for 1 ms then returns to normal PLL operation. H L H_ | High for 1 ms then returns to high impedance. H H L__| Normal Operation * H H H__| High Impedance * + These combinations are not accepted and PCOL, PCOH are automaticaly reset low alter 1 ms: 815 ee 112

Register 9 — NV Memory Address. 4 0 ADDRESS 5 bits MSB MSB Registers 10 & 11 - NV Memory Data. 7 0 7 0 UPPER EIGHT R10 LOWER EIGHT R11 DATABITS 8 bits DATA BITS 8 bits MSB LSB Register 12 — NV Modify Status/Reset Status. 1 0 RESET MODIFY it . STATUS ome fo tag MODIFY STATUS Modify in progress. Modify over. RESET STATUS Reset actived. Reset not actived. | ey Ss-THOMSON ss | SY iecromecraonics 113

STATIC ELECTRICAL CHARACTERISTICS (Tam = 0 to 70 °C ; typical values are at Tay = 25 °C) Symbol Test Conditions __ J Supply Votage [se | df as | 8s | 58 | Vep Memory Supply v Voltage [Vi | inputtowVotage [ratoiea7[ | ow | Input High Voltage [12isiea7{ ne | 5.25 TV | Ver Peak to Peak Wt AC COUPLING 05 13.2 v Signal |__Vin | Threshold Voltage | 11 | DC COUPLING | fas |v Vor Output Low Voltage] 10-12-13 | Vop = 4.75 V 16-18-20 lou = 1.6 mA 21-22-23 a lou = 0.2 mA lou V Vop =4.75 V lou =1mA 2-3-4-26 Voo =4.75V lo. =5mA 27-28 | 24 [Von =475V ton =25ma | [| 8 | Vou Von = 4.75 V 24 v lon =~ 0.2 mA 15 lon =-1mA Vopz2 | Voo2 -0.2|-0.4 low | Output Leakage | 2-3-4-10-16 | Voo = 4.75 V Vo jot) = 9.25 V LA ‘Current 20-21--22-23 26-27-28 [24 [Vo =475V Vow =26v | | | 100 | ua | | te Input Low Current 12-13 Vop = 5.25 V A | Vo. =04 V High Impedance Vo =0 to Vop2 nA output Current [oor | Supply Curent | 6 [Voor =525v || | ma | [toe | Supply Gurrent |S | Vooe=525v TT 0 [ma | Memory Supply Ver =26V |wrte[ Peak [| | 40 | current [Average| | | 11 | Graso| Pak | | 7 | ng ett te

105 SCS-THOMSON

ey — | a 114

DYNAMIC ELECTRICAL CHARACTERISTICS [ Sympoi [Parameter Test Conditions | Min. | Tup. | Max. | Unit | | tox ['sactowtime ae P80 | SBC HGH Tine es oe [oss [OataSeup ting S| SSS Cd [tons | DataHos time Sd Time between SBE Rising Edge and OK of us Reception [tox | 0K of Recepon Time es ee Minimum SBC Delay Time from OK of Reception [15 [Propagaton Doty orpuc PSS | TIMING WAVEFORMS REGISTER LOAD ul ton S8E See [tesewe tenn enoid tone ‘SBD a ‘Osetus I" hold, tee prele, sau REGISTER READ o ame tenets | Ed sos | — G57 S&S:THOMSON iis “YU icromecrnomes 115

PRESCALER MODULO CONTROL TIMING +5 sts Pot PMc {1015/16 ‘duider) ts) sen INPUT AND OUTPUT CONFIGURATIONS SBC PDI Yon2 sue sese | CLIN RCIN | f sso

125 THOMSON

SBD, SBE DA1-DA6, B0-B3, OL, RCOUT Ypp2 l $5120 sus “Depletion ransistors PCO PMC, CLOUT, CLBUF Yoo2 ssa ssa 1 . 19/15 | 417

Remote Controlled TV Frequency Synthetizer. 709 | y~ 7 H Far “rh fr042320 M705 TLprescaver | M710 MODULO | ' CONTROL | ' int. ' TUNER i Ke i ' a FIUTER| 1 ' M206 BANO eee ite op | cua 6 oA Bist EET | M3870 — Ah ONIOF eT) SIOPIAEC Fraga ate —HFLYBACK Heeienaes Sa — vecereat viEWOATA ON/OFF sTFAEO s-s4son | ~ Remote Control Decoding by Microprocessor. +4 MHz Fine Tuning (62.5 kHz per Step) 7 32 Station Non-Volatile Memory or 30 Station. Automatic Search within Channel (using

1 Memory + Normalized D/A Positions TDA4433)

7 Flexible System Operation ~ AFC Operation (using TDA4433)

7 Frequency Synthesis of all Standard and CATV _-6 D/A Converters

Channels > Teletext and Viewdata Data Bus Conversion ~ Direct Channel Selection

1405 Gyy S88:THOMSON _

Remote Controlled TV Frequency Synthetizer and Clock Timer. A ofp — EARS CONTROL BUS, Lf 362 i LinreRRuer | \\|PRESCALER| 1 — ' H ene = : ' T LOOP i M3872. [Laec onrorr efawatoc” L_SZooaaca PONTROLS On srr SHOPIAES | 1944433 Fenn voaL ~ HOS oceeeetad STEREO. TELETEXT AND. VIEWOATA ON- oFt JcraNNeL /PROGH aM Frequency Synthesis as described in the Basic Configuration with the addition of : ~ Further Station Memory, using M120, 1 K NV MEMORY - Clock and programmable timer for automatic switch ON/OFF, using M755. | 15/15 THOMSON SIS G7 Sistema 1190