M1AFS1500-2FGG256PP

M7AFS600-1FGG256I ACTEL | Alldatasheet

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© 2008 Actel Corporation Actel Fusion Mixed-Signal FPGAs Family with Optional ARM® Support Features and Benefits High-Performance Reprogrammable Flash Technology

• Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process  Nonvolatile, Retains Program when Powered Off  Live at Power-Up (LAPU) Single-Chip Solution  350 MHz System Performance Embedded Flash Memory  User Flash Memory – 2 Mbits to 8 Mbits – Configurable 8-, 16-, or 32-Bit Datapath – 10 ns Access in Read-Ahead Mode  1 kbit of Additional FlashROM Integrated A/D Converter (ADC) and Analog I/O  Up to 12-Bit Resolution and up to 600 ksps  Internal 2.56 V or External Reference Voltage  ADC: Up to 30 Scalable Analog Input Channels  High-Voltage Input Tolerance: –10.5 V to +12 V  Current Monitor and Temperature Monitor Blocks  Up to 10 MOSFET Gate Driver Outputs – P- and N-Channel Power MOSFET Support – Programmable 1, 3, 10, 30 µA and 20 mA Drive Strengths  ADC Accuracy is Better than 1% On-Chip Clocking Support  Internal 100 MHz RC Oscillator (accurate to 1%)  Crystal Oscillator Support (32 kHz to 20 MHz)  Programmable Real-Time Counter (RTC)  6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated PLLs – Phase Shift, Multiply/Divide, and Delay Capabilities – Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz Low Power Consumption  Single 3.3 V Power Supply with On-Chip 1.5 V Regulator  Sleep and Standby Low Power Modes In-System Programming (ISP) and Security  Secure ISP with 128-Bit AES via JTAG F l a s h L o c k® to Secure FPGA Contents Advanced Digital I/O  1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation  Bank-Selectable I/O Voltages – Up to 5 Banks per Chip  Single-Ended I/O Standards: LVTTL, LVCMOS LVCMOS 2.5 V / 5.0 V Input  Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS – Built-In I/O Registers – 700 Mbps DDR Operation  Hot-Swappable I/Os  Programmable Output Slew Ra te, Drive Strength, and Weak Pull-Up/Down Resistor  Pin-Compatible Packages across the Fusion Family SRAMs and FIFOs  Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations available)  True Dual-Port SRAM (except ×18)  Programmable Embedded FIFO Control Logic Soft ARM7™ Core Support in M7 and M1 Fusion Devices  ARM Cortex™-M1 (without debug), CoreMP7Sd (with debug) and CoreMP7S (without debug) Fusion Family Fusion Devices AFS090 AFS250 AFS600 AFS1500 ARM-Enabled Fusion Devices CoreMP7 1 M7AFS600 Cortex-M1 2 M1AFS250 M1AFS600 M1AFS1500 General Information System Gates 90,000 250,000 600,000 1,500,000 Tiles (D-flip-flops) 2,304 6,144 13,824 38,400 Secure (AES) ISP Yes Yes Yes Yes PLLs 1 1 2 2 G l o b a l s 1 81 81 81 8 Memory Flash Memory Blocks (2 Mbits) 1 1 2 4 Total Flash Memory Bits 2 M 2 M 4 M 8 M FlashROM Bits 1 k 1 k 1 k 1 k RAM Blocks (4,608 bits) 6 8 24 60 RAM kbits 27 36 108 270 Analog and I/Os Analog Quads 5 6 10 10 Analog Input Channels 15 18 30 30 Gate Driver Outputs 5 6 10 10 I/O Banks (+ JTAG) 4 4 5 5 Maximum Digital I/Os 75 114 172 252 Analog I/Os 20 24 40 40 Notes: 1. Refer to the CoreMP7 datasheet for more information. 2. Refer to the Cortex-M1 product brief for more information. Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs II Preliminary v1.7 Fusion Device Architecture Overview Package I/Os: Single-/Double-Ended (Analog) Figure 1-1 • Fusion Device Architecture Overview (AFS600) Fusion Devices AFS090 AFS250 AFS600 AFS1500 ARM-Enabled Devices CoreMP7 M7AFS600 Cortex-M1 M1AFS250 M1AFS600 M1AFS1500 QN108 37/9 (16) QN180 60/16 (20) 65/15 (24) PQ208 93/26 (24) 95/46 (40) FG256 75/22 (20) 114/37 (24) 119/58 (40) 119/58 (40) FG484 172/86 (40) 223/109 (40) FG676 252/126 (40) Note: All devices in the same package are pin compatible with the exception of the PQ208 package (AFS250 and AFS600). VersaTile CCC CCC I/Os OSC CCC/PLL Bank 0 Bank 4 Bank 2 Bank 1 Bank 3 SRAM Block 4,608-Bit Dual-Port SRAM or FIFO Block SRAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Flash Memory Blocks Flash Memory BlocksADC Analog Quad ISP AES Decryption User Nonvolatile FlashROM Charge Pumps Analog Quad Analog Quad Analog Quad Analog Quad Analog Quad Analog Quad Analog Quad Analog Quad Analog Quad

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 III Product Ordering Codes Notes: 1. DC and switching characteristics for –F sp eed grade targets are based only on simulation. The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications . Some restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only supp orted in the commercial temperature range. 2. Quad Flat No Lead packages are on ly offered as RoHS compliant, QNG. M7AFS600 FG_ Part Number Fusion Devices Speed Grade Blank = Standard 1 = 15% Faster than Standard F = 20% Slower than Standard 2 = 25% Faster than Standard Package Type QN = Quad Flat No Lead (0.5 mm pitch) 256 IG Package Lead Count Application (ambient temperature range) Blank = Commercial (0 to +70°C) I = Industrial (–40 to +85°C) PP = Pre-Production ES = Engineering Silicon (room temperature only) 90,000 System Gates AFS090 = 250,000 System Gates AFS250 = ARM-Enabled Fusion Devices 600,000 System Gates AFS600 = 1,500,000 System GatesAFS1500 = 600,000 System Gates M7AFS600 = 250,000 System GatesM1AFS250 = 600,000 System GatesM1AFS600 = 1,500,000 System GatesM1AFS1500 = PQ = Plastic Quad Flat Pack (0.5 mm pitch) FG = Fine Pitch Ball Grid Array (1.0 mm pitch) Lead-Free Packaging Options Blank = Standard Packaging G = RoHS-Compliant (green) Packaging

Actel Fusion Mixed-Signal FPGAs IV Preliminary v1.7 Temperature Grade Offerings Speed Grade and Temperature Grade Matrix Contact your local Actel representative for device availability (http://www.actel.com/contact/offices/index.html). Fusion Devices AFS090 AFS250 AFS600 AFS1500 ARM-Enabled Devices CoreMP7 M7AFS600 Cortex-M1 M1AFS250 M1AFS600 M1AFS1500 QN108 C, I – – – QN180 C, I C, I – – PQ208 – C, I C, I – FG256 C, I C, I C, I C, I FG484 – – C, I C, I FG676 – – – C, I Notes: 1. C = Commercial Temperature Range: 0°C to 70°C Ambient 2. I = Industrial Temperature Ra nge: –40°C to 85°C Ambient 1 Std. –1 –2 C2 ✓✓✓✓ I3 – ✓✓✓ Notes: 1. DC and switching characteristics for –F speed grade targets are based only on simulation. The characteristics provided for the –F speed grade are subject to chan ge after establishing FPGA specificatio ns. Some restrictions might be added and will be reflected in future revisions of this document. The –F sp eed grade is only supp orted in the commercial temperature range. 2. C = Commercial Temperature Range: 0°C to 70°C Ambient 3. I = Industrial Temperature Ra nge: –40°C to 85°C Ambient

Preliminary v1.7 1-1 1 – Fusion Device Family Overview Introduction The Actel Fusion® mixed-signal FPGA satisfies the demand from system architects for a device that simplifies design and unleashes their creativity. As the world’s first mi xed-signal programmable logic family, Fusion integrates mixed-signal analog, flash memory, and FPGA fabric in a monolithic device. Actel Fusion devices enable designers to quickly move from conc ept to completed design and then deliver feature-rich systems to market . This new technology takes advantage of the unique properties of Actel flash-based FPGAs, including a high-isolation, triple-well process and the ability to support high-voltage transistors to meet the demanding requirements of mixed-signal system design. Actel Fusion mixed-signal FPGAs bring the benefits of programmable logic to many application areas, including power management, smart battery charging, clock generation and management, and motor control. Until now, these applications have only been implem ented with costly and space-consuming discrete analog components or mi xed-signal ASIC solutions. Actel Fusion mixed- signal FPGAs present new capabilities for system development by allowing designers to integrate a wide range of functionalit y into a single device, while at the same time offering the flexibility of upgrades late in the manufacturing process or after the device is in the fiel d. Actel Fusion devices provide an excellent alternative to costly and time-consuming mixed-si gnal ASIC designs. In addition, when used in conjunc tion with the Actel or ARM-ba sed soft MCU core, Actel Fusion technology represents the definitive mixed-signal FPGA platform. Flash-based Fusion devices are li ve at power-up. As soon as sy stem power is applied and within normal operating specifications, Fu sion devices are working. Fusion devices have a 128-bit flash- based lock and industry-leading AES decryption, us ed to secure programmed intellectual property (IP) and configuration data. Actel Fusion devices are the most comprehensive single-chip analog and digital programmable logic solution available today. To support this new ground-breaking technology , Actel has developed a series of major tool innovations to help maximize designer producti vity. Implemented as exte nsions to the popular Actel Libero ® Integrated Design Enviro nment (IDE), these new tool s allow design ers to easily instantiate and configure peripherals within a de sign, establish links between peripherals, create or import building blocks or reference designs, and perform hardware verification. This tool suite will also add comprehensive hardwa re/software debug capability as well as a suite of utilities to simplify development of embedded soft-processor-based solutions. General Description The Actel Fusion family, based on the highly successful ProASIC ®3 and ProASIC3E Flash FPGA architecture, has been designed as a high-perfo rmance, programmable, mixed-signal platform. By combining an advanced flash FPGA core with flash memory blocks and analog peripherals, Fusion devices dramatically simplify system design and, as a result, dramatically reduce overall system cost and board space. The state-of-the-art flash memory technology offe rs high-density integrated flash memory blocks, enabling savings in cost, power, and board area relative to external flash solutions, while providing increased flexibility and performance. The flash me mory blocks and integrated analog peripherals enable true mixed-mode programmable logic designs. Two examples are using an on-chip soft processor to implement a fully functional Flash MCU and using high-speed FPGA logic to offer system and power supervisory capabilities. Live at power-up and capable of operating from a single 3.3 V supply, the Fusion family is ideally suited for system management and control applications. The devices in the Fusion fami ly are categorized by FPGA core density. Each family member contains many peripherals, incl uding flash memory blocks, an an alog-to-digital-converter (ADC), high-drive outputs, both RC and crystal oscillators, and a real-time counter (RTC). This provides the

Fusion Device Family Overview 1-2 Preliminary v1.7 user with a high level of flexibility and integr ation to support a wide variety of mixed-signal applications. The flash memory bl ock capacity ranges from 2 Mbits to 8 Mbits. Th e integrated 12- bit ADC supports up to 30 independently configurable input channels. The on-chip crystal and RC oscillators work in conjunction with the integrated phase-locked loops (PLLs) to provide clocking support to the FPGA array and on-chip resources. In addition to supporting typical RTC uses such as watchdog timer, the Fusion RT C can control the on-chip voltag e regulator to power down the device (FPGA fabric, flash memory block, and ADC), enabling a low-power standby mode. The Actel Fusion family offers revolutionary features, never befo re available in an FPGA. The nonvolatile flash technology gives the Fusion solution the advantage of being a secure, low-power, single-chip solution that is live at power-up. Fu sion is reprogrammable and offers time to market benefits at an ASIC-level unit cost. These features enable design ers to create high-density systems using existing ASIC or FPGA design flows and tools. The family has up to 1.5 M system gates, supported with up to 270 kbits of true dual-port SRAM, up to 8 Mbits of flash memory, 1 kbit of user FlashROM, and up to 278 user I/Os. With integrated flash memory, the Fusion family is the ultimate soft-processor platform. The AFS600 and AFS1500 devices both support the Actel ARM7 core (CoreMP7). The ARM-enabled vers ions are identified with the M7 prefix as M7AFS600 and M7AFS1500. The AF S250, AFS600, and AFS1500 devices support the Actel Cortex-M1 core. The Cortex-M1-enabled vers ions are identified with the M1 prefix as M1AFS250, M1AFS600, and M1AFS1500. Flash Advantages Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, high performance, and ease of use. Flash- based Fusion devices are live at power-up and do not need to be loaded from an external boot PROM. On-board security mechanisms prevent access to the programming information and enable secure remote updates of the FPGA logic. De signers can perform secure remote in-system reprogramming to support future design iterat ions and field upgrades, with confidence that valuable IP cannot be compromi sed or copied. Secure ISP can be performed using the industry- standard AES algorithm with MAC data authentica tion on the device. The Fusion family device architecture mitigates the need for ASIC migratio n at higher user volume s. This makes the Fusion family a cost-effective ASIC replacement solution for applications in the consumer, networking and communications, computing, and avionics markets. Security As the nonvolatile, flash-based Fusion family requires no boot PROM, there is no vulnerable external bitstream. Fusion devices incorporate FlashLock, which pr ovides a unique combination of reprogrammability and design securi ty without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. Fusion devices utilize a 128-bit flash-based key lock and a separate AES key to secure programmed IP and configuration data. The FlashROM data in Fusion devices can also be encrypted prior to loading. Additionally, the Flash memory blocks can be programmed during runtime using the industry-leading AES-128 block cipher encryption standard (FIPS Publication 192). The AES standard was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the DES standard, which was adopted in 1977. Fusion devices have a built-in AES decryption engine and a flash-based AES key that make Fusion de vices the most comprehensive programmable logic device security solution available today. Fusion devices with AES-based security allow for secure remote field updates over public networks, such as the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP th ieves. As an additional security measure, the FPGA configuration data of a programmed Fusion device cannot be read back, although secure design verifi cation is possible. During design , the user controls and defines both internal and external access to the flash memory blocks. Security, built into the FPGA fabric , is an inherent component of th e Fusion family. The Flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. Fusion with FlashLock and AES security is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected,

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 1-3 making secure remote ISP possible. A Fusion de vice provides the most im penetrable security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (u nlike SRAM-based FPGAs). Therefore, flash-based Fusion FPGAs do not require system conf iguration components such as EEPROMs or microcontrollers to load device configuration da ta. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Live at Power-Up Flash-based Fusion devices are Level 0 live at power-up (LAPU). LAPU Fusion devices greatly simplify total system design and reduce total system cost by eliminating the need for CPLDs. The Fusion LAPU clocking (PLLs) replaces off-chip clocking resources. The Fusion mi x of LAPU clocking and analog resources makes these devi ces an excellent choice for both system supervisor and system management functions. LAPU from a single 3.3 V source enables Fusion devices to initiate, control, and monitor multiple voltage supplies while also providing system clocks. In addition, glitches and brownouts in system power will no t corrupt the Fusion device fl ash configuration. Unlike SRAM- based FPGAs, the device will not have to be reload ed when system power is restored. This enables reduction or complete removal of expensive voltage monitor and brownout detection devices from the PCB design. Flash-based Fusion devices simplify total system design and reduce cost and design risk, while increasing system reliability. Firm Errors Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. Another source of radiation-indu ced firm errors is alpha particles. For an alpha to cause a soft or firm error, its source must be in very close proxim ity to the affected circuit. The alpha source must be in the package molding compound or in the die itself. While low-alpha molding compounds are being used increasingly, this helps reduce but does not entirely eliminate alpha-induced firm errors. Firm errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not occur in Fusion Flash-based FPGAs. Once it is programmed, the flash cell config uration element of Fusion FPGA s cannot be altered by high- energy neutrons and is therefore immune to errors from them. Recoverable (or soft) errors occur in the user da ta SRAMs of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric. Low Power Flash-based Fusion devices exhibi t power characteristics similar to those of an ASIC, making them an ideal choice for power-sensitive applications. With Fusion devices, there is no power-on current surge and no high current transition, both of which occur on many FPGAs. Fusion devices also have low dynamic power consumption and support both low power standby mode and very low power sleep mode, offering further power savings. Advanced Flash Technology The Fusion family offers many benefits, including nonvolatility and reprogrammability through an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows very high logic utilization (much higher than competing SRAM technologies ) without compro mising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy.

Fusion Device Family Overview 1-4 Preliminary v1.7 Advanced Architecture The proprietary Fusion architecture provides granularity co mparable to standard-cell ASICs. The Fusion device consists of several distinct and pr ogrammable architectural features, including the following (Figure 1-1 on page 1-5):  Embedded memories – Flash memory blocks –F l a s h R O M – SRAM and FIFO  Clocking resources – PLL and CCC – RC oscillator – Crystal oscillator – No-Glitch MUX (NGMUX)  Digital I/Os with advanced I/O standards  FPGA VersaTiles  Analog components – ADC – Analog I/Os supporting voltage, current, and temperature monitoring – 1.5 V on-board voltage regulator – Real-time counter The FPGA core consists of a sea of VersaTiles. Ea ch VersaTile can be configured as a three-input logic lookup table (LUT) equivalent or a D-fl ip-flop or latch (with or without enable) by programming the appropriate flash switch interconne ctions. This versatility allows efficient use of the FPGA fabric. The VersaTile capability is uniq ue to the Actel families of flash-based FPGAs. VersaTiles and larger functions are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. In addition, extensive on-chip programming circ uitry allows for rapid (3.3 V) single-voltage programming of Fusion devices via an IEEE 1532 JTAG interface. Unprecedented Integration Integrated Analog Blocks and Analog I/Os Fusion devices offer robust and flex ible analog mixed-signal capabi lity in addition to the high- performance flash FPGA fabric and flash memory block. The many built-in analog peripherals include a configurable 32:1 input analog MUX, up to 10 independent MOSFET gate driver outputs, and a configurable ADC. The ADC supports 8-, 10-, and 12-bit modes of operation with a cumulative sample rate up to 600 k samples per second (ksps), differential nonlinearity (DNL) < 1.0 LSB, and Total Unadjusted Error (TUE) of 0.72 LSB in 10-bit mode. The TUE is used for characterization of the conversion error and includes errors from all sources, su ch as offset and linearity. Internal bandgap circui try offers 1% voltage reference accuracy with the flexibility of utilizing an external reference voltage. The ADC channel sampling sequence and sampling rate are programmable and implemented in the FPGA logi c using Designer and Li bero IDE software tool support. Two channels of the 32-channel ADCMUX are dedica ted. Channel 0 is conn ected internally to V CC and can be used to monitor core power supply. Channel 31 is connected to an internal temperature diode which can be used to monitor device te mperature. The 30 rema ining channels can be connected to external an alog signals. The exact number of I/ Os available for external connection signals is device-dependent (refer to the "Fusion Family" table on page I for details).

Fusion Device Family Overview 1-6 Preliminary v1.7 flash operation without wait states. The memory block is organized in pages and sectors. Each page has 128 bytes, with 33 pages comprising one sector and 64 sectors per block. The flash block can support multiple partitions. The only constrai nt on size is that partition boundaries must coincide with page boundaries. The flexibility and granularity enable many use models and allow added granularity in programming updates. Fusion devices support two methods of external access to the flash memory blocks. The first method is a serial interface that features a bu ilt-in JTAG-compliant port, which allows in-system programmability during user or monitor/test modes. This serial interface supports programming of an AES-encrypted stream. Secure da ta can be passed through the JTAG interface, decrypted, and then programmed in the flash block. The second method is a soft parallel interface. FPGA logic or an on-chip soft microprocessor can access flash memory through the parallel interface. Since the flash parallel interface is implemented in the FPGA fabric, it can potentially be customized to meet special user requirem ents. For more information, refer to the CoreCFI Handbook. The flash memory parallel interface provid es configurable byte -wide (×8), word-wide (×16), or dual-word-wide (×32) data port options. Through the programmable flash parallel interface, the on-chip and off-chip memories can be cascaded for wider or deeper configurations. The flash memory has built-in secu rity. The user can configure either the entire flash block or the small blocks to prevent unintentional or intr usive attempts to change or destroy the storage contents. Each on-chip flash memory block ha s a dedicated controller, enabling each block to operate independently. The flash block logic consists of the following sub-blocks:  Flash block – Contains all stored data. The flash block contains 64 sectors and each sector contains 33 pages of data.  Page Buffer – Contains the contents of the cu rrent page being modified. A page contains 8 blocks of data.  Block Buffer – Contains the contents of th e last block accessed. A block contains 128 data bits.  ECC Logic – The flash memory stores erro r correction information with each block to perform single-bit error correction and double-bit error detection on all data blocks. User Nonvolatile FlashROM In addition to the flash blocks, Actel Fusion de vices have 1 kbit of user-accessible, nonvolatile FlashROM on-chip. The FlashROM is organized as 8×128-bit pages. The FlashROM can be used in diverse system applications:  Internet protocol addressing (wireless or fixed)  System calibration settings  Device serialization and/or inventory control  Subscription-based business mode ls (for example, set-top boxes)  Secure key storage for secu re communications algorithms  Asset management/tracking  Date stamping  Version management The FlashROM is written using the standard IE EE 1532 JTAG programming interface. Pages can be individually programmed (erased and written). On-chip AES decryption can be used selectively over public networks to securely load data such as security keys st ored in the Flas hROM for a user design. The FlashROM can be programmed (erased and wri tten) via the JTAG programming interface, and its contents can be read back either through th e JTAG programming interface or via direct FPGA core addressing. The FlashPoint tool in the Actel Fusion developm ent software solutions, Libero IDE and Designer, has extensive support for flash memory blocks and FlashROM. One such feature is auto-generation of sequential programmin g files for applicat ions requiring a unique se rial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using the Actel Libero IDE and Designer software

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 1-7 tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. SRAM and FIFO Fusion devices have embedded SRAM blocks alon g the north and south sides of the device. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be written through a 4-bit port and read as a single bitstre am. The SRAM blocks can be initialized from the flash memory blocks or via the device JTAG port (ROM emulation mode), using the UJTAG macro. In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FI FO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal EMPTY and FULL flags. The embedded FIFO control unit contains the counte rs necessary for the genera tion of the read and write address pointers. The SRAM/FIFO blocks can be cascaded to create larger configurations. Clock Resources PLLs and Clock Conditioning Circuits (CCCs) Fusion devices provide designers with very flexible clock conditioning capabilities. Each member of the Fusion family contains six CCCs. In the two larger family members, two of these CCCs also include a PLL; the smaller devices support one PLL. The inputs of the CCC blocks are accessible from the FPGA core or from one of several inputs with dedicated CCC block connections. The CCC block has the following key features:  Wide input frequency range (f IN_CCC) = 1.5 MHz to 350 MHz  Output frequency range (f OUT_CCC) = 0.75 MHz to 350 MHz  Clock phase adjustment via pr ogrammable and fixed delays from –6.275 ns to +8.75 ns  Clock skew minimization (PLL)  Clock frequency synthesis (PLL)  On-chip analog clocking resources usable as inputs: – 100 MHz on-chip RC oscillator – Crystal oscillator Additional CCC specifications:  Internal phase shift = 0°, 90°, 180°, and 270°  Output duty cycle = 50% ± 1.5%  Low output jitter. Samples of peak-to-peak period jitter when a single global network is used: – 70 ps at 350 MHz – 90 ps at 100 MHz – 180 ps at 24 MHz – Worst case < 2.5% × clock period  Maximum acquisition time = 150 µs  Low power consumption of 5 mW Global Clocking Fusion devices have exte nsive support for multiple clocking domains. In addition to the CCC and PLL support described above, there are on-chip oscillators as well as a comprehensive global clock distribution network. The integrated RC oscillator generates a 100 MHz cl ock. It is used internally to provide a known clock source to the flash memory read and write control. It can also be used as a source for the PLLs.

Fusion Device Family Overview 1-8 Preliminary v1.7 The crystal oscillator supports the following operating modes:  Crystal (32.768 kHz to 20 MHz)  Ceramic (500 kHz to 8 MHz)  RC (32.768 kHz to 4 MHz) Each VersaTile input and output port has access to nine VersaNets: six main and three quadrant global networks. The VersaNets can be driven by the CCC or directly acce ssed from the core via MUXes. The VersaNets can be used to distribute lo w-skew clock signals or for rapid distribution of high-fanout nets. Digital I/Os with Advanced I/O Standards The Fusion family of FPGAs features a flexible digital I/O structure, supporting a range of voltages single-ended and differential. The I/Os are organized into banks, with four or five banks per device. The configuration of these banks determines the I/O standards supported. Th e banks along the east and west sides of the device support the full range of I/O standards (single-ended and differ ential). The south bank supports the Analog Quads (analog I/O). In th e family's two smaller devices, the north bank supports multiple single-ended digital I/O standards. In the family’s larger devices, the north bank is divided into two banks of digital Pro I/Os, supporting a wide variety of single-ended, differential, and voltage-referenced I/O standards. Each I/O module contains several input, output , and enable registers. These registers allow the implementation of the following applications:  Single-Data-Rate (S DR) applications  Double-Data-Rate (DDR) applications—DDR LVDS I/O for chip-to-chip communications  Fusion banks support LVPECL, LVDS, BLVDS, and M-LVDS with 20 multi-drop points. VersaTiles The Fusion core consists of VersaTiles, which are also used in the successful Actel ProASIC3 family. The Fusion VersaTile supports the following:  All 3-input logic functions—LUT-3 equivalent  Latch with clear or set  D-flip-flop with clear or set and optional enable Refer to Figure 1-2 for the VersaTile configuration arrangement. Figure 1-2  VersaTile Configurations YX2 LUT-3 Data Y CLK Enable CLR D-FFE Data Y CLK CLR D-FF LUT-3 Equivalent D-Flip-Flop with Clear or Set Enable D-Flip-Flop with Clear or Set

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 1-9 Related Documents Application Notes Fusion FlashROM http://www.actel.com/documents/Fusion_FROM_AN.pdf Fusion SRAM/FIFO Blocks http://www.actel.com/documents/Fusion_RAM_FIFO_AN.pdf Using DDR in Fusion Devices http://www.actel.com/documents/Fusion_DDR_AN.pdf Fusion Security http://www.actel.com/documents/Fusion_Security_AN.pdf Using Fusion RAM as Multipliers http://www.actel.com/documents/Fusion_Multipliers_AN.pdf Prototyping with AFS600 for Smaller Devices http://www.actel.com/documents/Fusion_Prototyp_AN.pdf UJTAG Applications in Actel’s Low-Power Flash Devices http://www.actel.com/documents/LPD_UJTAG_HBs.pdf In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 http://www.actel.com/documents/LPD_ISP_HBs.pdf Handbook Fusion Handbook http://www.actel.com/documents/Fusion_HB.pdf User’s Guides Designer User's Guide http://www.actel.com/documents/designer_UG.pdf Fusion, IGLOO/e and ProASIC3/E Macro Library Guide http://www.actel.com/documents/pa3_libguide_ug.pdf SmartGen, FlashROM, Flash Memory System Builder, and Analog System Builder User's Guide http://www.actel.com/documents/genguide_ug.pdf White Papers Fusion Technology http://www.actel.com/documents/Fusion_Tech_WP.pdf

Fusion Device Family Overview 1-10 Preliminary v1.7 Part Number and Revision Date Part Number 51700092-013-0 Revised October 2008 List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Curr ent Version (Preliminary v1.7) Page Advance v1.6 (August 2008) The version number category was changed from Advance to Preliminary, which means the datasheet contains informatio n based on simulation and/or initial characterization. The information is be lieved to be correct, but changes are possible. Advance v1.4 (July 2008) The title of the datasheet changed fr om Actel Programmable System Chips to Actel Fusion Mixed- Signal FPGAs. In addition, all instances of programmable system chip were changed to mixed-signal FPGA. N/A Advance v0.9 (October 2007) The following bullet was updated from High-Voltage Input Tolerance: ±12 V to High-Voltage Input Tolerance: 10.5 V to 12 V. I The following bullet was updated from Programmable 1, 3, 10, 30 µA and 25 mA Drive Strengths to Programmable 1, 3, 10, 30 µA and 20 mA Drive Strengths. I This bullet was added to the "Integrated A/D Converter (ADC) and Analog I/O" section: ADC Accuracy is Better than 1% I In the "Integrated Analog Blocks and Analog I/Os" section, ±4 LSB was changed to 0.72. The following sentence was deleted: The input range for voltage signals is from –12 V to +12 V with full-scale output values from 0.125 V to 16 V. In addition, 2°C was changed to 3°C: "One analog input in each quad can be connected to an external temperature monitor diode and achieves detection accuracy of ±3ºC." The following sentence was deleted: The input range for voltage signals is from –12 V to +12 V with full-scale output values from 0.125 V to 16 V. 1-4 Advance v0.7 (January 2007) In the "Package I/Os: Single-/Double-Ended (Analog)" table , the AFS1500/M7AFS1500 I/O counts were updated for the following devices: FG484: 223/109 FG676: 252/126 II Advance v0.4 (April 2006) The AFS1500 digital I/O count was updated in the "Fusion Family" table. I The AFS1500 digital I/O co unt was updated in the "Package I/Os: Single- /Double-Ended (Analog)" table. II Advance v0.3 (April 2006) The G was moved in the "Product Ordering Codes" section. III Advance v0.2 (April 2006) The "Features and Benefits" section was updated. I The "Fusion Family" table was updated. I The "Package I/Os: Single-/Double-Ended (Analog)" table was updated. II

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 1-11 Advance v0.2 (continued) The "Product Ordering Codes" table was updated. III The "Temperature Grade Offerings" table was updated. IV The "General Description" section was updated to include ARM information. 1-1 Previous Version Changes in Curr ent Version (Preliminary v1.7) Page

Fusion Device Family Overview 1-12 Preliminary v1.7 Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advance," "Preliminary," and "Production." The definition of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document give s an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on si mulation and/or initia l characterization. The information is believed to be correct, but changes are possible. Unmarked (production) This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this do cument are subject to the Expo rt Administration Regulations (EAR). They could require an ap proved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status document may not have completed Actel’s qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functional ity or performance. It is the responsibility of each customer to ensure the fitn ess of any Actel product (but especially a new product) for a particular purpose, including appr opriateness for safety-cri tical, life-s upport, and other high-reliability applicatio ns. Consult Actel’s Terms and Cond itions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel’s products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information.

Preliminary v1.7 2-1 2 – Device Architecture Fusion Stack Architecture To manage the unprecedented level of integratio n in Fusion devices, Ac tel developed the Fusion technology stack ( Figure 2-1). This layered model offers a fl exible design environment, enabling design at very high and very low levels of abstra ction. Fusion peripheral s include hard analog IP and hard and soft digital IP. Perip herals communicate across the FPGA fabric via a layer of soft gates—the Fusion backbone. Much more than a common bus interface, this Fusion backbone integrates a micro-sequencer within the FPGA fabric and configures the individual peripherals and supports low-level processing of peripheral da ta. Fusion applets are application building blocks that can control and respond to peripherals and other system si gnals. Applets can be rapidly combined to create large applicatio ns. The technology is scalable across devices, families, design types, and user expertise, and supports a well -defined interface for external IP and tool integration. At the lowest level, Level 0, ar e Fusion peripherals. These are conf igurable functional blocks that can be hardwired structures such as a PLL or anal og input channel, or soft (FPGA gate) blocks such as a UART or two-wire serial interface. The Fusi on peripherals are configurable and support a standard interface to facilitate communication and implementation. Connecting and controlling access to the peripherals is the Fusion backbone, Level 1. The backbone is a soft-gate structure, scalable to any number of peripherals. The backbone is a bus and much more; it manages peripheral configuration to en sure proper operation. Leveraging the common peripheral interface and a low-lev el state machine, the backbone efficiently offloads peripheral management from the system design. The backbone can set and clear flags based upon peripheral behavior and can define performa nce criteria. The flexibility of the stack enables a designer to configure the silicon, directly bypassing the backbone if that level of control is desired. One step up from the backbone is the Fusion applet, Level 2. The applet is an application building block that implements a specific function in FPGA gates. It can react to stimuli and board-level events coming through the backbone or from ot her sources, and respon ds to these stimuli by accessing and manipulating peripherals via the backbone or initiating some other action. An applet controls or responds to the peri pheral(s). Applets can be easily imported or exported from the design environment. The applet structure is open and well-def ined, enabling users to import applets from Actel, system developers, third parties, and user groups. Note: Levels 1, 2, and 3 are implemented in FPGA logic gates. Figure 2-1  Fusion Architecture Stack Flash Memory Analog Smart Peripheral 1 Analog Smart Peripheral 2 Analog Smart Peripheral n Smart Peripherals in FPGA Fabric (e.g., logic, PLL, FIFO) Fusion Smart Backbone Fusion Applets User Applications Level 1 Level 0 Level 2 Level 3 Optional ARM or 8051 Processor

2-2 Preliminary v1.7 The system application, Level 3, is the larger us er application that utili zes one or more applets. Designing at the highest level of abstraction supp orted by the Actel Fusion technology stack, the application can be easily created in FPGA gates by importing and configuring multiple applets. In fact, in some cases an entire FPGA system design can be created without any HDL coding. An optional MCU enables a combination of softw are and HDL-based design methodologies. The MCU can be on-chip or off-chip as system requirem ents dictate. System portioning is very flexible, allowing the MCU to reside abov e the applets or to absorb appl ets, or applets and backbone, if desired. The Actel Fusion technology stack enables a very flexible design environment. Users can engage in design across a continuum of abstraction from very low to very high. Core Architecture VersaTile Based upon successful Actel ProASIC3/E logic ar chitecture, Fusion devices provide granularity comparable to gate arrays. The Fusion device core consists of a sea-of-VersaTiles architecture. As illustrated in Figure 2-2, there are four inputs in a logic VersaTile cell, and each VersaTile can be configured using the appropriate flash switch connections:  Any 3-input logic function  Latch with clear or set  D-flip-flop with clear or set  Enable D-flip-flop with clear or set (on a 4th input) VersaTiles can flexibly map the logic and sequenti al gates of a design. The inputs of the VersaTile can be inverted (allowing bubble pushing), and th e output of the tile can connect to high-speed, very-long-line routing resources. VersaTiles and larger functions are connected with any of the four levels of routing hierarchy. When the VersaTile is used as an enable D-flip-f lop, the SET/CLR signal is supported by a fourth input, which can only be routed to the core cell over the VersaNet (global) network.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-3 The output of the VersaTile is F2 when the connection is to the ultra-fast local lines, or YL when the connection is to the efficient long-line or very-long-line resources (Figure 2-2). Note: *This input can only be connected to the global clock distribution network. Figure 2-2  Fusion Core VersaTile Switch (flash connection) GroundVia (hard connection)Legend: Y Pin 1 Data CLK CLR/ Enable CLR XC* YL

2-4 Preliminary v1.7 VersaTile Characteristics Sample VersaTile Specifications—Combinatorial Module The Fusion library offers all combin ations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library ( Figure 2-3). For more details, refer to the Fusion, IGLOO/e and ProASIC3/E Macro Library Guide. Figure 2-3  Sample of Combinatorial Cells MAJ3 A C BY MUX2 B A S Y AY B B A XOR2 Y NOR2 B A Y B A YOR2 INV A YAND2 B A Y NAND3B A C XOR3 YB A C NAND2

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-5 Figure 2-4  Combinatorial Timing Model and Waveforms tPD tPD tPD VCCA VCCA tPD tPD VCCA tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)) where edges are applicable for the particular combinatorial cell NAND2 or Any Combinatorial Logic A B Y (RR) A, B, C OUT 50% GND (FF) 50% 50%50% GND (RF) 50% (FR) 50% OUT GND

2-6 Preliminary v1.7 Timing Characteristics Sample VersaTile Specifications—Sequential Module The Fusion library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from the library ( Figure 2-5). For more details, refer to the Fusion, IGLOO/e and ProASIC3/E Macro Library Guide. Table 2-1  Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Combinatorial Cell Equation Parameter –2 –1 Std. Units INV Y = !A t PD 0.40 0.46 0.54 ns AND2 Y = A · B t PD 0.47 0.54 0.63 ns NAND2 Y = !(A · B) t PD 0.47 0.54 0.63 ns OR2 Y = A + B t PD 0.49 0.55 0.65 ns NOR2 Y = !(A + B) t PD 0.49 0.55 0.65 ns XOR2 Y = A ⊕ Bt PD 0.74 0.84 0.99 ns MAJ3 Y = MAJ(A, B, C) t PD 0.70 0.79 0.93 ns XOR3 Y = A ⊕ B ⊕ Ct PD 0.87 1.00 1.17 ns MUX2 Y = A !S + B S t PD 0.51 0.58 0.68 ns AND3 Y = A · B · C t PD 0.56 0.64 0.75 ns Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

2-8 Preliminary v1.7 Sequential Timing Characteristics Table 2-2  Register Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tCLKQ Clock-to-Q of the Core Register 0.55 0.63 0.74 ns tSUD Data Setup Time for the Core Register 0.43 0.49 0.57 ns tHD Data Hold Time for the Core Register 0.00 0.00 0.00 ns tSUE Enable Setup Time for the Core Register 0.45 0.52 0.61 ns tHE Enable Hold Time for the Core Register 0.00 0.00 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.40 0.45 0.53 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.40 0.45 0.53 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 0.00 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.22 0.25 0.30 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 0.00 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.22 0.25 0.30 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.22 0.25 0.30 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.22 0.25 0.30 ns tCKMPWH Clock Minimum Pulse Width HIGH for the Core Register 0.32 0.37 0.43 ns tCKMPWL Clock Minimum Pulse Width LOW for the Core Register 0.36 0.41 0.48 ns Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

2-10 Preliminary v1.7 Routing Architecture The routing structure of Fusion devices is designed to provide high performance through a flexible four-level hierarchy of routing re sources: ultra-fast local resource s; efficient long-line resources; high-speed very-long-line resources; and the high-performance VersaNet networks. The ultra-fast local resources are dedicated lines that allow the output of each VersaTile to connect directly to every input of the eight surrounding VersaTiles (Figure 2-8). The exception to this is that the SET/CLR input of a VersaTile configured as a D-flip-flop is driven only by the VersaNet global network. The efficient long-line resour ces provide routing for longer distance s and higher-fanout connections. These resour ces vary in length (spanning one, two, or four VersaTiles), run both vertically and horizontally, and co ver the entire Fu sion device ( Figure 2-9 on page 2-11 ). Each VersaTile can drive signals onto the efficient lo ng-line resources, which can access every input of every VersaTile. Active buffers are inserted auto matically by routing software to limit loading effects. The high-speed very-long-line resources, which span the entire device with minimal delay, are used to route very long or high-fanout nets: length +/ –12 VersaTiles in the vertical direction and length +/–16 in the horizontal direction from a given core VersaTile ( Figure 2-10 on page 2-12). Very long lines in Fusion devices, like those in ProASIC3 devices, have been enhanced. This provides a significant performance boost for long-reach signals. The high-performance VersaNet global networks are low-skew, high-fanout nets that are accessible from external pins or from internal logic (Figure 2-11 on page 2-13). These nets are typically used to distribute clocks, reset signals, and other high -fanout nets requiring minimum skew. The VersaNet networks are implemented as clock trees, and signals can be introduced at any junction. These can be employed hierarchically, with signals accessing every input on all VersaTiles. Global Resources (VersaNets) Fusion devices offer powerful and flexible control of circuit timing through the use of analog circuitry. Each chip has six CCCs. Th e west CCC also contains a PLL core. In the two larger devices Note: Input to the core cell for the D-flip-flop set and reset is only available via the VersaNet global network connection. Figure 2-8  Ultra-Fast Local Lines Connected to the Eight Nearest Neighbors L L L LL L Inputs Output Ultra-Fast Local Lines (connects a VersaTile to the adjacent VersaTile, I/O buffer, or memory block) L LL Long Lines

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-11 (AFS600 and AFS1500), the west and the east CCCs each contain a PLL. The PLLs include delay lines, a phase shifter (0°, 90°, 180°, 270°), and clock mu ltipliers/dividers. Each CCC has all the circuitry needed for the selection and interconnection of inputs to the VersaNet global network. The east and west CCCs each have access to three VersaNet glob al lines on each side of the chip (six lines total). The CCCs at the four co rners each have access to thre e quadrant global lines on each quadrant of the chip. Advantages of the VersaNet Approach One of the architectural benefits of Fusion is the set of powe rful and low-delay VersaNet global networks. Fusion offers six chip (main) global networks that are distributed from the center of the FPGA array (Figure 2-11). In addition, Fusion devices have three regional globals (quadrant globals) in each of the four chip quadrants. Each core VersaTile has access to nine global network resources: three quadrant and six chip (main) global networks. There are a total of 18 global networks on the device. Each of these networks contains spines an d ribs that reach all VersaTiles in all quadrants (Figure 2-12 on page 2-14). This flexible VersaNet global network architecture allows users to map up to 180 different internal/external clocks in a Fusion device. Details on the VersaNet networks are given in Table 2-4 on page 2-14. The flexibility of the Fusion Ve rsaNet global network allows the designer to address several design requirements. User applications that are clock-resource-intensive can easily route external or gated internal cl ocks using VersaNet global routing networks. Designers can also drastically re duce delay penalties and minimi ze resource usage by mapping critical, high-fanout nets to the VersaNet global network. Figure 2-9  Efficient Long-Line Resources LL LLLL LLL L L L LL LLLL LL LLLL LL LLLL Spans One VersaTile Spans Two VersaTiles Spans Four VersaTiles Spans One VersaTileSpans Two VersaTiles Spans Four VersaTiles VersaTile

2-12 Preliminary v1.7 Figure 2-10  Very-Long-Line Resources High-Speed, Very-Long-Line Resources Pad Ring Pad Ring I/O Ring I/O Ring 16×12 Block of VersaTiles SRAM

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-13 Figure 2-11  Overview of Fusion VersaNet Global Network Main (chip) Global Network Top Spine Bottom Spine Pad Ring Pad Ring I/O Ring I/O Ring Chip (main) Global Pads Global Pads High-Performance VersaNet Global Network Global Spine Global Ribs Spine-Selection Tree MUX Quadrant Global Pads

2-14 Preliminary v1.7 Figure 2-12  Global Network Architecture Table 2-4  Globals/Spines/Rows by Device AFS090 AFS250 AFS600 AFS1500 Global VersaNets (trees)* 9 9 9 9 VersaNet Spines/Tree 4 8 12 20 Total Spines 36 72 108 180 VersaTiles in Each Top or Bottom Spine 384 768 1,152 1,920 Total VersaTiles 2,304 6,144 13,824 38,400 Note: *There are six chip (main) globals and three globals per quadrant. Northwest Quadrant Global Network Southeast Quadrant Global Network Chip (main) Global Network 33 3 3 33 3 Global Spine Quadrant Global Spine CCC CCC CCC CCC CCC CCC

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-15 VersaNet Global Networks and Spine Access The Fusion architecture contains a total of 18 segmented global networks that can access the VersaTiles, SRAM, and I/O tiles on the Fusion devi ce. There are 6 chip (main) global networks that access the entire device and 12 quadrant networks (3 in each quadrant). Each device has a total of 18 globals. These VersaNet global networks offer fast, low-skew routing resources for high-fanout nets, including clock signals. In addition, these highly segmented global networks offer users the flexibility to create low-skew local networks using spines for up to 180 inte rnal/external clocks (in an AFS1500 device) or other high -fanout nets in Fusion devices. Optimal usage of these low-skew networks can result in significant improvement in design performance on Fusion devices. The nine spines available in a vert ical column reside in global ne tworks with two separate regions of scope: the quadrant global network, which has three spines, and the chip (main) global network, which has six spines. Note that there are three quadrant spines in each quadrant of the device. There are four quadrant global network regions per device (Figure 2-12 on page 2-14). The spines are the vertical branches of the global network tree, shown in Figure 2-11 on page 2-13. Each spine in a vertical co lumn of a chip (main) global network is further divided into two equal- length spine segments: one in the top and one in the bottom half of the die. Each spine and its associated ribs cover a certain area of the Fusi on device (the "scope" of the spine; see Figure 2-11 on page 2-13). Each spine is accessed by the dedicated global network MUX tree architecture, which defines how a particular spine is driven—either by the signal on the global network from a CCC, for example, or another net defined by the user ( Figure 2-13). Quadrant spines can be driven from user I/Os on the north and south sides of the die, via analog I/Os configured as direct digital inputs. The ability to drive spines in the quadrant global networks can have a significant effect on system performance for high-fanout inputs to a design. Details of the chip (main) global network spine-selection MUX are presented in Figure 2-13. The spine drivers for each spine are located in the middle of the die. Quadrant spines are driven from a north or south rib. Access to the top and bottom ribs is from the corner CCC or from the I/Os on the north and sout h sides of the device. For details on using spines in Fusion devices, see the Actel application note Using Global Resources in Actel Fusion Devices. Figure 2-13  Spine-Selection MUX of Global Tree Internal/External Signal Internal/External Signal Internal/External Signals Spine Global Rib Global Driver MUX Tree Node MUX Tree Node MUX Internal/External Signals Tree Node MUX

2-16 Preliminary v1.7 Clock Aggregation Clock aggregation allows for mu lti-spine clock domains. A MU X tree provides the necessary flexibility to allow long lines or I/Os to access do mains of one, two, or four global spines. Signal access to the clock aggregation system is achieved through long-line resources in the central rib, and also through local resources in the north and south ribs, allowing I/Os to feed directly into the clock system. As Figure 2-14 indicates, this access system is contiguous. There is no break in the middle of the chip for north and south I/O VersaNet access. This is different from the quadrant clocks, located in these ribs, which only reach the middle of the rib.Refer to the Using Global Resources in Actel Fusion Devices application note. Figure 2-14  Clock Aggregation Tree Architecture Global Spine Global Rib Global Driver and MUX I/O Access Internal Signal Access I/O Tiles Global Signal Access Tree Node MUX

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-17 Global Resource Characteristics AFS600 VersaNet Topology Clock delays are device-specific. Figure 2-15 is an example of a global tree used for clock routing. The global tree presented in Figure 2-15 is driven by a CCC located on the west side of the AFS600 device. It is used to drive all D-flip-flops in the device. Figure 2-15  Example of Global Tree Use in an AFS600 Device for Clock Routing Central Global Rib VersaTile Rows Global Spine CCC

2-18 Preliminary v1.7 VersaNet Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are dependent upon I/O standard, and the clock may be driven and conditioned internally by the CCC module. Table 2-5, Table 2-6, Table 2-7, and Table 2-8 on page 2-19 present minimum and maximum gl obal clock delays within the device.Minimum and maximum delays are me asured with minimum and maximu m loading, respectively. Timing Characteristics Table 2-5  AFS1500 Global Resource Timing Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.34 ns FRMAX Maximum Frequency for Global Clock MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9. Table 2-6  AFS600 Global Resource Timing Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock 0.27 0.31 0.36 ns FRMAX Maximum Frequency for Global Clock MHz Notes: 1. Value reflects minimum load. The de lay is measured from the CCC output to the clock pin of a sequential element located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The de lay is measured on the clock pin of the farthest se quential element located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-19 Table 2-7  AFS250 Global Resource Timing Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock 0.26 0.30 0.35 ns FRMAX Maximum Frequency for Global Clock MHz Notes: 1. Value reflects minimum load. The de lay is measured from the CCC output to the clock pin of a sequential element located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The de lay is measured on the clock pin of the farthest se quential element located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9. Table 2-8  AFS090 Global Resource Timing Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock 0.27 0.30 0.36 ns FRMAX Maximum Frequency for Global Clock MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the fa rthest sequential element located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

2-20 Preliminary v1.7 Clocking Resources The Fusion family has a robust coll ection of clocking peripherals, as shown in the block diagram in Figure 2-16. These on-chip resources enable the creati on, manipulation, and distribution of many clock signals. The Fusion integrated RC oscillator produces a 100 MHz clock source with no external components. For systems requiring more precise clock si gnals, the Actel Fusion family supports an on-chip crystal oscillator circuit. The integrated PLLs in each Fusion device can use the RC oscillator, crystal oscillator, or another on-chip clock sign al as a source. These PLLs offer a variety of capabilities to modify th e clock source (multiply, divide, synchr onize, advance, or delay). Utilizing the CCC found in the popular Actel ProASIC3 fam ily, Fusion incorporates six CCC blocks. The CCCs allow access to Fusion global and local clock distribution nets, as described in the "Global Resources (VersaNets)" section on page 2-10. Figure 2-16  Fusion Clocking Options Clock Out to FPGA Core through CCC GLINT GNDOSC On-ChipOff-Chip VCCOSC Crystal Oscillator Clock I/OsExternal Crystal External RC Xtal Clock PLL/ CCC GLA To Core CLKOUT NGMUX GLC From FPGA Core

100 MHz

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-21 RC Oscillator The RC oscillator is an on-chip free-running clock source generating a 100 MHz clock. It can be used as a source clock for both on-chip and off-chip resources. When used in conjunction with the Fusion PLL and CCC circuits, the RC oscillator clock source can be used to generate clocks of varying frequency and phase. The Fusion RC oscillator is very accurate at ±1% over commercial and industrial temperature ranges. It is an automated clock, requiring no se tup or configuration by the user. It requires only that the power and GNDOSC pins be connected; no external components are required. The RC oscillator can be used to drive either a PLL or another internal signal. RC Oscillator Characteristics Table 2-9  Electrical Characteristics of RC Oscillator Parameter Description Condi tions Min. Typ. Max. Units FRC Operating Frequency Accuracy Temperature: 0°C to 85°C Voltage: 3.3 V ± 5% Temperature: –40°C to 125°C Voltage: 3.3 V ± 5% Output Jitter Peri od Jitter (at 5 k cycles) 100 ps Cycle–Cycle Jitter (at 5 k cycles) 100 ps Period Jitter (at 5 k cycles) with 1 kHz / 300 mV peak-to-peak noise on power supply 150 ps Cycle–Cycle Jitter (at 5 k cycles) with 1 kHz / 300 mV peak-to-peak noise on power supply 150 ps Output Duty Cycle 50 % I DYNRC Operating Current 1 mA

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-23 In Modes 1 to 3, the crystal oscillator is config ured to support an external crystal or ceramic resonator. These modes correspond to low, medium , and high gain. They differ in the crystal or resonator frequency supported. The crystal or resonator is connected to the XTAL1 and XTAL2 pins. Additionally, a capacitor is required on both XTAL1 and XTAL2 pins to ground ( Figure 2-16 on page 2-20). Table 2-10 on page 2-22 details each crystal oscillat or mode, supported frequency range, and recommended capacitor value. A use model supported by the Fusion device in volves powering down the core while the RTC continues to run, clocked by the crystal oscillator. When powered down, the core cannot control crystal oscillator mode pins. Also, some designers may wish to avoid the RTC altogether. To support both situations, the crystal oscillator can be cont rolled by either the RTC or the FPGA core. If the RTC is instantiated in the design, it will by defa ult use RTCMODE[1:0] to set the crystal oscillator control pins (the default). If the RTC is not used in the design, the FPGA co re will set the crystal oscillator control pins with MODE[1:0]. The crystal oscillator can be disa bled/enabled by RTC or FPGA upon operation requirement. When the crystal oscillator is disabled, XTL1 and XTL2 pins can be left floating. Crystal Oscillator Characteristics Table 2-11  Electrical Characteristics of the Crystal Oscillator Parameter Description Conditions Min. Typ. Max. Units FXTAL Operating Frequency Using External Crystal 0.032 20 MHz Using Ceramic Resonator 0.5 8 MHz Using RC Network 0.032 4 MHz Output Duty Cycle 50 % Output Jitter With 10 MHz Crystal 50 ps RMS IDYNXTAL Operating Current RC 0.6 mA 0.032–0.2 MHz 0.19 mA 0.2–2.0 MHz 0.6 mA 2.0–20.0 MHz 0.6 mA ISTBXTAL Sleep Current 10 µA PSRRXTAL Power Supply Noise Tolerance

0.5 Vp–p

VIHXTAL Input Logic Level HIGH 90% of V CC V VILXTAL Input Logic Level LOW 10% of V CC V

2-24 Preliminary v1.7 Clock Conditioning Circuits In Fusion devices, the CCCs are used to impl ement frequency division, frequency multiplication, phase shifting, and delay operations. The CCCs are available in six chip locations—each of the four chip corners and the middle of the east and west chip sides. Each CCC can implement up to three independent global buffers (with or without programmable delay), or a PLL function (programmable frequency division/multiplication, phase shift, and delays) with up to three global outputs. Unused global outputs of a PLL can be used to implement independent global buffers, up to a maximum of three global outputs for a given CCC. A global buffer can be placed in any of the three global locations (CLKA-GLA, CLKB-GLB, and CLKC- GLC) of a given CCC. A PLL macro uses the CLKA CCC input to drive its re ference clock. It uses the GLA and, optionally, the GLB and GLC global outputs to drive the global networks. A PLL macro can also drive the YB and YC regular core outputs. The GLB (or GLC) glob al output cannot be reused if the YB (or YC) output is used (Figure 2-19). Refer to the "PLL Macro" section on page 2-30 for more information. Each global buffer, as well as the PLL reference clock, can be driven from one of the following:  3 dedicated single-ended I/Os using a hardwired connection  2 dedicated differential I/Os using a hardwired connection  The FPGA core The CCC block is fully configurab le, either via flash configurat ion bits set in the programming bitstream or through an asynchronous interface . This asynchronous interface is dynamically accessible from inside the Fusion device to permit changes of parameters (such as divide ratios) during device operation. To increase the versatility and flexibility of the clock conditioning system, the CCC configuration is determined either by the user during the design process, with configuration data being stored in flash memory as part of the device programming procedure, or by writing data into a dedicate d shift register during normal devi ce operation. This latter mode allows the user to dynamically reconfigure the CCC without the need fo r core programming. The shift register is accessed through a simple serial interface. Refer to the UJTAG Applications in Actel’s Low-Power Flash Devices handbook chapter and the "CCC and PLL Characte ristics" section on page 2-31 for more information.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-25 Notes: 1. Visit the Actel website for future application note s concerning dynamic PLL reco nfiguration. Refer to the "PLL Macro" section on page 2-30 for signal descriptions. 2. Many specific INBUF macros support the wide variety of single-ended and differential I/O standards for the Fusion family. 3. Refer to the Fusion, IGLOO/e, and ProASIC3/E Macro Library Guide for more information. Figure 2-19  Fusion CCC Options: Global Buffers with the PLL Macro Table 2-12  Available Selections of I/O Standards within CLKBUF and CLKBUF_LVDS/LVPECL Macros CLKBUF Macros CLKBUF_LVCMOS5 CLKBUF_LVCMOS331 CLKBUF_LVCMOS18 CLKBUF_LVCMOS15 CLKBUF_PCI CLKBUF_LVDS2 CLKBUF_LVPECL Notes: 1. This is the default macro. Fo r more details, refer to the Fusion, IGLOO/e and ProASIC3/E Macro Library Guide. 2. The BLVDS and M-LVDS standards are supported with CLKBUF_LVDS. PADN PADP Y PAD Y Input LVDS/LVPECL Macro INBUF2 Macro GLA or GLA and (GLB or YB) or GLA and (GLC or YC) or GLA and (GLB or YB) and (GLC or YC) Clock Source Clock Conditioning Output OADIVHALF OADIV[4:0] OAMUX[2:0] DLYGLA[4:0] OBDIV[4:0] OBMUX[2:0] DLYYB[4:0] DLYGLB[4:0] OCDIV[4:0] OCMUX[2:0] DLYYC[4:0] DLYGLC[4:0] FINDIV[6:0] FBDIV[6:0] FBDLY[4:0] FBSEL[1:0] XDLYSEL VCOSEL[2:0] CLKA EXTFB POWERDOWN OADIVRST GLA LOCK GLB YB GLC YC

2-26 Preliminary v1.7 Global Buffers with No Programmable Delays The CLKBUF and CLKBUF_LVPECL/LVDS macros are composite macros that include an I/O macro driving a global buffer, hardwired together (Figure 2-20). The CLKINT macro provides a global buffer function driven by the FPGA core. The CLKBUF, CLKBUF_LVPECL/LVDS, and CLKINT macros are pass-through clock sources and do not use the PLL or provide any programmable delay functionality. Many specific CLKBUF macros support the wide variety of single-ended and differential I/O standards supported by Fusion devices. The av ailable CLKBUF macros are described in the Fusion, IGLOO/e and ProASIC3/E Macro Library Guide. Figure 2-20  Global Buffers with No Programmable Delay CLKBUF_LVDS/LVPECL Macro PADN PADP YY APAD Y CLKINT MacroCLKBUF Macro GLA or GLB or GLC Clock Source Clock Conditioning Output None

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-27 Global Buffers with Programmable Delay The CLKDLY macro is a pass-through clock source that does not use the PLL, but provides the ability to delay the clock input using a programmable delay ( Figure 2-21). The CLKDLY macro takes the selected clock input and adds a us er-defined delay element. This macro generates an output clock phase shift from the input clock. The CLKDLY macro can be driven by an INBUF ma cro to create a composite macro, where the I/O macro drives the global buffer (with programmable delay) using a hardwired connection. In this case, the I/O must be placed in one of the dedicated global I/O locations. Many specific INBUF macros support the wide variety of single-ended and differential I/O standards supported by the Fusion family. The avai lable INBUF macros are described in the Fusion, IGLOO/e and ProASIC3/E Macro Library Guide. The CLKDLY macro can be driven directly from the FPGA core. The CLKDLY macro can also be driven from an I/O that is routed through the FPGA regular routing fabric. In this case, users must instantiate a sp ecial macro, PLLINT, to differentiate from the hardwired I/O connection described earlier. The visual CLKDLY configuration in the SmartGen part of the Libero IDE and Designer tools allows the user to select the desired amount of delay and configures the delay elements appropriately. SmartGen also allows the user to select the input clock source. SmartGen will automatically instantiate the special macro, PLLINT, when needed. Figure 2-21  Fusion CCC Options: Global Buffers with Programmable Delay PADN PADP Y PAD Y Input LVDS/LVPECL Macro INBUF* Macro GLA or GLB or GLC Clock Source Clock Conditioning Output CLK DLYGL[4:0] GL

2-28 Preliminary v1.7 Global Input Selections Each global buffer, as well as the PLL reference clock, can be driven from one of the following (Figure 2-22):  3 dedicated single-ended I/Os using a hardwired connection  2 dedicated differential I/Os using a hardwired connection  The FPGA core Notes: 3. Represents the global input pins. Globals have direct access to the clock conditioning block and are not routed via the FPGA fa bric. Refer to the "User I/O Naming Conventi on" section on page 2-157 for more information. 4. Instantiate the routed cloc k source input as follows: a) Connect the output of a logic element to the clock input of the PLL, CLKDLY, or CLKINT macro. b) Do not place a clock source I/O (INBUF or INBUF_LVPECL/LVDS) in a relevant global pin location. 5. LVDS-based clock sources are available in th e east and west banks on all Fusion devices. Figure 2-22  Clock Input Sources Including CLKBUF, CLKBUF_LVDS/LVPECL, and CLKINT Source for CCC (CLKA or CLKB or CLKC) Each shaded box represents an input buffer called out by the appropriate name: INBUF or INBUF_LVDS/LVPECL. To Core Routed Clock (from FPGA core) Sample Pin Names GAA01 GAA11 GAA21 GAA[0:2]: GA represents global in the northwest corner of the device. A[0:2]: designates specific A clock source.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-29 CCC Physical Implementation The CCC circuit is composed of the following (Figure 2-23):  PLL core  3 phase selectors  6 programmable delays and 1 fixed delay  5 programmable frequency dividers that provide frequency multiplication/division (not shown in Figure 2-23 because they are automatically configured based on the user's required frequencies)  1 dynamic shift register that provides CCC dynamic reconfiguration capability (not shown) CCC Programming The CCC block is fully configurable. It is configur ed via static flash config uration bits in the array, set by the user in the programming bitstream, or configured through an asynchronous dedicated shift register, dynamically access ible from inside the Fusion de vice. The dedicated shift register permits changes of parameters such as PLL divide ra tios and delays during device operation. This latter mode allows the user to dynamically reconfigure the PLL without the need for core programming. The register file is accessed through a simple serial interface. Note: Clock divider and multiplier blocks are not shown in this figure or in SmartGen. They are automatically configured based on the user's required frequencies. Figure 2-23  PLL Block PLL Core Phase Select Phase Select Phase Select GLA CLKA GLB YB GLC YC Fixed Delay Programmable Delay Type 1 Programmable Delay Type 2 Programmable Delay Type 2 Programmable Delay Type 1 Programmable Delay Type 2 Programmable Delay Type 1 Four-Phase Output

2-30 Preliminary v1.7 PLL Macro The PLL functionality of the clock conditioning bloc k is supported by the PLL macro. Note that the PLL macro reference clock uses the CLKA input of the CCC block, which is only accessible from the global A[0:2] package pins. Refer to Figure 2-22 on page 2-28 for more information. The PLL macro provides five deri ved clocks (three independent) from a single reference clock. The PLL feedback loop can be driven either internally or externally. The PLL macro also provides power- down input and lock output signals. During power-up, POWERDOWN should be asserted LOW until V CC is up. See Figure 2-19 on page 2-25 for more information. Inputs:  CLKA: selected clock input  POWERDOWN (active low): disables PLLs. The de fault state is power-down on (active low). Outputs:  LOCK (active high): indicates that PLL outp ut has locked on the input reference signal  GLA, GLB, GLC: outputs to respective global networks  YB, YC: allows output from the CCC to be routed back to the FPGA core As previously described, the PLL allows up to five flexible and independently configurable clock outputs. Figure 2-23 on page 2-29 illustrates the various clock output options and delay elements. As illustrated, the PLL supports three distinct output frequencies from a given input clock. Two of these (GLB and GLC) can be routed to the B and C global networks, respectively, and/or routed to the device core (YB and YC). There are five delay elements to support phase control on all five outputs (GLA, GLB, GLC, YB, and YC). There is also a delay element in the feedback loop that can be used to advance the clock relative to the reference clock. The PLL macro reference clock can be driven by an INBUF macro to create a composite macro, where the I/O macro drives the global buffer (with programmable delay) using a hardwired connection. In this case, the I/O must be placed in one of the dedicated global I/O locations. The PLL macro reference clock can be driven directly from the FPGA core. The PLL macro reference clock can also be driven from an I/O routed through the FPGA regular routing fabric. In this case, use rs must instantiate a special macro, PLLINT, to differentiate it from the hardwired I/O connection described earlier. The visual PLL configuration in SmartGen, available with the Libero IDE and Designer tools, will derive the necessary internal divider ratios based on the input frequ ency and desired output frequencies selected by the user. SmartGen allows the user to sele ct the various delays and phase shift values necessary to adjust the phases be tween the reference clock (CLKA) and the derived clocks (GLA, GLB, GLC, YB, and YC). SmartGen also allows the user to select where the input clock is coming from. SmartGen automatically instantiates the special macro, PLLINT, when needed.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-31 CCC and PLL Characteristics Timing Characteristics Table 2-13  Fusion CCC/PLL Specification Parameter Min. Typ. Max. Unit Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 350 MHz Clock Conditioning Circuitry Output Frequency fOUT_CCC 0.75 350 MHz Delay Increments in Programmable Delay Blocks1, 2 160 ps Number of Programmable Values in Each Programmable Delay Block Input Period Jitter 1.5 ns CCC Output Peak-to-Peak Period Jitter FCCC_OUT Max Peak-to-Peak Period Jitter

1 Global

3 Global

0.75 MHz to 24 MHz 1.00% 1.00% 24 MHz to 100 MHz 1.50% 1.50% 100 MHz to 250 MHz 2.25% 2.25% 250 MHz to 350 MHz 3.50% 3.50% Acquisition Time LockControl = 0 300 µs LockControl = 1 6.0 ms Tracking Jitter 3 LockControl = 0 1.6 ns LockControl = 1 0.8 ns Output Duty Cycle 48.5 51.5 % Delay Range in Block: Programmable Delay 1 1, 2 0.6 5.56 ns Delay Range in Block: Programmable Delay 2 1, 2 0.025 5.56 ns Delay Range in Block: Fixed Delay 1, 2 2.2 ns Notes: 1. This delay is a function of voltage and temperature. See Table 3-7 on page 3-9 for deratings. 2. T J = 25°C, VCC = 1.5 V 3. Tracking jitter is defined as the va riation in clock edge position of PLL outputs with reference to PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter.

2-32 Preliminary v1.7 No-Glitch MUX (NGMUX) Positioned downstream fro m the PLL/CCC blocks, the NGMUX provides a special switching sequence between two asynchronous clock do mains that prevents generating any unwanted narrow clock pulses. The NGMUX is used to switch the so urce of a global be tween three different clock sources. Allowable inputs are either two PLL/CCC outputs or a PLL/CCC output and a regular net, as shown in Figure 2-24. The GLMUXCFG[1:0] configuration bits determine the source of the CLK inputs (i.e., internal signal or GLC). These are set by Smar tGen during design but can also be changed by dynamically reconfiguring the PLL. The GLMUXSEL[1:0] bits control which clock source is passed through the NGMUX to the global network (GL). See Table 2-14. Figure 2-24  NGMUX Table 2-14  NGMUX Configuration and Selection Table GLMUXCFG[1:0] GLMUXSEL[1:0] Selected Input Signal MUX Type

00 X 0 GLA 2-to-1 GLMUX

01 X 0 GLA 2-to-1 GLMUX

GLMUXCFG[1:0] PWR UP GLMUXSEL[1:0] GL To Clock Rib Driver

2-34 Preliminary v1.7 Real-Time Counter System The addition of the RTC system enables Fusion devices to support both standby and sleep modes of operation, greatly reducing power consumption in many applications. The RTC system comprises six blocks that work together to provide this increased functionality and reduced power consumption. Figure 2-27 shows these blocks and how they are connected. R T C ( Figure 2-28)  Crystal oscillator V CC33UP detector  Voltage regulato r initialization  Voltage regulator logic  1.5 V voltage regulator The RTC provides a counter as well as a MATCH ou tput signal that can be used in the FPGA and, optionally, to power up the on-chi p 1.5 V voltage regulator and pr ovide a 1.5 V power source (in conjunction with an external pass transistor) to the FPGA fabric portion of the Fusion silicon device. The FPGA fabric can then be used to power down the 1.5 V voltage regulator. Figure 2-27  Real-Time Counter System RTC RTCCLK RTCPSMMATCH RTCMODE[1:0] SELMODE RTCMATCH Crystal Oscillator XTAL2 XTAL1 EN MODE[1:0] CLKOUT

1.5 V Voltage

1.5 V FPGA Supply Input

~ VRPSM Power-Up/Down Toggle Control Switch 1.5 V Output External Pass Transistor 3.3 V 1.5/3.3 Volt Level Shift Circuitry FPGA_VRON VRFPD VCC33UP From Core Flash Bits

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-35 Real-Time Counter The RTC can be configured to power up the FPGA fabric at a specific time or periodically. Custom user logic or a soft microcontro ller within the FPGA fabric port ion of the Fusion device can be programmed to read and modify the registers in the RTC. Based on this information or other internal or external conditions , the FPGA may decide to power down the voltage regulator and thereby shut off the FPGA fabric. The 3.3 V supply must be valid and the crystal oscillator (nom inally 32.768 kHz) enabled for a self- timed wake-up/restart operation. When operatin g from the 3.3 V supply with the 1.5 V core voltage disabled, the ACM interface to the FPGA is disabled. A 40-bit loadable counter is used as the primary timekeeping element within the RTC. This counter can be configured to reset itself when a count value is reached that matches the value set within a 40-bit match register. Note that the only exception to this self-clearing mechanism occurs when the 40-bit counter is equal to zero (0x0000000000) , since the counter would never increment from zero. When the device is first powered up (i.e., when the 3.3 V su pply becomes valid), the 40-bit counter and 40-bit match register are cleared to logic 0, and the MATCH ou tput signal is active (logic 1). At any time when the 40-bit counter va lue does not match the va lue in the 40-bit match register, the MATCH output signal will become inactive (logic 0). Both the counter and ma tch registers are addressable (read/write) from the FPGA and through a JTAG instruction. The RTC is considered part of the analog system and is accessed via the ACM. Refer to the "Analog Configuration MUX" section on page 2-124 for detailed instructions on writing to the RTC via the ACM. The counter action can be suspen ded/resumed by clearing/setting the Cntr_En bit in the Control/Status register. If a 32.768 kHz external crystal is connected to the crystal oscillator pad, the 40-bit counter will have a maximum count of 4,294,967, 296 seconds, which equates to just over 136 years of elapsed timekeeping with a minimum period of 1/256 of a second, which will be the toggle rate of the LSB of the 40-bit counter. Frequencies other than 32.768 kHz can be used as a clock source with the appropriate scaling of the LSB time interval. The maximum input clock frequency is 20 MHz (the crystal oscillator limit). The RTC signals are included in th e Analog Block macro. The signal functions and descriptions are listed in Table 2-15. A Fusion use model includes the RTC controlling the power-up state of the FPGA core via the 1.5 V regulator. To support this model, the crystal osci llator must be running and configured when the FPGA is powered off. Hence, when the RTC is enabled in the syst em design, it will configure the crystal oscillator via the RTCXTLMODE[1:0] and RTCXTLSEL pins. A 7-bit prescaler block is used to divide the sour ce clock (from the external crystal) by 128. This prescaled 50%-duty-cycle clock signal is then used by the counter logic as its reference clock. Given Figure 2-28  RTC Block Diagram Analog Configuration MUX (ACM) Interface 40-Bit Read-Hold Register Main Registers Match Bits Match

40 XNORs

(Crystal ÷ 128) Control/Status Register 40-Bit Counter 40-Bit Match Register

2-36 Preliminary v1.7 an external crystal frequ ency of 32.768 kHz, the prescaler output clock will toggle at a rate of 32.768 kHz / 128 = 256 Hz. The RTC is built from and controlled by a se t of registers, denoted "Main Registers" in Figure 2-27 on page 2-34. These registers are accessed via the ACM. The FPGA fabric portion of the Fusion device must be powered up and active at least once to write to the various registers within the RTC to initialize them for the user’s application. Users set up the RTC by configuring it from the Actel SmartGen tool, implementing custom logic or programming a soft microcontroller. The 40-bit counter and match regi sters are each divided into five bytes. Each byte is directly addressable by the ACM. The address map of regi sters accessed through the ACM and used by the RTC is shown in Table 2-16 on page 2-36. Table 2-15  RTC Macro Signal Description Signal Name Number of Bits Direction Function RTCMATCH 1 Out Match between 40-bit counter and match register RTCPSMMATCH 1 Out RTCMATCH connecte d to voltage regulator power supply monitor (VRPSM) (Figure 2-30 on page 2-40) RTCXTLMODE[1:0] 2 Out Drives XTLOSC RTCMODE[1:0] pins RTCXTLSEL 1 Out Drives XTLOSC SELMODE pin RTCCLK 1 In RTC clock input from XTLOSC CLKOUT pin Table 2-16  RTC ACM Memory Map ACM_ADDR[7:0] Decimal Regist er Name Description Use 0x40 64 COUNTER0 Counter bits 7:0 Use d to preload the counter to a specified start point. Default setting is all zeroes.0x41 65 COUNTER1 Counter bits 15:8 0x42 66 COUNTER2 Counter bits 23:16 0x43 67 COUNTER3 Counter bits 31:24 0x44 68 COUNTER4 Counter bits 39:32 0x48 72 MATCHREG0 Match register bits 7:0 The RTC uses a 40-bit register to compare against the 40-bit counter value to determine when a match occurs. This 40-bit match register, like the counter, is broken into 5 bytes (MATCHREG0–4). 0x49 73 MATCHREG1 Match register bits 15:8 0x4A 74 MATCHREG2 Match register bits 23:16 0x4B 75 MATCHREG3 Match register bits 31:24 0x4C 76 MATCHREG4 Match register bits 39:32 0x50 80 MATCHBITS0 Individual match bits 7:0 Each bit of the 40-bit counter is compared to each bit of the 40-bit match register via XNOR gates. These 40 match bits are partitioned into 5 bytes. 0x51 81 MATCHBITS1 Indivi dual match bits 15:8 0x52 82 MATCHBITS2 Indivi dual match bits 23:16 0x53 83 MATCHBITS3 Indivi dual match bits 31:24 0x54 84 MATCHBITS4 Indivi dual match bits 39:32 0x58 88 CTRL_STAT Control (write) / Status (read) register bits 7:0 Control (write) / Status (read) register bits 7:0 0x59 89 TEST_REG Test register(s) Test register(s) Note: Accessing RTC Registers: When reading the RTC count or match register, which operates in the XTLCLK domain, the appropriate 40-bit value is first copied to a capture register through clock synchronization circuitry, if and only if the least significant byte of that set of register is addressed. Higher-order bytes of the same set of registers captured with the LSB can then be read on immediately later read cycles. Higher- order bytes of that set of registers can be read in any order but must be read before switching to a different set of registers to ensure data consistency. For example, RTC counter address ranges from 0x40 to 0x44, register 0x40 must be accessed first before accessing addresses 0x41, 0x42, 0x43, and 0x44 to get the full 40-bit value.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-37 The Control/Status register (CTRL_STAT) is an 8-bit register that defines the operation of the RTC. The Control register can reset the RT C, enabling operation to begin with all zeroes in the counter. The RTC can be configured to clear upon a match with the Match register, or it can continue to count while still setting the match signal. To enable the Fusion device to power up at a specific time or at periodic intervals, the RTC can be conf igured to turn on the 1.5 V voltage regulator. Table 2-17 details the CTRL_STAT settings. Table 2-17  RTC Control/Status Register Bit Name Description 7 rtc_rst RTC Reset: Writin g a logic 1 to this bit causes an RTC reset.2 Writing a logic 0 to this bit will allow synchronous deassertion of reset after two ACM_CLK cycles if VCC33UP = 1.3 6 cntr_en Counter Enable: A logic 1 in this bit will enable the counter if the RTC is not in reset. It takes 64 RTCCLK positive edges (one-half of the prescaler division factor), after reset is removed and cntr_en = 1, before the counter is incremented.4 A logic 0 in this bit resets the prescaler and therefore suspends incrementing the counter, but the counter is not reset. Before writing to the counter registers, the counter must be disabled. 5 vr_en_mat Voltage Regulator Enable on Match: Writ ing a logic 1 to this bit will allow the RTCMATCH output port to go to logic 1 when a match occurs between the 40-bit counter and the 40- bit match register. Logic 0 forces RTCMATCH to logic 0 to prevent enabling th e voltage regulator from the RTC. 4:3 xt_mode[1:0 Crystal Oscillator Mode: Thes e bits control the RTCXTLMODE [1:0] output ports that are connected to the RTCMODE[1:0] input pins of the crystal oscillator pad. For 32 kHz crystal operation, this should be set to '01'. (See the "Crystal Oscillator" section on page 2-22.) 2 rst_cnt_omat Reset Counter on Match: A logic 1 written to this bit allows the counter to clear itself when a match occurs. In this situatio n, the 40-bit counter clears on the next rising edge of the prescaled clock, approximately 4 ms after the match occurs (the prescaled clock toggles at a rate of 256 Hz, given a 32.768 kHz external crystal). A logic 0 written to this bit allows the counter to increment indefinitely while still allowing match events to occur. 1 rstb_cnt Counter Reset: A logic 0 resets the 40-b it counter value to zero. A logic 1 allows the counter to count.4 0 xtal_en Crystal Oscillator Enable: This bit contro ls the RTCXTLSEL output port connected to the SELMODE input pin of the crystal oscillator. If a logic 0 is written to this bit, only the FPGA fabric can be used to control the crystal oscillator EN and MODE[1:0] inputs. xtal_en = 1: RTC takes control of crystal os cillator. For example, the RTC Mode bits configure the crystal oscillator (not the FPGA mode bits). To enable sleep mode, set xtal_en = ‘0’, so the crystal is controlled from the FPGA EN signal. Then when the FPGA is powered down, the signal from the fpga_en will be 0. It disables the crystal oscillator. Notes: 1. Default state (set when V CC33UP = 0) for bits 0–7 is logic 0. 2. Reset of all RTC states (excep t this Control/Status register) occurs asynchronously if V CC33UP = 0 or CTRL_STAT bit 7 (rtc_rst) is set to 1. 3. Reset is removed synchronously after two rising edges of ACM_CLK, following both VCC33UP = 1 and rtc_rst = 0. 4. Counter will first increment on th e 64th rising edge of RTCCLK after all of the following are true: a. reset is removed b. rstb_cnt (CTRL_STAT bit 1) is set to 1 c. cntr_en (CTRL_STAT bit 6) is set to 1 and will then increment every 128 RTCCLK cycles.

2-38 Preliminary v1.7 Crystal Oscillator (Xtal Osc) When used as the clock source for the RTC, the crystal oscillator will be configured by the RTC with the RTCXTLMODE[1:0] RTC macro pins. Refer to the "Crystal Oscillator" section on page 2-22 for specific details on crystal oscillator operation. The crystal oscillator input to the RTC is divided by 128, so bit 0 of the RTC toggles at the frequency of the crystal oscillator divided by 128. The frequencies of the RTC are gated by those of the crystal oscillator, from 32.768 kHz to 20 MHz. When used with a 32.768 kHz crystal, bit 0 of the of RTC has a period of ~7.8 ms, and bit 7 has a period of 1 second. Voltage Regulator (VR) Initialization (Init) The VR Init block determines voltage regulator behavior when the 3.3 V supply is valid. The Fusion devices support different use models. Some of these require the 1.5 V voltage regulator to turn on when the 3.3 V supply is stable. Other use models require ad ditional conditions to be met before the 1.5 V VR turns on. Since the FPGA is not operating when the 3.3 V supply is off, the VR Init block lets the user define VR behavior at design time. Two bits can be set within the core, which bits the VR Init block will read as it comes out of reset and either turn on the VR or leave it in an off state. Voltage Regulator Logic The VR Logic block, along with the VR, combines commands from the FPGA, RTC, VR Init block, V CC33UP detector, and PUB pad to determine whether or not the VR is enabled. The VR can be enabled from seve ral sources: the PUB pin, the RTC_MATCH signal from the RTC block, or triggered by the VR Init block. Once triggered, the VR will remain on. Only the FPGA fabric can disable the VR, unless the V CC33A supply falls below the V CC33UP threshold and a reset occurs.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-39

1.5 V Voltage Regulator

The VR generates a 1.5 V power supply from the 3.3 V power supply. The 1.5 V output is intended to supply all 1.5 V needs of the Fusion device. This regulator re quires an external bipolar pass transistor (Figure 2-29). The VR can drive up to 20 mA of current through the PTBASE pad. The amount of 1.5 V current available is dependent upon the gain of the external pass transistor used. Enable for this block is generated in the VR Logic block or from the PUB pin. The VR is forced "on" with TRST high or floating (internal pull-up), so an external pull-down is required on TRST if the customer desires to power-down the VR. The 1.5 V is not supplied internally to the Fusion device. It must be routed externally to the VCC pins on the device. Therefore the user is not required to use the VR and can use an off-chip 1.5 V supply if desired. Figure 2-29  Voltage Regulator RTC FPGA PUB 1 µA PTBASE PTEM PDVR 1.5 V Regulator VCC33A

1.5 V Out

Power-Up/Down Control Circuit

2-40 Preliminary v1.7 Voltage Regulator Power Supply Monitor (VRPSM) As the functions of the VR Logic and Power Syste m Monitor work closely to gether to control the power-up state of the FPGA core, these function s were combined into a single VRPSM macro (Figure 2-30). The signals for the VRPSM macro are listed in Table 2-18. The PUB input comes from the PUB pin on the device and can be pulled LOW by a signal exte rnal to the Fusion devi ce. This can be used to wake up the device. The inputs VRINITSTATE and RTCPSMMTACH come from the VR Init and RTC blocks, respectively, and either can initiate a VR power-up. The detailed description is available in the Fusion Handbook. Figure 2-30  VRPSM Macro Table 2-18  Signals for VRPSM Macro Signal Name Number of Bits Direction Function PUB 1 Input Active low signal to power up the FPGA core via the 1.5 V regulator. In this reference design, PUB is on the top level, connected to an external switch. VRPU 1 Input When this pin is at logic 1, the FPGA core will be turned off via the voltage regulator. VRINITSTATE 1 Input This feature is not used in this reference design and is not shown in the macro generated by SmartGen. If used, the signal enables you to set your voltage regulator output at power-up (ON or OFF). RTCPSMMATCH 1 Input This feature is not used in this reference design. If used, this active high signal is driven by the RTC’s match signal to indicate that the RTC counter value matches the pre-defined Match register value set in SmartGen. FPGAGOOD 1 Output Logic 1 indicates th at FPGA is logically functional. PUCORE 1 Output Logic 1 indicates that FPGA is logically functional. PUB FPGAGOOD VRPU PUCORE VRINITSTATE RTCPSMMATCH

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-41 Embedded Memories Fusion devices include four types of embedded memory: flash block, FlashROM, SRAM, and FIFO. Flash Memory Block Fusion is the first FPGA that offers a flash memory block (FB). Each FB block stores 2 Mbits of data. The flash memory block macro is illustrated in Figure 2-31. The port pin name and descriptions are detailed on Table 2-19 on page 2-42. All flash memory block signals are active high, except for CLK and active low RESET. All flash memory operations are synchronous to the rising edge of CLK. Figure 2-31  Flash Memory Block ADDR[17:0] WD[31:0] PROGRAM CLK RESET RD[31:0] BUSY STATUS[1:0] UNPROTECTPAGE DISCARDPAGE OVERWRITEPROTECT PAGELOSSPROTECT DATAWIDTH[1:0] REN WEN ERASEPAGE SPAREPAGE AUXBLOCK READNEXT OVERWRITEPAGE PAGESTATUS PIPE LOCKREQUEST

2-42 Preliminary v1.7 Flash Memory Block Pin Names Table 2-19  Flash Memory Block Pin Names Interface Name Width D irection Description ADDR[17:0] 18 In Byte offset into the FB. Byte-based address. AUXBLOCK 1 In When asserted, the page addresse d is used to access the auxiliary block within that page. BUSY 1 Out When asserted, indicates that the FB is performing an operation. CLK 1 In User interface clock. All operat ions and status are synchronous to the rising edge of this clock. DATAWIDTH[1:0] 2 In Data width 00 = 1 byte in RD/WD[7:0] 01 = 2 bytes in RD/WD[15:0] 1x = 4 bytes in RD/WD[31:0] DISCARDPAGE 1 In When asserted, th e contents of the Page Buffer are discarded so that a new page write can be started. ERASEPAGE 1 In When asserted, the contents of the Page Buffer are discarded so that a new page write can be started. LOCKREQUEST 1 In When asserted, indicates to the JTAG controller that the FPGA interface is accessing the FB. OVERWRITEPAGE 1 In When asserted, the page ad dressed is overwritten with the contents of the Page Buffer if the page is writable. OVERWRITEPROTE CT

1 In When asserted, all program operatio ns will set the overwrite protect

bit of the page being programmed. PAGESTATUS 1 In When asserted with REN, in itiates a read page status operation. PAGELOSSPROTECT 1 In When asse rted, a modified Page Buffer must be programmed or discarded before accessing a new page. PIPE 1 In Adds a pipeline stage to the output for operation above 50 MHz. PROGRAM 1 In When asserted, writes the conten ts of the Page Buffer into the FB page addressed. RD[31:0] 32 Out Read data; data will be va lid from the first non-busy cycle (BUSY = 0) after REN has been asserted. READNEXT 1 In When asserted with REN, initiates a read-next operation. REN 1 In When asserted, init iates a read operation. RESET 1 In When asserted, resets th e state of the FB (active low). SPAREPAGE 1 In When asserted, the sector addr essed is used to access the spare page within that sector.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-43 All flash memory block input signals are active high, except for RESET. STATUS[1:0] 2 Out Status of the last operation completed: 00: Successful completion 01: Read-/Unprotect-Page: single error detected and corrected Write: operation addressed a write-protected page Erase-Page: protection violation Program: Page Buffer is unmodified Protection violation 10: Read-/Unprotect-Page: two or more errors detected 11: Write: attempt to write to another page before programming current page Erase-Page/Program: page write count has exceeded the 10-year retention threshold UNPROTECTPAGE 1 In When asserted, the page addr essed is copied into the Page Buffer and the Page Buffer is made writable. WD[31:0] 32 In Write data WEN 1I n When asserted, stores WD in the page buffer. Table 2-19  Flash Memory Block Pin Names (continued) Interface Name Width D irection Description

2-44 Preliminary v1.7 Flash Memory Block Diagram A simplified diagram of the flash memory block is shown in Figure 2-32. The logic consists of the following sub-blocks:  Flash Array Contains all stored data. The flash array contains 64 sectors, and each sector contains 33 pages of data.  Page Buffer A page-wide volatile register. A page contains 8 blocks of data and an AUX block.  Block Buffer Contains the contents of the last block accessed. A block contains 128 data bits.  ECC Logic The FB stores error correction information with each block to perf orm single-bit error correction and double-bit error detection on all data blocks. Figure 2-32  Flash Memory Block Diagram ADDDR[17:0] DATAWIDTH[1:0] REN READNEXT PAGESTATUS WEN ERASEPAGE PROGRAM SPAREPAGE AUXBLOCK UNPROTECTPAGE OVERWRITEPAGE DISCARDPAGE OVERWRITEPROTECT PAGELOSSPROTECT PIPE LOCKREQUEST CLK RESET STATUS[1:0] BUSY Control Logic Output MUX Block Buffer (128 bits) ECC Logic Flash Array = 64 SectorsRD[31:0] WD[31 :0] Page Buffer = 8 Blocks Plus AUX Block

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-45 Flash Memory Block Addressing Figure 2-33 shows a graphical representation of the flash memory block. Each FB is partitioned into sectors, pages, blocks, and bytes. There are 64 sectors in an FB, and each sector contains 32 pages and 1 spare page. Each page contains 8 data blocks and 1 auxiliary block. Each data block contains 16 bytes of user data, and the auxiliary block contains 4 bytes of user data. Addressing for the FB is shown in Table 2-20. When the spare page of a sector is addressed (SPAREPAGE active), ADDR[11:7] are ignored. When the Auxiliary block is addressed (AUXBLOCK active), ADDR[6:2] are ignored. Note: The spare page of sector 0 is unavailable for any user data. Writes to this page will return an error, and reads will return all zeroes. Figure 2-33  Flash Memory Block Organization Byte 0 Byte 1 Byte 2 Byte 3 Byte 14 Byte 15 Block Organization User Data (32 bits) 140 Block 0 1234567 Aux Block . . . . . . . . Sector 0 Sector 1 Sector n . . . .

33 Pages

Notes: 1 block = 128 bits 1 page = 8 blocks plus the AUX block 1 sector = 33 pages

1 Flash array = 64 sectors

Table 2-20  FB Address Bit Allocation ADDR[17:0] 1 7 1 2 1 1 76430 Sector Page Block Byte

2-46 Preliminary v1.7 Data operations are performed in widths of 1 to 4 bytes. A write to a location in a page that is not already in the Page Buffer will cause the page to be read from the FB Array and stored in the Page Buffer. The block that was addressed during the wr ite will be put into the Block Buffer, and the data written by WD will overwrite the data in th e Block Buffer. After the data is written to the Block Buffer, the Block Buffer is then written to the Page Buffer to keep both buffers in sync. Subsequent writes to the same block will overwrite the Block Buffer and the Page Buffer. A write to another block in the page will cause the addressed block to be loaded from the Page Buffer, and the write will be performed as described previously. The data width can be selected dynamically via the DATAWIDTH input bus. The truth table for the data width settings is detailed in Table 2-21. The minimum resolvable address is one 8-bit byte. For data widths greater than 8 bits, the co rresponding address bi ts are ignored—when DATAWIDTH = 0 (2 bytes), ADDR[0] is ignored, an d when DATAWIDTH = '10' or '11' (4 bytes), ADDR[1:0] are ignored. Data pins are LSB-oriented and unused WD data pins must be grounded. Flash Memory Block Protection Page Loss Protection When the PAGELOSSPROTECT pin is set to logic 1, it prevents writes to any page other than the current page in the Page Buffer until the page is either discarded or programmed. A write to another page while the current page is Page Loss Protected will return a STATUS of '11'. Overwrite Protection Any page that is Overwrite Protected will result in the STATUS being set to '01' when an attempt is made to either write, program, or erase it. To set the Overwrite Protection state for a page, set the OVERWRITEPROTECT pin when a Program operation is undertaken. To clear the Overwrite Protect state for a given page, an Unprotect Page operation must be performed on the page, and then the page must be programmed with the OVERWRITEPROTECT pin cleared to save the new page. LOCKREQUEST The LOCKREQUEST signal is used to give the user interface control over simultaneous access of the FB from both the User and JTAG interfaces. When LOCKREQUEST is asserted, the JTAG interface will hold off any access attempts until LOCKREQUEST is deasserted. Flash Memory Block Operations FB Operation Priority The FB provides for priority of operations when multiple acti ons are requested simultaneously. Table 2-22 shows the priority order (priority 0 is the highest). Table 2-21  Data Width Settings DATAWIDTH[1:0] Data Width 00 1 byte [7:0] 01 2 byte [15:0] 10, 11 4 bytes [31:0] Table 2-22  FB Operation Priority Operation Priority System Initialization 0 FB Reset 1 Read 2 Write 3 Erase Page 4 Program 5 Unprotect Page 6 Discard Page 7

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-47 Access to the FB is controlled by the BUSY signal. The BUSY output is synchronous to the CLK signal. FB operations are only accepted in cycles where BUSY is logic 0. Write Operation Write operations are initiated with the assertion of the WEN signal. Figure 2-34 on page 2-47 illustrates the multiple Write operations. When a Write operation is initiated to a page that is currently not in the Page Buffer, the FB control logic will issue a BUSY signal to the user interface while the page is loaded from the FB Array into the Page Buffer. (Note: The number of clock cycles that the BUSY output is asserted during the load of the Page Buffer is variable.) After loading the page into th e Page Buffer, the addressed data block is loaded from the Page Buffer into the Block Buffer. Subsequent writes to the same block of the page will incur no busy cycles . A write to another block in the page will assert BUSY for four cycles (five cycles when PIPE is asserted), to a llow the data to be written to the Page Buffer and have the current block loaded into the Block Buffer. Write operations are considered successful as long as the STATUS output is '00'. A non-zero STATUS indicates that an error was detected during th e operation and the write was not performed. Note that the STATUS output is "sticky"; it is unchanged until another operation is started. Only one word can be written at a time. Write word width is controlled by the DATAWIDTH bus. Users are responsible for keeping track of the contents of the Page Buffer and when to program it to the array. Just like a regular RAM, writing to random addresses is poss ible. Users can write into the Page Buffer in any order but will incur additional BUSY cycles. It is not necessary to modify the entire Page Buffer before saving it to nonvolatile memory. Write errors include the following: 1. Attempting to write a page that is Overwrite Protected (STATUS = '01'). The write is not performed. 2. Attempting to write to a page that is not in the Page Buffer when Page Loss Protection is enabled (STATUS = '11'). The write is not performed. Program Operation A Program operation is initiated by asserting the PROGRAM signal on the interface. Program operations save the contents of the Page Buffer to the FB Array. Due to the technologies inherent in the FB, a program operation is a time consuming operation (~8 m s). While the FB is writing the data to the array, the BUSY signal will be asserted. Figure 2-34  FB Write Waveform CLK WEN ADDR[17:0] WD[31:0] DATAWIDTH[1:0] PAGELOSSPROTECT BUSY STATUS[1:0] A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 S0 S1 S2 S3 S4 S5 S6

2-48 Preliminary v1.7 During a Program operation, the sector and pa ge addresses on ADDR are compared with the stored address for the page (and sector) in the Page Buffer. If there is a mismatch between the two addresses, the Program operation will be aborted and an error will be reported on the STATUS output. It is possible to write the Page Buffer to a different page in memory. When asserting the PROGRAM pin, if OVERWRITEPAGE is asserted as well, the FB will write the contents of the Page Buffer to the sector and page designated on the ADDR inputs if the destination page is not Overwrite Protected. A Program operation can be utilized to either modi fy the contents of the page in the flash memory block or change the protections for the page. Setting the OVERWRITEPROTECT bit on the interface while asserting the PROGRAM pin will put the page addressed into Overwrite Protect Mode. Overwrite Protect Mode safe guards a page from being inad vertently overwritten during subsequent Program or Erase operations. Program operations that result in a STATUS value of '01' do not modify the addressed page. For all other values of STATUS, the addressed page is modified. Program errors include the following: 1. Attempting to program a page that is Overwrite Protected (STATUS = '01') 2. Attempting to program a page that is not in the Page Buffe r when the Page Buffer has entered Page Loss Protection Mode (STATUS = '01') 3. Attempting to perform a program with OVER WRITEPAGE set when the page addressed has been Overwrite Protected (STATUS = '01') 4. The Write Count of the page programmed ex ceeding the Write Threshold defined in the part specification (STATUS = '11') 5. The ECC Logic determining th at there is an uncorrectable error within the programmed page (STATUS = '10') 6. Attempting to program a page that is not in the Page Buffer when OVERWRITEPAGE is not set and the page in the Page Buffer is modified (STATUS = '01') 7. Attempting to program the page in the Page Buffer when the Page Buffer is not modified The waveform for a Program operation is shown in Figure 2-35. Note: OVERWRITEPAGE is only sampled when the PROGRAM or ERASEPAGE pins are asserted. OVERWRITEPAGE is ignored in all other operations. Figure 2-35  FB Program Waveform CLK PROGRAM ADDR[17:0] OVERWRITEPAGE OVERWRITEPROTECT PAGELOSSPROTECT BUSY STATUS[1:0] Page

0 Valid

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-49 Erase Page Operation The Erase Page operation is initiated when the ERASEPAGE pin is asserted. The Erase Page operation allows the user to erase (set user data to zero) any page within the FB. The use of the OVERWRITEPAGE and PAGELOSSPROTECT pins is the same for erase as for a Program Page operation. As with the Program Page operation, a STATUS of '01' indicates that th e addressed page is not erased. A waveform for an Erase Page operation is shown in Figure 2-36. Erase errors include the following: 1. Attempting to erase a page that is Overwrite Protected (STATUS = '01') 2. Attempting to erase a page that is not in the Page Buffer when the Page Buffer has entered Page Loss Protection mode (STATUS = '01') 3. The Write Count of the erased page exceed ing the Write Threshold defined in the part specification (STATUS = '11') 4. The ECC Logic determining that there is an uncorrectable error wi thin the erased page (STATUS = '10') Figure 2-36  FB Erase Page Waveform CLK ERASE ADDR[17:0] OVERWRITEPROTECT PAGELOSSPROTECT BUSY STATUS[1:0] Page Valid

2-50 Preliminary v1.7 Read Operation Read operations are designed to read data from the FB Array, Page Buffer, Block Buffer, or status registers. Read operations supp ort a normal read and a read-a head mode (done by asserting READNEXT). Also, the timing for Read operations is dependent on the setting of PIPE. The following diagrams illustrate represen tative timing for Non-Pipe Mode ( Figure 2-37) and Pipe Mode (Figure 2-38) reads of the flash memory block interface. Figure 2-37  Read Waveform (Non-Pipe Mode, 32-bit access) Figure 2-38  Read Waveform (Pipe Mode, 32-bit access) CLK REN ADDR[17:0] DATAWIDTH[1:0] BUSY STATUS[1:0] RD[31:0] A0 A1 A2 A3 A4

0 S 0S 1S 2 S 4

ADDR[17:0] DATAWIDTH[1:0] BUSY STATUS[1:0] RD[31:0] 0D3

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-51 The following error indications are possible for Read operations: 1. STATUS = '01' when a single-bit data error was detected and correct ed within the block addressed. 2. STATUS = '10' when a double-bit error was detected in the bl ock addressed (note that the error is uncorrected). In addition to data reads, users can read the status of any page in the FB by asserting PAGESTATUS along with REN. The format of the data returned by a page status read is shown in Table 2-23, and the definition of the page status bits is shown in Table 2-24. Table 2-23  Page Status Read Data Format 31 8 7 4 3 2 1 0 Write Count Reserved Over Threshold Read Prot ected Write Protected Overwrite Protected Table 2-24  Page Status Bit Definition Page Status Bit(s) Definition 31–8 The number of times the page ad dressed has been programmed/erased 7–4 Reserved; read as 0

3 Over Threshold indicator (see the "Program Operation" section on page 2-47)

2 Read Protected; read protect bit for page, which is set via the JTAG interface

and only affects JTAG operations. This bit can be overridden by using the correct user key value.

1 Write Protected; write protect bit for page, which is set via the JTAG interface

and only affects JTAG operations. This bit can be overridden by using the correct user key value.

0 Overwrite Protected; designates that the user has set the OVERWRITEPROTECT

bit on the interface while doing a Program operation. The page cannot be written without first performing an Unprotect Page operation.

2-52 Preliminary v1.7 Read Next Operation The Read Next operation is a feature by which th e next block relative to the block in the Block Buffer is read from the FB Arra y while performing reads from th e Block Buffer. The goal is to minimize wait states during consecutive sequential Read operations. The Read Next operation is performed in a pr edetermined manner beca use it does look-ahead reads. The general look-ahead function is as follows:  Within a page, the next block fetched will be the next in linear address.  When reading the last data block of a page, it will fetch the first block of the next page.  When reading spare pages, it will read the first block of the next sector's spare page.  Reads of the last sector w ill wrap around to sector 0.  Reads of Auxiliary blocks will read th e next linear page's Auxiliary block. When an address on the ADDR input does not ag ree with the predetermined look-ahead address, there is a time penalty for this access. The FB wi ll be busy finishing th e current look-ahead read before it can start the next read. The worst case is a total of nine BUSY cycles before data is delivered. The Non-Pipe Mode and Pipe Mode waveforms for Read Ne xt operations are illustrated in Figure 2-39 and Figure 2-40. Figure 2-39  Read Next Waveform (Non-Pipe Mode, 32-bit access) Figure 2-40  Read Next WaveForm (Pipe Mode, 32-bit access) CLK REN READNEX T ADDR[17:0] DATAWIDTH[1:0] BUSY STATUS[1:0] RD[31:0] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9

0 S 0S 1S 2 S 4S 5S 6 S 8 S 9

0 D 0D 1D 2

ADDR[17:0] BUSY STATUS[1:0] RD[31:0] A0 A1 A2 A3 A4 A5 A6 A7 A8 S0 S1 S2 S4 S5 S6 0D 0 D 1 D 2 0D 4 D 5 D 6 S7 0 0D7

2-54 Preliminary v1.7 Flash Memory Block Characteristics Figure 2-43  Reset Timing Diagram Table 2-25  Flash Memory Block Timing Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tCLK2RD Clock-to-Q in 5-cycle read mode of the Read Data 7.99 9.10 10.70 ns Clock-to-Q in 6-cycle read mode of the Read Data 5.03 5.73 6.74 ns tCLK2BUSY Clock-to-Q in 5-cycle read mode of BUSY 4.95 5.63 6.62 ns Clock-to-Q in 6-cycle read mode of BUSY 4.45 5.07 5.96 ns tCLK2STATUS Clock-to-Status in 5-cycle read mode 11.24 12.81 15.06 ns Clock-to-Status in 6-cycle read mode 4.48 5.10 6.00 ns tDSUNVM Data Input Setup time for the Control Logic 1.92 2.19 2.57 ns tDHNVM Data Input Hold time for the Control Logic 0.00 0.00 0.00 ns tASUNVM Address Input Setup time for the Control Logic 2.76 3.14 3.69 ns tAHNVM Address Input Hold time for the Control Logic 0.00 0.00 0.00 ns tSUDWNVM Data Width Setup time for the Control Logic 1.85 2.11 2.48 ns tHDDWNVM Data Width Hold time for the Control Logic 0.00 0.00 0.00 ns tSURENNVM Read Enable Setup time for the Control Logic 3.85 4.39 5.16 ns tHDRENNVM Read Enable Hold Time for the Control Logic 0.00 0.00 0.00 ns tSUWENNVM Write Enable Setup time for the Control Logic 2.37 2.69 3.17 ns tHDWENNVM Write Enable Hold Time for the Control Logic 0.00 0.00 0.00 ns tSUPROGNVM Program Setup time for the Control Logic 2.16 2.46 2.89 ns tHDPROGNVM Program Hold time for the Control Logic 0.00 0.00 0.00 ns tSUSPAREPAGE SparePage Setup time for the Control Logic 3.74 4.26 5.01 ns tHDSPAREPAGE SparePage Hold time for the Control Logic 0.00 0.00 0.00 ns tSUAUXBLK Auxiliary Block Setup Time for the Control Logic 3.74 4.26 5.00 ns tHDAUXBLK Auxiliary Block Hold Time for the Control Logic 0.00 0.00 0.00 ns tSURDNEXT ReadNext Setup Time for the Control Logic 2.17 2.47 2.90 ns tHDRDNEXT ReadNext Hold Time for the Control Logic 0.00 0.00 0.00 ns tSUERASEPG Erase Page Setup Time for the Control Logic 3.76 4.28 5.03 ns tHDERASEPG Erase Page Hold Time for the Control Logic 0.00 0.00 0.00 ns tSUUNPROTECTPG Unprotect Page Setup Time for the Control Logic 2.01 2.29 2.69 ns tHDUNPROTECTPG Unprotect Page Hold Time for the Control Logic 0.00 0.00 0.00 ns CLK RESET Active Low, Asynchronous BUSY

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-55 tSUDISCARDPG Discard Page Setup Time for the Control Logic 1.88 2.14 2.52 ns tHDDISCARDPG Discard Page Hold Time for the Control Logic 0.00 0.00 0.00 ns tSUOVERWRPRO Overwrite Protect Setup Time for the Control Logic 1.64 1.86 2.19 ns tHDOVERWRPRO Overwrite Protect Hold Time for the Control Logic 0.00 0.00 0.00 ns tSUPGLOSSPRO Page Loss Protect Setup Time for the Control Logic 1.69 1.93 2.27 ns tHDPGLOSSPRO Page Loss Protect Hold Time for the Control Logic 0.00 0.00 0.00 ns tSUPGSTAT Page Status Setup Time for the Control Logic 2.49 2.83 3.33 ns tHDPGSTAT Page Status Hold Time for the Control Logic 0.00 0.00 0.00 ns tSUOVERWRPG Over Write Page Setup Time for the Control Logic 1.88 2.14 2.52 ns tHDOVERWRPG Over Write Page Hold Time for the Control Logic 0.00 0.00 0.00 ns tSULOCKREQUEST Lock Request Setup Time for the Control Logic 0.87 0.99 1.16 ns tHDLOCKREQUEST Lock Request Hold Time for the Control Logic 0.00 0.00 0.00 ns tRECARNVM Reset Recovery Time 0.94 1.07 1.25 ns tREMARNVM Reset Removal Time 0.00 0.00 0.00 ns tMPWARNVM Asynchronous Reset Minimum Pulse Width for the Control Logic 10.00 12.50 12.50 ns tMPWCLKNVM Clock Minimum Pulse Width for the Control Logic 4.00 5.00 5.00 ns tFMAXCLKNVM Maximum Frequency for Clock for the Control Logic 100.00 80.00 80.00 MHz Table 2-25  Flash Memory Block Timing (continued) Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units

2-56 Preliminary v1.7 FlashROM Fusion devices have 1 kbit of on-chip nonvolatil e flash memory that can be read from the FPGA core fabric. The FlashROM is arranged in eight banks of 128 bits during programming. The 128 bits in each bank are addressable as 16 bytes during the read-back of the FlashROM from the FPGA core (Figure 2-44). The FlashROM can only be programmed via the IEEE 1532 JTAG port. It cannot be programmed directly from the FPGA core. When programming, each of the eight 128-bit banks can be selectively reprogrammed. The FlashROM ca n only be reprogrammed on a bank boundary. Programming involves an automatic, on-chi p bank erase prior to reprogramming the bank. The FlashROM supports a synchronous read and can be read on byte boundaries. The upper three bits of the FlashROM address from the FPGA co re define the bank that is be ing accessed. The lower four bits of the FlashROM address from the FPGA core defi ne which of the 16 bytes in the bank is being accessed. The maximum FlashROM access clock is 20 MHz. Figure 2-45 shows the timing behavior of the FlashROM access cycle—the address has to be set up on the rising edge of the clock for DOUT to be valid on the next falling edge of the clock. If the address is unchanged for two cycles:  D0 becomes invalid 10 ns after the second rising edge of the clock.  D0 becomes valid again 10 ns a fter the second falling edge. If the address unchanged for three cycles:  D0 becomes invalid 10 ns after the second rising edge of the clock.  D0 becomes valid again 10 ns a fter the second falling edge.  D0 becomes invalid 10 ns after the third rising edge of the clock.  D0 becomes valid again 10 ns after the third falling edge. Figure 2-44  FlashROM Architecture Bank Number

3 MSB of ADDR (READ)

Byte Number in Bank 4 LSB of ADDR (READ) 0123456789101112131415

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-57 FlashROM Characteristics Figure 2-45  FlashROM Timing Diagram Table 2-26  FlashROM Access Time Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tSU Address Setup Time 0.53 0.61 0.71 ns tHOLD Address Hold Time 0.00 0.00 0.00 ns tCK2Q Clock to Out 21.42 24.40 28.68 ns FMAX Maximum Clock frequency 15.00 15.00 15.00 MHz tSU tHOLD Address tCK2Q D0 D0 tSU tHOLD tCK2Q tSU tHOLD tCK2Q

2-58 Preliminary v1.7 SRAM and FIFO All Fusion devices have SRAM blocks along the north side of the device. Additionally, AFS600 and AFS1500 devices have an SRAM block on the south side of the device. To meet the needs of high- performance designs, the memory blocks operate s trictly in synchronous mo de for both read and write operations. The read and write clocks are completely independent, and each may operate at any desired frequency less than or equal to 350 MHz. The following configurations are available:  4k×1, 2k×2, 1k×4, 512×9 (dual-port RAM—two read, two write or one read, one write)  512×9, 256×18 (two-port RA M—one read and one write)  Sync write, sync pipelined/nonpipelined read The Fusion SRAM memory block includes dedica ted FIFO control logic to generate internal addresses and external flag logic (FULL, EMPTY, AFULL, AEMPTY). During RAM operation, addresses are sourced by the user logic, and the FIFO controller is ignored. In FIFO mode, the internal addresses are generate d by the FIFO controller and routed to the RAM array by internal MUXes. Refer to Figure 2-46 for more information ab out the implementation of the embedded FIFO controller. The Fusion architecture enables the read and write sizes of RAMs to be organized independently, allowing for bus conversion. This is done with the WW (write width) and RW (read width) pins. The different D×W configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1. For example, the write size can be set to 256×18 and the read size to 512×9. Both the write and read widths for the RAM blocks can be specified independently with the WW (write width) and RW (read width) pins. The different D×W configurat ions are 256×18, 512×9, 1k×4, 2k×2, and 4k×1. Refer to the allowable RW and WW values su pported for each of the RAM macro types in Table 2-27 on page 2-61. When a width of one, two, or four is selected, the ninth bit is unused. For example, when writing 9- bit values and reading 4-bit values, only the first four bits and the second four bits of each 9-bit value are addressable for read operations. The ninth bit is not accessible.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-59 Conversely, when writing 4-bit values and reading 9-bit values, the ninth bi t of a read operation will be undefined. The RAM blocks employ little-endian byte order for read and write operations. Figure 2-46  Fusion RAM Block with Embedded FIFO Controller RCLK WD WCLK Reset RBLK REN ESTOP WBLK WEN FSTOP RD[17:0] WD[17:0] RCLK WCLK RADD[J:0] WADD[J:0] REN FREN FWEN WEN FULL AEMPTY AFULL EMPTY RD RPIPE RW[2:0] WW[2:0] RAM CNT 12 E = E AFVAL AEVALSUB 12CNT 12

2-60 Preliminary v1.7 RAM4K9 Description Figure 2-47  RAM4K9 ADDRA11 DOUTA8 DOUTA7 DOUTA0 DOUTB8 DOUTB7 DOUTB0 ADDRA10 ADDRA0 DINA8 DINA7 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB11 ADDRB10 ADDRB0 DINB8 DINB7 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB RAM4K9 RESET

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-61 The following signals are used to configure the RAM4K9 memory element: WIDTHA and WIDTHB These signals enable the RAM to be configured in one of four allowable aspect ratios (Table 2-27). BLKA and BLKB These signals are active low and will enable the respective ports when asserted. When a BLKx signal is deasserted, the corresponding port’s outputs hold the previous value. WENA and WENB These signals switch th e RAM between read and write mode for the respective ports. A LOW on these signals indicates a write operation, and a HIGH indicates a read. CLKA and CLKB These are the clock signals for the synchronous read and write operations. These can be driven independently or with the same driver. PIPEA and PIPEB These signals are used to specify pipelined read on the output. A LOW on PIPEA or PIPEB indicates a nonpipelined read, and the data appears on the corresponding output in the same clock cycle. A HIGH indicates a pipelined, read and data appears on the corresponding output in the next clock cycle. WMODEA and WMODEB These signals are used to configure the behavior of the output when the RAM is in write mode. A LOW on these signals makes the output retain data from the previous read. A HIGH indicates pass- through behavior, wherein the data being writte n will appear immediately on the output. This signal is overridden when the RAM is being read. RESET This active low signal resets the output to zero, disables reads and writes from the SRAM block, and clears the data hold registers when asserted. It does not reset the contents of the memory. ADDRA and ADDRB These are used as read or write addresses, and they are 12 bits wide. When a depth of less than 4 k is specified, the unused high-order bits must be grounded (Table 2-28). Table 2-27  Allowable Aspect Ratio Settings for WIDTHA[1:0] WIDTHA1, WIDTHA0 WIDTHB1, WIDTHB0 D×W 00 00 4k×1 01 01 2k×2 10 10 1k×4 11 11 512×9 Note: The aspect ratio settings are constant and cannot be changed on the fly. Table 2-28  Address Pins Unused/Used for Various Supported Bus Widths D×W ADDRx Unused Used 4k×1 None [11:0] 2k×2 [11] [10:0] 1k×4 [11:10] [9:0] 512×9 [11:9] [8:0] Note: The "x" in ADDRx implies A or B.

2-62 Preliminary v1.7 DINA and DINB These are the input data signals, and they are ni ne bits wide. Not all nine bits are valid in all configurations. When a data width less than nine is specified, unused hi gh-order signals must be grounded (Table 2-29). DOUTA and DOUTB These are the nine-bit output data signals. Not all nine bits are valid in all configurations. As with DINA and DINB, high-order bits may not be used ( Table 2-29). The output data on unused pins is undefined. Table 2-29  Unused/Used Input and Output Data Pins for Various Supported Bus Widths D×W DINx/DOUTx Unused Used 4k×1 [8:1] [0] 2k×2 [8:2] [1:0] 1k×4 [8:4] [3:0] 512×9 None [8:0] Note: The "x" in DINx and DOUTx implies A or B.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-63 RAM512X18 Description Figure 2-48  RAM512X18 RADDR8 RD17 RADDR7 RD16 RADDR0 RD0 WD17 WD16 WD0 WW1 WW0 RW1 RW0 PIPE REN RCLK RAM512X18 WADDR8 WADDR7 WADDR0 WEN WCLK RESET

2-64 Preliminary v1.7 RAM512X18 exhibits slightly differ ent behavior from RAM4K9, as it has dedicated read and write ports. WW and RW These signals en able the RAM to be configured in one of the two allowable aspect ratios (Table 2-30). WD and RD These are the input and output data signals, and they are 18 bits wide. When a 512×9 aspect ratio is used for write, WD[17:9] are unused and must be grounded. If this aspect ratio is used for read, then RD[17:9] are undefined. WADDR and RADDR These are read and write addresse s, and they are nine bits wide . When the 256×18 aspect ratio is used for write or read, WADDR[8] or RADDR[8] are unused and must be grounded. WCLK and RCLK These signals are the write and read clocks, respectively. They are both active high. WEN and REN These signals are the write and read enables, resp ectively. They are both active low by default. These signals can be configured as active high. RESET This active low signal resets the output to zero, disables reads and/or writes from the SRAM block, and clears the data hold registers when asserted. It does not reset the contents of the memory. PIPE This signal is used to specify pipelined read on the output. A LOW on PIPE indicates a nonpipelined read, and the data appears on the output in th e same clock cycle. A HIGH indicates a pipelined read, and data appears on the output in the next clock cycle. Clocking The dual-port SRAM blocks are only clocked on the rising edge. SmartGen allows falling-edge- triggered clocks by adding inverters to the netlist, hence achieving dual-port SRAM blocks that are clocked on either edge (rising or falling). For dual-port SRAM, each port can be clocked on either edge or by separate clocks, by port. Fusion devices support inversion (bubble pushing) throughout the FPGA architecture, including the clock input to the SRAM modules. Inversions added to the SRAM clock pin on the design schematic or in the HDL code will be automatically acco unted for during design compile without incurring additional delay in the clock path. The two-port SRAM can be clocked on the rising edge or falling edge of WCLK and RCLK. If negative-edge RAM and FIFO clocking is selected for memory macros, clock edge inversion management (bubble pushing) is automatically used within the Fusion development tools, without performance penalty. Table 2-30  Aspect Ratio Settings for WW[1:0] WW[1:0] RW[1:0] D×W 01 01 512×9 10 10 256×18 00, 11 00, 11 Reserved

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-65 Modes of Operation There are two read modes and one write mode:  Read Nonpipelined (synchronous—1 clock edge ): In the standard read mode, new data is driven onto the RD bus in the same clock cycle following RA and REN valid. The read address is registered on the read port clock active edge, and data appears at RD after the RAM access time. Setting PIPE to OFF enables this mode.  Read Pipelined (synchronous—2 clock edges): The pipelined mode incurs an additional clock delay from the address to the data but enables operation at a much higher frequency. The read address is registered on the read port active clock edge, and the read data is registered and appears at RD after the second read clock edge. Setting PIPE to ON enables this mode.  Write (synchronous—1 clock edge ): On the write clock active edge, the write data is written into the SRAM at the write address when WEN is HIGH. The setup times of the write address, write enables, and write data are minimal with resp ect to the write clock. Write and read transfers are described with timing requirements in the "SRAM Characteristics" section on page 2-66 and the "FIFO Characteristics" section on page 2-77. RAM Initialization Each SRAM block can be individually initialized on power-up by means of the JTAG port using the UJTAG mechanism (refer to the "JTAG IEEE 1532" section on page 2-224 and the Fusion SRAM/FIFO Blocks application note). The shift regi ster for a target block can be selected and loaded with the proper bit configuration to enable serial loading. The 4,608 bits of data can be loaded in a single operation.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-69 Figure 2-55  Read Access After Write onto Same Address CLK1 ADD1 WEN_B2 DI1 WEN_B1 CLK2 ADD2 DO2 (pass-through) DO2 (pipelined) tAS tAH tWRO Dn A0 A1 A4 tAS tAH tDS tDH tCKQ1 D0 D1 Dn D0 tCKQ2

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-71 Timing Characteristics Table 2-31  RAM4K9 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tAS Address Setup time 0.25 0.28 0.33 ns tAH Address Hold time 0.00 0.00 0.00 ns tENS REN_B,WEN_B Setup time 0.14 0.16 0.19 ns tENH REN_B, WEN_B Hold time 0.10 0.11 0.13 ns tBKS BLK_B Setup time 0.23 0.27 0.31 ns tBKH BLK_B Hold time 0.02 0.02 0.02 ns tDS Input data (DI) Setup time 0.18 0.21 0.25 ns tDH Input data (DI) Hold time 0.00 0.00 0.00 ns tCKQ1 Clock High to New Data Valid on DO (output retained, WMODE = 0) 1.79 2.03 2.39 ns Clock High to New Data Valid on DO (flow-through, WMODE = 1) 2.36 2.68 3.15 ns tCKQ2 Clock High to New Data Valid on DO (pipelined) 0.89 1.02 1.20 ns tWRO Address collision clk-to-clk delay for reliable read access after write on same address TBD TBD TBD ns tCCKH Address collision clk-to-clk delay for reliable write access after write/read on same address TBD TBD TBD ns tRSTBQ RESET_B Low to Data Out Low on DO (flow-through) 0.92 1.05 1.23 ns RESET_B Low to Data Out Low on DO (pipelined) 0.92 1.05 1.23 ns tREMRSTB RESET_B Removal 0.29 0.33 0.38 ns tRECRSTB RESET_B Recovery 1.50 1.71 2.01 ns tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 ns tCYC Clock Cycle time 3.23 3.68 4.32 ns FMAX Maximum Clock Frequency 310 272 231 MHz Note: For the derating values at specific junction temperature and voltage-supply levels, refer to Table 3-7 on page 3-9.

2-72 Preliminary v1.7 Table 2-32  RAM512X18 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tAS Address Setup time 0.25 0.28 0.33 ns tAH Address Hold time 0.00 0.00 0.00 ns tENS REN_B,WEN_B Setup time 0.09 0.10 0.12 ns tENH REN_B, WEN_B Hold time 0.06 0.07 0.08 ns tDS Input data (DI) Setup time 0.18 0.21 0.25 ns tDH Input data (DI) Hold time 0.00 0.00 0.00 ns tCKQ1 Clock High to New Data Valid on DO (output retained, WMODE = 0) 2.16 2.46 2.89 ns tCKQ2 Clock High to New Data Valid on DO (pipelined) 0.90 1.02 1.20 ns tWRO Address collision clk-to-clk delay for reliable read access after write on same address TBD TBD TBD ns tCCKH Address collision clk-to-clk delay for reliable write access after write/read on same address TBD TBD TBD ns tRSTBQ RESET_B Low to Data Out Low on DO (flow-through) 0.92 1.05 1.23 ns RESET_B Low to Data Out Low on DO (pipelined) 0.92 1.05 1.23 ns tREMRSTB RESET_B Removal 0.29 0.33 0.38 ns tRECRSTB RESET_B Recovery 1.50 1.71 2.01 ns tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 ns tCYC Clock Cycle time 3.23 3.68 4.32 ns FMAX Maximum Clock Frequency 310 272 231 MHz Note: For the derating values at specific junction temperature and voltage-supply levels, refer to Table 3-7 on page 3-9.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-73 FIFO4K18 Description Figure 2-58  FIFO4KX18 FIFO4K18 RW2 RD17 RW1 RD16 RW0 WW2 WW1 WW0 RD0 ESTOP FSTOP FULL AFULL EMPTY AFVAL11 AEMPTY AFVAL10 AFVAL0 AEVAL11 AEVAL10 AEVAL0 REN RBLK RCLK WEN WBLK WCLK RPIPE WD17 WD16 WD0 RESET

2-74 Preliminary v1.7 The following signals are used to configure the FIFO4K18 memory element: WW and RW These signals enable the FIFO to be configured in one of the five allowable aspect ratios (Table 2-33). WBLK and RBLK These signals are active low and will enable the respective ports when LOW. When the RBLK signal is HIGH, the corresponding port’s outputs hold the previous value. WEN and REN Read and write enables. WEN is active low and REN is active high by default. These signals can be configured as active high or low. WCLK and RCLK These are the clock signals for the synchronous read and write operations. These can be driven independently or with the same driver. RPIPE This signal is used to specify pipelined r ead on the output. A LO W on RPIPE indicates a nonpipelined read, and the data appears on the output in the same clock cycle. A HIGH indicates a pipelined read, and data appears on the output in the next clock cycle. RESET This active low signal re sets the output to zero when asserted . It resets the FIFO counters. It also sets all the RD pins LOW, the FULL and AFULL pins LOW, and the EMPTY and AEMPTY pins HIGH (Table 2-34). WD This is the input data bus and is 18 bits wide. Not all 18 bits are valid in all configurations. When a data width less than 18 is specified, unused higher-order signals must be grounded (Table 2-34). RD This is the output data bus and is 18 bits wide. Not all 18 bits are valid in all configurations. Like the WD bus, high-order bits become unusable if the data width is less than 18. The output data on unused pins is undefined (Table 2-34). Table 2-33  Aspect Ratio Settings for WW[2:0] WW2, WW1, WW0 RW2, RW1, RW0 D ×W 000 000 4k ×1 001 001 2k ×2 010 010 1k ×4 011 011 512 ×9 100 100 256 ×18 101, 110, 111 101, 110, 111 Reserved Table 2-34  Input Data Signal Usage for Different Aspect Ratios D×W WD/RD Unused 256×18 –

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-75 ESTOP, FSTOP ESTOP is used to stop the FIFO read counter from further counting once the FIFO is empty (i.e., the EMPTY flag goes HIGH). A HIGH on this signal inhibits the counting. FSTOP is used to stop th e FIFO write counter from further coun ting once the FIFO is full (i.e., the FULL flag goes HIGH). A HIGH on this signal inhibits the counting. For more information on th ese signals, refer to the "ESTOP and FSTOP Usage" section on page 2-76. FULL, EMPTY When the FIFO is full and no more data can be written, the FULL flag asserts HIGH. The FULL flag is synchronous to WCLK to inhibit writing immediately upon detection of a full condition and to prevent overflows. Since the write address is co mpared to a resynchron ized (and thus time- delayed) version of the read addr ess, the FULL flag will remain asserted until two WCLK active edges after a read operation eliminates the full condition. When the FIFO is empty and no more data can be read, the EMPTY flag asserts HIGH. The EMPTY flag is synchronous to RCLK to inhibit reading immediately upon detection of an empty condition and to prevent underflows. Since the read address is compared to a resynchronized (and thus time- delayed) version of the write address, the EMPT Y flag will remain asserted until two RCLK active edges after a write operation removes the empty condition. For more information on these signals, refer to the "FIFO Flag Usage Cons iderations" section on page 2-76. AFULL, AEMPTY These are programmable flags and will be asse rted on the threshold specified by AFVAL and AEVAL, respectively. When the number of words store d in the FIFO reaches the am ount specified by AEVAL while reading, the AEMPTY output will go HIGH. Likewise, when the number of words stored in the FIFO reaches the amount specified by AFVAL while writing, the AFULL output will go HIGH.

2-76 Preliminary v1.7 AFVAL, AEVAL The AEVAL and AFVAL pins are used to specify the almost-empty and almost-full threshold values, respectively. They are 12-bit signals. Fo r more information on these signals, refer to "FIFO Flag Usage Considerations" section. ESTOP and FSTOP Usage The ESTOP pin is used to stop th e read counter from co unting any further once the FIFO is empty (i.e., the EMPTY flag goes HIGH). Likewise, the FSTOP pin is used to stop the wr ite counter from counting any further once the FIFO is full (i.e., the FULL flag goes HIGH). The FIFO counters in the Fusion device start the count at 0, reach the maximum depth for the configuration (e.g., 511 for a 51 2×9 configuration), and then resta rt at 0. An exam ple application for the ESTOP, where the read counter keeps coun ting, would be writing to the FIFO once and reading the same content over and over without doing another write. FIFO Flag Usage Considerations The AEVAL and AFVAL pins are used to specify the 12-bit AEMPTY and AFULL threshold values, respectively. The FIFO contains separate 12-bi t write address (WADDR) and read address (RADDR) counters. WADDR is incremente d every time a write operation is performed, and RADDR is incremented every time a read operation is performed. Whenever the difference between WADDR and RADDR is greater than or equal to AFVAL, the AFULL out put is asserted. Likewise, whenever the difference between WADDR and RADDR is less than or equal to AEVAL, the AEMPTY output is asserted. To handle different read and write aspect ratios, AFVAL and AEVAL are expressed in terms of total data bits instead of total data word s. When users specify AFVAL and AEVAL in terms of read or write words, the SmartGen tool translat es them into bit addre sses and configures these signals automaticall y. SmartGen configures the AFULL flag to assert when the write address exceeds the read address by at least a predefined value. In a 2k×8 FIFO, for example, a value of 1,500 for AFVAL means that the AFULL flag will be asserted after a write when the difference between the write address and the read address reaches 1,500 (there have been at least 1500 more writes than reads). It will stay asserted until the difference be tween the write and read addresses drops below 1,500. The AEMPTY flag is asserted when the difference between the write address and the read address is less than a predefined value. In the exampl e above, a value of 200 for AEVAL means that the AEMPTY flag will be asserted when a read causes the difference between the write address and the read address to drop to 200. It will stay asserted until that difference rises above 200. Note that the FIFO can be configured with different read and write widths; in this case, the AFVAL setting is based on the number of write data entries and the AEVAL setting is based on the number of read data entries. For aspect ratios of 512×9 and 256×18, only 4,096 bits can be addressed by the 12 bits of AFVAL and AEVAL. The number of words must be multiplied by 8 and 16, instead of 9 and 18. The SmartGen tool automatically uses the proper values. To avoid halfwords being written or read, which could happen if different read and write aspect ratios are specified, the FIFO will assert FULL or EMPTY as soon as at least a minimum of one wo rd cannot be written or read. For example, if a two-bit word is written and a four-bit word is be ing read, the FIFO will remain in the empty state when the first word is written. This occurs even if the FIFO is not completely empty, because in this case, a complete word cannot be read. The same is applicable in the full state. If a four-bit word is written and a two-bit word is read, the FIFO is full and one word is read. The FULL flag will remain asserted because a complete word cannot be written at this point.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-79 Timing Characteristics Table 2-35  FIFO Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. Units tENS REN_B, WEN_B Setup time 1.34 1.52 1.79 ns tENH REN_B, WEN_B Hold time 0.00 0.00 0.00 ns tBKS BLK_B Setup time 0.19 0.22 0.26 ns tBKH BLK_B Hold time 0.00 0.00 0.00 ns tDS Input data (DI) Setup time 0.18 0.21 0.25 ns tDH Input data (DI) Hold time 0.00 0.00 0.00 ns tCKQ1 Clock High to New Data Valid on DO (flow-through) 2.17 2.47 2.90 ns tCKQ2 Clock High to New Data Valid on DO (pipelined) 0.94 1.07 1.26 ns tRCKEF RCLK High to Empty Flag Valid 1.72 1.96 2.30 ns tWCKFF WCLK High to Full Flag Valid 1.63 1.86 2.18 ns tCKAF Clock High to Almost Empty/Full Flag Valid 6.19 7.05 8.29 ns tRSTFG RESET_B Low to Empty/Full Flag Valid 1.69 1.93 2.27 ns tRSTAF RESET_B Low to Almost-Empty/Full Flag Valid 6.13 6.98 8.20 ns tRSTBQ RESET_B Low to Data out Low on DO (flow-through) 0.92 1.05 1.23 ns RESET_B Low to Data out Low on DO (pipelined) 0.92 1.05 1.23 ns tREMRSTB RESET_B Removal 0.29 0.33 0.38 ns tRECRSTB RESET_B Recovery 1.50 1.71 2.01 ns tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 ns tCYC Clock Cycle time 3.23 3.68 4.32 ns FMAX Maximum Frequency for FIFO 310 272 231 ns Note: For specific junction temperature and voltage-supply levels, refer to Table 3-7 on page 3-9 for derating values.

2-80 Preliminary v1.7 Analog Block With the Fusion family, Actel has introduced the wo rld's first mixed-mo de FPGA solution. Supporting a robust analog pe ripheral mix, Fusion devices will support a wide variety of applications. It is this Analog Block that se parates Fusion from all other FPGA solutions on the market today. By combining both flash and high-speed CMOS processes in a single chip, these devices offer the best of both worlds. The high-pe rformance CMOS is used for building RAM resources. These high- performance structures support device operation up to 350 MHz. Additionally, the advanced Actel 0.13 µm flash process incorporates high-voltage transistors and a high-isolation, triple-well process. Both of these are suited for the flash-ba sed programmable logic and nonvolatile memory structures. High-voltage transistors support the integration of analog technology in several ways. They aid in noise immunity so that the analog portions of th e chip can be better isolated from the digital portions, increasing analog accuracy. Because they support high voltages, Actel flash FPGAs can be connected directly to high-voltage input signals, el iminating the need for external resistor divider networks, reducing component count, and increasing accuracy. By supporting higher internal voltages, the Actel advanced flash process enab les high dynamic range on analog circuitry, increasing precision and signal–noise ratio. Acte l flash FPGAs also driv e high-voltage outputs, eliminating the need for external level shifters and drivers. The unique triple-well process en ables the integration of high-p erformance analog features with increased noise immunity and better isolation. By increasing the efficiency of analog design, the triple-well process also enables a smaller overall design size, reducing die size and cost. The Analog Block consists of the Analog Quad I/O structure, RTC (for details refer to the "Real-Time Counter System" section on page 2-34), ADC, and ACM. All of these elements are combined in the single Analog Block macro, with which the user implements this functionality (Figure 2-64). The Analog Block needs to be reset/reinitialized after the core powers up or the device is programmed. An external reset/initialize sign al, which can come from the internal voltage regulator when it powers up, must be applied.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-81 Figure 2-64  Analog Block Macro VAREF GNDREF AV0 AC0 AT0 AV9 AC9 AT9 ATRETURN01 ATRETURN9 DENAV0 DENAC0 DAVOUT0 DACOUT0 DATOUT0 DACOUT9 DAVOUT9 DATOUT9 AG1 AG0 AG9 DENAT0 DENAV0 DENAC0 DENAT0 CMSTB0 CSMTB9 GDON0 GDON9 TMSTB0 TMSTB9 MODE[3:0] TVC[7:0] STC[7:0] CHNUMBER[4:0] TMSTINT ADCSTART VAREFSEL PWRDWN ADCRESET BUSY CALIBRATE DATAVALID SAMPLE RESULT[11:0] RTCMATCH RTCXTLMODE RTCXTLSEL RTCPSMMATCH RTCCLK SYSCLK ACMWEN ACMRDATA[7:0] ACMRESET ACMWDATA ACMADDR ACMCLK AB

2-82 Preliminary v1.7 Table 2-36 describes each pin in the Analog Block. Each function within the Analog Block will be explained in detail in the following sections. Table 2-36  Analog Block Pin Description Signal Name Number of Bits Direction Function Location of Details VAREF 1 Input/Output Voltage reference for ADC ADC GNDREF 1 Input External ground reference ADC MODE[3:0] 4 Input ADC operating mode ADC SYSCLK 1 Input External system clock TVC[7:0] 8 Input Clock divide control ADC STC[7:0] 8 Input Sample time control ADC ADCSTART 1 Input Start of conversion ADC PWRDWN 1 Input Comparator power-down if 1 ADC ADCRESET 1 Input ADC resets and disables Analog Quad – active high ADC BUSY 1 Output 1 – Running conversion ADC CALIBRATE 1 Output 1 – Power-up calibration ADC DATAVALID 1 Output 1 – Valid conversion result ADC RESULT[11:0] 12 Output Conversion result ADC TMSTBINT 1 Input Internal temp. monitor strobe ADC SAMPLE 1 Output 1 – An analog signal is actively being sampled (stays hi gh during signal acquisition only) 0 – No analog signal is being sampled ADC VAREFSEL 1 Input 0 = Output internal voltage reference (2.56 V) to VAREF 1 = Input external voltage reference from VAREF and GNDREF ADC CHNUMBER[4:0] 5 Input Analog input channel select Input multiplexer ACMCLK 1 Input ACM clock ACM ACMWEN 1 Input ACM write en able – active high ACM ACMRESET 1 Input ACM reset – active low ACM ACMWDATA[7:0] 8 Input ACM write data ACM ACMRDATA[7:0] 8 Output ACM read data ACM ACMADDR[7:0] 8 Input ACM address ACM CMSTB0 to CMSTB9 10 Input Current monitor strobe – 1 per quad, active high Analog Quad GDON0 to GDON9 10 Input Control to power MOS – 1 per quad Analog Quad TMSTB0 to TMSTB9 10 Input Tempera ture monitor strobe – 1 per quad; active high Analog Quad

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-83 DAVOUT0, DACOUT0, DATOUT0 to DAVOUT9, DACOUT9, DATOUT9

30 Output Digital outputs – 3 per quad Analog Quad

DENAV0, DENAC0, DENAT0 to DENAV9, DENAC9, DENAT9

30 Input Digital input enable s – 3 per quad Analog Quad

AV0 1 Input Analog Quad 0 Analog Quad AC0 1 Input Analog Quad AG0 1 Output Analog Quad AT0 1 Input Analog Quad ATRETURN01 1 Input Temperatur e monitor return shared by Analog Quads 0 and 1 Analog Quad AV1 1 Input Analog Quad 1 Analog Quad AC1 1 Input Analog Quad AG1 1 Output Analog Quad AT1 1 Input Analog Quad AV2 1 Input Analog Quad 2 Analog Quad AC2 1 Input Analog Quad AG2 1 Output Analog Quad AT2 1 Input Analog Quad ATRETURN23 1 Input Temperatur e monitor return shared by Analog Quads 2 and 3 Analog Quad AV3 1 Input Analog Quad 3 Analog Quad AC3 1 Input Analog Quad AG3 1 Output Analog Quad AT3 1 Input Analog Quad AV4 1 Input Analog Quad 4 Analog Quad AC4 1 Input Analog Quad AG4 1 Output Analog Quad AT4 1 Input Analog Quad ATRETURN45 1 Input Temperatur e monitor return shared by Analog Quads 4 and 5 Analog Quad AV5 1 Input Analog Quad 5 Analog Quad AC5 1 Input Analog Quad AG5 1 Output Analog Quad AT5 1 Input Analog Quad AV6 1 Input Analog Quad 6 Analog Quad AC6 1 Input Analog Quad AG6 1 Output Analog Quad AT6 1 Input Analog Quad Table 2-36  Analog Block Pin Description (continued) Signal Name Number of Bits Direction Function Location of Details

2-84 Preliminary v1.7 Analog Quad With the Fusion family, Actel intro duces the Analog Quad, shown in Figure 2-65 on page 2-85, as the basic analog I/O structure. The Analog Quad is a four-channel system used to precondition a set of analog signals before sending it to the ADC for conversion into a digital signal. To maximize the usefulness of the Analog Quad, th e analog input signals can also be configured as LVTTL digital input signals. The Analog Quad is divided into four sections. The first section is called the Vo ltage Monitor Block, and its input pin is named AV. It contains a two-channel analog multiplexer that allows an incoming analog signal to be routed directly to the A D C o r a l l o w s t h e s i g n a l t o b e r o u t e d t o a p rescaler circuit before being sent to the ADC. The prescaler can be configured to accept analog signals between –12 V and 0 or between 0 and +12 V. The prescaler circuit scales the voltage applied to the ADC input pad such that it is compatible with the ADC input voltage range. The AV pin can also be used as a digital input pin. The second section of the Analog Quad is called the Current Monitor Block. Its input pin is named AC. The Current Moni tor Block contains all th e same functions as the Voltage Monitor Block with one addition, which is a current monitoring func tion. A small external current sensing resistor (typically less than 1 Ω) is connected between the AV and AC pins and is in series with a power source. The Current Monitor Block contains a cu rrent monitor circuit th at converts the current through the external resistor to a voltage that can then be read using the ADC. The third part of the Analog Quad is called the Gate Driver Block, and its output pin is named AG. This section is used to drive an external FET. There are two modes availabl e: a High Current Drive mode and a Current Source Control mode. Both negative and positive voltage polarities are available, and in the current source control mode, four different current levels are available. ATRETURN67 1 Input Temperatur e monitor return shared by Analog Quads 6 and 7 Analog Quad AV7 1 Input Analog Quad 7 Analog Quad AC7 1 Input Analog Quad AG7 1 Output Analog Quad AT7 1 Input Analog Quad AV8 1 Input Analog Quad 8 Analog Quad AC8 1 Input Analog Quad AG8 1 Output Analog Quad AT8 1 Input Analog Quad ATRETURN89 1 Input Temperatur e monitor return shared by Analog Quads 8 and 9 Analog Quad AV9 1 Input Analog Quad 9 Analog Quad AC9 1 Input Analog Quad AG9 1 Output Analog Quad AT9 1 Input Analog Quad RTCMATCH 1 Output MATCH RTC RTCPSMMATCH 1 Output MATCH connected to VRPSM RTC RTCXTLMODE[1:0] 2 Output Drives XTLOSC RTCMODE[1:0] pins RTC RTCXTLSEL 1 Output Drives XTLOSC MODESEL pin RTC RTCCLK 1 Input RTC clock input RTC Table 2-36  Analog Block Pin Description (continued) Signal Name Number of Bits Direction Function Location of Details

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-85 The fourth section of th e Analog Quad is called the Temperat ure Monitor Block, and its input pin name is AT. This block is similar to the Voltage Monitor Block, except th at it has an additional function: it can be used to monitor the temperat ure of an external diode-connected transistor. It has a modified prescaler and is limited to positive voltages only. The Analog Quad can be configured during design time by Actel Libero IDE; however, the ACM can be used to change the parameters of any of th ese I/Os during runtime. This type of change is referred to as a context switch. The Analog Quad is a modular structure th at is replicated to generate the analog I/O resources. Each Fusion device supports between 5 and 10 Analog Quads. The analog pads are numb ered to clearly identify both the type of pad (voltage, current, gate driver, or temperature pad) and its corresponding Analog Quad (AV0, AC0, AG0, AT0, AV1, …, AC9, AG9, and AT9). There are three types of input pads (AVx, ACx, and ATx) and one type of analog output pad (AGx). Since there can be up to 10 Analog Quads on a device, there can be a maximum of 30 analog input pads and 10 analog output pads. Figure 2-65  Analog Quad Analog Quad AV AC AT Voltage Monitor Block Current Monitor Block AG Prescaler Prescaler Prescaler Digital Input Power MOSFET Gate Driver Current Monitor/Instr Amplifier Temperature Monitor Digital Input Digital Input Pads To Analog MUX To Analog MUX To Analog MUX To FPGA (DAVOUTx) To FPGA (DACOUTx) To FPGA (DATOUTx) On-Chip Gate Driver Temperature Monitor Block Off-Chip From FPGA (GDONx)

2-86 Preliminary v1.7 Voltage Monitor The Fusion Analog Quad offers a robust set of voltage-monitoring capabilities unique in the FPGA industry. The Analog Quad comprises three an alog input pads— Analog Voltage (AV), Analog Current (AC), and Analog Temperature (AT)—and a single gate driver output pad, Analog Gate (AG). There are many common characteristics among the analog input pads. Each analog input can be configured to connect directly to the input MUX of the ADC. When configured in this manner (Figure 2-66), there will be no prescaling of the input signal. Care must be taken in this mode not to drive the ADC into sa turation by applying an input voltag e greater than the reference voltage. The internal reference voltage of the ADC is 2.56 V. Optionally , an external reference can be supplied by the user. The external reference can be a maximum of 3.3 V DC. Figure 2-66  Analog Quad Direct Connect Prescaler Prescaler Prescaler Analog Quad AV AC AT Voltage Monitor Block Current Monitor Block AG Digital Input Power MOSFET Gate Driver Current Monitor / Instr Amplifier Temperature Monitor Digital Input Digital Input Pads To Analog MUX To Analog MUX To Analog MUX To FPGA (DAVOUTx) To FPGA (DACOUTx) To FPGA (DATOUTx) On-Chip Gate Driver Temperature Monitor Block Off-Chip From FPGA (GDONx)

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-87 The Analog Quad offers a wide variety of prescaling options to enable the ADC to resolve the input signals. Figure 2-67 shows the path through the Analog Quad for a signal that is to be prescaled prior to conversion. The ADC internal reference voltage and the prescaler factors were selected to make both prescaling and postscaling of the signals easy binary calculations (refer to Table 2-54 on page 2-128 for details). When an analog input pad is co nfigured with a prescaler, there will be a 1M Ω resistor to ground. This occurs even when the device is in power-down mode. In low power standby or sleep mode (V CC is OFF, V CC33A is ON, V CCI is ON) or when the resource is not used, analog inputs are pulled down to ground through a 1 M Ω resistor. The gate driver output is floating (or tristated), and there is no extra current on VCC33A. These scaling factors hold true whether the particular pad is configured to accept a positive or negative voltage. Note that whereas the AV and AC pads support the same prescaling factors, the AT pad supports a reduced set of prescaling factors and supports positive voltages only. Typical scaling factors are given in Table 2-54 on page 2-128, and the gain error (which contributes to the minimum and maximum) is in Table 2-46 on page 2-115. Figure 2-67  Analog Quad Prescaler Input Configuration Prescaler Prescaler Prescaler Analog Quad AV AC AT Voltage Monitor Block Current Monitor Block AG Digital Input Power MOSFET Gate Driver Current Monitor / Instr Amplifier Temperature Monitor Digital Input Digital Input Pads To Analog MUX To Analo g MUX To Analo g MUX To FPGA (DAVOUTx) To FPGA (DACOUTx) To FPGA (DATOUTx) On-Chip Gate Driver Temperature Monitor Block Off-Chip From FPGA (GDONx)

2-88 Preliminary v1.7 Terminology BW – Bandwidth BW is a range of frequencies that a Channel can handle. Channel A channel is define as an an alog input configured as one of the Prescaler range shown in Table 2-54 on page 2-128. The channel includes the Prescaler circuit and the ADC. Channel Gain Channel Gain is a measured of the deviation of th e actual slope from the ideal slope. The slope is measured from the 20% and 80% point. EQ 2-1 Channel Gain Error Channel Gain Error is a deviation from the ideal slope of the transfer function. The Prescaler Gain Error is expressed as the percent difference between the actual and ideal, as shown in EQ 2-2. EQ 2-2 Channel Input Offset Error Channel Offset error is measured as the input voltage that causes the transition from zero to a count of one. An Ideal Prescaler will have offset equal to ½ of LSB voltage. Offset error is a positive or negative when the first transition point is higher or lower than ideal. Offset error is expressed in LSB or input voltage. Total Channel Error Total Channel Error is defined as the total erro r measured compared to the ideal value. Total Channel Error is the sum of gain error and offset error combined. Figure 2-68 shows how Total Channel Error is measured. Total Channel Error is defined as the difference between the actual AD C output and ideal ADC output. In the example shown in Figure 2-68, the Total Channel Error would be a negative number. Figure 2-68  Total Channel Error Example Gain Gainactual Gainideal ErrorGain (1-Gain) 100%×= ADC Output CodeIdeal Output Input Voltage to Prescaler Total Channel Error Channel Gain Actual Output Channel Input Offset Error

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-89 Direct Digital Input The AV, AC, and AT pads can also be configured as high-voltage digital inputs ( Figure 2-69). As these pads are 12 V–tolerant, the digital input can also be up to 12 V. However, the frequency at which these pads can operate is limited to 10 MHz. To enable one of these analog input pads to oper ate as a digital input, its corresponding Digital Input Enable (DENAxy) pin on the Analog Block mu st be pulled HIGH, where x is either V , C, or T (for AV, AC, or AT pads, respectively) and y is in the range 0 to 9, corresponding to the appropriate Analog Quad. When the pad is configured as a digital input, th e signal will come out of the Analog Block macro on the appropriate DAxOUTy pin, where x represents the pad type (V for AV pad, C for AC pad, or T for AT pad) and y represents the appropriat e Analog Quad number. Ex ample: If the AT pad in Analog Quad 5 is configured as a digital input, it will come out on the DATOUT5 pin of the Analog Block macro. Figure 2-69  Analog Quad Direct Digital Input Configuration Analog Quad AV AC AT Voltage Monitor Block Current Monitor Block AG Digital Input Power MOSFET Gate Driver Current Monitor / Instr Amplifier Temperature Monitor Digital Input Digital Input Pads To Analog MUX To Analog MUX To Analog MUX To FPGA (DAVOUTx) To FPGA (DACOUTx) To FPGA (DATOUTx) On-Chip Gate Driver Temperature Monitor Block Off-Chip From FPGA (GDONx) PrescalerPrescalerPrescaler

2-90 Preliminary v1.7 Current Monitor The Fusion Analog Quad is an excellent element for voltage- and current-monitoring applications. In addition to supporting the same functionality offered by the AV pad, the AC pad can be configured to monitor current acro ss an external sense resistor ( Figure 2-70). To support this current monitor function, a differential amplifier with 10x ga in passes the amplified voltage drop between the AV and AC pads to the ADC. The amplifier enables the user to use very small resistor values, thereby limiting an y impact on the circuit. This function of the AC pad does not limit AV pad operation. The AV pad can still be configured for use as a direct voltage input or scaled through the AV prescaler independently of it’s use as an input to the AC pad’s differential amplifier. Figure 2-70  Analog Quad Current Monitor Configuration PrescalerPrescalerPrescaler Analog Quad AV AC AT Voltage Monitor Block Current Monitor Block AG Power Digital Input Power MOSFET Gate Driver Current Monitor / Instr Amplifier Temperature Monitor Digital Input Digital Input Pads To Analog MUX To Analog MUX To Analog MUX To FPGA (DAVOUTx) To FPGA (DACOUTx) To FPGA (DATOUTx) On-Chip Gate Driver Temperature Monitor Block Off-Chip From FPGA (GDONx)

2-92 Preliminary v1.7 Care must be taken when choosi ng the right re sistor for current measur ement application. Note that because of the 10× amplification, the maxi mum measurable difference between the AV and AC pads is V AREF / 10. A larger AV-to-AC voltage drop will result in ADC saturation; that is, the digital code put out by the ADC will stay fixed at the full scale value. Therefore, the user must select the external sense resistor appropriately. Table 2-37 shows recommended resistor values for different current measurement ranges. When choosing resistor values for a system, there is a trade- off between measurement accuracy and power consumption. Choosing a large resistor will increase the voltage drop and hence increase accuracy of the measurement; however the larger voltage drop dissipates more power (P = I2 × R). The Current Monitor is a unipolar system, meaning that the diff erential voltage swing must be from 0 V to V AREF/10. Therefore, the Current Monitor only supports differential voltage where |VAV-VAC| is greater than 0 V. This results in the requirement that the potential of the AV pad must be larger than the potential of the AC pad. This is straightforward for positive voltage systems. For a negative voltage system, it means that the AV pad must be "more negative" than the AC pad. This is shown in Figure 2-73. In this case, both the AV pad and the AC pad are configured for negati ve operations and the output of the differential amplifier still falls between 0 V and VAREF as required. Figure 2-72  Positive Current Monitor 0-12 V RSENSE I ACxAVx CMSTBx 10 X Current Monitor VADC to Analog MUX (refer Table 2-36 for MUX channel number)

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-93 Terminology Accuracy The accuracy of Fusion Current Monitor is ±2 mV minimum plus 5% of the differential voltage at the input. The input accuracy can be transla ted to error at the ADC output by using EQ 2-4. The

10 V/V gain is the gain of the Current Monitor Circuit, as described in the "Current Monitor"

section on page 2-90. For 8-bit mode, N = 8, VAREF= 2.56 V, zero differential voltage between AV and AC, the Error (EADC) is equal to 2 LSBs. EQ 2-4 where N is the number of bits VAREF is the Reference voltage VAV is the voltage at AV pad VAC is the voltage at AC pad Table 2-37  Recommended Resistor for Different Current Range Measurement Current Range Recommended Minimum Resistor Value (Ohms) > 5 mA – 10 mA 10 – 20 > 10 mA – 20 mA 5 – 10 > 20 mA – 50 mA 2.5 – 5 > 50 mA – 100 mA 1 – 2 > 100 mA – 200 mA 0.5 – 1 > 200 mA – 500 mA 0.3 – 0.5 > 500 mA – 1 A 0.1 – 0.2 > 1 A – 2 A 0.05 – 0.1 > 2 A – 4 A 0.025 – 0.05 > 4 A – 8 A 0.0125 – 0.025 > 8 A – 12 A 0.00625 – 0.02 Figure 2-73  Negative Current Monitor IRSENSE0 to –10.5 V AVx ACx CMSTBx 10 X VADC Current Monitor to Analog MUX (refer Table 2-36 for MUX channel number) EADC 2mV 0.05 VAV VAC–+() 10V() V⁄× 2N VAREF

2-94 Preliminary v1.7 Gate Driver The Fusion Analog Quad includes a Gate Driver connected to the Quad's AG pin ( Figure 2-74). Designed to work with external p- or n-channel MOSFETs, the Gate driver is a configurable current sink or source and requires an external pull-up or pull-down resistor. The AG supports 4 selectable gate drive levels: 1 µA, 3 µA, 10 µA, and 30 µA ( Figure 2-75 on page 2-95). The AG also supports a High Current Drive mode in which it can sink 20 mA; in this mode the switching rate is approximately 1.3 MHz with 100 ns turn-on time and 600 ns turn-off time. Modeled on an open- drain-style output, it does not output a voltage level without an appropriate pull-up or pull-down resistor. If 1 V is forced on the drain, the current sinking/sourcing will exceed the ability of the transistor, and the device could be damaged. The AG pad is turned on via the corresponding GDON x pin in the Analog Block macro, where x is the number of the corresponding Analog Quad for the AG pad to be enabled (GDON0 to GDON9). The gate-to-source voltage (V gs) of the external MOSFET is li mited to the programmable drive current times the external pull-up or pull-down resistor value (EQ 2-5). Vgs ≤ Ig × (Rpullup or Rpulldown) EQ 2-5 The rate at which the gate volt age of the external MOSFET slews is determined by the current, I g, sourced or sunk by the AG pin and the gate-to-source capacitance, CGS, of the external MOSFET. As an approximation, the slew rate is given by EQ 2-6. dv/dt = Ig / CGS EQ 2-6 Figure 2-74  Gate Driver Analog Quad AV AC AT Voltage Monitor Block Current Monitor Block AG Power Line Side Load Side Digital Input Power MOSFET Gate Driver Current Monitor / Instr Amplifier Temperature Monitor Digital Input Digital Input Pads To Analog MUX To Analog MUX To Analog MUX To FPGA (DAVOUTx) To FPGA (DACOUTx) To FPGA (DATOUTx) On-Chip Gate Driver Temperature Monitor Block Off-Chip Rpullup From FPGA (GDONx) PrescalerPrescalerPrescaler

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-95 CGS is not a fixed capacitance but, depending on th e circuitry connected to its drain terminal, can vary significantly during the course of a turn-on or turn-o ff transient. Thus, EQ 2-6 on page 2-94 can only be used for a first-order estimate of the switching speed of the external MOSFET. Figure 2-75  Gate Driver Example AG High Current 1 µA 3 µA 10 µA 30 µA 1 µA 3 µA 10 µA 30 µA

2-96 Preliminary v1.7 Temperature Monitor The final pin in the Analog Quad is the Analog Temperature (AT) pin. The AT pin is used to implement an accurate temperature monitor in conjunction with an external diode-connected bipolar transistor ( Figure 2-76). For improved temperature measurement accuracy, it is important to use the ATRTN pin for the retu rn path of the current sourced by the AT pin. Each ATRTN pin is shared between two adjacent Analog Quads. Additionally, if not used for temperature monitoring, the AT pin can provide functionality similar to that of the AV pad. However, in this mode only positive voltages can be applied to the AT pin, and only two pr escaler factors are available (16 V and 4 V ranges—refer to Table 2-54 on page 2-128). Fusion uses a remote diode as a temperature sensor. The Fusion Temp erature Monitor uses a differential input; the AT pin and ATRTN (AT Return) pin are the diff erential inputs to the Figure 2-76  Temperature Monitor Quad Analog Quad AV AC AT Voltage Monitor Block Current Monitor Block AG Digital Input Power MOSFET Gate Driver Current Monitor / Instr Amplifier Temperature Monitor Digital Input Digital Input Pads To Analog MUX To Analog MUX To Analog MUX To FPGA (DAVOUTx) To FPGA (DACOUTx) To FPGA (DATOUTx) On-Chip Gate Driver Temperature Monitor Block Off-Chip From FPGA (GDONx) PrescalerPrescalerPrescaler ATRTN Discrete Bipolar Transistor

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-97 Temperature Monitor. There is one Temperature Monitor in each Quad. A simplified block diagram is shown in Figure 2-77. The Fusion approach to measuring temperature is forcing two different currents through the diode with a ratio of 10:1. The switch that controls the different currents is controlled by the Temperature Monitor Strobe signal, TMSTB. Setting TMSTB to '1' will initiate a Temperature reading. The TMSTB should remain '1' until the ADC finishes sampling the voltage from the Temperature Monitor. The minimum sample time for the Temperature Monitor cannot be less than the minimum strobe high time minus the setup time. Figure 2-78 shows the timing diagram. The diode’s voltage is measured at each current level and the temperature is calculated based on EQ 2-7. EQ 2-7 Figure 2-77  Block Diagram for Temperature Monitor Circuit Figure 2-78  Timing Diagram for the Temperature Monitor Strobe Signal TMSTBx VDD33A ATRTNxy ATx

12.5 X∆V

(refer Table 2-36 for MUX Channel Number) VADC 100 µA10 µA VADC TMSTBx ADC should start sampling at this point ADCSTART tTMSLO tTMSHI tTMSSET VTMSLO VTMSHI– nkT ITMSLO ITMSHI ⎛⎞=

2-98 Preliminary v1.7 where ITMSLO is the current when the Temperature Strobe is Low, typically 100 µA ITMSHI is the current when the Temperature Strobe is High, typically 10 µA VTMSLO is diode voltage while Temperature Strobe is Low VTMSHI is diode voltage while Temperature Strobe is High n is the non-ideality factor of the diode-connecte d transistor. It is typically 1.004 for the Actel- recommended transistor type 2N3904. K = 1.3806 x 10-23 J/K is the Boltzman constant Q = 1.602 x 10-19 C is the charge of a proton When ITMSLO / ITMSHI = 10, the equation can be simplified as shown in EQ 2-8. EQ 2-8 In the Fusion TMB, the ideality factor n for 2N3904 is 1.004 and ΔV is amplified 12.5 times by an internal amplifier; hence the voltage before entering the ADC is as given in EQ 2-9. EQ 2-9 This means the temperature to voltage relationship is 2.5 mV per degree Kelvin. The unique design of Fusion has made the Temperature Monitor Sys tem simple for the user. When the 10-bit mode ADC is used, each LSB represents 1 degree Kelvin, as shown in EQ 2-10. That is, e. 25°C is equal to 293°K and is represented by decimal 293 counts from the ADC. EQ 2-10 If 8-bit mode is used for the ADC resolution, eac h LSB represents 4 degrees Kelvin; however, the resolution remains as 1 degree Kelvin per LSB , even for 12-bit mode, due to the Temperature Monitor design. An example of the temperature data format for 10-bit mode is shown in Table 2-38. Table 2-38  Temperature Data Format Temperature Temperature (K) Digital Output (ADC 10-bit mode) –40°C 233 00 1110 1001 –20°C 253 00 1111 1101 0°C 273 01 0001 0001 1°C 274 01 0001 0010 10 °C 283 01 0001 1011 25°C 298 01 0010 1010 50 °C 323 01 0100 0011 85 °C 358 01 0110 0110 ΔVV TMSLO VTMSHI– 1.986 10 4–× nT== VADC ΔV 12.5× 2.5 mV KT×()⁄== 1K 2.5 mV 210

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-99 Terminology Resolution Resolution defines the sma llest temperature change Fusion Temperature Monitor can resolve. For ADC configured as 8-bit mode, each LSB represents 4°C, and 1°C per LSB for 10-bit mode. With 12- bit mode, the Temperature Monitor can still only resolve 1°C due to Temperature Monitor design. Offset The Fusion Temperature Monitor has a systematic offset of +5°C, excluding error due board resistance and ideality factor of the external diod e, between the operation range of –40°C to +85°C. For instance, 25°C will be read by the Temperature Monitor as 30°C plus error. The user can remove any offset error through hardware or software during the calibration routine.

2-100 Preliminary v1.7 Analog-to-Digital Converter Block At the heart of the Fusi on analog system is a programmable Successive Approximation Register (SAR) ADC. The ADC can support 8-, 10-, or 12-bit modes of operation. In 12-bit mode, the ADC can resolve 500 ksps. All results are MSB-justified in the ADC. The input to the ADC is a large 32:1 analog input multiplexer. A simplified block diagram of the Analog Quads, analog input multiplexer, and ADC is shown in Figure 2-79. The ADC offers multiple self-calibrating modes to ensure consistent high performance both at power-up and during runtime. Figure 2-79  ADC Block Diagram ADC 12Analog MUX (32 to 1) Temperature Monitor Pads Internal Diode Digital Output to FPGA AV0 AC0 AG0 AT0 AV1 AC1 AG1 AT1 AV2 AC2 AG2 AT2 AV3 AC3 AG3 AT3 AV4AC4AG4AT4 AV5 AC5 AG5 AT5 AV6 AC6 AG6 AT6 AV7 AC7 AG7 AT7 AV8 AC8 AG8 AT8 AV9 AC9 AG9 AT9 ATRETURN89 ATRETURN67 ATRETURN45 ATRETURN23 ATRETURN01 Analog Quad 0 Analog Quad 4 Analog Quad 5 Analog Quad 6 Analog Quad 7 Analog Quad 8 Analog Quad 9 Analog Quad 3 Analog Quad 2 Analog Quad 1 VCC (1.5 V) These are hardwired connections within Analog Quad. CHNUMBER[4:0]

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-101 ADC Input Multiplexer At the input to the Fusion ADC is a 32:1 multiplexer. Of the 32 input channels, up to 30 are user definable. Two of these channels are hardwire d internally. Channel 31 connects to an internal temperature diode so the temperature of the Fusion device itself can be monitored. Channel 0 is wired to the FPGA’s 1.5 V VCC supply, enabling the Fusion device to monitor its own power supply. Doing this internally makes it unnecessary to use an analog I/ O to support these functions. The balance of the MUX inputs are conn ected to Analog Quads (see the "Analog Quad" section on page 2-84). Table 2-39 defines which Analog Quad inputs are associated with which specific analog MUX channels. The number of Analog Quads present is device-dependent; refer to the family list in the "Fusion Family" table on page I of this datasheet for the number of quads per device. Regardless of the number of quads populated in a device, the internal connections to both VCC and the internal temperature diode remain on Channels 0 and 31, respectively. To sample the internal temperature monitor, it must be strobed (similar to the AT pads). The TMSTBINT pin on the Analog Block macro is the control for strobing the internal temperature measurement diode. To determine which channel is sele cted for conversion, there is a five-pin interface on the Analog Block, CHNUMBER[4:0], defined in Table 2-40 on page 2-102 . Table 2-39 shows the correlation between the analog MUX input channels and the analog input pins. Table 2-39  Analog MUX Channels Analog MUX Channel Signal Analog Quad Number

0 Vcc_analog

1 AV0 Analog Quad 0

4 AV1 Analog Quad 1

7 AV2 Analog Quad 2

10 AV3 Analog Quad 3

11 AC3

12 AT3

13 AV4 Analog Quad 4

14 AC4

15 AT4

16 AV5 Analog Quad 5

17 AC5

18 AT5

19 AV6 Analog Quad 6

20 AC6

21 AT6

2-102 Preliminary v1.7

22 AV7 Analog Quad 7

23 AC7

24 AT7

25 AV8 Analog Quad 8

26 AC8

27 AT8

28 AV9 Analog Quad 9

29 AC9

30 AT9

31 Internal temperature

Table 2-40  Channel Selection Channel Number CHNUMBER[4:0] 0 00000 1 00001 2 00010 3 00011 30 11110 31 11111 Table 2-39  Analog MUX Channels (continued) Analog MUX Channel Signal Analog Quad Number

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-103 ADC Description The Actel Fusion ADC is a 12-bit SAR ADC. It offers a wide variet y of features for different use models. Figure 2-80 shows a block diagram of the Fusion ADC.  Configurable resolution: 8-bit, 10-bit, and 12-bit mode  DNL: 0.6 LSB for 10-bit mode  INL: 0.4 LSB for 10-bit mode  No missing code  Internal VAREF = 2.56 V  Maximum Sample Rate = 600 ksps  Power-up calibration and dynamic calibration after every sample to compensate for temperature drift over time ADC Configuration Description The Fusion ADC can be configured to operate in 8-, 10-, or 12-bit modes, power-down after conversion, and dynamic calibration. This is controlled by MODE[3:0], as defined in Table 2-41. Figure 2-80  ADC Simplified Block Diagram Table 2-41  Mode Bits Function Name Bits Function MODE 3 0 – Internal calibration after ever y conversion; two ADCCLK cycles are used after the conversion. 1 – No calibration after every conversion MODE 2 0 – Power-down after conversion 1 – No Power-down after conversion MODE 1:0 00 – 10-bit 01 – 12-bit 10 – 8-bit 11 – Unused TVCSYSCLK ADCCLK Signals from Analog Quads CHNUMBER SAR ADC STC MODE RESULT DATAVALID BUSY STATUS SAMPLE CALIBRATE VAREFAnalog MUX 32 12

2-104 Preliminary v1.7 The speed of the ADC depends on its internal cloc k, ADCCLK, which is not accessible to users. The ADCCLK is derived from SYSCLK. Input signal TVC[7:0], Time Divider Control, determines the speed of the ADCCLK in relationship to SYSCLK, based on EQ 2-11. EQ 2-11 TVC: Time Divider Control (0–255) t ADCCLK is the period of ADCCLK, and must be between 0.5 MHz and 10 MHz tSYSCLK is the period of SYSCLK The frequency of ADCCLK, fADCCLK, must be within 0.5 Hz to 10 MHz. The inputs to the ADC are synchronized to SYSC LK. A conversion is init iated by asserting the ADCSTART signal on a rising edge of SYSCLK. Figure 2-82 on page 2-108 and Figure 2-83 on page 2-108 show the timing diagram for the ADC. A conversion is performed in three phases. In the first phase, the analog input voltage is sampled on the input capacitor. This phase is called sa mple phase. During the sample phase, the output signals BUSY and SAMPLE change from '0' to '1', indicating the ADC is busy and sampling the analog signal. The sample time can be controlled by input signals STC[7:0]. The sample time can be calculated by EQ 2-12. When controlling the sample time for the ADC along with the use of Prescaler or Current Monitor or Temperature Monitor, the minimum sample time for each must be obeyed. Refer to the corresponding section and Table 2-43 for further information. EQ 2-12 STC: Sample Time Control value (0–255) tSAMPLE is the sample time Sample time is computed based on the period of ADCCLK. The second phase is called the distribution phase. During distribution phase, the ADC computes the equivalent digital value from the value stored in the input capacito r. In this phase, the output signal SAMPLE goes back to '0', indicating the sample is comple ted; but the BUSY signal remains '1', indicating the ADC is still busy for distribu tion. The distribution time depends strictly on the number of bits. If the ADC is configured as a 10-bit ADC, then 10 ADCCLK cycles are needed. EQ 2- 13 describes the distribution time. EQ 2-13 N: Number of bits The last phase is the post-calibratio n phase. This is an optional phase. The post-calibration phase takes two ADCCLK cycles. The output BUSY signal will remain '1' until the post-calibration phase is completed. If the post-calibrati on phase is skipped, then the BUSY signal goes to '0' after distribution phase. As soon as BUSY signal goes to '0', the DATAVALID signal goes to '1', indicating the digital result is available on the RESULT output signals. DATAVAILD will remain '1' until the next ADCSTART is asserted. Actel recommends enabling post-calibration to comp ensate for drift and temperature-dependent effects. This ensures that the ADC remains consistent over time and with Table 2-42  TVC Bits Function Name Bits Function TVC [7:0] SYSCLK divider control Table 2-43  STC Bits Function Name Bits Function STC [7:0] Sample time control tADCCLK 4 1 TVC+()× tSYSCLK×= tsample 2 STC+() tADCCLK×= tdistrib Nt ADCCLK×=

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-105 temperature. The post-calibration phase is enabled by bit 3 of the Mode register. EQ 2-14 describes the post-calibration time. EQ 2-14 MODE[3]: Bit 3 of the Mode register, described in Table 2-41 on page 2-103. The calculation for the conversion time for the ADC is summarized in EQ 2-15. tconv = tsync_read + tsample + tdistrib + tpost-cal + tsync_write EQ 2-15 tconv: conversion time tsync_read: maximum time for a signal to synchronize with SYSCLK. For calculation purposes, the worst case is a period of SYSCLK, tSYSCLK. tsample: Sample time tdistrib: Distribution time tpost-cal: Post-calibration time tsync_write: Maximum time for a signal to synchronize with SYSCLK. For calculation purposes, the worst case is a period of SYSCLK, tSYSCLK. Example This example shows how to choose the correct settings to achieve the fastest sample time in 10-bit mode for a system that runs at 66 MHz. The period of SYSCLK: tSYSCLK = 1/66 MHz = 0.015 µs Choosing TVC between 1 and 33 will meet th e maximum and minimum period for the ADCCLK requirement. A higher TVC leads to a higher ADCCLK period. The minimum TVC is chosen so that t distrib and t post-cal can be run faster. The period of ADCCLK with a TVC of 1 can be computed by EQ . From Table 2-47 on page 2-118, minimum conversion for 10-bit mode is 1.8 µs. To compute STC, the calculation will first compute the post-calibration time, second the distribution time, and finally the STC setting. Since Actel recommends post-calibration for temperature drift over time, post-calibration shall be enabled and the post-calibration time, t post-cal, can be computed by EQ 2-16. The post-calibration time is 0.24 µs. EQ 2-16 The distribution time, tdistrib, is equal to 1.2 µs and can be computed using EQ 2-17. EQ 2-17 The STC value can now be computed through EQ 2-18. The sample time is equal to 0.32 µs. By rearranging EQ 2-12 on page 2-104 with a tsample of 0.35 µs, the STC can be computed. tsample = tconv – tpost-cal – tdistrib – tsync_read – tsync_write EQ 2-18 tpost-cal MODE 3[] 2t ADCCLK×()×= tADCCLK 4 1 TVC+()× tSYSCLK× 41 1 +()× 0.015 µs× 0.12 µs== = tpost-cal 2t ADCCLK× 0.24 µs== tdistrib Nt ADCCLK× 10 0.12× 1.2 µs== = STC tsample tADCCLK

2-106 Preliminary v1.7 And so, STC will be rounded up to 3 to ensure the minimum conversion time is met. The sample time, tsample, with an STC of 3, is now equal to 0.36 µs. The total sample time, using EQ 2-19, can now be summated. EQ 2-19 The optimal setting for the system running at 66 MHz with an ADC for 10-bit mode chosen is listed as follows: *Note that no power-down after every conversion is chosen in this case; however, if the application is power-sensitive, the MODE[2] ca n be set to '0', as described abov e, and it will not affect any performance. Integrated Voltage Reference The Fusion device has an integrated on-chip 2.56 V reference voltage for the ADC. The value of this reference voltage was chosen to make the presca ling and postscaling fa ctors for the prescaler blocks change in a binary fashion. However, if desired, an external reference voltage of up to 3.3 V can be connected between the VAREF and GNDREF pins. The VAREFSEL control pin is used to select the reference voltage. ADC Operation Description The ADC can be powered down independently of the FPGA core, as an additional control or for power-saving considerations, via the PWRDWN pin of the Analog Block. The PWRDWN pin controls only the comparators in the ADC. Once the ADC has powered up and been released from reset, ADCRESET, the ADC will initiate a calibration routine designed to provide optimal ADC performance. The Fusion ADC offers a robust calibration scheme to reduce integrated offset an d linearity errors. The offset and linearity errors of the main capacitor array are compensated for with an 8-bit calibration capacitor array. The offset/linearity error calibration is carried out in two ways. First, a power-up calibration is carried out when the ADC comes ou t of reset. This is initiated by the CALIBRATE output of the Analog Block macro and is a fixed number of ADC_C LK cycles (3,840 cy cles), as shown in Figure 2-81 on page 2-107. In this mode, the linearity and offset errors of the capacitors are calibrated. To further compensate for drift and temperature- dependent effects, every conversion is followed by post-calibration of either the offset or a bi t of the main capacitor array. The post-calibration ensures that, over time and with temperature, the ADC remains consistent. After both calibration and the se tting of the appropriate configur ations, as explained above, the ADC is ready for operation. Setting the ADCSTART signal high for one clock period will initiate the sample and conversion of the analog signal on the channel as configured by CHNUMBER[4:0]. The status signals SAMPLE and BUSY will show wh en the ADC is sampling and converting ( Figure 2-83 on page 2-108). Both SAMPLE and BUSY will initially go high. After the ADC has sampled and held the analog signal, SAMPLE will go low. After the entire operat ion has completed and the analog signal is converted, BUSY will go low and DATAVALID will go high. This indicates that the digital result is available on the RESULT[11:0] pins. Table 2-44  VAREF Bit Function Name Bit Function VAREF 0 Reference voltage selection 0 – Internal voltage reference selected. VAREF pin outputs 2.56 V. 1 – Input external voltage reference from VAREF and GNDREF

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-107 DATAVALID will remain high until a subsequent ADC_START is issued. The DATAVALID goes low on the rising edge of SYSCLK as shown in Figure 2-82 on page 2-108. The RESULT signals will be kept constant until the ADC finishes the subsequent sample. The next sampled RESULT will be available when DATAVALID goes high again. It is ideal to read the RESULT when DATAVALID is '1'. The RESULT is latched and remains unchanged until the next DATAVLAID rising edge. Intra-Conversion Performing a conversion during power-up, calibration is possible but should be avoided, since the performance is not guaranteed, as shown in Table 2-46 on page 2-115. This is described as intra- conversion. Injected Conversion A conversion can be interrupted by another conversion. Before the current conversion is finished, a second conversion can be started by issuing a pulse on signal ADCSTART. When a second conversion is issued before the current conversion is completed, the current conversion would be dropped and the ADC would start the second conv ersion on the rising edge of the SYSCLK. This is known as injected conversion. Since the ADC is synchronous, the minimum time to issue a second conversion is two clock cycles of SYSCLK after the previous one. Timing Diagram Note: *Refer to EQ 2-11 on page 2-104 for the calculation on the period of ADCCLK, tADCCLK. Figure 2-81  Power-Up Calibration Status Signal Timing Diagram SYSCLK ADCRESET CALIBRATE tREMCLR tCK2QCAL tCK2QCAL TVC[7:0] tSUTVC tHDTVC tCAL = 3,840 tADCCLK* tRECCLR

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-109 ADC Interface Timing Table 2-45  ADC Interface Timing Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tSUMODE Mode Pin Setup Time 0.56 0.64 0.75 ns tHDMODE Mode Pin Hold Time 0.26 0.29 0.34 ns tSUTVC Clock Divide Control (TVC) Setup Time 0.68 0.77 0.90 ns tHDTVC Clock Divide Control (TVC) Hold Time 0.32 0.36 0.43 ns tSUSTC Sample Time Control (STC) Setup Time 1.58 1.79 2.11 ns tHDSTC Sample Time Control (STC) Hold Time 1.27 1.45 1.71 ns tSUVAREFSEL Voltage Reference Select (VAREFSEL) Setup Time 0.00 0.00 0.00 ns tHDVAREFSEL Voltage Reference Select (VAREFSEL) Hold Time 0.67 0.76 0.89 ns tSUCHNUM Channel Select (CHNUMBER) Setup Time 0.90 1.03 1.21 ns tHDCHNUM Channel Select (CHNUMBER) Hold Time 0.00 0.00 0.00 ns tSUADCSTART Start of Conversion (ADCSTART) Setup Time 0.75 0.85 1.00 ns tHDADCSTART Start of Conversion (ADCSTART) Hold Time 0.43 0.49 0.57 ns tCK2QBUSY Busy Clock-to-Q 1.33 1.51 1.78 ns tCK2QCAL Power-Up Calibration Clock-to-Q 0.63 0.71 0.84 ns tCK2QVAL Valid Conversion Result Clock-to-Q 3.12 3.55 4.17 ns tCK2QSAMPLE Sample Clock-to-Q 0.22 0.25 0.30 ns tCK2QRESULT Conversion Result Clock-to-Q 2.53 2.89 3.39 ns tCLR2QBUSY Busy Clear-to-Q 2.06 2.35 2.76 ns tCLR2QCAL Power-Up Calibration Clear-to-Q 2.15 2.45 2.88 ns tCLR2QVAL Valid Conversion Result Clear-to-Q 2.41 2.74 3.22 ns tCLR2QSAMPLE Sample Clear-to-Q 2.17 2.48 2.91 ns tCLR2QRESULT Conversion result Clear-to-Q 2.25 2.56 3.01 ns tRECCLR Recovery Time of Clear 0.00 0.00 0.00 ns tREMCLR Removal Time of Clear 0.63 0.72 0.84 ns tMPWSYSCLK Clock Minimum Pulse Width for the ADC 4.00 4.00 4.00 ns tFMAXSYSCLK Clock Maximum Frequency for the ADC 100.00 100.00 100.00 MHz

2-110 Preliminary v1.7 Terminology Conversion Time Conversion time is the interval between the release of the hold state (imposed by the input circuitry of a track-and-hold) and the instant at which the voltage on the sampling capacitor settles to within one LSB of a new input value. DNL – Differential Non-Linearity For an ideal ADC, the analog-input levels that trigger any two successive output codes should differ by one LSB (DNL = 0). Any deviation from one LSB in defined as DNL (Figure 2-84). ENOB – Effective Number of Bits ENOB specifies the dynamic perfo rmance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists only of quantization of noise. As the input frequency increases, the overall noise (particularly in the distortion compon ents) also increases, thereby reducing the ENOB and SINAD (also see “Signa l-to-Noise and Distorti on Ratio (SINAD)”.) ENOB for a full-scale, sinusoidal input waveform is computed using EQ 2-20. EQ 2-20 FS Error – Full-Scale Error Full-scale error is the difference between the actual value that trig gers that transition to full-scale and the ideal analog full-scale transition value. Full-scale error equals offset error plus gain error. Figure 2-84  Differential Non-Linearity (DNL) ADC Output Code Input Voltage to Prescaler Error = –0.5 LSB Error = +1 LSB Ideal Output Actual Output ENOB SINAD 1.76–

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-111 Gain Error The gain error of an ADC indicates how well the sl ope of an actual transf er function matches the slope of the ideal transfer function. Gain error is usually expressed in LSB or as a percent of full- scale (%FSR). Gain error is the full-scale error minus the offset error (Figure 2-85). Gain Error Drift Gain-error drift is the variation in gain error du e to a change in ambien t temperature, typically expressed in ppm/°C. Figure 2-85  Gain Error ADC Output Code Input Voltage to Prescaler Ideal Output Actual Output Gain = 2 LSB 1...11 0...00 FS Voltage

2-112 Preliminary v1.7 INL – Integral Non-Linearity INL is the deviation of an actual transfer function from a straight line. After nullifying offset and gain errors, the straight line is either a best-fit straight line or a line drawn between the end points of the transfer function (Figure 2-86). LSB – Least Significant Bit In a binary number, the LSB is the least weighted bit in the group. Typically, the LSB is the furthest right bit. For an ADC, the weight of an LSB equals the full-scale voltage range of the converter divided by 2 N, where N is the converter’s resolution. Fo r a 10-bit ADC with a unipolar full-scale voltage of 2.56 V, 1 LSB = (2.56 V / 210) = 2.5 mV. No Missing Codes An ADC has no missing codes if it produces all po ssible digital codes in re sponse to a ramp signal applied to the analog input. Offset Error Offset error indicates how well the actual transfer function matches the ideal transfer function at a single point. For an ideal ADC, the first transition occurs at 0.5 LSB above zero. The offset voltage is measured by applying an analog input such that the ADC outputs all zeroes and increases until the first transition occurs (Figure 2-87). Figure 2-86  Integral Non-Linearity (INL) ADC Output Code Input Voltage to Prescaler IN L = +0.5 LSB IN L = +1 LSB Ideal Output Actual Output

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-113 Resolution ADC resolution is the number of bits used to represent an analog input signal. To more accurately replicate the analog signal, resolution needs to be increased. Sampling Rate Sampling rate or sample frequency, specified in samples per second (sps), is the rate at which an ADC acquires (samples) the analog input. SNR – Signal-to-Noise Ratio SNR is the ratio of the amplitude of the desired si gnal to the amplitude of the noise signals at a given point in time. For a waveform perfectly reco nstructed from digital samples, the theoretical maximum SNR ( EQ 2-21) is the ratio of the full-scale an alog input (RMS value) to the RMS quantization error (res idual error). The ideal, theoretical minimum ADC noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): EQ 2-21 SINAD – Signal-to-Noise and Distortion SINAD is the ratio of the rms amplitude to the m ean value of the root-sum-square of the all other spectral components, in cluding harmonics, but excluding DC. SINAD is a good indication of the overall dynamic performance of an ADC because it includes all compon ents which make up noise and distortion. Total Harmonic Distortion THD measures the distortion content of a signal, and is specified in decibels relative to the carrier (dBc). THD is the ratio of the RMS sum of the selected harmonics of th e input signal to the fundamental itself. Only harmonics within the Nyquist limit are included in the measurement. TUE – Total Unadjusted Error Figure 2-87  Offset Error ADC Output Code Input Voltage to Prescaler Ideal Output Offset Error = 1.5 LSB Actual Output 0...00 0...01 SNR dB[MAX] 6.02dB N 1.76dB+×=

2-114 Preliminary v1.7 TUE is a comprehensive specification that includes linearity errors, gain error, and offset error. It is the worst-case deviation from the ideal device performance. TUE is a static specification (Figure 2-88). Figure 2-88  Total Unadjusted Error (TUE) ADC Output Code Input Voltage to Prescaler IDEAL OUTPUT T U E = ±0.5 LSB

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-115 Analog System Characteristics Table 2-46  Analog Channel Specifications All Values at Industrial Operating Conditions (unless noted otherwise) Typical: VCC33A = 3.3 V, VCC = 1.5 V, and TA = 25°C Parameter Description Condition Minimum Typical Maximum Units Voltage Monitor using Analog Pads AV, AC and AT (using prescaler) V INAP Input Voltage Refer to Table 3-2 on page 3-3. Uncalibrated Gain and Offset Errors Refer to Table 2-48 on page 2-120. Calibrated Gain and Offset Errors Refer to Table 2-49 on page 2-121. Bandwidth 100 kHz Input Resistance Refer to Table 3-3 on page 3-4. Scaling Factor Prescaler modes ( Table 2-54 on page 2-128). Sampling Time 10 µs Current Monitor using Analog Pads AV and AC1 (potential on the AV pad must be greater than the AC pad) VRSM 1 Maximum Differential Input VAREF / 10 mV Resolution See Accuracy specification Common Mode Range Refer to Table 3-2 on page 3-3 for maximum voltage limits. –10.5 to +12 V CMRR Common Mode Rejection Ratio DC – 1 kHz 60 dB 1 kHz – 10 kHz 50 dB >10 kHz 30 dB tCMSHI Strobe High time ADC conv. time 200 µs tCMSLO Low time 5 µs tCMSSET Setting time 0.02 µs Accuracy Input differential vo ltage > 50 mV –2 – (0.05 × (AV – AC) to 2 + (0.05 × (AV – AC)) mV Notes: 1. V RSM is the maximum voltage drop across the current sense resistor. 2. Analog inputs used as digital inpu ts can tolerate the same voltage limits as the corresponding analog pad. There is no reliability concern on digital inputs as long as VIND does not exceed these limits. 3. V IND is limited to VCC33A + 0.2 to allow reaching 10 MHz input frequency. 4. Measurement is done by forcing a temperature on an external diode, with the Fusion device at room temperature. 5. The temperature offset is a fixed positive value. 6. The high current mode has a maximum power limit of 20 mW. Appropriate current limit resistors must be used, based on voltage on the pad.

2-116 Preliminary v1.7 Temperature Monitor Using Analog Pad AT External Temperature Monitor4 (using external diode 2N3904) Resolution 8-bit ADC 4 °C 10-bit ADC 1 °C 12-bit ADC 1 °C Offset 5 5º C Accuracy ±3 °C External Sensor Source Current High level 10 µA Low level 100 µA Internal Temperature Monitor Resolution 8-bit ADC 4 °C 10-bit ADC 1 °C 12-bit ADC 1 °C Offset 5 5º C Accuracy ±3 °C tTMSHI Temperature Monitor Strobe High time 10 105 µs tTMSLO Low time 5 µs tTMSSET Setting time 5 µs Analog Input as a Digital Input V IND 2, 3 Input Voltage Refer to Table 3-2 on page 3-3. VHYSDIN Hysteresis 0.3 V VIHDIN Input HIGH 1.2 V VILDIN Input LOW 0.9 V VMPWDIN Minimum Pulse Width 50 ns FDIN Maximum Frequency 10 MHz ISTBDIN Input Leakage Current 2µ A IDYNDIN Dynamic Current 20 µA tINDIN Input Delay 10 ns Table 2-46  Analog Channel Specifications (continued) All Values at Industrial Operating Conditions (unless noted otherwise) Typical: VCC33A = 3.3 V, VCC = 1.5 V, and TA = 25°C Parameter Description Condition Minimum Typical Maximum Units Notes: 1. V RSM is the maximum voltage drop across the current sense resistor. 2. Analog inputs used as digital inpu ts can tolerate the same voltage limits as the corresponding analog pad. There is no reliability concern on digital inputs as long as VIND does not exceed these limits. 3. V IND is limited to VCC33A + 0.2 to allow reaching 10 MHz input frequency. 4. Measurement is done by forcing a temperature on an external diode, with the Fusion device at room temperature. 5. The temperature offset is a fixed positive value. 6. The high current mode has a maximum power limit of 20 mW. Appropriate current limit resistors must be used, based on voltage on the pad.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-117 Gate Driver Output Using Analog Pad AG VG Voltage Range Refer to Table 3-2 on page 3-3. IG Output Current Drive High Current Mode 6 at 1.0 V ±20 mA Low Current Mode – ± 1 µA ±1 µA Low Current Mode – ± 3 µA ±3 µA Low Current Mode – ± 10 µA ±10 µA Low Current Mode – ± 30 µA ±30 µA I OFFG Maximum Off Current 100 nA FG (maximum switching rate) High Current Mode at 1.0 V 1 kΩ resistive load 1.3 MHz Low Current Mode – ±1 µA 3,000 kΩ resistive load 3 kHz Low Current Mode – ±3 µA 1,000 kΩ resistive load 7 kHz Low Current Mode – ±10 µA 300 kΩ resistive load 25 kHz Low Current Mode – ±30 µA 105 kΩ resistive load 78 kHz Table 2-46  Analog Channel Specifications (continued) All Values at Industrial Operating Conditions (unless noted otherwise) Typical: VCC33A = 3.3 V, VCC = 1.5 V, and TA = 25°C Parameter Description Condition Minimum Typical Maximum Units Notes: 1. V RSM is the maximum voltage drop across the current sense resistor. 2. Analog inputs used as digital inpu ts can tolerate the same voltage limits as the corresponding analog pad. There is no reliability concern on digital inputs as long as VIND does not exceed these limits. 3. V IND is limited to VCC33A + 0.2 to allow reaching 10 MHz input frequency. 4. Measurement is done by forcing a temperature on an external diode, with the Fusion device at room temperature. 5. The temperature offset is a fixed positive value. 6. The high current mode has a maximum power limit of 20 mW. Appropriate current limit resistors must be used, based on voltage on the pad.

2-118 Preliminary v1.7 Table 2-47  ADC Characteristics in Direct Input Mode All Values at Industrial Operating Conditions (unless noted otherwise) Typical: VCC33A = 3.3 V, VCC = 1.5 V, and TA = 25°C Parameter Description Condition Minimum Typical Maximum Units All Analog Inputs V INADC Input Voltage (direct to ADC) Refer to Table 3-2 on page 3-3. CINADC Input Capacitance Channel not selected 7 pF Channel selected but not sampling 8p F Channel selected and sampling 18 pF ZINADC Input Impedance 8-bit mode 2 k Ω 10-bit mode 2 k Ω 12-bit mode 2 k Ω VAREF Reference Voltage Internal reference Accuracy at 25°C 2.537 2.56 2.583 V Temperature Drift of Internal Reference 65 ppm/° C External reference 2.527 V CC33A + 0.05 V DC Accuracy (using external reference)1, 2 TUE Total Unadjusted Error 8-bit mode 0.29 LSB 10-bit mode 0.72 LSB 12-bit mode 1.80 LSB INL Integral Non-Linearity 8-bit mode 0.20 0.25 LSB 10-bit mode 0.32 0.43 LSB 12-bit mode 1.71 1.80 LSB DNL Differential Non- Linearity (no missing codes) 8-bit mode 0.20 0.24 LSB 10-bit mode 0.60 0.65 LSB 12-bit mode 2.40 2.48 LSB Offset Error 8-bit mode 0.01 0.17 LSB 10-bit mode 0.05 0.20 LSB 12-bit mode 0.20 0.40 LSB Gain Error 8-bit mode 0.0004 0.003 LSB 10-bit mode 0.002 0.011 LSB 12-bit mode 0.007 0.044 LSB Gain Error (with internal reference) All modes 2.0 %FSR Notes: 1. Accuracy of the external reference is 2.56 V ± 4.6 mV. 2. Data is based on characterization. 3. The sample rate is time-sha red among active analog inputs.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-119 Dynamic Accuracy (using external reference, 100 kHz Sine Wave Input, 2.38 VP-P, 500 ksps, fADCCLK = 10 MHz)1, 2 SNR Signal-to-Noise Ratio 8-bit mode 48.0 49.5 dB 10-bit mode 58.0 60.0 dB 12-bit mode 62.9 64.5 dB SINAD Signal-to-Noise and Distortion 8-bit mode 47.6 49.5 dB 10-bit mode 57.4 59.8 dB 12-bit mode 62.0 64.2 dB THD Total Harmonic Distortion 8-bit mode –74.4 –63.0 dBc 10-bit mode –78.3 –63.0 dBc 12-bit mode –77.9 –64.4 dBc ENOB Effective Number of Bits 8-bit mode 7.6 7.9 bits 10-bit mode 9.2 9.6 bits 12-bit mode 10.0 10.4 bits Conversion Conversion Time 8-bit mode 1.7 µs 10-bit mode 1.8 µs 12-bit mode 2.0 µs Sample Rate 2 8-bit mode 600 ksps 10-bit mode 550 ksps 12-bit mode 500 ksps Table 2-47  ADC Characteristics in Direct Input Mode (continued) All Values at Industrial Operating Conditions (unless noted otherwise) Typical: V CC33A = 3.3 V, VCC = 1.5 V, and TA = 25°C Parameter Description Condition Minimum Typical Maximum Units Notes: 1. Accuracy of the external reference is 2.56 V ± 4.6 mV. 2. Data is based on characterization. 3. The sample rate is time-sha red among active analog inputs.

2-120 Preliminary v1.7 Table 2-48  Uncalibrated Analog Channel Accuracy* Worst-Case Industrial Conditions, TA = 85°C Total Channel Error (LSB) Channel Input Offset Error (LSB) Channel Input Offset Error (mV) Channel Gain Error (%FSR) Analog Pad Prescaler Range (V) Neg. Max. Med. Pos. Max. Neg Max Med. Pos. Max. Neg. Max. Med. Pos. Max. Min. Typ. Max. Positive Range ADC in 10-Bit Mode AV, AC 16 –22 –2 12 –11 –2 14 –169 –32 224 3 0 –3 8 –40 –5 17 –11 –5 21 –87 –40 166 2 0 –4 4 –45 –9 24 –16 –11 36 –63 –43 144 2 0 –4 2 –70 –19 33 –33 –20 66 –66 –39 131 2 0 –4 0.5 –41 –12 8 –12 –7 38 –6 –4 19 3 –1 –3 0.25 –53 –14 19 –20 –14 40 –5 –3 10 5 0 –4 0.125 –89 –29 24 –40 –28 88 –5 –4 11 7 0 –5 AT 16 –3 9 15 –4 0 4 –64 5 64 1 0 –1 4 –10 2 15 –11 –2 11 –44 –8 44 1 0 –1 Negative Range ADC in 10-Bit Mode AV, AC 16 –35 –10 9 –24 –6 9 –383 –96 148 5 –1 –6 8 –65 –19 12 –34 –12 9 –268 –99 75 5 –1 –5 4 –86 –28 21 –64 –24 19 –254 –96 76 5 –1 –6 2 –136 –53 37 –115 –42 39 –230 –83 78 6 –2 –7 1 –98 –35 8 –39 –8 15 –39 –8 15 10 –3 –10 0.5 –121 –46 7 –54 –14 18 –27 –7 9 10 –4 –11 0.25 –149 –49 19 –72 –16 40 –18 –4 10 14 –4 –12 0.125 –188 –67 38 –112 –27 56 –14 –3 7 16 –5 –14 Note: *Channel Accuracy includes prescaler and ADC accuracies. For 12-bit mode, multiply the LSB count by 4. For 8-bit mode, divide the LSB count by 4. Gain remains the same.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-121 Table 2-49  Calibrated Analog Channel Accuracy 1,2,3 Worst-Case Industrial Conditions, TA = 85°C Condition Total Channel Error (LSB) Analog Pad Prescaler Range (V) Input Voltage 4 (V) Negative Max. Me dian Positive Max. Positive Range ADC in 10-Bit Mode AV, AC 16 0.300 to 12.0 –6 1 6 8 0.250 to 8.00 –6 0 6 4 0.200 to 4.00 –7 –1 7 2 0.150 to 2.00 –7 0 7 1 0.050 to 1.00 –6 –1 6 AT 16 0.300 to 16.0 –5 0 5 4 0.100 to 4.00 –7 –1 7 Negative Range ADC in 10-Bit Mode AV, AC 16 –0.400 to –10.5 –7 1 9 8 –0.350 to –8.00 –7 –1 7 4 –0.300 to –4.00 –7 –2 9 2 –0.250 to –2.00 –7 –2 7 1 –0.050 to –1.00 –16 –1 20 Notes: 1. Channel Accuracy includes prescale r and ADC accuracies. For 12-bit mode, multiply the LSB count by 4. For 8-bit mode, divide the LSB count by 4. Overall accuracy remains the same. 2. Requires enabling Analog Calibr ation in the Actel tool flow. 3. Calibrated with two-point calibration methodology, using 20% and 80% full-scale points. 4. The lower limit of the input voltage is determined by the prescaler input offset.

2-122 Preliminary v1.7 Examples Calculating Accuracy for an Uncalibrated Analog Channel Formula For a given prescaler range, Output Voltage = (Channel Output Offset in V) + (Input Voltage x Channel Gain) where Channel Output offset in V = Channel Output offset in LSBs x Equivalent voltage per LSB Channel Gain Factor = 1+ (% Channel Gain / 100) Example Input Voltage = 5 V Chosen Prescaler range = 8 V range Refer to Table 2-48 on page 2-120. Max. Output Voltage = (Max Positive output offset) + (Input Voltage x Max Gain Factor) Max. Positive output offset = (8 LSB) x (8mV per LSB in 10-bit mode) Max. Positive output offset = 64 mV Max. Gain = 1 + (2/100) Max. Gain = 1.02 Max. Output Voltage = (64 mV) + (5 V x 1.02) Max. Output Voltage = 5.164 V Similarly, Table 2-50  Analog Channel Accuracy: Monitoring Standard Positive Voltages Typical Conditions, T A = 25°C Input Voltage (V) Calibrated Typical Error per Positive Prescaler Setting1 (%FSR) Direct ADC2,3 (%FSR)

16 V (AT)

16 V (12 V)

(AV/AC) 8 V (AV/AC) 4 V (AT) 4 V (AV/AC) 2 V (AV/AC) 1 V (AV/AC) VAREF = 2.56 V 15 1 14 1 12 1 1 52 2 1 3.3 2 2 1 1 1 2.5 3 2 1 1 1 1 1.8 4 4 1 1 1 1 1 1.5 5 5 2 2 2 1 1 1.2 7 6 2 2 2 1 1 0.9 9 9 4 3 3 1 1 1 Notes: 1. Requires enabling Analog Calibr ation in the Actel tool flow. 2. Direct ADC mode using an external VAREF of 2.56V±4.6mV, without Analog Calibration macro. 3. For input greater than 2.56 V, th e ADC output will saturate. A hi gher VAREF or prescaler usage is recommended.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-123 Min. Output Voltage = (Min. Negative output offset) + (Input Voltage x Min. Gain) Calculating Accuracy for a Calibrated Analog Channel Formula For a given prescaler range, Output Voltage = Channel TUE in V + Input Voltage where Channel TUE in V = Channel TUE in LSBs x Equivalent voltage per LSB Example Input Voltage = 5 V Chosen Prescaler range = 8 V range Refer to Table 2-49 on page 2-121. Max. Output Voltage = Max. Channel TUE in V + Input Voltage Max. Channel TUE in V = (6 LSB) × (8 mV per LSB in 10-bit mode) = 48 mV Max. Output Voltage = 48 mV + 5 V = 5.048 V Similarly, Min Output Voltage = Min Channel TUE in V + Input Voltage = (-48 mV) + 5 V = 4.952 V Calculating LSBs from a Given Error Budget Formula For a given prescaler range, LSB count = ± (Input Voltage × Required % error) / (Equivalent voltage per LSB) Example Input Voltage = 5 V Required error margin= 1% Refer to Table 2-49 on page 2-121. Equivalent voltage per LSB = 16 mV for a 16V prescaler, with ADC in 10-bit mode LSB Count = ± (5.0 V × 1%) / (0.016) LSB Count = ± 3.125 Equivalent voltage per LSB = 8 mV for an 8 V prescaler, with ADC in 10-bit mode LSB Count = ± (5.0 V × 1%) / (0.008) LSB Count = ± 6.25 The 8 V prescaler satisfies the calculat ed LSB count accuracy requirement (see Table 2-49 on page 2-121).

2-124 Preliminary v1.7 Analog Configuration MUX The ACM is the interface between the FPGA, the Analog Block configurations, and the real-time counter. Actel Libero IDE will generate IP that will load and configure the Analog Block via the ACM. However, users are not limited to using the Libero IDE IP. This section provides a detailed description of the ACM's register map, truth tabl es for proper configuration of the Analog Block and RTC, as well as timing wave forms so users can access and con trol the ACM directly from their designs. The Analog Block contains four 8-bit latches pe r Analog Quad that are initialized through the ACM. These latches act as configuration bits for Analog Quads. The ACM block runs from the core voltage supply (1.5 V). Access to the ACM is achieved via 8-bit addres s and data busses with enables. The pin list is provided in Table 2-36 on page 2-82 . The ACM clock speed is limited to a maximum of 10 MHz, more than sufficient to handle the low-bandwidth requirements of configuring the Analog Block and the RTC (sub-block of the Analog Block). Table 2-51 decodes the ACM address space and maps it to the correspondin g Analog Quad and configuration byte for that quad. Table 2-51  ACM Address Decode Table for Analog Quad ACMADDR [7:0] in Decimal Name Description Associated Peripheral 0 – – Analog Quad

1 AQ0 Byte 0 Analog Quad

2 AQ0 Byte 1 Analog Quad

3 AQ0 Byte 2 Analog Quad

4 AQ0 Byte 3 Analog Quad

5 AQ1 Byte 0 Analog Quad

36 AQ8 Byte 3 Analog Quad

37 AQ9 Byte 0 Analog Quad

38 AQ9 Byte 1 Analog Quad

39 AQ9 Byte 2 Analog Quad

40 AQ9 Byte 3 Analog Quad

41 Undefined Analog Quad

63 Undefined RTC

64 COUNTER0 Counter bits 7:0 RTC

65 COUNTER1 Counter bits 15:8 RTC

66 COUNTER2 Counter bits 23:16 RTC

67 COUNTER3 Counter bits 31:24 RTC

68 COUNTER4 Counter bits 39:32 RTC

72 MATCHREG0 Match register bits 7:0 RTC

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-125 ACM Characteristics1

73 MATCHREG1 Match register bits 15:8 RTC

74 MATCHREG2 Match register bits 23:16 RTC

75 MATCHREG3 Match register bits 31:24 RTC

76 MATCHREG4 Match register bits 39:32 RTC

80 MATCHBITS0 Individual match bits 7:0 RTC

81 MATCHBITS1 Individual match bits 15:8 RTC

82 MATCHBITS2 Individual match bits 23:16 RTC

83 MATCHBITS3 Individual match bits 31:24 RTC

84 MATCHBITS4 Individual match bits 39:32 RTC

88 CTRL_STAT Control (write) / Status (read)

register bits 7:0 RTC

89 TEST_REG Test register(s) RTC

Note: ACMADDR bytes 1 to 40 pertain to the Analog Quads; bytes 64 to 89 pertain to the RTC. 1. When addressing the RTC addresses (i.e., ACMADDR 64 to 89), there is no timing generator, and the rc_osc, byte_en, and aq_wen signals have no impact. Table 2-51  ACM Address Decode Table for Analog Quad (continued) ACMADDR [7:0] in Decimal Name Description Associated Peripheral Figure 2-89  ACM Write Waveform Figure 2-90  ACM Read Waveform tSUEACM tHEACM tSUDACM tHDACM tSUAACM tHAACM ACMCLK ACMWEN ACMWDATA ACMADDRESS A0 A1 RD0 RD1 tMPWCLKACM tCLKQACM ACMCLK ACMADDRESS ACMRDATA

2-126 Preliminary v1.7 Timing Characteristics Table 2-52  Analog Configuration Multiplexer (ACM) Timing Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tCLKQACM Clock-to-Q of the ACM 19.73 22.48 26.42 ns tSUDACM Data Setup time for the ACM 4.39 5.00 5.88 ns tHDACM Data Hold time for the ACM 0.00 0.00 0.00 ns tSUAACM Address Setup time for the ACM 4.73 5.38 6.33 ns tHAACM Address Hold time for the ACM 0.00 0.00 0.00 ns tSUEACM Enable Setup time for the ACM 3.93 4.48 5.27 ns tHEACM Enable Hold time for the ACM 0.00 0.00 0.00 ns tMPWARACM Asynchronous Reset Mini mum Pulse Width for the ACM 10.00 10.00 10.00 ns tREMARACM Asynchronous Reset Removal time for the ACM 12.98 14.79 17.38 ns tRECARACM Asynchronous Reset Recovery time for the ACM 12.98 14.79 17.38 ns tMPWCLKACM Clock Minimum Pulse Width for the ACM 45.00 45.00 45.00 ns tFMAXCLKACM lock Maximum Frequency for the ACM 10.00 10.00 10.00 MHz

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-127 Analog Quad ACM Description Table 2-53 maps out the ACM space associated with configuration of the Analog Quads within the Analog Block. Table 2-53 shows the byte assignment within each quad and the function of each bit within each byte. Subsequent tables will explain each bit setting and how it corresponds to a particular configuration. After 3. 3 V and 1.5 V are applied to Fusion, Analog Quad configuration registers are loaded with defaul t settings until the initializatio n and configuration state machine changes them to user-defined settings. Table 2-53  Analog Quad ACM Byte Assignment Byte Bit Signal (Bx) Fu nction Default Setting Byte 0 (AV)

0 B0[0] Scaling factor control – prescaler Highest voltage range

1 B0[1]

2 B0[2]

3 B0[3] Analog MUX select Prescaler

4 B0[4] Current mo nitor switch Off

5 B0[5] Direct analog input switch Off

6 B0[6] Selects V-pad polarity Positive

7 B0[7] Prescaler op amp mode Power-down

(AC)

0 B1[0] Scaling factor control – prescaler Highest voltage range

1 B1[1]

2 B1[2]

3 B1[3] Analog MUX select Prescaler

4 B1[4]

5 B1[5] Direct analog input switch Off

6 B1[6] Selects C-pad polarity Positive

7 B1[7] Prescaler op amp mode Power-down

(AG)

0 B2[0] Internal chip temperature

1 B2[1] Spare –

2 B2[2] Current drive control Lowest current

3 B2[3]

4 B2[4] Spare –

5 B2[5] Spare –

6 B2[6] Selects G-pad polarity Positive

7 B2[7] Selects low/high drive Low drive

(AT)

0 B3[0] Scaling factor control – prescaler Highest voltage range

1 B3[1]

2 B3[2]

3 B3[3] Analog MUX select Prescaler

4 B3[4]

5 B3[5] Direct analog input switch Off

6 B3[6] – –

7 B3[7] Prescaler op amp mode Power-down

2-128 Preliminary v1.7 Table 2-54 details the settings available to control the prescaler values of the AV, AC, and AT pins. Note that the AT pin has a reduced number of available prescaler values. Table 2-55 details the settings availabl e to control the MUX within each of the AV, AC, and AT circuits. This MUX determi nes whether the signal routed to the ADC is the direct analog input, prescaled signal, or output of either the Current Monitor Block or the Temperature Monitor Block. Table 2-56 details the settings available to control the Direct Analog Input switch for the AV, AC, and AT pins. Table 2-57 details the settings available to control the polarity of the signals coming to the AV, AC, and AT pins. Note that the only valid setting for the AT pin is logic 0 to support positive voltages. Table 2-54  Prescaler Control Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3) Control Lines Bx[2:0] Scaling Factor, Pad to ADC Input LSB for an 8-Bit Conversion2 (mV) LSB for a 10-Bit Conversion2 (mV) LSB for a 12-Bit Conversion2 (mV) Full-Scale Voltage Range Name 000 1 0.15625 64 16 4 16.368 V 16 V 001 0.3125 32 8 2 8.184 V 8 V 010 1 0.625 16 4 1 4.092 V 4 V 011 1.25 8 2 0.5 2.046 V 2 V 100 2.5 4 1 0.25 1.023 V 1 V Notes: 1. These are the only valid ranges for the Temperature Monitor Block Prescaler. 2. LSB voltage equivalences assume VAREF = 2.56 V. Table 2-55  Analog Multiplexer Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3) Control Lines Bx[4] Control Lines Bx[3] ADC Connected To 0 0 Prescaler 0 1 Direct input 1 0 Current amplifier temperature monitor 1 1 Not valid Table 2-56  Direct Analog Input Switch Control Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3) Control Lines Bx[5] Direct Input Switch

0 Off

Table 2-57  Voltage Polarity Control Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3)* Control Lines Bx[6] Input Signal Polarity

0 Positive

1 Negative

Note: *The B3[6] signal for the AT pad should be kept at logic 0 to accept only positive voltages.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-129 Table 2-58 details the settings available to either po wer down or enable the prescaler associated with the analog inputs AV, AC, and AT. Table 2-59 details the settings available to enable the Current Monitor Block associated with the AC pin. Table 2-60 details the settings available to configure the drive strength of the gate drive when not in high-drive mode. Table 2-61 details the settings available to set the pola rity of the gate driver (either p-channel- or n-channel-type devices). Table 2-62 details the settings available to turn on the Gate Driver and set whether high-drive mode is on or off. Table 2-63 details the settings available to turn on and off the chip internal temperature monitor. Table 2-58  Prescaler Op Amp Power-Down Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3) Control Lines Bx[7] Prescaler Op Amp

0 Power-down

1 Operational

Table 2-59  Current Monitor Input Switch Control Truth Table—AV (x = 0) Control Lines B0[4] Current Monitor Input Switch Table 2-60  Low-Drive Gate Driver Current Truth Table (AG) Control Lines B2[3] Control Lines B2[2] Current (µA) 0 0 1 0 1 3 1 0 10 1 1 30 Table 2-61  Gate Driver Polarity Truth Table (AG) Control Lines B2[6] Gate Driver Polarity Table 2-62  Gate Driver Control Truth Table (AG) Control Lines B2[7] G DON Gate Driver 0 0 Off 0 1 Low drive on 1 0 Off 1 1 High drive on Table 2-63  Internal Temperature Monitor Control Truth Table Control Lines B2[0] PDTMB Chip Internal Temperature Monitor

00 O f f

11 O n

2-130 Preliminary v1.7 User I/Os Introduction Fusion devices feature a flexible I/O structure, su pporting a range of mixed voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V) through a bank-selectable voltage. Table 2-65, Table 2-66, Table 2-67, and Table 2-68 on page 2-133 show the voltages and the compatible I/O standards. I/Os provide programmable slew rates, drive strengths, weak pull-up, and weak pull-down circuits. 3.3 V PCI and 3.3 V PCI-X are 5 V–tolerant. See the "5 V Input Tolerance" section on page 2-143 for possible implementations of 5 V tolerance. All I/Os are in a known state during power-up, and any power-up sequence is allowed without current impact. Refer to the "I/O Power-Up and Supply Voltag e Thresholds for Power-On Reset (Commercial and Industrial)" section on page 3-5 for more information. In low power standby or sleep mode (VCC is OFF, VCC33A is ON, VCCI is ON) or when the resource is not used, digital inputs are tristated, digital outputs are tristated, and digital bibufs (input/output) are tristated. I/O Tile The Fusion I/O tile provides a flexible, programmable structure for implementing a large number of I/O standards. In addition, the registers available in the I/O tile in selected I/O banks can be used to support high-performance register inputs and outputs, with register enable if desired ( Figure 2-91 on page 2-131). The registers can also be used to support the JESD-79C DDR standard within the I/O structure (see the "Double Data Rate (DDR) Support" section on page 2-137 for more information). As depicted in Figure 2-92 on page 2-136, all I/O registers share one CLR port. The output register and output enable register share one CLK port. Refer to the "I/O Registers" section on page 2-136 for more information. I/O Banks and I/O Standards Compatibility The digital I/Os are grouped into I/O voltage banks. There are three digital I/O banks on the AFS090 and AFS250 devices and four digital I/O banks on the AFS600 and AFS1500 devices. Figure 2-105 on page 2-158 and Figure 2-106 on page 2-158 show the bank configuration by device. The north side of the I/O in the AFS600 and AFS1500 devices comp rises two banks of Actel Pro I/Os. The Actel Pro I/Os support a wide number of voltage-referenced I/O standards in addition to the multitude of single-ended and differ ential I/O standards common throug hout all Actel digital I/Os. Each I/O voltage bank has dedicated I/O supply and ground voltages (V CCI/GNDQ for input buffers and VCCI/GND for output buffers). Because of these de dicated supplies, only I/Os with compatible standards can be assigned to the same I/O voltage bank. Table 2-66 and Table 2-67 on page 2-132 show the required voltage compatibility values for each of these voltages. For more information about I/O and global assignments to I/O banks, refer to the specific pin table of the device in the "Package Pin Assignments" section on page 4-1 and the "User I/O Naming Convention" section on page 2-157. Each Pro I/O bank is divided into minibanks. Any user I/O in a V REF minibank (a minibank is the region of scope of a VREF pin) can be configured as a VREF pin (Figure 2-91 on page 2-131). Only one VREF pin is needed to control the entire V REF minibank. The location and scope of the V REF minibanks can be determined by the I/O name. For details, see the "User I/O Naming Convention" section on page 2-157. Table 2-67 on page 2-132 shows the I/O standards supporte d by Fusion devices and the corresponding voltage levels. I/O standards are compatible if the following are true:  Their V CCI values are identical.  If both of the standards need a V REF, their VREF values must be identical (Pro I/O only).

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-131 Figure 2-91  Fusion Pro I/O Bank Detail Showing VREF Minibanks (north side of AFS600 and AFS1500) Table 2-64  I/O Standards Supported by Bank Type I/O Bank Single-Ended I/O Standards Differential I/O Standards Voltage-Referenced Hot- Swap Standard I/O LVTTL/LVCMOS 3.3 V, LVCMOS 2.5 V / 1.8 V / 1.5 V, LVCMOS 2.5/5.0 V –– Y e s Advanced I/O LVTTL/LVCMOS 3.3 V, LVCMOS 2.5 V / 1.8 V / 1.5 V, LVCMOS 2.5/5.0 V, 3.3 V PCI / 3.3 V PCI-X LVPECL and LVDS – – Pro I/O LVTTL/LVCMOS 3.3 V, LVCMOS 2.5 V / 1.8 V / 1.5 V, LVCMOS 2.5/5.0 V, 3.3 V PCI / 3.3 V PCI-X LVPECL and LVDS GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Class I and II Yes Bank 1Bank 0 I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O Pad If needed, the VREF for a given minibank can be provided by any I/O within the minibank. CCC CCC CCC Up to five VREF minibanks within an I/O bank VREF signal scope is between 8 and 18 I/Os. Common VREF signal for all I/Os in VREF minibanks VCCI VCC VCCI VCC

2-132 Preliminary v1.7 Table 2-65  I/O Bank Support by Device I/O Bank AFS090 AFS250 AFS600 AFS1500 Standard I/O N N – – Advanced I/O E, W E, W E, W E, W Pro I/O – – N N Analog Quad S S S S Note: E = East side of the device W = West side of the device N = North side of the device S = South side of the device Table 2-66  Fusion V CCI Voltages and Compatible Standards VCCI (typical) Compatible Standards 1.8 V LVCMOS 1.8 1.5 V LVCMOS 1.5, HSTL (Class I),* HSTL (Class II)* Note: *I/O standard supported by Pro I/O banks. Table 2-67  Fusion V REF Voltages and Compatible Standards* VREF (typical) Compatible Standards

1.5 V SSTL3 (Class I and II)

1.25 V SSTL2 (Class I and II)

1.0 V GTL+ 2.5, GTL+ 3.3 0.8 V GTL 2.5, GTL 3.3

0.75 V HSTL (Class I), HSTL (Class II)

Note: *I/O standards supported by Pro I/O banks.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-133 Table 2-68  Fusion Standard and Advanced I/O Features I/O Bank Voltage (typical) Minibank Voltage (typical) LVTTL/LVCMOS 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V

3.3 V PCI / PCI-X

GTL + (3.3 V) GTL + (2.5 V) GTL (3.3 V) GTL (2.5 V) HSTL Class I and II (1.5 V) SSTL2 Class I and II (2.5 V) SSTL3 Class I and II (3.3 V) LVDS (2.5 V ± 5%) LVPECL (3.3 V)

3.3 V –

0.80 V 1.00 V 1.50 V

2.5 V –

0.80 V 1.00 V 1.25 V

1.8 V –

1.5 V –

0.75 V Note: White box: Allowable I/O standard combinations Gray box: Illegal I/O standard combinations

2-134 Preliminary v1.7 Features Supported on Pro I/Os Table 2-69 lists all features supported by transmitter /receiver for single-ended and differential I/Os. Table 2-69  Fusion Pro I/O Features Feature Description Single-ended and voltage- referenced transmitter

features

 Hot insertion in every mode except PC I or 5 V input tolerant (these modes use clamp diodes and do not allow hot insertion)  Activation of hot insertion (disabling the clamp diode) is selectable by I/Os.  Weak pull-up and pull-down  Two slew rates  Skew between output buffer enable/d isable time: 2 ns delay (rising edge) and 0 ns delay (falling edge); see "Selectable Skew between Output Buffer Enable/Disable Time" on page 2-148 for more information  Five drive strengths  5 V–tolerant receiver ( "5 V Input Tolerance" section on page 2-143)  LVTTL/LVCMOS 3.3 V outputs comp atible with 5 V TTL inputs ( "5 V Output Tolerance" section on page 2-146)  High performance ( Table 2-73 on page 2-141) Single-ended receiver features  Schmitt trigger option  ESD protection  Programmable delay: 0 ns if bypassed , 0.625 ns with '000' setting, 6.575 ns with '111' setting, 0.85-ns intermediate delay increments (at 25°C, 1.5 V)  High performance ( Table 2-73 on page 2-141)  Separate ground planes, GND/GNDQ, for input buffers only to avoid output-induced noise in the input circuitry Voltage-referenced differential receiver features  Programmable Delay: 0 ns if bypassed, 0.625 ns with '000' setting, 6.575 ns with '111' setting, 0.85-ns intermediate delay increments (at 25°C, 1.5 V)  High performance ( Table 2-73 on page 2-141)  Separate ground planes, GND/GNDQ, for input buffers only to avoid output-induced noise in the input circuitry CMOS-style LVDS, BLVDS, M-LVDS, or LVPECL transmitter  Two I/Os and external resistors are used to provide a CMOS-style LVDS, BLVDS, M-LVDS, or LVPECL transmitter solution.  Activation of hot insertion (disabling the clamp diode) is selectable by I/Os.  Weak pull-up and pull-down  Fast slew rate LVDS/LVPECL differential receiver features  ESD protection  High performance ( Table 2-73 on page 2-141)  Programmable delay: 0.625 ns with '000' setting, 6.575 ns with '111' setting, 0.85-ns intermediate delay increments (at 25°C, 1.5 V)  Separate input buffer ground and power planes to avoid output-induced noise in the input circuitry

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-135 Table 2-70  Maximum I/O Frequency for Single-Ended, Voltage-Referenced, and Differential I/Os; All I/O Bank Types (maximum drive strength and high slew selected) Specification Performance Up To LVTTL/LVCMOS 3.3 V 200 MHz LVCMOS 2.5 V 250 MHz LVCMOS 1.8 V 200 MHz LVCMOS 1.5 V 130 MHz PCI 200 MHz PCI-X 200 MHz HSTL-I 300 MHz HSTL-II 300 MHz SSTL2-I 300 MHz SSTL2-II 300 MHz SSTL3-I 300 MHz SSTL3-II 300 MHz GTL+ 3.3 V 300 MHz GTL+ 2.5 V 300 MHz GTL 3.3 V 300 MHz GTL 2.5 V 300 MHz LVDS 350 MHz LVPECL 300 MHz

2-136 Preliminary v1.7 I/O Registers Each I/O module contains several input, output, and enable registers. Refer to Figure 2-92 for a simplified representation of the I/O block. The number of input registers is selected by a set of switches (not shown in Figure 2-92) between registers to implement single or differential data transmission to and from the FPGA core. The Designer software sets these switches for the user. A common CLR/PRE signal is employed by all I/O registers when I/O register combining is used. Input register 2 does not have a CLR/PRE pin, as this register is used fo r DDR implementation. The I/O register combining must satisfy some rules. Note: Fusion I/Os have registers to support DDR functionality (see the "Double Data Rate (DDR) Support" section on page 2-137 for more information). Figure 2-92  I/O Block Logical Representation Input Reg E = Enable PinA Y PAD 1 2 OCE ICE ICE Input Reg Input Reg CLR/PRE CLR/PRE CLR/PRE CLR/PRE CLR/PRE Pull-Up/Down Resistor Control Signal Drive Strength and Slew-Rate Control Output Reg Output Reg To FPGA Core From FPGA Core Output Enable Reg OCE I/O / CLR or I/O / PRE / OCE I/O / Q0 I/O / Q1 I/O / ICLK I/O / D0 I/O / D1 / ICE I/O / OCLK I/O / OE

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-137 Double Data Rate (DDR) Support Fusion Pro I/Os support 350 MHz DDR inputs and outputs. In DDR mode, new data is present on every transition of the clock signal. Clock and data lines have identical bandwidths and signal integrity requirements, making it very efficient for implementing very high-speed systems. DDR interfaces can be implemented using HSTL, SSTL, LVDS, and LVPECL I/O standards. In addition, high-speed DDR interfaces can be implemented using LVDS I/O. Input Support for DDR The basic structure to support a DDR input is shown in Figure 2-93. Three input registers are used to capture incoming data, which is presented to the core on each rising edge of the I/O register clock. Each I/O tile on Fusion devices supports DDR inputs. Output Support for DDR The basic DDR output structure is shown in Figure 2-94 on page 2-138 . New data is presented to the output every half clock cycl e. Note: DDR macros and I/O regi sters do not require additional routing. The combiner automatically recognizes the DDR macro and pushes its registers to the I/O register area at the edge of the chip. The routing delay from the I/O registe rs to the I/O buffers is already taken into account in the DDR macro. Refer to the Actel application note Using DDR for Fusion Devices for more information. Figure 2-93  DDR Input Register Support in Fusion Devices Input DDR Data CLK CLKBUF INBUF Out_QF (to core) FF2 FF1 INBUF CLR DDR_IN E A B C D Out_QR (to core)

2-138 Preliminary v1.7 Figure 2-94  DDR Output Support in Fusion Devices Data_F (from core) CLK CLKBUF Out FF2 INBUF CLR DDR_OUT FF1 A B D EC C B OUTBUF Data_R (from core)

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-139 Hot-Swap Support Hot-swapping (also called hot plugging) is the operation of hot insertion or hot removal of a card in (or from) a powered- up system. The levels of hot-swap support and examples of related applications are described in Table 2-71. The I/Os also need to be configured in hot insertion mode if hot plugging compliance is required. Table 2-71  Levels of Hot-Swap Support Hot Swapping Level Description Power Applied to Device Bus State Card Ground Connection Device Circuitry Connected to Bus Pins Example of Application with Cards that Contain Fusion Devices Compliance of Fusion Devices

1 Cold-swap No – – – System and card

are powered down, then card gets plugged into system, then power supplies are turned on for system but not for FPGA on card. Compliant I/Os can but do not have to be set to hot insertion mode.

2 Hot-swap

before, during, and after insertion/ removal – In PCI hot plug specification, reset control circuitry isolates the card busses until the card supplies are at their nominal operating levels and stable. Compliant I/Os can but do not have to be set to hot insertion mode.

3 Hot-swap

(no ongoing I/O processes during insertion/re moval) Same as Level Must remain glitch-free during power-up or power- down Board bus shared with card bus is "frozen," and there is no toggling activity on bus. It is critical that the logic states set on the bus signal do not get disturbed during card insertion/removal. Compliant with cards with two levels of staging. I/Os have to be set to hot insertion mode.

4 Hot-swap

ongoing, but device being inserted or removed must be idle. Same as Level Same as Level 3 There is activity on the system bus, and it is critical that the logic states set on the bus signal do not get disturbed during card insertion/removal. Compliant with cards with two levels of staging. I/Os have to be set to hot insertion mode.

2-140 Preliminary v1.7 For Fusion devices requiring Level 3 and/or Le vel 4 compliance, the board drivers connected to Fusion I/Os need to have 10 k Ω (or lower) output drive resistance at hot insertion, and 1 k Ω (or lower) output drive resistance at hot removal. This is the resistance of the transmitter sending a signal to the Fusion I/O, and no additional resistance is need ed on the board. If that cannot be assured, three levels of staging can be used to meet Level 3 and/or Level 4 compliance. Cards with two levels of staging should have the following sequence: 1. Grounds 2. Powers, I/Os, other pins Cold-Sparing Support Cold-sparing means that a subsystem with no power applied (usually a circuit board) is electrically connected to the system that is in operation. Th is means that all input buffers of the subsystem must present very high input impedance with no power applied so as not to disturb the operating portion of the system. Pro I/O banks and standard I/O banks fully support cold-sparing. For Pro I/O banks, standards such as PCI that require I/O clamp diodes, can also achieve cold-sparing compliance, since clamp diodes get disconnected internally when the supplies are at 0 V. For Advanced I/O banks, since the I/O clamp diode is always active , cold-sparing can be accomplished either by employing a bus switch to isolate the device I/Os from the rest of the system or by driving each advanced I/O pin to 0 V. If Standard I/O banks are used in applications requiring cold-sparing, a discharge path from the power supply to ground should be provided. This can be done with a discharge resistor or a switched resistor. This is necessary because the standard I/O buffers do not have built-in I/O clamp diodes. If a resistor is chosen, the resistor value must be calculated based on decoupling capacitance on a given power supply on the board (this decoupling capacitor is in parallel with the resistor). The RC time constant should ensure full discharge of supplies before cold-sparing functionality is required. The resistor is necessary to ensure that the power pins are discharged to ground every time there is an interruption of power to the device. I/O cold-sparing may add additional current if the pin is configured with either a pull-up or pull down resistor and driven in the opposite direction. A small static current is induced on each IO pin when the pin is driven to a voltage opposite to the weak pull resistor. The current is equal to the voltage drop across the input pin divided by the pull resistor. Please refer to Table 2-92 on page 2-169, Table 2-93 on page 2-169 , and Table 2-94 on page 2-171 for the specific pull resistor value for the corresponding I/O standard. For example, assuming an LVTTL 3.3 V input pin is configured with a weak Pull-up resistor, a current will flow through the pull-up resisto r if the input pin is driven lo w. For an LVTTL 3.3 V, pull-up resistor is ~45 kΩ and the resulting current is equal to 3.3 V / 45 k Ω = 73 µA for the I/O pin. This is true also when a weak pull-down is chosen and the input pin is driven high. Avoiding this current can be done by driving the input low when a weak pull-down resistor is used, and driving it high when a weak pull-up resistor is used. In Active and Static modes, this current draw can occur in the following cases:  Input buffers with pull-up, driven low  Input buffers with pull-down, driven high  Bidirectional buffers with pull-up, driven low  Bidirectional buffers with pull-down, driven high  Output buffers with pull-up, driven low  Output buffers with pull-down, driven high  Tristate buffers with pull-up, driven low  Tristate buffers with pull-down, driven high

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-141 Electrostatic Discharge (ESD) Protection Fusion devices are tested per JEDEC Standard JESD22-A114-B. Fusion devices contain clamp diodes at every I/O, global, and power pad. Clamp diodes protect all device pads against damage from ESD as well as from excessive voltage transients. Each I/O has two clamp diodes. One diode has its positive (P) side connected to the pad and its negative (N) side connected to VCCI. The second diode has its P side connected to GND and its N side connected to the pad. During oper ation, these diodes are normally biased in the Off state, except when transient voltage is significantly above VCCI or below GND levels. By selecting the appropriate I/O configuration, the diode is turned on or off. Refer to Table 2-72 on page 2-141 and Table 2-73 on page 2-141 for more information about I/O standards and the clamp diode. The second diode is always connected to the pad, regardless of the I/O configuration selected. Table 2-72  Fusion Standard and Advanced I/O – Hot-Swap and 5 V Input Tolerance Capabilities I/O Assignment Clamp Diode Hot Insertion 5 V Input Tolerance 1 Input Buffer Output Buffer Standard I/O Advanced I/O Standard I/O Advanced I/O Standard I/O Advanced I/O

3.3 V LVTTL/LVCMOS No Yes Yes No Yes 1 Yes1 Enabled/Disabled

3.3 V PCI, 3.3 V PCI-X N/A Yes N/A No N/A Yes 1 Enabled/Disabled LVCMOS 2.5 V No Yes Yes No Yes 1 Yes2 Enabled/Disabled LVCMOS 2.5 V / 5.0 V No Yes Yes No Yes 1 Yes2 Enabled/Disabled LVCMOS 1.8 V No Yes Yes No No No Enabled/Disabled LVCMOS 1.5 V No Yes Yes No No No Enabled/Disabled Differential, LVDS/BLVDS/M-LVDS/ LVPECL N/A Yes N/A No N/A No Enabled/Disabled Notes: 1. Can be implemented with an external IDT bus sw itch, resistor divider, or Zener with resistor. 2. Can be implemented with an external resistor and an internal clamp diode. 3. Bidirectional LVPECL buffers are not supported. I/Os can be configured as either input buffers or output buffers. Table 2-73  Fusion Pro I/O – Hot-Swap and 5 V Input Tolerance Capabilities I/O Assignment Clamp Diode Hot Insertion

5 V Input

Tolerance Input Buffer Output Buffer

3.3 V LVTTL/LVCMOS No Yes Yes 1 Enabled/Disabled

3.3 V PCI, 3.3 V PCI-X Yes No Yes 1 Enabled/Disabled LVCMOS 2.5 V 3 No Yes No Enabled/Disabled LVCMOS 2.5 V / 5.0 V 3 Yes No Yes 2 Enabled/Disabled LVCMOS 1.8 V No Yes No Enabled/Disabled LVCMOS 1.5 V No Yes No Enabled/Disabled Voltage-Referenced Input Buffer No Yes No Enabled/Disabled

2-142 Preliminary v1.7 Differential, LVDS/BLVDS/M-LVDS/LVPECL4 No Yes No Enabled/Disabled Notes: 1. Can be implemented with an external IDT bus sw itch, resistor divider, or Zener with resistor. 2. Can be implemented with an external resistor and an internal clamp diode. 3. In the SmartGen, FlashROM, Flash Memory System Builder, and Analog System Builder User's Guide , select the LVCMOS5 macro for the LVCMOS 2.5 V / 5.0 V I/O standard or the LVCMOS25 macro for the LVCMOS 2.5 V I/O standard. 4. Bidirectional LVPECL buffers are not supported. I/Os can be configured as either input buffers or output buffers. Table 2-73  Fusion Pro I/O – Hot-Swap and 5 V Input Tolerance Capabilities I/O Assignment Clamp Diode Hot Insertion Tolerance Input Buffer Output Buffer

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-143

5 V Input Tolerance

I/Os can support 5 V input tolerance when LVTTL 3.3 V, LVCMOS 3.3 V, LVCMOS 2.5 V / 5 V, and LVCMOS 2.5 V configurations are used (see Table 2-74 on page 2-146 for more details). There are four recommended solutions (see Figure 2-95 to Figure 2-98 on page 2-146 for details of board and macro setups) to achieve 5 V receiver tolerance. All the solutions meet a common requirement of limiting the voltage at the input to 3.6 V or less. In fact, the I/O absolute maximum voltage rating is 3.6 V, and any voltage above 3.6 V may cause long-term gate oxide failures. Solution 1 The board-level design needs to ensure that the reflected waveform at the pad does not exceed the limits provided in Table 3-4 on page 3-4. This is a long-term reliability requirement. This scheme will also work for a 3.3 V PCI / PCI-X configuration, bu t the internal diode should not be used for clamping, and the vo ltage must be limited by the two external resistors, as explained below. Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V. The following are some examples of possible re sistor values (based on a simplified simulation model with no line effects and 10 Ω transmitter output resistance, where Rtx_out_high = (V CCI – VOH)/I OH, Rtx_out_low = VOL /I OL). Example 1 (high speed, high current): Rtx_out_high = Rtx_out_low = 10 Ω Imax_tx = 5.5 V / (82 * 0.95 + 36 * 0.95 + 10) = 45.04 mA t RISE =t FALL = 0.85 ns at C_pad_load = 10 pF (includes up to 25% safety margin) tRISE =t FALL = 4 ns at C_pad_load = 50 pF (includes up to 25% safety margin) Example 2 (low–medium speed, medium current): Rtx_out_high = Rtx_out_low = 10 Ω Imax_tx = 5.5 V / (220 * 0.95 + 390 * 0.95 + 10) = 9.17 mA tRISE =t FALL = 4 ns at C_pad_load = 10 pF (includes up to 25% safety margin) tRISE =t FALL = 20 ns at C_pad_load = 50 pF (includes up to 25% safety margin) Other values of resistors are also allowed as long as the resistors are sized appropriately to limit the voltage at the receiving end to 2.5 V < Vin(rx) < 3 .6 V when the transmitter sends a logic 1. This range of Vin_dc(rx) must be assured for an y combination of transmitter supply (5 V ± 0.5 V), transmitter output resistance, and board resistor tolerances.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-145 Solution 3 The board-level design must ensure that the reflected waveform at the pad does not exceed limits provided in Table 3-4 on page 3-4. This is a long-term reliability requirement. This scheme will also work for a 3.3 V PCI/PCIX configuration, but the internal diode should not be used for clamping, and the voltage must be limited by the bus switch, as shown in Figure 2-97. Relying on the diode clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V. Figure 2-97  Solution 3 Solution 3 Requires a bus switch on the board, LVTTL/LVCMOS 3.3 V I/Os. Fusion I/O Input 3.3 V 5.5 V 5.5 V Bus Switch IDTQS32X23 On-ChipOff-Chip

2-146 Preliminary v1.7 Solution 4

5 V Output Tolerance

Fusion I/Os must be set to 3.3 V LVTTL or 3.3 V LVCMOS mode to reliably drive 5 V TTL receivers. It is also critical that there be NO external I/O pull-up resistor to 5 V, since this resistor would pull the I/O pad voltage beyond the 3.6 V absolute maximum value and consequently cause damage to the I/O. When set to 3.3 V LVTTL or 3.3 V LVCMOS mode, Fusion I/Os can directly drive signals into 5 V TTL Figure 2-98  Solution 4 Solution 4

2.5 V On-Chip

Requires one board resistor. Available for LVCMOS 2.5 V / 5.0 V. On-ChipOff-Chip 5.5 V 2.5 V Fusion I/O Input Rext1 Table 2-74  Comparison Table for 5 V–Compliant Receiver Scheme Scheme Board Components Speed Current Limitations

1 Two resistors Low to high 1 Limited by transmitter's drive strength

2 Resistor and Zener 3.3 V Medium Limit ed by transmitter's drive strength 3B u s s w i t c h H i g h N / A

4 Minimum resistor value

R = 47 Ω at TJ = 70°C R = 150 Ω at TJ = 85°C R = 420 Ω at TJ = 100°C Medium Maximum diode current at 100% duty cycle, signal constantly at '1' 52.7 mA at TJ =70°C / 10-year lifetime 16.5 mA at TJ = 85°C / 10-year lifetime 5.9 mA at TJ = 100°C / 10-year lifetime For duty cycles other than 100%, the currents can be increased by a factor = 1 / (duty cycle). Example: 20% duty cycle at 70°C Maximum current = (1 / 0.2) * 52.7 mA = 5 * 52.7 mA = 263.5 mA Notes: 1. Speed and current consumption increase as the board resistance values decrease. 2. Resistor values ensure I/O diode long-term reliability.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-147 the VIL =0 . 8V a n d VIH = 2 V level requirements of 5 V TTL receivers. Therefore, level '1' and level '0' will be recognized correctly by 5 V TTL receivers. Simultaneously Switching Outputs and PCB Layout  Simultaneously switching outpu ts (SSOs) can produce signal integrity problems on adjacent signals that are not part of the SSO bus. Both inductive and capacitive coupling parasitics of bond wires inside packages and of traces on PCBs will transfer noise from SSO busses onto signals adjacent to those busses. Additionally, SSOs can produce ground bounce noise and V CCI dip noise. These two noise types are caused by rapidly changing currents through GND and VCCI package pin inductances during switching activities:  Ground bounce noise vo ltage = L(GND) * di/dt V CCI dip noise voltage = L(VCCI) * di/dt Any group of four or more input pins switching on the same clock edge is considered an SSO bus. The shielding should be done both on the board and inside the package unless otherwise described. In-package shielding can be achieved in several ways; the required shielding will vary depending on whether pins next to SSO bus are LVTTL/LVCMOS inputs, LVTTL/LVCMOS outputs, or GTL/SSTL/HSTL/LVDS/LVPECL inputs and outputs. Board traces in the vicinity of the SSO bus have to be adequately shielded from mutu al coupling and inductive noise that can be generated by the SSO bus. Also, noise generated by the SSO bus needs to be reduced inside the package. PCBs perform an important function in feeding sta ble supply voltages to the IC and, at the same time, maintaining signal integrity between devices. Key issues that need to considered are as follows:  Power and ground plane design and decoupling network design  Transmission line reflections and terminations

2-150 Preliminary v1.7 Weak Pull-Up and Weak Pull-Down Resistors Fusion devices support optional weak pull-up and pull-down resistors for each I/O pin. When the I/O is pulled up, it is connected to the VCCI of its corresponding I/O bank. When it is pulled down, it is connected to GND. Refer to Table 2-94 on page 2-171 for more information. Slew Rate Control and Drive Strength Fusion devices support output sl ew rate control: high and low. The high slew rate option is recommended to minimize the propagation delay. This high-speed option may introduce noise into the system if appropriate signal integrity measur es are not adopted. Selecting a low slew rate reduces this kind of noise but adds some delays in the system. Low slew rate is recommended when bus transients are expected. Drive strength shou ld also be selected according to the design requirements and noise immunity of the system. The output slew rate and multiple drive strength controls are available in LVTTL/LVCMOS 3.3 V, standards have a high output slew rate by default. For Fusion slew rate and drive strength specifications, refer to the appropriate I/O bank table:  Fusion Standard I/O ( Table 2-75 on page 2-151)  Fusion Advanced I/O ( Table 2-76 on page 2-151)  Fusion Pro I/O ( Table 2-77 on page 2-151) Table 2-79 on page 2-153 lists the default values for the above selectable I/O attributes as well as those that are preset for each I/O standard. Figure 2-104  Timing Diagram (with skew circuit selected) EN (b1) EN (b2) Transmitter 1: ON ENABLE (t2) Transmitter 2: ON Transmitter 2: OFF ENABLE (t1) Result: No Bus Contention Transmitter 1: OFF Transmitter 1: OFF

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-151 Refer to Table 2-75, Table 2-76, and Table 2-77 on page 2-151 for SLEW and OUT_DRIVE settings. Table 2-78 on page 2-152 lists the I/O default attributes. Table 2-79 on page 2-153 lists the voltages for the supported I/O standards. Table 2-75  Fusion Standard I/O Standards—OUT_DRIVE Settings I/O Standards OUT_DRIVE (mA) 2 4 6 8 Slew LVTTL/LVCMOS 3.3 V ✓✓✓✓ High Low LVCMOS 2.5 V ✓✓✓✓ High Low LVCMOS 1.8 V ✓✓ – – High Low LVCMOS 1.5 V – – – – High Low Table 2-76  Fusion Advanced I/O Standards— SLEW and OUT_DRIVE Settings I/O Standards OUT_DRIVE (mA) 2 4 6 8 12 16 Slew LVTTL/LVCMOS 3.3 V ✓✓✓✓✓✓ High Low LVCMOS 1.8 V ✓✓✓✓ – – High Low LVCMOS 1.5 V ✓✓ – – – – High Low Table 2-77  Fusion Pro I/O Standards—SLEW and OUT_DRIVE Settings I/O Standards OUT_DRIVE (mA) Slew2 4 6 8 12 16 24 LVTTL/LVCMOS 3.3 V ✓✓✓✓ ✓ ✓ ✓ High Low LVCMOS 2.5 V/5.0 V ✓✓✓✓ ✓ ✓ ✓ High Low LVCMOS 1.8 V ✓✓✓✓ ✓ ✓ –H i g h L o w

2-152 Preliminary v1.7 Table 2-78  Fusion Pro I/O Default Attributes I/O Standards SLEW (output only) OUT_DRIVE (output only) SKEW (tribuf and bibuf only) RES_PULL OUT_LOAD (output only) COMBINE_REGISTER IN_DELAY (input only) IN_DELAY_VAL (input only) SCHMITT_TRIGGER (input only) LVTTL/LVCMOS 3.3 V Refer to the following tables for more information: Table 2-75 on page 2-151 Table 2-76 on page 2-151 Table 2-77 on page 2-151 Refer to the following tables for more information: Table 2-75 on page 2-151 Table 2-76 on page 2-151 Table 2-77 on page 2-151 Off None 35 pF – Off 0 Off LVCMOS 2.5 V Off None 35 pF – Off 0 Off LVCMOS 2.5/5.0 V Off None 35 pF – Off 0 Off LVCMOS 1.8 V Off None 35 pF – Off 0 Off LVCMOS 1.5 V Off None 35 pF – Off 0 Off PCI (3.3 V) Off None 10 pF – Off 0 Off PCI-X (3.3 V) Off None 10 pF – Off 0 Off GTL+ (3.3 V) Off None 10 pF – Off 0 Off GTL+ (2.5 V) Off None 10 pF – Off 0 Off GTL (3.3 V) Off None 10 pF – Off 0 Off GTL (2.5 V) Off None 10 pF – Off 0 Off HSTL Class I Off None 20 pF – Off 0 Off HSTL Class II Off None 20 pF – Off 0 Off SSTL2 Class I and II Off None 30 pF – Off 0 Off SSTL3 Class I and II Off None 30 pF – Off 0 Off LVDS, BLVDS, M-LVDS Off None 0 pF – Off 0 Off LVPECL Off None 0 pF – Off 0 Off

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-153 Table 2-79  Fusion Pro I/O Supported Standards and Corresponding VREF and VTT Voltages I/O Standard Input/Output Supply Voltage (VCCI_TYP) Input Reference Voltage (VREF_TYP) Board Termination Voltage (VTT_TYP) LVTTL/LVCMOS 3.3 V 3.30 V – – LVCMOS 2.5 V 2.50 V – – LVCMOS 2.5 V / 5.0 V Input

2.50 V – –

LVCMOS 1.8 V 1.80 V – – LVCMOS 1.5 V 1.50 V – – PCI 3.3 V 3.30 V – – PCI-X 3.3 V 3.30 V – – GTL+ 3.3 V 3.30 V 1.00 V 1.50 V GTL+ 2.5 V 2.50 V 1.00 V 1.50 V GTL 3.3 V 3.30 V 0.80 V 1.20 V GTL 2.5 V 2.50 V 0.80 V 1.20 V HSTL Class I 1.50 V 0.75 V 0.75 V HSTL Class II 1.50 V 0.75 V 0.75 V SSTL3 Class I 3.30 V 1.50 V 1.50 V SSTL3 Class II 3.30 V 1.50 V 1.50 V SSTL2 Class I 2.50 V 1.25 V 1.25 V SSTL2 Class II 2.50 V 1.25 V 1.25 V LVDS, BLVDS, M-LVDS 2.50 V – – LVPECL 3.30 V – –

2-154 Preliminary v1.7 I/O Software Support In the Fusion development softw are, default settings have be en defined for the various I/O standards supported. Changes can be made to th e default settings via the use of attributes; however, not all I/O attributes are applicable for all I/O standards. Table 2-80 and Table 2-81 list the valid I/O attributes that can be manipulated by the user for each I/O standard. Single-ended I/O standards in Fusion support up to five different drive strengths. Table 2-80  Fusion Standard and Advanced I/O Attributes vs. I/O Standard Applications I/O Standards SLEW (output only) OUT_DRIVE (output only) SKEW (all macros with OE)* RES_PULL OUT_LOAD (output only) COMBINE_REGISTER PCI (3.3 V) ✓✓ ✓ PCI-X (3.3 V) ✓✓✓ ✓ LVDS, BLVDS, M-LVDS ✓✓ LVPECL ✓ Note: *This does not apply to the north I/O bank on AFS090 and AFS250 devices. Table 2-81  Fusion Pro I/O Attributes vs. I/O Standard Applications I/O Standards SLEW (output only) OUT_DRIVE (output only) SKEW (all macros with OE) RES_PULL OUT_LOAD (output only) COMBINE_REGISTER IN_DELAY (input only) IN_DELAY_VAL (input only) SCHMITT_TRIGGER (input only) HOT_SWAPPABLE

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-155 Table 2-82 lists the default values for the above selectab le I/O attributes as we ll as those that are preset for each I/O standard. See Table 2-75, Table 2-76, and Table 2-77 on page 2-151 for SLEW and OUT_DRIVE settings. SSTL2 Class I and II ✓✓ ✓ ✓ ✓✓ SSTL3 Class I and II ✓✓ ✓ ✓ ✓✓ LVDS, BLVDS, M-LVDS ✓✓ ✓ ✓ ✓ LVPECL ✓✓✓ ✓ Table 2-81  Fusion Pro I/O Attributes vs. I/O Standard Applications (continued) I/O Standards SLEW (output only) OUT_DRIVE (output only) SKEW (all macros with OE) RES_PULL OUT_LOAD (output only) COMBINE_REGISTER IN_DELAY (input only) IN_DELAY_VAL (input only) SCHMITT_TRIGGER (input only) HOT_SWAPPABLE

2-156 Preliminary v1.7 Table 2-82  I/O Default Attributes I/O Standards SLEW (output on ly) OUT_DRIVE (output only) SKEW (tribuf and bibuf only) RES_PULL OUT_LOAD (output only) COMBINE_REGISTER LVTTL/LVCMOS 3.3 V Refer to the following tables for more information: Table 2-75 on page 2-151 Table 2-76 on page 2-151 Table 2-77 on page 2-151 Refer to the following tables for more information: Table 2-75 on page 2-151 Table 2-76 on page 2-151 Table 2-77 on page 2-151 Off None 35 pF – LVCMOS 2.5 V Off None 35 pF – LVCMOS 2.5/5.0 V Off None 35 pF – LVCMOS 1.8 V Off None 35 pF – LVCMOS 1.5 V Off None 35 pF – PCI (3.3 V) Off None 10 pF – PCI-X (3.3 V) Off None 10 pF – LVDS, BLVDS, M-LVDS Off None – – LVPECL Off None – –

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-157 User I/O Naming Convention Due to the comprehensive and flexible nature of Fu sion device user I/Os, a naming scheme is used to show the details of the I/O ( Figure 2-105 on page 2-158 and Figure 2-106 on page 2-158 ). The name identifies to which I/O bank it belongs, as well as the pairing and pin polarity for differential I/Os. I/O Nomenclature = Gmn/IOuxwByVz Gmn is only used for I/Os that also have CCC access—i.e., global pins. G= G l o b a l m = Global pin location associated with each CCC on th e device: A (northwest corner), B (northeast corner), C (east middle), D (southeast corner), E (southwest corner), and F (west middle). n = Global input MUX and pin number of the associated Gl obal location m, either A0, A1, A2, B0, B1, B2, C0, C1, or C2. Figure 2-22 on page 2-28 shows the three input pins per clock source MUX at CCC location m. u = I/O pair number in the bank, starting at 00 from the northwest I/O bank and proceeding in a clockwise direction. x = P (Positive) or N (Negative) for di fferential pairs, or R (Regular – single-ended) for the I/Os that support single-ended and voltage-referenced I/O standards only. U (Positive-LVDS only) or V (Negative-LVDS only) restrict the I/O differential pair from being selected as an LVPECL pair. w = D (Differential Pair), P (Pair), or S (Single-Ended). D (Differential Pair) if both members of the pair are bonded out to adjacent pins or are separated only by one GND or NC pin; P (Pair) if both members of the pair are bonded out but do not meet the adjacency requirement; or S (Single-Ended) if the I/O pair is not bonded out. For Differential (D) pairs, adjacency for ball grid packages means only vertical or horizontal. Diagonal adjacency does not meet the requirements for a true differential pair. B = Bank y = Bank number (0–3). The Bank number starts at 0 from the northwest I/O bank and proceeds in a clockwise direction. V = Reference voltage z = Minibank number

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-159 User I/O Characteristics Timing Model Figure 2-107  Timing Model Operating Conditions: –2 Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case VCC = 1.425 V DQ Y Y DQDQ DQY Combinational Cell Combinational Cell Combinational Cell Register Cell Register Cell I/O Module (Non-Registered) LVPECL (Pro IO banks) LVPECL (Pro IO Banks) LVDS, BLVDS, M-LVDS (Pro IO Banks) GTL+ 3.3 V Y Combinational Cell Y Combinational Cell Y Combinational Cell LVTTL/LVCMOS 3.3 V (Pro I/O banks) Output drive strength = 24 mA High slew rate LVCMOS 1.5 V (Pro IO banks) Output drive strength = 12 mA High slew LVTTL/LVCMOS 3.3 V (Pro I/O banks) Output drive strength = 12 mA High slew rate IInput LVTTL/LVCMOS

3.3 V (Pro IO banks)

(Non-Registered) I/O Module (Non-Registered) I/O Module (Non-Registered) I/O Module (Registered) I/O Module (Registered) I/O Module (Non-Registered) t PD = 0.56 ns tPD = 0.49 ns tDp = 1.60 ns tPD = 0.87 ns tDP = 2.74 ns tPD = 0.51 ns tPD = 0.47 ns tPD = 0.47 ns tOCLKQ = 0.59 ns tOSUD = 0.31 ns tPY = 0.90 ns tDP = 1.53 ns tDP = 3.30 ns tDP = 2.39 ns tCLKQ = 0.55 ns tSUD = 0.43 ns tPY = 0.90 ns tCLKQ = 0.55 ns tSUD = 0.43 ns tPY = 1.36 ns tPY = 0.90 ns tPY = 1.22 ns tICLKQ = 0.24 ns tISUD = 0.26 ns

2-160 Preliminary v1.7 Figure 2-108  Input Buffer Timing Model and Delays (example) tPY = MAX(tPY (R), tPY (F)) tPYs = MAX(tPYS (R), tPYS (F)) tDIN = MAX(tDIN (R), tDIN (F)) tPY (R) PAD Y Vtrip GND tPY (F) Vtrip 50%50% VIH VCC VIL tPYS (R) tPYS (F) tDOUT (R) DIN GND tDOUT (F) 50%50% VCC PAD Y tPY tPYS D CLK Q I/O interface DIN tDIN To Array

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-161 Figure 2-109  Output Buffer Model and Delays (example) tDP (R) PAD VOL tDP (F) VtripVtrip VOH VCC D 50% 50% VCC 0 V DOUT 50% 50% 0 V tDOUT (R) tDOUT (F) From Array PAD tDP Std Load D CLK Q I/O Interface DOUT D tDOUT tDP = MAX(tDP(R), tDP(F)) tDOUT = MAX(tDOUT(R), tDOUT(F))

2-162 Preliminary v1.7 Figure 2-110  Tristate Output Buffer Timing Model and Delays (example) D CLK Q D CLK Q 10% VCCI tZL Vtrip 50% tHZ 90% VCCI tZH Vtrip 50% 50% tLZ 50% EOUT PAD D E 50% tEOUT (R) 50% tEOUT (F) PADDOUT EOUT D I/O Interface E tEOUT tZLS Vtrip 50% tZHS Vtrip 50%EOUT PAD D E 50% 50%tEOUT (R) tEOUT (F) 50% VCC VCC VCC VCCI VCC V VCC VOH VOL VOL CC tZL, tZH, tHZ, tLZ, tZLS, tZHS tEOUT = MAX(tEOUT (R). tEOUT (F))

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-163 Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-83  Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions Applicable to Pro I/Os I/O Standard Drive Strength Slew Rate VIL VIH VOL VOH IOL IOH

3.3 V LVTTL /

3.3 V LVCMOS

3.3 V PCI Per PCI Specification

3.3 V PCI-X Per PCI-X Specification

3.3 V GTL 25 mA

Notes: 1. Currents are measured at 85°C junction temperature. 2. Output drive strength is below JEDEC specification. 3. Output slew rate can be ex tracted by the IBIS models. Table 2-84  Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions Applicable to Advanced I/Os I/O Standard Drive Strength Slew Rate V IL VIH VOL VOH IOL IOH

3.3 V PCI Per PCI specifications

3.3 V PCI-X Per PCI-X specifications

Notes: 1. Currents are measured at 85°C junction temperature. 2. Output drive strength is below JEDEC specification.

2-164 Preliminary v1.7 Table 2-85  Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions Applicable to Standard I/Os I/O Standard Drive Strength Slew Rate V IL VIH VOL VOH IOL IOH Notes: 1. Currents are measured at 85°C junction temperature. 2. Output drive strength is below JEDEC specification. Table 2-86  Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions Applicable to All I/O Bank Types DC I/O Standards Commercial

1 Industrial2

µA µA µA µA 3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15

2.5 V LVCMOS 10 10 15 15

1.8 V LVCMOS 10 10 15 15

1.5 V LVCMOS 10 10 15 15

3.3 V PCI 10 10 15 15

3.3 V PCI-X 10 10 15 15

3.3 V GTL 10 10 15 15

2.5 V GTL 10 10 15 15

3.3 V GTL+ 10 10 15 15

2.5 V GTL+ 10 10 15 15

HSTL (I) 10 10 15 15 HSTL (II) 10 10 15 15 SSTL2 (I) 10 10 15 15 SSTL2 (II) 10 10 15 15 SSTL3 (I) 10 10 15 15 SSTL3 (II) 10 10 15 15 Notes: 1. Commercial range (0°C < T A < 70°C) 2. Industrial range (–40°C < T A < 85°C)

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-165 Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-87  Summary of AC Measuring Points Applicable to All I/O Bank Types Standard Input Reference Voltage (VREF_TYP) Board Termination Voltage (VTT_REF) Measuring Trip Point (Vtrip) 3.3 V LVTTL / 3.3 V LVCMOS – – 1.4 V 2.5 V LVCMOS – – 1.2 V 1.8 V LVCMOS – – 0.90 V 1.5 V LVCMOS – – 0.75 V 3.3 V PCI – – 0.285 * V CCI (RR) 0.615 * VCCI (FF)) 3.3 V PCI-X – – 0.285 * V CCI (RR) 0.615 * VCCI (FF) 3.3 V GTL 0.8 V 1.2 V V REF 2.5 V GTL 0.8 V 1.2 V V REF 3.3 V GTL+ 1.0 V 1.5 V V REF 2.5 V GTL+ 1.0 V 1.5 V V REF HSTL (I) 0.75 V 0.75 V V REF HSTL (II) 0.75 V 0.75 V V REF SSTL2 (I) 1.25 V 1.25 V V REF SSTL2 (II) 1.25 V 1.25 V V REF SSTL3 (I) 1.5 V 1.485 V V REF SSTL3 (II) 1.5 V 1.485 V V REF LVDS – – Cross point LVPECL – – Cross point Table 2-88  I/O AC Parameter Definitions Parameter Definition t DP Data to Pad delay through the Output Buffer tPY Pad to Data delay through the Input Buffer with Schmitt trigger disabled tDOUT Data to Output Buffer delay through the I/O interface tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface tDIN Input Buffer to Data delay through the I/O interface tPYS Pad to Data delay through the Input Buffer with Schmitt trigger enabled tHZ Enable to Pad delay through the Output Buffer—HIGH to Z tZH Enable to Pad delay through the Output Buffer—Z to HIGH tLZ Enable to Pad delay through the Output Buffer—LOW to Z tZL Enable to Pad delay through the Output Buffer—Z to LOW tZHS Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH tZLS Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW

2-166 Preliminary v1.7 Table 2-89  Summary of I/O Timing Characteristics – Software Default Settings Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/Os I/O Standard Drive Strength (mA) Slew Rate Capacitive Load (pF) External Resistor (Ohm) t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

3.3 V LVTTL/

3.3 V PCI Per

3.3 V PCI-X Per

LVDS 24 mA High – – 0.49 1.57 0.03 1.36 – – – – – – – – ns LVPECL 24 mA High – – 0.49 1.60 0.03 1.22 – – – – – – – – ns Notes: 1. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-7 for derating values. 2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-115 on page 2-191 for connectivity. This resistor is not required during normal operation.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-167 Table 2-90  Summary of I/O Timing Characteristics – Software Default Settings Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/Os I/O Standard Drive Strength (mA) Slew Rate Capacitive Load (pF) External Resistor (Ohm) t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 1.8 V LVCMOS

3.3 V PCI Per PCI

3.3 V PCI-X Per PCI-X

LVDS 24 mA High – – 0.49 1.37 0. 03 1.20 N/A N/A N/A N/A N/A N/A N/A ns LVPECL 24 mA High – – 0.49 1.34 0. 03 1.05 N/A N/A N/A N/A N/A N/A N/A ns Notes: 1. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-7 for derating values. 2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-115 on page 2-191 for connectivity. This resistor is not required during normal operation.

2-168 Preliminary v1.7 Table 2-91  Summary of I/O Timing Characteristics – Software Default Settings Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/Os I/O Standard Drive Strength (mA) Slew Rate Capacitive Load (pF) External Resistor (Ohm) t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units Notes: 1. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-7 for derating values. 2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-115 on page 2-191 for connectivity. This resistor is not required during normal operation.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-169 Detailed I/O DC Characteristics Table 2-92  Input Capacitance Symbol Definition Condi tions Min. Max. Units CIN Input capacitance V IN = 0, f = 1.0 MHz 8 pF CINCLK Input capacitance on the clock pin V IN = 0, f = 1.0 MHz 8 pF Table 2-93  I/O Output Buffer Maximum Resistances1 Standard Drive Strength RPULL-DOWN (ohms)2 RPULL-UP (ohms)3 Applicable to Pro I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 4 mA 100 300 8 mA 50 150 12 mA 25 75 16 mA 17 50 24 mA 11 33

2.5 V LVCMOS 4 mA 100 200

1.8 V LVCMOS 2 mA 200 225

1.5 V LVCMOS 2 mA 200 224

3.3 V PCI/PCI-X Per PCI/PCI-X specification 25 75

3.3 V GTL 25 mA 11 –

2.5 V GTL 25 mA 14 –

3.3 V GTL+ 35 mA 12 –

Notes: 1. These maximum values are provided for informatio nal reasons only. Minimum output buffer resistance values depend on V CC, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corres ponding IBIS models located on the Actel website at http://www.actel.com/techdocs/models/ibis.html. 2. R (PULL-DOWN-MAX) = VOLspec / IOLspec 3. R (PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

2-170 Preliminary v1.7

2.5 V GTL+ 33 mA 15 –

HSTL (I) 8 mA 50 50 HSTL (II) 15 mA 25 25 SSTL2 (I) 17 mA 27 31 SSTL2 (II) 21 mA 13 15 SSTL3 (I) 16 mA 44 69 SSTL3 (II) 24 mA 18 32 Applicable to Advanced I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300 4 mA 100 300 6 mA 50 150 8 mA 50 150 12 mA 25 75 16 mA 17 50 24 mA 11 33

2.5 V LVCMOS 2 mA 100 200

Table 2-93  I/O Output Buffer Maximum Resistances 1 (continued) Standard Drive Strength RPULL-DOWN (ohms)2 RPULL-UP (ohms)3 Notes: 1. These maximum values are provided for informatio nal reasons only. Minimum output buffer resistance values depend on VCC, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corres ponding IBIS models located on the Actel website at http://www.actel.com/techdocs/models/ibis.html. 2. R (PULL-DOWN-MAX) = VOLspec / IOLspec 3. R (PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-171 Applicable to Standard I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300 4 mA 100 300 6 mA 50 150 8 mA 50 150 Table 2-94  I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values V CCI R(WEAK PULL-UP) (ohms) R(WEAK PULL-DOWN) (ohms) Min. Max. Min. Max.

3.3 V 10 k 45 k 10 k 45 k

2.5 V 11 k 55 k 12 k 74 k

1.8 V 18 k 70 k 17 k 110 k

1.5 V 19 k 90 k 19 k 140 k

Notes: 1. R (WEAK PULL-DOWN-MAX) = VOLspec / IWEAK PULL-DOWN-MIN 2. R (WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / IWEAK PULL-UP-MIN Table 2-93  I/O Output Buffer Maximum Resistances1 (continued) Standard Drive Strength RPULL-DOWN (ohms)2 RPULL-UP (ohms)3 Notes: 1. These maximum values are provided for informatio nal reasons only. Minimum output buffer resistance values depend on VCC, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corres ponding IBIS models located on the Actel website at http://www.actel.com/techdocs/models/ibis.html. 2. R (PULL-DOWN-MAX) = VOLspec / IOLspec 3. R (PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

2-172 Preliminary v1.7 Table 2-95  I/O Short Currents IOSH/IOSL Drive Strength I OSH (mA)* I OSL (mA)* Applicable to Pro I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 4 mA 25 27 8 mA 51 54 12 mA 103 109 16 mA 132 127 24 mA 268 181

2.5 V LVCMOS 4 mA 16 18

1.8 V LVCMOS 2 mA 9 11

1.5 V LVCMOS 2 mA 13 16

Applicable to Advanced I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 25 27 4 mA 25 27 6 mA 51 54 8 mA 51 54 12 mA 103 109 16 mA 132 127 24 mA 268 181

3.3 V LVCMOS 2 mA 25 27

Note: *T J = 100°C

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-173 The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data below is based on a 3.3 V, 36 mA I/O setting, which is the worst case for this type of analysis. For example, at 110°C, the short current condition would have to be sustained for more than three months to cause a reliability concern. The I/O desi gn does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions.

2.5 V LVCMOS 2 mA 16 18

3.3 V PCI/PCI-X Per PCI/PCI-X

Applicable to Standard I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 25 27 4 mA 25 27 6 mA 51 54 8 mA 51 54 Table 2-95  I/O Short Currents I OSH/IOSL (continued) Drive Strength I OSH (mA)* I OSL (mA)* Note: *TJ = 100°C

2-174 Preliminary v1.7 Table 2-96  Short Current Event Duration before Failure Temperature Time before Failure –40°C >20 years 0°C >20 years 25°C >20 years 70°C 5 years 85°C 2 years 100°C 6 months 110°C 3 months Table 2-97  Schmitt Trigger Input Hysteresis Hysteresis Voltage Value (typ.) for Schmitt Mode Input Buffers Input Buffer Configuration Hysteresis Value (typ.)

3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode) 240 mV

2.5 V LVCMOS (Schmitt trigger mode) 140 mV

1.8 V LVCMOS (Schmitt trigger mode) 80 mV

1.5 V LVCMOS (Schmitt trigger mode) 60 mV

Table 2-98  I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability LVTTL/LVCMOS (Schmitt trigger disabled) No requirement 10 ns* 20 years (110°C) LVTTL/LVCMOS (Schmitt trigger enabled) No requirement No requirement, but input noise voltage cannot exceed Schmitt hysteresis 20 years (110°C) HSTL/SSTL/GTL No requirement 10 ns* 10 years (100°C) LVDS/BLVDS/M-LVDS/LVPECL No requ irement 10 ns* 10 years (100°C) Note: *The maximum input rise/fall time is related only to the noise induced into the input buffer trace. If the noise is low, the rise time and fall time of input buffers, when Schmitt trigger is disabled, can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure there is no excessive noise coupling into input signals.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-175 Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. The 3.3 V LVCMOS standard is supported as part of the 3.3 V LVTTL support. Table 2-99  Minimum and Maximum DC Input and Output Levels

3.3 V LVCMOS V IL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Max., mA1 Max., mA1 µA2 µA2 Applicable to Pro I/O Banks Applicable to Advanced I/O Banks Applicable to Standard I/O Banks Notes: 1. Currents are measured at high temperature (100 °C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Figure 2-111  AC Loading Table 2-100  AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) Measuring Point* (V) V REF (typ.) (V) C LOAD (pF) 03 . 3 1 . 4 – 3 5 Note: *Measuring point = V trip. See Table 2-87 on page 2-165 for a complete table of trip points. Test Point Test Point Enable PathData Path 35 pF R = 1 k R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ

2-176 Preliminary v1.7 Timing Characteristics Table 2-101  3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9. Table 2-102  3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-177 Table 2-103  3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9. Table 2-104  3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

2-178 Preliminary v1.7 Table 2-105  3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9. Table 2-106  3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-179

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general- purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer. Table 2-107  Minimum and Maximum DC Input and Output Levels

2.5 V LVCMOS V IL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Max., mA1 Max., mA1 µA2 µA2 Applicable to Pro I/O Banks Applicable to Advanced I/O Banks Applicable to Standard I/O Banks Notes: 1. Currents are measured at high temperature (100 °C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Figure 2-112  AC Loading Table 2-108  AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) Measuring Point* (V) V REF (typ.) (V) C LOAD (pF) 02 . 5 1 . 2 – 3 5 Note: *Measuring point = V trip. See Table 2-87 on page 2-165 for a complete table of trip points. Test Point Test Point Enable PathData Path 35 pF R = 1 k R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ

2-180 Preliminary v1.7 Timing Characteristics Table 2-109  2.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Pro I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9. Table 2-110  2.5 V LVCMOS High Slew Commercial-Case Conditions: T J = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Pro I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-181 Table 2-111  2.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9. Table 2-112  2.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/Os Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

2-182 Preliminary v1.7 Table 2-113  2.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard I/Os Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9. Table 2-114  2.5 V LVCMOS High Slew Commercial-Case Conditions: T J = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-183

1.8 V LVCMOS

Low-Voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.8 V applications. It uses a 1.8 V input buffer and push-pull output buffer. Table 2-115  Minimum and Maximum DC Input and Output Levels 1.8 V LVCMOS V IL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Drive Max., mA1 Max., mA1 µA2 µA2 Applicable to Pro I/O Banks Applicable to Advanced I/O Banks 2 mA –0.3 0.35 * V CCI 0.65 * V CCI 3.6 0.45 V CCI – 0.45 2 2 11 9 10 10 Applicable to Standard I/O Banks Notes: 1. Currents are measured at high temperature (100 °C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Figure 2-113  AC Loading Table 2-116  AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input LOW (V) Measuring Point* (V) V REF (typ.) (V) C LOAD (pF) 01 . 8 0 . 9 – 3 5 Note: *Measuring point = Vtrip. See Table 2-87 on page 2-165 for a complete table of trip points. Test Point Test Point Enable PathData Path 35 pF R = 1 k R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ

2-184 Preliminary v1.7 Timing Characteristics Table 2-117  1.8 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Pro I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9. Table 2-118  1.8 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Pro I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-185 Table 2-119  1.8 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9. Table 2-120  1.8 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 8 mA Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

2-186 Preliminary v1.7 Table 2-121  1.8 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9. Table 2-122  1.8 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard I/Os Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-187

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.5 V applications. It uses a 1.5 V input buffer and push-pull output buffer. Table 2-123  Minimum and Maximum DC Input and Output Levels 1.5 V LVCMOS V IL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Drive Max., mA1 Max., mA1 µA2 µA2 Applicable to Pro I/O Banks Applicable to Pro I/O Banks Applicable to Pro I/O Banks Notes: 1. Currents are measured at high temperature (100 °C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Figure 2-114  AC Loading Table 2-124  AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) Measuring Point* (V) V REF (typ.) (V) C LOAD (pF) 0 1.5 0.75 – 35 Note: *Measuring point = Vtrip. See Table 2-87 on page 2-165 for a complete table of trip points. Test Point Test Point Enable PathData Path 35 pF R = 1 k R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ

2-188 Preliminary v1.7 Timing Characteristics Table 2-125  1.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Pro I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9. Table 2-126  1.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Pro I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-189 Table 2-127  1.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9. Table 2-128  1.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

2-190 Preliminary v1.7 Table 2-129  1.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Standard I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9. Table 2-130  1.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Standard I/Os Drive Strength Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-191 3.3 V PCI, 3.3 V PCI-X The Peripheral Component Interface for 3.3 V st andard specifies suppor t for 33 MHz and 66 MHz PCI Bus applications. AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable path characterization are described in Figure 2-115. AC loadings are defined per PCI/PCI-X specifications for the data path; Actel loading for tristate is described in Table 2-132. Table 2-131  Minimum and Maximum DC Input and Output Levels

3.3 V PCI/PCI-X V IL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Max., mA1 Max., mA1 µA2 µA2 Per PCI specification Per PCI curves 10 10 Notes: 1. Currents are measured at high temperature (100 °C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. Figure 2-115  AC Loading Test Point Enable Path R = 1 k Test Point Data Path R = 25 R to VCCI for tDP (F) R to GND for tDP (R) R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 10 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Table 2-132  AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) Measuring Point* (V) V REF (typ.) (V) C LOAD (pF) 0 3.3 0.285 * V CCI for tDP(R) 0.615 * VCCI for tDP(F) –1 0 Note: *Measuring point = Vtrip. See Table 2-87 on page 2-165 for a complete table of trip points.

2-192 Preliminary v1.7 Timing Characteristics Table 2-133  3.3 V PCI/PCI-X Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/Os Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9. Table 2-134  3.3 V PCI/PCI-X Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/Os Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-193 Voltage Referenced I/O Characteristics

3.3 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V. Timing Characteristics Table 2-135  Minimum and Maximum DC Input and Output Levels

3.3 V GTL V IL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Max., mA1 Max., mA1 µA2 µA2 Note: 1. Currents are measured at high temperature (100 °C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Output drive strength is below JEDEC specification. Figure 2-116  AC Loading Table 2-136  AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) Measuring Point* (V) V REF (typ.) (V) V TT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-87 on page 2-165 for a complete table of trip points. Test Point 10 pF 25GTL VTT Table 2-137  3.3 V GTL Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 0.8 V Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

2-194 Preliminary v1.7

2.5 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V. Timing Characteristics Table 2-138  Minimum and Maximum DC Input and Output Levels

2.5 GTL V IL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Min., Max., mA1 Max., mA1 µA2 µA2 1. Currents are measured at hi gh temperature (100°C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Output drive strength is below JEDEC specification. Figure 2-117  AC Loading Table 2-139  AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) Measuring Point* (V) V REF (typ.) (V) V TT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-87 on page 2-165 for a complete table of trip points. Test Point 10 pF 25GTL VTT Table 2-140  2.5 V GTL Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 0.8 V Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-195

3.3 V GTL+

Gunning Transceiver Logic Plus is a high-speed bu s standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V. Timing Characteristics Table 2-141  Minimum and Maximum DC Input and Output Levels

3.3 V GTL+ V IL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

m A m A Max., mA1 Max. mA1 µA2 µA2 Notes: 1. Currents are measured at high temperature (100 °C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. Figure 2-118  AC Loading Table 2-142  AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) Measuring Point* (V) V REF (typ.) (V) V TT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-87 on page 2-165 for a complete table of trip points. Test Point 10 pF 25GTL+ VTT Table 2-143  3.3 V GTL+ Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 1.0 V Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

2-196 Preliminary v1.7

2.5 V GTL+

Gunning Transceiver Logic Plus is a high-speed bu s standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V. Timing Characteristics Table 2-144  Minimum and Maximum DC Input and Output Levels

2.5 V GTL+ V IL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Strength Min., V Max., V Min., V Max., V Max., V Min., Vm A m A Max., mA1 Max., mA1 µA2 µA2 Notes: 1. Currents are measured at high temperature (100 °C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. Figure 2-119  AC Loading Table 2-145  AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) Measuring Point* (V) V REF (typ.) (V) V TT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-87 on page 2-165 for a complete table of trip points. Test Point 10 pF 25GTL+ VTT Table 2-146  2.5 V GTL+ Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V, VREF = 1.0 V Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-197 HSTL Class I High-Speed Transceiver Logic is a general-purpos e high-speed 1.5 V bus standard (EIA/JESD8-6). Fusion devices support Class I. This provides a di fferential amplifier inpu t buffer and a push-pull output buffer. Timing Characteristics Table 2-147  Minimum and Maximum DC Input and Output Levels HSTL Class I V IL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Drive Max., mA1 Max. mA1 µA2 µA2 Notes: 1. Currents are measured at high temperature (100 °C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. Figure 2-120  AC Loading Table 2-148  AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) Measuring Point* (V) V REF (typ.) (V) V TT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-87 on page 2-165 for a complete table of trip points. Test Point 20 pF HSTL Class I VTT Table 2-149  HSTL Class I Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V, VREF = 0.75 V Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

2-198 Preliminary v1.7 HSTL Class II High-Speed Transceiver Logic is a general-purpos e high-speed 1.5 V bus standard (EIA/JESD8-6). Fusion devices support Class II. This provides a di fferential amplifier inpu t buffer and a push-pull output buffer. Timing Characteristics Table 2-150  Minimum and Maximum DC Input and Output Levels HSTL Class II V IL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Drive Max., mA1 Max., mA1 µA µA Note: 1. Currents are measured at high temperature (100 °C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Output drive strength is below JEDEC specification. Figure 2-121  AC Loading Table 2-151  AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) V TT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-87 on page 2-165 for a complete table of trip points. Test Point 20 pF HSTL Class II VTT Table 2-152  HSTL Class II Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V, VREF = 0.75 V Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-199 SSTL2 Class I Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). Fusion devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Timing Characteristics Table 2-153  Minimum and Maximum DC Input and Output Levels SSTL2 Class I V IL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Drive Max., mA1 Max., mA1 µA2 µA2 Notes: 1. Currents are measured at high temperature (100 °C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. Figure 2-122  AC Loading Table 2-154  AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) Measuring Point* (V) V REF (typ.) (V) V TT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-87 on page 2-165 for a complete table of trip points. Test Point 30 pF SSTL2 Class I VTT Table 2-155  SSTL 2 Class I Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V, VREF = 1.25 V Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

2-200 Preliminary v1.7 SSTL2 Class II Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). Fusion devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Timing Characteristics Table 2-156  Minimum and Maximum DC Input and Output Levels SSTL2 Class II V IL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2 Notes: 1. Currents are measured at high temperature (100 °C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. Figure 2-123  AC Loading Table 2-157  AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) Measuring Point* (V) V REF (typ.) (V) V TT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-87 on page 2-165 for a complete table of trip points. Test Point 30 pF SSTL2 Class II VTT Table 2-158  SSTL 2 Class II Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V, VREF = 1.25 V Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-201 SSTL3 Class I Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). Fusion devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Timing Characteristics Table 2-159  Minimum and Maximum DC Input and Output Levels SSTL3 Class I V IL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2 Notes: 1. Currents are measured at high temperature (100 °C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. Figure 2-124  AC Loading Table 2-160  AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) Measuring Point* (V) V REF (typ.) (V) V TT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-87 on page 2-165 for a complete table of trip points. Test Point 30 pF SSTL3 Class I VTT Table 2-161  SSTL3 Class I Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 1.5 V Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

2-202 Preliminary v1.7 SSTL3 Class II Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). Fusion devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Timing Characteristics Table 2-162  Minimum and Maximum DC Input and Output Levels SSTL3 Class II V IL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Drive Strength Min., V Max., V Min., V Max., V Max. , V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2 Notes: 1. Currents are measured at high temperature (100 °C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. Figure 2-125  AC Loading Table 2-163  AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V ) Measuring Point* (V) V REF (typ.) (V) V TT (typ.) (V) C LOAD (pF) Note: *Measuring point = Vtrip. See Table 2-87 on page 2-165 for a complete table of trip points. Test Point 30 pF SSTL3 Class II VTT Table 2-164  SSTL3- Class II Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 1.5 V Speed Grade t DOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-203 Differential I/O Characteristics Configuration of the I/O modules as a differential pair is handled by the Actel Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no support for bidirectional I/Os or tristates with these standards. LVDS Low-Voltage Differential Signal (ANSI/TIA/EIA-644) is a high-speed differential I/O standard. It requires that one data bit be carried through tw o signal lines, so two pi ns are needed. It also requires external resistor termination. The full implementation of the LVDS transmitt er and receiver is shown in an example in Figure 2-126. The building blocks of the LVDS transmitt er–receiver are one transmitter macro, one receiver macro, three board resistors at the transm itter end, and one resistor at the receiver end. The values for the three driv er resistors are different from those used in the LVPECL implementation because the output standard specifications are different. Figure 2-126  LVDS Circuit Diagram and Board-Level Implementation Table 2-165  Minimum and Maximum DC Input and Output Levels DC Parameter Descripti on Min. Typ. Max. Units VCCI Supply Voltage 2.375 2.5 2.625 V VOL Output LOW Voltage 0.9 1.075 1.25 V VOH Input HIGH Voltage 1.25 1.425 1.6 V IOL 3 Input LOW Voltage 0.65 0.91 1.16 mA IOH 3 Output HIGH Voltage 0.65 0.91 1.16 mA VI Input Voltage 0 2.925 V IIL

4 Input LOW Voltage 10 μA

4 Output HIGH Voltage 10 μA

VODIFF Differential Output Voltage 250 350 450 mV VOCM Output Common Mode Voltage 1.125 1.25 1.375 V VICM Input Common Mode Voltage 0.05 1.25 2.35 V VIDIFF Input Differential Voltage 100 350 mV Notes: 1. ±5% 2. Differential input voltage = ±350 mV 140 Ω 100 Ω ZO = 50 Ω ZO = 50 Ω 165 Ω 165 Ω P N P N INBUF_LVDS OUTBUF_LVDS FPGA FPGA Bourns Part Number: CAT16-LV4F12

2-204 Preliminary v1.7 Timing Characteristics BLVDS/M-LVDS Bus LVDS (BLVDS) and Multipoint LVDS (M-LVDS) sp ecifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations can contain any combin ation of drivers, receivers, and transce ivers. Actel LVDS drivers provide the higher drive current required by BLVDS and M-LVDS to accommodate the loading. The driver requires series terminations for better signal qu ality and to control voltage swing. Termination is also required at both ends of the bus, since the driver can be located anywhere on the bus. These configurations can be implemented using TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations. Multipoint designs usin g Actel LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sa mple application is given in Figure 2-127. The input and output buffer delays are available in the LVDS section in Table 2-168. Example: For a bus consisting of 20 equidistant loads, the following te rminations provide the required differential voltage, in worst-case industrial operating conditions at the farthest receiver: R S =6 0 Ω and RT =7 0 Ω, given Z0 =5 0 Ω (2") and Zstub =5 0 Ω (~1.5"). Table 2-166  AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) Measuring Point* (V) V REF (typ.) (V) 1.075 1.325 Cross point – Note: *Measuring point = V trip. See Table 2-87 on page 2-165 for a complete table of trip points. Table 2-167  LVDS Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Pro I/Os Speed Grade t DOUT tDP tDIN tPY Units –1 0.56 1.79 0.04 1.55 ns –2 0.49 1.57 0.03 1.36 ns Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9. Figure 2-127  BLVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers ... RT RT BIBUF_LVDSR + - T + - R + - T + - D + - EN EN EN EN EN Receiver Transceiver Receiver Transceiver Driver RS RS RS RS RS RS RS RSRS RS Zstub Zstub Zstub Zstub Zstub Zstub Zstub Zstub

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-205 LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitt er and receiver is shown in an example in Figure 2-128. The building blocks of the LVPECL transm itter–receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for th e three driver resistors are differ ent from those used in the LVDS implementation because the output standard specifications are different. Timing Characteristics Figure 2-128  LVPECL Circuit Diagram and Board-Level Implementation Table 2-168  Minimum and Maximum DC Input and Output Levels VCCI Supply Voltage 3.0 3.3 3.6 V VIL, VIH Input LOW, Input HIGH Voltages 0 3.3 0 3.6 0 3.9 V VIDIFF Input Differential Voltage 300 300 300 mV Table 2-169  AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) Measuring Point* (V) V REF (typ.) (V) 1.64 1.94 Cross point – Note: *Measuring point = V trip. See Table 2-87 on page 2-165 for a complete table of trip points.

187 W 100 Ω

ZO = 50 Ω ZO = 50 Ω 100 Ω 100 Ω P N P N INBUF_LVPECL OUTBUF_LVPECL FPGA FPGA Bourns Part Number: CAT16-PC4F12 Table 2-170  LVPECL Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Pro I/Os Speed Grade t DOUT tDP tDIN tPY Units –1 0.56 1.82 0.04 1.39 ns –2 0.49 1.60 0.03 1.22 ns Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

2-206 Preliminary v1.7 I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset Figure 2-129  Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset INBUF INBUF INBUF TRIBUF CLKBUF INBUFINBUFCLKBUF Data Input I/O Register with: Active High Enable Active High Preset Positive Edge Triggered Data Output Register and Enable Output Register with: Active High Enable Active High Preset Postive Edge Triggered Pad Out CLK Enable Preset Data_out Data XX X X X X X X X X XX X X EOUT DOUT Enable CLK DQ DFN1E1P1 PRE DQ DFN1E1P1 PRE DQ DFN1E1P1 PRE D_Enable A B C D E E E E F G H I J L K Y Core Array

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-207 Table 2-171  Parameter Definitions and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register H, DOUT tOSUD Data Setup Time for the Output Data Register F, H tOHD Data Hold Time for the Output Data Register F, H tOSUE Enable Setup Time for the Output Data Register G, H tOHE Enable Hold Time for the Output Data Register G, H tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register L,DOUT tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H tOECLKQ Clock-to-Q of the Output Enable Register H, EOUT tOESUD Data Setup Time for the Output Enable Register J, H tOEHD Data Hold Time for the Output Enable Register J, H tOESUE Enable Setup Time for the Output Enable Register K, H tOEHE Enable Hold Time for the Output Enable Register K, H tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register I, EOUT tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register I, H tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register I, H tICLKQ Clock-to-Q of the Input Data Register A, E tISUD Data Setup Time for the Input Data Register C, A tIHD Data Hold Time for the Input Data Register C, A tISUE Enable Setup Time for the Input Data Register B, A tIHE Enable Hold Time for the Input Data Register B, A tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A Note: *See Figure 2-129 on page 2-206 for more information.

2-208 Preliminary v1.7 Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear Figure 2-130  Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear Core Array Data Input I/O Register with Active High Enable Active High Clear Positive Edge Triggered Data Output Register and Enable Output Register with Active High Enable Active High Clear Positive Edge Triggered Enable CLK Pad Out CLK Enable CLR Data_out Data Y AA EOUT DOUT DQ DFN1E1C1 E CLR DQ DFN1E1C1 E CLR DQ DFN1E1C1 E CLR D_Enable BB CC DD EE FF GG LL HH JJ KK CLKBUF INBUF INBUF TRIBUF INBUF INBUF CLKBUF INBUF

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-209 Table 2-172  Parameter Definitions and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register HH, DOUT tOSUD Data Setup Time for the Output Data Register FF, HH tOHD Data Hold Time for the Output Data Register FF, HH tOSUE Enable Setup Time for the Output Data Register GG, HH tOHE Enable Hold Time for the Output Data Register GG, HH tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register LL, DOUT tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH tORECCLR Asynchronous Clear Recovery Time for the Output Data Register LL, HH tOECLKQ Clock-to-Q of the Output Enable Register HH, EOUT tOESUD Data Setup Time for the Output Enable Register JJ, HH tOEHD Data Hold Time for the Output Enable Register JJ, HH tOESUE Enable Setup Time for the Output Enable Register KK, HH tOEHE Enable Hold Time for the Output Enable Register KK, HH tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register II, EOUT tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register II, HH tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register II, HH tICLKQ Clock-to-Q of the Input Data Register AA, EE tISUD Data Setup Time for the Input Data Register CC, AA tIHD Data Hold Time for the Input Data Register CC, AA tISUE Enable Setup Time for the Input Data Register BB, AA tIHE Enable Hold Time for the Input Data Register BB, AA tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register DD, AA Note: *See Figure 2-130 on page 2-208 for more information.

2-210 Preliminary v1.7 Input Register Timing Characteristics Figure 2-131  Input Register Timing Diagram 50% Preset Clear Out_1 CLK Data Enable tISUE 50% 50% tISUD tIHD 50% 50% tICLKQ 1 0 tIHE tIRECPRE tIREMPRE tIRECCLR tIREMCLRtIWCLR tIWPRE tIPRE2Q tICLR2Q tICKMPWH tICKMPWL 50% 50% 50% 50% 50% 50% 50% 50% Table 2-173  Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tICLKQ Clock-to-Q of the Input Data Register 0.24 0.27 0.32 ns tISUD Data Setup Time for the Input Data Register 0.26 0.30 0.35 ns tIHD Data Hold Time for the Input Data Register 0.00 0.00 0.00 ns tISUE Enable Setup Time for the Input Data Register 0.37 0.42 0.50 ns tIHE Enable Hold Time for the Input Data Register 0.00 0.00 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.45 0.52 0.61 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.45 0.52 0.61 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.22 0.25 0.30 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.22 0.25 0.30 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.22 0.25 0.30 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.22 0.25 0.30 ns tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register 0.36 0.41 0.48 ns tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register 0.32 0.37 0.43 ns Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-211 Output Register Timing Characteristics Output Enable Register Figure 2-132  Output Register Timing Diagram Preset Clear DOUT CLK Data_out nable tOSUE 50% 50% tOSUD tOHD 50% 50% tOCLKQ 1 0 tOHE tORECPRE tOREMPRE tORECCLR tOREMCLRtOWCLR tOWPRE tOPRE2Q tOCLR2Q tOCKMPWH tOCKMPWL 50% 50% 50% 50% 50% 50% 50% 50% 50% Table 2-174  Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tOCLKQ Clock-to-Q of the Output Data Register 0.59 0.67 0.79 ns tOSUD Data Setup Time for the Output Data Register 0.31 0.36 0.42 ns tOHD Data Hold Time for the Output Data Register 0.00 0.00 0.00 ns tOSUE Enable Setup Time for the Output Data Register 0.44 0.50 0.59 ns tOHE Enable Hold Time for the Output Data Register 0.00 0.00 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.80 0.91 1.07 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.80 0.91 1.07 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.22 0.25 0.30 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.22 0.25 0.30 ns tOWCLR Asynchronous Clear Minimum Pu lse Width for the Output Data Register 0.22 0.25 0.30 ns tOWPRE Asynchronous Preset Minimum Pu lse Width for the Output Data Register 0.22 0.25 0.30 ns tOCKMPWH Clock Minimum Pulse Width HIGH for the Output Data Register 0.36 0.41 0.48 ns

2-212 Preliminary v1.7 tOCKMPWL Clock Minimum Pulse Width LOW for the Output Data Register 0.32 0.37 0.43 ns Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9. Figure 2-133  Output Enable Register Timing Diagram Table 2-174  Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units 50% Preset Clear EOUT CLK D_Enable Enable tOESUE 50% 50% tOESUD tOEHD 50% 50% tOECLKQ 1 0 tOEHE tOERECPRE tOEREMPRE tOERECCLR tOEREMCLRtOEWCLR tOEWPRE tOEPRE2Q tOECLR2Q tOECKMPWH tOECKMPWL 50% 50% 50% 50% 50% 50% 50% 50%

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-213 Timing Characteristics Table 2-175  Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tOECLKQ Clock-to-Q of the Output Enable Register 0.44 0.51 0.59 ns tOESUD Data Setup Time for the Output Enable Register 0.31 0.36 0.42 ns tOEHD Data Hold Time for the Output Enable Register 0.00 0.00 0.00 ns tOESUE Enable Setup Time for the Output Enable Register 0.44 0.50 0.58 ns tOEHE Enable Hold Time for the Output Enable Register 0.00 0.00 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.67 0.76 0.89 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.67 0.76 0.89 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 0.00 ns tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.22 0.25 0.30 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.22 0.25 0.30 ns tOEWCLR Asynchronous Clear Minimum Puls e Width for the Output Enable Register 0.22 0.25 0.30 ns tOEWPRE Asynchronous Preset Minimum Pu lse Width for the Output Enable Register 0.22 0.25 0.30 ns tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register 0.36 0.41 0.48 ns tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register 0.32 0.37 0.43 ns Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

2-214 Preliminary v1.7 DDR Module Specifications Input DDR Module Figure 2-134  Input DDR Timing Model Table 2-176  Parameter Definitions Parameter Name Parameter Definiti on Measuring Nodes (from, to) tDDRICLKQ1 Clock-to-Out Out_QR B, D tDDRICLKQ2 Clock-to-Out Out_QF B, E tDDRISUD Data Setup Time of DDR Input A, B tDDRIHD Data Hold Time of DDR Input A, B tDDRICLR2Q1 Clear-to-Out Out_QR C, D tDDRICLR2Q2 Clear-to-Out Out_QF C, E tDDRIREMCLR Clear Removal C, B tDDRIRECCLR Clear Recovery C, B Input DDR Data CLK CLKBUF INBUF Out_QF (to core) FF2 FF1 INBUF CLR DDR_IN E A B C D Out_QR (to core)

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-215 Timing Characteristics Figure 2-135  Input DDR Timing Diagram tDDRICLR2Q2 tDDRIREMCLR tDDRIRECCLR tDDRICLR2Q1 12 3 4 5 6 7 8 9 CLK Data CLR Out_QR Out_QF tDDRICLKQ1 2 4 6 3 5 7 tDDRIHDtDDRISUD tDDRICLKQ2 Table 2-177  Input DDR Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.39 0.44 0.52 ns tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.27 0.31 0.37 ns tDDRISUD Data Setup for Input DDR 0.28 0.32 0.38 ns tDDRIHD Data Hold for Input DDR 0.00 0.00 0.00 ns tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR 0.57 0.65 0.76 ns tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.46 0.53 0.62 ns tDDRIREMCLR Asynchronous Clear Removal Time for Input DDR 0.00 0.00 0.00 ns tDDRIRECCLR Asynchronous Clear Recovery Time for Input DDR 0.22 0.25 0.30 ns tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.22 0.25 0.30 ns tDDRICKMPWH Clock Minimum Pulse Width HIGH for Input DDR 0.36 0.41 0.48 ns tDDRICKMPWL Clock Minimum Pulse Width LOW for Input DDR 0.32 0.37 0.43 ns FDDRIMAX Maximum Frequency for Input DDR MHz Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

2-216 Preliminary v1.7 Output DDR Figure 2-136  Output DDR Timing Model Table 2-178  Parameter Definitions Parameter Name Parameter Definition Measuring Nodes (From, To) tDDROCLKQ Clock-to-Out B, E tDDROCLR2Q Asynchronous Clear-to-Out C, E tDDROREMCLR Clear Removal C, B tDDRORECCLR Clear Recovery C, B tDDROSUD1 Data Setup Data_F A, B tDDROSUD2 Data Setup Data_R D, B tDDROHD1 Data Hold Data_F A, B tDDROHD2 Data Hold Data_R D, B Data_F (from core) CLK CLKBUF Out FF2 INBUF CLR DDR_OUT FF1 X X X X X X X A B D EC C B OUTBUF Data_R (from core)

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-217 Timing Characteristics Figure 2-137  Output DDR Timing Diagram 116 91 0 28 3 9 tDDROREMCLR tDDROHD1tDDROSUD1 tDDROHD2tDDROSUD2 tDDROCLKQ tDDRORECCLR CLK Data_R Data_F CLR Out tDDROCLR2Q 71 0 4 Table 2-179  Output DDR Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tDDROCLKQ Clock-to-Out of DDR for Output DDR 0.70 0.80 0.94 ns tDDROSUD1 Data_F Data Setup for Output DDR 0.38 0.43 0.51 ns tDDROSUD2 Data_R Data Setup for Output DDR 0.38 0.43 0.51 ns tDDROHD1 Data_F Data Hold for Output DDR 0. 00 0.00 0.00 ns tDDROHD2 Data_R Data Hold for Output DDR 0.00 0.00 0.00 ns tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 0.80 0.91 1.07 ns tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 0.00 0.00 ns tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.22 0.25 0.30 ns tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.22 0.25 0.30 ns tDDROCKMPWH Clock Minimum Pulse Width HIGH for the Output DDR 0.36 0.41 0.48 ns tDDROCKMPWL Clock Minimum Pulse Width LOW for the Output DDR 0.32 0.37 0.43 ns FDDOMAX Maximum Frequency for the Output DDR MHz Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

2-218 Preliminary v1.7 Pin Descriptions Supply Pins GND Ground Ground supply voltage to the core, I/O outputs, and I/O logic. GNDQ Ground (quiet) Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is decoupled from the simultaneous switching noi se originated from the output buffer ground domain. This minimizes the noise transfer within the package and improves input signal integrity. GNDQ needs to always be conn ected on the board to GND. Note : In FG256, FG484, and FG676 packages, GNDQ and GND pins are connected with in the package and are labeled as GND pins in the respective package pin assignment tables. ADCGNDREF Analog Reference Ground Analog ground reference used by the ADC. This pad should be connected to a quiet analog ground. GNDA Ground (analog) Quiet ground supply voltage to th e Analog Block of Fusion device s. The use of a separate analog ground helps isolate the analog functionality of the Fusion device from any digital switching noise. A 0.2 V maximum differential voltage between GND and GNDA/GNDQ should apply to system implementation. GNDAQ Ground (analog quiet) Quiet ground supply voltage to the analog I/O of Fusion devices. The use of a separate analog ground helps isolate the analog functionality of the Fusion device from any digital switching noise. A 0.2 V maximum differential voltage between GND and GNDA/GNDQ should apply to system implementation. Note: In FG 256, FG484, and FG676 packages, GNDAQ and GNDA pins are connected within the package and are labeled as GNDA pins in the respective package pin assignment tables. GNDNVM Flash Memory Ground Ground supply used by the Fusion device's flash memory block module(s). GNDOSC Oscillator Ground Ground supply for both integrated RC oscillator and crystal oscillator circuit. VCC15A Analog Power Supply (1.5 V) A 1.5 V analog power supply input should be used to provide this input. VCC33A Analog Power Supply (3.3 V) 3.3 V clean analog power supply input for use by the 3.3 V portion of the analog circuitry. VCC33N Negative 3.3 V Output This is the –3.3 V output from the voltage conv erter. A 2.2 µF capacitor must be connected from this pin to ground. VCC33PMP Analog Power Supply (3.3 V) 3.3 V clean analog power supply in put for use by the analog charge pump. To avoid high current draw, VCC33PMP should be powered up before or simultaneously with VCC33A. VCCNVM Flash Memory Block Power Supply (1.5 V) 1.5 V power supply input used by the Fusion device's flash memory block module(s). To avoid high current draw, V CC should be powered up before or simultaneously with VCCNVM.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-219 VCCOSC Oscillator Power Supply (3.3 V) Power supply for both integrated RC oscillator and crystal oscillator circuit. VCC Core Supply Voltage Supply voltage to the FPGA core, nominally 1.5 V. VCC is also required for powering the JTAG state machine, in addition to V JTAG. Even when a Fusion device is in bypass mode in a JTAG chain of interconnected devices, both V CC and V JTAG must remain powered to al low JTAG signals to pass through the Fusion device. VCCIBx I/O Supply Voltage Supply voltage to the bank's I/O output buffers and I/O logic. B x is the I/O bank number. There are either four (AFS090 and AFS250) or five (AFS600 and AFS1500) I/O banks on the Fusion devices plus a dedicated VJTAG bank. Each bank can have a separate V CCI connection. All I/Os in a bank will run off the same V CCIBx corresponding VCCI pins tied to GND. VCCPLA/B PLL Supply Voltage Supply voltage to analog PLL, nominally 1.5 V, where A and B refer to the PLL. AFS090 and AFS250 each have a single PLL. The AFS600 and AFS1500 devices each have two PLLs. Actel recommends tying VCCPLX to VCC and using proper filtering circuits to decouple VCC noise from PLL. If unused, VCCPLA/B should be tied to GND. VCOMPLA/B Ground for West and East PLL VCOMPLA is the ground of the west PLL (CCC location F) and V COMPLB is the ground of the east PLL (CCC location C). VJTAG JTAG Supply Voltage Fusion devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and simp lifies power supply and PCB design. If the JTAG interface is neither used nor planned to be used, the V JTAG pin together with the TRST pin could be tied to GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is insufficient. If a Fusion device is in a JTAG chain of interconnected boards and it is desired to power down the board containing the Fusion device, this may be done provided both V JTAG and VCC to the Fusion part remain powe red; otherwise, JTAG signals will not be able to transition the Fusion device, even in bypass mode. VPUMP Programming Supply Voltage Fusion devices support single-voltage ISP progra mming of the configuration flash and FlashROM. For programming, V PUMP should be in the 3.3 V +/-5% range. During normal device operation, VPUMP can be left floating or can be tied to any voltage between 0 V and 3.6 V. When the VPUMP pin is tied to ground, it shuts off the charge pump circuitry, resulting in no sources of oscillation from the charge pump circuitry. For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible. User-Defined Supply Pins VREF I/O Voltage Reference Reference voltage for I/O minibanks. Both AFS600 and AFS1500 (north bank only) support Actel Pro I/O. These I/O banks support voltag e reference standard I/O. The V REF pins are configured by the user from regular I/Os, and any I/O in a bank, except JTAG I/Os, can be designated as the voltage reference I/O. Only certain I/O standards require a voltage reference—HSTL (I ) and (II), SSTL2 (I) and (II), SSTL3 (I) and (II), and GTL/GTL+. One V REF pin can support the number of I/Os available in its minibank.

2-220 Preliminary v1.7 VAREF Analog Reference Voltage The Fusion device can be configured to generate a 2.56 V internal reference voltage that can be used by the ADC. While using the internal reference, the reference voltage is output on the VAREF pin for use as a system reference. If a different reference voltage is required, it can be supplied by an external source and applied to this pin. The valid range of values that can be supplied to the ADC is 1.0 V to 3.3 V. When VAREF is internally generated by the Fusion device, a bypass capacitor must be connected from this pin to ground. The value of the bypass capacitor should be between 3.3 µF and 22 µF , which is based on the needs of the individual designs. The choice of the capacitor value has an impact on the settling time it takes the VAREF signal to reach the required specification of 2.56 V to initiate valid conve rsions by the ADC. If the lower capacitor value is chosen, the settling time required for VAREF to achieve 2.56 V will be shorter than when selecting the larger capacitor value. The above range of capacitor values supports the accuracy specification of the ADC, which is detailed in the datasheet. Designers choosing the smaller capacitor value will not obtain as much marg in in the accuracy as that achieved with a larger capacitor value. Depending on the capacitor value selected in the Analog System Builder, a to ol in Libero IDE, an automatic delay circuit will be generated using logic tiles available within the FPGA to ensure that VAREF has achieved the 2.56 V value. Actel recomme nds customers use 10 µF as the value of the bypass capacitor. Designers choosing to use an external VAREF need to ensure that a stable and clean VAREF source is supplied to the VAREF pin before initiating conversions by the ADC. Designers should also make sure that the ADCRESET signal is d easserted before initiating valid conversions.2 User Pins I/O User Input/Output The I/O pin functions as an input, output, tristate , or bidirectional buffer. Input and output signal levels are compatible with the I/O standard selected. Unused I/O pins are configured as inputs with pull-up resistors. During programming, I/Os become tri stated and weakly pulled up to V CCI. With the V CCI and V CC supplies continuously powered up, when the devi ce transitions from programming to operating mode, the I/Os get instantly configured to the desired user configuration. Axy Analog Input/Output Analog I/O pin, where x is the analog pad type (C = current pad, G = Gate driver pad, T = Temperature pad, V = Voltage pad) and y is the Analog Qu ad number (0 to 9). There is a minimum 1 MΩ to ground on AV, AC, and AT. This pin can be left floating when it is unused. ATRTNx Temperature Monitor Return AT returns are the returns for the temperature sensors. The cathode terminal of the external diodes should be connected to these pins. There is one analog return pin for every two Analog Quads. The x in the ATRTNx designator indicates the quad pairing ( x = 0 for AQ1 and AQ2, x = 1 for AQ2 and AQ3, ..., x = 4 for AQ8 and AQ9). The signals that driv e these pins are called out as ATRETUN xy in the software (where x and y refer to the quads that share the return signal). ATRTN is internally connected to ground. It can be left floating when it is unused. GL Globals GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the global network (spines). Additionally, the global I/Os can be used as Pro I/Os since they have identical capabilities. Unused GL pins are config ured as inputs with pu ll-up resistors. See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits" section on page 2-24. Refer to the "User I/O Naming Convention" section on page 2-157 for a description of naming of global pins. 2. The ADC is functional with an external refere nce down to 1V, however to meet the performance parameters highlighted in the datasheet refer to the VAREF specification in Table 3-2 on page 3-3.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-221 JTAG Pins Fusion devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). V CC must also be powered for the JTAG state machine to operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the Fusion part must be supplied to allow JTAG signals to transition the Fusion device. Isolating the JTAG power supply in a separate I/O bank gives greater flexibility with supply selection and simplifies power supp ly and PCB design. If the JTAG interface is neither used nor planned to be used, the VJTAG pin together with the TRST pin could be tied to GND. TCK Test Clock Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-up/-down resistor. If JTAG is not used , Actel recommends tyin g off TCK to GND or V JTAG through a resistor placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state. Note that to operate at all V JTAG voltages, 500 Ω to 1 k Ω will satisfy the requirements. Refer to Table 2-180 for more information. TDI Test Data Input Serial input for JTAG boundary sc an, ISP, and UJTAG usage. Ther e is an internal weak pull-up resistor on the TDI pin. TDO Test Data Output Serial output for JTAG boundary scan, ISP, and UJTAG usage. TMS Test Mode Select The TMS pin controls the use of the IEEE1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an internal weak pull-up resistor on the TMS pin. TRST Boundary Scan Reset Pin The TRST pin functions as an acti ve low input to asynch ronously initialize (or reset) the boundary scan circuitry. There is an internal weak pull-up resistor on the TR ST pin. If JTAG is not used, an external pull-down resistor could be included to ensure the TAP is held in reset mode. The resistor values must be chosen from Table 2-180 and must satisfy the parallel resistance value requirement. The values in Table 2-180 correspond to the resistor recommended when a single device is used and to the equivalent parallel resistor when multiple devices are connected via a JTAG chain. In critical applications, an upset in the JTAG circuit could allow entering an undesired JTAG state. In such cases, Actel recommends tyin g off TRST to GND through a resi stor placed close to the FPGA pin. Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ will satisfy the requirements. Table 2-180  Recommended Tie-Off Values for the TCK and TRST Pins VJTAG Tie-Off Resistance2, 3 VJTAG at 3.3 V 200 Ω to 1 kΩ VJTAG at 2.5 V 200 Ω to 1 kΩ VJTAG at 1.8 V 500 Ω to 1 kΩ VJTAG at 1.5 V 500 Ω to 1 kΩ Notes: 1. Equivalent parallel resistance if mo re than one device is on JTAG chain. 2. The TCK pin can be pulled up/down. 3. The TRST pin can only be pulled down.

2-222 Preliminary v1.7 Special Function Pins NC No Connect This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. DC Don't Connect This pin should not be connected to any signals on the PCB. These pins should be left unconnected. NCAP Negative Capacitor Negative Capacitor is where the negative terminal of the charge pump capacitor is connected. A capacitor, with a 2.2 µF recommended value, is required to connect between PCAP and NCAP. PCAP Positive Capacitor Positive Capacitor is where the positi ve terminal of the charge pump capacitor is connected. A capacitor, with a 2.2 µF recommended value, is required to connect between PCAP and NCAP. PUB Push Button Push button is the connection for the external momentary switch used to turn on the 1.5 V voltage regulator and can be floating if not used. PTBASE Pass Transistor Base Pass Transistor Base is the control signal of the voltage regulator. This pin should be connected to the base of the external pass transistor used with the 1.5 V internal voltage regulator and can be floating if not used. PTEM Pass Transistor Emitter Pass Transistor Emitter is the feedback input of the voltage regulator. This pin should be connected to the emitter of the external pass transistor used with the 1.5 V internal voltage regulator and can be floating if not used. XTAL1 Crystal Oscillator Circuit Input Input to crystal oscillator circuit. Pin for connecting external crystal, ceramic resonator, RC network, or external clock input. When using an external crystal or ceramic oscillator, external capacitors are also recommended (Please refer to the crystal oscillator manufacturer for proper capacitor value). If using external RC network or clock input, XTAL1 should be used and XTAL2 left unconnected. XTAL2 Crystal Oscillator Circuit Input Input to crystal oscillator circuit. Pin for connecting external crystal, ceramic resonator, RC network, or external clock input. When using an external crystal or ceramic oscillator, external capacitors are also recommended (Please refer to the crystal oscillator manufacturer for proper capacitor value). If using external RC network or clock input, XTAL1 should be used and XTAL2 left unconnected. Software Tools and Programming Overview of Tools Flow The Fusion family of FPGAs is fully supported by both Actel Libero IDE and Designer FPGA development software. Actel Libero IDE is an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment (see the Libero IDE flow diagram located on the Actel website). Libero IDE includes Synplify ® AE from Synplicity,® ViewDraw® AE from Mentor Graphics, ® ModelSim® HDL Simulator from Mentor Graphics, WaveFormer Lite™ AE from SynaptiCAD, ® PALACE™ AE Physical Synthesis from Magma Design Automation,™ and De signer software from Actel.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-223 Actel Designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for FPGA development. The Designer software includes the following:  SmartTime – a world-class integrated stati c timing analyzer and constraints editor that supports timing-driven place-and-route  NetlistViewer – a design netlist schematic viewer  ChipPlanner – a graphical floorplanning viewer and editor  SmartPower – a sophisticated power analysis en vironment that gives designers the ability to quickly determine the power consumption of an FPGA or its components  PinEditor – a graphical ap plication for editing pin assignments and I/O attributes  I/O Attribute Editor – displays all assigned and unassigned I/O macros and their attributes in a spreadsheet format With the Designer software, a user can lock th e design pins before layout while minimally impacting the results of place-and-route. Ad ditionally, the Actel back-annotation flow is compatible with all major simu lators. Included in the Designer software is SmartGen core generator, which easily creates commonly used logic function s for implementation into your Fusion-based schematic or HDL design. Actel Designer software is compatible with the most popular FPGA design entry and verification tools from EDA vendors, such as Cadence, ® Magma,® Mentor Graphics, Synopsys, and Synplicity. The Designer software is available for both the Windows® and UNIX operating systems. CoreMP7 and Cortex-M1 Software Tools CoreConsole is the Intellectual Property Deployment Platform (I DP) that assists the developer in programming the soft ARM core onto M7 (CoreMP7) and M1 (Cortex-M1) Fusion devices. CoreConsole provides the seamless environment to work with the Libero IDE and Designer FPGA development software tools concurrently. Security Fusion devices have a built-in 128-bit AES decryption core. The decryption core facilitates secure, in- system programming of the FPGA core array fabric and the FlashROM. The FlashROM and the FPGA core fabric can be programmed independently from each other, allowing the FlashROM to be updated without the need for change to the FPGA core fabric. The AES master key is stored in on- chip nonvolatile memory (flash). The AES master key can be preloaded into parts in a secure programming environment (such as the Actel in-house programming center), and then "blank" parts can be shipped to an un trusted programming or manufacturing center for final personalization with an AES-encrypted bitstream. Late stage product changes or personalization can be implemented easily and securely by simply sending a STAPL file wi th AES-encrypted data. Secure remote field updates over public networks (such as the Internet) are possible by sending and programming a STAPL file with AES-encrypted data. For more information, refer to the Fusion Security application note. 128-Bit AES Decryption The 128-bit AES standard (FIPS-1 92) block cipher is the Nation al Institute of Standards and Technology (NIST) replacement for DES (Data Encryption Stan dard FIPS46-2). AES has been designed to protect sensitive go vernment information well into th e 21st century. It replaces the aging DES, which NIST adopted in 1977 as a Federal Inform ation Processing Standard used by federal agencies to protect sensitive, unclassi fied information. The 128-bit AES standard has 3.4 × 1038 possible 128-bit key variants, and it has been estimated that it would take 1,000 trillion years to crack 128-bit AES cipher text using exhau stive techniques. Keys are stored (securely) in Fusion devices in nonvolatile flash memory. All programming files sent to the device can be authenticated by the part prior to programming to ensure that bad programming data is not loaded into the part that may possibly damage it. All programmi ng verification is performed on- chip, ensuring that the contents of Fusion devices remain secure.

2-224 Preliminary v1.7 AES decryption can also be used on the 1,024-bit FlashROM to allow for secure remote updates of the FlashROM contents. Th is allows for easy, secure support for subscription mo del products. See the application note Fusion Security for more details. AES for Flash Memory AES decryption can also be used on the flash memory blocks. This allows for the secure update of the flash memory blocks. During runtime, the encrypted data can be clocked in via the JTAG interface. The data can be passed through the in ternal AES decryption engine, and the decrypted data can then be stored in the flash memory block. Programming Programming can be performed using various programming to ols, such as Silicon Sculptor II (BP Micro Systems) or FlashPro3 (Actel). The user can generate STP programming files from the Designer software and can use these files to program a device. Fusion devices can be programmed in-system. During programming, V CCOSC is needed in order to power the internal 100 MHz oscillator . This oscillator is used as a source for the 20 MHz oscillator that is used to drive the charge pump for programming. ISP Fusion devices support IEEE 1532 ISP via JTAG and require a single V PUMP voltage of 3.3 V during programming. In addition, programming via a microc ontroller in a target system can be achieved. Refer to the standard or the In-System Programming (ISP) of Actel's Low-Power Flash Devices Using FlashPro3 document for more details. JTAG IEEE 1532 Programming with IEEE 1532 Fusion devices support the JTAG-based IEEE1532 standar d for ISP. As part of this support, when a Fusion device is in an unprogrammed state, all user I/O pins are disabl ed. This is achieved by keeping the global IO_EN signal d eactivated, which also has the effect of disabling the input buffers. Consequently, the SAMPLE instruction will have no effect while the Fusion device is in this unprogrammed state—different beha vior from that of the ProASICPLUS® device family. This is done because SAMPLE is defined in the IEEE1532 specific ation as a noninvasive in struction. If the input buffers were to be enabled by SAMPLE temporarily turning on the I/Os, then it would not truly be a noninvasive instruction. Refer to the standard or the In-System Programming (ISP) of Actel's Low- Power Flash Devices Using FlashPro3 document for more details. Boundary Scan Fusion devices are compatible wi th IEEE Standard 1149.1, which defines a hardware architecture and the set of mechanisms for boundary scan testing. The basic Fusion boundary scan logic circuit is composed of the test access port (TAP) controller, test data regi sters, and instruction register (Figure 2-138 on page 2-226). This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/PRELOAD, and BYPASS) and the optional IDCODE instruction (Table 2-182 on page 2-226). Each test section is accessed through the TAP, which has five associated pins: TCK (test clock input), TDI, TDO (test data input and output), TMS (test mo de selector), and TRST (test reset input). TMS, TDI, and TRST are equipped with pull-up resistors to ensure proper operation when no input data is supplied to them. These pins are dedicated for boundary scan test usage. Refer to the "JTAG Pins" section on page 2-221 for pull-up/-down recommendations for TDO and TCK pins. The TAP controller is a 4-bit state machine (16 states) that operates as shown in Figure 2-138 on page 2-226. The 1s and 0s represent the values that must be present on TM S at a rising edge of TCK for the

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-225 given state transition to occur. IR and DR indicate that the instruction register or the data register is operating in that state. The TAP controller receives two control inputs (TMS and TCK) and gene rates control and clock signals for the rest of the test lo gic architecture. On power-up, th e TAP controller enters the Test- Logic-Reset state. To guarantee a reset of the controller from any of the possible states, TMS must remain HIGH for five TCK cycles. The TRST pin can also be us ed to asynchronously place the TAP controller in the Test-Logic-Reset state. Fusion devices support three types of test data registers: bypass, devi ce identification, and boundary scan. The bypass register is selected when no other regi ster needs to be accessed in a device. This speeds up test data transfer to othe r devices in a test data path. The 32-bit device identification register is a shift register with four fields (LSB, ID number, part number, and version). The boundary scan register observes and controls th e state of each I/O pin. Each I/O cell has three boundary scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pin. The serial pins are used to serial ly connect all the boundary scan register cells in a device into a boundary scan register chain, wh ich starts at the TDI pin and ends at the TDO pin. The parallel ports are connected to the internal core logic I/O tile and the input, output, and control ports of an I/O buffer to capture and load data into the regi ster to control or observe the logic state of each I/O. Table 2-181  TRST and TCK Pull-Down Recommendations VJTAG Tie-Off Resistance* VJTAG at 3.3 V 200 Ω to 1 kΩ VJTAG at 2.5 V 200 Ω to 1 kΩ VJTAG at 1.8 V 500 Ω to 1 kΩ VJTAG at 1.5 V 500 Ω to 1 kΩ Note: *Equivalent parallel resistance if more than one device is on JTAG chain.

2-226 Preliminary v1.7 Figure 2-138  Boundary Scan Chain in Fusion Table 2-182  Boundary Scan Opcodes Hex Opcode EXTEST 00 HIGHZ 07 USERCODE 0E SAMPLE/PRELOAD 01 IDCODE 0F CLAMP 05 BYPASS FF Device Logic TDI TCK TMS TRST TDO I/OI/OI/O I/O I/O I/OI/OI/O I/O I/O I/O I/O I/O I/O Bypass Register Instruction Register TAP Controller Test Data Registers

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-227 IEEE 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/Os" section on page 2-130 for more details. Timing Characteristics Table 2-183  JTAG 1532 Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. Units tDISU Test Data Input Setup Time 0.50 0.57 0.67 ns tDIHD Test Data Input Hold Time 1.00 1.13 1.33 ns tTMSSU Test Mode Select Setup Time 0.50 0.57 0.67 ns tTMDHD Test Mode Select Hold Time 1.00 1.13 1.33 ns tTCK2Q Clock to Q (data out) 6.00 6.80 8.00 ns tRSTB2Q Reset to Q (data out) 20.00 22.67 26.67 ns FTCKMAX TCK Maximum Frequency 25.00 22.00 19.00 MHz tTRSTREM ResetB Removal Time 0.00 0.00 0.00 ns tTRSTREC ResetB Recovery Time 0.20 0.23 0.27 ns tTRSTMPW ResetB Minimum Pulse TBD TBD TBD ns Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.

2-228 Preliminary v1.7 Part Number and Revision Date Part Number 51700092-014-0 Revised October 2008 List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Curr ent Version (Preliminary v1.7) Page Advance v1.6 (August 2008) The version number category was changed from Advance to Preliminary, which means the datasheet contains informatio n based on simulation and/or initial characterization. The information is be lieved to be correct, but changes are possible. N/A The following updates were made to Table 2-38 Temperature Data Format: Temperature Digital Output 213 00 1111 1101 283 01 0001 1011 358 01 0110 0110 – only the digital output was updated. Temperature 358 remains in the temperature column. 2-98 In Advance v1.2, the "V AREF Analog Reference Voltage" pin description was significantly updated but the change was not noted in the change table. 2-220 Advance v1.5 (July 2008) The references to the Peripherals User’s Guide in the "No-Glitch MUX (NGMUX)" section and "Voltage Regulator Power Supply Monitor (VRPSM)" section were changed to Fusion Handbook. 2-32, 2-40 Advance v1.4 (July 2008) The title of the datasheet changed fr om Actel Programmable System Chips to Actel Fusion Mixed- Signal FPGAs. In addition, all instances of programmable system chip were changed to mixed-signal FPGA. N/A Advance v1.2 (June 2008) The "ADC Description" section was significantly updated. Please review carefully. 2-103 Advance v1.1 (May 2008) Table 2-25 · Flash Memory Block Timing was significantly updated. 2-54 The "VAREF Analog Reference Voltage" pin description section was significantly update. Please review it carefully. 2-220 Table 2-45 · ADC Interface Timingwas significantly updated. 2-109 Table 2-56 · Direct Analog Input Switch Control Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3) was significantly updated. 2-128 The following sentence was deleted from the "Voltage Monitor" section: The Analog Quad inputs are tolerant up to 12 V + 10%. 2-86 Advance v1.0 (January 2008) The following text was incorrect and therefore deleted: VCC33A Analog Power Filter Analog power pin for the analog power supply low-pass filter. An external 100 pF capacitor should be connected between this pin and ground. There is still a description of V CC33A on page 2-218. 2-204 Advance v0.9 (October 2007) All Timing Characteristics tables were updated. For the Differential I/O Standards, the Standard I/O support tables are new. N/A Table 2-3 · Array Coordinates was updated to change the max x and y values 2-9 T a b l e2 - 1 3·F u s i o n C CC/PLL Specification was updated. 2-31

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 2-229 Advance v0.9 (continued) A note was added to T a b l e2 - 1 6·R T C A C M M e m o r y M a p. 2-36 A reference to the Peripheral’s User’s Guide was added to the "Voltage Regulator Power Supply Monitor (VRPSM)" section. 2-40 In Table 2-25 · Flash Memory Block Timing , the commercial conditions were updated. 2-54 In Table 2-26 · FlashROM Access Time, the commercial conditions were missing and have been added below the title of the table. 2-57 In Table 2-36 · Analog Block Pin Description , the function description was updated for the ADCRESET. 2-82 In the "Voltage Monitor" section, the following sentence originally had ± 10% and it was changed to +10%. The Analog Quad inputs are tolerant up to 12 V + 10%. In addition, this statement was deleted from the datasheet: Each I/O will draw power when connected to power (3 mA at 3 V). 2-86 The "Terminology" section is new. 2-88 The "Current Monitor" section was significantly updated. Figure 2-71 · Timing Diagram for Current Monitor Strobe to Figure 2-73 · Negative Current Monitor and Table 2-37 · Recommended Resistor for Different Current Range Measurement are new. 2-90 The "ADC Description" section was updated to add the "Terminology" section. 2-93 In the "Gate Driver" section , 25 mA was changed to 20 mA and 1.5 MHz was changed to 1.3 MHz. In addition, the following sentence was deleted: The maximum AG pad switching frequency is 1.25 MHz. 2-94 The "Temperature Monitor" section was updated to rewrite most of the text and add Figure 2-77, Figure 2-78, and Figure 2-38 · Temperature Data Format. 2-96 In Table 2-38 · Temperature Data Format , the temperature K column was changed for 85°C from 538 to 358. 2-98 In Table 2-45 · ADC Interface Timing , "Typical-Case" was changed to "Worst- Case." 2-109 The "ADC Interface Timing" section is new. 2-109 Table 2-46 · Analog Channel Specifications was updated. 2-115 The "VCC15A Analog Power Supply (1.5 V)" section was updated. 2-218 The "VCCPLA/B PLL Supply Voltage" section is new. 2-219 In "VCCNVM Flash Memory Block Power Supply (1.5 V)" section , supply was changed to supply input. 2-218 The "VCCPLA/B PLL Supply Voltage" pin description was updated to include the following statement: Actel recommends tying V CCPLX to V CC and using proper filtering circuits to decouple VCC noise from PLL. 2-219 The "VCOMPLA/B Ground for West and East PLL" section was updated. 2-219 In T a b l e2 - 4 7·A D C C h a r a c t e r i s tics in Direct Input Mode , the commercial conditions were updated and note 2 is new. 2-118 The V CC33ACAP signal name was changed to "XTAL1 Crystal Oscillator Circuit Input". 2-222 Previous Version Changes in Curr ent Version (Preliminary v1.7) Page

2-232 Preliminary v1.7 Advance v0.7 (continued) Table 2-75 · Fusion Standard I/O Standards—OUT_DRIVE Settings was updated. 2-151 The "GNDA Ground (analog)" section and "GNDAQ Ground (analog quiet)" section were updated to add information about maximum differential voltage. 2-218 The "VAREF Analog Reference Voltage" section and "VPUMP Programming Supply Voltage" section were updated. 2-220 The "VCCPLA/B PLL Supply Voltage" section was updated to include information about the east and west PLLs. 2-219 The VCOMPLF pin description was deleted. N/A The "Axy Analog Input/Output" section was updated with information about grounding and floating the pin. 2-220 The voltage range in the "VPUMP Programming Supply Voltage" section was updated. The parenthetical reference to "pulled up" was removed from the statement, " VPUMP can be left floating or can be tied (pulled up) to any voltage between 0 V and 3.6 V." 2-219 The "ATRTNx Temperature Monitor Return" section was updated with information about grounding and floating the pin. 2-220 The following text was deleted from the "VREF I/O Voltage Reference" section: (all digital I/O). 2-219 The "NCAP Negative Capacitor" section and "PCAP Positive Capacitor" section were updated to include information about the type of capacitor that is required to connect the two. 2-222 1 µF was changed to 100 pF in the "XTAL1 Crystal Oscillator Circuit Input". 2-222 The "Programming" section was updated to include information about VCCOSC. 2-224 Advance v0.5 (June 2006) The second paragraph of the "PLL Macro" section was updated to include information about POWERDOWN. 2-30 The description for bit 0 was updated in Table 2-17 · RTC Control/Status Register. 2-37 3.9 was changed to 7.8 in the "Crystal Oscillator (Xtal Osc)" section. 2-38. All function descriptions in Table 2-18 · Signals for VRPSM Macro. 2-40 In Table 2-19 · Flash Memory Block Pin Names , the RD[31:0] description was updated. 2-42 The "RESET" section was updated. 2-61 The "RESET" section was updated. 2-64 T a b l e2 - 3 5·F I F O was updated. 2-79 The VAREF function description was updated in T a b l e2 - 3 6·A n a l o g B l o c k P i n Description. 2-82 The "Voltage Monitor" section was updated to include information about low power mode and sleep mode. 2-86 The text in the "Current Monitor" section was changed from 2 mV to 1 mV. 2-90 The "Gate Driver" section was updated to include information about forcing 1 V on the drain. 2-94 The "Analog-to-Digital Converter Block" section was updated with the following statement: "All results are MSB justified in the ADC." 2-100 Previous Version Changes in Curr ent Version (Preliminary v1.7) Page

Preliminary v1.7 3-1 3 – DC and Power Characteristics General Specifications DC and switching characteristics for –F speed grade targets are based only on simulation. The characteristics prov ided for –F speed grade are subject to change after establishing FPGA specifications. Some restri ctions might be added and will be re flected in future revisions of this document. The –F speed grade is only supported in the commercial temperature range. Operating Conditions Stresses beyond those listed in Table 3-1 may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the recommended operating ranges specified in Table 3-2 on page 3-3. Table 3-1  Absolute Maximum Ratings Symbol Parameter Commercial Industrial Units VCC DC core supply voltage –0. 3 to 1.65 –0.3 to 1.65 V VJTAG JTAG DC voltage –0.3 to 3.75 –0.3 to 3.75 V VPUMP Programming voltage –0.3 to 3.75 –0.3 to 3.75 V VCCPLL Analog power supply (PLL) –0.3 to 1.65 –0.3 to 1.65 V VCCI DC I/O output buffer supply voltage –0.3 to 3.75 –0.3 to 3.75 V VI I/O input voltage 1 –0.3 V to 3.6 V (when I/O hot insertion mode is enabled) –0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when I/O hot-insertion mode is disabled) V VAREF Voltage reference for ADC –0.3 to 3.75 –0.3 to 3.75 V VCC15A Digital power supply for the analog system –0.3 to 1.65 –0.3 to 1.65 V VCCNVM Embedded flash power supply –0 .3 to 1.65 –0.3 to 1.65 V VCCOSC Oscillator power supply –0.3 to 3.75 –0.3 to 3.75 V AV, AC Unpowered, ADC reset asserted or unconfigured –11.0 to 12.6 –11.0 to 12.4 V Analog input (+16 V to +2 V prescaler range) –0.4 to 12.6 –0.4 to 12.4 V Analog input (+1 V to +0.125 V prescaler range) –0.4 to 3.75 –0.4 to 3.75 V Notes: 1. The device should be operated within the limits sp ecified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 3-4 on page 3-4. 2. Analog data not valid beyond 3.65 V. 3. For flash programming and rete ntion maximum limits, refer to Table 3-5 on page 3-5. For recommended operating limits refer to Table 3-2 on page 3-3.

DC and Power Characteristics 3-2 Preliminary v1.7 Analog input (–16 V to –2 V prescaler range) –11.0 to 0.4 –11.0 to 0.4 V Analog input (–1 V to –0.125 V prescaler range) –3.75 to 0.4 –3.75 to 0.4 V Analog input (direct input to ADC) –0.4 to 3.75 –0.4 to 3.75 V Digital input –0.4 to 12.6 –0.4 to 12.4 V AG Unpowered, ADC reset asserted or unconfigured –11.0 to 12.6 –11.0 to 12.4 V Low Current Mode (1 µA, 3 µA, 10 µA, 30 µA) –0.4 to 12.6 –0.4 to 12.4 V Low Current Mode (–1 µA , –3 µA, –10 µA, –30 µA) –11.0 to 0.4 –11.0 to 0.4 V High Current Mode3 –11.0 to 12.6 –11.0 to 12.4 V AT Unpowered, ADC reset asserted or unconfigured –0.4 to 16.5 –0.4 to 16.0 V Analog input (+16 V, 4 V prescaler range) –0.4 to 16.5 –0.4 to 16.0 V Analog input (direct input to ADC) –0.4 to 3.75 –0.4 to 3.75 V Digital input –0.4 to 16.5 –0.4 to 16.0 V TSTG

3 Storage temperature –65 to +150 °C

3 Junction temperature +125 °C

Table 3-1  Absolute Maximum Ratings (continued) Symbol Parameter Commercial Industrial Units Notes: 1. The device should be operated within the limits sp ecified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 3-4 on page 3-4. 2. Analog data not valid beyond 3.65 V. 3. For flash programming and rete ntion maximum limits, refer to Table 3-5 on page 3-5. For recommended operating limits refer to Table 3-2 on page 3-3.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 3-3 Table 3-2  Recommended Operating Conditions Symbol Parameter Commercial Industrial Units TA,TJ Ambient and junction temperature 0 to +70 –40 to +85 °C VJTAG JTAG DC voltage 1.4 to 3.6 1.4 to 3.6 V VPUMP Programming voltage Programming mode 3.15 to 3.45 3.15 to 3.45 V Operation3 0 to 3.6 0 to 3.6 V VCCPLL Analog power supply (PLL) 1.4 25 to 1.575 1.425 to 1.575 V LVDS differential I/O 2.375 to 2.625 2.375 to 2.625 V LVPECL differential I/O 3.0 to 3.6 3.0 to 3.6 V V VAREF Voltage reference for ADC 2.527 to 2.593 2.527 to 2.593 V V CC15A 6 Digital power supply for the analog system 1.425 to 1.575 1.425 to 1.575 V VCCNVM Embedded flash power supply 1. 425 to 1.575 1.425 to 1.575 V VCCOSC Oscillator power supply 2. 97 to 3.63 2.97 to 3.63 V AV, AC4 Unpowered, ADC reset asserted or unconfigured –10.5 to 12.0 –10.5 to 12.0 V Analog input (+16 V to +2 V prescaler range) –0.3 to 12.0 –0.3 to 12.0 V Analog input (–16 V to –2 V prescaler range) –10.5 to 0.3 –10.5 to 0.3 V Analog input (direct input to ADC) –0.3 to 3.6 –0.3 to 3.6 V Digital input –0.3 to 12.0 –0.3 to 12.0 V AG 4 Unpowered, ADC reset asserted or unconfigured –10.5 to 12.0 –10.5 to 12.0 V Low Current Mode (1 µA, 3 µA, 10 µA, 30 µA) –0.3 to 12.0 –0.3 to 12.0 V Low Current Mode (–1 µA, –3 µA, –10 µA, –30 µA) –10.5 to 0.3 –10.5 to 0.3 V High Current Mode5 –10.5 to 12.0 –10.5 to 12.0 V AT4 Unpowered, ADC reset asserted or unconfigured –0.3 to 16.0 –0.3 to 15.5 V Analog input (+16 V, +4 V prescaler range) –0.3 to 16.0 –0.3 to 15.5 V Analog input (direct input to ADC) –0.3 to 3.6 –0.3 to 3.6 V Digital input –0.3 to 16.0 –0.3 to 15.5 V Notes: 1. The ranges given here are for powe r supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-81 on page 2-154. 2. All parameters representing voltages are measured with respect to GND unless otherwise specified. 3. V PUMP can be left floating during normal operation (not programming mode). 4. The input voltage may overshoot by up to 500 mV above the Recommended Ma ximum (150 mV in Direct mode), provided the duration of the overshoot is less than 50% of the operating lifetime of the device. 5. The AG pad should also conform to the limits as specified in Table 2-45 on page 2-109. 6. Violating the V CC15A recommended voltage supply during an embedded flash program cycle can corrupt the page being programmed.

DC and Power Characteristics 3-4 Preliminary v1.7 Table 3-3  Input Resistance of Analog Pads Pads Pad Configuration Prescaler Range Input Resistance to Ground AV, AC Analog Input (direct in put to ADC) +16 V to +2 V 1 M Ω (typical) +1 V to +0.125 V > 10 M Ω Analog Input (positive prescaler) +16 V to +2 V 1 M Ω (typical) +1 V to +0.125 V > 10 M Ω Analog Input (negative prescaler) –16 V to –2 V 1 M Ω (typical) –1 V to –0.125 V > 10 M Ω Digital input +16 V to +2 V 1 M Ω (typical) Current monitor +16 V to +2 V 1 M Ω (typical) –16 V to –2 V 1 M Ω (typical) AT Analog Input (direct inpu t to ADC) +16 V, +4 V 1 M Ω (typical) Analog Input (positive prescaler) +16 V, +4 V 1 M Ω (typical) Digital input +16 V, +4 V 1 M Ω (typical) Temperature monitor +16 V, +4 V > 10 M Ω Table 3-4  Overshoot and Undershoot Limits 1 VCCI Average VCCI–GND Overshoot or Undershoot Duration as a Percentage of Clock Cycle2 Maximum Overshoot/ Undershoot2 2.7 V or less 10% 1.4 V 5% 1.49 V 3.0 V 10% 1.1 V 5% 1.19 V 3.3 V 10% 0.79 V 5% 0.88 V 3.6 V 10% 0.45 V 5% 0.54 V Notes: 1. Based on reliability requirements at 85°C. 2. The duration is allowed at one cycle out of six clock cycle. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 3-5 I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial) Sophisticated power-up management circuitry is designed into ev ery Fusion device. These circuits ensure easy transition from the powered off state to the powered up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 3-1 on page 3-6. There are five regions to consider during power-up. Fusion I/Os are activated only if ALL of the following three conditions are met: 1. V CC and VCCI are above the minimum specified trip points (Figure 3-1). 2. V CCI > VCC – 0.75 V (typical). 3. Chip is in the operating mode. VCCI Trip Point: Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V VCC Trip Point: Ramping up: 0.6 V < trip_point_up < 1.1 V Ramping down: 0.5 V < trip_point_down < 1 V VCC and V CCI ramp-up trip points are about 100 mV hi gher than ramp-dow n trip points. This specifically built-in hysteresis pr events undesirable power-up oscillations and current surges. Note the following:  During programming, I/Os become tri stated and weakly pulled up to VCCI.  JTAG supply, PLL power supplies, and charge pump V PUMP supply have no influence on I/O behavior. Internal Power-Up Activation Sequence 1. Core 2. Input buffers 3. Output buffers, after 200 ns de lay from input buffer activation Table 3-5  FPGA Programming, Storage, and Operating Limits Product Grade Element Grade Programming Cycles Retention Storage Temperature (°C) Minimum Maximum Commercial FPGA/FlashROM 500 20 years 2 08 5 Embedded Flash 1 k 20 years 2 08 5 15 k 5 years 2 08 5 Industrial FPGA/FlashROM 500 20 years –40 85 Embedded Flash 1 k 20 years –40 85 15 k 5 years –40 85 Notes: 1. This is a stress rating only. Function al operation at any condition other than those indicated is not implied. 2. If the embedded flash has been programmed less than 1 k times, every time it is programmed, the data will hold for 20 years. If the embedde d flash has been programmed more than 1 k times but less than 15 k times, every time it is programmed, the data will hold for 5 years.

DC and Power Characteristics 3-6 Preliminary v1.7 PLL Behavior at Brownout Condition Actel recommends using monotonic power supplies or voltage regulators to ensure proper power- up behavior. Power ramp-up should be monotonic at least until V CC and VCCPLX exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 3-1 on page 3-6 for more details). When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25 V), the PLL outp ut lock signal goes low and/or the output clock is lost. Refer to the Power- Up/Down of Fusion FPGAs application note for information on clock and lock recovery. Figure 3-1  I/O State as a Function of VCCI and VCC Voltage Levels Region 1: I/O buffers are OFF Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because V CCI/VCC are below specification. For the same reason, input buffers do not meet V IH/VIL levels, and output buffers do not meet VOH/VOL levels. Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V VCC VCC = 1.425 V Region 1: I/O Buffers are OFF Activation trip point: Va = 0.85 V ± 0.25 V Deactivation trip point: Vd = 0.75 V ± 0.25 V Activation trip point: Va = 0.9 V ±0.3 V Deactivation trip point: Vd = 0.8 V ± 0.3 V VCC = 1.575 V Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH/VIL , VOH /VOL , etc. Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because V CCI is below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC = VCCI + VT VCCI Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 3-7 Thermal Characteristics Introduction The temperature variable in the Actel Designer software refers to the junction temperature, not the ambient, case, or board temperatures. This is an important distinction because dynamic and static power consumption will cause the chip's ju nction temperature to be higher than the ambient, case, or board temperatures. EQ 3-1 through EQ 3-3 give the relationship between thermal resistance, temperature gradient, and power. EQ 3-1 EQ 3-2 EQ 3-3 where θJA = Junction-to-air thermal resistance θJB = Junction-to-board thermal resistance θJC = Junction-to-case thermal resistance TJ = Junction temperature TA = Ambient temperature TB = Board temperature (measured 1.0 mm away from the package edge) TC = Case temperature P = Total power dissipated by the device θJA TJ θA– θJB TJ TB– θJC TJ TC– Table 3-6  Package Thermal Resistance Product θJA θJC θJB UnitsStill Air 1.0 m/s 2.5 m/s AFS090-QN108 TBD TBD TBD TBD TBD °C/W AFS090-QN180 TBD TBD TBD TBD TBD °C/W AFS250-QN180 TBD TBD TBD TBD TBD °C/W AFS250-PQ208 TBD TBD TBD TBD TBD °C/W AFS600-PQ208 TBD TBD TBD TBD TBD °C/W AFS1500-FG676 TBD TBD TBD TBD TBD °C/W

DC and Power Characteristics 3-8 Preliminary v1.7 Theta-JA Junction-to-ambient thermal resistance (θJA) is determined under standar d conditions specified by JEDEC (JESD-51), but it has little relevance in actual performance of the product. It should be used with caution but is useful for comparing the thermal performance of one package to another. A sample calculation showing the maximum power di ssipation allowed for the AFS600-FG484 package under forced convection of 1.0 m/s and 75°C ambient temperature is as follows: EQ 3-4 where The power consumption of a device can be calculated using the Actel power calculator. The device's power consumption must be lower than the calculated maximum power dissipation by the package. If the power consumption is higher than the device's ma ximum allowable power dissipation, a heat sink can be attached on top of the case, or the airflow inside the system must be increased. Theta-JB Junction-to-board th ermal resistance ( θJB) measures the ability of th e package to dissipate heat from the surface of the chip to the PCB. As defined by the JEDE C (JESD-51) standard, the thermal resistance from junction to board uses an isothe rmal ring cold plate zone concept. The ring cold plate is simply a means to generate an isothe rmal boundary condition at the perimeter. The cold plate is mounted on a JEDEC standard board with a minimum distance of 5.0 mm away from the package edge. Theta-JC Junction-to-case thermal resistance (θJC) measures the ability of a device to dissipate heat from the surface of the chip to the top or bottom surface of the package. It is appl icable for packages used with external heat sinks. Constant temperature is applied to the surface in consideration and acts as a boundary condition. This only applies to si tuations where all or n early all of the heat is dissipated through the surface in consideration. Calculation for Heat Sink For example, in a design implemented in an AFS600-FG484 package with 2.5 m/s airflow, the power consumption value using the power calculator is 3.00 W. The user-dependent Ta and Tj are given as follows: From the datasheet: EQ 3-5 θJA = 19.00°C/W (taken from Table 3-6 on page 3-7). TA = 75.00°C TJ = 110.00°C TA = 70.00°C θJA = 17.00°C/W θJC = 8.28°C/W Maximum Power Allowed TJ(MAX) TA(MAX)– θJA Maximum Power Allowed 110.00°C 75.00°C– P TJ TA– θJA

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 3-9 The 2.35 W power is less than the required 3.00 W. The design therefore requires a heat sink, or the airflow where the device is mounted should be increased. The design's total junction-to-air thermal resistance requirement can be estimated by EQ 3-6: EQ 3-6 Determining the heat sink's thermal performance proceeds as follows: EQ 3-7 where EQ 3-8 A heat sink with a thermal resist ance of 5.01°C/W or better shou ld be used. Thermal resistance of heat sinks is a function of airflow. The heat si nk performance can be significantly improved with increased airflow. Carefully estimating thermal resistance is importan t in the long-term reliab ility of an Actel FPGA. Design engineers should always correlate the power consumption of the device with the maximum allowable power dissipation of the package selected for that device. Note: The junction-to-air and junction-to-board thermal resistances are based on JEDEC standard (JESD-51) and assumptions made in building the model. It may not be realized in actual application and therefore should be used with a degree of caution. Junction-to- case thermal resistance assumes that all power is dissipated through the case. Temperature and Voltage Derating Factors θJA = 0.37°C/W = Thermal resistance of the interface material between the case and the heat sink, usually provided by the thermal interface manufacturer θSA = Thermal resistance of the heat sink in °C/W Table 3-7  Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.425 V) Array Voltage VCC (V) Junction Temperature (°C) –40°C 0°C 25°C 70°C 85°C 110°C θja(total) TJ TA– θJA(TOTAL) θJC θCS θSA++= θSA θJA(TOTAL) θJC– θCS–= θSA 13.33°C/W 8.28°C/W– 0.37°C/W– 5.01°C/W==

DC and Power Characteristics 3-10 Preliminary v1.7 Calculating Power Dissipation Quiescent Supply Current Table 3-8  Quiescent Supply Current Characteristics (IDDQ)1 Parameter Conditions and Modes AFS090 AFS250 AFS600 AFS1500 IDC1 Maximum in operating mode (85°C) 2 15 mA 30 mA 45 mA TBD Maximum in operating mode (70°C) 2 10 mA 20 mA 30 mA TBD Typical in operating mode (25°C) 2 2 mA 3 mA 5 mA TBD IDC2 Typical in standby mode (25°C) 3,5 200 µA 200 µA 200 µA TBD IDC3 Typical in sleep mode (25°C) 4,5 10 µA 10 µA 10 µA TBD Notes: 1. –F speed grade devices may experience higher Quiescent Supply current of up to five times the standard IDD, and higher I/O leakage. 2. I DC1 includes VCC, VPUMP, and VCCI, currents. Values do not include I/O static contribution, which is shown in Table 3-9 on page 3-11 and Table 3-10 on page 3-13. 3. I DC2 represents the current from the V CC33A and V CCI supplies when the RTC (and the 32 kHz crystal oscillator) is ON, the FPGA is OFF, and the voltage regulator is OFF. 4. I DC3 represents the current from the VCC33A and VCCI supplies when the RTC (and the crystal oscillator), the FPGA, and the voltage regulator are OFF. 5. V CCI supply is ON, since the east and west I/O banks are not cold-sparable. Values do not include I/O static contribution, which is shown in Table 3-9 on page 3-11 and Table 3-10 on page 3-13.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 3-11 Power per I/O Pin Table 3-9  Summary of I/O Input Buffer Power (per pin)—Default I/O Software Settings VCCI (V) Static Power PDC7 (mW)1 Dynamic Power PAC9 (µW/MHz)2 Applicable to Pro I/O Banks Single-Ended 3.3 V LVTTL/LVCMOS 3.3 – 17.39 3.3 V LVTTL/LVCMOS – Schmitt trigger 3.3 – 25.51 2.5 V LVCMOS 2.5 – 5.76 2.5 V LVCMOS – Schmitt trigger 2.5 – 7.16 1.8 V LVCMOS 1.8 – 2.72 1.8 V LVCMOS – Schmitt trigger 1.8 – 2.80 1.5 V LVCMOS (JESD8-11) 1.5 – 2.08 1.5 V LVCMOS (JESD8-11) – Schmitt trigger 1.5 – 2.00 3.3 V PCI 3.3 – 18.82 3.3 V PCI – Schmitt trigger 3.3 – 20.12 3.3 V PCI-X 3.3 – 18.82 3.3 V PCI-X – Schmitt trigger 3.3 – 20.12 Voltage-Referenced 3.3 V GTL 3.3 2.90 8.23 2.5 V GTL 2.5 2.13 4.78 3.3 V GTL+ 3.3 2.81 4.14 2.5 V GTL+ 2.5 2.57 3.71 HSTL (I) 1.5 0.17 2.03 HSTL (II) 1.5 0.17 2.03 SSTL2 (I) 2.5 1.38 4.48 SSTL2 (II) 2.5 1.38 4.48 SSTL3 (I) 3.3 3.21 9.26 SSTL3 (II) 3.3 3.21 9.26 Differential LVDS 2.5 2.26 1.50 LVPECL 3.3 5.71 2.17 Notes: 1. P DC7 is the static power (where applicable) measured on VCCI. 2. P AC9 is the total dynamic power measured on VCC and VCCI.

DC and Power Characteristics 3-12 Preliminary v1.7 Applicable to Advanced I/O Banks Single-Ended 3.3 V LVTTL/LVCMOS 3.3 – 16.69 2.5 V LVCMOS 2.5 – 5.12 1.8 V LVCMOS 1.8 – 2.13 1.5 V LVCMOS (JESD8-11) 1.5 – 1.45 3.3 V PCI 3.3 – 18.11 3.3 V PCI-X 3.3 – 18.11 Differential LVDS 2.5 2.26 1.20 LVPECL 3.3 5.72 1.87 Applicable to Standard I/O Banks 3.3 V LVTTL/LVCMOS 3.3 – 16.79 2.5 V LVCMOS 2.5 – 5.19 1.8 V LVCMOS 1.8 – 2.18 1.5 V LVCMOS (JESD8-11) 1.5 – 1.52 Table 3-9  Summary of I/O Input Buffer Power (per pin)—Default I/O Software Settings (continued) V CCI (V) Static Power PDC7 (mW)1 Dynamic Power PAC9 (µW/MHz)2 Notes: 1. P DC7 is the static power (where applicable) measured on VCCI. 2. P AC9 is the total dynamic power measured on VCC and VCCI.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 3-13 Table 3-10  Summary of I/O Output Buffer Power (per pin)—Default I/O Software Settings 1 CLOAD (pF) V CCI (V) Static Power PDC8 (mW)2 Dynamic Power PAC10 (µW/MHz)3 Applicable to Pro I/O Banks Single-Ended 3.3 V LVTTL/LVCMOS 35 3.3 – 474.70 2.5 V LVCMOS 35 2.5 – 270.73 1.8 V LVCMOS 35 1.8 – 151.78 1.5 V LVCMOS (JESD8-11) 35 1.5 – 104.55 3.3 V PCI 10 3.3 – 204.61 3.3 V PCI-X 10 3.3 – 204.61 Voltage-Referenced 3.3 V GTL 10 3.3 – 24.08 2.5 V GTL 10 2.5 – 13.52 3.3 V GTL+ 10 3.3 – 24.10 2.5 V GTL+ 10 2.5 – 13.54 HSTL (I) 20 1.5 7.08 26.22 HSTL (II) 20 1.5 13.88 27.22 SSTL2 (I) 30 2.5 16.69 105.56 SSTL2 (II) 30 2.5 25.91 116.60 SSTL3 (I) 30 3.3 26.02 114.87 SSTL3 (II) 30 3.3 42.21 131.76 Differential LVDS – 2.5 7.70 89.62 LVPECL – 3.3 19.42 168.02 Applicable to Advanced I/O Banks Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 – 468.67 2.5 V LVCMOS 35 2.5 – 267.48 1.8 V LVCMOS 35 1.8 – 149.46 1.5 V LVCMOS (JESD8-11) 35 1.5 – 103.12 3.3 V PCI 10 3.3 – 201.02 3.3 V PCI-X 10 3.3 – 201.02 Notes: 1. Dynamic power consumption is given for standard load and software-default drive strength and output slew. 2. P DC8 is the static power (where applicable) measured on VCCI. 3. P AC10 is the total dynamic power measured on VCC and VCCI.

DC and Power Characteristics 3-14 Preliminary v1.7 Differential LVDS – 2.5 7.74 88.92 LVPECL – 3.3 19.54 166.52 Applicable to Standard I/O Banks Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 – 431.08 2.5 V LVCMOS 35 2.5 – 247.36 1.8 V LVCMOS 35 1.8 – 128.46 1.5 V LVCMOS (JESD8-11) 35 1.5 – 89.46 Table 3-10  Summary of I/O Output Buffer Power (per pin)—Default I/O Software Settings 1 (continued) CLOAD (pF) V CCI (V) Static Power PDC8 (mW)2 Dynamic Power PAC10 (µW/MHz)3 Notes: 1. Dynamic power consumption is given for standard load and software-default drive strength and output slew. 2. P DC8 is the static power (where applicable) measured on VCCI. 3. P AC10 is the total dynamic power measured on VCC and VCCI.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 3-15 Dynamic Power Consumption of Various Internal Resources Table 3-11  Different Components Contributing to the Dynamic Power Consumption in Fusion Devices Parameter Definition Power Supply Device-Specific Dynamic Contributions UnitsName Setting AFS1500 AFS600 AFS250 AFS090 PAC1 Clock contribution of a Global Rib VCC 1.5 V 14.5 12.8 11 11 µW/MHz PAC2 Clock contribution of a Global Spine PAC3 Clock contribution of a VersaTile row VCC 1.5 V 0.81 µW/MHz PAC4 Clock contribution of a VersaTile used as a sequential module VCC 1.5 V 0.11 µW/MHz PAC5 First contribution of a VersaTile used as a sequential module VCC 1.5 V 0.07 µW/MHz PAC6 Second contribution of a VersaTile used as a sequential module VCC 1.5 V 0.29 µW/MHz PAC7 Contribution of a VersaTile used as a combinatorial module VCC 1.5 V 0.29 µW/MHz PAC8 Average contribution of a routing net VCC 1.5 V 0.70 µW/MHz PAC9 Contribution of an I/O input pin (standard dependent) VMV/ VCC See Table 3-9 on page 3-11 PAC10 Contribution of an I/O output pin (standard dependent) VCCI/ VCC See Table 3-10 on page 3-13 PAC11 Average contribution of a RAM block during a read operation VCC 1.5 V 25 µW/MHz PAC12 Average contribution of a RAM block during a write operation VCC 1.5 V 30 µW/MHz PAC13 Dynamic Contribution for PLL V CC 1.5 V 2.6 µW/MHz PAC15 Contribution of NVM block during a read operation (F < 33MHz) VCC 1.5 V 358 µW/MHz PAC16 1st contribution of NVM block during a read operation (F > 33MHz) VCC 1.5 V 12.88 mW PAC17 2nd contribution of NVM block during a read operation (F > 33MHz) VCC 1.5 V 4.8 µW/MHz PAC18 Crystal Oscillator contribution V CC33A 3.3 V 0.63 mW PAC19 RC Oscillator contribution V CC33A 3.3 V 3.3 mW PAC20 Analog Block dynamic power contribution of ADC VCC 1.5 V 3 mW

DC and Power Characteristics 3-16 Preliminary v1.7 Static Power Consumption of Various Internal Resources Table 3-12  Different Components Contributing to the Static Power Consumption in Fusion Devices Parameter Definition Power Supply Device-Specific Static Contributions UnitsAFS1500 AFS600 AFS250 AFS090 PDC1 Core static power contribution in operating mode VCC 1.5 V TBD 7.5 4.50 3.00 mW PDC2 Device static power contribution in standby mode VCC33A 3.3 V 0.66 mW PDC3 Device static power contribution in sleep mode VCC33A 3.3 V 0.03 mW PDC4 NVM static power contribution V CC 1.5 V 1.19 mW PDC5 Analog Block static power contribution of ADC VCC33A 3.3 V 8.25 mW PDC6 Analog Block static power contribution per Quad VCC33A 3.3 V 3.3 mW PDC7 Static contribution per input pin – standard dependent contribution VMV/ VCC See Table 3-9 on page 3-11 PDC8 Static contribution per input pin – standard dependent contribution VMV/ VCC See Table 3-10 on page 3-13 PDC9 Static contribution for PLL V CC 1.5 V 2.55 mW

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 3-17 Power Calculation Methodology This section describes a simplified method to estimate power consumptio n of an application. For more accurate and detailed power estimations, use the SmartPower tool in the Libero IDE software. The power calculation methodology described below uses the following variables:  The number of PLLs as well as the number and the frequency of each output clock generated  The number of combinatorial and se quential cells used in the design T h e i n t e r n a l clock frequencies  The number and the standard of I/O pins used in the design  The number of RAM blocks used in the design  The number of NVM blocks used in the design  The number of Analog Quads used in the design  Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 3-13 on page 3-21.  Enable rates of output buffers—guidelines are provided for typical applications in Table 3-14 on page 3-21.  Read rate and write rate to the RAM—guidelin es are provided for typical applications in Table 3-14 on page 3-21.  Read rate to the NVM blocks The calculation should be repeated for each clock domain defined in the design. Methodology Total Power Consumption—P TOTAL Operating Mode, Standby Mode, and Sleep Mode PTOTAL = PSTAT + PDYN PSTAT is the total static power consumption. PDYN is the total dynamic power consumption. Total Static Power Consumption—P STAT Operating Mode PSTAT = PDC1 + (NNVM-BLOCKS * PDC4) + PDC5+ (NQUADS * PDC6) + (NINPUTS * PDC7) + (NOUTPUTS * PDC8) + (NPLLS * PDC9) NNVM-BLOCKS is the number of NVM blocks available in the device. NQUADS is the number of Analog Quads used in the design. NINPUTS is the number of I/O input buffers used in the design. NOUTPUTS is the number of I/O output buffers used in the design. NPLLS is the number of PLLs available in the device. Standby Mode PSTAT = PDC2 Sleep Mode P STAT = PDC3 Total Dynamic Power Consumption—P DYN Operating Mode P DYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL + PNVM+ PXTL-OSC + PRC-OSC + PAB

DC and Power Characteristics 3-18 Preliminary v1.7 Standby Mode PDYN = PXTL-OSC Sleep Mode P DYN = 0 W Global Clock Dynamic Contribution—P CLOCK Operating Mode P CLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK NSPINE is the number of global sp ines used in the user desi gn—guidelines are provided in Table 3-13 on page 3-21. NROW i s t h e n u m b e r o f V e r s a T i l e r o w s u s e d in the design—guidelines are provided in Table 3-13 on page 3-21. FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design. Standby Mode and Sleep Mode PCLOCK = 0 W Sequential Cells Dynamic Contribution—P S-CELL Operating Mode P S-CELL = NS-CELL * (PAC5 + (α1 / 2) * PAC6) * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi- tile sequential cell is used, it should be accounted for as 1. α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-13 on page 3-21. FCLK is the global clock signal frequency. Standby Mode and Sleep Mode PS-CELL = 0 W Combinatorial Cells Dynamic Contribution—P C-CELL Operating Mode P C-CELL = NC-CELL* (α1 / 2) * PAC7 * FCLK NC-CELL is the number of VersaTiles used as combinatorial modules in the design. α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-13 on page 3-21. FCLK is the global clock signal frequency. Standby Mode and Sleep Mode PC-CELL = 0 W Routing Net Dynamic Contribution—P NET Operating Mode P NET = (NS-CELL + NC-CELL) * (α1 / 2) * PAC8 * FCLK NS-CELL is the number VersaTiles used as sequential modules in the design. NC-CELL is the number of VersaTiles used as combinatorial modules in the design. α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-13 on page 3-21. FCLK is the global clock signal frequency.

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 3-19 Standby Mode and Sleep Mode PNET = 0 W I/O Input Buffer Dynamic Contribution—P INPUTS Operating Mode P INPUTS = NINPUTS * (α2 / 2) * PAC9 * FCLK NINPUTS is the number of I/O input buffers used in the design. α2 is the I/O buffer toggle rate—guidelines are provided in Table 3-13 on page 3-21. FCLK is the global clock signal frequency. Standby Mode and Sleep Mode PINPUTS = 0 W I/O Output Buffer Dynamic Contribution—P OUTPUTS Operating Mode P OUTPUTS = NOUTPUTS * (α2 / 2) * β1 * PAC10 * FCLK NOUTPUTS is the number of I/O output buffers used in the design. α2 is the I/O buffer toggle rate—guidelines are provided in Table 3-13 on page 3-21. β1 is the I/O buffer enable rate—guidelines are provided in Table 3-14 on page 3-21. FCLK is the global clock signal frequency. Standby Mode and Sleep Mode POUTPUTS = 0 W RAM Dynamic Contribution—P MEMORY Operating Mode P MEMORY = (NBLOCKS * PAC11 * β2 * FREAD-CLOCK) + (NBLOCKS * PAC12 * β3 * FWRITE-CLOCK) NBLOCKS is the number of RAM blocks used in the design. FREAD-CLOCK is the memory read clock frequency. β2 is the RAM enable rate for read op erations—guidelines are provided in Table 3-14 on page 3-21. β3 the RAM enable rate for write oper ations—guidelines are provided in Table 3-14 on page 3-21. FWRITE-CLOCK is the memory write clock frequency. Standby Mode and Sleep Mode PMEMORY = 0 W PLL/CCC Dynamic Contribution—P PLL Operating Mode P PLL = PAC13 * FCLKOUT FCLKIN is the input clock frequency. FCLKOUT is the output clock frequency.1 Standby Mode and Sleep Mode PPLL = 0 W 1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output clock in the formula output clock by adding its corresponding contribution (P AC14 * FCLKOUT product) to the total PLL contribution.

DC and Power Characteristics 3-20 Preliminary v1.7 Nonvolatile Memory Dynamic Contribution—P NVM Operating Mode The NVM dynamic power consumption is a piecewise linear function of frequency. PNVM = NNVM-BLOCKS * β4 * PAC15 * FREAD-NVM when FREAD-NVM ≤ 33 MHz, PNVM = NNVM-BLOCKS * β4 *(PAC16 + PAC17 * FREAD-NVM)when FREAD-NVM > 33 MHz NNVM-BLOCKS is the number of NVM blocks used in the design (2 in AFS600). β4 is the NVM enable rate for read operations. Default is 0 (NVM mainly in idle state). FREAD-NVM is the NVM read clock frequency. Standby Mode and Sleep Mode PNVM = 0 W Crystal Oscillator Dynamic Contribution—P XTL-OSC Operating Mode P XTL-OSC = PAC18 Standby Mode P XTL-OSC = PAC18 Sleep Mode P XTL-OSC = 0 W RC Oscillator Dynamic Contribution—P RC-OSC Operating Mode P RC-OSC = PAC19 Standby Mode and Sleep Mode P RC-OSC = 0 W Analog System Dynamic Contribution—P AB Operating Mode P AB = PAC20 Standby Mode and Sleep Mode P AB = 0 W

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 3-21 Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that the net switches at half the clock frequency. Below are some examples:  The average toggle rate of a shift register is 100%, as all flip-flop outputs toggle at half of the clock frequency.  The average toggle rate of an 8-bit counter is 25%: – Bit 0 (LSB) = 100% – Bit 1 = 50% – Bit 2 = 25% – Bit 7 (MSB) = 0.78125% Enable Rate Definition Output enable rate is the average percentage of time during which tris tate outputs are enabled. When non-tristate output buffers are used, the enable rate should be 100%. Table 3-13  Toggle Rate Guidelines Recommended for Power Calculation Component Definition Guideline α1 Toggle rate of VersaTile outputs 10% α2 I/O buffer toggle rate 10% Table 3-14  Enable Rate Guidelines Recommended for Power Calculation Component Defini tion Guideline β1 I/O output buffer enable rate 100% β2 RAM enable rate for read operations 12.5% β3 RAM enable rate for write operations 12.5% β4 NVM enable rate for read operations 0%

DC and Power Characteristics 3-22 Preliminary v1.7 Example of Power Calculation This example considers a shift register with 5,0 00 storage tiles, including a counter and memory that stores analog information. The shift regist er is clocked at 50 MHz and stores and reads information from a RAM. The device used is a commercial AFS600 device operating in typical conditions. The calculation below uses the power calculation methodology pr eviously presented and shows how to determine the dynamic and static power consumption of resources used in the application. Also included in the example is the calculation of power consumption in operating, standby, and sleep modes to illustrate the benefit of power-saving modes. Global Clock Contribution—P CLOCK FCLK = 50 MHz Number of sequential VersaTiles: NS-CELL = 5,000 Estimated number of Spines: NSPINES = 5 Estimated number of Rows: NROW = 313 Operating Mode PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK PCLOCK = (0.0128 + 5 * 0.0019 + 313 * 0.00081 + 5,000 * 0.00011) * 50 PCLOCK = 41.28 mW Standby Mode and Sleep Mode PCLOCK = 0 W Logic—Sequential Cells, Combinationa l Cells, and Routing Net Contributions—P S-CELL, PC-CELL, and PNET FCLK = 50 MHz Number of sequential VersaTiles: NS-CELL = 5,000 Number of combinatorial VersaTiles: NC-CELL = 6,000 Estimated toggle rate of VersaTile outputs: α1 = 0.1 (10%) Operating Mode PS-CELL = NS-CELL * (PAC5+ (α1 / 2) * PAC6) * FCLK PS-CELL = 21.13 mW PC-CELL = NC-CELL* (α1 / 2) * PAC7 * FCLK PC-CELL = 4.35 mW PNET = (NS-CELL + NC-CELL) * (α1 / 2) * PAC8 * FCLK PNET = 19.25 mW PLOGIC = PS-CELL + PC-CELL + PNET PLOGIC = 21.13 mW + 4.35 mW + 19.25 mW PLOGIC = 44.73 mW Standby Mode and Sleep Mode

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 3-23 PS-CELL = 0 W PC-CELL = 0 W PNET = 0 W PLOGIC = 0 W I/O Input and Output Buffer Contribution—P I/O This example uses LVTTL 3.3 V I/O cells. The ou tput buffers are 12 mA–capable, configured with high output slew and driving a 35 pF output load. FCLK = 50 MHz Number of input pins used: NINPUTS = 30 Number of output pins used: NOUTPUTS = 40 Estimated I/O buffer toggle rate: α2 = 0.1 (10%) Estimated IO buffer enable rate: β1 = 1 (100%) Operating Mode PINPUTS = NINPUTS * (α2 / 2) * PAC9 * FCLK PINPUTS = 30 * (0.1 / 2) * 0.01739 * 50 PINPUTS = 1.30 mW POUTPUTS = NOUTPUTS * (α2 / 2) * β1 * PAC10 * FCLK POUTPUTS = 40 * (0.1 / 2) * 1 * 0.4747 * 50 POUTPUTS = 47.47 mW PI/O = PINPUTS + POUTPUTS PI/O = 1.30 mW + 47.47 mW PI/O = 48.77 mW Standby Mode and Sleep Mode PINPUTS = 0 W POUTPUTS = 0 W PI/O = 0 W RAM Contribution—P MEMORY Frequency of Read Clock: FREAD-CLOCK = 10 MHz Frequency of Write Clock: FWRITE-CLOCK = 10 MHz Number of RAM blocks: NBLOCKS = 20 Estimated RAM Read Enable Rate: β2 = 0.125 (12.5%) Estimated RAM Write Enable Rate: β3 = 0.125 (12.5%) Operating Mode PMEMORY = (NBLOCKS * PAC11 * β2 * FREAD-CLOCK) + (NBLOCKS * PAC12 * β3 * FWRITE-CLOCK) PMEMORY = 1.38 mW Standby Mode and Sleep Mode PMEMORY = 0 W PLL/CCC Contribution—P PLL PLL is not used in this application.

DC and Power Characteristics 3-24 Preliminary v1.7 PPLL = 0 W Nonvolatile Memory—P NVM Nonvolatile memory is not used in this application. PNVM = 0 W Crystal Oscillator—P XTL-OSC The application utilizes standby mode. The crystal oscillator is assumed to be active. Operating Mode PXTL-OSC = PAC18 PXTL-OSC = 0.63 mW Standby Mode PXTL-OSC = PAC18 PXTL-OSC = 0.63 mW Sleep Mode PXTL-OSC = 0 W RC Oscillator—P RC-OSC Operating Mode P RC-OSC = PAC19 PRC-OSC = 3.30 mW Standby Mode and Sleep Mode PRC-OSC = 0 W Analog System—P AB Number of Quads used: NQUADS = 4 Operating Mode PAB = PAC20 PAB = 3.00 mW Standby Mode and Sleep Mode PAB = 0 W Total Dynamic Power Consumption—P DYN Operating Mode P DYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL + PNVM+ PXTL-OSC + PRC- OSC + PAB 0.63 mW + 3.30 mW + 3.00 mW PDYN = 143.06 mW Standby Mode PDYN = PXTL-OSC PDYN = 0.63 mW Sleep Mode PDYN = 0 W

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 3-25 Total Static Power Consumption—P STAT Number of Quads used: NQUADS = 4 Number of NVM blocks available (AFS600): NNVM-BLOCKS = 2 Number of input pins used: NINPUTS = 30 Number of output pins used: NOUTPUTS = 40 Operating Mode PSTAT = PDC1 + (NNVM-BLOCKS * PDC4) + PDC5 + (NQUADS * PDC6) + (NINPUTS * PDC7) + (NOUTPUTS * PDC8) PSTAT = 31.33 mW Standby Mode PSTAT = PDC2 PSTAT = 0.03 mW Sleep Mode PSTAT = PDC3 PSTAT = 0.03 mW Total Power Consumption—P TOTAL In operating mode, the total power consumption of the device is 174.39 mW: PTOTAL = PSTAT + PDYN PTOTAL = 143.06 mW + 31.33 mW PTOTAL = 174.39 mW In standby mode, the total power consumption of the device is limited to 0.66 mW: PTOTAL = PSTAT + PDYN PTOTAL = 0.03 mW + 0.63 mW PTOTAL = 0.66 mW In sleep mode, the total power consumption of the device drops as low as 0.03 mW: PTOTAL = PSTAT + PDYN PTOTAL = 0.03 mW

DC and Power Characteristics 3-26 Preliminary v1.7 Power Consumption Table 3-15  Power Consumption Parameter Description Condition Min. Typical Max. Units Crystal Oscillator ISTBXTAL Standby Current of Crystal Oscillator 10 µA IDYNXTAL Operating Current RC 0.6 mA 0.032–0.2 0.19 mA 0.2–2.0 0.6 mA 2.0–20.0 0.6 mA RC Oscillator IDYNRC Operating Current 1 mA ACM Operating Current (fixed clock) 200 µA/MHz Operating Current (user clock) 30 µA NVM System NVM Array Operating Power Idle 795 µA Read operation See Table 3-12 on page 3-16. See Table 3-12 on page 3-16. Erase 900 µA Write 900 µA PNVMCTRL NVM Controller Operating Power 20 µW/MHz

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 3-27 Part Number and Revision Date Part Number 51700092-015-0 Revised October 2008 List of Changes The following table lists critic al changes that were made in the current version of the document. Previous Version Changes in Curren t Version (Preliminary v1.7) Page Advance v1.6 (August 2008) The version number category was change d from Advance to Preliminary, which means the datasheet contains information based on simulation and/or initial characterization. Th e information is believed to be correct, but changes are possible. N/A Advance v1.4 (July 2008) The title of the datasheet changed fr om Actel Programmable System Chips to Actel Fusion Mixed- Signal FPGAs. In addition, all instances of programmable system chip were changed to mixed-signal FPGA. N/A Advance v1.3 (July 2008) In Table 3-8 · Quiescent Supply Cu rrent Characteristics (IDDQ)1 , footnote references were updated for IDC2 and IDC3. Footnote 3 and 4 were updated and footnote 5 is new. 3-10 Advance v1.1 Table 3-6 · Package Thermal Resistance was significantly updated 3-7 Table 3-11 · Different Components Con tributing to th e Dynamic Power Consumption in Fusion Devices was significantly updated. 3-15 T a b l e3 - 1 3·T o g g l e R a t e G u i d e l i n e s Recommended for Po wer Calculation was significantly updated. 3-21 Advance v0.9 In Table 3-1 · Absolute Maximum Ratings, the AT for the Unpowered, ADC reset asserted or unconfigured parameter, –11 was changed to –0.4. 3-1 The units column of Table 3-2 · Recommended Operating Conditions was incomplete in the previous version. V was added to all the rows. In addition, AT for the Unpowered, ADC reset asserted or unconfigured parameter, –10.5 was changed to –0.3. Note 6 was updated to include VCC15A. 3-3 In the title of Table 3-3 · Input Resistance of Analog Pads , Impedance was changed to Resistance. 3-4 In Table 3-5 · FPGA Programming, Storage, and Operating Limits , note 2 is new. "Program" was removed from the table heading in the Retention column. 3-5 The "PLL Behavior at Brownout Condition" section is new. 3-6 Table 3-7 · Temperature and Voltage De rating Factors for Timing Delays was updated. 3-9 In the Table 3-9 · Summary of I/O Input Buffer Power (per pin)—Default I/O Software Settings , the HSTL (I) for the Static Power PDC7 (mW) was changed from 0.1 to 0.17. 3-11 The Table 3-11 · Different Components Co ntributing to th e Dynamic Power Consumption in Fusion Devices was updated. 3-15 The Table 3-12 · Different Components Contributing to the Static Power Consumption in Fusion Devices was updated. 3-16 In the "PLL/CCC Dynamic Contribution—P PLL" section, PAC14 was deleted. 3-19

DC and Power Characteristics 3-28 Preliminary v1.7 Advance v0.8 (June 2007) In Table 3-6 · Package Thermal Resistance , the data for the following device/packages were updated: AFS090-FG256 AFS250-FG256 AFS600-FG256 AFS1500-FG256 AFS600-FG484 AFS1500-FG484 AFS1500-FG676 3-7 Advance v0.7 (January 2007) The VMV pins have now been tied internally with the V CCI pins. N/A The VCOMPLF pin description was deleted. N/A Table 3-1 · Absolute Maximum Ratings , Table 3-2 · Recommended Operating Conditions, and Table 3-3 · Input Resistance of Analog Pads were updated. 3-1 to 3-4 Table 3-5 · FPGA Programming, Storage, and Operating Limits was updated. 3-5 PAC13 and P AC14 were updated in Table 3-11 · Different Components Contributing to the Dynamic Power Consumption in Fusion Devices. 3-15 The Operating Mode for the "PLL/CCC Dynamic Contribution—P PLL" section was updated. 3-19 Table 3-15 · Power Consumption was updated to change the typical value of IDYNXTAL for 0.032–0.2 MHz to 0.19. 3-26 Advance v0.5 (June 2006) Table 3-3 · Input Resistance of Analog Pads is new. 3-4 Advance v0.4 (April 2006) The low power modes of operation were updated and clarified. N/A Advance v0.2 (April 2006) Table 3-8 · Quiescent Supply Current Characteristics (IDDQ)1 was updated. 3-10 Table 3-11 · Different Components Con tributing to th e Dynamic Power Consumption in Fusion Devices was updated. 3-15 Table 3-11 · Different Components Con tributing to th e Dynamic Power Consumption in Fusion Devices was updated. 3-15 The "Example of Power Calculation" was updated. 3-22 The Analog System info rmation was deleted from T a b l e3 - 1 5·P o w e r Consumption. 3-26 Previous Version Changes in Curren t Version (Preliminary v1.7) Page

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 3-29 Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance st atus datasheet may not have completed Actel’s qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functional ity or performance. It is the responsibility of each customer to ensure the fitn ess of any Actel product (but especially a new product) for a particular purpose, including appr opriateness for safety-cri tical, life-s upport, and other high-reliability applicatio ns. Consult Actel’s Terms and Cond itions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel’s products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information.

Preliminary v1.7 4-1 Actel Fusion® Mixed-Signal FPGAs Packaging 4 – Package Pin Assignments 108-Pin QFN Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/default.aspx. Note: The die attach paddle center of the package is tied to ground (GND). B41 B52 A44 A56 B26 B14 A28 A15 A14 B13 A43 A29 B40 B27 Pin A1 Mark

4-2 Preliminary v1.7 108-Pin QFN Pin Number AFS090 Function A1 NC A2 GNDQ A3 GAA2/IO52PDB3V0 A4 GND A5 GFA1/IO47PDB3V0 A6 GEB1/IO45PDB3V0 A7 VCCOSC A8 XTAL2 A9 GEA1/IO44PPB3V0 A10 GEA0/IO44NPB3V0 A11 GEB2/IO42PDB3V0 A12 VCCNVM A13 VCC15A A14 PCAP A15 NC A16 GNDA A17 AV0 A18 AG0 A19 ATRTN0 A20 AT1 A21 AC1 A22 AV2 A23 AG2 A24 AT2 A25 AT3 A26 AC3 A27 GNDAQ A28 ADCGNDREF A29 NC A30 GNDA A31 PTEM A32 GNDNVM A33 VPUMP A34 TCK A35 TMS A36 TRST A37 GDB1/IO39PSB1V0 A38 GDC1/IO38PDB1V0 A39 GND A40 GCB1/IO35PDB1V0 A41 GCB2/IO33PDB1V0 A42 GBA2/IO31PDB1V0 A43 NC A44 GBA1/IO30RSB0V0 A45 GBB1/IO28RSB0V0 A46 GND A47 VCC A48 GBC1/IO26RSB0V0 A49 IO21RSB0V0 A50 IO19RSB0V0 A51 IO09RSB0V0 A52 GAC0/IO04RSB0V0 A53 VCCIB0 A54 GND A55 GAB0/IO02RSB0V0 A56 GAA0/IO00RSB0V0 B1 VCOMPLA B2 VCCIB3 B3 GAB2/IO52NDB3V0 B4 VCCIB3 B5 GFA0/IO47NDB3V0 B6 GEB0/IO45NDB3V0 B7 XTAL1 B8 GNDOSC B9 GEC2/IO43PSB3V0 B10 GEA2/IO42NDB3V0 B11 VCC B12 GNDNVM B13 NCAP B14 VCC33PMP B15 VCC33N B16 GNDAQ B17 AC0 B18 AT0 B19 AG1 B20 AV1 108-Pin QFN Pin Number AFS090 Function B21 AC2 B22 ATRTN1 B23 AG3 B24 AV3 B25 V CC33A B26 VAREF B27 PUB B28 V CC33A B29 PTBASE B30 V CCNVM B31 V CC B32 TDI B33 TDO B34 V JTAG B35 GDC0/IO38NDB1V0 B36 V CCIB1 B37 GCB0/IO35NDB1V0 B38 GCC2/IO33NDB1V0 B39 GBB2/IO31NDB1V0 B40 V CCIB1 B41 GNDQ B42 GBA0/IO29RSB0V0 B43 V CCIB0 B44 GBB0/IO27RSB0V0 B45 GBC0/IO25RSB0V0 B46 IO20RSB0V0 B47 IO10RSB0V0 B48 GAC1/IO05RSB0V0 B49 GAB1/IO03RSB0V0 B50 V CC B51 GAA1/IO01RSB0V0 B52 V CCPLA 108-Pin QFN Pin Number AFS090 Function

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 4-3 180-Pin QFN Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/default.aspx. Note: The die attach paddle center of the package is tied to ground (GND). A1B1C1 A16B15C14 A48 Pin A1 Mark Optional Corner Pad (4X) A49 A64 A32 A17 B45 B46 B60 B30 B16 C42 C43 C56 C28 C15 A33B31C29

4-4 Preliminary v1.7 180-Pin QFN Pin Number AFS090 Function AFS250 Function A1 GNDQ GNDQ A2 V CCIB3 V CCIB3 A3 GAB2/IO52NDB3V0 IO74NDB3V0 A4 GFA2/IO51NDB3V0 IO71NDB3V0 A5 GFC2/IO50NDB3V0 IO69NPB3V0 A6 V CCIB3 V CCIB3 A7 GFA1/IO47PPB3V0 GFB1/IO67PPB3V0 A8 GEB0/IO45NDB3V0 NC A9 XTAL1 XTAL1 A10 GNDOSC GNDOSC A11 GEC2/IO43PPB3V0 GEA1/IO61PPB3V0 A12 IO43NPB3V0 GEA0/IO61NPB3V0 A13 NC V CCIB3 A14 GNDNVM GNDNVM A15 PCAP PCAP A16 V CC33PMP VCC33PMP A17 NC NC A18 AV0 AV0 A19 AG0 AG0 A20 ATRTN0 ATRTN0 A21 AG1 AG1 A22 AC1 AC1 A23 AV2 AV2 A24 AT2 AT2 A25 AT3 AT3 A26 AC3 AC3 A27 AV4 AV4 A28 AC4 AC4 A29 AT4 AT4 A30 NC AG5 A31 NC AV5 A32 ADCGNDREF ADCGNDREF A33 V CC33A VCC33A A34 GNDA GNDA A35 PTBASE PTBASE A36 V CCNVM VCCNVM A37 V PUMP VPUMP A38 TDI TDI A39 TDO TDO A40 V JTAG VJTAG A41 GDB1/IO39PPB1V0 GDA1/IO54PPB1V0 A42 GDC1/IO38PDB1V0 GDB1/IO53PDB1V0 A43 V CC VCC A44 GCB0/IO35NPB1V0 GCB0/IO48NPB1V0 A45 GCC1/IO34PDB1V0 GCC1/IO47PDB1V0 A46 V CCIB1 V CCIB1 A47 GBC2/IO32PPB1V0 GBB2/IO41PPB1V0 A48 V CCIB1 V CCIB1 A49 NC NC A50 GBA0/IO29RSB0V 0 GBB1/IO37RSB0V0 A51 V CCIB0 V CCIB0 A52 GBB0/IO27RSB0V 0 GBC0/IO34RSB0V0 A53 GBC1/IO26RSB0V0 IO33RSB0V0 A54 IO24RSB0V0 IO29RSB0V0 A55 IO21RSB0V0 IO26RSB0V0 A56 V CCIB0 V CCIB0 A57 IO15RSB0V0 IO21RSB0V0 A58 IO10RSB0V0 IO13RSB0V0 A59 IO07RSB0V0 IO10RSB0V0 A60 GAC0/IO04RSB0V0 IO06RSB0V0 A61 GAB1/IO03RSB0V0 GAC1/IO05RSB0V0 A62 V CC VCC A63 GAA1/IO01RSB0V0 GAB0/IO02RSB0V0 A64 NC NC B1 V COMPLA VCOMPLA B2 GAA2/IO52PDB3V0 GAC2/IO74PDB3V0 B3 GAC2/IO51PDB3V0 GFA2/IO71PDB3V0 B4 GFB2/IO50PDB3V0 GFB2/IO70PSB3V0 B5 V CC VCC B6 GFC0/IO49NDB3V0 GFC0/IO68NDB3V0 B7 GEB1/IO45PDB3V0 NC B8 V CCOSC VCCOSC 180-Pin QFN Pin Number AFS090 Func tion AFS250 Function

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 4-5 B9 XTAL2 XTAL2 B10 GEA0/IO44NDB3V0 GFA0/IO66NDB3V0 B11 GEB2/IO42PDB3V0 IO60NDB3V0 B12 V CC VCC B12 V CC VCC B13 V CCNVM VCCNVM B14 V CC15A VCC15A B15 NCAP NCAP B16 VCC33N VCC33N B17 GNDAQ GNDAQ B18 AC0 AC0 B19 AT0 AT0 B20 AT1 AT1 B21 AV1 AV1 B22 AC2 AC2 B23 ATRTN1 ATRTN1 B24 AG3 AG3 B25 AV3 AV3 B26 AG4 AG4 B27 ATRTN2 ATRTN2 B28 NC AC5 B29 V CC33A VCC33A B30 VAREF VAREF B31 PUB PUB B32 PTEM PTEM B33 GNDNVM GNDNVM B34 V CC VCC B34 V CC VCC B35 TCK TCK B36 TMS TMS B37 TRST TRST B38 GDB2/IO41PSB1V0 GDA2/IO55PSB1V0 B39 GDC0/IO38NDB1V0 GDB0/IO53NDB1V0 B40 V CCIB1 V CCIB1 B41 GCA1/IO36PDB1V0 GCA1/IO49PDB1V0 B42 GCC0/IO34NDB1V0 GCC0/IO47NDB1V0 180-Pin QFN Pin Number AFS090 Function AFS250 Function B43 GCB2/IO33PSB1V 0 GBC2/IO42PSB1V0 B44 V CC VCC B45 GBA2/IO31PDB1V0 GBA2/IO40PDB1V0 B46 GNDQ GNDQ B47 GBA1/IO30RSB0V0 GBA0/IO38RSB0V0 B48 GBB1/IO28RSB0V0 GBC1/IO35RSB0V0 B49 V CC VCC B50 GBC0/IO25RSB0V0 IO31RSB0V0 B51 IO23RSB0V0 IO28RSB0V0 B52 IO20RSB0V0 IO25RSB0V0 B53 V CC VCC B54 IO11RSB0V0 IO14RSB0V0 B55 IO08RSB0V0 IO11RSB0V0 B56 GAC1/IO05RSB0V0 IO08RSB0V0 B57 V CCIB0 V CCIB0 B58 GAB0/IO02RSB0V0 GAC0/IO04RSB0V0 B59 GAA0/IO00RSB0V0 GAA1/IO01RSB0V0 B60 V CCPLA VCCPLA C1 NC NC C2 NC V CCIB3 C3 GND GND C4 NC GFC2/IO69PPB3V0 C5 GFC1/IO49PDB3V0 GFC1/IO68PDB3V0 C6 GFA0/IO47NPB3V0 GFB0/IO67NPB3V0 C7 V CCIB3 NC C8 GND GND C9 GEA1/IO44PDB3V0 GFA1/IO66PDB3V0 C10 GEA2/IO42NDB3V0 GEC2/IO60PDB3V0 C11 NC GEA2/IO58PSB3V0 C12 NC NC C13 GND GND C14 NC NC C15 NC NC C16 GNDA GNDA C17 NC NC C18 NC NC 180-Pin QFN Pin Number AFS090 Func tion AFS250 Function

4-6 Preliminary v1.7 C19 NC NC C20 NC NC C21 AG2 AG2 C22 NC NC C23 NC NC C24 NC NC C25 NC AT5 C26 GNDAQ GNDAQ C27 NC NC C28 NC NC C29 NC NC C30 NC NC C31 GND GND C32 NC NC C33 NC NC C34 NC NC C35 GND GND C36 GDB0/IO39NPB1V0 GDA0/IO54NPB1V0 C37 GDA1/IO37NSB1V 0 GDC0/IO52NSB1V0 C38 GCA0/IO36NDB1V0 GCA0/IO49NDB1V0 C39 GCB1/IO35PPB1V0 GCB1/IO48PPB1V0 C40 GND GND C41 GCA2/IO32NPB1V0 IO41NPB1V0 C42 GBB2/IO31NDB1V0 IO40NDB1V0 C43 NC NC C44 NC GBA1/IO39RSB0V0 C45 NC GBB0/IO36RSB0V0 C46 GND GND C47 NC IO30RSB0V0 C48 IO22RSB0V0 IO27RSB0V0 C49 GND GND C50 IO13RSB0V0 IO16RSB0V0 C51 IO09RSB0V0 IO12RSB0V0 C52 IO06RSB0V0 IO09RSB0V0 C53 GND GND C54 NC GAB1/IO03RSB0V0 180-Pin QFN Pin Number AFS090 Function AFS250 Function C55 NC GAA0/IO00RSB0V0 C56 NC NC D1 NC NC D2 NC NC D3 NC NC D4 NC NC 180-Pin QFN Pin Number AFS090 Func tion AFS250 Function

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 4-7 208-Pin PQFP Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/default.aspx. 208-Pin PQFP 1 208

4-8 Preliminary v1.7 208-Pin PQFP Pin Number AFS250 Function AFS600 Function 1V CCPLA VCCPLA 2V COMPLA VCOMPLA

3 GNDQ GAA2/IO85PDB4V0

5 GAA2/IO76PDB3V0 GAB2/IO84PDB4V0

6 IO76NDB3V0 IO84NDB4V0

7 GAB2/IO75PDB3V0 GAC2/IO83PDB4V0

8 IO75NDB3V0 IO83NDB4V0

9 NC IO77PDB4V0

10 NC IO77NDB4V0

12 GND IO76NDB4V0

13 V CCIB3 V CC

14 IO72PDB3V0 GND

15 IO72NDB3V0 V CCIB4

16 GFA2/IO71PDB3V0 GFA2/IO75PDB4V0

17 IO71NDB3V0 IO75NDB4V0

18 GFB2/IO70PDB3V0 GFC2/IO73PDB4V0

19 IO70NDB3V0 IO73NDB4V0

20 GFC2/IO69PDB3V0 V

21 IO69NDB3V0 XTAL1

22 V CC XTAL2

23 GND GNDOSC

25 GFC1/IO68PDB3V0 GFC0/IO72NDB4V0

26 GFC0/IO68NDB3V0 GFB1/IO71PDB4V0

27 GFB1/IO67PDB3V0 GFB0/IO71NDB4V0

28 GFB0/IO67NDB3V0 GFA1/IO70PDB4V0

30 XTAL1 IO69PDB4V0

31 XTAL2 IO69NDB4V0

32 GNDOSC V CC

33 GEB1/IO62PDB3V0 GND

34 GEB0/IO62NDB3V0 V

35 GEA1/IO61PDB3V0 GEC1/IO63PDB4V0

36 GEA0/IO61NDB3V0 GEC0/IO63NDB4V0

37 GEC2/IO60PDB3V0 GEB1/IO62PDB4V0

38 IO60NDB3V0 GEB0/IO62NDB4V0

39 GND GEA1/IO61PDB4V0

41 GEB2/IO59PDB3V0 GEC2/IO60PDB4V0

42 IO59NDB3V0 IO60NDB4V0

43 GEA2/IO58PDB3V0 V

44 IO58NDB3V0 GNDQ

45 V CC VCC

46 V CCNVM VCCNVM

47 GNDNVM GNDNVM

48 GND GND

49 V CC15A VCC15A

50 PCAP PCAP

51 NCAP NCAP

52 V CC33PMP VCC33PMP

53 VCC33N VCC33N

54 GNDA GNDA

55 GNDAQ GNDAQ

56 NC AV0

57 NC AC0

58 NC AG0

59 NC AT0

60 NC ATRTN0

61 NC AT1

62 NC AG1

63 NC AC1

64 NC AV1

65 AV0 AV2

66 AC0 AC2

67 AG0 AG2

68 AT0 AT2

69 ATRTN0 ATRTN1

70 AT1 AT3

71 AG1 AG3

Pin Number AFS250 Function AFS600 Function

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 4-9

72 AC1 AC3

73 AV1 AV3

74 AV2 AV4

75 AC2 AC4

76 AG2 AG4

77 AT2 AT4

78 ATRTN1 ATRTN2

79 AT3 AT5

80 AG3 AG5

81 AC3 AC5

82 AV3 AV5

83 AV4 AV6

84 AC4 AC6

85 AG4 AG6

86 AT4 AT6

87 ATRTN2 ATRTN3

88 AT5 AT7

89 AG5 AG7

90 AC5 AC7

91 AV5 AV7

92 NC AV8

93 NC AC8

94 NC AG8

95 NC AT8

96 NC ATRTN4

97 NC AT9

98 NC AG9

99 NC AC9

100 NC AV9

101 GNDAQ GNDAQ

103 ADCGNDREF ADCGNDREF

104 VAREF VAREF

105 PUB PUB

107 GNDA GNDA

Pin Number AFS250 Function AFS600 Function

108 PTEM PTEM

109 PTBASE PTBASE

110 GNDNVM GNDNVM

111 V CCNVM VCCNVM

112 V CC VCC

113 V PUMP VPUMP

114 GNDQ NC

115 V CCIB1 TCK

116 TCK TDI

117 TDI TMS

118 TMS TDO

119 TDO TRST

120 TRST V

121 V JTAG IO57NDB2V0

122 IO57NDB1V0 GDC2/IO57PDB2V0

123 GDC2/IO57PDB1V0 IO56NDB2V0

124 IO56NDB1V0 GDB2/IO56PDB2V0

125 GDB2/IO56PDB1V0 IO55NDB2V0

127 GND GDA0/IO54NDB2V

128 IO55NDB1V0 GDA1/IO54PDB2V0

129 GDA2/IO55PDB1V0 V

130 GDA0/IO54NDB1V0 GND

131 GDA1/IO54PDB1V0 V CC

132 GDB0/IO53NDB1V0 GCA0/IO45NDB2V0

133 GDB1/IO53PDB1V0 GCA1/IO45PDB2V0

134 GDC0/IO52NDB1V0 GCB0/IO44NDB2V0

135 GDC1/IO52PDB1V 0 GCB1/IO44PDB2V0

136 IO51NSB1V0 GCC0/IO43NDB2V0

138 GND IO42NDB2V0

139 V CC IO42PDB2V0

140 IO50NDB1V0 IO41NDB2V0

141 IO50PDB1V0 GCC2/IO41PDB2V0

Pin Number AFS250 Function AFS600 Function

4-10 Preliminary v1.7

142 GCA0/IO49NDB1V0 V CCIB2

143 GCA1/IO49PDB1V0 GND

144 GCB0/IO48NDB1V0 V CC

145 GCB1/IO48PDB1V0 IO40NDB2V0

146 GCC0/IO47NDB1V 0 GCB2/IO40PDB2V0

147 GCC1/IO47PDB1V0 IO39NDB2V0

148 IO42NDB1V0 GCA2/IO39PDB2V0

149 GBC2/IO42PDB1V0 IO31NDB2V0

151 GND IO30NDB2V0

152 V CC GBA2/IO30PDB2V0

153 IO41NDB1V0 V CCIB2

154 GBB2/IO41PDB1V0 GNDQ

155 IO40NDB1V0 V COMPLB

156 GBA2/IO40PDB1V0 V CCPLB

157 GBA1/IO39RSB0V0 V CCIB1

158 GBA0/IO38RSB0V0 GNDQ

159 GBB1/IO37RSB0V0 GBB1/IO27PPB1V1

160 GBB0/IO36RSB0V0 GBA1/IO28PPB1V1

161 GBC1/IO35RSB0V 0 GBB0/IO27NPB1V1

163 GND V CCIB1

164 V CC GND

165 GBC0/IO34RSB0V0 V CC

166 IO33RSB0V0 GBC1/IO26PDB1V1

167 IO32RSB0V0 GBC0/IO26NDB1V1

168 IO31RSB0V0 IO24PPB1V1

169 IO30RSB0V0 IO23PPB1V1

170 IO29RSB0V0 IO24NPB1V1

171 IO28RSB0V0 IO23NPB1V1

172 IO27RSB0V0 IO22PPB1V0

173 IO26RSB0V0 IO21PPB1V0

174 IO25RSB0V0 IO22NPB1V0

176 GND IO20PSB1V0

177 V CC IO19PSB1V0

Pin Number AFS250 Function AFS600 Function

178 IO24RSB0V0 IO14NSB0V1

179 IO23RSB0V0 IO12PDB0V1

180 IO22RSB0V0 IO12NDB0V1

181 IO21RSB0V0 V CCIB0

182 IO20RSB0V0 GND

183 IO19RSB0V0 V

184 IO18RSB0V0 IO10PPB0V1

185 IO17RSB0V0 IO09PPB0V1

186 IO16RSB0V0 IO10NPB0V1

187 IO15RSB0V0 IO09NPB0V1

189 GND IO07PPB0V1

190 V CC IO08NPB0V1

191 IO14RSB0V0 IO07NPB0V1

192 IO13RSB0V0 IO06PPB0V0

193 IO12RSB0V0 IO05PPB0V0

194 IO11RSB0V0 IO06NPB0V0

195 IO10RSB0V0 IO04PPB0V0

196 IO09RSB0V0 IO05NPB0V0

197 IO08RSB0V0 IO04NPB0V0

198 IO07RSB0V0 GAC1/IO03PDB0V0

199 IO06RSB0V0 GAC0/IO03NDB0V0

200 GAC1/IO05RSB0V0 V

201 V CCIB0 GND

202 GND V CC

203 V CC GAB1/IO02PDB0V0

204 GAC0/IO04RSB0V0 GAB0/IO02NDB0V0

205 GAB1/IO03RSB0V0 GAA1/IO01PDB0V0

206 GAB0/IO02RSB0V0 GAA0/IO01NDB0V

207 GAA1/IO01RSB0V0 GNDQ

208 GAA0/IO00RSB0V0 V CCIB0

Pin Number AFS250 Function AFS600 Function

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 4-11 256-Pin FBGA Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/default.aspx. 13579111315 246810121416 C E G J L N R D F H K M P T B A A1 Ball Pad Corner

4-12 Preliminary v1.7 256-Pin FBGA Pin Number AFS090 Function AFS250 Func tion AFS600 Function AFS1500 Function A1 GND GND GND GND A2 V CCIB0 V CCIB0 V CCIB0 V CCIB0 A3 GAB0/IO02RSB0V0 GAA0/IO00RSB0V0 GAA0/IO01NDB0V0 GAA0/IO01NDB0V0 A4 GAB1/IO03RSB0V0 GAA1/IO01RSB0V0 GAA1/IO01PDB0V0 GAA1/IO01PDB0V0 A5 GND GND GND GND A6 IO07RSB0V0 IO11RSB0V0 IO10PDB0V1 IO07PDB0V1 A7 IO10RSB0V0 IO14RSB0V0 IO12PDB0V1 IO13PDB0V2 A8 IO11RSB0V0 IO15RSB0V0 IO12NDB0V1 IO13NDB0V2 A9 IO16RSB0V0 IO24RSB0V0 IO22NDB1V0 IO24NDB1V0 A10 IO17RSB0V0 IO25RSB0V0 IO22PDB1V0 IO24PDB1V0 A11 IO18RSB0V0 IO26RSB0V 0 IO24NDB1V1 IO29NDB1V1 A12 GND GND GND GND A13 GBC0/IO25RSB0V0 GBA0/IO38RSB0V0 GBA0/IO28NDB1V1 GBA0/IO42NDB1V2 A14 GBA0/IO29RSB0V0 IO32RSB 0V0 IO29NDB1V1 IO43NDB1V2 A15 V CCIB0 V CCIB0 V CCIB1 V CCIB1 A16 GND GND GND GND B1 V COMPLA VCOMPLA VCOMPLA VCOMPLA B2 V CCPLA VCCPLA VCCPLA VCCPLA B3 GAA0/IO00RSB0V0 IO07RSB0V0 IO00NDB0V0 IO00NDB0V0 B4 GAA1/IO01RSB0V0 IO06RSB0V0 IO00PDB0V0 IO00PDB0V0 B5 NC GAB1/IO03RSB0V0 GAB1/IO 02PPB0V0 GAB1/IO02PPB0V0 B6 IO06RSB0V0 IO10RSB0V0 IO10NDB0V1 IO07NDB0V1 B7 V CCIB0 V CCIB0 V CCIB0 V CCIB0 B8 IO12RSB0V0 IO16RSB0V0 IO18NDB1V0 IO22NDB1V0 B9 IO13RSB0V0 IO17RSB0V0 IO18PDB1V0 IO22PDB1V0 B10 V CCIB0 V CCIB0 V CCIB1 V CCIB1 B11 IO19RSB0V0 IO27RSB0V0 IO24PDB1V1 IO29PDB1V1 B12 GBB0/IO27RSB0V0 GBC0/IO34RSB0V 0 GBC0/IO26NPB1V1 GBC0/IO40NPB1V2 B13 GBC1/IO26RSB0V0 GBA1/IO39RSB0V 0 GBA1/IO28PDB1V1 GBA1/IO42PDB1V2 B14 GBA1/IO30RSB0V0 IO33RSB0V0 IO29PDB1V1 IO43PDB1V2 B15 NC NC V CCPLB VCCPLB B16 NC NC V COMPLB VCOMPLB C1 V CCIB3 V CCIB3 V CCIB4 V CCIB4 C2 GND GND GND GND C3 V CCIB3 V CCIB3 V CCIB4 V CCIB4 C4 NC NC V CCIB0 V CCIB0 C5 V CCIB0 V CCIB0 V CCIB0 V CCIB0 C6 GAC1/IO05RSB0V0 GAC1/ IO05RSB0V0 GAC1/IO03PDB 0V0 GAC1/IO03PDB0V0

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 4-13 C7 IO09RSB0V0 IO12RSB0V0 IO06NDB0V0 IO09NDB0V1 C8 IO14RSB0V0 IO22RSB0V0 IO16PDB1V0 IO23PDB1V0 C9 IO15RSB0V0 IO23RSB0V0 IO16NDB1V0 IO23NDB1V0 C10 IO22RSB0V0 IO30RSB0V 0 IO25NDB1V1 IO31NDB1V1 C11 IO20RSB0V0 IO31RSB0V0 IO25PDB1V1 IO31PDB1V1 C12 V CCIB0 V CCIB0 V CCIB1 V CCIB1 C13 GBB1/IO28RSB0V0 GBC1/IO35RSB0V 0 GBC1/IO26PPB1V1 G BC1/IO40PPB1V2 C14 V CCIB1 V CCIB1 V CCIB2 V CCIB2 C15 GND GND GND GND C16 V CCIB1 V CCIB1 V CCIB2 V CCIB2 D1 GFC2/IO50NPB3V0 IO75NDB 3V0 IO84NDB4V0 IO124NDB4V0 D2 GFA2/IO51NDB3V0 GAB2/IO75PDB3 V0 GAB2/IO84PDB4V0 GAB2/IO124PDB4V0 D3 GAC2/IO51PDB3V0 IO76NDB3V0 IO85NDB4V0 IO125NDB4V0 D4 GAA2/IO52PDB3V0 GAA2/IO76PDB3V0 G AA2/IO85PDB4V0 GAA2/IO125PDB4V0 D5 GAB2/IO52NDB3V0 GAB0/ IO02RSB0V0 GAB0/IO02NPB 0V0 GAB0/IO02NPB0V0 D6 GAC0/IO04RSB0V0 GAC0/ IO04RSB0V0 GAC0/IO03NDB0V0 GAC0/IO03NDB0V0 D7 IO08RSB0V0 IO13RSB0V0 IO06PDB0V0 IO09PDB0V1 D8 NC IO20RSB0V0 IO14NDB0V1 IO15NDB0V2 D9 NC IO21RSB0V0 IO14PDB0V1 IO15PDB0V2 D10 IO21RSB0V0 IO28RSB0V0 IO23PDB1V1 IO37PDB1V2 D11 IO23RSB0V0 GBB0/IO36RSB0V0 G BB0/IO27NDB1V1 GBB0/IO41NDB1V2 D12 NC NC V CCIB1 V CCIB1 D13 GBA2/IO31PDB1V0 GBA2/IO40PDB1V0 GBA2/IO30PDB2V0 GBA2/IO44PDB2V0 D14 GBB2/IO31NDB1V0 IO40NDB 1V0 IO30NDB2V0 IO44NDB2V0 D15 GBC2/IO32PDB1V0 GBB2/IO41PDB1 V0 GBB2/IO31PDB2V0 GBB2/IO45PDB2V0 D16 GCA2/IO32NDB1V0 IO41NDB 1V0 IO31NDB2V0 IO45NDB2V0 E1 GND GND GND GND E2 GFB0/IO48NPB3V0 IO73NDB 3V0 IO81NDB4V0 IO118NDB4V0 E3 GFB2/IO50PPB3V0 IO73PDB3V0 IO81PDB4V0 IO118PDB4V0 E4 V CCIB3 V CCIB3 V CCIB4 V CCIB4 E5 NC IO74NPB3V0 IO83NPB4V0 IO123NPB4V0 E6 NC IO08RSB0V0 IO04NPB0V0 IO05NPB0V1 E7 GND GND GND GND E8 NC IO18RSB0V0 IO08PDB0V1 IO11PDB0V1 E9 NC NC IO20NDB1V0 IO27NDB1V1 E10 GND GND GND GND E11 IO24RSB0V0 GBB1/IO37RSB0V0 G BB1/IO27PDB1V1 GBB1/IO41PDB1V2 E12 NC IO50PPB1V0 IO33PSB2V0 IO48PSB2V0 256-Pin FBGA Pin Number AFS090 Function AFS250 Func tion AFS600 Function AFS1500 Function

4-14 Preliminary v1.7 E13 V CCIB1 V CCIB1 V CCIB2 V CCIB2 E14 GCC2/IO33NDB1V0 IO42NDB 1V0 IO32NDB2V0 IO46NDB2V0 E15 GCB2/IO33PDB1V0 GBC2/IO42PDB1 V0 GBC2/IO32PDB2V0 GBC2/IO46PDB2V0 E16 GND GND GND GND F1 NC NC IO79NDB4V0 IO111NDB4V0 F2 NC NC IO79PDB4V0 IO111PDB4V0 F3 GFB1/IO48PPB3V0 IO72NDB3V0 IO76NDB4V0 IO112NDB4V0 F4 GFC0/IO49NDB3V0 IO72PDB3V0 IO76PDB4V0 IO112PDB4V0 F5 NC NC IO82PSB4V0 IO120PSB4V0 F6 GFC1/IO49PDB3V0 GAC2/ IO74PPB3V0 GAC2/IO83PPB 4V0 GAC2/IO123PPB4V0 F7 NC IO09RSB0V0 IO04PPB0V0 IO05PPB0V1 F8 NC IO19RSB0V0 IO08NDB0V1 IO11NDB0V1 F9 NC NC IO20PDB1V0 IO27PDB1V1 F10 NC IO29RSB0V0 IO23NDB1V1 IO37NDB1V2 F11 NC IO43NDB1V0 IO36NDB2V0 IO50NDB2V0 F12 NC IO43PDB1V0 IO36PDB2V0 IO50PDB2V0 F13 NC IO44NDB1V0 IO39NDB2V0 IO59NDB2V0 F14 NC GCA2/IO44PDB1V0 GCA2/IO39PDB2V0 GCA2/IO59PDB2V0 F15 GCC1/IO34PDB1V0 GCB2/IO45PDB1 V0 GCB2/IO40PDB2V0 GCB2/IO60PDB2V0 F16 GCC0/IO34NDB1V0 IO45NDB 1V0 IO40NDB2V0 IO60NDB2V0 G1 GEC0/IO46NPB3V0 IO70NPB3V0 IO74NPB4V0 IO109NPB4V0 G2 V CCIB3 V CCIB3 V CCIB4 V CCIB4 G3 GEC1/IO46PPB3V0 GFB2/IO70PPB3V0 G FB2/IO74PPB4V0 GFB2/IO109PPB4V0 G4 GFA1/IO47PDB3V0 GFA2/IO71PDB3V0 GFA2/IO75PDB4V0 GFA2/IO110PDB4V0 G5 GND GND GND GND G6 GFA0/IO47NDB3V0 IO71NDB3V0 IO75NDB4V0 IO110NDB4V0 G7 GND GND GND GND G8 V CC VCC VCC VCC G9 GND GND GND GND G10 V CC VCC VCC VCC G11 GDA1/IO37NDB1V0 GCC0/IO47NDB1V0 G CC0/IO43NDB2V0 GCC0/IO62NDB2V0 G12 GND GND GND GND G13 IO37PDB1V0 GCC1/IO47PDB1V0 GCC1/IO43PDB2V0 GCC1/IO62PDB2V0 G14 GCB0/IO35NPB1V0 IO46NPB 1V0 IO41NPB2V0 IO61NPB2V0 G15 V CCIB1 V CCIB1 V CCIB2 V CCIB2 G16 GCB1/IO35PPB1V0 GCC2/IO46PPB1V0 GCC2/IO41PPB2V0 GCC2/IO61PPB2V0 H1 GEB1/IO45PDB3V0 GFC2/IO69PDB3V0 G FC2/IO73PDB4V0 GFC2/IO108PDB4V0 H2 GEB0/IO45NDB3V0 IO69NDB3V0 IO73NDB4V0 IO108NDB4V0 256-Pin FBGA Pin Number AFS090 Function AFS250 Func tion AFS600 Function AFS1500 Function

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 4-15 H3 XTAL2 XTAL2 XTAL2 XTAL2 H4 XTAL1 XTAL1 XTAL1 XTAL1 H5 GNDOSC GNDOSC GNDOSC GNDOSC H6 V CCOSC VCCOSC VCCOSC VCCOSC H7 V CC VCC VCC VCC H8 GND GND GND GND H9 V CC VCC VCC VCC H10 GND GND GND GND H11 GDC0/IO38NDB1V0 IO51NDB 1V0 IO47NDB2V0 IO69NDB2V0 H12 GDC1/IO38PDB1V0 IO51PDB1V0 IO47PDB2V0 IO69PDB2V0 H13 GDB1/IO39PDB1V0 GCA1/IO49PDB1V0 GCA1/IO45PDB2V0 GCA1/IO64PDB2V0 H14 GDB0/IO39NDB1V0 GCA0/IO49NDB1V 0 GCA0/IO45NDB2V0 GCA0/IO64NDB2V0 H15 GCA0/IO36NDB1V0 GCB0/IO48NDB1V 0 GCB0/IO44NDB2V0 GCB0/IO63NDB2V0 H16 GCA1/IO36PDB1V0 GCB1/IO48PDB1 V0 GCB1/IO44PDB2V0 GCB1/IO63PDB2V0 J1 GEA0/IO44NDB3V0 GFA0/IO66NDB3V 0 GFA0/IO70NDB4V0 GFA0/IO105NDB4V0 J2 GEA1/IO44PDB3V0 GFA1/IO66PDB3V0 GFA1/IO70PDB4V0 GFA1/IO105PDB4V0 J3 IO43NDB3V0 GFB0/IO67NDB3V0 GFB 0/IO71NDB4V0 GFB0/IO106NDB4V0 J4 GEC2/IO43PDB3V0 GFB1/IO67PDB3V0 G FB1/IO71PDB4V0 GFB1/IO106PDB4V0 J5 NC GFC0/IO68NDB3V0 GFC0/IO 72NDB4V0 GFC0/IO107NDB4V0 J6 NC GFC1/IO68PDB3V0 GFC1/IO 72PDB4V0 GFC1/IO107PDB4V0 J7 GND GND GND GND J8 V CC VCC VCC VCC J9 GND GND GND GND J10 V CC VCC VCC VCC J11 GDC2/IO41NPB1V0 IO56NP B1V0 IO56NPB2V0 IO83NPB2V0 J12 NC GDB0/IO53NPB1V0 GDB0/ IO53NPB2V0 GDB0/IO80NPB2V0 J13 NC GDA1/IO54PDB1V0 GDA1/IO54PDB2V0 GDA1/IO81PDB2V0 J14 GDA0/IO40PDB1V0 GDC1/IO52PPB1V0 GDC1/IO52PPB2V0 GDC1/IO79PPB2V0 J15 NC IO50NPB1V0 IO51NSB2V0 IO77NSB2V0 J16 GDA2/IO40NDB1V0 GDC0/IO52NPB1V0 GDC0/IO52NPB2V0 GDC0/IO79NPB2V0 K1 NC IO65NPB3V0 IO67NPB4V0 IO92NPB4V0 K2 V CCIB3 V CCIB3 V CCIB4 V CCIB4 K3 NC IO65PPB3V0 IO67PPB4V0 IO92PPB4V0 K4 NC IO64PDB3V0 IO65PDB4V0 IO96PDB4V0 K5 GND GND GND GND K6 NC IO64NDB3V0 IO65NDB4V0 IO96NDB4V0 K7 V CC VCC VCC VCC K8 GND GND GND GND 256-Pin FBGA Pin Number AFS090 Function AFS250 Func tion AFS600 Function AFS1500 Function

4-16 Preliminary v1.7 K9 V CC VCC VCC VCC K10 GND GND GND GND K11 NC GDC2/IO57PPB1V0 GDC2 /IO57PPB2V0 GDC2/IO84PPB2V0 K12 GND GND GND GND K13 NC GDA0/IO54NDB1V0 GDA0/IO 54NDB2V0 GDA0/IO81NDB2V0 K14 NC GDA2/IO55PPB1V0 GDA2/IO55PPB2V0 GDA2/IO82PPB2V0 K15 V CCIB1 V CCIB1 V CCIB2 V CCIB2 K16 NC GDB1/IO53PPB1V0 GDB1 /IO53PPB2V0 GDB1/IO80PPB2V0 L1 NC GEC1/IO63PDB3V0 GEC1/IO63PDB4V0 GEC1/IO90PDB4V0 L2 NC GEC0/IO63NDB3V0 GEC0/ IO63NDB4V0 GEC0/IO90NDB4V0 L3 NC GEB1/IO62PDB3V0 GEB1/IO62PDB4V0 GEB1/IO89PDB4V0 L4 NC GEB0/IO62NDB3V0 GEB0/ IO62NDB4V0 GEB0/IO89NDB4V0 L5 NC IO60NDB3V0 IO60NDB4V0 IO87NDB4V0 L6 NC GEC2/IO60PDB3V0 GEC2/IO60PDB4V0 GEC2/IO87PDB4V0 L7 GNDA GNDA GNDA GNDA L8 AC0 AC0 AC2 AC2 L 9 A V 2A V 2A V 4A V 4 L10 AC3 AC3 AC5 AC5 L11 PTEM PTEM PTEM PTEM L12 TDO TDO TDO TDO L13 V JTAG VJTAG VJTAG VJTAG L14 NC IO57NPB1V0 IO57NPB2V0 IO84NPB2V0 L15 GDB2/IO41PPB1V0 GDB2/ IO56PPB1V0 GDB2/IO56PPB2V0 GDB2/IO83PPB2V0 L16 NC IO55NPB1V0 IO55NPB2V0 IO82NPB2V0 M1 GND GND GND GND M2 NC GEA1/IO61PDB3V0 GEA1/IO61PDB4V0 GEA1/IO88PDB4V0 M3 NC GEA0/IO61NDB3V0 GEA0/IO61NDB4V0 GEA0/IO88NDB4V0 M4 V CCIB3 V CCIB3 V CCIB4 V CCIB4 M5 NC IO58NPB3V0 IO58NPB4V0 IO85NPB4V0 M6 NC NC AV0 AV0 M7 NC NC AC1 AC1 M8 AG1 AG1 AG3 AG3 M9 AC2 AC2 AC4 AC4 M10 AC4 AC4 AC6 AC6 M11 NC AG5 AG7 AG7 M12 V PUMP VPUMP VPUMP VPUMP M13 V CCIB1 V CCIB1 V CCIB2 V CCIB2 M14 TMS TMS TMS TMS 256-Pin FBGA Pin Number AFS090 Function AFS250 Func tion AFS600 Function AFS1500 Function

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 4-17 M15 TRST TRST TRST TRST M16 GND GND GND GND N1 GEB2/IO42PDB3V0 GEB2/IO59PDB3V0 GEB2/IO59PDB4V0 GEB2/IO86PDB4V0 N2 GEA2/IO42NDB3V0 IO59NDB 3V0 IO59NDB4V0 IO86NDB4V0 N3 NC GEA2/IO58PPB3V0 GEA2/ IO58PPB4V0 GEA2/IO85PPB4V0 N4 V CC33PMP VCC33PMP VCC33PMP VCC33PMP N5 V CC15A VCC15A VCC15A VCC15A N6 NC NC AG0 AG0 N7 AC1 AC1 AC3 AC3 N8 AG3 AG3 AG5 AG5 N 9 A V 3A V 3A V 5A V 5 N10 AG4 AG4 AG6 AG6 N11 NC NC AC8 AC8 N12 GNDA GNDA GNDA GNDA N13 V CC33A VCC33A VCC33A VCC33A N14 V CCNVM VCCNVM VCCNVM VCCNVM N15 TCK TCK TCK TCK N16 TDI TDI TDI TDI P1 V CCNVM VCCNVM VCCNVM VCCNVM P2 GNDNVM GNDNVM GNDNVM GNDNVM P3 GNDA GNDA GNDA GNDA P4 NC NC AC0 AC0 P5 NC NC AG1 AG1 P6 NC NC AV1 AV1 P7 AG0 AG0 AG2 AG2 P8 AG2 AG2 AG4 AG4 P9 GNDA GNDA GNDA GNDA P10 NC AC5 AC7 AC7 P11 NC NC AV8 AV8 P12 NC NC AG8 AG8 P13 NC NC AV9 AV9 P14 ADCGNDREF ADCGNDREF ADCGNDREF ADCGNDREF P15 PTBASE PTBASE PTBASE PTBASE P16 GNDNVM GNDNVM GNDNVM GNDNVM R1 V CCIB3 V CCIB3 V CCIB4 V CCIB4 R2 PCAP PCAP PCAP PCAP R3 NC NC AT1 AT1 R4 NC NC AT0 AT0 256-Pin FBGA Pin Number AFS090 Function AFS250 Func tion AFS600 Function AFS1500 Function

4-18 Preliminary v1.7 R 5 A V 0A V 0A V 2A V 2 R6 AT0 AT0 AT2 AT2 R 7 A V 1A V 1A V 3A V 3 R8 AT3 AT3 AT5 AT5 R 9 A V 4A V 4A V 6A V 6 R10 NC AT5 AT7 AT7 R11 NC AV5 AV7 AV7 R12 NC NC AT9 AT9 R13 NC NC AG9 AG9 R14 NC NC AC9 AC9 R15 PUB PUB PUB PUB R16 V CCIB1 V CCIB1 V CCIB2 V CCIB2 T1 GND GND GND GND T2 NCAP NCAP NCAP NCAP T3 VCC33N VCC33N VCC33N VCC33N T4 NC NC ATRTN0 ATRTN0 T5 AT1 AT1 AT3 AT3 T6 ATRTN0 ATRTN0 ATRTN1 ATRTN1 T7 AT2 AT2 AT4 AT4 T8 ATRTN1 ATRTN1 ATRTN2 ATRTN2 T9 AT4 AT4 AT6 AT6 T10 ATRTN2 ATRTN2 ATRTN3 ATRTN3 T11 NC NC AT8 AT8 T12 NC NC ATRTN4 ATRTN4 T13 GNDA GNDA GNDA GNDA T14 V CC33A VCC33A VCC33A VCC33A T15 VAREF VAREF VAREF VAREF T16 GND GND GND GND 256-Pin FBGA Pin Number AFS090 Function AFS250 Func tion AFS600 Function AFS1500 Function

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 4-19 484-Pin FBGA Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/default.aspx. A B C D E F G H J K L M N P R T U V W Y AA AB 12345678910111213141516171819202122 A1 Ball Pad Corner

4-20 Preliminary v1.7 484-Pin FBGA Pin Number AFS600 Func tion AFS1500 Function A1 GND GND A2 V CC NC A3 GAA1/IO01PDB0V0 GAA1/IO01PDB0V0 A4 GAB0/IO02NDB0V0 GAB0/IO02NDB0V0 A5 GAB1/IO02PDB0V0 GAB1/IO02PDB0V0 A6 IO07NDB0V1 IO07NDB0V1 A7 IO07PDB0V1 IO07PDB0V1 A8 IO10PDB0V1 IO09PDB0V1 A9 IO14NDB0V1 IO13NDB0V2 A10 IO14PDB0V1 IO13PDB0V2 A11 IO17PDB1V0 IO24PDB1V0 A12 IO18PDB1V0 IO26PDB1V0 A13 IO19NDB1V0 IO27NDB1V1 A14 IO19PDB1V0 IO27PDB1V1 A15 IO24NDB1V1 IO35NDB1V2 A16 IO24PDB1V1 IO35PDB1V2 A17 GBC0/IO26NDB1V1 GBC0/IO40NDB1V2 A18 GBA0/IO28NDB1V1 GBA0/IO42NDB1V2 A19 IO29NDB1V1 IO43NDB1V2 A20 IO29PDB1V1 IO43PDB1V2 A21 V CC NC A22 GND GND AA1 V CC NC AA2 GND GND AA3 V CCIB4 V CCIB4 AA4 V CCIB4 V CCIB4 AA5 PCAP PCAP AA6 AG0 AG0 AA7 GNDA GNDA AA8 AG1 AG1 AA9 AG2 AG2 AA10 GNDA GNDA AA11 AG3 AG3 AA12 AG6 AG6 AA13 GNDA GNDA AA14 AG7 AG7 AA15 AG8 AG8 AA16 GNDA GNDA AA17 AG9 AG9 AA18 VAREF VAREF AA19 V CCIB2 V CCIB2 AA20 PTEM PTEM AA21 GND GND AA22 V CC NC AB1 GND GND AB2 V CC NC AB3 NC IO94NSB4V0 AB4 GND GND AB5 VCC33N VCC33N AB6 AT0 AT0 AB7 ATRTN0 ATRTN0 AB8 AT1 AT1 AB9 AT2 AT2 AB10 ATRTN1 ATRTN1 AB11 AT3 AT3 AB12 AT6 AT6 AB13 ATRTN3 ATRTN3 AB14 AT7 AT7 AB15 AT8 AT8 AB16 ATRTN4 ATRTN4 AB17 AT9 AT9 AB18 V CC33A VCC33A AB19 GND GND AB20 NC IO76NPB2V0 AB21 V CC NC AB22 GND GND B1 V CC NC B2 GND GND B3 GAA0/IO01NDB0V0 GAA0/IO01NDB0V0 B4 GND GND B5 IO05NDB0V0 IO04NDB0V0 B6 IO05PDB0V0 IO04PDB0V0 484-Pin FBGA Pin Number AFS600 Function AFS1500 Function

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 4-21 B7 GND GND B8 IO10NDB0V1 IO09NDB0V1 B9 IO13PDB0V1 IO11PDB0V1 B10 GND GND B11 IO17NDB1V0 IO24NDB1V0 B12 IO18NDB1V0 IO26NDB1V0 B13 GND GND B14 IO21NDB1V0 IO31NDB1V1 B15 IO21PDB1V0 IO31PDB1V1 B16 GND GND B17 GBC1/IO26PDB1V1 GBC1/IO40PDB1V2 B18 GBA1/IO28PDB1V1 GBA1/IO42PDB1V2 B19 GND GND B20 V CCPLB VCCPLB B21 GND GND B22 V CC NC C1 IO82PDB4V0 IO121PDB4V0 C2 NC IO122PSB4V0 C3 IO00NDB0V0 IO00NDB0V0 C4 IO00PDB0V0 IO00PDB0V0 C5 V CCIB0 V CCIB0 C6 IO06NDB0V0 IO05NDB0V1 C7 IO06PDB0V0 IO05PDB0V1 C8 V CCIB0 V CCIB0 C9 IO13NDB0V1 IO11NDB0V1 C10 IO11PDB0V1 IO14PDB0V2 C11 V CCIB0 V CCIB0 C12 V CCIB1 V CCIB1 C13 IO20NDB1V0 IO29NDB1V1 C14 IO20PDB1V0 IO29PDB1V1 C15 V CCIB1 V CCIB1 C16 IO25NDB1V1 IO37NDB1V2 C17 GBB0/IO27NDB1V1 GBB0/IO41NDB1V2 C18 V CCIB1 V CCIB1 C19 V COMPLB VCOMPLB C20 GBA2/IO30PDB2V0 GBA2/IO44PDB2V0 484-Pin FBGA Pin Number AFS600 Func tion AFS1500 Function C21 NC IO48PSB2V0 C22 GBB2/IO31PDB2V0 GBB2/IO45PDB2V0 D1 IO82NDB4V0 IO121NDB4V0 D2 GND GND D3 IO83NDB4V0 IO123NDB4V0 D4 GAC2/IO83PDB4V0 GAC2/IO123PDB4V D5 GAA2/IO85PDB4V0 GAA2/IO125PDB4V D6 GAC0/IO03NDB0V 0 GAC0/IO03NDB0V0 D7 GAC1/IO03PDB0V0 GAC1/IO03PDB0V0 D8 IO09NDB0V1 IO10NDB0V1 D9 IO09PDB0V1 IO10PDB0V1 D10 IO11NDB0V1 IO14NDB0V2 D11 IO16NDB1V0 IO23NDB1V0 D12 IO16PDB1V0 IO23PDB1V0 D13 NC IO32NPB1V1 D14 IO23NDB1V1 IO34NDB1V1 D15 IO23PDB1V1 IO34PDB1V1 D16 IO25PDB1V1 IO37PDB1V2 D17 GBB1/IO27PDB1V1 GBB1/IO41PDB1V2 D18 V CCIB2 V CCIB2 D19 NC IO47PPB2V0 D20 IO30NDB2V0 IO44NDB2V0 D21 GND GND D22 IO31NDB2V0 IO45NDB2V0 E1 IO81NDB4V0 IO120NDB4V0 E2 IO81PDB4V0 IO120PDB4V0 E3 V CCIB4 V CCIB4 E4 GAB2/IO84PDB4V0 GAB2/IO124PDB4V E5 IO85NDB4V0 IO125NDB4V0 E6 GND GND E7 V CCIB0 V CCIB0 E8 NC IO08NDB0V1 E9 NC IO08PDB0V1 E10 GND GND 484-Pin FBGA Pin Number AFS600 Function AFS1500 Function

4-22 Preliminary v1.7 E11 IO15NDB1V0 IO22NDB1V0 E12 IO15PDB1V0 IO22PDB1V0 E13 GND GND E14 NC IO32PPB1V1 E15 NC IO36NPB1V2 E16 V CCIB1 V CCIB1 E17 GND GND E18 NC IO47NPB2V0 E19 IO33PDB2V0 IO49PDB2V0 E20 V CCIB2 V CCIB2 E21 IO32NDB2V0 IO46NDB2V0 E22 GBC2/IO32PDB2V0 GBC2/IO46PDB2V0 F1 IO80NDB4V0 IO118NDB4V0 F2 IO80PDB4V0 IO118PDB4V0 F3 NC IO119NSB4V0 F4 IO84NDB4V0 IO124NDB4V0 F5 GND GND F6 V COMPLA VCOMPLA F7 V CCPLA VCCPLA F8 V CCIB0 V CCIB0 F9 IO08NDB0V1 IO12NDB0V1 F10 IO08PDB0V1 IO12PDB0V1 F11 V CCIB0 V CCIB0 F12 V CCIB1 V CCIB1 F13 IO22NDB1V0 IO30NDB1V1 F14 IO22PDB1V0 IO30PDB1V1 F15 V CCIB1 V CCIB1 F16 NC IO36PPB1V2 F17 NC IO38NPB1V2 F18 GND GND F19 IO33NDB2V0 IO49NDB2V0 F20 IO34PDB2V0 IO50PDB2V0 F21 IO34NDB2V0 IO50NDB2V0 F22 IO35PDB2V0 IO51PDB2V0 G1 IO77PDB4V0 IO115PDB4V0 G2 GND GND 484-Pin FBGA Pin Number AFS600 Func tion AFS1500 Function G3 IO78NDB4V0 IO116NDB4V0 G4 IO78PDB4V0 IO116PDB4V0 G5 V CCIB4 V CCIB4 G6 NC IO117PDB4V0 G7 V CCIB4 V CCIB4 G8 GND GND G9 IO04NDB0V0 IO06NDB0V1 G10 IO04PDB0V0 IO06PDB0V1 G11 IO12NDB0V1 IO16NDB0V2 G12 IO12PDB0V1 IO16PDB0V2 G13 NC IO28NDB1V1 G14 NC IO28PDB1V1 G15 GND GND G16 NC IO38PPB1V2 G17 NC IO53PDB2V0 G18 V CCIB2 V CCIB2 G19 IO36PDB2V0 IO52PDB2V0 G20 IO36NDB2V0 IO52NDB2V0 G21 GND GND G22 IO35NDB2V0 IO51NDB2V0 H1 IO77NDB4V0 IO115NDB4V0 H2 IO76PDB4V0 IO113PDB4V0 H3 V CCIB4 V CCIB4 H4 IO79NDB4V0 IO114NDB4V0 H5 IO79PDB4V0 IO114PDB4V0 H6 NC IO117NDB4V0 H7 GND GND H8 V CC VCC H9 V CCIB0 V CCIB0 H10 GND GND H11 V CCIB0 V CCIB0 H12 V CCIB1 V CCIB1 H13 GND GND H14 V CCIB1 V CCIB1 H15 GND GND H16 GND GND 484-Pin FBGA Pin Number AFS600 Function AFS1500 Function

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 4-23 H17 NC IO53NDB2V0 H18 IO38PDB2V0 IO57PDB2V0 H19 GCA2/IO39PDB2V0 GCA2/IO59PDB2V0 H20 V CCIB2 V CCIB2 H21 IO37NDB2V0 IO54NDB2V0 H22 IO37PDB2V0 IO54PDB2V0 J1 NC IO112PPB4V0 J2 IO76NDB4V0 IO113NDB4V0 J3 GFB2/IO74PDB4V0 GFB2/IO109PDB4V0 J4 GFA2/IO75PDB4V0 GFA2/IO110PDB4V J5 NC IO112NPB4V0 J6 NC IO104PDB4V0 J7 NC IO111PDB4V0 J8 V CCIB4 V CCIB4 J9 GND GND J10 V CC VCC J11 GND GND J12 V CC VCC J13 GND GND J14 V CC VCC J15 V CCIB2 V CCIB2 J16 GCB2/IO40PDB2V0 GCB2/IO60PDB2V0 J17 NC IO58NDB2V0 J18 IO38NDB2V0 IO57NDB2V0 J19 IO39NDB2V0 IO59NDB2V0 J20 GCC2/IO41PDB2V0 GCC2/IO61PDB2V0 J21 NC IO55PSB2V0 J22 IO42PDB2V0 IO56PDB2V0 K1 GFC2/IO73PDB4V0 GFC2/IO108PDB4V0 K2 GND GND K3 IO74NDB4V0 IO109NDB4V0 K4 IO75NDB4V0 IO110NDB4V0 K5 GND GND K6 NC IO104NDB4V0 K7 NC IO111NDB4V0 484-Pin FBGA Pin Number AFS600 Func tion AFS1500 Function K8 GND GND K9 V CC VCC K10 GND GND K11 V CC VCC K12 GND GND K13 V CC VCC K14 GND GND K15 GND GND K16 IO40NDB2V0 IO60NDB2V0 K17 NC IO58PDB2V0 K18 GND GND K19 NC IO68NPB2V0 K20 IO41NDB2V0 IO61NDB2V0 K21 GND GND K22 IO42NDB2V0 IO56NDB2V0 L1 IO73NDB4V0 IO108NDB4V0 L2 V CCOSC VCCOSC L3 V CCIB4 V CCIB4 L4 XTAL2 XTAL2 L5 GFC1/IO72PDB4V0 GFC1/IO107PDB4V0 L6 V CCIB4 V CCIB4 L7 GFB1/IO71PDB4V0 GFB1/IO106PDB4V0 L8 V CCIB4 V CCIB4 L9 GND GND L10 V CC VCC L11 GND GND L12 V CC VCC L13 GND GND L14 V CC VCC L15 V CCIB2 V CCIB2 L16 IO48PDB2V0 IO70PDB2V0 L17 V CCIB2 V CCIB2 L18 IO46PDB2V0 IO69PDB2V0 L19 GCA1/IO45PDB2V0 GCA1/IO64PDB2V0 L20 V CCIB2 V CCIB2 L21 GCC0/IO43NDB2V0 GCC0/IO62NDB2V0 484-Pin FBGA Pin Number AFS600 Function AFS1500 Function

4-24 Preliminary v1.7 L22 GCC1/IO43PDB2V0 GCC1/IO62PDB2V0 M1 NC IO103PDB4V0 M2 XTAL1 XTAL1 M3 V CCIB4 V CCIB4 M4 GNDOSC GNDOSC M5 GFC0/IO72NDB4V0 GFC0/IO107NDB4V M6 V CCIB4 V CCIB4 M7 GFB0/IO71NDB4V0 GFB0/IO106NDB4V M8 V CCIB4 V CCIB4 M9 V CC VCC M10 GND GND M11 V CC VCC M12 GND GND M13 V CC VCC M14 GND GND M15 V CCIB2 V CCIB2 M16 IO48NDB2V0 IO70NDB2V0 M17 V CCIB2 V CCIB2 M18 IO46NDB2V0 IO69NDB2V0 M19 GCA0/IO45NDB2V0 GCA0/IO64NDB2V0 M20 V CCIB2 V CCIB2 M21 GCB0/IO44NDB2V0 GCB0/IO63NDB2V0 M22 GCB1/IO44PDB2V0 GCB1/IO63PDB2V0 N1 NC IO103NDB4V0 N2 GND GND N3 IO68PDB4V0 IO101PDB4V0 N4 NC IO100NPB4V0 N5 GND GND N6 NC IO99PDB4V0 N7 NC IO97PDB4V0 N8 GND GND N9 GND GND N10 V CC VCC N11 GND GND 484-Pin FBGA Pin Number AFS600 Func tion AFS1500 Function N12 V CC VCC N13 GND GND N14 V CC VCC N15 GND GND N16 GDB2/IO56PDB2V0 GDB2/IO83PDB2V0 N17 NC IO78PDB2V0 N18 GND GND N19 IO47NDB2V0 IO72NDB2V0 N20 IO47PDB2V0 IO72PDB2V0 N21 GND GND N22 IO49PDB2V0 IO71PDB2V0 P1 GFA1/IO70PDB4V0 GFA1/IO105PDB4V P2 GFA0/IO70NDB4V0 GFA0/IO105NDB4V P3 IO68NDB4V0 IO101NDB4V0 P4 IO65PDB4V0 IO96PDB4V0 P5 IO65NDB4V0 IO96NDB4V0 P6 NC IO99NDB4V0 P7 NC IO97NDB4V0 P8 V CCIB4 V CCIB4 P9 V CC VCC P10 GND GND P11 V CC VCC P12 GND GND P13 V CC VCC P14 GND GND P15 V CCIB2 V CCIB2 P16 IO56NDB2V0 IO83NDB2V0 P17 NC IO78NDB2V0 P18 GDA1/IO54PDB2V0 GDA1/IO81PDB2V0 P19 GDB1/IO53PDB2V0 GDB1/IO80PDB2V0 P20 IO51NDB2V0 IO73NDB2V0 P21 IO51PDB2V0 IO73PDB2V0 P22 IO49NDB2V0 IO71NDB2V0 R1 IO69PDB4V0 IO102PDB4V0 484-Pin FBGA Pin Number AFS600 Function AFS1500 Function

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 4-25 R2 IO69NDB4V0 IO102NDB4V0 R3 V CCIB4 V CCIB4 R4 IO64PDB4V0 IO91PDB4V0 R5 IO64NDB4V0 IO91NDB4V0 R6 NC IO92PDB4V0 R7 GND GND R8 GND GND R9 V CC33A VCC33A R10 GNDA GNDA R11 V CC33A VCC33A R12 GNDA GNDA R13 V CC33A VCC33A R14 GNDA GNDA R15 V CC VCC R16 GND GND R17 NC IO74NDB2V0 R18 GDA0/IO54NDB2V0 GDA0/IO81NDB2V0 R19 GDB0/IO53NDB2V0 GDB0/IO80NDB2V0 R20 V CCIB2 V CCIB2 R21 IO50NDB2V0 IO75NDB2V0 R22 IO50PDB2V0 IO75PDB2V0 T1 NC IO100PPB4V0 T2 GND GND T3 IO66PDB4V0 IO95PDB4V0 T4 IO66NDB4V0 IO95NDB4V0 T5 V CCIB4 V CCIB4 T6 NC IO92NDB4V0 T7 GNDNVM GNDNVM T8 GNDA GNDA T9 NC NC T10 AV4 AV4 T11 NC NC T12 AV5 AV5 T13 AC5 AC5 T14 NC NC T15 GNDA GNDA 484-Pin FBGA Pin Number AFS600 Func tion AFS1500 Function T16 NC IO77PPB2V0 T17 NC IO74PDB2V0 T18 V CCIB2 V CCIB2 T19 IO55NDB2V0 IO82NDB2V0 T20 GDA2/IO55PDB2V0 GDA2/IO82PDB2V0 T21 GND GND T22 GDC1/IO52PDB2V0 GDC1/IO79PDB2V0 U1 IO67PDB4V0 IO98PDB4V0 U2 IO67NDB4V0 IO98NDB4V0 U3 GEC1/IO63PDB4V0 GEC1/IO90PDB4V0 U4 GEC0/IO63NDB4V0 GEC0/IO90NDB4V0 U5 GND GND U6 V CCNVM VCCNVM U7 V CCIB4 V CCIB4 U8 V CC15A VCC15A U9 GNDA GNDA U10 AC4 AC4 U11 V CC33A VCC33A U12 GNDA GNDA U13 AG5 AG5 U14 GNDA GNDA U15 PUB PUB U16 V CCIB2 V CCIB2 U17 TDI TDI U18 GND GND U19 IO57NDB2V0 IO84NDB2V0 U20 GDC2/IO57PDB2V0 GDC2/IO84PDB2V0 U21 NC IO77NPB2V0 U22 GDC0/IO52NDB2V0 GDC0/IO79NDB2V0 V1 GEB1/IO62PDB4V0 GEB1/IO89PDB4V0 V2 GEB0/IO62NDB4V0 GEB0/IO89NDB4V0 V3 V CCIB4 V CCIB4 V4 GEA1/IO61PDB4V0 GEA1/IO88PDB4V0 V5 GEA0/IO61NDB4V0 GEA0/IO88NDB4V0 V6 GND GND V7 V CC33PMP VCC33PMP 484-Pin FBGA Pin Number AFS600 Function AFS1500 Function

4-26 Preliminary v1.7 V8 NC NC V9 V CC33A VCC33A V10 AG4 AG4 V11 AT4 AT4 V12 ATRTN2 ATRTN2 V13 AT5 AT5 V14 V CC33A VCC33A V15 NC NC V16 V CC33A VCC33A V17 GND GND V18 TMS TMS V19 V JTAG VJTAG V20 V CCIB2 V CCIB2 V21 TRST TRST V22 TDO TDO W1 NC IO93PDB4V0 W2 GND GND W3 NC IO93NDB4V0 W4 GEB2/IO59PDB4V0 GEB2/IO86PDB4V0 W5 IO59NDB4V0 IO86NDB4V0 W6 AV0 AV0 W7 GNDA GNDA W8 AV1 AV1 W9 AV2 AV2 W10 GNDA GNDA W11 AV3 AV3 W12 AV6 AV6 W13 GNDA GNDA W14 AV7 AV7 W15 AV8 AV8 W16 GNDA GNDA W17 AV9 AV9 W18 V CCIB2 V CCIB2 W19 NC IO68PPB2V0 W20 TCK TCK W21 GND GND 484-Pin FBGA Pin Number AFS600 Func tion AFS1500 Function W22 NC IO76PPB2V0 Y1 GEC2/IO60PDB4V0 GEC2/IO87PDB4V0 Y2 IO60NDB4V0 IO87NDB4V0 Y3 GEA2/IO58PDB4V0 GEA2/IO85PDB4V0 Y4 IO58NDB4V0 IO85NDB4V0 Y5 NCAP NCAP Y6 AC0 AC0 Y7 V CC33A VCC33A Y8 AC1 AC1 Y9 AC2 AC2 Y10 V CC33A VCC33A Y11 AC3 AC3 Y12 AC6 AC6 Y13 V CC33A VCC33A Y14 AC7 AC7 Y15 AC8 AC8 Y16 V CC33A VCC33A Y17 AC9 AC9 Y18 ADCGNDREF ADCGNDREF Y19 PTBASE PTBASE Y20 GNDNVM GNDNVM Y21 V CCNVM VCCNVM Y22 V PUMP VPUMP 484-Pin FBGA Pin Number AFS600 Function AFS1500 Function

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 4-27 676-Pin FBGA Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/default.aspx. A1 Ball Pad Corner A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1234567891011121314151617181920212223242526

4-28 Preliminary v1.7 676-Pin FBGA Pin Number AFS1500 Function A1 NC A2 GND A3 NC A4 NC A5 GND A6 NC A7 NC A8 GND A9 IO17NDB0V2 A10 IO17PDB0V2 A11 GND A12 IO18NDB0V2 A13 IO18PDB0V2 A14 IO20NDB0V2 A15 IO20PDB0V2 A16 GND A17 IO21PDB0V2 A18 IO21NDB0V2 A19 GND A20 IO39NDB1V2 A21 IO39PDB1V2 A22 GND A23 NC A24 NC A25 GND A26 NC AA1 NC AA2 V CCIB4 AA3 IO93PDB4V0 AA4 GND AA5 IO93NDB4V0 AA6 GEB2/IO86PDB4V0 AA7 IO86NDB4V0 AA8 AV0 AA9 GNDA AA10 AV1 AA11 AV2 AA12 GNDA AA13 AV3 AA14 AV6 AA15 GNDA AA16 AV7 AA17 AV8 AA18 GNDA AA19 AV9 AA20 V CCIB2 AA21 IO68PPB2V0 AA22 TCK AA23 GND AA24 IO76PPB2V0 AA25 V CCIB2 AA26 NC AB1 GND AB2 NC AB3 GEC2/IO87PDB4V0 AB4 IO87NDB4V0 AB5 GEA2/IO85PDB4V0 AB6 IO85NDB4V0 AB7 NCAP AB8 AC0 AB9 V CC33A AB10 AC1 AB11 AC2 AB12 V CC33A AB13 AC3 AB14 AC6 AB15 V CC33A AB16 AC7 AB17 AC8 AB18 V CC33A AB19 AC9 AB20 ADCGNDREF 676-Pin FBGA Pin Number AFS1500 Function AB21 PTBASE AB22 GNDNVM AB23 V CCNVM AB24 V PUMP AB25 NC AB26 GND AC1 NC AC2 NC AC3 NC AC4 GND AC5 V CCIB4 AC6 V CCIB4 AC7 PCAP AC8 AG0 AC9 GNDA AC10 AG1 AC11 AG2 AC12 GNDA AC13 AG3 AC14 AG6 AC15 GNDA AC16 AG7 AC17 AG8 AC18 GNDA AC19 AG9 AC20 VAREF AC21 V CCIB2 AC22 PTEM AC23 GND AC24 NC AC25 NC AC26 NC AD1 NC AD2 NC AD3 GND AD4 NC 676-Pin FBGA Pin Number AFS1500 Function

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 4-29 AD5 IO94NPB4V0 AD6 GND AD7 VCC33N AD8 AT0 AD9 ATRTN0 AD10 AT1 AD11 AT2 AD12 ATRTN1 AD13 AT3 AD14 AT6 AD15 ATRTN3 AD16 AT7 AD17 AT8 AD18 ATRTN4 AD19 AT9 AD20 V CC33A AD21 GND AD22 IO76NPB2V0 AD23 NC AD24 GND AD25 NC AD26 NC AE1 GND AE2 GND AE3 NC AE4 NC AE5 NC AE6 NC AE7 NC AE8 NC AE9 GNDA AE10 NC AE11 NC AE12 GNDA AE13 NC AE14 NC 676-Pin FBGA Pin Number AFS1500 Function AE15 GNDA AE16 NC AE17 NC AE18 GNDA AE19 NC AE20 NC AE21 NC AE22 NC AE23 NC AE24 NC AE25 GND AE26 GND AF1 NC AF2 GND AF3 NC AF4 NC AF5 NC AF6 NC AF7 NC AF8 NC AF9 V CC33A AF10 NC AF11 NC AF12 V CC33A AF13 NC AF14 NC AF15 V CC33A AF16 NC AF17 NC AF18 V CC33A AF19 NC AF20 NC AF21 NC AF22 NC AF23 NC AF24 NC 676-Pin FBGA Pin Number AFS1500 Function AF25 GND AF26 NC B1 GND B2 GND B3 NC B4 NC B5 NC B6 V CCIB0 B7 NC B8 NC B9 V CCIB0 B10 IO15NDB0V2 B11 IO15PDB0V2 B12 V CCIB0 B13 IO19NDB0V2 B14 IO19PDB0V2 B15 V CCIB1 B16 IO25NDB1V0 B17 IO25PDB1V0 B18 V CCIB1 B19 IO33NDB1V1 B20 IO33PDB1V1 B21 V CCIB1 B22 NC B23 NC B24 NC B25 GND B26 GND C1 NC C2 NC C3 GND C4 NC C5 GAA1/IO01PDB0V0 C6 GAB0/IO02NDB0V0 C7 GAB1/IO02PDB0V0 C8 IO07NDB0V1 676-Pin FBGA Pin Number AFS1500 Function

4-30 Preliminary v1.7 C9 IO07PDB0V1 C10 IO09PDB0V1 C11 IO13NDB0V2 C12 IO13PDB0V2 C13 IO24PDB1V0 C14 IO26PDB1V0 C15 IO27NDB1V1 C16 IO27PDB1V1 C17 IO35NDB1V2 C18 IO35PDB1V2 C19 GBC0/IO40NDB1V2 C20 GBA0/IO42NDB1V2 C21 IO43NDB1V2 C22 IO43PDB1V2 C23 NC C24 GND C25 NC C26 NC D1 NC D2 NC D3 NC D4 GND D5 GAA0/IO01NDB0V0 D6 GND D7 IO04NDB0V0 D8 IO04PDB0V0 D9 GND D10 IO09NDB0V1 D11 IO11PDB0V1 D12 GND D13 IO24NDB1V0 D14 IO26NDB1V0 D15 GND D16 IO31NDB1V1 D17 IO31PDB1V1 D18 GND 676-Pin FBGA Pin Number AFS1500 Function D19 GBC1/IO40PDB1V2 D20 GBA1/IO42PDB1V2 D21 GND D22 V CCPLB D23 GND D24 NC D25 NC D26 NC E1 GND E2 IO122NPB4V0 E3 IO121PDB4V0 E4 IO122PPB4V0 E5 IO00NDB0V0 E6 IO00PDB0V0 E7 V CCIB0 E8 IO05NDB0V1 E9 IO05PDB0V1 E10 V CCIB0 E11 IO11NDB0V1 E12 IO14PDB0V2 E13 V CCIB0 E14 V CCIB1 E15 IO29NDB1V1 E16 IO29PDB1V1 E17 V CCIB1 E18 IO37NDB1V2 E19 GBB0/IO41NDB1V2 E20 V CCIB1 E21 V COMPLB E22 GBA2/IO44PDB2V0 E23 IO48PPB2V0 E24 GBB2/IO45PDB2V0 E25 NC E26 GND F1 NC F2 V CCIB4 676-Pin FBGA Pin Number AFS1500 Function F3 IO121NDB4V0 F4 GND F5 IO123NDB4V0 F6 GAC2/IO123PDB4V0 F7 GAA2/IO125PDB4V0 F8 GAC0/IO03NDB0V0 F9 GAC1/IO03PDB0V0 F10 IO10NDB0V1 F11 IO10PDB0V1 F12 IO14NDB0V2 F13 IO23NDB1V0 F14 IO23PDB1V0 F15 IO32NPB1V1 F16 IO34NDB1V1 F17 IO34PDB1V1 F18 IO37PDB1V2 F19 GBB1/IO41PDB1V2 F20 V CCIB2 F21 IO47PPB2V0 F22 IO44NDB2V0 F23 GND F24 IO45NDB2V0 F25 V CCIB2 F26 NC G1 NC G2 IO119PPB4V0 G3 IO120NDB4V0 G4 IO120PDB4V0 G5 V CCIB4 G6 GAB2/IO124PDB4V0 G7 IO125NDB4V0 G8 GND G9 V CCIB0 G10 IO08NDB0V1 G11 IO08PDB0V1 G12 GND 676-Pin FBGA Pin Number AFS1500 Function

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 4-31 G13 IO22NDB1V0 G14 IO22PDB1V0 G15 GND G16 IO32PPB1V1 G17 IO36NPB1V2 G18 V CCIB1 G19 GND G20 IO47NPB2V0 G21 IO49PDB2V0 G22 V CCIB2 G23 IO46NDB2V0 G24 GBC2/IO46PDB2V0 G25 IO48NPB2V0 G26 NC H1 GND H2 NC H3 IO118NDB4V0 H4 IO118PDB4V0 H5 IO119NPB4V0 H6 IO124NDB4V0 H7 GND H8 V COMPLA H9 V CCPLA H10 V CCIB0 H11 IO12NDB0V1 H12 IO12PDB0V1 H13 V CCIB0 H14 V CCIB1 H15 IO30NDB1V1 H16 IO30PDB1V1 H17 V CCIB1 H18 IO36PPB1V2 H19 IO38NPB1V2 H20 GND H21 IO49NDB2V0 H22 IO50PDB2V0 676-Pin FBGA Pin Number AFS1500 Function H23 IO50NDB2V0 H24 IO51PDB2V0 H25 NC H26 GND J1 NC J2 V CCIB4 J3 IO115PDB4V0 J4 GND J5 IO116NDB4V0 J6 IO116PDB4V0 J7 V CCIB4 J8 IO117PDB4V0 J9 V CCIB4 J10 GND J11 IO06NDB0V1 J12 IO06PDB0V1 J13 IO16NDB0V2 J14 IO16PDB0V2 J15 IO28NDB1V1 J16 IO28PDB1V1 J17 GND J18 IO38PPB1V2 J19 IO53PDB2V0 J20 V CCIB2 J21 IO52PDB2V0 J22 IO52NDB2V0 J23 GND J24 IO51NDB2V0 J25 V CCIB2 J26 NC K1 NC K2 NC K3 IO115NDB4V0 K4 IO113PDB4V0 K5 V CCIB4 K6 IO114NDB4V0 676-Pin FBGA Pin Number AFS1500 Function K7 IO114PDB4V0 K8 IO117NDB4V0 K9 GND K10 V CC K11 V CCIB0 K12 GND K13 V CCIB0 K14 V CCIB1 K15 GND K16 V CCIB1 K17 GND K18 GND K19 IO53NDB2V0 K20 IO57PDB2V0 K21 GCA2/IO59PDB2V0 K22 V CCIB2 K23 IO54NDB2V0 K24 IO54PDB2V0 K25 NC K26 NC L1 GND L2 NC L3 IO112PPB4V0 L4 IO113NDB4V0 L5 GFB2/IO109PDB4V0 L6 GFA2/IO110PDB4V0 L7 IO112NPB4V0 L8 IO104PDB4V0 L9 IO111PDB4V0 L10 V CCIB4 L11 GND L12 V CC L13 GND L14 V CC L15 GND L16 V CC 676-Pin FBGA Pin Number AFS1500 Function

4-32 Preliminary v1.7 L17 V CCIB2 L18 GCB2/IO60PDB2V0 L19 IO58NDB2V0 L20 IO57NDB2V0 L21 IO59NDB2V0 L22 GCC2/IO61PDB2V0 L23 IO55PPB2V0 L24 IO56PDB2V0 L25 IO55NPB2V0 L26 GND M1 NC M2 V CCIB4 M3 GFC2/IO108PDB4V0 M4 GND M5 IO109NDB4V0 M6 IO110NDB4V0 M7 GND M8 IO104NDB4V0 M9 IO111NDB4V0 M10 GND M11 V CC M12 GND M13 V CC M14 GND M15 V CC M16 GND M17 GND M18 IO60NDB2V0 M19 IO58PDB2V0 M20 GND M21 IO68NPB2V0 M22 IO61NDB2V0 M23 GND M24 IO56NDB2V0 M25 V CCIB2 M26 IO65PDB2V0 676-Pin FBGA Pin Number AFS1500 Function N1 NC N2 NC N3 IO108NDB4V0 N4 V CCOSC N5 V CCIB4 N6 XTAL2 N7 GFC1/IO107PDB4V0 N8 V CCIB4 N9 GFB1/IO106PDB4V0 N10 V CCIB4 N11 GND N12 V CC N13 GND N14 V CC N15 GND N16 V CC N17 V CCIB2 N18 IO70PDB2V0 N19 V CCIB2 N20 IO69PDB2V0 N21 GCA1/IO64PDB2V0 N22 V CCIB2 N23 GCC0/IO62NDB2V0 N24 GCC1/IO62PDB2V0 N25 IO66PDB2V0 N26 IO65NDB2V0 P1 NC P2 NC P3 IO103PDB4V0 P4 XTAL1 P5 V CCIB4 P6 GNDOSC P7 GFC0/IO107NDB4V0 P8 V CCIB4 P9 GFB0/IO106NDB4V0 P10 V CCIB4 676-Pin FBGA Pin Number AFS1500 Function P11 V CC P12 GND P13 V CC P14 GND P15 V CC P16 GND P17 V CCIB2 P18 IO70NDB2V0 P19 V CCIB2 P20 IO69NDB2V0 P21 GCA0/IO64NDB2V0 P22 V CCIB2 P23 GCB0/IO63NDB2V0 P24 GCB1/IO63PDB2V0 P25 IO66NDB2V0 P26 IO67PDB2V0 R1 NC R2 V CCIB4 R3 IO103NDB4V0 R4 GND R5 IO101PDB4V0 R6 IO100NPB4V0 R7 GND R8 IO99PDB4V0 R9 IO97PDB4V0 R10 GND R11 GND R12 V CC R13 GND R14 V CC R15 GND R16 V CC R17 GND R18 GDB2/IO83PDB2V0 R19 IO78PDB2V0 R20 GND 676-Pin FBGA Pin Number AFS1500 Function

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 4-33 R21 IO72NDB2V0 R22 IO72PDB2V0 R23 GND R24 IO71PDB2V0 R25 V CCIB2 R26 IO67NDB2V0 T1 GND T2 NC T3 GFA1/IO105PDB4V0 T4 GFA0/IO105NDB4V0 T5 IO101NDB4V0 T6 IO96PDB4V0 T7 IO96NDB4V0 T8 IO99NDB4V0 T9 IO97NDB4V0 T10 V CCIB4 T11 V CC T12 GND T13 V CC T14 GND T15 V CC T16 GND T17 V CCIB2 T18 IO83NDB2V0 T19 IO78NDB2V0 T20 GDA1/IO81PDB2V0 T21 GDB1/IO80PDB2V0 T22 IO73NDB2V0 T23 IO73PDB2V0 T24 IO71NDB2V0 T25 NC T26 GND U1 NC U2 NC U3 IO102PDB4V0 U4 IO102NDB4V0 676-Pin FBGA Pin Number AFS1500 Function U5 V CCIB4 U6 IO91PDB4V0 U7 IO91NDB4V0 U8 IO92PDB4V0 U9 GND U10 GND U11 V CC33A U12 GNDA U13 V CC33A U14 GNDA U15 V CC33A U16 GNDA U17 V CC U18 GND U19 IO74NDB2V0 U20 GDA0/IO81NDB2V0 U21 GDB0/IO80NDB2V0 U22 V CCIB2 U23 IO75NDB2V0 U24 IO75PDB2V0 U25 NC U26 NC V1 NC V2 V CCIB4 V3 IO100PPB4V0 V4 GND V5 IO95PDB4V0 V6 IO95NDB4V0 V7 V CCIB4 V8 IO92NDB4V0 V9 GNDNVM V10 GNDA V11 NC V12 AV4 V13 NC V14 AV5 676-Pin FBGA Pin Number AFS1500 Function V15 AC5 V16 NC V17 GNDA V18 IO77PPB2V0 V19 IO74PDB2V0 V20 V CCIB2 V21 IO82NDB2V0 V22 GDA2/IO82PDB2V0 V23 GND V24 GDC1/IO79PDB2V0 V25 V CCIB2 V26 NC W1 GND W2 IO94PPB4V0 W3 IO98PDB4V0 W4 IO98NDB4V0 W5 GEC1/IO90PDB4V0 W6 GEC0/IO90NDB4V0 W7 GND W8 V CCNVM W9 VCCIB4 W10 V CC15A W11 GNDA W12 AC4 W13 V CC33A W14 GNDA W15 AG5 W16 GNDA W17 PUB W18 V CCIB2 W19 TDI W20 GND W21 IO84NDB2V0 W22 GDC2/IO84PDB2V0 W23 IO77NPB2V0 W24 GDC0/IO79NDB2V0 676-Pin FBGA Pin Number AFS1500 Function

4-34 Preliminary v1.7 W25 NC W26 GND Y1 NC Y2 NC Y3 GEB1/IO89PDB4V0 Y4 GEB0/IO89NDB4V0 Y5 V CCIB4 Y6 GEA1/IO88PDB4V0 Y7 GEA0/IO88NDB4V0 Y8 GND Y9 V CC33PMP Y10 NC Y11 V CC33A Y12 AG4 Y13 AT4 Y14 ATRTN2 Y15 AT5 Y16 V CC33A Y17 NC Y18 V CC33A Y19 GND Y20 TMS Y21 V JTAG Y22 VCCIB2 Y23 TRST Y24 TDO Y25 NC Y26 NC 676-Pin FBGA Pin Number AFS1500 Function

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 4-35 Part Number and Revision Date Part Number 51700092-016-0 Revised October 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version Changes in Curren t Version (Preliminary v1.7) Page Advance v1.6 (August 2008) The version number catego ry was changed from Advance to Preliminary, which means the datasheet contains information based on simulation and/or initial characterization. The information is be lieved to be correct, but changes are possible. N/A Advance v1.4 (July 2008) The title of the datasheet changed fro m Actel Programmable System Chips to Actel Fusion Mixed-Signal FPGAs. In addition, all instances of programmable system chip were changed to mixed-signal FPGA. N/A Advance v1.1 (May 2008) The "108-Pin QFN"figure was updated. D1 to D4 are new and the figure was changed to bottom view. The note below the figure is new. 4-1 The "180-Pin QFN"figure was updated. D1 to D4 are new and the figure was changed to bottom view. The note below the figure is new. 4-3 Advance v0.9 October 2007 This change table states that in the "208-Pin PQFP" table listed under the Advance v0.8 changes, the AFS090 device had a pin change. That is incorrect. Pin 102 was updated for AFS250 and AFS 600. The function name changed from VCC33ACAP to VCC33A. 4-8 Advance v0.8 (June 2007) In the "108-Pin QFN" table, the function changed from V CC33ACAP to VCC33A for the following pin: B25 4-2 In the "180-Pin QFN" table, the function changed from V CC33ACAP to VCC33A for the following pins: AFS090: B29 AFS250: B29 4-4 In the "208-Pin PQFP" table, the function changed from V CC33ACAP to VCC33A for the following pins: AFS090: 102 AFS250: 102 4-8 In the "256-Pin FBGA" table, the function changed from VCC33ACAP to VCC33A for the following pins: AFS090: T14 AFS250: T14 AFS600: T14 AFS1500: T14 4-12 In the "484-Pin FBGA" table, the function changed from V CC33ACAP to VCC33A for the following pins: AFS600: AB18 AFS1500: AB18 4-20 In the "676-Pin FBGA" table, the function changed from VCC33ACAP to VCC33A for the following pins: AFS1500: AD20 4-28

4-36 Preliminary v1.7 Advance v0.7 (January 2007) The VMV pins have now been tied internally with the VCCI pins. N/A The AFS090"108-Pin QFN" table was updated. 4-2 The AFS090 and AFS250 devices were updated in the "108-Pin QFN" table. 4-2 The AFS250 device was updated in the "208-Pin PQFP" table. 4-8 Advance v0.7 (continued) The AFS600 device was updated in the "208-Pin PQFP" table. 4-8 The AFS090, AFS250, AFS600, and AFS1500 devices were updated in the "256-Pin FBGA" table. 4-12 The AFS600 and AFS1500 devices were updated in the "484-Pin FBGA" table. 4-20 The AFS600 device was updated in the "676-Pin FBGA" table. 4-28 Advance v0.5 (June 2006) The heading was incorrect in the "208-Pin PQFP" table. It should be AFS250 and not AFS090. 4-8 Advance v0.4 (April 2006) The "256-Pin FBGA" table for the AFS1500 is new. 4-12 Advance v0.2 (April 2006) The "108-Pin QFN" table for the AFS090 device is new. 4-2 The "180-Pin QFN" table for the AFS090 device is new. 4-4 The "208-Pin PQFP" table for the AFS090 device is new. 4-8 The "256-Pin FBGA" table for the AFS090 device is new. 4-12 The "256-Pin FBGA" table for the AFS250 device is new. 4-12 Previous Version Changes in Curren t Version (Preliminary v1.7) Page

Actel Fusion Mixed-Signal FPGAs Preliminary v1.7 4-37 Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as “Product Brief,” “Advance,” and “Production”. The definition of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estima ted information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data ha s not been fully characterized. Unmarked (production) This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status document may not have comp leted Actel’s qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functi onality or performance. It is the resp onsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel’s products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screen ing procedures. Contact your local Actel sales office for additional reliability information.

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