M16C6K7M8XXXRP

M16C6K7 RENESAS | Alldatasheet

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Technical content

Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERDescription Rev.1.0

Description

The M16C/6K7 (144-pin version) group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 144-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. To communicate with host CPU, the LPC bus interface is built in. In this way, this MCU can work as slave controller in the personal computer system. The specification is target oriented specification for the development of M16C/6K7 (144-pin version).

Features

interrupt sources; 7 levels (including key input interrupt) synchronous)

• I 1 (P85 shared with NMI pin) (built-in feedback resistor, and external ceramic or quartz oscillator)

Applications

Notebook PC, others Specifications written in this manual are believed to be ac- curate, but are not guaranteed to be entirely free of error. Specifications in this data sheet may be changed for functional or performance improvements. Please make sure your manual is the latest edition.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 I

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERDescription Rev.1.0 The differences in M16C/6K (144-pin) group 144-pin NEW DINOR Flash memory User ROM area Address 0E8000 16 - 0F5FFF16 Address 0FE00016 - 0FFFFF16 Boot ROM area In parallel I/O mode Address 0FE000 16 - 0FFFFF16 In CPU reprogram mode & standard serial I/O mode Address 0DE00016 - 0DFFFF16 Flash memory control register After reset XXXX00012 Flash memory recognition register After reset 000000002 Vcc 3.0 - 3.6V M2 pin 4.5 - 5.25V The input pin of power supply for program/erase 128 Port 0 - Port 16 without P84 3.3V/5V Exist Exist Not exist 144-pin NEW DINOR Flash memory User ROM area Address 0EF000 16 - 0FFFFF16 Boot ROM area Address 0FF000 16 - 0FFFFF16 Flash memory recognition register After reset 000000002 Flash memory control register After reset XX0000012 Vcc 3.0 - 3.6V Not exist 129 Port 0 - Port 16 3.3V Not exist Exist Exist Pin numbers ROM Built-in ROM area Address 03B416 Address 03B716 After reset 000000002 The power supply for program/erase M2 pin Programmable I/O The I/O voltage in P2, P3 Programmable I/O ports ISA bus interface Serial interrupt output & LPC bus interface Timer B TB2IN Type name M306K5F8LRP M306K7F8LRP Note 1: Timer B TB2IN refers to the count source input and pulse period measurement in event count mode/ pulse input in pulse width measurement mode.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Pin Configuration Fig.AA-1 shows the pin configurations (top view). PIN CONFIGURATION (top view) Package: 144PFB-A Fig. AA-1 Pin configuration (top view) 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 12 22 32 42 5 108 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 10710610510410310210110099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 26 27 28 29 30 31 32 33 34 35 36 P00 P01 P02 P03 P04 P05 P06 P07 0/LAD 1/LAD 2/LAD 3/LAD 4/LFRAME 5/LRESET 6/LCLK P13 P13 V CC V SS VREF AV SS AVcc P100/AN0 P101/AN1 P97/ADTRG /SIN4/INT60 V CCX IN X OUTV SS RESET M 7/X CIN 6/X COUT M 6/TB2 IN 5/NMI 5/TA2 IN /INT 2/PS2B P46/PWM 21/OBF3/CLKRUN P45/PWM 11/OBF2/PRST P47/PWM 31 P44/PWM 01/OBF1 P50/KI00 134 135 136 137 138 139 140 141 142 143 144 4/INT 1/PS2B 3/CTS /RTS /TA1 IN /INT 0/PS2B P15 P15 P15 P15 P13 P110 P16 1/TB4 1IN P15 P16 0/TB3 1IN P147/KI17 P146/KI16 P145/KI15 P144/KI14 P143/KI13 P142/KI12 P141/KI11 P140/KI10 P13 P13 P13 P13 P111 P112 P113 P114 P115 P116 P117 P120/INT61 P121/INT72 P122/INT82 6/ANEX1/S OUT4 /PWM 5/ANEX0/CLK 4/PWM VCC VSS 1/TA1 0OUT 2/R XD 1/CLK P13 P126 P125/INT111 P124/INT102 P123/INT92 P70/TXD 20/PS2A0 2/CLK /PS2A P63/TXD 00/SCL1 P65/CLK10 P66/RXD 10/TA3OUT /F1OUT0 P67/TXD 10/TA4OUT /F1OUT1 P61/CLK00/SCL0 P62/RXD 00/SDA1 P60/CTS00/RTS00/SDA0 P64/CTS10/RTS10 7/TA3 IN 1/S IN3 /INT 2/S OUT3 /INT 0/ICCK 2/TB0 IN 3/TB1 IN 0/CLK 3/INT 4/TB2 IN 1/TA4 IN 1/R XD /TA0 IN /TB5 IN /PS2A P102/AN2 P103/AN3/INT70 P107/AN7/INT110 P106/AN6/INT100 P105/AN5/INT90 P104/AN4/INT80 /CTS00/CLKS10 3/DA 0/TB3 0IN /PWM 4/DA 1/TB4 0IN /PWM P10/CTS01/RTS01 3/T XD 4/INT /CTS /RTS /CTS /CLKS 3/CTS /RTS 5/INT /CLK 0/T XD 6/INT XD 1/R XD 7/INT 101 XD 2/CLK P43/OBF01/SERIRQ P42/TA20OUT /GATE A20 P150/TA01OUT P151/TA11OUT P152/TA21OUT /KI01P51 /KI02P52 /KI03P53 /KI04P54 /KI05P55 /KI06P56 /CLKOUT /KI07P57 P12

7 TA0

/OBF M306K7F8LRP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERDescription Rev.1.0 Block Diagram Fig.AA-2 is a block diagram of the M16C/6K7 (144-pin version) group. Fig.AA-2 Block diagram of M16C/6K7 (144-pin version) group Timer Timer TA0(16 bits) Timer TA1(16 bits) Timer TA2(16 bits) Timer TA3(16 bits) Timer TA4(16 bits) Timer TB0(16 bits) Timer TB1(16 bits) Timer TB2(16 bits) Timer TB3(16 bits) Timer TB4(16 bits) Timer TB5(16 bits) Internal peripheral function Watchdog timer (15 bits) DMAC (2 channels) D-A converter (8 bits x 2channels) A-D converter (10 bits x 8 channels Expandable up to 10 channels) UART/clock synchronous SI/O (8 bits x 3 channels) System clock generator XIN-XOUT XCIN-XCOUT I/O ports Port P0 Port P1 Port P2 8 8 8 8 Port P6 Port P10 Port P9 Port P8 Port P8 Port P7 Note1 : ROM size depends on MCU type. Note2 : RAM size depends on MCU type. Port P5Port P4Port P3 Clock synchronous SI/O (8 bits x 2channels) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Memory ROM (Note1) RAM (Note2) M16C/60 series 16-bit CPU core L R0H R1H R1 LR 1FB R0L R0H R1H R1L FB Registers SB ISP USP Stack pointer Vector table INTB Multiplier Program counter PC FLG Flag register Port P11 Port P12 Port P13 Port P14 Port P15 Port P16 Comparator (8 channels) PS2 interface (3 channels) Host interface (LPC bus interface x 4 channels) PWM output (14 bits x 4channels) I C bus interface (2 channels) Serial interrupt output (6 factors)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Item Performance Number of basic instructions 91 instructions The Min. time of instruction execution 125ns (f(XIN)=8MHz, with 0 wait, Vcc=3V) Memory ROM (See the figure of ROM Expansion) capacity RAM 3K bytes I/O port P0 to P10 (except P85) 8 bits x 10, 7 bits x 1 P11 to P16 8 bitsx5, 2 bitsx1 Input port P85 1 bit x 1 Multifunction TA0, TA1, TA2, TA3, TA4 16 bits x 5 timer TB0, TB1, TB2, TB3, TB4, TB5 16 bits x 6 Serial I/O UART0, UART1, UART2 (UART or clock synchronous) x 3 SI/O3, SI/O4 (Clock synchronous) x 2 A-D converter 10 bits x (8 + 2) channels D-A converter 8 bits x 2 DMAC 2 channels (trigger: 24 sources) Watchdog timer 15 bits x 1 (with prescaler) Interrupt 36 internal and 15 external sources, 4 software sources, 7 levels Host interface 4 channels (LPC bus interface) Comparator circuit 8 channels PWM 14 bits x 4 I2C bus interface 2 channels PS2 interface 3 channels Serial interrupt output 6 factors (2 fixed factors, 4 programmable factors) Clock generating circuit 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) Supply voltage 3.0 to 3.6V (f(X IN)=8MH Z with 0 wait) Power consumption 41.3mW (3.3V, f(X IN)=8MHz, with 0 wait) I/O I/O withstand voltage 3.3V characteristics Output current 5mA Device configuration CMOS high performance silicon gate Package 144-pin plastic mold QFP Performance Outline Table AA-1 is a performance outline of M16C/6K7 (144-pin version) group. Table AA-1 Performance outline of M16C/6K7 (144-pin version) group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERDescription Rev.1.0 Mitsubishi plans to release the following products in the M16C/6K7 (144-pin version) group: (1) Support for flash memory version (2) ROM capacity (3) Package 144PFB-A : Plastic molded QFP(flash memory version) Fig.AA-3 ROM expansion ROM Size (Byte) External ROM 128K 96K 68K 32K Mask ROM version Flash version 80K 256K M306K7F8LRP Table AA-2 Product list Remarks Flash memory (NEW DINOR) version Type No. M306K7F8LRP ROM size 68K bytes RAM size 3K bytes Package type 144PFB-A Host Interface LPC

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.AA-4 Type No., memory size, and package Package type RP : 144PFB-A ROM No. ROM type 8 : 68Kbytes Memory type M : Mask ROM version F : Flash version Type No. M30 6K 7 M 8 XXX RP Shows RAM capacity, pin count, etc (The value itself has no specific maeaning) M16C/6KGroup M16C Family

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Pin Description Signal name Power supply input Reset input Clock input Clock output Chip mode setting Analog power supply input Analog power supply input Reference voltage input I/O port P0 I/O port P1 I/O port P2 I/O port P3 I/O port P4 I/O port P5 I/O type Input Input Output Input Input Input/output Input/output Input/output Input/output Input/output Input/output Function Apply 3.0 to 3.6 V to VCC . Apply 0V to VSS A “L” on this input resets the microcomputer. These pins are provided for the main clock generating circuit. Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. Connect to VSS This pin is a power supply input for the A-D converter. Connect this pin to VCC . This pin is a power supply input for the A-D converter. Connect this pin to VSS . This pin is a reference voltage input for the A-D converter. This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When set for input, the user can specify in units of four bits via software whether or not they are tied to a pull-up resistor. This port supports CMOS input level. And output type supports CMOS 3 state or N channel open drain selectable. This is an 8-bit I/O port equivalent to P0. Pins in this port also function as external interrupt pins as selected by software. This is an 8-bit I/O port equivalent to P0. (Except that output type just supports CMOS 3 state only). The 4 bits P24-P27 are available for directly driving LED's. This is an 8-bit I/O port equivalent to P0. (Except that output type just supports CMOS 3 state only). The port can be used for LPC bus interface I/O pins by software selection. This is an 8-bit I/O port equivalent to P0. (Except that output type just supports CMOS 3 state only). By software selecting, the port can also be used for LPC bus interface I/O pins, Timer A 0 to A2 output pins PWM output pins or serial interrupt output I/O pins. P40 to P46 pins' level can be read regardless the setting of input port or output port. If P40 or P43 are used for output ports, the function that clears P40 or P43 to "0" after the read of output data buffer from host CPU is available. This is an 8-bit I/O port equivalent to P0. (Except that output type is CMOS 3 state only). Key on wake interrupt 0 and comparator input function support. P5 7 in this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of the same frequency as XCIN as selected by software. Pin name Vcc, Vss RESET XIN XOUT M 0,M1 AV CC AV SS VREF P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Pin Description Signal name I/O port P6 I/O port P7 I/O port P8 I/O port P85 I/O port P9 I/O port P10 I/O type Input/output Input/output Input/output Input/output Input/output Input Input/output Input/output Function This is an 8-bit I/O port equivalent to P0. (Except that P60 to P63's output type is N channel open drain only; P64 to P67's output type is CMOS 3 state only; P60 to P63 no internal pull-up registor support.) By software selecting, this port can be used for I2C-BUS interface, UART0/UART1 input/ output pin, timerA3,A4 output pin or same frequency with XIN clock output pin. When P60 to P63 used as I2C-BUS interface SDA ,SCL , the input level of these pins are CMOS/ SMBUS selectable. This is an 8-bit I/O port equivalent to P0. (Except that P70 to P77 output type is N channel open drain only; no internal pull-up registor support.) By software selecting, this port can be used for external interrupt input pin, timerA0 to A3 and timerB5 input pin, PS2 interface input/output pin, or UART2 input/output pin. P7 0 to P75 pins' level can be read regardless of the setting of input port or output port. P80 to P84, P86, and P87 are I/O ports with the same functions as P0. (Except that P86 to P87's output type is CMOS 3 state only; P80 to P84's output type is N channel open drain only; P85 is input port only; the P80 to P84 and P85 are no internal pull-up registor support.) By software selecting, this port can be used for timer A4, B0 to B2, I2C-BUS interface I/O pins. P86 and P87 can be set using software to function as the I/O pins for a sub clock generation circuit. In this case, connect a quartz oscillator between P86 (XCOUT pin) and P87 (XCIN pin). P85 is an input-only port that______ ______ also functions for NMI. The NMI interrupt is generated when______ the input at this pin changes from “H ” to “L”. The NMI function cannot be cancelled using software. This is an 8-bit I/O port equivalent to P0. (Except that output type is CMOS 3 state only.) By software selecting, the port can be used for external interrupt, timer B3 to B4, A-D converter extended input pins, A-D trigger, SI/O3, SI/O4 I/O pins, PWM, D-A converter output pins. This is an 8-bit I/O port equivalent to P0. (Except that output type is CMOS 3 state only.) By software selecting, the port can be used for A-D converter, external interrupt input pins. Pin name P60 to P67 P70 to P77 P80 to P84, P86, P87, P85 P90 to P97 P100 to P107

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Pin Description Signal name I/O port P11 I/O port P12 I/O port P13 I/O port P14 I/O port P15 I/O port P16 I/O type Input/output Input/output Input/output Input/output Input/output Input/output Function This is an 8-bit I/O port equivalent to P0. This is an 8-bit I/O port equivalent to P0. (Except that output type is CMOS 3 state only.) By software selecting, this port can be used for external interrupt input pin. This is an 8-bit I/O port equivalent to P0. (Except that output type is N channel open drain only; no internal pull-up registor support.) This is an 8-bit I/O port equivalent to P0. The port can be used for key on wake-up interrupt 1 input pins. P140 to P143 are available for directly driving LED's. This is an 8-bit I/O port equivalent to P0. (Except that output type is CMOS 3 state only.) By software selecting, this port can be used for timer A0 to A2's output pin. This is an 2-bit I/O port equivalent to P0. (Except that output type is CMOS 3 state only.) By software selecting, this port can be used for timer B3 and B4 input pin. Pin name P110 to P117 P120 to P127 P130 to P137 P140 to P147 P150 to P157 P160, P161

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Operation of Functional Blocks The M16C/6K7 (144-pin version) group accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/ logic operations. Also peripheral units such as timers, serial I/O, D-A converter, DMAC, A-D converter, host bus interface, comparator, PWM output , I 2C BUS interface, PS2 interface and I/O ports are included. The following explains each unit. Memory Fig.CA-1 is the memory map. The address space extends up to 1M bytes from address 0000016 to FFFFF16. From FFFFF16 to the address decreasing direction ROM is allocated. For example, in the M306K7F8LRP, there is 68K bytes of internal ROM from EF00016 to FFFFF16. The vector table for fixed interrupts such as the reset and NMI are mapped from FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the section on interrupts for details. From 00400 16 to the address increasing direction RAM is allocated. For example, in the M306K7F8LRP, 3K bytes of internal RAM is mapped to the space from 0040016 to 00FFF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated. The SFR area is mapped from 00000 16 to 003FF16. This area accommodates the control registers for pe- ripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Fig.CA-2 to CA-5 are location of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and cannot be used for other purposes. The special page vector table is mapped from FFE00 16 to FFFDB16. If the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps. Fig.CA-1 Memory map SFR area For details, see Fig.CA-2 to Fig.CA-4 Internal RAM area Internal ROM area Reset Watchdog timer Single step Address match BRK instruction Overflow Undefined instruction Special page vector table 0000016 0040016 XXXXX 16 YYYYY 16 FFFFF 16 FFFFF 16 FFFDC 16 FFE00 16 DBC NMI Type No. Address YYYYY16Address XXXXX16 Inhibited M306K7F8LRP EF000 1600FFF 16

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Central Processing Unit (CPU) The CPU has a total of 13 registers shown in Fig.BA-1 Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks. (1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3) Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32- bit data registers (R2R0/R3R1). (2) Address registers (A0 and A1) Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be u2sed for address register indirect addressing and address register relative addressing. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). Fig.BA-1 Central processing unit register /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines H L b15 b8 b7 b0 R0 (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines H L b15 b8 b7 b0 R1 (Note) R2 (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 R3 (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 A0(Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 A1(Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 FB (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 Data registers Address registers Frame base register b15 b0 b15 b0 b15 b0 b15 b0 b0 b19 b0 b19 H L Program counter Interrupt table register User stack pointer Interrupt stack pointer Static base register Flag register PC INTB USP ISP SB FLG Note: These registers consist of two register banks. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines C D Z S B O I UIPL

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 (3) Frame base register (FB) Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing. (4) Program counter (PC) Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed. (5) Interrupt table register (INTB) Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table. (6) Stack pointer (USP/ISP) Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG). (7) Static base register (SB) Static base register (SB) is configured with 16 bits, and is used for SB relative addressing. (8) Flag register (FLG) Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Fig.BA-2 shows the flag register (FLG). The following explains the function of each flag:

• Bit 0: Carry flag (C flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag) This flag enables a single-step interrupt. When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag) This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag) This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”.
• Bit 4: Register bank select flag (B flag) This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
• Bit 5: Overflow flag (O flag) This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag) This flag enables a maskable interrupt. An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0” when the interrupt is acknowledged.
• Bit 7: Stack pointer select flag (U flag)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected when this flag is “1”. This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software interrupt No. 0 to 31 is executed.

• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with the three bits, for specification of up to eight proces- sor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled.
• Bit 15: Reserved area The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details. Fig.BA-2 Flag register (FLG) Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level (CPU) Reserved area Flag register (FLG)/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines C D Z S B O I UIPL b0b15

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.VB-2 Reset sequence Reset There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset. (See “Software Reset” for details of software resets.) This section explains the hardware reset. When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level “L” (0.2V CC max.) for at least 20 cycles. When the reset pin level is then returned to the “H ” level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. Fig.VB-1 shows the example reset circuit. Fig.VB-2 shows the reset sequence. Fig.VB-1 Example reset circuit Internal clock Φ Address Content of reset vectorSingle chip mode BCLK 24cycles FFFFE 16 XIN RESET FFFFC 16 More than 20 cycles are needed RESET VCC 0.6V RESET VCC 3.3V 3.3V 3.0V Exam ple when VCC = 3.3V

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Table VB-1 shows the statuses of the other pins while the RESET pin level is “L”. Fig.VB-3 and VB-4 show the internal status of the microcomputer immediately after the reset is cancelled. Table VB-1 Pin status when RESET pin level is “L” Status CNV SS = VSS (M0) Pin name P2, P3, P40 to P43 P44 P45 to P47 P50 P51 P52 P53 P54 P55 P56 P57 P6, P7, P80 to P84, P86, P87, P9, P10 I/O port (floating) I/O port (floating) I/O port (floating) I/O port (floating) I/O port (floating) I/O port (floating) I/O port (floating) I/O port (floating) I/O port (floating) I/O port (floating) I/O port (floating) I/O port (floating) I/O port (floating) I/O port (floating) P11, P12, P13, P14 I/O port (floating) P15, P16 I/O port (floating)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.VB-3 Device's internal status after a reset is cleared (1) x : Nothing is mapped to this bit ? : Undefined The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. (1) (0004 16)···Processor mode register 0 0016 (2) (0005 16)···Processor mode register 1 00 0 (3) (0006 16)···System clock control register 0 100 00 10 0 (4) (0007 16)···System clock control register 1 000 10 00 0 (5) (6) (000916)···Address match interrupt enable register 00 (7) Protect register (000A 16)··· 000 (9) (000F16)···Watchdog timer control register 0 0? 0? ? ? ? (11) (001416)···Address match interrupt register 1 (001516)··· (001616)··· 0 0016 0016 0 0 0 (12) (002C16)···DMA0 control register 00000?00 (13) (003C16)···DMA1 control register 00000?00 (21) (004B16)···DMA0 interrupt control register ? 000 (22) (004C16)···DMA1 interrupt control register ? 000 (23) (004D16)···Key input interrupt control register 0 ? 0 0 0 (20) (004A16)···Bus collision detection interrupt control register 0 0 0 ? (8) (001016)···Address match interrupt register 0 (001116)··· (001216)··· 0 0016 0016 0 0 0 (10) (14) (004416)···INT3 interrupt control register 00?000 (15) (004516)···Timer B5 interrupt control register ?000 (16) (004616)···Timer B4 interrupt control register ?000 (17) (004716)···Timer B3 interrupt control register ?000 (18) (004816)···SI/O4 interrupt control register 00?000 (19) (004916)···SI/O3 interrupt control register 00?000 A-D conversion interrupt control register UART2 transmit interrupt control register 000 (25) (26) (24)UART2 receive interrupt control register(005016)··· ? 0 0 0 (27) (28) (29) (30) UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register (31) (32) (33) (34) (35) (36) (37) Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register (38) Timer B2 interrupt control register (39) INT0 interrupt control register (40) INT1 interrupt control register (41) INT2 interrupt control register (45) PS21 shift register (46) PS21 status register PS20 status register (43) PS20 control register (44) (42) PS20 shift register (47) PS21 control register (48) PS22 shift register (49) PS22 status registerr PS22 control register 0016 (005116)··· (005216)··· (005316)··· (005416)··· (005516)··· (005616)··· (005716)··· (005816)··· (005916)··· (005A16)··· (005B16)··· (005C16)··· (005D16)··· (005E16)··· (005F16)··· (02A416)··· (02A516)··· (02A116)··· (02A216)··· (02A016)··· (02A616)··· (02A816)··· (02A916)··· (02AA16)··· (02AC16)···PS2 mode register ? 0 0 0 ? 000 ? 0 0 0 ? 000 ? 000 ? 000 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 000 ? 000 ? 000 ? 00000 ? 00000 ? 00000 0016 0016 0016 0016 0016 0016 0016 0016 0016

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.VB-4 Device's internal status after a reset is cleared (2) (02C716)···Data bus buffer status register 3 (02C816)···ISA bus control register 0 (56) (55) (02C916)···ISA bus control register 1 (57) (02CA16)···GateA20 control register (58) (61) (02E316)···Port P12 direction register (62) (63) (64) (59) (60) (02E216)···Port P11 direction register (02C516)···Data bus buffer status register 2 (54) 0016 0016 0016 0016 0016 (02EA16)···Port P15 direction register (69) (02EB16)···Port P16 direction register (70) (02F816)···Port function selection register 0 (71) (02F916)···Port function selection register 1 (72) (02FA16)···Port P4 input register (73) (02E616)···Port P13 direction register (65) (02E716)···Port P14 direction register (66) (67) 0016 (68) 0016 (02FB16)···Port P7 input register (74) (02FC16)···Pull-up control register 3 (75) (02FD16)···Pull-up control register 4 (76) 0016 Data bus buffer status register 0 (02C116)··· 0016 (02C316)···Data bus buffer status register 1 (52) (53) x : Nothing is mapped to this bit ? : Undefined The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. (0305 16)···PWM2L register (81) (030716)···PWM3L register (82) (030816)···PWM control register 0 (83) (030916)···PWM control register 1 (84) (032216)···I2C0 address register (85) (032316)···I2C0 control register (86) (032416)···I2C0 clock control register (87) (032516)···I2C0 start/stop condiction control register (88) (032616)···I2C0 control register 1 (89) (032716)···I2C0 control register 2 (90) (032816)···I2C0 status register (91) (033216)···I2C1 address register (92) (033316)···I2C1 control register (93) (033416)···I2C1 clock control register (94) I2C1 start/stop condiction control register (95) 0016 0016 0016 0016 0016 1A16 0016 0016 0016 0016 1A16 (030316)···PWM1L register (80) I2C1 status register (98) I2C1 control register 2 (97) TimerB3,4,5 count start flag (99) Interrupt factor selection register 1 (100) Interrupt factor selection register 2 (101) Interrupt factor selection register 3 Interrupt factor selection register 4 0016 0016 0016 0016 0016 I2C1 control register 1 (96) 3016 (033516)··· 0016 0016 0016 0016 0016 0016 0016 (02FE16)···Port control register 1 (77) (02FF16)···Port control register 2 (78) (030116)···PWM0L register (79) 0016 0016 (033616)··· (033716)··· (033816)··· (034016)··· (035616)··· (035716)··· (035816)··· (035916)··· TimerB3 mode register TimerB4 mode register TimerB5 mode register Interrupt factor selection register 0 SI/O3 control register SI/O4 control register 0016 4016 4016 (035B16)··· (035C16)··· (035D16)··· (035F16)··· (036216)··· (036616)··· 3016 00 00001 00 1 0000 00 ? 000 0 00 ? 000 0 00 ? 000 0 (50) (51) 0 0 00 0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.VB-5 Device's internal status after a reset is cleared (3) (037D16)···UART2 transmit/receive control register 1 (038016)··· Up-down flag (114) (113) (038116)··· Timer A0 mode register (115) (038216)··· Timer A1 mode register (116) (038316)··· Timer A2 mode register (119) (039716)··· Timer B0 mode register (120) (039816)··· Timer B1 mode register (121) (039916)··· Timer B2 mode register (122) (117) (038416)··· Timer A3 mode register (118) (039616)··· Timer A4 mode register (037C16)···UART2 transmit/receive control register 0 (112) 0016 0016 0016 0016 0016 0016 0016 0? 0000 00? 0000 00? 0000 (03A016)··· UART1 transmit/receive control register 0 (127) (03A416)··· UART1 transmit/receive control register 1 (128) (03A516)··· UART transmit/receive control register 2 (129) (03A816)··· DMA0 cause select register (130) (03AC16)··· DMA1 cause select register (131) (039A16)··· UART0 transmit/receive mode register (123) (039B16)··· UART0 transmit/receive control register 0 (124) (039C16)··· UART0 transmit/receive control register 1 (125) 0016 000 1000 000 0010 (039D16)··· UART1 transmit/receive mode register (126) 0016 000 1000 000 0010 00 0 0 00 0016 0016 (03AD16)··· (132) (03B016)··· A-D control register 0 (133) (03B816)··· A-D control register 1 (134) 000 0???0 0016 000 00 0 0 UART2 special mode register (037716)··· 0016 (037816)···UART2 transmit/receive mode register (110) (111) x : Nothing is mapped to this bit ? : Undefined The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. (03E2 16)···Port P0 direction register (141) (03E316)···Port P1 direction register (142) (03E616)···Port P2 direction register (143) (03E716)···Port P3 direction register (144) (03EA16)···Port P4 direction register (145) (03EB16)···Port P5 direction register (146) (03EE16)···Port P6 direction register (147) (03EF16)···Port P7 direction register (148) (03F216)···Port P8 direction register (149) (03F316)···Port P9 direction register (150) (03F616)···Port P10 direction register (151) (03FC16)···Pull-up control register 0 (152) (03FD16)···Pull-up control register 1 (153) (03FE16)···Pull-up control register 2 (154) Port control register 0 (155) 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 00 0 000 0 (03DC16)···D-A control register (139) 0016 Frame base register (FB) Address registers (A0/A1) Interrupt table register (INTB) User stack pointer (USP) Interrupt stack pointer (ISP) Static base register (SB) Flag register (FLG) 000016 000016 0000016 000016 000016 000016 000016 Data registers (R0/R1/R2/R3) (156) 000016 (03FF16)··· 0016 000 10000 000 00100 Trigger select flag One-shot start flag Clock prescaler reset flag Count start flag 0016 (03BA16)··· (03D616)·· (135) (136) (138) (137) (03D716)·· (03DE16)···Comparator control register (140) 0016 (106) (105) (107) (108) (109) (104) (102) (103) Flash memory control register 0001(03B716)··· Flash memory recognition register 00 0 00(03B416)···00 0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.VB-6 Device's internal status after a reset is cleared (2) (02B316)···IRQ request register 1 (02B416)··· LPC1 address register H (169) (168) (02B516)··· LPC2 address register L (170) (02B616)··· LPC2 address register H (02D016)··· LPC3 address register L (02D316)··· (02D416)··· (02D516)··· (02D116)··· LPC3 address register H (02D216)··· LPC control register (02B216)···IRQ request register 0 (167) (02D616)··· Serial interrupt control register 0(02B016)··· 0016 (02B116)···Serial interrupt control register 1 (165) (166) The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. 0016 LPC1 address register L IRQ request register 4 IRQ request register 3 IRQ request register 2(161) (160) (162) (163) (164) (159) (157) (158) 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.CA-2 Location of peripheral unit control registers (1) 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C 16 001D 16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C 16 004D 16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C 16 005D 16 005E16 005F16 006016 006116 027D 16 027E16 027F16 DMA0 control register (DM0CON) DMA0 source pointer (SAR0) DMA0 transfer counter (TCR0) DMA1 control register (DM1CON) DMA1 source pointer (SAR1) DMA1 transfer counter (TCR1) DMA1 destination pointer (DAR1) Watchdog timer start register (WDTS) Watchdog timer control register (WDC) Processor mode register 0 (PM0) Address match interrupt register 0 (RMAD0) Address match interrupt register 1 (RMAD1) System clock control register 0 (CM0) System clock control register 1 (CM1) Address match interrupt enable register (AIER) Protect register (PRCR) Processor mode register 1(PM1) DMA0 destination pointer (DAR0) Timer A1 interrupt control register (TA1IC) INT7 interrupt control register (INT7IC) UART0 transmit interrupt control register (S0TIC) I2C0 interrupt control register (IIC0IC) Timer A0 interrupt control register (TA0IC) INT8 interrupt control register (INT8IC) Timer A2 interrupt control register (TA2IC) UART0 receive interrupt control register (S0RIC) SCL0,SDA0 interrupt control register (SCLDA0IC) INT11 interrupt control register (INT11IC) UART1 transmit interrupt control register (S1TIC) I2C1 interrupt control register (IIC1IC) UART1 receive interrupt control register (S1RIC) SCL1,SDA1 interrupt control register (SCLDA1IC) INT10 interrupt control register (INT10IC) DMA1 interrupt control register (DM1IC) INT7 interrupt control register (INT7IC) DMA0 interrupt control register (DM0IC) INT8 interrupt control register (INT8IC) Key input interrupt 0 control register (KUP0IC) A-D conversion interrupt control register (ADIC) Bus collision detection interrupt control register (BCNIC) INT4 interrupt control register (INT4IC) UART2 transmit interrupt control register (S2TIC) IBF0 interrupt control register (IBF0IC) UART2 receive interrupt control register (S2RIC) IBF1 interrupt control register (IBF1IC) INT1 interrupt control register (INT1IC) PS21 interrupt control register (PS21IC) Timer B0 interrupt control register (TB0IC) SCL0,SDA0 interrupt control register (SCLDA0IC) INT11 interrupt control register (INT11IC) Timer B2 interrupt control register (TB2IC) Key input interrupt 1 control register (KUP1IC) Timer A3 interrupt control register (TA3IC) IBF2 interrupt control register (IBF2IC) INT2 interrupt control register (INT2IC) PS22 interrupt control register (PS22IC) INT0 interrupt control register (INT0IC) PS20 interrupt control register (PS20IC) Timer B1 interrupt control register (TB1IC) SCL1,SDA1 interrupt control register (SCLDA1IC) INT10 interrupt control register (INT10IC) Timer A4 interrupt control register (TA4IC) IBF3 interrupt control register (IBF3IC) INT3 interrupt control register (INT3IC) Timer B5 interrupt control register (TB5IC) INT9 interrupt control register (INT9IC) Timer B4 interrupt control register (TB4IC) Timer B3 interrupt control register (TB3IC) SI/O4 interrupt control register (S4IC) INT6 interrupt control register (INT6IC) SI/O3 interrupt control register (S3IC) INT5 interrupt control register (INT5IC) Note 1: The areas that nothing are allocated in SFR are reserved. Read and Write to the areas are inhibited.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.CA-3 Location of peripheral unit control registers (2) 02C0 16 02C1 16 02C2 16 02C3 16 02C4 16 02C5 16 02C6 16 02C7 16 02C8 16 02C9 16 02CA 16 02CB 16 02CC 16 02CD 16 02CE 16 02CF 16 02D0 16 02D1 16 02D2 16 02D3 16 02D4 16 02D5 16 02D6 16 02D7 16 02D8 16 02D9 16 02DA 16 02DB 16 02DC 16 02DD 16 02DE 16 02DF 16 02E016 02E116 02E216 02E316 02E416 02E516 02E616 02E716 02E816 02E916 02EA 16 02EB 16 02EC 16 02ED 16 02EE 16 02EF 16 02F016 02F116 02F216 02F316 02F416 02F516 02F616 02F716 02F816 02F916 02FA 16 02FB 16 02FC 16 02FD 16 02FE 16 02FF16 028016 028116 028216 028316 028416 028516 028616 028716 028816 028916 028A16 028B16 028C 16 028D 16 028E16 028F16 029016 029116 029216 029316 029416 029516 029616 029716 029816 029916 029A16 029B16 029C 16 029D 16 029E16 029F16 02A016 02A116 02A216 02A316 02A416 02A516 02A616 02A716 02A816 02A916 02AA 16 02AB 16 02AC 16 02AD 16 02AE 16 02AF 16 02B016 02B116 02B216 02B316 02B416 02B516 02B616 02B716 02B816 02B916 02BA 16 02BB 16 02BC 16 02BD 16 02BE 16 02BF 16 Data bus buffer register0 (DBB0) Port P11 (P11) Port P12 (P12) Port P4 input register (P4PIN) P14 event register (P14EV) PS20 shift register (PS20SR) PS20 control register (PS20CON) PS20 status register (PS20STS) PS21 shift register (PS21SR) PS21 control register (PS21CON) PS21 status register (PS21STS) PS22 shift register (PS22SR) PS22 control register (PS22CON) PS22 status register (PS22STS) PS2 mode register (PS2MOD) Data bus buffer status register0 (DBBSTS0) Data bus buffer register1 (DBB1) Data bus buffer status register1 (DBBSTS1) Data bus buffer register2 (DBB2) Data bus buffer status register2 (DBBSTS2) Data bus buffer register3 (DBB3) Data bus buffer status register3 (DBBSTS3) ISA control register0 (DBBCON0) ISA control register1 (DBBCON1) Gate A20 control register (GA20CON) Port P11 direction register (PD11) Port P12 direction register (PD12) Port P13 (P13) Port P14 (P14) Port P13 direction register (PD13) Port P14direction register (PD14) Port P15 (P15) Port P16 (P16) Port P15 direction register (PD15) Port P16 direction register (PD16) Port function selection register0 (PSL0) Port function selection register1 (PSL1) Port P7 input register (P7PIN) Port control register1 (PCR1) Pull-up control register3 (PUR3) Pull-up control register4 (PUR4) Port control register2 (PCR2) Serial Interrupt control register 0 (SERCON0) Serial Interrupt control register 1 (SERCON1) IRQ request register 0 (IRQ0) IRQ request register 1 (IRQ1) IRQ request register 2 (IRQ2) IRQ request register 3 (IRQ3) IRQ request register 4 (IRQ4) LPC1 address registerL (LPC1ADL) LPC1 address registerH (LPC1ADH) LPC2 address registerL (LPC2ADL) LPC2 address registerH (LPC2ADH) LPC3 address registerL (LPC3ADL) LPC3 address registerH (LPC3ADH) LPC control register (LPCCON) Port control register3 (PCR3) Note 1: The areas that nothing are allocated in SFR are reserved. Read and Write to the areas are inhibited.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.CA-4 Location of peripheral unit control registers (3) 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C 16 034D 16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C 16 035D 16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C 16 036D 16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C 16 037D 16 037E16 037F16 030016 030116 030216 030316 030416 030516 030616 030716 030816 030916 030A16 030B16 030C 16 030D 16 030E16 030F16 031016 031116 031216 031316 031416 031516 031616 031716 031816 031916 031A16 031B16 031C 16 031D 16 031E16 031F16 032016 032116 032216 032316 032416 032516 032616 032716 032816 032916 032A16 032B16 032C 16 032D 16 032E16 032F16 033016 033116 033216 033316 033416 033516 033616 033716 033816 033916 033A16 033B16 033C 16 033D 16 033E16 033F16 TimerB3,4,5 count start flag (TBSR) UART2 tranmit buffer register (U2TB) UART2 special mode register (U2SMR) I2C 0 data shift register (S00) I2C0 address register (S0D0) UART2 transmit/receive mode register (U2MR) UART2 communication speed register (U2BRG) UART2 receive buffer register (U2RB) UART2 transmit/receive control register0 (U2C0) UART2 transmit/receive control register1 (U2C1) PWM0H register (PWM0H) PWM0L register (PWM0L) PWM1H register (PWM1H) PWM1L register (PWM1L) PWM2H register (PWM2H) PWM2L register (PWM2L) PWM3H register (PWM3H) PWM3L register (PWM3L) PWM control register0 (PWMCON0) PWM control register1 (PWMCON1) I2C0 control register0 (S1D0) I2C0 clock control register (S20) I2C0 start/stop condition control register (S2D0) I2C0 control register1 (S3D0) I2C0 control register2 (S4D0) I2C0 status register (S10) I2C 1 data shift register (S01) I2C1 address register (S0D1) I2C1 control register0 (S1D1) I2C1 clock control register (S21) I2C1 start/stop condition control register (S2D1) I2C1 control register1 (S3D1) I2C1 control register2 (S4D1) I2C1 status register (S11) TimerB3 register (TB3) TimerB4 register (TB4) TimerB5 register (TB5) Interrupt event select register1 (IFSR1) Interrupt event select register2 (IFSR2) Interrupt event select register3 (IFSR3) Interrupt event select register4 (IFSR4) TimerB3 mode register (TB3MR) TimerB4 mode register (TB4MR) TimerB5 mode register (TB5MR) Interrupt event select register0 (IFSR0) SI/O3 transmit/receive register (S3TRR) SI/O3 control register (S3C) SI/O3 communication speed register (S3BRG) SI/O4 transmit/receive register (S4TRR) SI/O4 control register (S4C) SI/O4 communication speed register (S4BRG) Note 1: The areas that nothing are allocated in SFR are reserved. Read and Write to the areas are inhibited.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.CA-5 Location of peripheral unit control registers (4) 03C0 16 03C1 16 03C2 16 03C3 16 03C4 16 03C5 16 03C6 16 03C7 16 03C8 16 03C9 16 03CA 16 03CB 16 03CC 16 03CD 16 03CE 16 03CF 16 03D0 16 03D1 16 03D2 16 03D3 16 03D4 16 03D5 16 03D6 16 03D7 16 03D8 16 03D9 16 03DA 16 03DB 16 03DC 16 03DD 16 03DE 16 03DF 16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA 16 03EB 16 03EC 16 03ED 16 03EE 16 03EF 16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA 16 03FB 16 03FC 16 03FD 16 03FE 16 03FF16 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C 16 038D 16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C 16 039D 16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA 16 03AB 16 03AC 16 03AD 16 03AE 16 03AF 16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA 16 03BB 16 03BC 16 03BD 16 03BE 16 03BF 16 A-D register0 (AD0) A-D register1 (AD1) A-D register2 (AD2) A-D register3 (AD3) Pull-up control register0 (PUR0) Pull-up control register1 (PUR1) Count start flag (TABSR) Clock prescaler reset flag (CPSRF) One-shot start flag (ONSF) Trigger select register (TRGSR) Up-down flag (UDF) TimerA0 (TA0) TimerA1 (TA1) DMA0 request cacse select register (DM0SL) D-A register0 (DA0) D-A control register (DACON) Comparator data register (CMPD) Port P0 (P0) Port P0 direction register (P0D) Port P1 direction register (P1D) TimerA2 (TA2) TimerA3 (TA3) TimerA4 (TA4) TimerB0 (TB0) TimerB1 (TB1) TimerB2 (TB2) TimerA0 mode register (TA0MR) TimerA1 mode register (TA1MR) TimerA2 mode register (TA2MR) TimerA3 mode register (TA3MR) TimerA4 mode register (TA4MR) TimerB0 mode register (TB0MR) TimerB1 mode register (TB1MR) TimerB2 mode register (TB2MR) Port control register0 (PCR0) UART0 tranmit buffer register (U0TB) UART0 transmit/receive mode register (U0MR) UART0 communication speed register (U0BRG) UART0 receive buffer register (U0RB) UART0 transmit/receive control register0 (U0C0) UART0 transmit/receive control register1 (U0C1) UART1 tranmit buffer register (U1TB) UART1 transmit/receive mode register (U1MR) UART1 communication speed register (U1BRG) UART1 receive buffer register (U1RB) UART1 transmit/receive control register0 (U1C0) UART1 transmit/receive control register1 (U1C1) UART transmit/receive control register2 (UCON) DMA1 request cacse select register (DM1SL) A-D register4 (AD4) A-D register5 (AD5) A-D register6 (AD6) A-D register7 (AD7) A-D control register0 (ADCON0) A-D control register1 (ADCON1) D-A register1 (DA1) Comparator control register (CMPCON) Port P1 (P1) Port P2 (P2) Port P2 direction register (P2D) Port P3 direction register (P3D) Port P3 (P3) Port P4 (P4) Port P4 direction register (P4D) Port P5 direction register (P5D) Port P5 (P5) Port P6 (P6) Port P6 direction register (P6D) Port P7 direction register (P7D) Port P7 (P7) Port P8 (P8) Port P8 direction register (P8D) Port P9 direction register (P9D) Port P9 (P9) Port P10 (P10) Port P10 direction register (P10D) Pull-up control register2 (PUR2) Flash memory control register (FMCR) Note 1: The areas that nothing are allocated in SFR are reserved. Read and Write to the areas are inhibited. Flash memory recognition register (FMRR)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Software Reset Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal RAM are retained. Processor Mode (1) Types of Processor Mode The single-chip mode is supported in processor mode.

• Single-chip mode In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be accessed. Ports P0 to P16 can be used as programmable I/O ports or as I/O ports for the internal peripheral functions. Fig. BG-1 shows the structure of processor mode register 0 and processor mode register 1. Software Reset Processor mode register 0 (Note 1) Symbol Address When reset PM0 0004 16 0016 (Note 2) Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 0 0: Single-chip mode 0 1: Inhibited 1 0: Inhibited 1 1: Inhibited b1 b0 PM03 PM01 PM00 Processor mode bit Reserved bit Must always be set to “0” Software reset bit The device is reset when this bit is set to “1”. The value of this bit is “0” when read. Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register. Processor mode register 1 (Note 1) Symbol Address When reset PM1 0005 16 00000XX0 2 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Reserved bit Must always be set to “0” Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register. /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines PM17 Wait bit 0 : No wait state 1 : Wait state inserted /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Reserved bit Must always be set to “0” 0 0 Reserved bit Must always be set to “0” 0 0 0 000 0 Fig.BG-1 Processor mode register 0 and 1

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 (1) Software wait A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 000516) (Note) . A software wait is inserted in the internal ROM/RAM area by setting the wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK cycle. When set to “1”, each bus cycle is executed in 2 BCLK cycles. After the microcomputer has been reset, this bit defaults to “0”. Set this bit after referring to the recommended operating conditions (main clock input oscillation frequency) of the electric characteristics. The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Table.EF-1 shows the software wait and bus cycles. Fig.EF-1 shows example bus timing when using soft- ware waits. Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect register (address 000A 16) to “1”. Table.EF-1 Software waits and bus cycles Bus control Area Wait bit Bus cycle 1 2 BCLK cycles SFR Internal ROM/RAM 0 1 BCLK cycle Invalid 2 BCLK cycles

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.EF-1 Typical bus timings using software wait Output Input Address Address With wait BCLK Read signal Write signal Data bus Address bus Chip select BCLK Read signal Write signal Address bus Address Address No wait OutputData bus Chip select Input Bus cycle (Note 1) Note 1: This timing sample shows the lenth of bus cycle. It is possible that the read cyles, write cycle comes after this cycle in succession. Bus cycle (Note 1) Bus cycle (Note 1) Bus cycle (Note 1)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.WA-2 Examples of sub clock Table.WA-1 Main clock and sub clock generating circuits Clock Generating Circuit The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral units. Example of oscillator circuit Fig.WA-1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Figure WA-2 shows some examples of sub clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Circuit constants in Fig.WA-1 and WA-2 vary with each oscillator used. Use the values recommended by the manufacturer of your oscillator. Fig.WA-1 Examples of main clock Main clock generating circuit Sub clock generating circuit Use of clock • CPU’s operating clock source • CPU’s operating clock source

• Internal peripheral units’ • Timer A/B’s count clock operating clock source source Usable oscillator Ceramic or crystal oscillator Crystal oscillator Pins to connect oscillator X IN, XOUT XCIN, XCOUT Oscillation stop/restart function Available Available Oscillator status immediately after resetOscillating Stopped Other Externally derived clock can be input Microcomputer (Built-in feedback resistor) XIN XOUT Externally derived clock Open Vcc Vss Microcomputer (Built-in feedback resistor) XIN XOUT R d C IN C OUT (Note) Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Apply the feedback register between X IN and XOUT if required by oscillator maker. Microcomputer (Built-in feedback resistor) XCIN XCOUT Externally derived clock Open Vcc Vss Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Apply the feedback register between X CIN and XCOUT if required by oscillator maker. Microcomputer (Built-in feedback resistor) XCIN XCOUT (Note) C CIN C COUT R Cd

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Clock Control Fig.WA-3 shows the block diagram of the clock generating circuit. Fig.WA-3 Clock generating circuit Sub clock CM04 fC32 CM0i : Bit i at address 000616 CM1i : Bit i at address 000716 WD C i : Bit i at address 000F16 XCIN CM10 “1” Write signal XCOUT QS R WAIT instruction XOUT Main clock CM05 fC CM02 Q S R NMI Interrupt request level judgment output RESET Software reset fC CM07=0 CM07=1 fAD /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Dividera d 1/2 1/2 1/2 1/2 CM06=0 CM17,CM16=00 CM06=0 CM17,CM16=01 CM06=0 CM17,CM16=10 CM06=1 CM06=0 CM17,CM16=11 d a Details of divider XIN f32 cb b c f32SIO2 f8SIO2 f1SIO2 BCLK

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 The following paragraphs describes the clocks generated by the clock generating circuit. (1) Main clock The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). After switching the CPU operation clock to sub clock stopping the clock reduces the power dissipation. After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the X IN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit de- faults to “1” when shifting from high speed mode or mid-speed mode to stop mode and after a reset. (2) Sub clock The sub clock is generated by the sub clock oscillation circuit. No sub clock is generated after a reset. After oscillation is started using the port Xc select bit (bit 4 at address 0006 16), the sub clock can be selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the sub clock oscillation has fully stabilized before switching. After the oscillation of the sub clock oscillation circuit has stabilized, the drive capacity of the sub clock oscillation circuit can be reduced using the X CIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the drive capacity of the sub clock oscillation circuit reduces the power dissipation. This bit changes to “1” when shifting to stop mode and at a reset. (3) BCLK The BCLK is the clock that drives the CPU, and is either the main clock or fc or is derived by dividing the main clock by 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. When shifting from high speed mode or mid-speed mode to stop mode, the main clock division select bit (bit 6 at 0006 16) is set to “1”. The bit maintains in low speed mode and low power save mode. (4) Peripheral function clock f1, f8, f32, f1SIO2, f8SIO2, f32SIO2, fAD The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 0006 16) to “1” and then executing a WAIT instruction. (5) fC32 This clock is derived by dividing the sub clock by 32. It is used for the timer A and timer B counts. (6) fC This clock has the same frequency as the sub clock. It is used for the BCLK and for the watchdog timer.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.WA-4 shows the system clock control registers 0 and 1. Fig.WA-4 System clock control registers 0 and 1 System clock control register 0 (Note 1) Symbol Address When reset CM0 0006 16 4816 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : I/O port P57 0 1 : fC output 1 0 : f8 output 1 1 : f32 output b1 b0 CM07 CM05 CM04 CM03 CM01 CM02 CM00 CM06 Clock output function select bit WAIT peripheral function clock stop bit 0 :Do not stop peripheral clock in wait mode 1 :Stop peripheral clock in wait mode (Note8) XCIN-XCOUT drive capacity select bit (Note 2) 0 : LOW 1 : HIGH Port XC select bit 0 : I/O port 1 : XCIN-XCOUT generation Main clock (XIN-XOUT ) stop bit (Note 3) (Note 4) (Note 5) 0 : On 1 : Off Main clock division select bit 0 (Note 7) 0 : CM16 and CM17 valid 1 : Division by 8 mode System clock select bit (Note 6) 0 : XIN, XOUT 1 : XCIN, XCOUT Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register. Note 2: Changes to "1" when shiffing to stop mode. Note 3: When entering power saving mode, main clock stops using this bit. When returning from stop mode and operating with XIN, set this bit to "0". When main clock oscillation is operating by itself, set system clock select bit (CM07) to "1" before setting this bit to "1". Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. Note 5: If this bit is set to "1", X OUT turns "H". The built-in feedback resistor remains ON, so XIN turns pulled up to XOUT ("H") via the feedback resistor. Note 6: In the case of setting the bit from "0" to "1", set port XC select bit (CM04) to "1" and wait for the subclock being stable before wrting the bit. Don't write in the same time. In the case of setting the bit from "1" to "0", set main clock stop bit (CM05) to "0" and wait for the main clock being stable before write the bit. Note 7: The bit is set to "1" when shifting from high speed mode or mid speed mode to stop mode and after reset. The bit maintains in low speed mode and power save mode. Note 8: fc32 is not included. Do not set to "1" when using low-speed or low power dissipation mode. W R /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines System clock control register 1 (Note 1) Symbol Address When reset CM1 0007 16 2016 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 CM10 All clock stop control bit (Note4) 0 : Clock on 1 : All clocks off (stop mode) Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register. Note 2: Changes to "1" when shiffing to stop mode. Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is "0". If "1", division mode is fixed at 8. Note 4: If this bit is set to "1", XOUT turns "H", and the built-in feedback resistor turns null. CM15 XIN-XOUT drive capacity select bit (Note 2) 0 : LOW 1 : HIGH W R CM16 CM17 Reserved bit Always set to “0” Reserved bit Always set to “0” Main clock division select bit 1 (Note 3) 0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode b7 b6 0 0 Reserved bit Always set to “0” Reserved bit Always set to “0” 0 0 /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Pin Single-chip mode Port Retains status before stop mode CLK OUT When fc selected “H ” When f8, f32 selected Retains status before stop mode Table.WA-2 Port status during stop mode Clock Output In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8, f32, or fc to be output from the P57/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address 000616) is set to “1”, the output of f8 and f32 stops when a WAIT instruction is executed. Stop Mode Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcom- puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains above 2V. The oscillation , BCLK, f1 to f32, f1SIO2 to f32SIO2, fC , fC32 , and fAD stop in stop mode, peripheral functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B operate pro- vided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2) ,SIO3,4 functions provided an external clock is selected. Table.WA-2 shows the status of the ports in stop mode. Stop mode is cancelled by a hardware reset or interrupt. If an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled.After the restoration by interrupt, the corresponding interrupt routine will be processed.When shifting from high speed mode or mid-speed mode to stop mode, the main clock division select bit 0 (bit 6 at 0006 16) is set to “1”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Wait Mode When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but the BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral func- tion clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. However, because the peripheral function clock (fc32) that is generated by sub clock does not stop, there is no reducing of power dissipation. Do not set the bit to "1" then enter wait mode in low speed mode and low power dissipation mode.Table.WA-3 shows the status of the ports in wait mode. Wait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, the microcomputer restarts from interrupt routine using as BCLK, the clock that had been selected when the WAIT instruction was executed. Table.WA-3 Port status during wait mode Pin Single-chip mode CLK OUT When fC selected Does not stop When f8, f32 selected Does not stop when the WAIT peripheral function clock stop bit is “0”. When the WAIT peripheral function clock stop bit is “1”, the status immediately prior to entering wait mode is maintained. Port maintained the status immediately prior to enterig wait mode Wait Mode

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0

01000 Invalid Division by 2 mode

10000 Invalid Division by 4 mode

Invalid Invalid 0 1 0 Invalid Division by 8 mode

11000 Invalid Division by 16 mode

00000 Invalid No-division mode

Invalid Invalid 1 Invalid 0 1 Low-speed mode Invalid Invalid 1 Invalid 1 1 Low power dissipation mode Status Transition Of BCLK Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table.WA-4 shows the operating modes corresponding to the settings of system clock control regis- ters 0 and 1. After a reset, operation defaults to division by 8 mode. When shifting from high speed mode or mid-speed mode to stop mode, and after a reset main clock division select bit 0 (bit 6 at address 0006 16) is set to “1”. It is matained in low speed mode and low power dissipation mode. (1) Division by 2 mode The main clock is divided by 2 to obtain the BCLK. (2) Division by 4 mode The main clock is divided by 4 to obtain the BCLK. (3) Division by 8 mode The main clock is divided by 8 to obtain the BCLK. After reset, it works in this mode. Note that oscillation of the main clock must have stabilized before transferring from this mode to No-division, Division by 2 and Division by 4 mode. Oscillation of the sub clock must have stabilized before transferring this mode to Low- speed mode and Low power dissipation mode. (4) Division by 16 mode The main clock is divided by 16 to obtain the BCLK. (5) No-division mode The main clock is used as the BCLK. (6) Low-speed mode fC is used as the BCLK. Note that oscillation of both the main and sub clocks must have stabilized before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately after power- ing up and after stop mode is cancelled. (7) Low power dissipation mode fC is the BCLK and the main clock is stopped. Precaution In the case of switching the BCLK count source from XIN to XCIN, or from XCIN to XIN, it is necessary that the destination clock count source be stable. The transition should be waited by software after the oscillation being stable. CM17 CM16 CM07 CM06 CM05 CM04 Operating mode of BCLK Table.WA-4 Operating modes dictated by settings of system clock control registers 0 and 1 Status Transition Of BCLK

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Power control The following is a description of the power control modes: Modes Power control is available in three modes. (1) Normal operation mode

• High-speed mode Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the internal clock selected. Each peripheral function operates according to its assigned clock.
• Medium-speed mode Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the BCLK. The CPU operates according to the internal clock selected. Each peripheral function operates according to its assigned clock.
• Low-speed mode f C becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the sub clock. Each peripheral function operates according to its assigned clock.
• Low power consumption mode The main clock operating in low-speed mode is stopped. The CPU operates according to the f C clock. The fc clock is supplied by the sub clock. The only peripheral functions that operate are those with the sub-clock selected as the count source. (2) Wait mode The CPU operation is stopped. The oscillators do not stop. (3) Stop mode All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three modes listed here, is the most effective in decreasing power consumption. Fig.WA-5 is the state transition diagram of (1) to (3). Power control

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.WA-5 State transition diagram of Power control mode Power control BCLK : f(XIN)/8 Main clock is oscillating Sub clock is oscillating Main clock is oscillating Sub clock is stop Main clock is stop Sub clock is oscillating CM07 = “0” Note 1 CM06 = “1” CM04 = “0” BCLK : f(XCIN) CM07 = “1” BCLK : f(XIN) High-speed mode Medium-speed mode (divided-by-2) Medium-speed mode (divided-by-16) Medium-speed mode (divided-by-4) Low-speed mode High-speed mode Medium-speed mode (divided-by-2) Medium-speed mode (divided-by-16) Medium-speed mode (divided-by-4) Main clock oscillation Sub clock stop Medium-speed mode (divided-by-8 mode) Reset Medium-speed mode (Divided-by-8 mode) WAIT command (Please see the diagram below on transition of normal mode) Interrupt Transition of stop mode, wait mode Transition of normal mode Normal mode Please switch after the main clock oscillation being stable. Please switch after the sub clock oscillation being stable. Please change the CM06 after CM16,CM17 being changed. Please transit following the arrow direction. Note 1: Note 2: Note 3: Note 4: Stop mode All oscillators stopCM10 = “1” Interrupt Stop mode All oscillators stop High-speed/medium- speed mode CM10 = “1” low-speed/low power dissipation modeStop mode All oscillators stopCM10 = “1” Interrupt Interrupt Wait mode CPU operation stop WAIT command Interrupt Wait mode CPU operation stop WAIT command Interrupt Wait mode CPU operation stop CM06 = “1” BCLK : f(XIN)/2 BCLK : f(XIN)/16 BCLK : f(XIN)/4 BCLK : f(XIN)/8 CM07 = “0” CM06 = “1” Medium-speed mode (divided-by-8) Main clock is oscillating Sub clock is oscillating CM07 = “0” Note1,Note3 CM07 = “1” Note2 BCLK : f(XCIN) CM07 = “1” Low power dissipation mode BCLK : f(XIN) BCLK : f(XIN)/2 BCLK : f(XIN)/16 BCLK: f(XIN)/4 CM06 = “0” Note1,Note3 CM07 = “0” Note 1 CM06 = “0” Note 3 CM04 = “1” CM07 = “1” Note 2 CM05 = “1”

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Protection The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Fig.WA-6 shows the protect register. The values in the processor mode register 0 (address 0004 16), processor mode register 1 (address 000516), system clock control register 0 (address 000616), system clock control register 1 (address 000716), port P9 direction register (address 03F316) , SI/O3 control register (address 036216) and SI/O4 control register (address 036616) can only be changed when the respective bit in the protect register is set to “1”. Therefore, important outputs can be allocated to port P9. If, after “1” (write-enabled) has been written to the port P9 direction register and SI/Oi control register (i=3,4) write-enable bit (bit 2 at address 000A 16), a value is written to any address, the bit automatically reverts to “0” (write-inhibited). However, the system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and 1 write-enable bit (bit 1 at 000A16) do not automatically return to “0” after a value has been written to an address. The program must therefore be written to return these bits to “0”. Fig.WA-6 Protect register Protection Protect register Symbol Address When reset PRCR 000A 16 XXXXX000 2 Bit name Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : Write-inhibited 1 : Write-enabled PRC1 PRC0 PRC2 Enables writing to processor mode registers 0 and 1 (addresses 000416 and 000516) Function 0 : Write-inhibited 1 : Write-enabled Enables writing to system clock control registers 0 and 1 (addresses 0006 16 and 000716) Enables writing to port P9 direction register (address 03F3 16) and SI/Oi control register (i=3,4) (address 036216 and 036616 ) (Note) 0 : Write-inhibited 1 : Write-enabled W R /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note: Writing a value to an address after “1” is written to this bit returns the bit to “0”. Other bits do not automatically return to “0” and they must therefore be reset by the program.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0

• Maskable interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level. Fig.DD-1 Classification of interrupts Interrupt Software Hardware Special Peripheral I/O (Note) Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Reset NMI DBC Watchdog timer Single step Address matched Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system. Overview of Interrupt Type of Interrupts Fig.DD-1 lists the types of interrupts.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable inter- rupts.

• Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to “1”. The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt An INT interrupt occurs when assigning one of software interrupt numbers 0 through 63 and executing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so ex- ecuting the INT instruction allows executing the same interrupt routine that a peripheral I/O interrupt does. The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is in- volved. So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts. (1) Special interrupts Special interrupts are non-maskable interrupts.

• Reset Reset occurs if an “L” is input to the RESET pin.
• NMI interrupt An NMI interrupt occurs if an “L” is input to the NMI pin.
• DBC interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt Generated by the watchdog timer.
• Single-step interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
• Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to “1”. If an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. (2) Peripheral I/O interrupts A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral functions are dependent on classes of products, so the interrupt factors are also dependent on classes of products. The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts. 1)Bus collision detection interrupt This is an interrupt that the serial I/O bus collision detection generates. 2)DMA0 interrupt, DMA1 interrupt These are interrupts that DMA generates. 3)Key-input interrupt 0 / Key-input interrupt 1 ___ A key-input interrupt occurs if an “L” is input to the KI pin. 4)A-D conversion interrupt This is an interrupt that the A-D converter generates. 5)UART0, UART1, UART2/NACK, SI/O3 and SI/O4 transmission interrupt These are interrupts that the serial I/O transmission generates. 6)UART0, UART1, UART2/ACK, SI/O3 and SI/O4 reception interrupt These are interrupts that the serial I/O reception generates. 7)Timer A0 interrupt through timer A4 interrupt These are interrupts that timer A generates 8)Timer B0 interrupt through timer B5 interrupt These are interrupts that timer B generates. 9)INT0 interrupt through INT11 interrupt An INT interrupt occurs if either a rising edge or a falling edge or both edges are input to the INT pin.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 10)IBF0 to IBF3 interrupt These are interrupts that host bus interface generates. 11)I 2C0,I2C1,SCL0,SDA0,SCL1,SDA1 interrupt These are interrupts that I2C bus interface generates. 12)PS20 to PS22 interrupt These are interrupt that PS2 interface generates.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Interrupt source Vector table addresses Remarks Address (L) to address (H) Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction Overflow FFFE0 16 to FFFE316 Interrupt on INTO instruction BRK instruction FFFE4 16 to FFFE716 If the vector contains FF16, program execution starts from the address shown by the vector in the variable vector table Address match FFFE8 16 to FFFEB16 There is an address-matching interrupt enable bit Single step (Note) FFFEC 16 to FFFEF16 Do not use Watchdog timer FFFF0 16 to FFFF316 DBC (Note) FFFF4 16 to FFFF716 Do not use NMI FFFF8 16 to FFFFB16 External interrupt by input to NMI pin Reset FFFFC 16 to FFFFF16 Note: Interrupts used for debugging purposes only. Fig.DD-2 Format for specifying interrupt vector addresses Interrupts and Interrupt Vector Tables If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Fig.DD-2 shows the format for specifying the address. Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting.

• Fixed vector tables The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFDC 16 to FFFFF16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table.DD-1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. Table.DD-1 Interrupts assigned to the fixed vector tables and addresses of vector tables /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Mid address/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Low address /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 0 0 0 0 High address /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 0 0 0 0 0 0 0 0 Vector address + 0 Vector address + 1 Vector address + 2 LSBMSB

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0

• Variable vector tables The addresses in the variable vector table can be modified, according to the user’s settings. The start address of vector table is set to the interrupt table register (INTB). The 256-byte area subsequent that the start address is indicated by the INTB becomes the area for the variable vector tables. One vector table comprises 4 bytes. Set the first address of the interrupt routine in each vector table. Table.DD-2 shows the interrupts assigned to the variable vector tables and addresses of vector tables.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Table.DD-2 Interrupts assigned to the variable vector tables and addresses of vector tables Software interrupt number Interrupt sourceVector table address Address (L) to address (H) Remarks Cannot be masked by I flag+0 to +3 (Note 1) BRK instructionSoftware interrupt number 0 +44 to +47 (Note 1) Software interrupt number 11 +48 to +51 (Note 1) Software interrupt number 12 +52 to +55 (Note 1) Software interrupt number 13 +56 to +59 (Note 1) Software interrupt number 14 +68 to +71 (Note 1) Software interrupt number 17 +72 to +75 (Note 1) Software interrupt number 18 +76 to +79 (Note 1) Software interrupt number 19 +80 to +83 (Note 1) Software interrupt number 20 +84 to +87 (Note 1) Software interrupt number 21 +88 to +91 (Note 1) Software interrupt number 22 +92 to +95 (Note 1) Software interrupt number 23 +96 to +99 (Note 1) Software interrupt number 24 +100 to +103 (Note 1)Software interrupt number 25 +104 to +107 (Note 1)Software interrupt number 26 +108 to +111 (Note 1)Software interrupt number 27 +112 to +115 (Note 1)Software interrupt number 28 +116 to +119 (Note 1)Software interrupt number 29 +120 to +123 (Note 1)Software interrupt number 30 +124 to +127 (Note 1)Software interrupt number 31 +128 to +131 (Note 1)Software interrupt number 32 +252 to +255 (Note 1)Software interrupt number 63 to Note 1: Address relative to address in interrupt table register (INTB). Note 2: It is selected by interrupt request cause bit. Note 3: Depend on interrupt event selection bit setting.Please do not set same interrupt event at the same time. Cannot be masked by I flag +40 to +43 (Note 1) Software interrupt number 10 +60 to +63 (Note 1) Software interrupt number 15 +64 to +67 (Note 1) Software interrupt number 16 +20 to +23 (Note 1) Software interrupt number 5 +24 to +27 (Note 1) Software interrupt number 6 +28 to +31 (Note 1) Software interrupt number 7 +32 to +35 (Note 1) Software interrupt number 8 +16 to +19 (Note 1) INT3Software interrupt number 4 +36 to +39 (Note 1) SI/O3/INT5 Software interrupt number 9 SI/O4/INT6 Timer B3 Timer B4 Timer B5/INT9 (Note 2) (Note 2) to DMA0/INT8 DMA1/INT7 Key input interrupt 0 A-D UART0 transmit/I2C0 (Note 2) UART0 receive/SCL0,SDA0/INT11 (Note 3) UART1 transmit/I2C1 (Note 2) UART1 receive/SCL1,SDA1/INT10 (Note 3) Timer A0/INT8 Timer A1/INT7 Timer A2 Timer A3/IBF2 Timer A4/IBF3 Timer B0/INT11/SCL0,SDA0 (Note 3) Timer B1/INT10/SCL1,SDA1 (Note 3) Timer B2/Key input interrupt 1 (Note 2) INT0/PS20 (Note 2) INT1/PS21 (Note 2) INT2/PS22 (Note 2) Software interrupt Bus collision detection/INT4 UART2 transmit/IBF0 (Note 2) UART2 receive/IBF1 (Note 2) (Note 2) (Note 2) (Note 3) (Note 3) (Note 3) (Note 3)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Interrupt Control Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selection bits and processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bits are located in the interrupt control register of each interrupt. The interrupt enable flag (I flag) and the IPL are located in the flag register (FLG). Fig.DD-3 and DD-4 shows the memory map of the interrupt control registers. The interrupt factors in the same vector share the same interrupt control register. Which factor to be used depends on interrupt factor selection bit of interrupt event selection register i(address:035F 16,035616, to 035816, i = 0 to 3) setting. After setting the interrupt factor, the corresponding interrupt request bit must be set to "0" before changing the interrupt. Fig.DD-3 Interrupt control registers(1) Interrupt control register b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Bit name FunctionBit symbol W R Symbol Address When reset TBiIC(i=3,4) 0047 16 ,004616 XXXXX000 2 KUP0IC 004D 16 XXXXX000 2 ADIC 004E 16 XXXXX000 2 S2TIC/IBF0IC 004F 16 XXXXX000 2 S2RIC/IBF1IC 0050 16 XXXXX000 2 SiTIC/IICjIC(i=0,1) 0051 16 ,005316 XXXXX000 2 (j=0,1) 005116 ,005316 XXXXX000 2 TA2IC 0057 16 XXXXX000 2 TAiIC/IBFjIC(i=3,4) 0058 16 ,005916 XXXXX000 2 (j=2,3) 005816 ,005916 XXXXX000 2 TB2IC/KUP1IC 005C 16 XXXXX000 2 ILVL0 IR Interrupt priority level select bit Interrupt request bit 0 : Interrupt not requested 1 : Interrupt requested ILVL1 ILVL2 Nothing is assigned. (Note 1) Note 1: Can only be writing by "0" (Please do not write "1" to this bit) 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.DD-4 Interrupt control registers (2) Symbol Address When reset INT3IC 0044 16 XX00X000 2 TB5IC/INT9IC 0045 16 XX00X000 2 SiIC/INTjIC (i=4, 3) 0048 16, 004916 XX00X000 2 (j=6, 5) 0048 16, 004916 XX00X000 2 BCNIC/INT4IC 004A 16 XX00X000 2 DMiIC/INTjIC(i=0, 1) 004B 16, 004C16 XX00X000 2 (j=8, 7) 004B 16, 004C16 XX00X000 2 SiRIC/SCLDAjIC/INTkIC(i=0, 1) 0052 16, 005416 XX00X000 2 (j=0, 1) 005216, 005416 XX00X000 2 (k=11,10) 005216, 005416 XX00X000 2 TAiIC/INTjIC(i=0, 1) 0055 16, 005616 XX00X000 2 (j=8, 7) 0055 16, 005616 XX00X000 2 TBiIC/INTjIC/SCLDkIC(i=0, 1) 005A 16, 005B16 XX00X000 2 (j=11, 10) 005A16, 005B16 XX00X000 2 (k=0,1) 005A16, 005B16 XX00X000 2 INTiIC/PS2jIC(i=0 to 2) 005D 16 to 005F16 XX00X000 2 (j=0 to 2) 005D16 to 005F16 XX00X000 2 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines ILVL0 IR POL Nothing is assigned. Interrupt priority level select bit Interrupt request bit Polarity select bit Reserved bit 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Always set to “0” ILVL1 ILVL2 Note 1: Can only be written by "0" (Please do not write "1" to this bit) (Note 1) 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Interrupt Enable Flag (I flag) The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set to “0” after reset. Interrupt Request Bit The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The interrupt request bit can also be set to "0" by software. (Do not set this bit to "1"). Table.DD-4 Interrupt levels enabled according to the contents of the IPL Table.DD-3 Settings of interrupt priority levels Interrupt Priority Level Select Bits and Processor Interrupt Priority Level (IPL) Set the interrupt priority level using the interrupt priority level select bits in the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is en- abled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt priority level to “0” disables the interrupt. Table.DD-3 shows the settings of interrupt priority levels and Table.DD-4 shows the interrupt levels enabled, according to the consist of the IPL. The following are conditions under which an interrupt is accepted:

• interrupt enable flag (I flag) = 1
• interrupt request bit = 1
• interrupt priority level > processor interrupt priority level (IPL) The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bits, and the IPL are independent, and they are not affected each other. Interrupt priority level select bit Interrupt priority level Priority order 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Low High b2 b1 b0 Enabled interrupt priority levels 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 4 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled IPL2 IPL1 IPL0 IPL

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Example 1: INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. NOP ; Four NOP instructions are required when using HOLD function. NOP FSET I ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. MOV.W MEM, R0 ; Dummy read. FSET I ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG ; Push Flag register onto stack FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. POPC FLG ; Enable interrupts. The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. Rewrite the interrupt control register To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occurrence, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow: When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the inter- rupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execu- tion of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. In the interrupt sequence, the processor carries out the following in sequence given: (1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 00000 16. (2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU. (3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to “0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed) (4) Saves the content of the temporary register (Note) within the CPU in the stack area. (5) Saves the content of the program counter (PC) in the stack area. (6) Sets the interrupt priority level of the accepted instruction in the IPL. After the procession of interrupt sequence the processor executes instructions from the first address of the interrupt routine. Note: This register cannot be utilized by the user. Interrupt Response Time 'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruc- tion within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). Fig.DD-5 shows the interrupt response time. Fig.DD-5 Interrupt response time Instruction Interrupt sequence Instruction in interrupt routine Time Interrupt response time (a) (b) Interrupt request acknowledgedInterrupt request generated

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Interrupt sources without priority levels Value set in the IPL Watchdog timer, NMI Other Not changed Variation of IPL when Interrupt Request is Accepted If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in Table.DD-6 is set in the IPL. Table.DD-6 Relationship between interrupts without interrupt priority levels and IPL Stack pointer (SP) valueInterrupt vector address 16-Bit bus, without wait 8-Bit bus, without wait Even Even Odd (Note 2) Odd (Note 2) Even Odd Even Odd 18 cycles (Note 1) 19 cycles (Note 1) 19 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) Table.DD-5 Time required for executing the interrupt sequence Reset Time (a) is dependent on the instruction under execution. 30 cycles is the maximum required for the DIVX instruction (without wait). Time (b) is as shown in Table.DD-5 Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence interrupt or of a single-step interrupt. Note 2: Locate an interrupt vector address in an even address, if possible. Fig.DD-6 Time required for executing the interrupt sequence Indeterminate 123456789 1 0 1 1 12 13 14 15 16 17 18 The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs. Indeterminate SP-2

contents

0000 Indeterminate SP-2 SP-4 vec vec+2 PC

W R

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Saving Registers In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the stack area. First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. Fig.DD-7 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM instruction alone can save all the registers except the stack pointer (SP). Fig.DD-7 State of stack before and after acceptance of interrupt request Address Content of previous stack Stack area [SP] Stack pointer value before interrupt occurs m m – 1 m – 2 m – 3 m – 4 Stack status before interrupt request is acknowledged Stack status after interrupt request is acknowledged Content of previous stackm + 1 MSB LSB m m – 1 m – 2 m – 3 m – 4 Address Flag register (FLGL) Content of previous stack Stack area Flag register (FLGH ) Program counter (PCH ) [SP] New stack pointer value Content of previous stackm + 1 MSB LSB Program counter (PC Program counter (PCM ) The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Fig.DD-8 shows the operation of the saving registers. Note: Stack pointer is indicated by U flag when software number 32 - 63 INT command is executed, otherwise is indicated by ISP. Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. (1) Saved simultaneously, all 16 bits (2) Stack pointer (SP) contains odd number [SP] (Odd) [SP] – 1 (Even) [SP] – 2 (Odd) [SP] – 3 (Even) [SP] – 4 (Odd) [SP] – 5 (Even) Address Sequence in which order registers are saved (2) (1) Finished saving registers in four operations. (3) (4) (1) Stack pointer (SP) contains even number [SP] (Even) [SP] – 1 (Odd) [SP] – 2 (Even) [SP] – 3 (Odd) [SP] – 4 (Even) [SP] – 5 (Odd) Address Program counter (PCM) Stack area Flag register (FLGL) Program counter (PCL) Sequence in which order registers are saved (2) Saved simultaneously, all 16 bits Finished saving registers in two operations. Program counter (PCM) Stack area Flag register (FLGL) Program counter (PCL) Saved simultaneously, all 8 bits Flag register (FLGH) Flag register (FLGH) Program counter (PCH) Program counter (PCH) Fig.DD-8 Operation of saving registers

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Returning from an Interrupt Routine Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter (PC), both of which have been saved in the stack area. Then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process resumes. Return the other registers saved by software within the interrupt routine using the POPM or similar instruc- tion before executing the REIT instruction. Interrupt Priority If there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level select bits. If the same interrupt priority level is assigned, however, the interrupt with higher hardware priority is accepted. Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. Fig.DD-9 shows the priorities of hardware interrupts. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine Interrupt priority level judgement circuit When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest priority level. Fig.DD-10 shows the circuit that judges the interrupt priority level..

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.DD-10 Interrupt priority judgement circuit Timer B2/Key input interrupt 1 Timer B0/INT11/SCL0,SDA0 Timer A3/IBF2 Timer A1/INT7 Timer B1/INT10/SCL1,SDA1 Timer A4/IBF3 Timer A2 UART1 reception/SCL1,SDA1/INT10 UART0 reception/SCL0,SDA0/INT11 UART2 reception/IBF1 A-D conversion DMA1/INT7 Bus collision detection/INT4 Timer A0/INT8 UART1 transmission/I2C1 UART0 transmission/I2C0 UART2 transmission/IBF0 Key input interrupt 0 DMA0/INT8 Processor interrupt priority level (IPL) Interrupt enable flag (I flag) INT1/PS21 INT2/PS22 INT0/PS20 Watchdog timer Reset DBC NMI Level 0 (initial value)Priority level of each interrupt High Low Priority of peripheral I/O interrupts (if priority levels are same) Timer B4 INT3 Timer B3 Timer B5/INT9 Serial I/O4/INT6 Serial I/O3/INT5 Address match Interrupt request accepted To interrupt request level judgment output clock generation circuit (Fig. WA-3) Fig.DD-9 Hardware interrupts priorities Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 INT Interrupt INT0 to INT11 are triggered by the edges of external inputs. The edge polarity can be selected using the polarity select bit. INT0 to INT2 and INT4 to INT11 have polarity switching bit in the interrupt event select register. The polarity switching bit has to set to "0" when INT interrupt event is not selected. As for external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge by setting “1” in the INTi interrupt polarity switching bit of the interrupt factor selection register0,4 (035F16,035916). To select both edges, set the polarity switching bit of the corresponding interrupt control register to ‘falling edge’ (“0”). Fig.DD-11, Fig.DD-13 show the Interrupt factor selection register 0, 4. Fig.DD-11 Interrupt factor selection register(1) INT Interrupt Interrupt factor selection register 0 Bit name FunctionBit symbol W R Symbol Address When reset IFSR0 035F 16 0016 IFSR00 b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines INT0 interrupt polarity switching bit 0 : SIO3 1 : INT5 0 : SIO4 1 : INT6 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges INT1 interrupt polarity switching bit INT2 interrupt polarity switching bit INT3 interrupt polarity switching bit INT4 interrupt polarity switching bit INT5 interrupt polarity switching bit 0 : One edge 1 : Two edges Interrupt factor selection bit (Selecting interrupt factor in the address of 0049 16) Interrupt factor selection bit (Selecting interrupt factor in the address of 0048 16) IFSR01 IFSR02 IFSR03 IFSR04 IFSR05 IFSR06 IFSR07 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Factor selection Numbers of interrupt factors share the same interrupt registers in the addresses of 004516, 004816 - 004C16, 004F16 - 005616, 005816 -005F16. The setting of interrupt factor selection bits of interrupt factor selection registers 0 - 3 (addresses of 035F16, 035616 - 035816) select the interrupt factor. After the selection of interrupt factor, the corresponding interrupt request bit must be "0" before enabling the interrupt. Fig.DD-11 - Fig.DD-13 show the structure of interrupt factor selection register 0 - 3.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.DD-12 Interrupt factor selection register(2) Interrupt factor selection register 1 Bit name FunctionBit symbol W R Symbol Address When reset IFSR1 0356 16 0016 IFSR10 b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Interrupt factor selection bit (Selecting interrupt factor in the address of 0045 16) 0 : TimerB5 1 : INT9 /LiteDiagLines/LiteDiagLines /LiteDiagLines 0 : Bus collision detection 1 : INT4 Interrupt factor selection bit (Selecting interrupt factor in the address of 004A 16) IFSR11 /LiteDiagLines/LiteDiagLines /LiteDiagLines 0 : UART0 transmission 1 : I2C0 0 : UART1 transmission 1 : I 2C1 0 : DMA0 1 : INT8 0 : DMA1 1 : INT7 0 : UART2 transmission 1 : IBF0 Interrupt factor selection bit (Selecting interrupt factor in the address of 004B 16) Interrupt factor selection bit (Selecting interrupt factor in the address of 004C 16) Interrupt factor selection bit (Selecting interrupt factor in the address of 0050 16) 0 : UART2 reception 1 : IBF1 Interrupt factor selection bit (Selecting interrupt factor in the address of 0051 16) Interrupt factor selection bit (Selecting interrupt factor in the address of 0053 16) IFSR12 IFSR13 IFSR14 IFSR15 IFSR16 IFSR17 /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines Interrupt factor selection register 2 Bit name FunctionBit symbol W R Symbol Address When reset IFSR2 0357 16 0016 IFSR20 b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Interrupt factor selection bit (Note1) (Selecting interrupt factor in the address of 0052 16) 0 0 : UART0 reception 0 1 : SCL0,SDA0 1 0 : INT11 1 1 : Inhibited Interrupt factor selection bit (Note1) (Selecting interrupt factor in the address of 0054 16) Interrupt factor selection bit (Note1) (Selecting interrupt factor in the address of 005A 16) Interrupt factor selection bit (Note1) (Selecting interrupt factor in the address of 005B 16) IFSR21 IFSR22 IFSR23 IFSR24 IFSR25 IFSR26 IFSR27 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines Note1 : Do not select INT10, INT11, SCL0, SDA0, SCL1, SDA1 simultaneously in the interrupt control registers. Interrupt factor selection bit (Selecting interrupt factor in the address of 004F 16) Note 1: Do not select the bit if INT7, INT8 are selected by interrupt factor selection register 3. (Note1) (Note1) b1 b0 0 0 : UART1 reception 0 1 : SCL1,SDA1 1 0 : INT10 1 1 : Inhibited b3 b2 0 0 : TimerB0 0 1 : INT11 1 0 : SCL0,SDA0 1 1 : Inhibited b5 b4 0 0 : TimerB1 0 1 : INT10 1 0 : SCL1,SDA1 1 1 : Inhibited b7 b6

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.DD-13 Interrupt factor selection register(3) Interrupt factor selection register 3 Bit name FunctionBit symbol W R Symbol Address When reset IFSR3 0358 16 0016 IFSR30 b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Interrupt factor selection bit (Selecting interrupt factor in the address of 0055 16) 0 : INT1 1 : PS21 0 : INT2 1 : PS22 0 : TimerA0 1 : INT8 0 : TimerA1 1 : INT7 0 : TimerA3 1 : IBF2 0 : TimerA4 1 : IBF3 0 : TimerB2 1 : Key input interrupt 1 Interrupt factor selection bit (Selecting interrupt factor in the address of 0056 16) 0 : INT0 1 : PS20 IFSR31 IFSR32 IFSR33 IFSR34 IFSR35 IFSR36 IFSR37 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Interrupt factor selection register 4 Bit name FunctionBit symbol W R Symbol Address When reset IFSR4 0359 16 0016 IFSR40 b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines INT6 Interrupt polarity switching bit 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges INT7 Interrupt polarity switching bit INT8 Interrupt polarity switching bit INT9 Interrupt polarity switching bit INT10 Interrupt polarity switching bit INT11 Interrupt polarity switching bit 0 : One edge 1 : Two edges IFSR41 IFSR42 IFSR43 IFSR44 IFSR45 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines (Note1) (Note1) Note1: Do not select the bit if INT7, INT8 are selected by interrupt factor selection register 1. Nothing is assigned Interrupt factor selection bit (Selecting interrupt factor in the address of 0058 16) Interrupt factor selection bit (Selecting interrupt factor in the address of 0059 16) Interrupt factor selection bit (Selecting interrupt factor in the address of 005C 16) Interrupt factor selection bit (Selecting interrupt factor in the address of 005D 16) Interrupt factor selection bit (Selecting interrupt factor in the address of 005E 16) Interrupt factor selection bit (Selecting interrupt factor in the address of 005F 16)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.DD-14 Block diagram of key input interrupt 0 NMI Interrupt An NMI interrupt is generated when the input to the P85/NMI pin changes from “H ” to “L”. The NMI interrupt is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address 03F016). This pin cannot be used as a normal port input. Key Input Interrupt 0 If the direction register of any of P50 to P57 is set for input and a falling edge is input to that port, a key input interrupt 0 is generated. A key input interrupt 0 can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. Fig.DD-14 shows the block diagram of the key input interrupt 0. Note that if an “L” level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an interrupt. Key Input Interrupt 1 If the direction register of any of P140 to P147 is set for input and a falling edge is input to that port, a key input interrupt 1 is generated. The key input interrupt 1's function is equity to key input interrupt 0 except for the valid falling edge input will be latched. When there is a valid falling edge input in P14 0 to P147 the corre- sponding bit of P14 event register (Address : 02F616) will be set to "1". After interrupt request is generated, the interrupt generated by "L" input can be conformed by reading the the register even the pin has been returned to "H". A dummy write to the P14 event register clears the register to "0". The block diagram of key input interrupt 1 is shown on Fig.DD-15 and the timing diagram of key input interrupt 1 is shown on Fig.DD-16. NMI Interrupt Interrupt control circuit Key input interrupt 0 control register (address 004D16) Key input interrupt 0 request P57/KI07 P56/KI06 P55/KI05 P54/KI04 Pull-up select bit Port P57 direction register Pull-up transistor Port P57 direction register Port P56 direction register Port P55 direction register Port P54 direction register Pull-up transistor Pull-up transistor Pull-up transistor P53/KI03 P52/KI02 P51/KI01 Port P53 direction register Port P52 direction register Port P51 direction register Pull-up transistor Pull-up transistor Pull-up transistor P50/KI00 Port P50 direction registerPull-up transistor

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.DD-15 Block diagram of key input interrupt 1 (005C16) Key input interrupt 1 request 02F616 read DB6P146 event latch circuit 02F616 write P146/KI16 Pull-up transistor P146 direction register Pull-up select bit P147 direction register Pull-up transistor P147/KI17 P147 direction register P145/KI15 Pull-up transistor P145 direction register P144/KI14 Pull-up transistor P144 direction register P143/KI13 Pull-up transistor P143 direction register P142/KI12 Pull-up transistor P142 direction register P141/KI11 Pull-up transistor P141 direction register P140/KI10 Pull-up transistor P140 direction register Falling edge detection one-shot generate circuit 02F616 read 02F616 write DB7P147 event latch circuit 02F616 read DB5P145 event latch circuit 02F616 write 02F616 read DB4P144 event latch circuit 02F616 write 02F616 read DB3P143 event latch circuit 02F616 write 02F616 read DB2P142 event latch circuit 02F616 write 02F616 read DB1P141 event latch circuit 02F616 write 02F616 read DB0P140 event latch circuit 02F616 write Interrupt control circuit Key input interrupt 1 register SQ RQ C Fig.DD-16 Block diagram of key input interrupt 1 P14 event request Key input interrupt 1 request P140 P141 P142 0116 0116Read out data from address 02F616 Write signal of address 02F616 0016 0416 0616 0616 00160016 0016 Interrupt process Interrupt process Interrupt process Note 1: The input sequence order can not be conformed if there are numbers of valid falling edge inputs, Note2 : If the valid falling edge input and the write to the address of 02F616 occur simultaneously, the event may not be latched. (Note1) (Note2) Interrupt request bit

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Address Match Interrupt An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). The stacked value of the program counter (PC) for an address match interrupt varies depending on the instruction being executed. Fig.DD-17 shows the address match interrupt-related registers. Fig.DD-17 Address match interrupt-related registers Address Match Interrupt Bit name Bit symbol Symbol Address When reset AIER 0009 16 XXXXXX00 2 Address match interrupt enable register Function W R /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Address match interrupt 0 enable bit 0 : Interrupt disabled 1 : Interrupt enabled AIER0 Address match interrupt 1 enable bit AIER1 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Symbol Address When reset RMAD0 0012 16 to 001016 X0000016 RMAD1 0016 16 to 001416 X0000016 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminated. b7 b6 b5 b4 b3 b2 b1 b0 W R Address setting register for address match interrupt Function Values that can be set Address match interrupt register i (i = 0, 1) 0000016 to FFFFF16 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminated. 0 : Interrupt disabled 1 : Interrupt enabled b0 b7 b0 b3 (b19) (b16) b7 b0 (b15) (b8) (b23) /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Precautions for Interrupts (1) Reading address 0000016

• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 00000 16 will then be set to “0”. Reading address 0000016 by software sets the request bit, which the interrupt source is enabled with the highest priority, to “0”. Though the interrupt is generated, the interrupt routine may not be executed. Hence do not read address 00000 16 by software. (2) Setting the stack pointer
• The value of the stack pointer is initialized to 000016 right after the reset. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point at the beginning of a program. Concerning the first instruction immediately after reset, generating any interrupts including the NMI interrupt is prohibited. (3) The NMI interrupt
• As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the Vcc pin via a resistor (pull- up) if unused. Be sure to work on it.
• The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time when the NMI interrupt is input.
• Do not reset the CPU with the input to the NMI pin being in the “L” state.
• Do not attempt to go into stop mode with the input to the NMI pin being in the “L” state. With the input to the NMI being in the “L” state, the CM10 is fixed to “0”, so attempting to go into stop mode is turned down.
• Do not attempt to go into wait mode with the input to the NMI pin being in the “L” state. With the input to the NMI pin being in the “L” state, the CPU stops but the oscillation does not stop, so no power is saved. In this instance, the CPU is returned to the normal state by a later interrupt.
• Signals input to the NMI pin require an "L" level of 1 clock or more, from the operation clock of the CPU. (4) External interrupt
• Either an “L” level or an “H ” level of at least 380 ns width is necessary for the signal input to pins INT0 through INT11 regardless of the CPU operation clock.
• When the polarity of the INT0 to INT11 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0". Fig.DD-18 shows the procedure for changing the INT interrupt generate factor. Precautions for Interrupts

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.DD-18 Switching condition of INT interrupt request Precautions for Interrupts Example 1: INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. NOP ; Four NOP instructions are required when using HOLD function. NOP FSET I ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. MOV.W MEM, R0 ; Dummy read. FSET I ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG ; Push Flag register onto stack FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. POPC FLG ; Enable interrupts. The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. (5) Rewrite the interrupt control register

• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occurs, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow:
• When a instruction to rewrite the interrupt control register is executed when the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the regis- ter. Instructions : AND, OR, BCLR, BSET Set the polarity select bit Clear the interrupt request bit to “0” Set the interrupt priority level to level 1 to 7 (Enable the accepting of INTi interrupt request) Set the interrupt priority level to level 0 (Disable INTi interrupt) Clear the interrupt enable flag to “0” (Disable interrupt) Set the interrupt enable flag to “1” (Enable interrupt)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Watchdog Timer The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. When X IN is selected for the BCLK , bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000F16). Thus the watchdog timer's period can be calculated as given below. The watchdog timer's period is, however, subject to an error due to the pre-scaler. For example, suppose that BCLK runs at 10 MHz and that 16 has been chosen for the dividing ratio of the pre-scaler, then the watchdog timer's period becomes approximately 52.4 ms. The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by writing to the watchdog timer start register (address 000E 16). Fig.DG-1 shows the block diagram of the watchdog timer. Fig.DG-2 shows the watchdog timer-related reg- isters. With X IN chosen for BCLK Watchdog timer period = pre-scaler dividing ratio (16 or 128) X watchdog timer count (32768) BCLK With XCIN chosen for BCLK Watchdog timer period = pre-scaler dividing ratio (2) X watchdog timer count (32768) BCLK Fig.DG-1 Block diagram of watchdog timer BCLK Write to the watchdog timer start register (address 000E 16) RESET Watchdog timer interrupt request Watchdog timer Set to “7FFF 16” “CM07 = 0” “WDC7 = 1 ” “CM07 = 0” “WDC7 = 0 ” “CM07 = 1” HOLD Prescaler

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.DG-2 Watchdog timer control and start registers Watchdog timer control register Symbol Address When reset WDC 000F 16 000XXXXX 2 FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 High-order bit of watchdog timer WDC7 Bit name Prescaler select bit 0 : Divided by 16 1 : Divided by 128 Watchdog timer start register Symbol Address When reset WDTS 000E 16 Indeterminate W R b7 b0 Function The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to “7FFF 16” regardless of whatever value is written. Reserved bit Reserved bit Must always be set to “0” Must always be set to “0” 0 0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERDMAC Rev.1.0 DMAC This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16-bit) or 1-byte (8-bit) data transfer can be performed at high speed. Fig.EC-1 shows the block diagram of the DMAC. Table.EC-1 shows the DMAC specifications. Fig.EC-2 to EC-4 show the registers used by the DMAC. Fig.EC-1 Block diagram of DMAC Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt priority level. The DMA transfer doesn't affect any interrupts neither. If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the number of transfers. For details, see the description of the DMA request bit. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Data bus low-order bits DMA latch high-order bitsDMA latch low-order bits DMA0 source pointer SAR0(20) DMA0 destination pointer DAR0 (20) DMA0 forward address pointer (20) (Note) Data bus high-order bits /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Address bus /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines DMA1 destination pointer DAR1 (20) DMA1 source pointer SAR1 (20) DMA1 forward address pointer (20) (Note)/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines DMA0 transfer counter reload register TCR0 (16) DMA0 transfer counter TCR0 (16) DMA1 transfer counter reload register TCR1 (16) DMA1 transfer counter TCR1 (16) /LiteDiagLines /LiteDiagLines (addresses 002916, 002816) (addresses 003916, 003816) (addresses 002216 to 002016) (addresses 002616 to 002416) (addresses 003216 to 003016) (addresses 003616 to 003416) Note: Pointer is incremented by a DMA request. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Item Specification No. of channels 2 (cycle steal method) Transfer memory space •From any address in the 1M bytes space to a fixed address

• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address (Note that DMA-related registers [002016 to 003F16] cannot be accessed) Maximum No. of bytes transferred128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers) DMA request factors (Note) Falling edge of INT0 or INT1 or both edge Timer A0 to timer A4 interrupt requests Timer B0 to timer B5 interrupt requests UART0 transfer and reception interrupt requests UART1 transfer and reception interrupt requests UART2 transfer and reception interrupt requests Serial I/O3, 4 interrpt requests A-D conversion interrupt requests IBF0 to IBF3 interrupt requests Software triggers Channel priority DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously Transfer unit 8 bits or 16 bits Transfer address direction forward/fixed (forward direction cannot be specified for both source and destination simultaneously) Transfer mode •Single transfer mode After the transfer counter underflows, the DMA enable bit turns to “0”, and the DMAC turns inactive
• Repeat transfer mode After the transfer counter underflows, the value of the transfer counter reload register is reloaded to the transfer counter. The DMAC remains active unless a “0” is written to the DMA enable bit. DMA interrupt request generation timingWhen an underflow occurs in the transfer counter Active When the DMA enable bit is set to “1”, the DMAC is active. When the DMAC is active, data transfer starts every time a DMA transfer request signal occurs. Inactive •When the DMA enable bit is set to “0”, the DMAC is inactive.
• After the transfer counter underflows in single transfer mode At the time of starting data transfer immediately after turning the DMAC active, the value of one of source pointer and destination pointer - the one specified for the forward direction - is reloaded to the forward direction address pointer,and the value of the transfer counter reload register is reloaded to the transfer counter. Writing to register Registers specified for forward direction transfer are always write enabled. Registers specified for fixed address transfer are write-enabled when the DMA enable bit is “0”. Reading the register Can be read at any time. However, when the DMA enable bit is “1”, reading the register set up as the forward register is the same as reading the value of the forward address pointer. Table.EC-1 DMAC specifications Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt priority level. Forward address pointer and reload timing for transfer counter

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERDMAC Rev.1.0 Fig.EC-2 DMAC register (1) DMA0 request factor selection register Symbol Address When reset DM0SL 03B8 16 0016 FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 DMA request factor selection bitsDSEL0 RW DSEL1 DSEL2 DSEL3 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Software DMA request bit If software trigger is selected, a DMA request is generated by setting this bit to “1” (When read, the value of this bit is always “0”) DSR b3 b2 b1 b0 0 0 0 0 : Falling edge of INT0 pin 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3 0 1 1 0 : Timer A4 (DMS=0) /two edges of INT0 pin (DMS=1) 0 1 1 1 : Timer B0 (DMS=0) Timer B3 (DMS=1) 1 0 0 0 : Timer B1 (DMS=0) Timer B4 (DMS=1) 1 0 0 1 : Timer B2 (DMS=0) Timer B5 (DMS=1) 1 0 1 0 : UART0 transmit (DMS=0) /IBF0(DMS=1) 1 0 1 1 : UART0 receive (DMS=0) /IBF1(DMS=1) 1 1 0 0 : UART2 transmit (DMS=0) /IBF2(DMS=1) 1 1 0 1 : UART2 receive(DMS=0) /IBF3(DMS=1) 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 transmit /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Bit name DMA request factor expansion bit DMS 0 : Normal 1 : Expanded factor /LiteDiagLines/LiteDiagLines/LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.EC-3 DMAC register (2) DMAi control register Symbol Address When reset DMiCON(i=0,1) 002C 16, 003C16 00000X002 Bit name Function Bit symbol Transfer unit bit select bit b7 b6 b5 b4 b3 b2 b1 b0 0 : 16 bits 1 : 8 bits DMBIT RW DMASL DMAS DMAE Repeat transfer mode select bit 0 : Single transfer 1 : Repeat transfer DMA request bit (Note 1)0 : DMA not requested 1 : DMA requested 0 : Disabled 1 : Enabled 0 : Fixed 1 : Forward DMA enable bit Source address direction select bit (Note 3) Destination address direction select bit (Note 3) 0 : Fixed 1 : Forward DSD DAD Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Note 1: DMA request can be cleared by resetting the bit to "0". Note 2: This bit can only be set to “0”. Note 3: Source address direction select bit and destination address direction select bit cannot be set to “1” simultaneously. (Note 2) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines DMA1 request factor selection register Symbol Address When reset DM1SL 03BA 16 0016 FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 DMA request factor selection bits DSEL0 RW DSEL1 DSEL2 DSEL3 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Software DMA request bit If software trigger is selected, a DMA request is generated by setting this bit to “1” (When read, the value of this bit is always “0”) DSR b3 b2 b1 b0 0 0 0 0 : Falling edge of INT1 pin 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3(DMS=0) /serial I/O3 (DMS=1) 0 1 1 0 : Timer A4 (DMS=0) /serial I/O4 (DMS=1) 0 1 1 1 : Timer B0 (DMS=0) /two edges of INT1 (DMS=1) 1 0 0 0 : Timer B1 1 0 0 1 : Timer B2 1 0 1 0 : UART0 transmit (DMS=0) /IBF0(DMS=1) 1 0 1 1 : UART0 receive (DMS=0) /IBF1(DMS=1) 1 1 0 0 : UART2 transmit(DMS=0) /IBF2(DMS=1) 1 1 0 1 : UART2 receive(DMS=0) /IBF3(DMS=1) 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 receive /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Bit name DMA request factor expansion bit DMS 0 : Normal 1 : Expanded factor /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERDMAC Rev.1.0 Fig.EC-4 DMAC register (3) b7 b0 b7 b0 (b8) (b15) Function RW

• Transfer counter Set a value one less than the transfer count Symbol Address When reset TCR0 0029 16, 002816 Indeterminate TCR1 0039 16, 003816 Indeterminate DMAi transfer counter (i = 0, 1) Transfer count specification 000016 to FFFF16 (b23) b3 b0 b7 b0 b7 b0 Function RW
• Source pointer Stores the source address Symbol Address When reset SAR0 0022 16 to 002016 Indeterminate SAR1 0032 16 to 003016 Indeterminate DMAi source pointer (i = 0, 1) Transfer count specification 0000016 to FFFFF16 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Symbol Address When reset DAR0 0026 16 to 002416 Indeterminate DAR1 0036 16 to 003416 Indeterminate b3 b0 b7 b0 b7 b0 Function RW
• Destination pointer Stores the destination address DMAi destination pointer (i = 0, 1) Transfer count specification 0000016 to FFFFF16 (b23) Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 (1) Transfer cycle The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) and the bus cycle in which the data is written to memory or to the SFR area (destination write). The number of read and write bus cycles depends on the source and destination addresses. * Effect of source and destination addresses When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there are one more source read cycle and destination write cycle than when the source and destination both start at even addresses. Fig.EC-5 shows the example of the transfer cycles for a source read. For convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respective conditions to both the destination write cycle and the source read cycle. For example (2) in Fig.EC-5, if data are being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the source read cycle and the destination write cycle. (2) DMAC transfer cycles Any combination of even or odd transfer read and write addresses is possible. Table.EC-2 shows the num- ber of DMAC transfer cycles. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k Single-chip mode Memory expansion mode Transfer unit Bus width Access address Microprocessor mode No. of read No. of write No. of read No. of write cycles cycles cycles cycles 16-bit Even 1 1 1 1 8-bit transfers (BYTE= “L”) Odd 1 1 1 1 (DMBIT= “1”) 8-bit Even —— 11 (BYTE = “H ”) Odd —— 11 16-bit Even 1 1 1 1 16-bit transfers (BYTE = “L”) Odd 2 2 2 2 (DMBIT= “0”) 8-bit Even —— 22 (BYTE = “H ”) Odd —— 22 Table.EC-2 No. of DMAC transfer cycles Internal memory External memory Internal ROM/RAM Internal ROM/RAM SFR area Separate bus Separate bus Multiplex No wait With wait No wait With wait bus 12 2 1 2 3 Coefficient j, k

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERDMAC Rev.1.0 Fig.EC-5 Example of the transfer cycles for a source read BCLK Address bus RD signal WR signal Data bus CPU use CPU use CPU use CPU useSource Source Destination Destination Dummy cycle Dummy cycle (1) 8-bit transfers 16-bit transfers from even address and the source address is even. BCLK Address bus RD signal WR signal Data bus CPU use CPU use CPU use CPU useSource Source Destination Destination Dummy cycle Dummy cycle (3) One wait is inserted into the source read under the conditions in (1) BCLK Address bus RD signal WR signal Data bus CPU use CPU use CPU use CPU useSource Source Destination Destination Dummy cycle Dummy cycle Source + 1 Source + 1 (2) 16-bit transfers and the source address is odd Transferring 16-bit data on an 8-bit data bus (In this case, there are also two destination write cycles). BCLK Address bus RD signal WR signal Data bus CPU use CPU use CPU use CPU useSource Source Destination Destination Dummy cycle Dummy cycle Source + 1 Source + 1 (4) One wait is inserted into the source read under the conditions in (2) (When 16-bit data is transferred on an 8-bit data bus, there are two destination write cycles). Note: The same timing changes occur with the respective conditions at the destination as at the source.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 DMA enable bit Setting the DMA enable bit to "1" makes the DMAC active. The DMAC carries out the following operations at the time data transfer starts immediately after DMAC is turned active. (1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the forward direction - to the forward direction address pointer. (2) Reloads the value of the transfer counter reload register to the transfer counter. Thus overwriting "1" to the DMA enable bit with the DMAC being active carries out the operations given above, so the DMAC operates again from the initial state at the instant "1" is overwritten to the DMA enable bit. DMA request bit The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of DMA request factors for each channel. DMA request factors include the following. * Factors effected by using the interrupt request signals from the built-in peripheral functions and software DMA factors (internal factors) effected by a program. * External factors effected by utilizing the input from external interrupt signals. For the selection of DMA request factors, see the descriptions of the DMAi factor selection register. The DMA request bit turns to "1" if the DMA transfer request signal occurs regardless of the DMAC's state (regardless of whether the DMA enable bit is set "1" or to "0"). It turns to "0" immediately before data transfer starts. In addition, it can be set to "0" by use of a program, but cannot be set to "1". There can be instances in which a change in DMA request factor selection bit causes the DMA request bit to turn to "1". So be sure to set the DMA request bit to "0" after the DMA request factor selection bit is changed. The DMA request bit turns to "1" if a DMA transfer request signal occurs, and turns to "0" immediately just before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the DMA request bit, if read by use of a program, turns out to be "0" in most cases. To examine whether the DMAC is active, read the DMA enable bit. Here follows the timing of changes in the DMA request bit. (1) Internal factors Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to "1" due to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to turn to "1" due to several factors. Turning the DMA request bit to "0" due to an internal factor is timed to be effected immediately just before the transfer starts. (2) External factors An external factor is a factor caused to occur by the edge of input from the INTi pin (i depends on which DMAC channel is used). Selecting the INTi pins as external factors using the DMA request factor selection bit causes input from these pins to become the DMA transfer request signals. The timing for the DMA request bit to turn to "1" when an external factor is selected synchronizes with the signal's edge applicable to the function specified by the DMA request factor selection bit (synchronizes with the falling edge of the input signal to each INTi pin, for example). With an external factor selected, the DMA request bit is timed to turn to "0" immediately just before data transfer starts similarly to the state in which an internal factor is selected.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERDMAC Rev.1.0 (3) The priorities of channels and DMA transfer timing If a DMA transfer request signal falls on tne same sampling cycle (a sampling cycle means one period from the rising edge to the falling edge of BCLK), the DMA request bits of applicable channels concurrently turn to "1". If the channels are active at that moment, DMA0 is given a high priority to start data transfer. When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU finishes single bus access, then DMA1 starts data transfer and gives the bus right to the CPU. An example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer request signals due to external factors concurrently occur. Fig.EC-6 An example of DMA transfer effected by external factors. Fig.EC-6 An example of DMA transfer effected by external factors BCLK /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLinesDMA0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLinesDMA1 DMA0 request bit DMA1 request bit /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLinesCPU INT0 INT1 Obtaining the bus right An example in which DMA transmission is carried out in minimum cycles at the time when DMA transmission request signals due to external factors concurrently occur.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Timer There are eleven 16-bit timers. These timers can be classified by function into timers A (five) and timers B (six). All these timers function independently. Fig.FB-1 and FB-2 show the block diagram of timers. Fig.FB-1 Timer A block diagram

• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode TA0 IN TA1 IN TA2 IN TA3 IN TA4 IN Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 f1 f8 f32 fC32 Timer A0 interrupt Timer A1 interrupt Timer A2 interrupt Timer A3 interrupt Timer A4 interrupt Noise filter Noise filter Noise filter Noise filter Noise filter 1/32 fC32 f32 XIN XCIN Clock prescaler reset flag (bit 7 at address 038116) set to “1” Reset Clock prescaler Timer B2 overflow Note 1: The TA0IN pin (P71) is shared with RxD2 and the TB5IN pin, so be careful.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.FB-2 Timer B block diagram

• Event counter mode
• Event counter mode
• Event counter mode
• Timer mode
• Pulse width measuring mode
• Timer mode
• Pulse width measuring mode
• Timer mode
• Pulse width measuring mode TB0 IN TB1 IN TB2 IN Timer B0 Timer B1 Timer B2 f1 f8 f32 fC32 Timer B0 interruptNoise filter Noise filter Noise filter 1/32 fC32 f32 XIN XCIN Clock prescaler reset flag (bit 7 at address 038116) set to “1” Reset Clock prescaler Timer A
• Event counter mode
• Event counter mode
• Event counter mode
• Timer mode
• Pulse width measuring mode
• Timer mode
• Pulse width measuring mode
• Timer mode
• Pulse width measuring mode TB3 IN TB4 IN TB5 IN Timer B3 Timer B4 Timer B5 Timer B3 interrupt Noise filter Noise filter Noise filter Timer B1 interrupt Timer B2 interrupt Timer B4 interrupt Timer B5 interrupt Note 1: The TB5IN pin (P71) is shared with RxD2 and the TA0IN pin, so be careful.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Timer A Fig.FB-3 shows the block diagram of timer A. Fig.FB-4 to FB-6 show the timer A-related registers. Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode. Timer A has the four operation modes listed as follows:

• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer over flow.
• One-shot timer mode: The timer stops counting when the count reaches “000016”.
• Pulse width modulation (PWM) mode: The timer continually outputs pulse with arbitrary width. Fig.FB-4 Timer A-related registers (1) Fig.FB-3 Block diagram of timer A Count start flag (Address 038016) Up count/down count TAi Addresses TAj TAk Timer A0 038716 038616 Timer A4 Timer A1 Timer A1 038916 038816 Timer A0 Timer A2 Timer A2 038B16 038A16 Timer A1 Timer A3 Timer A3 038D 16 038C 16 Timer A2 Timer A4 Timer A4 038F16 038E16 Timer A3 Timer A0 Always down count except in event counter mode Reload register (16) Counter (16) Low-order 8 bits /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines High-order 8 bits Clock source selection
• Timer (gate function)
• Timer
• One shot
• PWM f32 External trigger TAiIN (i = 0 to 4) TB2 overflow
• Event counter fC32 Clock selection TAj overflow (j = i – 1. Note, however, that j = 4 when i = 0) Pulse output Toggle flip-flop TAiOUT (i = 0 to 4) Data bus low-order bits Data bus high-order bits /LiteDiagLines /LiteDiagLines Up/down flag Down count (Address 038416) TAk overflow (k = i + 1. Note, however, that k = 0 when i = 4) Polarity selection Timer Ai mode register Symbol Address When reset TAiMR(i=0 to 4) 039616 to 039A16 0016 Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode b1 b0 TCK1 MR3 MR2 MR1 TMOD1 MR0 TMOD0 TCK0 Function varies with each operation mode Count source selection bits (Function varies with each operation mode) Operation mode selection bits /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.FB-5 Timer A-related registers (2) Timer A4 up/down flag Timer A3 up/down flag Timer A2 up/down flag Timer A1 up/down flag Timer A0 up/down flag Timer A2 two-phase pulse signal processing select bit Timer A3 two-phase pulse signal processing select bit Timer A4 two-phase pulse signal processing select bit Symbol Address When reset UDF 0384 16 0016 TA4P TA3P TA2P Up/down flag Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 TA4UD TA3UD TA2UD TA1UD TA0UD 0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching factor 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled When not using the two-phase pulse signal processing function, set the select bit to “0” Symbol Address When reset TABSR 0380 16 0016 Count start flag Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Timer B2 count start flag Timer B1 count start flag Timer B0 count start flag Timer A4 count start flag Timer A3 count start flag Timer A2 count start flag Timer A1 count start flag Timer A0 count start flag0 : Stop count 1 : Start count TB2S TB1S TB0S TA4S TA3S TA2S TA1S TA0S Symbol Address When reset TA0 0387 16,038616 Indeterminate TA1 0389 16,038816 Indeterminate TA2 038B 16,038A16 Indeterminate TA3 038D 16,038C16 Indeterminate TA4 038F 16,038E16 Indeterminate b7 b0 b7 b0 (b15) (b8) Timer Ai register (Note) W R

• Timer mode Count the internal count source Function Values that can be set
• Event counter mode Count pulses from external input or the overflow of timer
• One-shot timer mode Count one shot width /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines
• Pulse width modulation mode (16-bit PWM) Function as a 16-bit pulse width modulator
• Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 16 to FE16 (Both high-order and low-order addresses) 000016 to FFFE16 Note: Read and write data in 16-bit units. /LiteDiagLines /LiteDiagLines /LiteDiagLines 000016 to FFFF16 000016 to FFFF16 000016 to FFFF16

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Symbol Address When reset CPSRF 0381 16 0XXXXXXX 2 Clock prescaler reset flag Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Clock prescaler reset flag0 : No effect 1 : Prescaler is reset (When read, the value is “0”) CPSR W R Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. TA1TGL Symbol Address When reset TRGSR 0383 16 0016 Timer A1 event/trigger selection bits 0 0 : Input on TA1IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected Trigger selection register Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : Input on TA2IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA1 overflow is selected 1 1 : TA3 overflow is selected 0 0 : Input on TA3IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA2 overflow is selected 1 1 : TA4 overflow is selected 0 0 : Input on TA4IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA3 overflow is selected 1 1 : TA0 overflow is selected Timer A2 event/trigger selection bits Timer A3 event/trigger selection bits Timer A4 event/trigger selection bits W R TA1TGH TA2TGL TA2TGH TA3TGL TA3TGH TA4TGL TA4TGH b1 b0 b3 b2 b5 b4 b7 b6 Note: Set the corresponding port direction register to “0”. TA1OS TA2OS TA0OS One-shot start flag Symbol Address When reset ONSF 0382 16 00X000002 Timer A0 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag TA3OS TA4OS Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. TA0TGL TA0TGH 0 0 : Input on TA0IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA4 overflow is selected 1 1 : TA1 overflow is selected Timer A0 event/trigger selection bits b7 b6 Note: Set the corresponding port direction register to “0”. W R 1 : Timer start When read, the value is “0” /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Fig.FB-6 Timer A-related registers (3)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Item Specification Count source f 1, f8, f32, fC32 Count operation • Down count

• When the timer underflows, it reloads the reload register contents and then continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingWhen the timer underflows TAiIN pin function Programmable I/O port or gate input TAiOUT pin function Programmable I/O port or pulse output Read from timer Count value can be read out by reading timer Ai register Write to timer • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Select function • Gate function Counting can be started and stopped by the TAiIN pin’s input signal
• Pulse output function Each time the timer underflows, the TAiOUT pin’s polarity is reversed (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table.FB-1) Fig.FB-7 shows the timer Ai mode register in timer mode. Table.FB-1 Specifications of timer mode Fig.FB-7 Timer Ai mode register in timer mode Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: The bit can be “0” or “1”. Note 3: Set the corresponding port direction register to “0”. Timer Ai mode register Symbol Address When reset TAiMR(i=0 to 4) 039616 to 039A16 0016 Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 Operation mode selection bits 0 0 : Timer mode b1 b0 TMOD1 TMOD0 MR0 Pulse output function selection bit 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TA iOUT pin is a pulse output pin) Gate function selection bits0 X (Note 2): Gate function not available (TAiIN pin is a normal port pin) 1 0 : Timer counts only when TAiIN pin is held “L” (Note 3) 1 1 : Timer counts only when TAiIN pin is held “H ” (Note 3) b4 b3 MR2 MR1 MR3 0 (Must always be fixed to “0” in timer mode) 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 TCK1 TCK0 Count source selection bits 000 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Item Specification Count source • External signal input to TAiIN pin (effective edge can be selected by software)

• TB2 overflow, TAj overflow Count operation • Up count or down count can be selected by external signal or software
• When the timer overflows or underflows, it reloads the reload register con tents and then continuing counting (Note) Divide ratio 1/ (FFFF 16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingThe timer overflows or underflows TAiIN pin function Programmable I/O port or count source input TAiOUT pin function Programmable I/O port, pulse output, or up/down count select input Read from timer Count value can be read out by reading timer Ai register Write to timer • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Select function • Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded to it
• Pulse output function Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed Note: This does not apply when the free-run function is selected. (2) Event counter mode In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase external signals. Table.FB-2 lists timer specifications and Fig. FB-8 shows the timer Ai mode register in event count mode when counting a single-phase external signal. Table.FB-3 lists timer specifications and Fig. FB-8 shows the timer Ai mode register in event count mode when counting a two-phase external signals. Table.FB-2 Timer specifications in event counter mode (when not processing two-phase pulse signal) Fig.FB-8 Timer Ai mode register in event counter mode Timer Ai mode register Note 1: In event counter mode, the count source is selected by the event / trigger select bit (addresses 038216 and 038316). Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Valid only when counting an external signal. Note 4: When an “L” signal is input to the TAi OUT pin, the downcount is activated. When “H ”, the upcount is activated. Set the corresponding port direction register to “0”. Symbol Address When reset TAiMR(i = 0, 1) 039616, 039716 0016 W R b7 b6 b5 b4 b3 b2 b1 b0 Operation mode selection bits 0 1 : Event counter mode (Note 1) b1 b0 TMOD0 MR0 Pulse output function selection bit 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 2) (TAiOUT pin is a pulse output pin) Count polarity selection bit (Note 3) MR2 MR1 MR3 0 (Must always be fixed to “0” in event counter mode) TCK0 Count operation type selection bit 010 0 : Counts external signal's falling edge 1 : Counts external signal's rising edge Up/down switching factor selection bit 0 : Up/down flag's content 1 : TAiOUT pin's input signal (Note 4) 0 : Reload type 1 : Free-run type Bit symbol Bit name Function RW TCK1 Invalid in event counter mode Can be “0” or “1” TMOD1 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Item Specification Count source • Two-phase pulse signals input to TAiIN and TAiOUT pin Count operation • Up count or down count can be selected by two-phase pulse signals

• When the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (Note) Divide ratio 1/ (FFFF 16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingTimer overflows or underflows TAiIN pin function Two-phase pulse input TAiOUT pin function Two-phase pulse input Read from timer Count value can be read out by reading timer A2, A3, or A4 register Write to timer • When counting stopped When a value is written to timer A2, A3, or A4 register, it is written to both reload register and counter
• When counting in progress When a value is written to timer A2, A3, or A4 register, it is written to only reload register. (Transferred to counter at next reload time.) Select function • Normal processing operation The timer up-counts by the rising edge of TAiIN pin and down-counts by the falling edge fo TAiIN pin during the "H" level period of input signal in TAiOUT pin.
• Multiply-by-4 processing operation If the phase relationship is such that the TAi IN pin goes “H ” when the input signal on the TAiOUT pin is “H ”, the timer counts up rising and falling edges on the TAiOUT and TAiIN pins. If the phase relationship is such that the TAiIN pin goes “L” when the input signal on the TAiOUT pin is “H ”, the timer counts down rising and falling edges on the TAiOUT and TAiIN pins. Note: This does not apply when the free-run function is selected. Table.FB-3 Timer specifications in event counter mode (when processing two-phase pulse signals with timers A2, A3, and A4) TAiOUT Up count Up count Up count Down count Down count Down count TAiIN (i=2,3) TAiOUT TAiIN (i=3,4) Count up all edges Count up all edges Count down all edges Count down all edges

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.FB-9 Timer Ai mode register in event counter mode Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: This bit is valid when only counting an external signal. Note 3: Set the corresponding port direction register to “0”. Note 4: This bit is valid for the timer A3 mode register. For timer A2 and A4 mode registers, this bit can be “0 ”or “1”. Note 5: When performing two-phase signal processing, make sure the two-phase pulse signals' processing operation selection bit (address 0384 16) is set to “1”. Also, always be sure to set the event/trigger selection bit (addresses 038216 and 038316) to “00”. Timer Ai mode register (When not using two-phase pulse signals' processing) Symbol Address When reset TAiMR(i = 2 to 4) 0398 16 to 039A16 0016 b7 b6 b5 b4 b3 b2 b1 b0 Operation mode selection bits 0 1 : Event counter mode b1 b0 TMOD1 TMOD0 MR0 Pulse output function selection bit 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin) Count polarity selection bit (Note 2) MR2 MR1 MR3 0 : (Must always be “0” in event counter mode) TCK1 TCK0 010 0 : Counts external signal's falling edges 1 : Counts external signal's rising edges Up/down switching factor selection bit 0 : Up/down flag's content 1 : TAiOUT pin's input signal (Note 3) Bit symbol Bit name Function W R Count operation type selection bit Two-phase pulse signals' processing operation selection bit (Note 4)(Note 5) 0 : Reload type 1 : Free-run type 0 : Normal processing operation 1 : Multiply-by-4 processing operation /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Note 1: This bit is valid for timer A3 mode register. For timer A2 and A4 mode registers, this bit can be “0” or “1”. Note 2: When performing two-phase pulse signals' processing, make sure the two-phase pulse signals' processing operation selection bit (address 038416) is set to “1”. Also, always be sure to set the event/trigger selection bit (addresses 038216 and 038316) to “00”. Timer Ai mode register (When using two-phase pulse signals' processing) Symbol Address When reset TAiMR(i = 2 to 4) 039816 to 039A16 0016 b7 b6 b5 b4 b3 b2 b1 b0 Operation mode selection bits 0 1 : Event counter mode b1 b0 TMOD1 TMOD0 MR0 0 (Must always be “0” when using two-phase pulse signal processing) 0 (Must always be “0” when using two-phase pulse signal processing) MR2 MR1 MR3 0 (Must always be “0” when using two-phase pulse signal processing) TCK1 TCK0 010 1 (Must always be “1” when using two-phase pulse signal processing) Bit symbol Bit name Function W R Count operation type selection bit Two-phase pulse processing operation selection bit (Note 1)(Note 2) 0 : Reload type 1 : Free-run type 0 : Normal processing operation 1 : Multiply-by-4 processing operation 0 0 1 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Count source f 1, f8, f32, fC32 Count operation • The timer counts down

• When the count reaches 000016, the timer stops counting after reloading a new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting Divide ratio 1/n n : Set value Count start condition • An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1) Count stop condition • A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0) Interrupt request generation timingThe count reaches 000016 TAiIN pin function Programmable I/O port or trigger input TAiOUT pin function Programmable I/O port or pulse output Read from timer When timer Ai register is read, it indicates an indeterminate value Write to timer •When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Item Specification Fig.FB-10 Timer Ai mode register in one-shot timer mode (3) One-shot timer mode In this mode, the timer operates only once. (See Table.FB-4) When a trigger occurs, the timer starts to operate for a given period. Fig.FB-10 shows the timer Ai mode register in one-shot timer mode. Table.FB-4 Timer specifications in one-shot timer mode Bit name Timer Ai mode register Symbol Address When reset TAiMR(i = 0 to 4) 039616 to 039A16 0016 Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 Operation mode selection bits 1 0 : One-shot timer mode b1 b0 TMOD1 TMOD0 MR0 Pulse output function selection bit 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAi OUT pin is a pulse output pin) MR2 MR1 MR3 0 (Must always be “0” in one-shot timer mode) 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 TCK1 TCK0 Count source selection bits 100 0 : One-shot start flag is valid 1 : Selected by event/trigger selection register Trigger selection bit External trigger selection bit (Note 2) 0 : Falling edge of TAiIN pin's input signal (Note 3) 1 : Rising edge of TAiIN pin's input signal (Note 3) Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: Valid only when the TAiIN pin is selected by the event/trigger selection bit (addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”. Note 3: Set the corresponding port direction register to “0”. W R /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 (4) Pulse width modulation (PWM) mode In this mode, the timer outputs pulses of a given width in succession. (See Table.FB-5) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Fig.FB-11 shows the timer Ai mode register in pulse width modulation mode. Fig.FB-12 shows the example of how a 16-bit pulse width modulator operates. Fig.FB-13 shows the example of how an 8-bit pulse width modulator operates. Fig.FB-11 Timer Ai mode register in pulse width modulation mode Table.FB-5 Timer specifications in pulse width modulation mode Bit name Timer Ai mode register Symbol Address When reset TAiMR(i=0 to 4) 039616 to 039A16 0016 FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 Operation mode selection bits 1 1 : PWM mode b1 b0 TMOD1 TMOD0 MR0 MR2 MR1 MR3 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 TCK1 TCK0 Count source selection bits W R 111 1 (Must always be “1” in PWM mode) 16/8-bit PWM mode selection bit 0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator Trigger selection bit External trigger selection bit (Note 1) 0: Falling edge of TAiIN pin's input signal (Note 2) 1: Rising edge of TAiIN pin's input signal (Note 2) 0: Count start flag is valid 1: Selected by event/trigger selection register Note 1: Valid only when the TA iIN pin is selected by the event/trigger selection bit (addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”. Note 2: Set the corresponding port direction register to “0”. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Item Specification Count source f 1, f8, f32, fC32 Count operation • The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)

• The timer reloads a new count at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs when counting 16-bit PWM • High level width n / fi n : Set value
• Cycle time (2 16-1) / fi fixed 8-bit PWM • High level width n (m+1) / fi n : values set to timer Ai register’s high-order address
• Cycle time (2 8-1) (m+1) / fim : values set to timer Ai register’s low-order address Count start condition • External trigger is input
• The timer overflows
• The count start flag is set (= 1) Count stop condition • The count start flag is reset (= 0) Interrupt request generation timingThe falling edge of PWM pulse TAiIN pin function Programmable I/O port or trigger input TAiOUT pin function Pulse output Read from timer When timer Ai register is read, it indicates an indeterminate value Write to timer • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.FB-12 Example of how a 16-bit pulse width modulator operates Fig.FB-13 Example of how an 8-bit pulse width modulator operates 1 / fi X (2 – 1) 16 Count source TA iIN pin input signal PWM pulse output from TAiOUT pin Condition : Reload register = 000316, when external trigger (rising edge of TAiIN pin input signal) is selected Trigger is not generated by this signal “H ” “H ” “L” “L” Timer Ai interrupt request bit “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software fi : Frequency of count source (f1, f8, f32, fC32 ) Note: n = 000016 to FFFE16. 1 / fi X n Count source (Note1) TA iIN pin input signal Underflow signal of 8-bit prescaler (Note2) PWM pulse output from TA iOUT pin “H ” “H ” “H ” “L” “L” “L” “1” “0” Timer Ai interrupt request bit Cleared to “0” when interrupt request is accepted, or cleared by softwarefi : Frequency of count source (f1, f8, f32, fC32 ) Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: m = 00 16 to FE16; n = 0016 to FE16. /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Condition : Reload register high-order 8 bits = 0216 Reload register low-order 8 bits = 0216 External trigger (falling edge of TAiIN pin input signal) is selected 1 / fi X (m + 1) X (2 – 1) 8 1 / fi X (m + 1) X n 1 / fi X (m + 1)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Timer B Fig.FB-14 shows the block diagram of timer B. Fig.FB-15 and FB-16 show the timer B-related registers. Use the timer Bi mode register (i = 0 to 5) bits 0 and 1 to choose the desired mode. Timer B has three operation modes listed as follows:

• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer overflow.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or pulse width. Fig.FB-14 Block diagram of timer B Fig.FB-15 Timer B-related registers (1) Clock source selection (address 038016)
• Event counter
• Timer
• Pulse period/pulse width measurement Reload register (16) Low-order 8 bits High-order 8 bits Data bus low-order bits Data bus high-order bits f32 TBj overflow (j = i – 1. Note, however, j = 2 when i = 0, j = 5 when i = 3) Can be selected in only event counter mode Count start flag fC32 Polarity switching and edge pulseTBiIN (i = 0 to 5) Counter reset circuit Counter (16) TBi Address TBj Timer B0 039116 039016 Timer B2 Timer B1 039316 039216 Timer B0 Timer B2 039516 039416 Timer B1 Timer B3 035116 035016 Timer B5 Timer B4 035316 035216 Timer B3 Timer B5 035516 035416 Timer B4 Timer Bi mode register Symbol Address When reset TBiMR(i = 0 to 5) 039B16 to 039D16 00XX0000 2 035B16 to 035D16 00XX0000 2 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/pulse width measurement mode 1 1 : Inhibited b1 b0 TCK1 MR3 MR2 MR1 TMOD1 MR0 TMOD0 TCK0 Function varies with each operation mode Count source selection bits (Function varies with each operation mode) Operation mode selection bits (Note 1) (Note 2) Note 1: Timer B0, timer B3. Note 2: Timer B1, timer B2, timer B4, timer B5. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.FB-16 Timer B-related registers (2) Symbol Address When reset TABSR 0380 16 0016 Count start flag Bit nameBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Timer B2 count start flag Timer B1 count start flag Timer B0 count start flag Timer A4 count start flag Timer A3 count start flag Timer A2 count start flag Timer A1 count start flag Timer A0 count start flag0 : Stops counting 1 : Starts counting TB2S TB1S TB0S TA4S TA3S TA2S TA1S TA0S Function /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Symbol Address When reset CPSRF 0381 16 0XXXXXXX 2 Clock prescaler reset flag Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Clock prescaler reset flag0 : No effect 1 : Prescaler is reset (When read, the value is “0”) CPSR /LiteDiagLines/LiteDiagLines/LiteDiagLines Symbol Address When reset TB0 0391 16, 039016 Indeterminate TB1 0393 16, 039216 Indeterminate TB2 0395 16, 039416 Indeterminate TB3 0351 16, 035016 Indeterminate TB4 0353 16, 035216 Indeterminate TB5 0355 16, 035416 Indeterminate b7 b0 b7 b0 (b15) (b8) Timer Bi register (Note) W R

• Pulse period / pulse width measurement mode Measures a pulse period or width
• Timer mode 0000 16 to FFFF16 Counts the timer's period Function Values that can be set
• Event counter mode 0000 16 to FFFF16 Counts external pulses input or a timer overflow Note: Read and write data in 16-bit units. /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines Symbol Address When reset TBSR 0340 16 000XXXXX 2 Timer B3, 4, 5 count start flag Bit nameBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Timer B5 count start flag Timer B4 count start flag Timer B3 count start flag0 : Stops counting 1 : Starts counting TB5S TB4S TB3S Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Function /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Item Specification Count source f 1, f8, f32, fC32 Count operation •Counts down

• When the timer underflows, it reloads the reload register contents and then continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingThe timer underflows TBiIN pin function Programmable I/O port Read from timer Count value is read out by reading timer Bi register Write to timer •When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table.FB-6.) Fig.FB-17 shows the timer Bi mode register in timer mode. Table.FB-6 Timer specifications in timer mode Fig.FB-17 Timer Bi mode register in timer mode Note 1: Timer B0, timer B3. Note 2: Timer B1, timer B2, timer B4, timer B5. Timer Bi mode register Symbol Address When reset TBiMR(i=0 to 5) 039B 16 to 039D16 00XX0000 2 035B16 to 035D16 00XX0000 2 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Operation mode selection bits 0 0 : Timer mode b1 b0 TMOD1 TMOD0 MR0 Invalid in timer mode Can be “0” or “1” MR2 MR1 MR3 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 TCK1 TCK0 Count source selection bits Invalid in timer mode. In an attempt to write to this bit, write “0”. The value, if read in timer mode, turns out to be indeterminate. 0 (Fixed to “0” in timer mode ; i = 0, 3) Nothing is assigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. (Note 1) (Note 2) b7 b6 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Item Specification Count source •External signals input to TBiIN pin

• Effective edge of count source can be a rising edge, a falling edge, or both edges as selected by software Count operation •Counts down
• When the timer underflows, it reloads the reload register contents and then continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingThe timer underflows TBiIN pin function Count source input Read from timer Count value can be read out by reading timer Bi register Write to timer •When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) (2) Event counter mode In this mode, the timer counts an external signal or an internal timer's overflow. (See Table.FB-7) Fig.FB-18 shows the timer Bi mode register in event counter mode. Table.FB-7 Timer specifications in event counter mode Fig.FB-18 Timer Bi mode register in event counter mode Timer Bi mode register Symbol Address When reset TBiMR(i=0 to 5) 039B16 to 039D16 00XX0000 2 035B16 to 035D16 00XX0000 2 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Operation mode selection bits 0 1 : Event counter mode b1 b0 TMOD1 TMOD0 MR0 Count polarity selection bits (Note 1) MR2 MR1 MR3 Invalid in event counter mode. In an attempt to write to this bit, write “0”. The value, if read in event counter mode, turns out to be indeterminate. TCK1 TCK0 0 0 : Counts external signal's falling edges 0 1 : Counts external signal's rising edges 1 0 : Counts external signal's falling and rising edges 1 1 : Inhibited b3 b2 Nothing is assigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. Note 1: Valid only when input from the TBiIN pin is selected as the event clock. If timer's overflow is selected, this bit can be “0” or “1”. Note 2: Timer B0, timer B3. Note 3: Timer B1, timer B2, timer B4, timer B5. Note 4: Set the corresponding port direction register to “0”. Invalid in event counter mode. Can be “0” or “1”. Event clock selection 0 : Input from TBiIN pin (Note 4) 1 : TBj overflow (j = i – 1; however, j = 2 when i = 0, j = 5 when i = 3) 0 (Fixed to “0” in event counter mode; i = 0, 3) (Note 2) (Note 3) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Item Specification Count source f 1, f8, f32, fC32 Count operation •Up count

• At measurement pulse's effective edge, after the count value is transferred to reload register, it is cleared to "000016" and then continues counting. Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing•When measurement pulse's effective edge is input (Note 1)
• When an overflow occurs. (Simultaneously, the timer Bi overflow flag becomes “1”. The timer Bi overflow flag becomes “0” when the count start flag is “1” and a value is written to the timer Bi mode register.) TBiIN pin function Measurement pulse input Read from timer When timer Bi register is read, it indicates the reload register’s content (measurement result) (Note 2) Write to timer Cannot be written to (3) Pulse period/pulse width measurement mode In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table.FB-8) Fig.FB-19 shows the timer Bi mode register in pulse period/pulse width measurement mode. Fig.FB-20 shows the operation timing when measuring a pulse period. Fig.FB-21 shows the operation timing when measuring a pulse width. Table.FB-8 Timer specifications in pulse period/pulse width measurement mode Fig.FB-19 Timer Bi mode register in pulse period/pulse width measurement mode Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting. Note 2: After count starts, the value read out from the timer Bi register is indeterminate until the second effective edge is input . Timer Bi mode register Symbol Address When reset TBiMR(i=0 to 5) 039B16 to 039D16 00XX0000 2 035B16 to 035D16 00XX0000 2 Bit nameBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 Operation mode selection bits 1 0 : Pulse period / pulse width measurement mode b1 b0 TMOD1 TMOD0 MR0 Measurement mode selection bits MR1 0 1 0 0 : Pulse period measurement (Interval between measurement pulse's falling edge to falling edge) 0 1 : Pulse period measurement (Interval between measurement pulse's rising edge to rising edge) 1 0 : Pulse width measurement (Interval between measurement pulse's falling edge to rising edge, and between rising edge to falling edge) 1 1 : Inhibited Function b3 b2 /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines Note 1: The timer Bi overflow flag becomes “0” when the count start flag is “1” and a value is written to the timer Bi mode register. This flag cannot be set to “1” by software. Note 2: Timer B0, timer B3. Note 3: Timer B1, timer B2, timer B4, timer B5. MR2 MR3 TCK1 TCK0 Nothing is assigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. Count source selection bits Timer Bi overflow flag ( Note 1) 0 : Timer did not overflow 1 : Timer has overflowed 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 0 (Fixed to “0” in pulse period/pulse width measurement mode; i = 0, 3) (Note 2) (Note 3) /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.FB-21 Operation timing when measuring a pulse width Fig.FB-20 Operation timing when measuring a pulse period Count source Measurement pulse Count start flag Timer Bi interrupt request bit Timing at which counter reaches “0000 16” “H ” “1” Transfer (indeterminate value) “L” “0” “0” Timer Bi overflow flag“1” “0” Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. (Note 1) (Note 1) When measuring a pulse time interval from falling edge to falling edge (Note 2) Cleared to “0” when interrupt request is accepted, or cleared by software. Transfer (measured value) “1” Reload register counter transfer timing Measurement pulse “H ” Count source Count start flag Timer Bi interrupt request bit Timing at which counter reaches “0000 16” “1” “1” Transfer (measured value) Transfer (measured value) “L” “0” “0” Timer Bi overflow flag“1” “0” Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. (Note 1)(Note 1)(Note 1) Transfer (measured value)(Note 1) Cleared to “0” when interrupt request is accepted, or cleared by software. (Note 2) Transfer (indeterminate value) Reload register counter transfer timing

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Serial I/O Serial I/O is configured as five channels: UART0, UART1, UART2, S I/O3 and S I/O4. UART0 to 2 Each of UART0 - UART2 has an exclusive timer to generate a transfer clock, operating independently from each other. Fig.GA-1 shows the block diagram of UART0, UART1 and UART2. Fig.GA-2 and GA-3 show the block diagram of the transmit/receive unit. UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O mode (UART mode). The contents of the serial I/O mode selection bits (bits 0 to 2 at addresses 03A0 16, 03A816 and 037816) determine whether UARTi is used as a clock synchronous serial I/O or as a UART. Although a few functions are different, UART0, UART1 and UART2 have almost the same functions. UART0 through UART2 are almost equal in their functions with minor exceptions. UART2, in particular, is compliant with the SIM interface with some extra settings added in clock-asynchronous serial I/O mode (Note). It also has the bus collision detection function that generates an interrupt request if the TxD pin and the RxD pin are different in level. Table.GA-1 shows the comparison of functions of UART0 through UART2, and Fig.GA-4 to GA-8 show the registers related to UARTi. Note: SIM : Subscriber Identity Module Table.GA-1 Comparison of functions of UART0 through UART2 Note 1: Only in clock synchronous serial I/O mode. Note 2: Only in clock synchronous serial I/O mode and 8-bit UART mode. Note 3: Only in UART mode. Note 4: Can be used for SIM interface. UART0 UART1 UART2Function CLK polarity selection Continuous receive mode selection LSB first / MSB first selection ImpossibleTransfer clock output from multiple pins selection Impossible Impossible Impossible ImpossibleSerial data logic switch Impossible Sleep mode selection Impossible ImpossibleTxD, RxD I/O polarity switch Impossible Possible CMOS outputTxD, RxD port output format CMOS output N-channel open-drain output ImpossibleParity error signal output Impossible ImpossibleBus collision detection Impossible Possible Possible (Note 1) Separate CTS/RTS pins Possible (Note 1) Possible (Note 1) Possible (Note 3) Possible (Note 1) Possible (Note 1) Possible (Note 1) Possible (Note 1) Possible (Note 3) Possible Possible (Note 1) Possible (Note 2) Possible (Note 1) Possible (Note 4) Possible (Note 4)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.GA-1 Block diagram of UARTi (i = 0 to 2) n0 : Values set to UART0 bit rate generator (BRG0) n1 : Values set to UART1 bit rate generator (BRG1) n2 : Values set to UART2 bit rate generator (BRG2) RxD 2 Reception control circuit Transmission control circuit 1 / (n2+1) Bit rate generator (address 037916) Clock synchronous type (when internal clock is selected) UART reception Clock synchronous type UART transmission Clock synchronous type Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) Receive clock Transmit clock CLK 2 CTS 2 / RTS2 f32 Vcc RTS 2 CTS 2 TxD 2 (UART2) RxD polarity switching circuit TxD polarity switching circuit RxD 0 1 / (n0+1) Bit rate generator (address 03A116) Clock synchronous type (when internal clock is selected) UART reception Clock synchronous type UART transmission Clock synchronous type Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) Receive clock Transmit clock CLK 0 Clock source selection CTS 0 / RTS0 f32 Reception control circuit Transmission control circuit Internal External Vcc RTS 0 CTS 0 TxD 0 Transmit/ receive unit RxD 1 1 / (n1+1) Bit rate generator (address 03A916) Clock synchronous type (when internal clock is selected) UART reception Clock synchronous type UART transmission Clock synchronous type Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) Receive clock Transmit clock CLK 1 Clock source selection f32 Reception control circuit Transmission control circuit Internal External RTS 1 CTS 1 TxD 1 (UART1) (UART0) CLK polarity switching circuit CLK polarity switching circuit CTS/RTS disabled CTS/RTS separated Clock output pin select switch CTS 1 / RTS1 / CTS0 / CLKS1 CTS/RTS disabled CTS0 from UART1 CTS/RTS selected CTS/RTS disabled VCC CTS0 to UART0CTS 0 CTS/RTS disabled CTS/RTS separated CTS/RTS disabled CTS/RTS disabled CTS/RTS selected CLK polarity switching circuit Internal External Clock source selection Transmit/ receive unit Transmit/ receive unit

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.GA-2 Block diagram of UARTi (i = 0, 1) transmit/receive unit SP SP PAR 2SP 1SP UART UART (7 bits) UART (8 bits) UART (7 bits) UART (9 bits) Clock synchronous type Clock synchronous type TxDi UARTi transmit register PAR enabled PAR disabled D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 SP: Stop bit PAR: Parity bit UARTi transmit buffer register MSB/LSB conversion circuit UART (8 bits) UART (9 bits) Clock synchronous type UARTi receive buffer register UARTi receive register 2SP 1SP PAR enabled PAR disabled UART UART (7 bits) UART (9 bits) Clock synchronous type Clock synchronous type UART (7 bits) UART (8 bits) RxDi Clock synchronous type UART (8 bits) UART (9 bits) Address 03A616 Address 03A716 Address 03AE16 Address 03AF16 Address 03A216 Address 03A316 Address 03AA16 Address 03AB16 Data bus low-order bits MSB/LSB conversion circuit D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0D 80000000 SP SP PAR “0” Data bus high-order bits

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.GA-3 Block diagram of UART2 transmit/receive unit SP SP PAR 2SP 1SP UART UART (7 bits) UART (8 bits) UART(7 bits) UART (9 bits) Clock synchronous type Clock synchronous type Data bus low-order bits TxD2 UART2 transmit registerPAR disabled PAR enabled D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 UART2 transmit buffer register UART (8 bits) UART (9 bits) Clock synchronous type UART2 receive buffer register UART2 receive register 2SP 1SP UART (7 bits) UART (8 bits) UART(7 bits) UART (9 bits) Clock synchronous type Clock synchronous type RxD2 UART (8 bits) UART (9 bits) Address 037E Address 037F16 Address 037A16 Address 037B16 Data bus high-order bits D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0D 80000000 SP SP PAR “0” Reverse No reverse Error signal output circuit RxD data reverse circuit Error signal output enable Error signal output disable Reverse Not reverse Logic reverse circuit + MSB/LSB conversion circuit Logic reverse circuit + MSB/LSB conversion circuit PAR enabled PAR disabled UART Clock synchronous type TxD data reverse circuit SP: Stop bit PAR: Parity bit

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.GA-4 Serial I/O-related registers (1) UARTi bit rate generator b0 Symbol Address When reset U0BRG 03A1 16 Indeterminate U1BRG 03A9 16 Indeterminate U2BRG 0379 16 Indeterminate Function Assuming that set value = n, BRGi divides the count source by n + 1 0016 to FF16 Values that can be set W R /LiteDiagLines b7 b0 (b15) (b8) b7 b0 UARTi transmit buffer register Function Transmit data Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turn out to be indeterminate. Symbol Address When reset U0TB 03A3 16, 03A216 Indeterminate U1TB 03AB 16, 03AA16 Indeterminate U2TB 037B 16, 037A16 Indeterminate W R /LiteDiagLines /LiteDiagLines (b15) Symbol Address When reset U0RB 03A7 16, 03A616 Indeterminate U1RB 03AF 16, 03AE16 Indeterminate U2RB 037F 16, 037E16 Indeterminate b7 b0 (b8) b7 b0 UARTi receive buffer register Function (During UART mode) Function (During clock synchronous serial I/O mode) Bit nameBit symbol Note 1: Bits 15 through 12 are set to “0” when the serial I/O mode selection bits (bits 2 to 0 at addresses 03A016, 03A816 and 037816) are set to “0002” or the receive enable bit is set to “0”. (Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the lower byte of the UARTi receive buffer register (addresses 03A616, 03AE16 and 037E16) is read out. Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Receive data W R Receive data /LiteDiagLines 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found Invalid Invalid Invalid OER FER PER SUM Overrun error flag (Note 1) Framing error flag (Note 1) Parity error flag (Note 1) Error sum flag (Note 1) 0 : No overrun error 1 : Overrun error found 0 : No overrun error 1 : Overrun error found /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.GA-5 Serial I/O-related registers (2) UARTi transmit/receive mode register Symbol Address When reset UiMR(i=0,1) 03A0 16, 03A816 0016 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol W R Must be fixed to 001 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited b2 b1 b0 CKDIR SMD1 SMD0 Serial I/O mode selection bits SMD2 Internal/external clock selection bit STPS PRY PRYE SLEP Parity enable bit 0 : Internal clock 1 : External clock (Note 1) Stop bit length selection bit Odd/even parity selection bit Sleep selection bit 0 : One stop bit 1 : Two stop bits 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited b2 b1 b0 0 : Internal clock 1 : External clock (Note 1) Invalid Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity Invalid Invalid Must always be “0” Function (During UART mode) Function (During clock synchronous serial I/O mode) UART2 transmit/receive mode register Symbol Address When reset U2MR 0378 16 0016 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol W R Must be fixed to 001 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited b2 b1 b0 CKDIR SMD1 SMD0 Serial I/O mode selection bits SMD2 Internal/external clock selection bit STPS PRY PRYE IOPOL Parity enable bit 0 : Internal clock 1 : External clock (Note 1) Stop bit length selection bit Odd/even parity selection bitTxD, RxD I/O polarity switching bit 0 : One stop bit 1 : Two stop bits 0 : Parity disabled 1 : Parity enabled 0 : Not reverse 1 : Reverse Usually set to “0” 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited b2 b1 b0 Must always be "0" Invalid Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity Invalid Invalid 0 : Not reverse 1 : Reverse Usually set to “0” Function (During UART mode) Function (During clock synchronous serial I/O mode) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Note 1: Set the corresponding port direction register to "0". Note 1: Set the corresponding port direction register to "0".

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.GA-6 Serial I/O-related registers (3) UARTi transmit/receive control register 0 Symbol Address When reset UiC0(i=0,1) 03A4 16, 03AC16 0816 b7 b6 b5 b4 b3 b2 b1 b0 Function (During UART mode) W R Function (During clock synchronous serial I/O mode) TXEPT CLK1 CLK0 CRS CRD NCH CKPOL BRG count source selection bits Transmit register empty flag 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge CLK polarity selection bit CTS/RTS function selection bit CTS/RTS disable bit Data output selection bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited b1 b0 0 : LSB first 1 : MSB first 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (Pins function as programmable I/O port) 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open- drain output UFORM Transfer format selection bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited b1 b0 Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output Must always be “0” Bit nameBit symbol Must always be “0” Note 1: Set the corresponding port direction register to “0”. Note 2: The settings of the corresponding port register and port direction register are invalid. 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (Pins function as programmable I/O port) /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines UART2 transmit/receive control register 0 Symbol Address When reset U2C0 037C 16 0816 b7 b6 b5 b4 b3 b2 b1 b0 Function (During UART mode) W R Function (During clock synchronous serial I/O mode) TXEPT CLK1 CLK0 CRS CRD CKPOL BRG count source selection bits Transmit register empty flag 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge CLK polarity selection bit CTS/RTS function selection bit CTS/RTS disable bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited b1 b0 0 : LSB first 1 : MSB first 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (Pins function programmable I/O port) 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open-drain output UFORM Transfer format selection bit (Note 3) 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited b1 b0 Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output Must always be “0” Bit nameBit symbol Note 1: Set the corresponding port direction register to “0”. Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid. 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (Pins function programmable I/O port) Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”. 0 : LSB first 1 : MSB first /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.0 Fig.GA-7 Serial I/O-related registers (4) UARTi transmit/receive control register 1 Symbol Address When reset UiC1(i=0,1) 03A5 16,03AD 16 0216 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol W RFunction (During UART mode) Function (During clock synchronous serial I/O mode) TE TI RE RI Transmit enable bit Receive enable bit Receive complete flag Transmit buffer empty flag 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : No data present in receive buffer register 1 : Data present in receive buffer register Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. UART2 transmit/receive control register 1 Symbol Address When reset U2C1 037D 16 0216 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol W RFunction (During UART mode) Function (During clock synchronous serial I/O mode) TE TI RE RI Transmit enable bit Receive enable bit Receive complete flag Transmit buffer empty flag 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : No data present in receive buffer register 1 : Data present in receive buffer register U2IRS UART2 transmit interrupt factor selection bit 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) U2RRM UART2 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Invalid Data logic selection bit 0 : Not reverse 1 : Reverse 0 : Not reverse 1 : Reverse U2LCH U2ERE Error signal output enable bit Must be fixed to “0” 0 : Output disabled 1 : Output enabled /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 100 Rev.1.0 Fig.GA-8 Serial I/O-related registers (5) Note: When using multiple pins to output the transfer clock, the following requirements must be met:

• UART1 internal/external clock selection bit (bit 3 at address 03A816) = “0”. UART transmit/receive control register 2 Symbol Address When reset UCON 03B0 16 X00000002 b7 b6 b5 b4 b3 b2 b1 b0 Bit name Bit symbol W RFunction (During UART mode) Function (During clock synchronous serial I/O mode) CLKMD0 CLKMD1 RCSP UART0 transmit interrupt factor selection bit UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled UART1 continuous receive mode enable bit CLK/CLKS selection bit 0 UART1 transmit interrupt factor selection bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Normal mode (CLK output is CLK1 only) 1 : Transfer clock output from multiple pins function selected 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) Must always be “0” U0IRS U1IRS U0RRM U1RRM 0 : CTS/RTS shared pin 1 : CTS/RTS separated 0 : CTS/RTS shared pin 1 : CTS/RTS separated Separate CTS/RTS bit Invalid Invalid Invalid CLK/CLKS selection bit 1 (Note) Valid when bit 5 = “1” 0 : Clock output to CLK1 1 : Clock output to CLKS1 /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines UART2 special mode register Symbol Address When reset U2SMR 0377 16 0016 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol W RFunction (During UART mode) Function (During clock synchronous serial I/O mode) ABSCS ACSE SSS Bus collision detect sampling clock selection bit 0 : Ordinary 1 : Falling edge of RxD2 Transmit start condition selection bit 0 : Rising edge of transfer clock 1 : Underflow signal of timer A0 Auto clear function selection bit of transmit enable bit /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 0 : No auto clear function 1 : Auto clear at occurrence of bus collision Must always be “0” Must always be “0” Must always be “0” Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”. Reserved bits Must always be “0” 00000

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 101 Rev.1.0 (1) Clock synchronous serial I/O mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables.GA-2 and GA-3 list the specifications of the clock synchronous serial I/O mode. Fig.GA-9 shows the UARTi transmit/ receive mode register. Table.GA-2 Specifications of clock synchronous serial I/O mode (1) Item Specification Transfer data format • Transfer data length: 8 bits Transfer clock • When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “0”) : fi/ 2(n+1) (Note 1) fi = f1, f8, f32

• When external clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “1”) : Input from CLKi pin Transmission/reception control
• Selecting from CTS function/RTS function/Disable CTS, RTS function Transmission start condition• To start transmission, the following requirements must be met: _ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1” _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0” _ When CTS function selected, CTS input level = “L”
• Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”: CLKi input level = “H ” _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”: CLKi input level = “L” Reception start condition• To start reception, the following requirements must be met: _ Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1” _ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1” _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”
• Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”: CLKi input level = “H ” _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”: CLKi input level = “L”
• When transmitting _ Transmit interrupt factor selection bits (bits 0, 1 at address 03B016, bit 4 at address 037D16) = “0”: At the completion of data transmission from UARTi transfer buffer register to UARTi transmit register _ Transmit interrupt factor selection bits (bits 0, 1 at address 03B016, bit 4 at address 037D16) = “1”: At the completion of data transmission from UARTi transfer register is completed
• When receiving _ At the completion of data transferring from UARTi receive register to UARTi receive buffer register Error detection • Overrun error (Note 2) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out Interrupt request generation timing Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator. Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit is not set to “1”. Clock synchronous serial I/O mode

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 102 Rev.1.0 Item Specification Function selection • CLK polarity selection Whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected

• LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection (UART1) (Note) UART1 transfer clock can be chosen by software to be output from one of the two pins set
• Separate CTS/RTS pins (UART0) (Note) Each of UART0 CTS and RTS pins can be assigned to separate pins
• Switching serial data logic (UART2) Whether to reverse data in writing to the transmission buffer register or reading the reception buffer register can be selected.
• TxD, RxD I/O polarity switching (UART2) This function is reversing TxD port output and RxD port input. All I/O data level is reversed. Table.GA-3 Specifications of clock synchronous serial I/O mode (2) Note: The transfer clock output from multiple pins and the separate CTS/RTS pins functions cannot be selected simultaneously. Clock synchronous serial I/O mode

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 103 Rev.1.0 Fig.GA-9 UARTi transmit/receive mode register in clock synchronous serial I/O mode Clock synchronous serial I/O mode Symbol Address When reset UiMR(i=0,1) 03A0 16, 03A816 0016 CKDIR UARTi transmit/receive mode registers Internal/external clock selection bit STPS PRY PRYE SLEP 0 : Internal clock 1 : External clock (Note 1) Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 0 (Must always be “0” in clock synchronous serial I/O mode) 010 SMD0 SMD1 SMD2 Serial I/O mode selection bits0 0 1 : Clock synchronous serial I/O mode b2 b1 b0 Invalid in clock synchronous serial I/O mode Symbol Address When reset U2MR 0378 16 0016 CKDIR UART2 transmit/receive mode register Internal/external clock selection bit STPS PRY PRYE IOPOL 0 : Internal clock 1 : External clock (Note 2) Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 010 SMD0 SMD1 SMD2 Serial I/O mode selection bit0 0 1 : Clock synchronous serial I/O mode b2 b1 b0 Invalid in clock synchronous serial I/O mode TxD, RxD I/O polarity reverse bit (Note 1) 0 : No reverse 1 : Reverse Note 1: Usually sent to "0". Note 2: The corresponding port direction register should be "0". /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Note 1: The corresponding port direction register should be "0".

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 104 Rev.1.0 Table.GA-4 lists the functions of the input/output pins during clock synchronous serial I/O mode. This table shows the pin functions that the transfer clock output from multiple pins and the separation of CTS/RTS pins are not selected. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H ”. (If the N-channel open-drain is selected, this pin is in floating state.) Table.GA-4 Input/output pin functions in clock synchronous serial I/O mode (The function that the transfer clock output from multiple pin is not selected. The function that separates CTS/RTS pins is not selected.) Clock synchronous serial I/O mode Pin name Function Method of selection TxDi (P63,P67,P70) Serial data output Serial data input Transfer clock output Transfer clock input Programmable I/O port (Outputs dummy data when performing reception only) RxDi (P62,P66,P71) CLKi (P61,P65,P72) Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “0” Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “1” Port P61, P65 and P72 direction register (bits 1 and 5 at address 03EE16, bit 2 at address 03EF16) = “0” Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16, bit 1 at address 03EF16)= “0” (Can be used as an input port when performing transmission only) CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) =“0” CTS/RTS function selection bit (bit 2 at address 03A416, 03AC16, 037C16) = “0” The corresponding port direction bit = “0” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “0” CTS/RTS function selection bit (bit 2 at address 03A416, 03AC16, 037C16) = “1” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “1” CTS input RTS output CTSi/RTSi (P60,P64,P73)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 105 Rev.1.0 Fig.GA-10 Typical transmit/receive timings in clock synchronous serial I/O mode

• Example of transmit timing (when internal clock is selected)
• Example of receive timing (when external clock is selected) Clock synchronous serial I/O mode D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Tc TCLK Stopped because transfer enable bit = “0” Data is set in UARTi transmit buffer register Tc = TCLK = 2(n + 1) / fi fi: frequency of BRGi count source (f1, f8, f32) n: value set to BRGi Transfer clock Transmit enable bit (TE) Transmit buffer empty flag (Tl) CLKi TxDi Transmit register empty flag (TXEPT) “H ” “L” “0” “1” “0” “1” “0” “1” CTSi The above timing applies to the following settings:
• Internal clock is selected.
• CTS function is selected.
• CLK polarity selection bit = “0”.
• Transmit interrupt factor selection bit = “0”. Transmit interrupt request bit (IR)“0” “1” Stopped because CTS = “H ” 1 / fEXT Dummy data is set in UARTi transmit buffer register Transmit enable bit (TE) Transmit buffer empty flag (Tl) CLKi RxDi Receive complete flag (Rl) RTSi “H ” “L” “0” “1” “0” “1” “0” “1” Receive enable bit (RE) “0” “1” Receive data is taken in Transferred from UARTi transmit buffer register to UARTi transmit register Read out from UARTi receive buffer register The above timing applies to the following settings:
• External clock is selected.
• RTS function is selected.
• CLK polarity selection bit = “0”. fEXT : frequency of external clock Transferred from UARTi receive register to UARTi receive buffer register Receive interrupt request bit (IR)“0” “1” D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 Shown in ( ) are bit symbols. Transferred from UARTi transmit buffer register to UARTi transmit register The following conditions should be matched when the input level of CLKi pin is "H" before the data reception.
• Transmit enable bit “1”
• Receive enable bit “1”
• Dummy data write to UARTi transmit buffer register Shown in ( ) are bit symbols. Cleared to “0” when interrupt request is accepted, or cleared by software Cleared to “0” when interrupt request is accepted, or cleared by software

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 106 Rev.1.0 (a) Polarity selection function As shown in Fig.GA-11, the CLK polarity selection bit (bit 6 at addresses 03A416, 03AC16, 037C16) allows to select the polarity of the transfer clock. Fig.GA-11 Polarity of transfer clock (b) LSB first/MSB first selection function As shown in Fig.GA-12, when the transfer format selection bit (bit 7 at addresses 03A416, 03AC16, 037C16) = “0”, the transfer format is “LSB first”; when the bit = “1”, the transfer format is “MSB first”. Fig.GA-12 Transfer format Clock synchronous serial I/O mode

• When CLK polarity select bit = “1” Note 2: The CLK pin level is "L" when there is no transferring.TXD i R XD i CLK i
• When CLK polarity selection bit = “0” Note 1: The CLK pin level is "H" when there is no transferring. D 1 D 2 D 3 D 4 D 5 D 6 D 7D 0 TXD i R XD i CLK i D 1 D 2 D 3 D 4 D 5 D 6 D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7D 0 LSB first
• When transfer format selection bit = “0” TXD i R XD i CLK i
• When transfer format selection bit = “1” D 6 D 5 D 4 D 3 D 2 D 1 D 0D 7TXD i R XD i CLK i MSB first Note: This applies when the CLK polarity selection bit = “0”. D 1 D 2 D 3 D 4 D 5 D 6 D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7D 0 D 6 D 5 D 4 D 3 D 2 D 1 D 0D 7

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 107 Rev.1.0 (c) Transfer clock output from multiple pins function (UART1) This function allows to set two transfer clock output pins and chooses one to output a clock by the setting of CLK and CLKS selection bits (bits 4 and 5 at address 03B0 16). (See Fig.GA-13) The function is valid only when the UART1 internal clock is selected. Note that when this function is selected, UART1 CTS/RTS function cannot be used. Fig.GA-13 The sample of transfer clock output from the multiple pins function (d) Continuous receive mode If the continuous receive mode enable bits (bits 2 and 3 at address 03B016, bit 5 at address 037D16) are set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. (e) Separate CTS/RTS pins function (UART0) This function works the same way as in the clock asynchronous serial I/O (UART) mode. The method of setting and the input/output pin functions are both the same, so refer to the selection function in the next section, “(2) Clock asynchronous serial I/O (UART) mode.” Note that this function is invalid if the transfer clock output from the multiple pins function is selected. (f) Serial data logic switch function (UART2) When the data logic selection bit (bit6 at address 037D16) = “1”, the data writing to transmit buffer register or reading from receive buffer register, are reversed. Fig.GA-14 shows the example of serial data logic switch timing. Fig.GA-14 Serial data logic switch timing Clock synchronous serial I/O mode Microcomputer TXD 1 (P67) CLKS 1 (P64) CLK 1 (P65) IN CLK IN CLK D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Transfer clock TxD 2 (no reverse) TxD 2 (reverse) “H ” “L” “H ” “L” “H ” “L”

• When LSB first

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 108 Rev.1.0 Item Specification Transfer data format • Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected

• Start bit: 1 bit
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected Transfer clock • When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “0”) : fi/16(n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at addresses 03A016, 03A816 =“1”) : fEXT /16(n+1)(Note 1) (Note 2)
• Do not select the external clock in UART2. Transmission/reception control
• Selecting from CTS function/ RTS function/ Disable CTS, RTS function Transmission start condition• To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1” - Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0” - When CTS function is selected CTS input level = “L” Reception start condition• To start reception, the following requirements must be met: - Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1” - Start bit detection Interrupt request • When transmitting generation timing - Transmit interrupt factor selection bits (bits 0,1 at address 03B016, bit4 at address 037D16) = “0”: At the completion of data transferring from UARTi transfer buffer register to UARTi transmit register - Transmit interrupt factor selection bits (bits 0, 1 at address 03B016, bit4 at address 037D16) = “1”: At the completion of data transmission from UARTi transfer register
• When receiving - At the completion of data transferring from UARTi receive register to UARTi receive buffer register Error detection • Overrun error (Note 3) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out
• Framing error This error occurs when the number set for stop bits is not detected
• Parity error This error occurs in the case that parity is enabled and the number of "1" in parity bit and character bits does not match the number of "1" in parity odd/ even setting.
• Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered (2) Clock asynchronous serial I/O (UART) mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Tables.GA-5 and GA-6 list the specifications of the UART mode. Fig.GA-15 shows the UARTi transmit/receive mode register. Table.GA-5 Specifications of UART Mode (1) Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate register. Note 2: fEXT is input from the CLKi pin. Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Also note that the UARTi receive interrupt request bit is not set to “1”. Clock asynchronous serial I/O (UART) mode

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 109 Rev.1.0 Table.GA-6 Specifications of UART Mode (2) Item Specification Function selection

• Separate CTS/RTS pins (UART0) Each of UART0 CTS and RTS pins can be assigned to separate pins
• Sleep mode selection (UART0, UART1) This mode is used to transfer data to and from one of multiple slave micro- computers
• Serial data logic switch (UART2) This function is reversing logic value of transferring data. Start bit,and stop bit are not reversed. XD, RXD I/O polarity switch (UART2) This function is reversing TXD port output and RXD port input. All I/O data level are reversed. Clock asynchronous serial I/O (UART) mode

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 110 Rev.1.0 Fig.GA-15 UARTi transmit/receive mode register in UART mode Clock asynchronous serial I/O (UART) mode Symbol Address When reset UiMR(i=0,1) 03A0 16, 03A816 0016 CKDIR UARTi transmit / receive mode registers Internal / external clock selection bit STPS PRY PRYE SLEP 0 : Internal clock 1 : External clock (Note 1) Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 SMD0 SMD1 SMD2 Serial I/O mode selection bits b2 b1 b0 0 : One stop bit 1 : Two stop bits 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity Stop bit length select bit Odd / even parity select bit Parity enable bit Sleep selection bit Symbol Address When reset U2MR 0378 16 0016 CKDIR UART2 transmit / receive mode register Internal / external clock selection bit STPS PRY PRYE IOPOL Must always be "0" Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 SMD0 SMD1 SMD2 Serial I/O mode selection bits b2 b1 b0 0 : One stop bit 1 : Two stop bits 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity Stop bit length select bit Odd / even parity selection bit Parity enable bit TxD, RxD I/O polarity switching bit (Note) /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Note: Usually set to “0”. Note 1: The corresponding port direction register should be "0".

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 111 Rev.1.0 Table.GA-7 lists the functions of the input/output pins during UART mode. This table shows the pin functions when the separate CTS/RTS pins function is not selected. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H ”. (If the N-channel open-drain is selected, this pin is in floating state.) Table.GA-7 Input/output pin functions in UART mode (when CTS/RTS separate function is not selected) Clock asynchronous serial I/O (UART) mode Pin name Function Method of selection Serial data output Serial data input Programmable I/O port Transfer clock input Programmable I/O port Internal/external clock selection bit (bit 3 at address 03A016, 03A816, 037816) = “0” Internal/external clock selection bit (bit 3 at address 03A016, 03A816) = “1” Corresponding port direction register bit = “0” (Don't select the external clock for UART2) Corresponding port direction register bit = "0".(Can be used as an input port when performing transmission only) CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) =“0” CTS/RTS function selection bit (bit 2 at address 03A416, 03AC16, 037C16) = “0” Corresponding port direction register bit = “0” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “0” CTS/RTS function selection bit (bit 2 at address 03A416, 03AC16, 037C16) = “1” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “1” CTS input RTS output TxDi (P63,P67,P70) RxDi (P6 2,P66,P71) CLKi (P6 1,P65,P72) CTSi/RTSi (P6 0,P64,P73)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 112 Rev.1.0

• Example of transmit timing when transfer data are 8 bits long (parity enabled, one stop bit)
• Example of transmit timing when transfer data are 9 bits long (parity disabled, two stop bits) Fig.GA-16 Typical transmit timings in UART mode Clock asynchronous serial I/O (UART) mode Transmit enable bit(TE) Transmit buffer empty flag(TI) Transmit register empty flag (TXEPT) Start bit Parity bit TxDi CTSi The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• CTS function is selected.
• Transmit interrupt factor selection bit = “1”. “1” “0” “1” “L” “H ” Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Transmit interrupt request bit (IR) Cleared to “0” when interrupt request is accepted, or cleared by software Transmit enable bit(TE) Transmit buffer empty flag(TI) TxDi Transmit register empty flag (TXEPT) “0” “1” “0” “1” The above timing applies to the following settings :
• Parity is disabled.
• Two stop bits.
• CTS function is disabled.
• Transmit interrupt factor selection bit = “0”. Transfer clock Tc Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Transmit interrupt request bit (IR) Shown in ( ) are bit symbols. Shown in ( ) are bit symbols. Tc Transfer clock D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7SP ST P SP D 0 D 1ST Stopped because transmit enable bit = “0”Stop bit Transferred from UARTi transmit buffer register to UARTi transmit register Start bit The transfer clock stops momentarily as CTS is “H ” when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTS changes to “L”. Data is set in UARTi transmit buffer register D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST SPD 8 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST D 8 D 0 D 1STSP SP Transferred from UARTi transmit buffer register to UARTi transmit register Stop bit Stop bit Data is set in UARTi transmit buffer register.“0” SP Cleared to “0” when interrupt request is accepted, or cleared by software “0” “1” “0” “1” “0” “1” “0” “1”

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 113 Rev.1.0 Fig.GA-17 Typical transmit timings in UART mode (UART2)

• Example of transmit timing when transfer data are 8 bits long (parity enabled, one stop bit) Transmit enable bit(TE) Transmit buffer empty flag(TI) Transmit register empty flag (TXEPT) TxD2 The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt factor selection bit = “1”. “1” “0” “1” Tc = 16 (n + 1) / fi fi : frequency of BRGi count source (f1, f8, f32) n : value set to BRGi Transmit interrupt request bit (IR) Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. Tc Transfer clock “0” Start bit Parity bit D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SP Stop bit Parity bit D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SP Transferred from UART2 transmit buffer register to UART2 transmit register Data is set in USAR2 transmit buffer register Note1 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SPD 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SP Note1. According to the above timing, the transmission is started by the timing of BRG overflow after writing to the transmit buffer. “0” “1” “0” “1”

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 114 Rev.1.0

• Example of receive timing when transfer data are 8 bits long (parity disabled, one stop bit) Fig.GA-18 Typical receive timing in UART mode (a) Separate CTS/RTS pins function (UART0) Setting the CTS/RTS separate bit (bit 6 of address 03B016) to "1" separates the RTS and CTS signals to different input/out pins.(Fig GA-19). Choosing one from CTS or RTS, by using of the CTS/RTS function selection bit (bit 2 of address 03A416). This function is effective in UART0 only. If the function is used, the user cannot use the CTS/RTS function of UART1. Set "0" both to the CTS/RTS function selection bit (bit 2 of address 03AC16) and to the CTS/RTS disable bit (bit 4 of address 03AC16). (b) Sleep mode (UART0, UART1) This mode is used to transfer data between specific microcomputers among multiple microcomputers con- nected with UARTi. The sleep mode is selected when the sleep selection bit (bit 7 at addresses 03A0 16, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”. Clock asynchronous serial I/O (UART) mode D 0Start bit Sampled “L” Receive data taken in BRGi count source Receive enable bit RxDi Transfer clock Receive complete flag RTSi Stop bit “1” “0” “0” “1” “H ” “L” The above timing applies to the following settings :
• Parity is disabled.
• One stop bit.
• RTS function is selected. Receive interrupt request bit “0” “1” Transferred from UARTi receive register to UARTi receive buffer register Reception triggered when transfer clock is generated by falling edge of start bit D 7D 1 Cleared to “0” when interrupt request is accepted, or cleared by software Microcomputer TXD 0 (P63) R XD 0 (P62) IN OUT CTS RTSCTS0 (P64) RTS0 (P60) IC Note : The user cannot use CTS and RTS at the same time. Fig.GA-19 The separate CTS/RTS pins function usage

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 115 Rev.1.0 (c) Function for switching serial data logic (UART2) When the data logic selection bit (bit 6 of address 037D16) is assigned 1, data is inverted in writing to the transmission buffer register or reading the reception buffer register. Fig.GA-20 shows the example of timing for switching serial data logic. Fig.GA-20 Timing for switching serial data logic (d) TxD, RxD I/O polarity switching function (UART2) This function is to reverse TXD pin output and RXD pin input. The level of any data to be input or output (including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not to reverse) for usual use. (e) Bus collision detection function (UART2) This function is to sample the output level of the TXD pin and the input level of the RXD pin at the rising edge of the transfer clock; if their values are different, then an interrupt request occurs. Fig.GA-21 shows the example of detection timing of a bus collision (in UART mode). Fig.GA-21 Detection timing of a bus collision (in UART mode) Clock asynchronous serial I/O (UART) mode ST : Start bit P : Even parity SP : Stop bit Transfer clock TxD 2 (no reverse) TxD 2 (reverse) “H ” “L” “H ” “L” “H ” “L”

• When LSB first, parity enabled, one stop bit ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST : Start bit SP : Stop bit ST ST SP SP Transfer clock TxD 2 RxD 2 Bus collision detection interrupt request signal “H ” “L” “H ” “L” “H ” “L” “1” “0” Bus collision detection interrupt request bit “1” “0”

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 116 Rev.1.0 Item Specification Transfer data format • Transfer data 8-bit UART mode (bit 2 through bit 0 of address 037816 = “1012”)

• One stop bit (bit 4 of address 037816 = “0”)
• With the direct format chosen Set parity to “even” (bit 5 and bit 6 of address 037816 = “1” and “1” respectively) Set data logic to “direct” (bit 6 of address 037D16 = “0”). Set transfer format to LSB (bit 7 of address 037C16 = “0”).
• With the inverse format chosen Set parity to “odd” (bit 5 and bit 6 of address 037816 = “0” and “1” respectively) Set data logic to “inverse” (bit 6 of address 037D16 = “1”) Set transfer format to MSB (bit 7 of address 037C16 = “1”) Transfer clock • With the internal clock chosen (bit 3 of address 037816 = “0”) : fi / 16 (n + 1) (Note 1) : fi=f1, f8, f32
• Don't chose external clock. Transmission / reception control
• Disable the CTS and RTS function (bit 4 of address 037C16 = “1”) Other settings • The sleep mode selection function is not available for UART2
• Set transmission interrupt factor to “transmission completed” (bit 4 of address 037D16 = “1”) Transmission start condition• To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 of address 037D16) = “1” - Transmit buffer empty flag (bit 1 of address 037D16) = “0” R eception start condition• To start reception, the following requirements must be met: - Reception enable bit (bit 2 of address 037D16) = “1” - Detection of a start bit
• When transmitting When data transmission from the UART2 transfer register is completed (bit 4 of address 037D16 = “1”)
• When receiving When data transfer from the UART2 receive register to the UART2 receive buffer register is completed Error detection • Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2)
• Framing error (see the specifications of clock-asynchronous serial I/O)
• Parity error (see the specifications of clock-asynchronous serial I/O) - On the reception side, an “L” level is output from the TXD 2 pin by use of the parity error signal output function (bit 7 of address 037D16 = “1”) when a parity error is detected - On the transmission side, a parity error is detected by the level of input to the RXD 2 pin when a transmission interrupt occurs
• The error sum flag (see the specifications of clock-asynchronous serial I/O) (3) Clock-asynchronous serial I/O mode (compliant with the SIM interface) The SIM interface is used for connecting the microcomputer with a memory card IC or the like; adding some extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table.GA-8 shows the specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface). Interrupt request generation timing Note 1: ‘n’ denotes the value 00 16 to FF16 that is set to the UARTi bit rate generator. Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Also Note that the UARTi receive interrupt request bit is not set to “1”. Table.GA-8 Specifications of clock-asynchronous serial I/O mode (compliant with SIM I/F) Clock asynchronous serial I/O (UART) mode

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 117 Rev.1.0 Fig.GA-22 Typical transmit/receive timing in UART mode (compliant with the SIM interface) Clock asynchronous serial I/O (UART) mode Parity bit Stop bit SP SP Transmit enable bit(TE) Transmit buffer empty flag(TI) Transmit register empty flag (TXEPT) TxD2 The above timing applies to the following settings :

• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”. “1” “0” “1” “0” “1” Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2 Transmit interrupt request bit (IR) “0” “1” Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. Tc Transfer clock “0” Start bit Parity bit D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P Stop bit D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P Transferred from UART2 transmit buffer register to UART2 transmit register Data is set in UART2 transmit buffer register Note1 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SPD 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SP Note 1. According to the above timing, the transmission is started by the timing of BRG overflow after writing to the transmit buffer. RxD2 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST PD 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SPD 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SPSignal conductor level (Note1) A "L" level returns from TxD2 due to the occurrence of a parity error The level is detected by the interrupt routine The level is detected by the interrupt routine Receive enable bit(RE) Receive complete flag (RI) RxD2 The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”. “1” Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2 Receive interrupt request bit (IR) Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. Tc Transfer clock “0” Start bit D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SPD 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SP D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SPD 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SP Note 2. The waveforms are the same because TxD2 and RxD2 are connected. TxD2 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SPD 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SP D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SPD 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SPSignal conductor level (Note 2) A "L" level returns from TxD2 due to the occurrence of a parity error Read to receive buffer Read to receive buffer “0” “1” “0” “1”

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 118 Rev.1.0 (a) Function for outputting a parity error signal With the error signal output enable bit (bit 7 of address 037D16) assigned “1”, an “L” level from the TxD2 pin will be output when a parity error is detected. Link with this function, the timing to generate a transmission completion interrupt varies according to the timing of a parity error signal detection. Fig.GA-23 shows the timing of the parity error signal output. Fig.GA-23 Timing of the parity error signal output (b) Direct format/inverse format Connecting the SIM card allows you to switch between direct format and inverse format. If you choose the direct format, data are output from TxD 2 beginning with D0. If you choose the inverse format, data are inverted and output from TxD2 beginning with D7. Fig.GA-24 shows the SIM interface format. Fig.GA-24 SIM interface format Clock asynchronous serial I/O (UART) mode D0 D1 D2 D3 D4 D5 D6 D7 P SP ST Hi-Z Transfer clock RxD 2 TxD 2 Receive complete flag “H ” “L” “H ” “L” “H ” “L” “1”

• LSB first “0” ST : Start bit P : Even parity SP : Stop bit P : Even parity Transfer clcck TxD 2 (direct) TxD 2 (inverse) D4 P D7 D6 D5 D3 D2 D1 D0 D3 PD0 D1 D2 D4 D5 D6 D7

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 119 Rev.1.0 Fig.GA-25 shows the example of connecting the SIM interface. Connect TXD 2 and RXD 2 and apply pull-up. Fig.GA-25 Connecting the SIM interface Clock asynchronous serial I/O (UART) mode Microcomputer SIM card TxD 2 RxD 2

UART2 Special Mode Register Mitsubishi microcomputers M16C / 6K7 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 120 Rev.1.0 UART2 Special Mode Register The UART2 special mode register (address 037716) is used to control UART2 in various ways. Fig.GA-26 shows the UART2 special mode register. Fig.GA-26 UART2 special mode register Some other functions added are explained here. Fig.GA-27 shows their workings. Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock selection bit. The bus collision detect interrupt occurs when the RxD2 level and TxD2 level do not match, but the nonconfor- mity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to “0”. If this bit is set to “1”, the nonconformity is detected at the timing of the overflow of timer A0 rather than at the rising edge of the transfer clock. Bit 5 of the UART2 special mode register is used as the auto clear function selection bit of transmit enable bit. Setting this bit to “1” automatically resets the transmit enable bit to “0” when “1” is set in the bus collision detect interrupt request bit (nonconformity). Bit 6 of the UART2 special mode register is used as the transmit start condition selection bit. Setting this bit to “1” starts the TxD transmission in synchronization with the falling edge of the RxD pin. UART2 special mode register Symbol Address When reset U2SMR 0377 16 0016 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol W RFunction (During UART mode) Function (During clock synchronous serial I/O mode) Reserved bits Must always be “0” ABSCS ACSE SSS Bus collision detect sampling clock selection bit 0 : Ordinary 1 : Falling edge of RxD2 Transmit start condition selection bit 0 : Rising edge of transfer clock 1 : Underflow signal of timer A0 Auto clear function selection bit of transmit enable bit /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 0 : No auto clear function 1 : Auto clear at occurrence of bus collision Must always be “0” Must always be “0” Must always be “0” 00 0 00 Reserved bit Must always be “0”

UART2 Special Mode Register Mitsubishi microcomputers M16C / 6K7 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 121 Rev.1.0 Fig.GA-27 Some other functions added 1. Bus collision detect sampling clock select bit (Bit 4 of the UART2 special mode register) 0: Rising edges of the transfer clock CLK Timer A0 1: Timer A0 overflow 2. Auto clear function selection bit of transmit enable bit (Bit 5 of the UART2 special mode register) CLK TxD/RxD Bus collision detect interrupt request bit Transmit enable bit 3. Transmit start condition selection bit (Bit 6 of the UART2 special mode register) CLK TxD Enabling transmission CLK TxD RxD With "1: falling edge of RxD2" selected 0: In normal state TxD/RxD

UART2 Special Mode Register Mitsubishi microcomputers M16C / 6K7 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 122 Rev.1.0 S I/O3, 4 S I/O 3 and S I/O 4 are exclusive clock-synchronous serial I/Os. Fig.GA-28 shows the S I/O 3, 4 block diagram, and Fig.GA-29 shows the S I/O 3, 4 control register. Table.GA-9 shows the specifications of S I/O 3, 4. Fig.GA-28 S I/O3, 4 block diagram S I/O3, 4 S I/Oi transmission/reception register (8) S I/O counter i (3) Synchronous circuit f32 Data bus S I/Oi interrupt request SMi5 LSB MSB SMi2 SMi3 SMi3 SMi6 SMi1 SMi0 P90/CLK 3 (P95/CLK 4) P92/SOUT3 (P96/SOUT4 ) P91/SIN3 (P97/SIN4) Transfer rate register (8) SMi6 Note: i = 3, 4. ni = A value set in the S I/O transfer rate register i (0363 16, 036716). 1/(ni+1)1/2

UART2 Special Mode Register Mitsubishi microcomputers M16C / 6K7 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 123 Rev.1.0 Fig.GA-29 S I/O3, 4 control registers S I/Oi control register (i = 3, 4) (Note 1) Symbol Address When reset SiC 0362 16, 036616 4016 b7 b6 b5 b4 b3 b2 b1 b0 WRDescription SMi5 SMi1 SMi0 SMi3 SMi6 SMi7 Transfer direction selection bit lect bit„û S I/Oi port selection bit (Note 2) S OUT i initial value set bit 0 0 : Selecting f1 0 1 : Selecting f8 1 0 : Selecting f32 1 1 : Not to be used b1 b0 0 : External clock 1 : Internal clock Effective when SMi3 = 0 0 : L output 1 : H output 0 : Input-output port 1 : S OUT i output, CLK function Bit nameBit symbol Synchronous clock selection bit (Note 2) 0 : LSB first 1 : MSB first SMi2 SOUT i output disable bit 0 : SOUT i output 1 : SOUTi output disable (high impedance) Note 1: Set "1" in bit 2 of the protection register (000A16) in advance to write to the S I/Oi control register (i = 3, 4). Note 2: When SI/Oi port selection bit (i= 3, 4) is set to "0" as for I/O port, set the synchronous clock selection bit to "1". Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”. SI/Oi bit rate generator b7 b0 Symbol Address When reset S3BRG 0363 16 Indeterminate S4BRG 0367 16 Indeterminate Indeterminate Assuming that set value = n, BRGi divides the count source by n + 1 0016 to FF16 Values that can be setW R SI/Oi transmission/reception register b7 b0 Symbol Address When reset S3TRR 0360 16 Indeterminate S4TRR 0364 16 Indeterminate Indeterminate Transmission/reception starts by writing data to this register. After transmission/reception finishes, reception data is input. W R Internal synchronous clock selection bits

UART2 Special Mode Register Mitsubishi microcomputers M16C / 6K7 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 124 Rev.1.0 Table.GA-9 Specifications of S I/O3, 4 Note 1: n is a value from 0016 through FF16 set in the S I/Oi transfer rate register (i = 3, 4). Note 2: With the external clock selected:

• Please write to the SI/Oi transmission/reception register(036016, 036416) under the status that the CLKi pin is input to "H" level. Also please write to the bit 7(SOUT i default value setting bit) under the status that the CLKi pin is input to "H" level.
• The S I/Oi circuit keeps on with the shift operation as long as the synchronous clock is entered in it, so stop the synchronous clock at the instant when it counts to eight. The internal clock, if selected, automatically stops. Note 3: If the internal clock is used for the synchronous clock, the transfer clock signal stops at the “H ” state. Item Transfer data format Transfer clock Conditions for transmission/ reception start Interrupt request generation timing Select function Precaution Specifications
• Transfer data length: 8 bits
• With the internal clock selected (bit 6 of 036216, 036616 = “1”): f1/2(ni+1), f8/2(ni+1), f32/2(ni+1) (Note 1)
• With the external clock selected (bit 6 of 036216, 036616 = 0):Input from the CLKi terminal (Note 2)
• To start transmit/reception, the following requirements must be met: - Select the synchronous clock (use bit 6 of 036216, 036616). Select a frequency dividing ratio if the internal clock has been selected (use bits 0 and 1 of 036216, 036616). - SOUT i initial value set bit (use bit 7 of 036216, 036616)= 1. - S I/Oi port select bit (bit 3 of 036216, 036616) = 1. - Select the transfer direction (use bit 5 of 036216, 036616) - Write transfer data to SI/Oi transmission/reception register(036016, 036416)
• To use S I/Oi interrupts, the following requirements must be met: - S I/Oi interrupt request bit (bit 3 of 004916, 004816) = 0.
• At the rising edge of the last transfer clock (Note3)
• LSB first or MSB first selection Whether transmission/reception begins with bit 0 (LSB) or bit 7 (MSB) can be selected. S I/O3, 4
• The SOUT i default value setting function If the transfer clock is selected to external clock, the output level of SOUT i pin can be selected when it is not in transferring please refer to Fig.GA-30.
• The SI/Oi (i=3,4) is different from UART0 to 2 that the register and buffer can not be separated, so don't write the next transfer data to the transmission/reception register(0360 16, 036416) during transferring.
• If the transfer clock is selected to internal clock, at the end of transferring, the SOUT i holds the last data during the last 1/2 transfer clock, and then to high impedance. If the transmission/reception register(036016, 036416) is written during the period, the SOUT i becomes the high impedance right the writing ,the data hold time will be shortened.

UART2 Special Mode Register Mitsubishi microcomputers M16C / 6K7 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 125 Rev.1.0 Functions for setting an SOUT i initial value In carrying out transmission, the output level of the SOUT i pin as it is before transmitting 1-bit data can be set either to “H ” or to “L”. Fig.GA-30 shows the timing chart for setting an SOUT i initial value and how to set it. Fig.GA-30 Timing chart for setting SOUT i’s initial value and how to set it S I/Oi operation timing Fig.GA-31 shows the S I/Oi operation timing Fig.GA-31 S I/Oi operation timing chart SI/Oi port selection bit SMi3 = 0 SOUTi initial value selection bit SMi7 = 1 (SOUTi: Internal "H" level) SI/Oi port selection bit SMi3 = 0 1 (Port selection: Normal port SOUTi) Signal written to the SI/Oi register (Falling edge ) SOUT i pin = Outputting stored data in the SI/Oi transmission/ reception register SOUTi pin = "H" output Signal written to the SI/Oi transmission /reception register SOUT i (internal) SOUT i's initial value set bit (SMi7) SOUT i pin output SI/Oi port selection bit (SMi3) (i = 3, 4) (Example) With "H" selected for SOUTi Note: The set value is output only when the external clock has been selected. Please set the SOUTi default under the status that the CLKi is input to "H" level. If the internal clock has been selected or if SOUTi output inhibition has been set, this output goes to the high-impedance state. Setting the SOUTi initial value to H Port selection (normal port SOUTi) D 0 Initial value = "H"(Note) Port output D 0 Note 1: With the internal clock selected for the transfer clock, the frequency dividing ratio can be selected using bits 0 and 1 of the SI/Oi control register (i = 3,4). (No frequency division, 8-division frequency, 32-division frequency.) Note 2: With the internal clock selected for the transfer clock, the SOUTi (i = 3,4) pin becomes to the high-impedance state after the transfer finishes. Note 3: The figure shows when the port selection bit of SOUTi (i = 3,4) is set to "1". D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 Transfer clock (Note 1) S I/Oi output SOUTi (i= 3, 4) SI/Oi input SINi (i= 3, 4) Signal written to the SI/Oi register (Note 2) SI/Oi internal clock Hiz SI/Oi interrupt request bit (i=3,4) MAX:1.5 cycle "1" "0" Hiz

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 126 Rev.1.0 Item Performance Method of A-D conversion Successive approximation (capacitive coupling amplifier) Analog input voltage 0V to AVCC (VCC ) Operating clockφAD (Note1) fAD /divide-by-2 of fAD /divide-by-4 of fAD , fAD =f(XIN) Resolution 8-bit or 10-bit (selectable) Absolute precision • 8-bit resolution ±2LSB

• 10-bit resolution ±6LSB Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 Analog input pins 8pins (AN 0 to AN7) + 2pins (ANEX0 and ANEX1) A-D conversion start condition•Software trigger A-D conversion starts when the A-D conversion start flag changes to “1”
• External trigger (can be retriggered) A-D conversion starts when the A-D conversion start flag is “1” and the AD TRG /P97 input changes from “H ” to “L” Conversion speed per pin•Without sample and hold function 8-bit resolution : 49 φAD cycles 10-bit resolution : 59 φAD cycles
• With sample and hold function 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles A-D Converter The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P100 to P107, P95, and P96 also function as the analog signal input pins. The direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D7 16) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF ) when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from VREF , reducing the power dissipation. When using the A-D converter, start A-D con- version only after setting bit 5 of 03D716 to connect VREF . The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses. Table.JA-1 shows the performance of the A-D converter. Fig.JA-1 shows the block diagram of the A-D converter, and Fig.JA-2 and JA-3 show the A-D converter-related registers. Note 1: Without sample and hold function,set the φAD frequency to 250kHz min. With the sample and hold fucntion, set the φAD frequency to 1MHz min. Table.JA-1 Performance of A-D converter

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERA-D Converter 127 Rev.1.0 Fig.JA-1 Block diagram of A-D converter (03C116, 03C016) (03C316, 03C216) (03C516, 03C416) (03C716, 03C616) (03C916, 03C816) (03CB16, 03CA16) (03CD16, 03CC16) (03CF16, 03CE16) 0 0 : AN0-AN7 0 1 : ANEX0 1 0 : ANEX1 1 1 : Inhibited A-D register 0(16) A-D register 1(1 6)A-D register 2(1 6)A-D register 3(1 6)A-D register 4(16) A-D register 5(16) A-D register 6(16) A-D register 7(16) Resistor ladder ANEX1 ANEX0 Successive conversion register OPA1,OPA0=0,1 OPA1,OPA0=1,0 AN 0 AN 1 AN 2 AN 3 AN 5 AN 6 AN 7 A-D control register 0 (address 03D616) A-D control register 1 (address 03D716) Vref VIN Data bus high-order Data bus low-order VREF AN 4 OPA1,OPA0=0,0 VCUT=0 AV SS VCUT=1 CH2,CH1,CH0=000 CH2,CH1,CH0=001 CH2,CH1,CH0=010 CH2,CH1,CH0=011 CH2,CH1,CH0=100 CH2,CH1,CH0=101 CH2,CH1,CH0=110 CH2,CH1,CH0=111 Decoder Comparator OPA1, OPA0 Addresses A-D conversion rate selection 1/2 1/2 fAD CKS0=0 CKS0=1 CKS1=1 φAD CKS1=0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 128 Rev.1.0 Fig.JA-2 A-D converter-related registers (1) A-D control register 0 (Note 1) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin selection bits 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected (Note 2) CH0 Bit symbol Bit name Function CH1 CH2 A-D operation mode selection bits 0 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 Repeat sweep mode 1 (Note 2) MD0 MD1 Trigger selection bit 0 : Software trigger 1 : ADTRG trigger TRG ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency selection bit 00 : fAD /4 is selected 1 : fAD /2 is selected CKS0 W R A-D control register 1 (Note) Symbol Address When reset ADCON1 03D7 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin selection bits SCAN0 SCAN1 MD2 BITS 8/10-bit mode selection bit0 : 8-bit mode 1 : 10-bit mode VCUT OPA0 Vref connect bit OPA1 A-D operation mode selection bit 1 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 0 : Vref not connected 1 : Vref connected ANEX0,1 selection bits W R b2 b1 b0 b4 b3 When single sweep and repeat sweep mode 0 are selected 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) b1 b0 When repeat sweep mode 1 is selected 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) b1 b0 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : Inhibited b7 b6 Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again. Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines CKS1 Frequency selection bit 10 : fAD /2 or fAD /4 is selected 1 : fAD is selected /LiteDiagLines/LiteDiagLines/LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERA-D Converter 129 Rev.1.0 Fig.JA-3 A-D converter-related registers (2) A-D register i Symbol Address When reset ADi(i=0 to 7) 03C0 16 to 03CF16 Indeterminate Eight low-order bits of A-D conversion result Function (b15) b7b7 b0 b0 (b8)

• During 10-bit mode Two high-order bits of A-D conversion result Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
• During 8-bit mode When read, the content is indeterminate RW /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines A-D control register 2 (Note) Symbol Address When reset ADCON2 03D4 16 0000XXX0 2 b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion method select bitSMP Bit symbol Bit name Function Reserved bit Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. W R Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 0 : Without sample and hold 1 : With sample and hold Always set to “0”. 0 0 0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 130 Rev.1.0 (1) One-shot mode In one-shot mode, the pin selected using the analog input pin selection bits is used for one-shot A-D conver- sion. Table.JA-2 shows the specifications of one-shot mode. Fig.JA-4 shows the A-D control register in one- shot mode. Table.JA-2 One-shot mode specifications Fig.JA-4 A-D conversion register in one-shot mode Item Specification Function The pin selected by the analog input pin selection bits is used for one A-D conversion Start condition Writing “1” to A-D conversion start flag Stop condition •End of A-D conversion (A-D conversion start flag changes to “0”, except when external trigger is selected)

• Writing “0” to A-D conversion start flag Interrupt request generation timingEnd of A-D conversion Input pin One of AN 0 to AN7, as selected Reading of result of A-D converterRead A-D register corresponding to selected pin A-D control register 0 (Note 1) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin selection bits Bit symbol Bit name Function CH1 CH2 A-D operation mode selection bits 0 MD0 MD1 Trigger selection bit 0 : Software trigger 1 : ADTRG triggerTRG ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency selection bit 00: fAD /4 is selected 1: fAD /2 is selected CKS0 W R 0 0 A-D control register 1 (Note) Symbol Address When reset ADCON1 03D7 16 0016 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin selection bits SCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT OPA0 Vref connect bit OPA1 A-D operation mode selection bit 1 0 : Any mode other than repeat sweep mode 1 1 : Vref connected ANEX0,1 selection bis 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : Inhibited W R Invalid in one-shot mode 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected (Note 2) b2 b1 b0 0 0 : One-shot mode (Note 2) b4 b3 CH0 b7 b6 Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again. Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Frequency selection bit 1CKS1 0: fAD /2 or fAD /4 is selected 1: fAD is selected /LiteDiagLines/LiteDiagLines/LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERA-D Converter 131 Rev.1.0 (2) Repeat mode In repeat mode, the pin selected using the analog input pin selection bits is used for repeated A-D conver- sion. Table.JA-3 shows the specifications of repeat mode. Fig.JA-5 shows the A-D control register in repeat mode. Fig.JA-5 A-D conversion register in repeat mode Item Specification Function The pin selected by the analog input pin selection bits is used for repeated A-D conversion Star condition Writing “1” to A-D conversion start flag Stop condition Writing “0” to A-D conversion start flag Interrupt request generation timingNot generated Input pin One of AN 0 to AN7, as selected Reading of result of A-D converterRead A-D register corresponding to selected pin Table.JA-3 Repeat mode specifications A-D control register 0 (Note 1) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin selection bits CH0 Bit symbol Bit name Function CH1 CH2 A-D operation mode selection bits 0 MD0 MD1 Trigger selection bit 0 : Software trigger 1 : ADTRG triggerTRG ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency selection bit 00 : fAD /4 is selected 1 : fAD /2 is selected CKS0 W R A-D control register 1 (Note) Symbol Address When reset ADCON1 03D7 16 0016 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin selection bits SCAN0 SCAN1 MD2 BITS 8/10-bit mode selection bit 0 : 8-bit mode 1 : 10-bit mode VCUT OPA0 Vref connect bit OPA1 A-D operation mode selection bit 1 1 : Vref connected W R Invalid in repeat mode 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected (Note 2) b2 b1 b0 0 1 : Repeat mode (Note 2) b4 b3 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : Inhibited b7 b6 Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again. Should be "0" in this mode Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines CKS1 /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLinesFrequency selection bit 10: fAD /2 or fAD /4 is selected 1: fAD is selected ANEX0,1 selection bis

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 132 Rev.1.0 (3) Single sweep mode In single sweep mode, the pins selected using the A-D sweep pin selection bits are used for one-by-one A- D conversion. Table.JA-4 shows the specifications of single sweep mode. Fig.JA-6 shows the A-D control register in single sweep mode. Table.JA-4 Single sweep mode specifications Fig.JA-6 A-D conversion register in single sweep mode Item Specification Function The pins selected by the A-D sweep pin selection bits are used for one-by-one A-D conversion Start condition Writing “1” to A-D converter start flag Stop condition •End of A-D conversion (A-D conversion start flag changes to “0”, except when external trigger is selected)

• Writing “0” to A-D conversion start flag Interrupt request generation timingEnd of A-D conversion Input pin AN 0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Reading of result of A-D converterRead A-D registers corresponding to selected pins A-D control register 0 (Note) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin selection bitsCH0 Bit symbol Bit name Function CH1 CH2 A-D operation mode selection bits 0 1 0 : Single sweep modeMD0 MD1 Trigger selection bit 0 : Software trigger 1 : ADTRG triggerTRG ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency selection bit 0 0 : fAD /4 is selected 1 : fAD /2 is selected CKS0 WR A-D control register 1 (Note 1) Symbol Address When reset ADCON1 03D7 16 0016 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bitSCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit0 : 8-bit mode 1 : 10-bit mode VCUT OPA0 Vref connect bit Should be "0" in this mode OPA1 A-D operation mode select bit 1 1 : Vref connected W R 1 0 Invalid in single sweep mode Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. b4 b3 When single sweep and repeat sweep mode 0 are selected 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) b1 b0 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : Inhibited b7 b6 Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines ANEX0,1 selection bis CKS1 Frequency selection bit 10 : fAD /2 or fAD /4 is selected 1 : fAD is selected /LiteDiagLines/LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERA-D Converter 133 Rev.1.0 (4) Repeat sweep mode 0 In repeat sweep mode 0, the pins selected using the A-D sweep pin selection bits are used for repeat sweep A-D conversion. Table.JA-5 shows the specifications of repeat sweep mode 0. Fig.JA-7 shows the A-D control register in repeat sweep mode 0. Fig.JA-7 A-D conversion register in repeat sweep mode 0 Item Specification Function The pins selected by the A-D sweep pin selection bits are used for repeat sweep A-D conversion Start condition Writing “1” to A-D conversion start flag Stop condition Writing “0” to A-D conversion start flag Interrupt request generation timingNot generated Input pin AN 0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Reading of result of A-D converterRead A-D registers corresponding to selected pins (at any time) Table.JA-5 Repeat sweep mode 0 specifications A-D control register 0 (Note) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin selection bitsCH0 Bit symbol Bit name Function CH1 CH2 A-D operation mode selection bits 0 1 1 : Repeat sweep mode 0MD0 MD1 Trigger selection bit 0 : Software trigger 1 : ADTRG triggerTRG ADST A-D conversion start flag0 : A-D conversion disabled 1 : A-D conversion started Frequency selection bit 00 : fAD /4 is selected 1 : fAD /2 is selectedCKS0 WR A-D control register 1 (Note 1) Symbol Address When reset ADCON1 03D7 16 0016 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin selection bitsSCAN0 SCAN1 MD2 BITS 8/10-bit mode selection bit0 : 8-bit mode 1 : 10-bit mode VCUT OPA0 Vref connect bit Should be "0" in this mode OPA1 A-D operation mode selection bits 1 1 : Vref connected W R 1 1 Invalid in repeat sweep mode 0 Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. b4 b3 When single sweep and repeat sweep mode 0 are selected 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) b1 b0 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : Inhibited b7 b6 Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines ANEX0,1 selection bis CKS1 Frequency selection bit 10 : fAD /2 or fAD /4 is selected 1 : fAD is selected /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 134 Rev.1.0 Item Specification Function All pins perform repeat sweep A-D conversion, with emphasis on the pin or pins selected by the A-D sweep pin selection bits Example : AN0 selected AN0 AN1 AN0 AN2 AN0 AN3, etc Start condition Writing “1” to A-D conversion start flag Stop condition Writing “0” to A-D conversion start flag Interrupt request generation timingNot generated Input pin AN 0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins) Reading of result of A-D converterRead A-D registers corresponding to selected pins (at any time) (5) Repeat sweep mode 1 In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using the A-D sweep pin selection bits. Table.JA-6 shows the specifications of repeat sweep mode 1. Fig.JA-8 shows the A-D control register in repeat sweep mode 1. Fig.JA-8 A-D conversion register in repeat sweep mode 1 Table.JA-6 Repeat sweep mode 1 specifications A-D control register 0 (Note) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin selection bitsCH0 Bit symbol Bit name Function CH1 CH2 A-D operation mode selection bits 0 1 1 : Repeat sweep mode 1MD0 MD1 Trigger select bit 0 : Software trigger 1 : ADTRG triggerTRG ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selectedCKS0 WR A-D control register 1 (Note 1) Symbol Address When reset ADCON1 03D7 16 0016 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin selection bitsSCAN0 SCAN1 MD2 BITS 8/10-bit mode selection bit0 : 8-bit mode 1 : 10-bit mode VCUT OPA0 Vref connect bit 1 : Repeat sweep mode 1 OPA1 A-D operation mode selection bit 1 1 : Vref connected W R 1 1 Invalid in repeat sweep mode 1 Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. b4 b3 When repeat sweep mode 1 is selected 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) b1 b0 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : Inhibited b7 b6 Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines ANEX0,1 selection bis CKS1 Frequency selection bit 1 0 : fAD /2 or fAD /4 is selected 1 : fAD is selected /LiteDiagLines/LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERA-D Converter 135 Rev.1.0 (a) Sample and hold Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”. When sample and hold is selected, the rage of conversion of each pin increases. As a result, a 28 fAD cycle is achieved with 8-bit resolution and 33fAD with 10-bit resolution. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and hold is to be used. (b) Extended analog input pins In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can also be converted from analog to digital. When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “0”, input via ANEX0 is converted from analog to digital. The result of conversion is stored in A-D register 0. When bit 6 of the A-D control register 1 (address 03D716) is “0” and bit 7 is “1”, input via ANEX1 is converted from analog to digital. The result of conversion is stored in A-D register 1.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 136 Rev.1.0 D-A Converter This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of this type. DA conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 (D-A output enable bits) of the D-A control register decide if the result of conversion is to be output. Do not set the corresponding port to output mode if D-A conversion is to be performed. If D-A output is enabled, the pull-up of corresponding port is inhibited. Output analog voltage (V) is determined by a set value n (n : decimal) in the D-A register. V = V REF X n/ 256 (n = 0 to 255) VREF : reference voltage Table.JB-1lists the performance of the D-A converter. Fig.JB-1 shows the block diagram of the D-A con- Table.JB-1 Performance of D-A converter Item Performance Conversion type R-2R type Resolution 8 bits Analog output pins 2 channels Fig.JB-1 Block diagram of D-A converter /LiteDiagLines/LiteDiagLines/LiteDiagLines P93/DA0 /LiteDiagLines/LiteDiagLines/LiteDiagLines P94/DA1 Data bus low-order bits D-A register0 (8) R-2R resistor ladder D-A0 output enable bit D-A register1 (8) R-2R resistor ladder D-A1 output enable bit (Address 03D816) (Address 03DA16)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 137 Rev.1.0 Fig.JB-2 D-A control register Fig.JB-3 D-A converter equivalent circuit D-A control register Symbol Address When reset DACON 03DC 16 0016 b7 b6 b5 b4 b3 b2 b1 b0 D-A0 output enable bit DA0E Bit symbol Bit name Function R W 0 : Output disabled 1 : Output enabled D-A1 output enable bit 0 : Output disabled 1 : Output enabled DA1E Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”D-A register Symbol Address When reset DAi (i = 0,1) 03D816, 03DA 16 Indeterminate W R b7 b0 Function R W Output value of D-A conversion /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines VREF AV SS R R R R R R R DA0 MSB LSB D-A0 output enable bit "0" "1" D-A0 register0 Note 1: The above diagram shows an instance in which the D-A register is assigned 2A16. Note 2: The same circuit as this is also used for D-A1. Note 3: To reduce the current consumption when the D-A converter is not used, set the D-A output enable bit to 0 and set the D-A register to 0016 Do not let current flows through R-2R resistors.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 138 Rev.1.0 Comparator Circuit Comparator Configuration A comparator circuit consists of a switch tree, ladder resistance, comparators, comparator control circuit, the comparator control register (address 03DE16), comparator data register (address 03DF16), and analog signal input pins(P50 - P57). The analog input pins (P50 - P57) are shared with the usual digital port I/O pins. The comparator control register is a 4-bit register and can generate internal analog voltages in steps of 1/16 Vcc with the contens of bits 0 to 3. In Table.JC-2 contents of bits 0 to 3 of the comparator control register and corresponding internal analog voltage generated are indicated. The compared result of the analog input voltage and internal analog voltage is stored in the comparator data register. The value of comparator control register can not be read out. Comparator Operation In order to perform comparator operation, first, set the port P5 direction register (address 03EB16) to "0", as P5 can be used as the analog input pins. Then write a digital value, which corresponds to the internal analog voltage to be compared, to bits 0 to 3 of the comparator control register (address 03DE 16) . The voltage comparison starts immediately by the writing operation. After 14 cycles of 1/2 main clock (the time needed for comparison), the compared result of the comparator is stored in the comparator data register (address 03DF 16). Each bit of this register becomes as follows depending on the status of corresponding P50 to P57 pins: When analog input voltage > internal analog voltage, it is "1". When analog input voltage < internal analog voltage, it is "0". For comparing once more, it is necessary to write data into comparator control register again even if the internal analog voltage is the same. To read the result, wait 14 or more cycles after the comparator operation starts. During the 14 cycles of the comparison, the ladder resistance is turned on and the reference voltage is generated. When the comparator is not in operation, the ladder resistance is off. Therefore, unnecessary consumption is prevented. The comparison is accomplished by capacitive coupling. If the clock frequency is too low, electric charge will be lost. While the comparator is in operation, the clock frequency must be 1MHz or higher. During this time, do not execute a STP instruction, a WIT instruction, or an I/O instruction for port P5. Fig.JC-1 Comparator circuit VSS 8 8 P5 (8) P57 P56 P50 Comparator data register(03DF16) Compa rator R-ladder connection signal Comparator Control CricuitComparator connection signal Compa rator Compa rator Data bus Comparator control register(03DE16) Switch Tree R-ladder

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 139 Rev.1.0 Fig.JC-2 Comparator control register Table.JC-1 Correspondence of internal analog voltage and contents of bits 0 to 3 of the comparator control register. Comparator Control Register Internal Analog Voltage Contents of bit 0 to 3 0 0 0 0 LSB 1 / 32•Vcc 0 0 0 1 1 / 16 •Vcc + 1 / 32•Vcc 0 0 1 0 2 / 16 •Vcc + 1 / 32•Vcc 0 0 1 1 3 / 16 •Vcc + 1 / 32•Vcc 0 1 0 0 4 / 16 •Vcc + 1 / 32•Vcc 0 1 0 1 5 / 16 •Vcc + 1 / 32•Vcc 0 1 1 0 6 / 16 •Vcc + 1 / 32•Vcc 0 1 1 1 7 / 16 •Vcc + 1 / 32•Vcc 1 0 0 0 8 / 16 •Vcc + 1 / 32•Vcc 1 0 0 1 9 / 16 •Vcc + 1 / 32•Vcc 1 0 1 0 10 / 16 •Vcc + 1 / 32•Vcc 1 0 1 1 11 / 16 •Vcc + 1 / 32•Vcc 1 1 0 0 12 / 16 •Vcc + 1 / 32•Vcc 1 1 0 1 13 / 16 •Vcc + 1 / 32•Vcc 1 1 1 0 14 / 16 •Vcc + 1 / 32•Vcc 1 1 1 1 15 / 16 •Vcc + 1 / 32•Vcc Comparator Control register Bit name FunctionBit Symbol W R Symbol Address When Reset CMPCON 03DE 16 0016 CREFS Internal analog voltage setting bits n/16•VCC +1/32•VCC n=setting vaule Reserved bit Can't be written. "0" will be read out. b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 140 Rev.1.0 Pulse Width Modulation (PWM) Output Circuit The M16C/6K group has four PWM output circuits, PWM0 to PWM3, with 14-bit resolution. They operate independently. When the oscillation frequency XIN= 8MHz, the minimum resolution bit width is 250 ns and the cycle period is 4096 µs. The PWM timing generator supplies a PWM control signal based on the XIN clock. The following explanation assumes XIN = 8 MHz. Fig.LA-1 PWM blobk diagram(PWM0) P44 latch P44/PWM 01 PWM0L register (address 030116) PWM0H register (address 030016) bit 7 bit 0bit 5 MSB LSB PWM 0 bit 7 bit 0 PWM0 timing generator (64 µs period) (4096 µs period) PWM0 latch (14 bits) Set to “1” at write Data Bus f(XIN) (8MHz) 14-bit PWM0 circuit P93 direction register PWM 0 output enable bit P93 latch P93/DA1/PWM 00 PWM 0 output selection bit P44 direction register (4MHz) PWM 0 output enable bit PWM 0 output selection bitPWM0 operation bit

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERPWM 141 Rev.1.0 Data Setup (PWM0) The PWM 0 output pin shares with P93 or P44. The PWM0 output pin is selected from either P93/PWM 00 or P44/PWM 01 by bit 0 of PWM control register 0 (address 030816). The PWM0 output is enabled by setting bit 4 of PWM control register (address 030816) to "1". The PWM operation starts by setting bit 0 of PWM control register 1 (address 030916) to "1". The high-order eight bits of output data are set in the PWM0H register (address 030016) and the low-order six bits are set in the PWM0L register (address 030116). PWM1 to PWM3 is set as the same way. PWM Operation The 14-bit PWM data is divided into the low-order six bits and the high-order eight bits in the PWM latch. The high-order eight bits of data determine how long an “H ”-level signal is output during each sub-period. There are 64 sub-periods in each period, and each sub-period is 256 X τ (64 µs) long. The signal is “H ” for a length equal to N times τ, where τ is the minimum resolution (250 ns). “H ” or “L” of the bit in the ADD part shown in Fig. LA-2 is added to this “H ” duration by the contents of the low-order 6-bit data according to the rule in Table.LA-1. That is, only in the sub-period tm shown by Table.LA-1 in the PWM cycle period T = 64t, its “H ” duration is lengthened to the minimum resolution τ added to the length of other periods. For example, if the high-order eight bits of the 14-bit data are 03 16 and the low-order six bits are 0516, the length of the “H ”-level output in sub-periods t8, t24, t32, t40, and t56 is 4 τ, and its length is 3 τ in all other sub- periods. Time at the “H ” level of each sub-period almost becomes equal, because the time becomes length set in the high-order 8 bits or becomes the value plus τ, and this sub-period t (= 64 µs approximate 15.6 kHz) becomes cycle period approximately. Transfer From Register to Latch Data written to the PWML register is transferred to the PWM latch at each PWM period (every 4096 µs) and data written to the PWMH register is transferred to the PWM latch at each sub-period (every 64 µs). The signal which is output to the PWM output pin corresponds to the contents of this latch. A read from the PWML gets the latch content. However, bit 7 of the PWML register indicates whether the transfer to the PWM latch is completed; the transfer is completed when bit 7 is “0” and it is not done when bit 7 is “1.” Table.LA-1 Relationship between low-order 6 bits of data and period set by the ADD bit. Low-order 6 bits of data (PWML) Sub-periods tm Lengthened (m=0 to 63) 0 0 0 0 0 0 LSB None 0 0 0 0 0 1 m=32 0 0 0 0 1 0 m=16,48 0 0 0 1 0 0 m=8,24,40,56 0 0 1 0 0 0 m=4,12,20,28,36,44,52,60

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 142 Rev.1.0 Fig.LA-2 PWM timing 4096 µs 64 µs 64 µs 64 µs 64 µs 64 µs m=0 m=7 m=9 m=63m=8 Pulse width modulation register H Pulse width modulation register L Sub-periods where “H ” pulse width is 16.0 µs : Sub-periods where “H ” pulse width is 15.75 µs : : 00111111 : 000101 m = 8, 24, 32, 40, 56 m = all other values

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERPWM 143 Rev.1.0 Fig.LA-3 14-bit PWM timing (PWM0) 6A 6A 6A 6A 6A 6B 6A 6A 6A 6A 6A 6A 6A 6A6B 6B 6B 6B 6B 6B 6B 6B 6B 6B 6B 6B 6B 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6A 6A 6B 6B 6B 6A 6B 6B 6B 6A 6B 6B 6B 6A6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 4 3 4 4 3 4 4 3 4 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 6B 6A 69 68 67 02 01 6A 69 68 67 02 01 02 01 00 FF FE FD 97 96 95 02 01 00FC FF FE FD 97 96 95FC ADD ADD 165316 1A9316 1AA4 16 1AA4 16 1EE4 16 1EF5 16 T = 4096 µs (64 X 64 µs) t = 64 µs When bit 7 of PWM0L is 0, transfer from register to latch is disabled.

1316 A416 2416 3516

Data 2416 stored at address 030116 Data 6A16 stored at address 030016 Data 7B16 stored at address 030016 Data 3516 stored at address 030116 Transfer from register to latch Transfer from register to latch Bit 7 cleared after transfer (107) (106) t = 64 µs (256 X 0.25 µs) Minimum resolution bit widthτ = 0.25 µs H duration length specified by PWM0H 256 τ (64 µs), fixed The ADD portions with additional τ are determined by PWML. PWM0H register PWM0L register PWM0 latch (14bits) Example 1 PWM 0 output low-order 6-bit output: Example 2 PWM 0 output low-order 6-bit output: H L 6A16, 1816 PWM output 8-bit counter

106 X 64 + 24

106 X 64 + 36

6A16, 2416

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 144 Rev.1.0 Fig.LA-4 PWM control registers PWM control register 0 Bit name FunctionBit symbol W R Symbol Address When reset PWMCON0 0308 16 0016 PWMSEL0 PWM0 output pin selection bit 0 : disable 1 : enable 0 : disable 1 : enable 0 : P93/PWM 00 1 : P44/PWM 01 0 : P94/PWM 10 1 : P45/PWM 11 0 : P95/PWM 20 1 : P46/PWM 21 0 : P96/PWM 30 1 : P47/PWM 31 0 : disable 1 : enable PWM1 output pin selection bit PWM2 output pin selection bit PWM3 output pin selection bit PWM0 output enable bit PWM1 output enable bit 0 : disable 1 : enable PWM2 output enable bit PWM3 output enable bit PWMSEL1 PWMSEL2 PWMSEL3 PWMEN0 PWMEN1 PWMEN2 PWMEN3 b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines PWM control register 1 Bit name FunctionBit symbol W R Symbol Address When reset PWMCON1 0309 16 0016 PWMST0 PWM0 operation bit 0 : operation stop 1 : operation start 0 : operation stop 1 : operation start 0 : operation stop 1 : operation start 0 : operation stop 1 : operation start PWM1 operation bit PWM2 operation bit PWM3 operation bit PWMST1 PWMST2 PWMST3 b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Reserved bit Can't be written. "0" will be read out.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 145 Rev.1.0 LPC Bus Interface LPC bus interface is based on Intel Low Pin Count (LPC) Interface Specification, Revision 1.0. It is I/O cycle data transfer format of serial communication. 4 channels are built in. The function of data bus buffer and data bus buffer status are almost the same as that of MELPS8-41 series. It can be written in or read out (as slave mode) by the control signals from host CPU side. The LPC bus interface functionality block diagram is shown in Figure GF-2. LPC data bus buffer functional Input / Output ports (P3 0-P36 ) are shared with GPIO port. The setting of bit3 (LPC bus buffer enable bit) of LPC control register (02D616 ) is as below: 0: General purpose Input / Output port 1: LPC bus buffer functional Input / Output port The enabling of channel of LPC bus buffer is controlled by bits 4-7 (LPC bus buffer 0-3 enable bits) of LPC control register (02D6 16 ). The slave address (16 bits) of LPC bus buffer channel 0 is fixed on 0060h, 0064h. The slave addresses (16 bits) of LPC bus buffer channel 1-3 are definable by setting LPC 1-3 address register H, L (02D0 16 to 02D516 ). The setting value of bit2 of LPC1-3 address register (A2) L will not be decoded. The bit is “0” when read from slave CPU. The A2 status of slave address is latched to XA2 flag when written by host CPU. The input buffer full interrupt is generated when written in the data by host CPU. The Output buffer empty interrupt is generated when read out the data by host CPU. As shown in GF-1, the input buffer full interrupt request and output buffer empty interrupt request are switched by bit6, 7 of ISA control register0.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 146 Rev.1.0 Fig.GF-1 Interrupt, request, circuit of Data Bus Buffer IBF3/OBE interrupt request IBF2/OBE interrupt request IBF1/OBE interrupt request OBE OBF 3(OBE 3) OBF 2(OBE 2) OBF 1(OBE 1) OBF 0(OBE 0) IBF3INT IBF3 IBF2INT IBF2 IBF1INT IBF1 IBF0 interrupt request IBF0 (Example) ISA control register 0 bit 7=1, bit 6=1 DBBCON 0 bit 7,6 Output buffer full flag0 OBF0 Input buffer full flag0 IBF0 Rising edge detection circuit One shot pulse generator Input Buffer Full0 interrupt request signal (IBF0 interrupt request) Input buffer full flag1 IBF1 Rising edge detection circuit One shot pulse generator Input Buffer Full1/output buffer empty interrupt request signal (IBF1/OBE interrupt request) Input buffer full flag2 IBF2 Rising edge detection circuit One shot pulse generator Input Buffer Full2/output buffer empty interrupt request signal (IBF2/OBE interrupt request) Input buffer full flag3 IBF3 Rising edge detection circuit One shot pulse generator Input Buffer Full3/output buffer empty interrupt request signal (IBF3/OBE interrupt request) IBF1INT IBF2INT IBF3INT b7,b6 0 0 1 0 1 1 b7,b6 0 0 0 1 1 1 b7,b6 0 0 0 1 1 0 b7,b6 0 1 b7,b6 1 0 b7,b6 1 1 Rising edge detection circuit One shot pulse generator Output buffer full flag1 OBF1 Output buffer full flag2 OBF2 Output buffer full flag3 OBF3 OBE OBE 0 OBE 1 OBE 2 OBE 3 Rising edge detection circuit One shot pulse generator Rising edge detection circuit One shot pulse generator Rising edge detection circuit One shot pulse generator

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 147 Rev.1.0 Fig.GF-2 LPC bus interface function block diagram (LPC1) Note1 : LPC bus interface channel 0 is fixed on slave address “0060h”, “0064h”. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Input Control Circuit Input Data Buffer [7:4] LPC control register (address 02D616) U 7 U 6 U 5 U 4 XA2 U 2 IBF OBF b7 b6 b5 b4 b3 Interrupt generate Circuit Interrupt signal IBF, OBE P32/LAD2 P33/LAD3 P31/LAD1 P30/LAD0 P34/LFRAME Input Data Buffer [3:0] Output Data Buffer [7:4]Output Data Buffer [3:0] P36/LCLK Output Control Circuit P35/LRESET 0 0 System Bus Input Data Comparator TAR registerSYNC register Data bus buffer status register Start registerRD/WR register Address register HH (Note1)Address register HL (Note1)Address register LH (Note1)Address register LL (Note1) Internal Data Bus

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 148 Rev.1.0 Figure GF-3: ISA control registers Figure GF-4: Data bus buffer status register Figure GF-5, 6: LPC related registers Data bus buffer status register (DBBSTS0-DBBSTS3) This is 8-bit register. The bit 0, 1, 3 are read only bits and indicatie the status of data bus buffer. Bit 2, 4, 5, 6, 7 are user definable and flags which can be read and written by software. The data bus buffer status register can be read out by host CPU when the slave address (16 bit) bit2 (A2) is high.

• Output buffer full flag (OBF) The bit will be set to "1" when a data is written into output data bus buffer and will be cleared to "0" when host CPU read out the data from output data bus buffer.
• Input buffer full flag (IBF) The bit will be set to "1" while a data is written into input data bus buffer by host CPU and will be cleared to "0" when the data is read out from input data bus buffer by slave CPU.
• XA2 flag (XA2) The bit 2 of slave address (16 bits) is latched while a data is written into data bus buffer. Input data bus buffer register (DBBIN0-DBBIN3) When there is a write request from host CPU, the data on the data bus will be latched to DBBIN0-3. The data of DBBIN0-3 can be read out from data bus buffer registers (Address:02C0 16, 02C216 , 02C416 , 02C616 ) in SFR field. Output data bus buffer register (DBBOUT0-DBBOUT3) When writing data to data bus buffer registers (Address: 02C016 , 02C216 , 02C416 , 02C616 ), the data will be transferred to DBBOUT0-3 automatically. The data of DBBOUT0-3 will be output to the data bus when there is a read request from host CPU and the status of bit2 (A2) of slave address (16 bits) is low. LPCi address register H/L (LPC1ADH-LPC3ADH / LPC1ADL-LPC3ADL) The slave address (16 bits) of LPC bus buffer channel 0 is fixed on 0060h, 0064h. The slave addresses (16 bits) of LPC bus buffer channel 1-3 are definable by setting LPC1-3 address regis- ters H/L (02D0 16 to 02D516 ). The settings are for slave address upper 8 bits and lower 8 bits. And these registers can be set and cleared in any time. The bit 2 of LPC 1-3 address L is not decoded regardless of the setting value. When slave CPU reads LPC1- 3 address registers, the bit2 (A2) of address low byte will be fixed to "0". The bit2 (A2) status of slave address is latched to XA2 flag when written by host CPU. The slave addresses that are already set in these registers will be used for comparing with the addresses to be received.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 149 Rev.1.0 LPC control register (LPCCON)

• LPC bus interface enable bit (LPCBEN) "0": P30 -P36 use as GPIO "1": P30 -P36 use as LPC bus interface
• LPC bus buffer 0 enable bit (LPCEN0) "0": LPC bus buffer0 disable "1": LPC bus buffer0 enable
• LPC bus buffer 1 enable bit (LPCEN1) "0": LPC bus buffer1 disable "1": LPC bus buffer1 enable
• LPC bus buffer 2 enable bit (LPCEN2) "0": LPC bus buffer2 disable "1": LPC bus buffer2 enable
• LPC bus buffer 3 enable bit (LPCEN3) "0": LPC bus buffer3 disable "1": LPC bus buffer3 enable
• LPC software reset bit (LPCSR) By setting the bit to "1", LPC interface is reset by the same status as LRESET="L". After 1.5 cycles of BCLK at writing "1", reset is released and the bit becomes "0". Nothing happens if "0" is set.
• SYNC output selection bits (SYNCSEL0,SYNCSEL1) Table.GF-1 shows the content of SYNC output selected by SYNC output selection bits. Table GF-1 SYNC output SYNCSEL1 SYNCSEL0 SYNC cycle 1st cycle 00002 01102 10102 01102 2nd cycle 01102 01102 3rd cycle 01102 01102 4th cycle 00002 10102 SYNC output

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 150 Rev.1.0 Fig.GF-3 ISA control registers ISA control register 0 Bit nameBit symbol W R Symbol Address When reset DBBCON0 02C8 16 000000002 b7 b6 b5 b4 b3 b2 b1 b0 Function IBF/OBE interrupt request select bit IBFSEL b7 b6 (Note 1) 0 0 : OBE disable 0 1 : OBE enable, IBF 1 disable 1 0 : OBE enable, IBF2 disable 1 1 : OBE enable, IBF3 disable Note 1: By setting these two bits, one of IBF1 to IBF3 interrupt requests will be switched to OBE interrupt request. There is no relative between IBF0 interrupt request and these two bits. IBF0 interrupt IBF1 interrupt IBF2 interrupt IBF3 interrupt IBF0 IBF1 IBF2 IBF3 IBF0 OBE IBF2 IBF3 IBF0 IBF1 OBE IBF3 IBF0 IBF1 IBF2 OBE Interrupt 0 , 0 0 , 1 1 , 0 1 , 1b7, b6 Nothing is assigned. Cannot be written. The value is "0" in reading. 0 00 00 0 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines ISA control register 1 Bit name FunctionBit symbol W R Symbol Address When reset DBBCON1 02C9 16 000000002 OBF0SEL OBF0 output selection bit 0 : OBF00 enable 1 : OBF01 enable 0 : P40 as GPIO 1 : P40 as OBF00 output 0 : P43 as GPIO 1 : P43 as OBF01 output 0 : P44 as GPIO 1 : P44 as OBF1 output OBF 00 output enable bit OBF 01 output enable bit OBF 1 output enable bit OBF 00EN OBF 01EN OBF 1EN b7 b6 b5 b4 b3 b2 b1 b0 OBF 2EN OBF 3EN OBF 2 output enable bit OBF 3 output enable bit 0 : P45 as GPIO 1 : P45 as OBF2 output 0 : P46 as GPIO 1 : P46 as OBF3 output Nothing is assigned. Cannot be written. The value is "0" in reading.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 151 Rev.1.0 Fig.GF-4 Data bus buffer status register Data bus buffer status register Bit name FunctionBit symbol W R Symbol Address When reset DBBSTS0 02C1 16 000000002 DBBSTS1 02C3 16 000000002 DBBSTS2 02C5 16 000000002 DBBSTS3 02C7 16 000000002 OBF Output buffer full flag 0 : Buffer empty 1 : Buffer full 0 : Buffer empty 1 : Buffer full This flag is indication the A2 status of the 16 bit slave address when IBF flag is set Input buffer full flag User definable flag XA2 flag IBF XA2 b7 b6 b5 b4 b3 b2 b1 b0 User definable flag This flag can be freely defined by user This flag can be freely defined by user

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 152 Rev.1.0 Fig.GF-5 LPC related registers LPC i address register L (i=1,2,3) (Note2) Symbol Address When reset LPC1ADL 02D0 16 000000002 LPC2ADL 02D2 16 000000002 LPC3ADL 02D4 16 000000002 b7 b6 b5 b4 b3 b2 b1 b0 LPC i address register H (i=1,2,3) b7 b6 b5 b4 b3 b2 b1 b0 Note1: Always returns “0” when read, even if writing “1” to this bit. Note2: Do not set the same 16 bits slave address in each channel. Symbol Address When reset LPC1ADH 02D1 16 000000002 LPC2ADH 02D3 16 000000002 LPC3ADH 02D5 16 000000002 Bit name Bit symbol LPCSAD0 Slave address0 Slave address1 Slave address2 (Note1) Slave address3 Slave address4 Slave address5 Slave address6 Slave address7 LPCSAD1 LPCSAD2 LPCSAD3 LPCSAD4 LPCSAD5 LPCSAD6 LPCSAD7 W R LPCSAD8 Slave address8 Slave address9 Slave address10 Slave address11 Slave address12 Slave address13 Slave address14 Slave address15 LPCSAD9 LPCSAD10 LPCSAD11 LPCSAD12 LPCSAD13 LPCSAD14 LPCSAD15 W RBit nameBit symbol

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 153 Rev.1.0 Fig.GF-6 LPC control register LPC control register Bit name Bit symbol Symbol Address When reset LPCCON 02D6 16 000000002 SYNCSEL0 b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Function W R LPC bus buffer 0 enable bit LPC bus buffer 1 enable bit LPC bus buffer 2 enable bit LPC bus buffer 3 enable bit LPCEN0 LPCEN1 LPCEN2 LPCEN3 0 : P30 - P36 as GPIO 1 : LPC bus buffer enable LPC interface enable bitLPCBEN LPC software reset bitLPCSR 0 : LPC bus buffer 2 disable 1 : LPC bus buffer 2 enable 0 : LPC bus buffer 3 disable 1 : LPC bus buffer 3 enable 0 : LPC bus buffer 0 disable 1 : LPC bus buffer 0 enable 0 : LPC bus buffer 1 disable 1 : LPC bus buffer 1 enable 0 : The release of reset (Note) 1 : Reset Note: For LPC software reset, the bit will automatically return to “0” after writing “1”. SYNCSEL1 SYNC output selection bits 0 0: OK 0 1: Long & OK 1 0: Err 1 1: Long & Err b1 b0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 154 Rev.1.0 Basic operation of LPC bus interface The status transition of LPC bus interface is shown in Figure GF-7. Setting steps for using LPC bus interface is explained below.

• Setting bit3 (LPC interface enable bit) of LPC control register(02D6 16 ) to "1"
• Choosing which LPC bus buffer channel will be used
• Setting "1" to bits 4-7 (LPC bus buffer 0-3 enable bit) of LPC control register (02D616 ).
• The 16-bit slave address of LPC bus buffer channel is defined by writing 16-bit slave address to LPC 1-3 address registers (02D016 - 02D516 ). If channel 1-3 LPC bus buffer is chosen, set the address to the corre- sponding address register.
• Selecting IBF/ OBE interrupt in ISA control register0 (02C8 16 )
• Selecting OBF output port in ISA control register1 (02C916 ) <1> Example of I/O writing cycle from HOST Writing timing is shown in Figure GF-8. The basic communication cycles of LPC I/O protocol are 13 cycles. The data of LAD[3:0] will be read by the rising edge of LCLK. Communication will start from LFRAME falling edge.
• 1st cycle : When LFRAME is "Low", sending "00002 " to LAD[3:0] for communication start frame detecting.
• 2nd cycle : When LFRAME is "High", sending "001X2 " to LAD[3:0] for write frame detecting.
• From 3rd cycle to 6th cycle: These four cycles are detecting for 16 bits slave address. 3rd cycle: The slave address which is from host is written to slave address register [15:12] through LAD[3:0] 4th cycle: The slave address which is from host is written to slave address register [11:8] through LAD[3:0] 5th cycle: The slave address which is from host is written to slave address register [7:4] through LAD[3:0] 6th cycle: The slave address which is from host is written to slave address register [3:0] through LAD[3:0]
• 7th and 8th cycles are used for one data byte transfer. 7th cycle: The data which is from host is written to input data buffer[3:0] through LAD[3:0] 8th cycle: The data which is from host is written to input data buffer[7:4] through LAD[3:0]
• 9th and 10thcycles are for changing the communication direction from host→ slave to slave→ host 9th cycle: Host outputs "11112 " to LAD[3:0] 10thcycle: The LAD[3:0] will be set to Hi-Z by HOST to switch the communication direction.
• 11th cycle: The "00002 " (SYNC OK) is output to LAD[3:0] for acknowledge.
• 12th cycle: The "11112 " is output to LAD[3:0]. The XA2 and IBF flag are set. IBF interrupt signal is generated.
• 13th cycle: The LAD[3:0] will be set to Hi-Z by slave to switch the communication direction. During the host write period, the bit2 (A2) status of 16 bits slave address will be latched to XA2 flag. When 8 bits data from input data buffer are read out by slave CPU, the IBF flag will be cleared simultaneously.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 155 Rev.1.0 <2> Example for I/O reading cycle from HOST Reading timing is shown in Figure GF-9. The basic communication cycles of LPC I/O protocol are 13 cycles. The data of LAD[3:0] will be read by the rising edge of LCLK. Communication will start from LFRAME falling edge.

• 1st cycle: When LFRAME is "Low", sending "00002 " to LAD[3:0] for communication start detecting.
• 2ndcycle: When LFRAME is "High", the host send "000X2 " on LAD[3:0] to inform the cycle type as I/O read.
• From 3rd cycle to 6thcycle: These four cycles are detecting for 16 bits slave address. 3rdcycle: The slave address which is from host is written to slave address register [15:12] throughLAD[3:0] 4thcycle: The slave address which is from host is written to slave address register [11:8] throughLAD[3:0] 5thcycle: The slave address which is from host is written to slave address register [7:4] throughLAD[3:0] 6thcycle: The slave address which is from host is written to slave address register [3:0] throughLAD[3:0]
• 7th and 8thcycles are used for changing the communication direction from host→ slave to slave→ host 7thcycle: Host is output "11112 " to LAD[3:0] 8thcycle: The LAD[3:0] will be set to Hi-Z by HOST to switch the communication direction.
• 9thcycle : The "00002 " (SYNC OK) is output to LAD[3:0] for acknowledge.
• 10th and 11thcycles are for output 8 bits data from output data buffer or output 8 bits data from status register. 10thcycle: Sending output data buffer [3:0] to LAD[3:0] or sending data of status register [3:0] to LAD[3:0] 11thcycle: Sending output data buffer [7:4] to LAD[3:0] or sending data of status register [7:4] to LAD[3:0].
• 12thcycle: The "11112 " is output to LAD[3:0]. The OBF flag is cleared and OBE interrupt signal is generated.
• 13thcycle: The LAD[3:0] will be set to Hi-Z by slave to switch the communication direction. OBF flag will be set when 8 bits data are written to output data buffer by slave CPU.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 156 Rev.1.0 Fig.GF-7 Data and Command write timing figure Note1 : LAD0 to LAD3 pins remain Hi-Z after transfer completion LCLK LFRAME LAD [3:0] Input buffer XA2 flag IBF flag LCLK LFRAME LAD [3:0] START WR 16 BIT ADDRESS DATA TAR SYNC TAR START WR TAR SYNC TAR Driven by the HOST Driven by the SLAVE (Note1) (Note1)

16 BIT ADDRESS DATA

Data WR (I/O write cycle) (I/O write cycle) Driven by the HOST Driven by the SLAVE

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 157 Rev.1.0 Fig.GF-8 Data and Status read timing figure Note1 : LAD0 to LAD3 pins become Hi-Z after transfer completion. Note2 : OBF flag does not change. Data RD LCLK LFRAME LAD [3:0] Output data bus buffer OBF flag START RD 16 BIT ADDRESS TAR SYNC DATA TAR Status RD LCLK LFRAME LAD [3:0] OBF flag START RD 16 BIT ADDRESS TAR SYNC DATA TAR (Note1) (Note2) (Note1) (I/O read cycle) Driven by the HOST Driven by the SLAVE (I/O read cycle) Driven by the HOST Driven by the SLAVE

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 158 Rev.1.0 Table GF-2 Function explanation of the control input and output pins in LPC bus interface functionP3 0/LAD LAD I/O LPC bus used for transmitting and receiving address,command and data between Host CPU and peripheral devices. 1/LAD LAD I/O 2/LAD LAD I/O 3/LAD LAD I/O 4/LFRAME LFRAME I It is used for indicating the start of LPC cycle and termination of abnormal communication cycle. 0/OBF OBF O Status output signal.OBF output. 3/OBF OBF O 4/OBF OBF O 5/OBF OBF O 6/OBF OBF O I LPC synchronous clock signal. 5/LRESET LRESET I LPC reset signal. LPC bus interface function is reset. Pin name Name LPC interfaceenable bit OBF outputenable bit OBF outputenable bit OBF outputenable bit OBF outputenable bit OBF outputenable bit OBF outputenable bit HOST EN control bit Input/Output Function 6/LCLK LCLK Status output signal.OBF output. Status output signal.OBF 1 output. Status output signal.OBF 2 output. Status output signal.OBF 3 output. 02D6 Bit 3 02C9 Bit 0 02C9 Bit 1 02C9 Bit 2 02C9 Bit 3 02C9 Bit 4 02C9 Bit 5 02C9 Bit 6

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 159 Rev.1.0 Table GF-3 Conditions of LPC bus interface function induced by LRESET input Pin name / Internal register P30/LAD0 P31/LAD1 P32/LAD2 P33/LAD3 P34/LFRAME P35/LRESET P36/LCLK P40/OBF00 P43/OBF01 P44/OBF1 P45/OBF2 P46/OBF3 P42/GateA20 Input data bus buffer Output data bus buffer U flag 7,6,5,4,2 XA 2 flag IBF flag OBF flag LPCADH/L LPCCON GA 20 circuit LRESET= “H ” LPC bus interface function(function is select) LRESET= “L” I/O port I/O port LPC bus interface function I/O port unstable It can't be written by slave side. It can be written and read by slave side. Initialization to "0" Initialization to "0" Initialization to "0" It can be written and read by slave side. It can be written and read by slave side. Initialization Note There is possibility to generate IBF interrupt request. There is possibility to generate OBE interrupt request. LRESET="L". A spike pluse may be output to the port when the port is already set to L output port and OBF signal is output to the port just before LRESET is set to L. Pin Internal register

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 160 Rev.1.0 GateA 20 output function The GateA20 pin (port P42) can be controlled by LPC interface function channel 0 in hardware. Hardware GateA20 is sharing with P42 pin. Setting "1" to bit 0 of GateA20 control reigsiter enables the hard- ware GateA20 function. The default value of hardware GateA20 is "1". The GateA20 control register is shown in Fig.GF-9. When the host CPU writes "D1" command to address 006416, and then writes data to address 006016 in succession, the value of bit 1 of the data will be output to GateA20 pin. The timing is shown in Fig.GF-10. The GateA20 operation sequences are shown in Fig.GF-11, Fig.GF-12. As shown in the figures, there is no change in input buffer full flag(IBF0) and no input buffer full(IBF) interrupt request, but the input data bus buffer and XA2 flag are changed in these sequences. The value of the GateA 20 output pin will be held till the data next to D1 command is written in. P42 becomes I/O port and the the value of GateA20 becomes "0" when LRESET input is "L". GateA20 will be initialized even if the sequence is executed. However, the GateA20 enable bit will not be changed and GateA20 output pin will be resumed after the LRESET input becomes "H". Fig.GF-9 GateA20 control register GateA20 control register Bit name FunctionBit Symbol W R Symbol Address Reset GA20CON 002CA 16 0016 GA 20EN GateA20 enable bit 0 : P42 as GPIO 1 : Hardware GateA20 function enable Nothing is assigned. Meanless in writing. "0" in reading. b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Reserved bit Must be set to "0" Fig.GF-10 GateA20 output timing LCLK LFRAME LAD (3:0) GateA20 pin START WRITE 16-bit address DATA TAR SYNC TAR Previous value The value of bit 1 of the data

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 161 Rev.1.0 Fig.GF-11 GateA20 operation sequence (1) Sequence 2 (basic operation 2) Yes Write data other than FF and D1 to 0064 Write data to 006016 Sequence 1 (basic operation 1) Bit 1 value of the dataPrevious value No GateA20 pin IBF0 flag refresh IBF interrupt request No LPC communication Write D1 to 006416 Write data to 006016 Write FF to 0064 No No No No No No No No Previous valueGateA20 pin IBF0 flag refresh IBF interrupt request LPC communication Yes Bit 1 value of the data Write D1 to 006416 Write data to 0060 Sequence 3 (basic operation 3) Bit 1 value of the dataPrevious value No GateA20 pin IBF0 flag refresh IBF interrupt request No LPC communication Write D1 to 006416 Write data to 006016 No No Yes Yes

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 162 Rev.1.0 Fig.GF-12 GateA20 operation sequence (2) Sequence 4 (re-trigger) GateA20 pin IBF0 flag refresh IBF interrupt request LPC communication Write D1 to 006416 Write D1 to 006416 Write data to 006016 Previous value Bit 1 value of the data No No No No No No Sequence 5 (cancel operation) GateA20 pin IBF0 flag refresh IBF interrupt request LPC communication Write D1 to 006416 Write data other than D1 to 0064 Previous value No No Yes Yes Sequence 6 (continuance operation) GateA20 pin IBF0 flag refresh IBF interrupt request LPC communication The value of bit 1 of data 2 Write D1 to 006416 Write data1 to 006016 Write D1 to 006416 Write data2 to 0060 Previous value No No No No No No No No Bit 1 value of the data

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 163 Rev.1.0 Serial Interrupt Output The serial interrupt output is the circuit that outputs the interrupt request to the host with serial interrupt data format. Tab.SI-1 shows the specification of serial interrupt output. Item The factors of serial interrupt The number of frame Operation clock Clock restart Clock stop inhibition OBF sync enable Specification The numbers of serial interrupt requests (numbers of channels) that can output simul- taneously are 5 factors. Each interrupt factor of each channel is explained as follows.

• Channel 0 ➀ By setting "1" to IRQi request bit (bit 5, 6 i=1,12) of IRQ request register 0, the interrupt request can be generated. ➁ Synchronized with the rising edge of OBF00 and OBF01 that are the host bus inter- face internal signals, the serial interrupt request can be generated.
• Channel 1-3 ➀ By setting "1" to IRQ request bit (bit 5) of IRQ request register 1-3, the interrupt request can be generated. ➁ Synchronized with the rising edge of OBF1-3 that are the host bus interface internal signals, the serial interrupt request can be generated.
• Channel 4 By setting "1" to IRQ request bit (bit 5) of IRQ request register 4, the interrupt request can be generated.
• Channel 0 ➀ Setting the IRQ1 request bit (bit 5) of IRQ request register0 to “1” or detecting the rising edge of OBF00, which is the host bus interface internal signal, selects Frame 1. ➁ Setting the IRQ12 request bit (bit 6) of IRQ request register0 to “1” or detecting the rising edge of OBF01, which is the host bus interface internal signal, selects Frame 12.
• Channel 1-4 Selecting the frame select bit (bit 0-4) of IRQ request register1-4 selects Frame 1-15 or extend Frame 0-10. The operation synchronized with LCLK (Max. 33MHz). (Note) Setting the clock restart enable bit (bit 6) of serial interrupt control register0 to “1” requests the clock restart if the clock has stopped or slowed down in serial interrupt output. Setting the clock stop inhibition bit (bit 5) of serial interrupt control register0 to “1” requests the inhibition of clock stop if the clock tends to stop or slow down in serial interrupt output. Setting the OBF00, OBF01, OBF1-3 sync enable bit (bit 0-4) of serial interrupt con- trol register0 to “1” enables the OBF synchronization. Table.SI-1 Specifications of serial interrupt output Note: To enable LCLK, it is necessary to enable the LPC bus interface function.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 164 Rev.1.0 Fig.SI-1 Serial interrupt block chart Internal data bus Serial interrupt control register0 (address:02B016 ) b7 b6 b5 b4 b3 b2 b1 b0 IRQ request register0 (address:02B216 ) b7 b6 b5 b4 b3 b2 b1 b0 IRQ request register1 - 4 (address:02B316 , 02B416 , 02B516 ,02B616) b7 b6 b5 b4 b3 b2 b1 b0 Reset selection LCLK IRQ request 0 - 4 IRQ request clear Frame number (CH0 – CH4) Serial interrupt request Control circuit Serial interrupt output Control circuit Clock monitor/ Control circuit IRQ frame number 1 - 4 OBF sync enable Clock stop inhibiting enable & clock restart enable Serial interrupt enable OBF00,OBF01, OBF1 – OBF3 Clock operation Status & finish acknowledge Clock restart request & start frame start request PRST CLKRUN SERIRQ LRESET b7 b6 b5 b4 b3 b2 b1 b0 Serial interrupt control register1(address: 02B116 ) Internal data bus IRQ request 00 ,01 Port control section IRQ request 1 - 4 IRQ request 0 - 4Internal signals

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 165 Rev.1.0 Fig.SI-2 Configuration of IRQ request register0 (1) Register explanation Fig.SI-2 shows the configuration of IRQ request register0, Fig.SI-3 shows the configuration of IRQ request register1-4, Fig.SI-4, SI-5 show the configurations of serial interrupt control regis- ter0,1 respectively. G IRQ request register0 IRQR0 The serial interrupt request of Channel 0 is set by software.

• IRQ1 request bit IR0 Setting the bit to “1” generates the serial interrupt request (Frame 1). By setting the OBF00 sync enable bit (bit 0) of the serial interrupt control register0 to “1”, the value of IR0 is the same as that of OBF00, which is the host bus interface internal signal. When the internal signal OBF00 is "1", the serial interrupt is generated. IR0 is cleared to "0" by writing "0" in software. IR0 can not be cleared to "0" by software when the internal signal OBF00 is "1" if OBF00 sync enable bit is set to "1".
• IRQ12 request bit IR1 Setting the bit to “1” generates the serial interrupt request (Frame 12). By setting the OBF01 sync enable bit (bit 1) of the serial interrupt control register0 to “1”, the value of IR1 is the same with that of OBF01, which is the host bus interface internal signal. When the internal signal OBF01 is "1", the serial interrupt is generated. IR1 is cleared to "0" by writing "0" in software. IR1 can not be cleared to "0" by software when the internal signal OBF01 is "1" if OBF01 sync enable bit is set to "1". IRQ request register0 Bit name FunctionBit symbol W R Symbol: IRQR0 Address: 02B2 16 When reset: 0016 0: No IRQ1 request 1: IRQ1 request 0: No IRQ12 request 1: IRQ12 request IRQ1 request bit IRQ12 request bit IR0 IR1 b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Nothing is located. Meaningless in writing, “0” in reading. Nothing is located. Meaningless in writing, “0” in reading.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 166 Rev.1.0 Fig.SI-3 Configuration of IRQ request register1-4 G IRQ request register i IRQRi (i=1-4) The serial interrupt request of Channel 1-4 is set by software, or asserting frame is selected.

• IRQ request bit IR Setting the bit to “1” generates the serial interrupt request. By setting the OBFj sync enable bit (bit2-4, j=1-3) of the serial interrupt control register0 to “1”, the value of IR is the same as that of OBFj, which is the host bus interface internal signal. When the internal signal OBFj is "1", the serial interrupt is generated. IR is cleared to "0" by writing "0" in software. IR can not be cleared to "0" by software when the internal signal OBFj is "1" if OBFj sync enable bit is set to "1". G IRQ select bit IS0-4 The asserting frame is selected. IRQ request register1-4 Symbol Address When reset IRQR1 02B3 16 0016 IRQR2 02B4 16 0016 IRQR3 02B5 16 00 16 IRQR4 02B6 16 0016 Bit name Function Bit symbol W R IS0 Frame select bit IS1 IS2 IS3 IS4 b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines IRQ request bit 0: No IRQ request 1: IRQ request IR Nothing is located. Meaningless in writing, “0” in reading. b4b3b2b1b0 IRQ Frame 0 0 0 0 0 : No SERIRQ output 0 0 0 0 1 : Frame 1 0 0 0 1 0 : Frame 2 0 0 0 1 1 : Frame 3 0 0 1 0 0 : Frame 4 0 0 1 0 1 : Frame 5 0 0 1 1 0 : Frame 6 0 0 1 1 1 : Frame 7 0 1 0 0 0 : Frame 8 0 1 0 0 1 : Frame 9 0 1 0 1 0 : Frame 10 0 1 0 1 1 : Frame 11 0 1 1 0 0 : Frame 12 0 1 1 0 1 : Frame 13 0 1 1 1 0 : Frame 14 0 1 1 1 1 : Frame 15 1 0 0 0 0 : Can’t select 1 0 0 0 1 : Can’t select 1 0 0 1 0 : Can’t select 1 0 0 1 1 : Can’t select 1 0 1 0 0 : Can’t select 1 0 1 0 1 : Extend Frame 0 1 0 1 1 0 : Extend Frame 1 1 0 1 1 1 : Extend Frame 2 1 1 0 0 0 : Extend Frame 3 1 1 0 0 1 : Extend Frame 4 1 1 0 1 0 : Extend Frame 5 1 1 0 1 1 : Extend Frame 6 1 1 1 0 0 : Extend Frame 7 1 1 1 0 1 : Extend Frame 8 1 1 1 1 0 : Extend Frame 9 1 1 1 1 1 : Extend Frame 10

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 167 Rev.1.0 G Serial interrupt control register0 SERCON0 The operation condition of serial interrupt is set.

• OBFi sync enable bit SENi (i=00,01,1-3) By setting the bit to “1”, the rising edge of OBFi output to host bus interface generates the serial interrupt request synchronously.
• Clock stop inhibition bit SUPEN Setting the bit to “1” will request the inhibition of clock if the clock tends to stop or slow down in serial interrupt request.
• Clock restart enable bit RUNEN Setting the bit to “1” requests the clock restart during the clock stop or clock slow down in serial interrupt request.
• Serial interrupt enable bit IRQEN 0: SERIRQ, PRST, CLKRUN are I/O ports. 1: SERIRQ, PRST, CLKRUN are serial interrupt function ports. Fig.SI-4 Configuration of serial interrupt control register0 Note 1 : By setting this bit to “1”, P43, P45 and P46 are selected as SERIRQI/O, PRST input and CLKRUN I/O ports respectively. The output of CLKRUN pin is N channel open drain type. P45/PRST functions as GPIO port even when the bit is "1" if bit 1 of serial interrupt control register 1 (Address 02B116) is "1". Serial interrupt control register0 SEN00 OBF00 sync enable bit 0: No clock restart 1: Clock restart 0: Serial interrupt inhibition 1: Serial interrupt enable 0: Sync inhibition 1: Sync enable 0: Sync inhibition 1: Sync enable 0: Sync inhibition 1: Sync enable 0: Sync inhibition 1: Sync enable 0: Sync inhibition 1: Sync enable OBF01 sync enable bit OBF1 sync enable bit OBF2 sync enable bit OBF3 sync enable bit Clock stop inhibition bit0: Stop control operation 1: No stop control operation Clock restart enable bit Serial interrupt enable bit SEN01 SEN1 SEN2 SEN3 SUPEN RUNEN IRQEN b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Symbol Address When reset SERCON0 02B0 16 00 16 Bit name FunctionBit symbol W R (Note 1)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 168 Rev.1.0 Fig.SI-5 Configuration of serial interrupt control register1 G Serial interrupt control register1 SERCON1 The register is for setting the pins of serial interrupt.

• Reset selection bit RSEL 0: The input of PRST is the reset signal. 1: The input of LRESET is the reset signal. (Note1) Note 1: The PRST pin becomes I/O port if setting the bit to “1”.
• OBF0 mergence function By setting the bit to “1”, the signal, which is logically OR by OBF00 and OBF01 signals from LPC bus interface, will output to IRQ1 and IRQ12 of serial interrupt circuit. Fig.SI-6 shows the selection circuit controlled by the bit. With the function, the IRQ1 and IRQ12 request bits can be cleared simultaneously by H/W at the read of output data buffer from system if both IRQ1 and IRQ12 request bits are set in the case that IRQ1 request bit (or IRQ12 request bit) is set after that of IRQ12 (or IRQ1) because of the overwrite to the output data buffer. Serial interrupt control register 1 Symbol Address When reset SERCON1 02B1 16 0016 0 : Select PRST pin. 1 : Select LRESET pin. Reset selection bitRSEL b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Nothing is allocated. Meaningless in writing. “0” in reading. Reserved bit Must be “0”. Bit symbol FunctionBit symbol W R Reserved bit Must be “0”. OBF0MRG OBF0 mergence bit 0 : OBF00 and OBF01 are independent. 1 : OBF00 and OBF01 are merged (logical OR).

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 169 Rev.1.0 Fig.SI-6 The selection circuit controlled by OBF0MRG OBF00 from LPC bus interface To IRQ1 request bit of serial interrupt output OBF0MRG OBF01 from LPC bus interface To IRQ12 request bit of serial interrupt output “0” “1” “0” “1”

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 170 Rev.1.0 Fig.SI-7 The configuration of serial interrupt control register 2 G Serial interrupt control register2 SERCON2 The polarity of serial interrupt output can be selected by bit 0 to bit 5 of serial interrupt control register 2. When the bit is set to “0”: If there is a request, Hiz-Hiz-Hiz If there is no request, L-H-Hiz When the bit is set to “1”: If there is a request, L-H-Hiz If there is no request, Hiz-Hiz-Hiz Only the default value of bit 4 (serial interrupt polarity bit 3) of serial interrupt control register 2 after reset is “1”. Fig.SI-7 shows the configuration of serial interrupt control register 2. Serial interrupt control register 2 Bit name FunctionBit symbol W R Symbol Address When reset SERCON2 02B7 16 1016 SERSEL00 Serial interrupt polarity selection bit 00 b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Select serial interrupt output polarity of IRQ1 in channel 0. (Note) Serial interrupt polarity selection bit 01 SERSEL01 Serial interrupt polarity selection bit 1 Serial interrupt polarity selection bit 2 Serial interrupt polarity selection bit 3 Serial interrupt polarity selection bit 4 SERSEL1 SERSEL2 SERSEL3 SERSEL4 Nothing is allocated. Meaningless in writing. “0” in reading. Select serial interrupt output polarity of IRQ12 in channel 0. (Note) Select serial interrupt output polarity of IRQ in channel 1. (Note) Select serial interrupt output polarity of IRQ in channel 2. (Note) Select serial interrupt output polarity of IRQ in channel 3. (Note) Select serial interrupt output polarity of IRQ in channel 4. (Note) Note: “0” : If there is a request Hiz-Hiz-Hiz If there is no request L-H-Hiz “1” : If there is a request L-H-Hiz If there is no request Hiz-Hiz-Hiz

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 171 Rev.1.0 (2) The operation of serial interrupt A cycle operation of serial interrupt starts with start frame and finishes with stop frame. There are 2 kinds of operation mode: continuous mode and quiet mode. The next operation mode is judged by monitoring the length of stop frame sent from host side. G The timing of serial interrupt cycle Fig.SI-8 shows an example of basic timing of serial interrupt cycle. ➀ Start frame The start frame will be detected if the SERIRQ remains “L” in 4-8 clock cycles. ➁ IRQ data frame Each IRQ data frame is 3 clock cycles.

• Channel 0-2,4:If the IRQ request bit is "0", then the SERIRQ is driven to “L” during the 1st clock cycle of the corresponding data frame, to “H ” during the 2nd clock cycle, to high impedance during the 3rd clock cycle. If the IRQ request bit is "1", then the SERIRQ is high impedance during all of the 3 clock cycles.
• Channel 3:If the IRQ request bit is "0", then the SERIRQ is high impedance during all of the 3 clock cycles. If the IRQ request bit is "1", then the SERIRQ is driven to “L” during the 1 st clock cycle of the corresponding data frame, to “H ” during the 2nd clock cycle, to high impedance during the 3rd clock cycle. z Stop frame The stop frame will be detected if the SERIRQ remains “L” in 2 or 3 clock cycles. The next opera- tion mode is quiet mode if the length of “L” is 2 clock cycles, the continuous mode mode if the length is 3 clock cycles. Fig.SI-8 Basic timing of serial interrupt cycle Start frame frame 0 frame 1 frame 15 IOCHK Device side Stop frame to the next cycle Device side System side Clock SERIRQ Driver source System side

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 172 Rev.1.0 G Operation mode Fig.SI-9 shows an example of timing of continuous mode, Fig.SI-10 shows that of quiet mode. ➀ Continuous mode After reset, at the rising edge of PRST (or LRESET) or the length of the last stop frame of serial interrupt cycle being 3 clock cycles, it will be the continuous mode. After receiving the start frame (Note 1), the Frame 1, Frame 12 or frames selected in each chan- nel will be asserted. Note 1: If the length of “L” is less than 4 clock cycles or more than 9 clock cycles, the start frame will not be detected and the next start (the falling edge of SERIRQ) is waited. Fig.SI-9 Timing diagram of continuous mode Fig.SI-10 Timing diagram of quiet mode ➁ Quiet mode At clock stop or clock slow down, or the length of the last stop frame of serial interrupt cycle being 2 clock cycles, it will be the quiet mode. In this mode the SERIRQ is driven to “L” in the 1 st clock cycle by device and after the receiving of the rest start frame (Note 1) from host, the IRQ1 Frame , IRQ12 Frame or frames selected in each channel will be asserted. Note 1: If the sum of length of “L” that is driven by the device in the 1 st clock cycle and by the host in the rest clock cycles is within 4-8 clock cycles, the start frame will be detected. If the sum of length of “L” is less than 4 clock cycles or more than 9 clock cycles, the start frame will not be detected and the next start (the falling edge of SERIRQ) is waited. Start frame (Note1) IRQ0 frame IRQ1 frame System side Device side Clock SERIRQ line Driver source IRQ2 frame IRQ3 frame System•SERIRQ output Device•SERIRQ output Note1 . The start frame is set to 4 clock as setting exemple Start frame (Note1) IRQ0 frame IRQ1 frame System side Device side LCLK SERIRQ line Driver source IRQ2 frame IRQ3 frame System•SERIRQ output Device•SERIRQ output Device side Note1 . The start frame is set to 4 clock as setting example

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 173 Rev.1.0 (3) Clock restart/ stop inhibition request Asserting the CLKRUN signal can request to restart or maintain the clock which stops or slows down or request the host to tend to stop or slow down. Fig.SI-11 shows an example of timing of clock restart request, Fig.SI-12 shows an example of timing of clock stop inhibition request. ➀ Clock restart operation Setting the clock restart bit of serial interrupt control register0 to “1” will request the clock restart if the clock has slowed down or stopped at serial interrupt request. Fig.SI-11 Timing diagram of clock restart request Fig.SI-12 Example of timing of clock stop inhibition request ➁ Clock stop inhibition request Setting the clock stop inhibition bit of serial interrupt control register0 to “1” will request the inhibi- tion of clock stop if the clock tends to stop or slow down during all the period of serial interrupt output. LCLK CLKRUN line System•CLKRUN Device•CLKRUN SERIRQ line System•SERIRQ Device•SERIRQ Serial interrupt request Internal Interrupt restart request signal Start frame Restart frame Clock CLKRUN line System•CLKRUN Device•CLKRUN Serial interrupt request Internal Interrupt Inhibition request signal SERIRQ line A cycle of serial interrupt Inhibition request

MULTI-MASTER I 2C-BUS Interface Mitsubishi microcomputers M16C / 6K7 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 174 Rev.1.0 MULTI-MASTER I 2C-BUS INTERFACE The multi-master I2C-BUS interface is a serial communication circuit based on Philips I2C-BUS data transfer format. 2 independ channels, with both arbitration lost detection and a synchronous functions, are built in for the multi-master serial communication. Fig.GC-1 shows a block diagram of the multi-master I2C-BUS inter- face and Table.GC-1 lists the multi-master I2C-BUS interface functions. The multi-master I2C-BUS interface consists of the I2C address register, the I2C data shift register, the I2C clock control register, the I2C control register 1, I2C control register 2, the I2C status register, the I2C start/stop condition control register and other control circuits. Table.GC-1 Multi-master I2C-BUS interface functions *VIIC=I2C system clock Item Function Based on Philips I2C-BUS standard: 10-bit addressing format Format 7-bit addressing format High-speed clock mode Standard clock mode Based on Philips I2C-BUS standard: Master transmission Communication mode Master reception Slave transmission Slave reception SCL clock frequency 16.1kHz to 400kHz (at V IIC = 4MHz)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERMULTI-MASTER I 2C-BUS Interface 175 Rev.1.0 Fig.GC-1 Block diagram of multi-master I2C-BUS interface Noiseelimination circuit Serial data(S DA Datacontrol circuit BB circuit Clockcontrol circuit Noiseelimination circuit Serialclock (S CL ACK ACKBIT FASTMODE CCR4 CCR3 CCR2 CCR1 CCR0 Internal data bud Clock division ALcircuit I2C address register SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW Address comparator I2C data shift register S 0S0D SIS control register I C start/stop condition SIP SSC4 SSC3 SSC2 SSC1 SSC0 I C clock control register S2D Interrupt generating circuit Interrupt request signal (S CL S DA IRQ) STSP SEL I2C Control register 1b7 ICK1 ICK0 SCLM SDAM WIT SIM S3D Interruptgenerating circuit Interrupt request signal(I2CIRQ) b7 MST TRX BB PIN AL AAS AD0 LRB S1 b7 TISS 10BITSAD ALS BC2 BC1 BC0 S1D Bit count ES0 I C status register2 I C control register 0 System clock select circuit ICK1,ICK0=1,0ICK1,ICK0=0,1ICK1,ICK0=0,0 I2C system clock IIC ICK1,ICK0=1,1 ICCK(External clock) Timeout detection circuit I C control register 22 S4D TOSEL TOF TOE

MULTI-MASTER I 2C-BUS Interface Mitsubishi microcomputers M16C / 6K7 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 176 Rev.1.0 I2C Data Shift Register The I2C data shift register (address 032016,033016) is an 8-bit shift register to store receiving data and write transmission data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted by one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the S CL clock, and each time one-bit data is input, the data of this register are shifted by one bit to the left. The timing of storing received data to this register is shown in figure GC-3.The I2C data shift register is in a write enable status only when the I2C-BUS interface enable bit (ES0 bit : bit 3 of address 032316,033316) of the I2C control register 0 is “1”. The bit counter is reset by a write instruction to the I2C data shift register. When both the ES0 bit and the MST bit of the I2C status register (address 032816,033816) are “1”, the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the value of ES0 bit. Fig.GC-2 I2C data shift register Fig.GC-3 The timing of receiving data stored to I2C data shift register Symbol Address When reset S0i(i=0,1) 0320 16,033016 -- b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines I C data shift register2 W R Transmission data /receiving data are stored. In the master transmission mode, the start condition/ stop condition are triggered by writing data to the register (refer to the section on the method to generate the start/stop condition). The transmission/receiving are started synchronized with S CL . Note The write is only enabled when bus interface enable bit (ES0 bit) is "1". Because the register is used both for storing transmission data/receiving data, the transmission data should be written after the receiving data are read out before writing transmission data to this register. Note Function SCL SDA Internal SCL Internal SDA Shift clock tdfil : Noise elimination circuit delay time 1 to 2 VIIC cycle tdfil tdfil tdsft Storing data at shift clock rising edge. tdsf : Shift clock delay time

1 VIIC cycle

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERMULTI-MASTER I 2C-BUS Interface 177 Rev.1.0 I2C Address Register The I2C address register (address 032216,033216) consists of a 7-bit slave address and a read/write bit. In the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the START condition is detected.

• Bit 0: Read/write bit (RBW) This is not used in the 7-bit addressing mode. In the 10-bit addressing mode, the first byte address data to be received are compared with the contents (SAD6 to SAD0 + RBW) of the I 2C address register. The RBW bit is cleared to “0” automatically when the stop condition is detected.
• Bits 1 to 7: Slave address (SAD0–SAD6) These bits store slave addresses. Regardless of the 7-bit addressing mode or the 10-bit addressing mode, the address data transmitted from the master is compared with the contents of these bits. Fig.GC-4 I2C address register Symbol Address When reset S0Di(i=0,1) 0322 16,033216 000000002 b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines I C address register2 Bit name FunctionBit Symbol W R RBW Read/Write bit Slave addressSAD0 SAD1 SAD2 SAD3 SAD4 SAD5 SAD6 This bit is using for comparing with receiving address data in the 10-bit address mode. (Note) For comparing with received address data Note.The RWB bit is cleard to "0" automatically when stop condition is detected

MULTI-MASTER I 2C-BUS Interface Mitsubishi microcomputers M16C / 6K7 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 178 Rev.1.0 I2C Clock Control Register The I2C clock control register 0,1 (address 032416,033416) is used to set ACK control, SCL mode and SCL frequency.

• Bits 0 to 4: SCL frequency control bits (CCR0–CCR4) These bits control the SCL frequency. Refer to Table GC-2.
• Bit 5: SCL mode specification bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to “0”, the standard clock mode is selected. When the bit is set to “1” , the high-speed clock mode is selected. When connecting to the bus with the high-speed mode I2C-BUS standard (maximum 400 kbits/s), set 4 MHz or more to I2C system clock(VIIC).
• Bit 6: ACK bit (ACK BIT) This bit sets the SDA status when an ACK clock is generated. When this bit is set to “0”, the ACK return mode is selected and SDA goes to “L” at the occurrence of an ACK clock. When the bit is set to “1”, the ACK nonreturn mode is selected. The SDA is held in the “H ” status at the occurrence of an ACK clock. However, when the slave address agrees with the address data in the reception of address data at ACK BIT = “0”, the SDA is automatically made “L” (ACK is returned). If there is a disagreement between the slave address and the address data, the SDA is automatically made “H ” (ACK is not returned). *ACK clock: Clock for acknowledgment
• Bit 7: ACK clock bit (ACK) This bit specifies the mode of acknowledgment which responses to the data transferring. When this bit is set to “0”, the no ACK clock mode is selected. In this case, no ACK clock occurs after data transmission. When the bit is set to “1”, the ACK clock mode is selected and the master generates an ACK clock at the comple- tion of each 1-byte data transfer. The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (makes SDA “H ”) and receives the ACK bit generated by the data receiving device. Note:Except for ACK bit (ACKBIT), do not write data into the I2C clock control register during transfer. If data is written during transfer, the I2C clock generator is reset, so that data cannot be transferred normally.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERMULTI-MASTER I 2C-BUS Interface 179 Rev.1.0 Fig.GC-5 I2C clock register I C clock control register Symbol Address When reset S2i(i=0,1) 0324 16,033416 000000002 b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines CCR0 SCL frequency control bits Refer to table.GC-2 CCR1 CCR2 CCR3 CCR4 0 : Standard clock mode 1 : High-speed clock mode 0 : ACK is returned 1 : ACK is not returned 0 : No ACK clock 1 : ACK clock S CL mode specification bit ACK bit ACK clock bit FAST MODE ACK BIT ACK Bit name FunctionBit Symbol W R

MULTI-MASTER I 2C-BUS Interface Mitsubishi microcomputers M16C / 6K7 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 180 Rev.1.0 Notes1:Duty of SCL clock output is 50 %. The duty becomes 35 to 45 % only when the high-speed clock mode is selected and CCR value = 5 (400 kHz, at VIIC = 4 MHz). “H ” duration of the clock fluctuates from –4 to +2 machine cycles in the standard clock mode, and fluctuates from –2 to +2 machine cycles in the high-speed clock mode. In the case of negative fluctuation, the frequency does not increase because “L” duration is extended instead of “H ” duration reduction. These are value when SCL clock synchronization by the synchronous function is not performed. CCR value is the decimal notation value of the SCL frequency control bits CCR4 to CCR0. 2:Each value of SCL frequency exceeds the limit at VIIC = 4 MHz or more. When using these setting value, use VIIC = 4 MHz or less. Refer to I2C system clock selection bits (bit 6,7 of I2C control register 1) on VIIC. 3:The data formula of SCL frequency is described below: VIIC/(8 X CCR value) Standard clock mode VIIC/(4 X CCR value) High-speed clock mode (CCR value ≠ 5) VIIC/(2 X CCR value) High-speed clock mode (CCR value = 5) Do not set 0 to 2 as CCR value regardless of VIIC frequency. Set 100 kHz (max.) in the standard clock mode and 400 kHz (max.) in the high-speed clock mode to the S CL frequency by setting the SCL frequency control bits CCR4 to CCR0. Table.GC-2 Set values of I2C clock control register and SCL frequency Setting value of CCR4 to CCR0 S CL frequency (at VIIC=4MHz, unit : kHz) (Note1) CCR4 CCR3 CCR2 CCR1 CCR0 Standard clock mode High-speed clock mode 0 0 0 0 0 Setting disabled Setting disabled 0 0 0 0 1 Setting disabled Setting disabled 0 0 0 1 0 Setting disabled Setting disabled 0 0 0 1 1 - (Note2) 333 0 0 1 0 0 - (Note2) 250 0 0 1 0 1 100 400 (Note3) 0 0 1 1 0 83.3 166 500 / CCR value 1000 / CCR value (Note3) (Note3) 1 1 1 0 1 17.2 34.5 1 1 1 1 0 16.6 33.3 1 1 1 1 1 16.1 32.3

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERMULTI-MASTER I 2C-BUS Interface 181 Rev.1.0 I2C Control Register 0 The I2C control register 0 (address 032316,033316) of channel 0, 1 controls data communication format.

• Bits 0 to 2: Bit counter (BC0–BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. The I2C interrupt request signal occurs immediately after the number of count specified with these bits (ACK clock is added to the number of count when ACK clock is selected by ACK bit (bit 7 of address 032416,033416)) have been trans- ferred, and BC0 to BC2 are returned to “0002”. Also when a START condition is detected, these bits become “0002” and the address data is always trans- mitted and received in 8 bits.
• Bit 3: I 2C interface enable bit (ES0) This bit enables to use the multi-master I2C-BUS interface. When this bit is set to “0”, the interface is disabled and the SDA and the SCL become high-impedance. When the bit is set to “1”, the interface is enabled. When ES0 = “0”, the following is performed. 1)Set MST = “0”, TRX = “0”, PIN = “1”, BB =“0”, AL = “0”, AAS = “0”, and AD0 = “0”, of I2C status register (Address : 032816, 033816) 2)Writing data to I2C data shift register (Address : 032016, 033016) is inhibited. 3)The TOF bit of I2C control register (Address : 032716,033716) is cleared to “0” 4)I2C system clock (VIIC) is stopped and the interval counter, flags are initialized.
• Bit 4: Data format selection bit (ALS) This bit decides if the recognition of slave address should be processed. When this bit is set to “0”, the addressing format is selected, so that address data will be recognized. The transfer will be processed only when a comparison is matched between the salve address and the address data or a general call is received (refer to the item of bit 1 of I 2C status register: general call detection flag). When this bit is set to “1”, the free data format is selected, so that slave address will not be not recognized.
• Bit 5: Addressing format selection bit (DBIT SAD) This bit selects a slave address specification format. When this bit is set to “0”, the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I 2C address register (address 0323 16,0333 16) are compared with address data. When this bit is set to “1”, the 10-bit addressing format is selected, and all the bits of the I2C address register are compared with address data.
• Bit 6: I2C-BUS interface reset bit (IHR) The bit is used to reset I2C-BUS interface circuit in the case that the abnormal communication occurs. When the ES0 bit is“1” (I2C-BUS interface is enabled), writing“1” to the IHR bit makes a H/W reset. Flags are processed as follows: 1)Set MST = “0”, TRX = “0”, PIN = “1”, BB =“0”, AL = “0”, AAS = “0”, and AD0 = “0”, of I 2C status register (Address : 032816, 033816) 2)The TOF bit of I2C control register (Address : 032716,033716) is cleared to “0” 3)The interval counter, flags are initialized. After writing“1” to IHR bit, the circuit reset processing will be finished in Max. 2.5 VIIC cycles and IHR bit will be automatically cleared to “0”. Fig.GC-6 shows the reset timing.
• Bit 7: I2C-BUS interface pin input level selection bit This bit selects the input level of the SCL and SDA pins of the multi-master I2C-BUS interface. When this bit is set to“1” the P60,P61,P62,P63 will become SMBus input level.

MULTI-MASTER I 2C-BUS Interface Mitsubishi microcomputers M16C / 6K7 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 182 Rev.1.0 Fig.GC-6 The timing of reset to the I2C-BUS interface circuit Fig.GC-7 I2C control register b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines I C control register 0 Symbol Address When reset S1Di(i=0,1) 0323 16,033316 000000002 BC0 Bit counter (Number of transmitting/ receiving bits) b2 b1 b0 (Note) 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 BC1 BC2 0 : Disable 1 : Enable 0 : Addressing format 1 : Free data formatData format selection bit ES0 ALS Addressing format selection bit 0 : 7-bit addressing format 1 : 10-bit addressing format DBIT SAD I C-BUS interface enable bit TISS I C-BUS interface pin input level selection bit Note In the following status, the bit counter will be cleared automatically

• Start condition/stop condition is detected
• Right after the completion of 1 byte data transmission
• Right after the completion of 1 byte data receiving 0 : I C-BUS input 1 : SMBUS input IHR I C-BUS interface reset bit0 : Release of reset (auto) 1 : Reset Bit name FunctionBit Symbol W R

2.5 VIIC cycles

The signal of writing "1" to IHR bit IHR bit The reset signal to I C-BUS interface circuit2

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERMULTI-MASTER I 2C-BUS Interface 183 Rev.1.0 I2C Status Register The I2C status register (address 032816,033816) controls the I2C-BUS interface status. The low-order 6 bits are read-only if it is used for status check. The high-order 2 bits can be both read and written. Regarding to the function of writing to the low-order 6 bits, refer to the the method of start condition/stop condition genera- tion described later.

• Bit 0: Last receive bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to “0”. If ACK is not returned, this bit is set to “1”. Except in the ACK mode, the last bit value of received data is input. The bit will be “0” by executing a write instruction to the I 2C data shift register (address 032016,033016).
• Bit 1: General call detecting flag (AD0) When the ALS bit is “0”, this bit is set to “1” when a general call* whose address data is all “0” is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to “0” by detecting the STOP condition, START condition, or ES0 is“0”, or reset. *General call: The master transmits the general call address “00 16” to all slaves.
• Bit 2: Slave address comparison flag (AAS) This flag indicates a comparison result of address data when the ALS bit is “0”. 1)In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in one of the following conditions:
• The address data, which following the start conduction, is same with upper bits data of I2C address register(Address 0032216,033216)
• A general call is received. 2)In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to “1” with the following condition:
• When the address data is compared with the I2C address register (8 bits consisting of slave address and RBW bit), the first bytes agree. 3)This bit is set to “0” by executing a write instruction to the I2C data shift register (address 032016, 033016) when ES0 is set to “1”. The bit is also set to “0” when ES0 is set to “0” or when reset.
• Bit 3: Arbitration lost* detecting flag (AL) In the master transmission mode, when the SDA is made “L” by any other device, arbitration is judged to have been lost, so that this bit is set to “1”. At the same time, the TRX bit is set to “0”. Immediately after transmis- sion of the byte whose arbitration was lost is completed, the MST bit is set to “0”. The arbitration lost can be detected only in the master transmission mode. When arbitration is lost during slave address transmission, the TRX bit is set to “0” and the reception mode is set. Consequently, it becomes possible to detect the agreement between its own slave address and address data transmitted by another master device. The bit is cleared to “0” if writing to I 2C data shift register (address 032016, 033016) when ES0 is “1”. The bit is also cleared to “0” when ES0 is set to “0” or when reset. *Arbitration lost: The status in which communication as a master is disabled.

MULTI-MASTER I 2C-BUS Interface Mitsubishi microcomputers M16C / 6K7 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 184 Rev.1.0

• Bit 4: I2C-BUS interface interrupt request bit (PIN) This bit generates an interrupt request signal. After each byte data is transmitted, the PIN bit changes from “1” to “0”. At the same time, an I2C interrupt request signal occurs to the CPU. The PIN bit is set to “0” synchronized with the falling edge of the last internal transmitting clock (including the ACK clock) and an interrupt request signal occurs synchronized with the falling edge of the PIN bit. When the PIN bit is “0”, the S CL is kept in the “0” state and clock generation is disabled. In the ACK clock enable mode, if WIT bit (bit 1 of I2C control register 1) is set to “1”, synchronized with the falling edge of last bit clock and ACK clock, PIN bit becomes to “0” and I2C interrupt request is generated (Refer to the description on bit 1 of I2C control register 1: the data reception completion interrupt enable bit). Fig.GC-9 shows the timing of I2C interrupt request generation. The bit is read-only, the value should be “0” in writing. The PIN bit is set to “0” in one of the following condition:
• Executing a write instruction to the I2C data shift register (address 032016,033016).
• Executing a write instruction to the I2C clock control register (Address : 032416,033416) (only when WIT is “1” and internal WAIT flag is “1”)
• When the ES0 bit is “0”
• At reset The PIN bit is set to “0” in one of the following condition:
• Immediately after the completion of 1-byte data transmission (including arbitration lost is detected)
• Immediately after the completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately after the completion of slave address agreement or general call address reception
• In the slave reception mode, with ALS = “1” and immediately after the completion of address data reception
• Bit 5: Bus busy flag (BB) This bit indicates the in-use status the bus system. When this bit is set to “0”, bus system is not busy and a START condition can be generated. The BB flag is set/reset by the SCL , SDA pins input signal regardless of master/slave. This flag is set to “1” by detecting the start condition, and is set to “0” by detecting the stop condition. The condition of the detecting is set by the start/stop condition setting bits (SSC4–SSC0) of the I2C start/stop condition control register (address 032516,033516). When the ES0 bit (bit 3) of the I2C control register (address 032316,033316) is “0” or reset, the BB flag is set to “0”. For the writing function to the BB flag, refer to the sections “START Condition Generating Method” and “STOP Condition Generating Method” described later.
• Bit 6: Communication mode specification bit (transfer direction specification bit: TRX) This bit decides a direction of transfer for data communication. When this bit is “0”, the reception mode is selected and the data from a transmitting device is received. When the bit is “1”, the transmission mode is selected and address data and control data are output onto the S DA synchronized with the clock gener- ated on the SCL . This bit can be set/reset by software or hardware. This bit is set to “1” by hardware in the following condition: In slave mode with ALS = “0”, if the AAS flag is set to “1” after the address data reception and the received ___ R/W bit is “1”. This bit is set to “0” by hardware in one of the following conditions:
• When arbitration lost is detected.
• When a STOP condition is detected.
• When a start condition is prevented by the start condition duplication preventing function (Note).
• When a start condition is detected with MST = “0”.
• When ACK non-return is detected with MST = “0”.
• When ES0 = “0”.
• At reset

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERMULTI-MASTER I 2C-BUS Interface 185 Rev.1.0

• Bit 7: Communication mode specification bit (master/slave specification bit: MST) This bit is used for master/slave specification for data communication. When this bit is “0”, the slave is specified, so that a START condition and a STOP condition generated by the master are received. The data communication is performed synchronized with the clock generated by the master. When this bit is “1”, the master is specified and a START condition and a STOP condition are generated. Additionally, the clocks required for data communication are generated on the S CL . This bit is set to “0” by hardware in one of the following conditions.
• Immediately after the completion of 1-byte data transfer when arbitration lost is detected.
• When a STOP condition is detected.
• Writing a start condition is prevented by the start condition duplication preventing function (Note).
• At reset Note:START condition duplication preventing function The MST, TRX, and BB bits is set to “1” at the same time after confirming that the BB flag is “0” in the procedure of a START condition occurrence. However, when a START condition by an other master device occurs and the BB flag is set to “1” immediately after the contents of the BB flag is confirmed, the START condition duplication prevent- ing function makes the writing to the MST and TRX bits invalid. The duplication preventing function becomes valid from the rising of the BB flag to reception completion of slave address. Refer to the method on the start condition generation in detail.Fig.GC-8 I2C status register Bit name FunctionBit symbol W R Symbol Address When reset S1i(i=0,1) 0328 16,033816 0001000X2 LRB Last receive bit b7 b6 0 0 : Slave receive mode 0 1 : Slave transmit mode 1 0 : Master receive mode 1 1 : Master transmit mode 0 : Last bit = "0" 1 : Last bit = "1" 0 : No general call detected 1 : General call detected 0 : Address disagreement 1 : Address agreement 0 : Not detected 1 : Detected 0 : Interrupt request issued 1 : No interrupt request issued General call detecting flag Slave address comparison flag Arbitration lost detection flag I C-BUS interface interrupt request bit Bus busy flag 0 : Bus free 1 : Bus busy Communication mode specification bits AD0 AAS AL PIN BB TRX MST b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines I C status register2 Note1.This bit is read only if it is used for the status check. How to write this bit, please refer to start condition/stop condition generating method. Note2.The bit can be read and only can be written with "0" by software. Note3.Refer to the method of start condition generation on how to write these bits. How to write this bit, please refer to start condition/stop condition generating method. (Note1) (Note1) (Note1) (Note1) (Note2) (Note1) (Note3) (Note3)

MULTI-MASTER I 2C-BUS Interface Mitsubishi microcomputers M16C / 6K7 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 186 Rev.1.0 Fig.GC-9 Interrupt request signal generating timing SCL PIN flag I2CIRQ

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERMULTI-MASTER I 2C-BUS Interface 187 Rev.1.0 I2C0, I2C1 control register 1 I2C control register 10 ,11 (address 032616,033616) controls I2C-BUS interface circuit.

• Bit 0 : Interrupt enable bit by STOP condition (SIM ) It is possible for I2C-BUS interface to request an interrupt by detecting a STOP condition. If the bit set to “1”, an interrupt from I2C-BUS interface occurs by detecting a STOP condition ( There is no change for PIN flag)
• Bit 1: Interrupt enable bit at the completion of data receiving (WIT) When with-ACK mode (ACK bit = “1”) is specified, by enabling the interrupt at the completion of data receiving (WIT bit = “1”), the I2C interrupt request occurs and PIN bit becomes “0” synchronized with the falling edge of last data bit clock. SCL is fixed “L” and the generation of ACK clock is suppressed. Table GC-3 and Fig.GC-10 show the I2C interrupt request timing and the method of communication restart. After the communication restart, synchronized with the falling edge of ACK clock, PIN bit becomes to “0” and I2C interrupt request occurs. Table.GC-3 Timing of interrupt generation in data receiving The timing of I2C interrupt generation The method of communication restart 1)Synchronized with the falling edge of the The execution of writing to ACKBIT of I2C clock control last data bit clock register. (Do not write to I 2C data shift register. The processing of ACK clock would be incorrect.) 2)Synchronized with the falling edge of the The execution of writing to I2C data shift register ACK clock The state of internal WAIT flag can be read out by reading the WIT bit. The internal WAIT flag is set after writing to I2C data shift register, and it is reset after writing to I2C clock control register. Consequently, which of the timing 1) and 2) of interrupt request occurring can be understood. (See Fig.GC-10)In the cases of transmission and address data reception immediately after the START condition, the interrupt request only occurs at the falling edge of ACK clock regardless of the value of WIT bit and the WAIT flag remains the reset state. Write “0” to WIT bit when in NACK is specified. (ACK bit = “0”)

MULTI-MASTER I 2C-BUS Interface Mitsubishi microcomputers M16C / 6K7 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 188 Rev.1.0

• Bits 2,3 : Port function selection bits PED, PEC When ES0 bit of I2C control register 0 is set to “1”, P61/P63 and P60/P62 function as SCL and SDA respec- tively. However, if PED is set to “1”, SDA functions as output port so as to SCL if PEC is set to “1”. In this case, if “0” or “1” is written to the port register, the data can be output on to the I2C-BUS regardless of the internal SCL /SDA output signals. The functions of SCL /SDA are returned back by setting PED/PEC to “1” again. If the ports are set in input mode, the values on the I2C-BUS can be known by reading the port register regardless of the values of PED and PEC.Table GC-4 shows the port specification. Table.GC-4 Ports specifications Note: f1 = f(XIN) ICCK = External I2C clock
• Bits 4,5 : SDA /SCL logic output value monitor bits SDAM /SCLM It is possible to monitor the logic value of the SDA and SCL output signals from I2C-BUS interface circuit. SDAM can monitor the output logic value of SDA . SCLM can monitor the output logic value of SCL . The bits are read-only. Write “0” if in writing (Writing “1” is reserved)
• Bits 6,7 : I2C system clock selection bits ICK0, ICK1 These bits select the basic operation clock of I2C-BUS interface circuit. It is possible to select I2C system clock VIIC among 1/2,1/4 and 1/8 of main clock f(XIN) and 1/2 of external I2C clock (ICCK) ICK1 ICK0 I 2C system clock 0 0 V IIC = 1 / 2f1 0 1 V IIC = 1 / 4f1 1 0 V IIC = 1 / 8f1 1 1 V IIC = 1 / 2ICCK Pin name P60/P62 P61/P63 ES0 bit ES0 bit PED bit PEC bit P6 port direction register P6 port direction register Function Port I/O function SDA I/O function SDA input function, port output function Function Port I/O function SCL I/O function SCL input function, port output function Table.GC-5 I2C system clock selecting bits

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERMULTI-MASTER I 2C-BUS Interface 189 Rev.1.0 Fig.GC-10 The timing of the interrupt generation at the completion of data reception When in reception mode, ACK bit = "1" WIT bit = "0" 7 clock 8 clock ACK clock 1 clock 1 bit7 bit 8 bit ACK bit SCL SDA ACKBIT PIN flag Internal WAIT flag I2C interrupt request signal The writing signal of I2C data shift register 7 clock 8 clock ACK clock 1 bit7 bit 8 bit SCL SDA ACKBIT PIN flag Internal WAIT flag I2C interrupt request signal The writing signal of I2C data shift register The writing signal of I2C clock control register Note. Do not write to I2C clock control register except bit ACKBIT. When in reception mode, ACK bit = "1" WIT bit = "1" Table.GC-6 Clock setting to the I2C system in different operation mode. Mode The setting content STOP mode The external clock is selcted as the I2C system clock ( ICK1 = 1, ICK0 = 1) and the external I2C clock is supplied by ICCK. WAIT mode The external clock is selcted as the I2C system clock ( ICK1 = 1, ICK0 = 1) and the external I2C clock is supplied by ICCK. Select the peripheral function clock stop bit CMO2 (bit 2 of the system clock control register 0, address : 000616) to the state of not stopping f1,f8,f32 (CMO2 = 0) when in WAIT mode, and then execute the WAIT command. Low power The external clock is selcted as the I2C system clock ( ICK1 = 1, ICK0 = 1) and consumption mode the external I2C clock is supplied by ICCK.

• The address reception in STOP mode /WAIT mode It is possible for I2C-BUS interface to receive address data even in STOP mode or in WAIT mode. However the I2C system clock VIIC should be supplied. Table.GC-6 shows the setting list.

MULTI-MASTER I 2C-BUS Interface Mitsubishi microcomputers M16C / 6K7 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 190 Rev.1.0 Fig.GC-11 I2C control register 1 Symbol Address When reset S3Di(i=0,1) 0326 16,033616 001100002 b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines I C control register 12 Bit name FunctionBit Symbol W R SIM The interrupt enable bit of STOP condition detection 0 : Disable the interrupt of STOP condition detection 1 : Enable the interrupt of STOP condition detection WIT The interrupt enable bit of at the completion of data reception 0 : Disable 1 : Enable When in NACK setting (ACK bit = "0") please write "0" SDAM The logic value monitor bit of SDA output 0 : SDA output logic value = "0" 1 : SDA output logic value = "1" SCLM The logic value monitor bit of SCL output 0 : SCL output logic value = "0" 1 : SCL output logic value = "1" ICK0 ICK1 I C system clock selection bits 2 b7 b6 0 0 : VIIC=1/2f1 0 1 : VIIC=1/4f1 ✼ f1=f(XIN) 1 0 : VIIC=1/8f1 1 1 : VIIC=1/2ICCK ✼ ICCK=External I2C clock PED S DA i/Port function switching bit 0 : SDA I/O pin(enable ES0 = 1) 1 : GPIO(enable ES0 = 1) PEC S CL i/Port function switching bit 0 : SCL I/O pin(enable ES0 = 1) 1 : GPIO(enable ES0 = 1)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERMULTI-MASTER I 2C-BUS Interface 191 Rev.1.0 I2C control register 2 I2C0, 1 control register 2 (address: 032716,033716) control the detection of communication abnormality. In I2C- BUS communication, the data transfer is controlled by the SCL clock signal. The devices will stop in the commu- nication state if SCL stops during transfer. So if the SCL clock stops in “H ” state for a period of time, the I2C-BUS interface circuit can detect the time out and request an I2C interrupt. Please see Fig.GC-12.

• Bit0: Time out detection function enable bit (TOE) The bit enables timeout detection function. By setting this bit to “1”, the I2C interrupt request signal will be generated if the SCL clock stops in “H ” state for a period of time during bus busy (BB flag =“1”). The time of time out detection which is selected by timeout detection time selection bit (TOSEL) with long time mode or short time mode will be calculated by internal counter. When time out is detected, please set “0” to I2C-BUS interface enable bit (ES0) and then process initialization.
• Bit1: Time out detection flag (TOF ) The bit is the flag showing timeout detection status. If the time which is calculated by the internal counter overflows, the time out detection flag (TOF) becomes to “1”, and at the same time the I 2C interrupt request signal is generated.
• Bit2: timeout detection time selection bit (TOSEL) The bit selects timeout detection time from long time and short time mode. If TOSEL = “0”, the long time mode; TOSEL = “1”, the short mode is selected respectively. The long time is up counted by 16 bits counter and the short time is up counted by 14 bits counter based on I 2C system clock (VIIC). Table GC-7 shows examples of the timeout detection time. Fig.GC-12 The timing of timeout detection Table.GC-7 Examples of timeout detection time (Unit: ms) VIIC(MHz) Long time mode Short time mode 4 16.4 4.1 2 32.8 8.2 1 65.6 16.4 1 clock 1 bit SCL SDA BB flag Internal counter start signal Internal counter stop, reset signal Internal counter overflow signal I2C interrupt request signal 2 bit 3 bit 2 clock 3 clock SCL clock stop (“H ”) The time of timeout detection

MULTI-MASTER I 2C-BUS Interface Mitsubishi microcomputers M16C / 6K7 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 192 Rev.1.0 Fig.GC-13 I2C control register 2

• Bit7: STOP condition detection interrupt request bit (SCPIN) The bit monitors the stop condition detection interrupt. The bit becomes to “1” when I2C-BUS interface interrupt is generated by the detecting of STOP condition. Writing “0” clears the bit and “1” can not be written. Bit name FunctionBit symbol W R Symbol Address When reset S4Di(i=0,1) 0327 16,033716 000000002 TOE Timeout detection function enable bit 0 : Disable 1 : Enable 0 : Not detected 1 : Detected Timeout detection flag Timeout detection time selection bit TOF TOSEL b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines I Control register 22 0 : Long time 1 : Short time Nothing on location Can not be written in the value is "0" STOP condition detection interrupt request bit SCPIN 0 : No interrupt request 1 : Interrupt request

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERMULTI-MASTER I 2C-BUS Interface 193 Rev.1.0 I2C START/STOP condition control register I2C START/STOP condition register(address 032516,033516) controls the detection of START/STOP condition.

• Bit0-Bit4: START/STOP condition setting bits (SSC4-SSC0) Because the release time, set up time and hold time of SCL is calculated on the base of I2C system clock(VIIC). the detecting condition changes depending on the oscillation frequency and I2C system clock selecting bits. It is necessary to set the suitable value of START/STOP condition setting bits (SSC4-SSC0) so that obtain the release time, set up time and hold time corresponding to the system clock frequency. Refer to Table GC-11. Do not set odd number or “00000 2” to START/STOP condition setting bits. The recommended setting value to START/STOP condition setting bits (SSC4-SSC0) at each oscillation frequency under standard clock mode is shown in Table. GC-8. The detection of START/STOP condition starts immediately after the setting of ES0=1.
• Bit5: S CL /SDA interrupt pin polarity selection bit (SIP) The interrupt can be generated by detecting the rising edge or the falling edge of SCL pin or SDA pin. SCL /SDA interrupt pin polarity selection bit selects the polarity of SCL pin or SDA pin for interrupt.
• Bit6 : SCL /SDA interrupt pin selection bit (SIS) SCL /SDA interrupt pin selection bit selects either SCL pin or SDA pin as SCL /SDA interrupt enable pin. Note: The SCL /SDA interrupt request may be set when the setting of I2C-BUS interface enable bit ES0 changes. Thus set the interrupt disable before the setting of SCL /SDA interrupt pin polarity selection bit (SIP) and SCL /SDA interrupt selection bit(SIS). After that reset “0” to the interrupt request bit before enabling the interrupt.
• Bit7: START/STOP condition generation selecting bit (STSPSEL) The bit selects the length of set up/hold time when START/STOP condition occurs. The length of set up/hold time is based on the I 2C system clock cycles. Refer to Table GC-9. Set the bit to “1” if I2C system clock frequency is over 4MHz.

MULTI-MASTER I 2C-BUS Interface Mitsubishi microcomputers M16C / 6K7 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 194 Rev.1.0 Fig.GC-14 I2C start/stop condition control register Note: Do not set odd value or “000002” to START/STOP condition setting bits Oscillation I2C system I2C system SSC4-SSC0 S CL release Setup time Hold time f(XIN) (MHz) clock selection clock(MHz) time(cycle) (cycle) (cycle) 10 1 / 2f1 5 XXX11110 6.2 µs (31) 3.2 µs (16) 3.0µs (15) 8 1 / 2f1 4 XXX11010 6.75 µs(27) 3.5 µs (14) 3.25µs(13) XXX11000 6.25 µs(25) 3.25 µs(13) 3.0µs (12) 8 1 / 8f1 1 XXX00100 5.0 µs (5) 3.0 µs (3) 2.0µs (2) 4 1 / 2f1 2 XXX01100 6.5 µs (13) 3.5 µs (7) 3.0µs (6) XXX01010 5.5 µs (11) 3.0 µs (6) 2.5µs (5) 2 1 / 2f1 1 XXX00100 5.0 µs (5) 3.0 µs (3) 2.0µs (2) Table.GC-8 Recommended setting value (SSC4 - SSC0) start/stop condition at each oscillation frequency Bit name FunctionBit Symbol W R Symbol Address When reset S2Di(i=0,1) 0325 16,033516 000110102 SSC0 START/STOP condition setting bits 0 : SDA enable 1 : SCL enable 0 : Setup/hold time short mode 1 : Setup/hold time long mode SCL /SDA interrupt pin polarity selection bit 0 : Active in falling edge 1 : Active in rising edge SCL /SDA interrupt pin selection bit START/STOP condition generation selection bit SSC1 SSC2 SSC3 SSC4 SIP SIS STSP SEL b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines I C start/stop condition control register The setting of the detecting condition of START/STOP condition.Refer to Table GC-8. Note: Prohibit the setting of "00000 2" and odd value

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERMULTI-MASTER I 2C-BUS Interface 195 Rev.1.0 START Condition Generation Method When ES0 bit of the I2C control register is “1” and the BB flag of I2C status register is “0”, writing “1” to the MST, TRX, and BB bits and “0” to the PIN and low-order 4 bits of the I2C status register (address 032816, 033816) simultaneously enters the standby status to generate the start condition. The start condition is gen- erated after writing slave address data to the I2C data shift register. After that, the bit counter becomes “0002” and 1 byte SCL are output. The START condition generation timing is different in the standard clock mode and the high-speed clock mode. Refer to Fig.GC-17 the START condition generation timing diagram, and Table GC-9 the START condition generation timing table. Fig.GC-15 Start condition generation flow chart Interrupt disable BB=0? S1i=E016 S0i=Data Interrupt enable No Yes Start condition standby status setting Start condition trigger occur. ✼ Data=Slave address data

MULTI-MASTER I 2C-BUS Interface Mitsubishi microcomputers M16C / 6K7 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 196 Rev.1.0 Function of protection of duplicate START condition It is necessary to verify that the bus is not in use via BB flag before setting up a START Condition. However, there is a possibility that right after the verification of BB flag, the BB flag becomes to “1” because a START condition is generated by another master device .In this case, the function to interrupt the start condition is built in.When the function starts, it works as follows:

• The prohibition of setting up START condition standby If the START condition standby has been set up, releases it and resets the bits of MST and TRX.
• The prohibition of writing to the I 2C data shift register (The prohibition of generating a START condition trigger)
• If the generation of start condition is interrupted, sets the AL flag. The function of protection of duplicate START condition is valid from the falling edge of S DA of START condition to the completion of slave reception. Fig.GC-16 shows the valid period of the function of protection of duplicate START condition. Fig.GC-16 The valid period of the function of protection of duplicate START condition 1 clock 1 bit SCL SDA BB flag 2 bit 3 bit 2 clock 3 clock 8 bit ACK bit The valid period of protection of duplicate START condition 8 clock ACK clock

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERMULTI-MASTER I 2C-BUS Interface 197 Rev.1.0 STOP Condition Generation Method When the ES0 bit of the I2C control register is “1”, writing “1” to the MST and TRX bits, and “0” to the BB, PIN and low-order bits of the I2C status register simultaneously enters the standby status to generate the stop condition. The stop condition is generated after writing dummy data to the I2C data shift register. The STOP condition generation timing is different in the standard clock mode and the high-speed clock mode. Refer to Fig.GC-18, the STOP condition generation timing diagram, and Table GC-9, the STOP condition generation timing table. Do not write data to I 2C status register and I2C data shift register, before BB flag becomes to “0” after the instruction to generate the stop condition to avoid the influence on generating STOP condition wave- form. Fig.GC-17 Start condition generation timing diagram Fig.GC-18 Stop condition generation timing diagram Table.GC-9 Start/Stop generation timing table Item Start/Stop condition generation Standard clock mode High-speed clock mode selection bit Setup “0” 5.0µs (20 cycle) 2.5 µs (10 cycle) time “1” 13.0µs (52 cycle) 6.5 µs (26 cycle) hold “0” 5.0µs (20 cycle) 2.5 µs (10 cycle) time “1” 13.0µs (52 cycle) 6.5 µs (26 cycle) As mentioned above, Writing “1” to MST and TRX bits. Writing “1” or “0” to BB bit, writing “0” to PIN and low-order 4 bits, simultaneously sets up the START or STOP condition standby. It releases SDA in START condition standby, makes SDA to “L” in STOP condition standby. The signal of writing to data shift register triggers the generation of START/STOP condition. In the case of setting MST, and TRX to “1” but do not want to generate a START/STOP condition. Write “1” to the low-order 4 bits simultaneously. Fig.GC-10 illustrates the function of writing to status register. Note: VIIC = 4MHz Table.GC-10 The function of writing to status register The value of the data writing to status register Function MST TRX BB PIN AL AAS AS0 LRB 1 1 1 0 0 0 0 0Setting up the START condition stand by in master transmission mode 1 1 0 0 0 0 0 0Setting up the STOP condition stand by in master transmission mode 0/1 0/1 - 0 1 1 1 1Setting up the communication mode (refer to the description on I2C status register) I2C data shift register write signal SCL SDA /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Hold time Setup time I2C data shift register write signal SCL SDA /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Setup time /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Hold time

MULTI-MASTER I 2C-BUS Interface Mitsubishi microcomputers M16C / 6K7 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 198 Rev.1.0 START/STOP Condition Detecting Operation The START/STOP condition detection operations are shown in Fig.GC-19, GC-20 and Table.GC-11 The START/STOP condition is set by the START/STOP condition set bit. The START/STOP condition can be de- tected only when the input signal of the S CL and SDA pins satisfy with three conditions: SCL release time, setup time, and hold time (see Table.GC-11). The BB flag is set to “1” by detecting the START condition and is reset to “0” by detecting the STOP condition. The BB flag set/reset timing is different in the standard clock mode and the high-speed clock mode. Refer to Table GC-11, the BB flag set/reset time. Fig.GC-19 Start condition detection timing diagram Fig.GC-20 Stop condition detection timing diagram Table.GC-11 Start/Stop generation timing table Standard clock mode High-speed clock mode SCL release time SSC value + 1 cycle (6.25 µs) 4 cycle (1.0 µs) Setup time SSC value + 1 cycle < 4.0 µs (3.25µs) 2 cycle (0.5 µs) Hold time SSC value cycle < 4.0 µs (3.0µs) 2 cycle (0.5 µs) BB flag set/reset SSC value - 1 +2 cycle (3.375µs) 3.5 cycle (0.875 µs) time 2 Note: Unit : Cycle number of system clock VIIC SSC value is the decimal notation value of the START/STOP condition set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC value. The value in parentheses is an example when the I2C START/STOP condition control register is set to “1816” at VIIC = 4 MHz. BB flag /LiteDiagLines/LiteDiagLines/LiteDiagLines Hold time SCL SCL release time Setup time /LiteDiagLines/LiteDiagLines BB flag set time SDA BB flag /LiteDiagLines/LiteDiagLines/LiteDiagLines Hold time SCL SDA SCL release time Setup time /LiteDiagLines/LiteDiagLines BB flag reset time

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERMULTI-MASTER I 2C-BUS Interface 199 Rev.1.0 Address Data Communication There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats are described below. (1) 7-bit addressing format To adapt the 7-bit addressing format, set the DBIT SAD bit of the I 2C control register 0 (address 032316,033316) to “0”. The first 7-bit address data transmitted from the master is compared with the high- order 7-bit slave address stored in the I2C address register (address 032216,033216). At the time of this comparison, address comparison of the RBW bit of the I2C address register (address 032216,033216) is not performed. For the data transmission format when the 7-bit addressing format is selected, refer to Fig.GC-21 (1) and (2). (2) 10-bit addressing format To adapt the 10-bit addressing format, set the DBIT SAD bit of the I 2C control register 0 (ad- dress032316,033316) to “1”. Also set the WIT bit of I2C control register 1 to “1”. An address comparison is performed between the first-byte address data transmitted from the master and the 8-bit slave address stored in the I 2C address register (address 032216,033216). At the time of this comparison, an address ____ comparison between the RBW bit of the I2C address register (address 032016,033016) and the R/W bit which is the last bit of the address data transmitted from the master is made. In the 10-bit addressing mode, the RBW bit which is the last bit of the address data not only specifies the direction of communication for control data, but also is processed as an address data bit. When the first-byte address data agree with the slave address, the AAS bit of the I 2C status register (address 032816,033816) is set to “1”. After the second-byte address data is stored into the I2C data shift register (address 32016,33016), perform an address comparison between the second-byte data and the slave ad- dress by software. When the address data of the 2 bytes agree with the slave address, write “0” to the ACKBIT to I2C clock control register, to return an ACK. When the address data of the 2 bytes do not agree with the slave address, it does not return an ACK so that makes the finish of the communication by writing “1” to the ACKBIT. If the address data agree with each other, set the RBW bit of the I2C address register ___ (address 032216,033216) to “1” by software. This processing can make the 7-bit slave address and R/W data agree, which are received after a RESTART condition is detected, with the value of the I2C address register (address 032216,033216). For the data transmission format when the 10-bit addressing format is selected, refer to Fig.GC-21(3) and (4).

MULTI-MASTER I 2C-BUS Interface Mitsubishi microcomputers M16C / 6K7 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 200 Rev.1.0 Fig.GC-21 Address data communication format S Slave address R/W A Data A A/A P 7 bits “0” 1 - 8 bits S R/W A A A P A/AR/W R/W “1” (1) A master-transmitter transmits data to a slave-receiver S A A “0” (2) A master-receiver receives data from slave-transmitter A P S A A “0” (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address Sr A A P “1” (4) A master-receiver receives data from slave-transmitter with a 10-bit address S: START condition P : STOP condition A: ACK bit R/W : Read/Write bit Sr : Restart condition R/W Data Data DataSlave address Slave address 1 st 7 bits Slave address 1 st 7 bits Slave address 2nd byte Slave address 2nd byte 1 - 8 bits 7 bits 7 bits 7 bits 1 - 8 bits 8 bits 8 bits 7 bits 1 - 8 bits 1 - 8 bits 1 - 8 bits 1 - 8 bits 1 - 8 bits Slave address 1 st 7 bits Data Data DataA Data

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERMULTI-MASTER I 2C-BUS Interface 201 Rev.1.0 Example of Master Transmission An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. 1)Set a slave address in the high-order 7 bits of the I2C address register and “0” into the RBW bit. 2)Set the ACK return mode and SCL = 100 kHz by setting “0016” in the I2C control register 1 and “8516” in the I2C clock control register respectively. (f(XIN)=8MHz) 3)Set “0016” in the I2C status register so that transmission/reception mode is initialized. 4)Set a communication enable status by setting “0816” in the I2C control register 0. 5)Confirm the bus free condition by the BB flag of the I2C status register. 6)Set “E016” in the I2C status register to setup a standby of START condition. 7)Set the destination address data for transmission in high-order 7 bit of I2C data shift register and set “0” in the least significant bit. And then a START condition occurs. At this time, SCL for 1 byte and an ACK clock automatically generate. 8)Set transmission data in the I2C data shift register. At this time, an SCL and an ACK clock automatically generate. 9)When transmitting control data of more than 1 byte, repeat step 8). 10)Set “C0 16” in the I2C status register to setup a STOP condition if ACK is not returned from slave reception side or transmission ends. 11)A STOP condition occurs when writing dummy data to I2C data shift register. Example of Slave Reception An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK return mode and using the addressing format is shown below. 1)Set a slave address in the high-order 7 bits of the I 2C address register and “0” in the RBW bit. 2)Set the ACK clock mode and SCL = 400 kHz by setting “0016” in the I2C control register 1 and “A516” in the I2C clock control register respectively. (f(XIN)=8MHz) 3)Set “0016” in the I2C status register so that transmission/reception mode is initialized. 4)Set a communication enable status by setting “0816” in the I2C control register 0. 5)When a START condition is received, an address comparison is performed. 6)•When all transmitted addresses are “0” (general call): AD0 of the I 2C status register is set to “1” and an interrupt request signal occurs.

• When the transmitted addresses agree with the address set in1): ASS of the I2C status register is set to “1” and an interrupt request signal occurs.
• In the cases other than the above AD0 and AAS of the I2C status register are set to “0” and no interrupt request signal occurs. 7)Set dummy data in the I2C data shift register. 8)After receiving 1 byte data, it returns an ACK automatically and an interrupt request signal occurs. 9)In the case of whether returning an ACK or not by the content of the received control data, set the WIT bit of I 2C control register 1 to “1”, and after writing dummy data to I2C data shift register, receives the control data. 10)After receiving 1 byte data, an interrupt request signal occurs, set the ACKBIT to “1” or “0” by reading the content of the data shift register. and then returns or does not return an ACK. 11)When receiving control data of more than 1 byte, repeat step 7) 8) or 7) 10). 12)When a STOP condition is detected, the communication ends.

MULTI-MASTER I 2C-BUS Interface Mitsubishi microcomputers M16C / 6K7 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 202 Rev.1.0 Usage precautions (1) Access to the registers of I2C-BUS interface circuit The precaution of read/write to the control registers of I2C-BUS circuit is as follows.

• I2C data shift register (S0i : 032016, 033016) Do not write the register during transfer. The transfer bit counter will be reset and makes data communication incorrect.
• I2C address register (S0Di : address 032216, 033216) After the detection of a STOP condition, RBW is reset by H/W. Do not read/write the register at the time, because data may become undetermined. Fig.GC-22 shows the RBW bit H/W reset timing.
• I2C control register 0 (S1Di : address 032316, 033316). After the detection of a START condition or the completion of 1 byte transfer, bit counter (bits BC0 - BC2) is reset by H/W. Do not read/write the register at the time, because data may become undetermined. Fig.GC-23, GC-24 show the bit counter H/W reset timing.
• I2C clock control register (S2i : address 032416, 033416) Do not write to this register except ACKBIT during transfer. The I2C clock generator will be reset and makes transfer incorrect.
• I2C control register 1 (S3Di : address 032616, 033616) Write I2C system clock selection bits when I2C-BUS interface enable bit (ES0)is in disable state. By read- ing the data reception completion interrupt enable bit (WIT), the internal WAIT flag will be read. Thus, do not use bit manipulation (read-modify-write instruction) to access the register. 2C status register (S1i : address 032816, 033816) Do not use bit manipulation (read-modify-write instruction) to access the register because all bits of this register are changed by H/W. Do not read/write during the timing when communication mode setting bits MST and TRX are changed by H/W. Data may become undetermined. Fig.GC-22, GC-23, and GC-24 show the change timing of MST and TRX bits by H/W.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERMULTI-MASTER I 2C-BUS Interface 203 Rev.1.0 Fig.GC-22 The timing of bit reset (The detection of STOP condition) Fig.GC-23 The timing of bit reset (The detection of START condition) BB flag SCL Bit reset signal /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines RBW MST TRX /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 1.5VIIC cycle SDA Related bits BB flag SCL Bit reset signal /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines BC0 - BC2 TRX(slave mode) SDA Related bits Fig.GC-24 Bit set/reset timing ( at the completion of data transfer) SCL Bit set signal /LiteDiagLines/LiteDiagLines/LiteDiagLines 1VIIC cycle PIN bit /LiteDiagLines/LiteDiagLines 2VIIC cycle Bit reset signal /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines BC0 - BC2 MST(When in arbitration lost) TRX(When in NACK reception in slave transmission mode) The bits referring to reset /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines TRX(ALS="0" meanwhile the slave reception R/W bit = "1" The bits referring to set

MULTI-MASTER I 2C-BUS Interface Mitsubishi microcomputers M16C / 6K7 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 204 Rev.1.0 (2) Generation of RESTART condition After 1 byte data transfer, a RESTART condition standby can be set up by writing “E016 ” to I2C statusregister and the SDA pin will be released. Wait in software until SDA become “H ” stable and then owing to writing to I2C data shift register a START condition trigger will be generated. Fig.GC-25 shows the restart condition generation timing. (3) Iimitation of internal clock 0 The registers of I2C-BUS interface circuit can not be read from or written to if the internal clock up selected to sub clock (XCIN, XCOUT ) by system clock selection bit (system clock control register 0, address 000616, CMO7 bit). Please select main clock (XIN, XOUT ) in read/write. Fig.GC-25 The time of generation of RESTART condition 8 clock ACK clockSCL SDA S1i writing signal ( Set the standby of start condition) Insert software wait S0i writing signal (START condition trigger generation)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERPS2 Interface 205 Rev.1.0 PS2 Interface PS2 interface is supported by 3 channels of serial transmission/reception circuit which is based on PS2 standard specifications. There are two signal lines, used by PS2 interface : PS2 data(DAT) and PS2 clock(CLK). The DAT and CLK signal lines are bidirection and should be connected to positive power supply via external pull-up resistors. These two pins are N-channel open drain output. While bus is released, the states of DAT and CLK is “High”. Fig.GK-1 shows the system configuration. Fig.GK-1 System configuration DAT Input Input Input Input Control side Device side DAT CLK CLK Output Output Output Output

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 206 Rev.1.0 The PS2 interface performs 1 byte data transfer with the format shown in Fig.GK-2. Table GK-1 shows the communication specification. Table GK-1 Communication specification Item Specification Data transfer format *Start bit : 1 bit *Data bit : 8 bits (LSB first) *Parity bit : 1 bit (Odd) *Stop bit : 1 bit *Acknowledge : 1 bit (Transmission only) Transfer clock *Using the clock, which is synchronized with the sampling clock of PS2 clock (CLK) Reception start condition *The following conditions should be met for reception start 1) Setting reception enable bit to “1” 2) The detection of “L” on both PS2 clock (CLK) and PS2 data (DAT) lines Transmission start condition *The following conditions should be met for transmission start 1) Setting transmission data to PS2i shift register 2) Setting transmission enable bit to “1” Transfer abort *The following conditions should be met for transfer abort 1) Setting transfer interruption bit to “1” 2) The transfer completion flag becomes “1” Interrupt request generation *In reception: At the completion of stop bit reception timing *In transmission: At the completion of ACK bit reception. *In transfer interruption: At the completion of transfer interruption Error detection *Parity error (In reception) It occurs when there is a parity error in data reception *Framing error (In reception) It occurs when the detection of stop bit of reception data fails. *Abnormal acknowledge reception (In transmission) It occurs when NAK is received from a device side after the data transmission Selection function *Sampling clock selection Selecting the clock which samples the PS2 clock (CLK) and PS2 data (DAT)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERPS2 Interface 207 Rev.1.0 Fig.GK-2 1 byte data format In reception Data :8-bit Parity :Odd 10-bit Stop :1 bit START D0 D1 D2 D3 D4 D5 D6 D7 PARITY STOP 1 byte data format In Transmission Data :8-bit Parity :Odd 11-bit Stop :1 bit Acknowledge :1 bit START D0 D1 D2 D3 D4 D5 D6 D7 PARITY STOP 1 byte data format ACK/NAK

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 208 Rev.1.0 Fig.GK-3 PS2 interface block diagram Fig.GK-3 shows the PS2 interface overall block diagram. Fig.GK-4 shows the transmission/reception block diagram. Internal data bus PS2Bi(i=0-2) PS2Ai(i=0-2) Port control section Pin selection Divider Ch0 Transmission/ reception section CLK output DAT output CLK input DAT input Sampling clock selection Sampling clock Interrupt request 0 Interrupt request 1 Interrupt request 2 Control stop PS2 mode register (02AC16) "1" "1" "1" "1" Ch1 Transmission/ reception section Ch2 Transmission/ reception section

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERPS2 Interface 209 Rev.1.0 Fig.GK-4 Transmission/reception section block diagram (One channel) Internal data bus Sampling clock DAT output Interrupt request PS2i shift register (02A016,02A416,02A816) CLK output CLK input DAT input Synchronization Reception start detection circuit Shift enable Transmission/reception control circuit Reception process section

• Completion detection
• Parity generation Transmission process section Completion detection
• Parity generation
• Acknowledge reception Transfer completion process circuit Reception completion PE & FE Transmission completion Acknowledge result Transfer completion flag refresh Transmission enable Transfer abort Reception enable All bits clear Communication status flags Internal data bus PS2i control register (02A216,02A616,02AA16) PS2i status register (02A116,02A516,02A916) Error flag refresh

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 210 Rev.1.0 (1) Register description G PS2i shift register

• Transmission/reception data (1) Data reception The reception data are stored. (2) Data transmission By writing the transmitted data to the register, data transmission is ready to start. PS2 data (DAT) will become “L” automatically (transmission start). Fig.GK-5 PS2i shift register PS2i Shift register Bit name FunctionBit symbol W R symbol Address Reset value PS20SR 02A0 16 0016 PS21SR 02A4 16 0016 PS22SR 02A8 16 0016 Transmission/reception data b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERPS2 Interface 211 Rev.1.0 G PS2i Control register

• Reception enable bit (REN) The data reception is allowed when this bit is set to “1”. The PS2 clock (CLK) will become to “H ” (reception enable status) automatically. This bit will be cleared to “0” automatically after the completion of data reception and PS2 clock (CLK) will become “L” (reception disable status) . If this bit is needed wants to be cleared after setting it to “1” but before the transfer completion flag is set, set reception enable bit = “0”, transfer abort request bit = “0” and proccess the transfer abort simultaneously.
• Transmission enable bit (TEN) After writing transmission data to the PS2i shift register, setting the bit to “1” makes data transmission enabled and PS2 clock (CLK) will become “H ” automatically (transmission enable status). This bit will be cleared to “0” automatically after the completion of data transmission and PS2 clock (CLK) will become “L” (transmission disable status). If this bit is needed to be cleared after setting it to “1” but before the transfer completion flag is set, set reception enable bit = “0”, transfer abort request bit = “0” and proccess the transfer abort simultaneously.
• Transfer abort request bit (RSTOP) This bit is used to abort the data transfer procession. At the completion of transfer abort procession, the transfer completion flag and transfer abort flag of PS2i status register are set to “1”, the bit is cleared to “0” automatically and PS2 clock (CLK) will become “L” ( reception disable status). After “L” is output to the PS2 clock (CLK), do not execute the following transmission/reception before the device recognizes the transfer abort request. Fig.GK-6 PS2i control register PS2i control register Bit name FunctionBit Symbol W R Symbol Address Reset Value PS20CON 02A2 16 0016 PS21CON 02A6 16 0016 PS22CON 02AA 16 0016 Reception enable bit 0 : No transfer abort 1 : Transfer abort RSTOP b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Nothing is allocated. Meaningless in writing, "0" in reading. TEN REN Transmission enable bit Transfer abort request bit 0 : Disable 1 : Enable 0 : Disable 1 : Enable

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 212 Rev.1.0 G PS2i status register

• Transfer completion flag (TI) The flag is set to “1” at the completion of transmission/reception and the completion of transfer abort. The flag is cleared at read out from PS2i shift register or when the reception enable bit is changed from “0” to “1”.
• Receiving flag (RF) The flag is set to “1” during the data reception. The flag is cleared automatically after the data reception or after the transfer abort.
• Reception abort incognizable flag (CD) The flag is set in the case that device side can not recognize the abort even if the reception abort is requested. (The flag is set in the period between the completion of data bit 6 reception and the completion of stop bit reception.) The flag is cleared automatically after the completion of data reception or after the completion of transfer abort. ✽ Note that during the period when the flag is set, the device side can not recognize the reception abort request even if the tranfer abort is executed. Thus the data that the transfer abort is requested will not be resent from device side.
• Transfer status flag (TS) The flag is set to “1” at the completion of data reception. The flag is cleared at read out from PS2i shift register or when the reception enable bit is changed from “0” to “1”.
• Parity error flag (PE) This bit is set to “1” when parity error occurs in received data. The flag is cleared at read out from PS2i shift register or when the reception enable bit is changed from “0” to “1”.
• Framing error / NACK reception flag (FE) At the completion of reception: The flag is set when the detection of stop bit of reception data fails. At the completion of transmission: The flag is set when NAK is received from the device side. The flag is cleared at read out from PS2i shift register, the reception enable bit or the transmission bit is changed from “0” to “1”.
• Transfer abort completion flag (CC) This bit is set to “1” when transfer abort procession is completed. The flag is cleared at read out from PS2i shift register, or when the reception enable bit or the transmission bit is changed from “0” to “1”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERPS2 Interface 213 Rev.1.0 Fig.GK-7 PS2i status register PS2i status register Bit name FunctionBit Symbol WR Symbol Address Reset Value PS20STS 02A1 16 0016 PS21STS 02A5 16 0016 PS22STS 02A9 16 0016 TI 0 : Waiting for transfer , During transfer 1 : Communication complete Receiving flag Parity error flag Framing error / NACK reception flag RF CD PE FE CC b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Transfer completion flag Nothing is allocated. Meaningless in writing, "0" in reading. Transfer abort completion flag 0 : Waiting for reception , Reception complete 1 : During receiving 0 : Recognizable 1 : Incognizable 0 : No error 1 : Error 0 : No error 1 : Error 0 : Not abort 1 : Abort TS Transfer status flag 0 : Transmission operation 1 : Reception operation Reception abort incognizable flag

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 214 Rev.1.0 G PS2 mode register

• Sampling clock selection bits (SCK0,1) These two bits select clock frequency for sampling PS2 clock (CLK) and PS2 data (DAT). The relation between main clock (XIN) and sampling cycle is shown in table below. XIN Setting value 1/4 1/8 1/16 1/32 8MHz 0.5 µ 1.0µ 2.0µ 4.0µ 5MHz 0.8 µ 1.6µ 3.2µ 6.4µ ✽Sampling clock , which samples each line periodically, is used for avoiding the reflection from each line. The sampling clock will be delayed by internal circuit around 1 cycle. Thus, set the samplingclock as fast as possible.
• Pin selection bit (PSEL) This bit is for selecting PS2 clock (CLK) or PS2 data (DAT) to connect to PS2Bi (i=0 to 2) .PS2Bi are external interrupt input pins. The bit setting definition is shown in table below. Pin selection bit PS2Bi (i= 0 to 2) “0” PS2 clock (CLK) “1” PS2 data (DAT)
• PS2 interface enable bit (PSEN) The PS2Ai (i= 0 to 2) and PS2Bi (i= 0 to 2) will be disconnected to hardware PS2 control section and become GPIO port when the bit is “0”. The PS2Ai and PS2Bi will be connected to hardware PS2 control section when this bit is “1”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERPS2 Interface 215 Rev.1.0 Fig.GK-8 PS2 mode register PS2 mode register Bit name FunctionBit Symbol W R Symbol Address Reset Value PS2MOD 02AC 16 0016 Sampling clock selection bits Pin selection bit b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 00 : Main clock /4 01 : Main clock /8 10 : Main clock /16 11 : Main clock /32 PS2 interface enable bits PSEN1 PSEN2 SCK0 SCK1 PSEL Nothing is allocated. Meaningless in writing, "0" in reading. PSEN0 0 : PS2B connects to PS2 clock(CLK) 1 : PS2B connects to PS2 data(DAT) 0 : P70,P73 as GPIO 1 : P70,P73 as PS2A0,PS2B0 0 : P71,P74 as GPIO 1 : P71,P74 as PS2A1,PS2B1 0 : P72,P75 as GPIO 1 : P72,P75 as PS2A2,PS2B2 Reserved bit Must be set to "0".

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 216 Rev.1.0 (2) Operation description G Basic setting The following items should be set for PS2 mode register (address 02AC16) set when PS2 interface is used.

• PS2 interface enable bit Set the PS2 interface enable bits (bit4 to 6 of PS2 mode register) to “1” to enable the PS2 channels to be used. At this time PS2 clock goes “Low ” (Receiving disable).
• Sampling clock selection bit Sampling clock cycle (1/4,1/8,1/16,1/32 of main clock) is selected by setting sampling clock bit (bits 0,1).
• External interrupt function support pin (PS2B) selection This bit is used to select PS2 clock (CLK) or PS2 data (DAT) for the external interrupt function support pin (PS2B).

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERPS2 Interface 217 Rev.1.0 G Reception operation Fig.GK-9 shows the reception operation timing. Fig.GK-9 Reception operation timing D0 D1 D2 D3 D4 D5 D6 D7 partystopstartDAT CLK (Device side CLK) (Controller side CLK) Reception enable bit Data receiving flag Reception abort incognizable flag Transfer completion flag Interrupt request 1 2 3 3 3 3 3 3 3 3 3 4 5 (1) Reception enable The reception operation is enabled by writing 0116 (reception enable bit = “1”) to PS2i control register (address : 02A216, 02A616, 02AA16). The PS2 clock (CLK) will become “H ”. (2) Reception start The reception operation starts when both PS2 clock (CLK) and PS2 data (DAT) are detected with “L”. (3) Data reception (The reception of data and parity bits) The content PS2 data (DAT) is read into PS2i shift register (address : 02A0 16, 02A416, 02A816) sequentially by the falling edge of PS2 clock (CLK). The data transfer sequence is data bit (D0 -D7) then parity bit. (4) Reception completion (Stop bit Reception completion) By detecting the falling edge of PS2 clock (CLK), the transfer completion flag (bit 0 of PS2i status register) is set to “1” after the update of error flag (bit 4 - 6 of PS2i status register) and the reception enable bit (bit 0 of PS2i control register) is cleared to “0”. The PS2 clock (CLK) becomes “L” (reception disable status) and interrupt request occurs. (5) Data read out Read out data from PS2i shift register (address : 02A0 16,02A416,02A816). At this time , the error flags (Bit4 to 6) of and transfer completion flag (bit 0) of PS2i status register (address: 02A116, 02A516, 02A916) will be cleared to “0”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 218 Rev.1.0 G Transmission operation Fig.GK-10 shows the transmission operation timing. Fig.GK-10 Transmission operation timing (1) Data writing Write transmission data to PS2i shift register (address : 02A016, 02A416, 02A816). At this time,PS2 data will become “L” (transmission start). (2) Transmission enable Set 02 16 (Transmission enable bit = “1”) to PS2i control register (address : 02A216, 02A616, 02AA16) for enabling transmission operation. At this time , PS2 clock (CLK) will become “H ”. (3) Data transmission (The transmission of data, parity and stop bits) The content of PS2i shift register (address : 02A0 16, 02A416, 02A816) will be output to the PS2 data (DAT) sequentially by the falling edge of PS2 clock (CLK). The sequence of data transfer is data bits (D0 to D7) , Parity bit, and stop bit. (4) Acknowledge reception The content of acknowledge bit will be read by the falling edge of PS2 clock (CLK). (5) Communication completion The communication opeartion is completed by detecting “H ” on both PS2 clock (CLK) and PS2 data (DAT). After the update of error flag (bit 4 - 6 of PS2i status register), the transfer completion flag (bit 0 of PS2i status register) is set to “1” and the reception enable bit (bit 0 of PS2i control register) is cleared to “0”. At this time, PS2 clock (CLK) becomes “L” (reception disable status) and the interrupt request occurs. (6) Status clear Read out the data from PS2i shift register (address : 02A0 16, 02A416, 02A816). At this time , the error flags (bits 4 to 6) and transfer completion flag (Bit0) of PS2i status register (address : 02A116, 02A516, 02A916) will be cleared to “0”. D0 D1 D2 D3 D4 D5 D6 D7 paritystopDAT CLK (Device side CLK) (Controller side CLK) Transmission enable flag Transfer completion flag Interrupt request (Device side DAT) (Controller side DAT) D0 D1 D2 D3 D4 D5 D6 D7 paritystopstart ackstart 1 2 3 3 3 3 3 3 3 3 3 3 4 5 6

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERPS2 Interface 219 Rev.1.0 (1) - (3) Data reception operation (4) Transfer abort request Set 04 16 (transfer abort request bit = “1”) to PS2i control register (address : 02A216, 02A616,02AA16). (5) Transfer abort completion The transfer abort completion flag (bit 6) and transfer completion flag (bit 0) of PS2i status register (address : 02A1 16, 02A516, 02A916) are set to “1”, transfer abort request bit (bit 2) of PS2i control register (address : 02A216, 02A616, 02AA16) is cleared to “0”. At this time, PS2 clock (CLK) becomes “L” (recep- tion disable status) and interrupt request occurs. (6) Status clear By a pseudo read of PS2i shift register (address : 02A016, 02A416, 02A816), the transfer abort completion flag (bit 6) and transfer completion flag (bit 0) of PS2i status register (address : 02A116, 02A516, 02A916) are cleared to “0”. Note: Do not execute the following transmission/reception during the period between the “L” output from PS2 clock (CLK) and the transfer abort request recognition of the device. Fig.GK-11 Transfer abort operation timing ( reception) G Transfer abort operation Fig.GK-11 shows the transfer abort operation timing. D0 D1 D2 D3 D4DAT CLK (Device side CLK) (Controller side CLK) Transfer abort request bit Transfer abort completion flag Reception abort incognizable flag Transfer completion flag Interrupt request start 1 2 3 3 3 3 4 5 6

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 220 Rev.1.0 Programmable I/O Ports There are 129 programmable I/O ports: P0 to P16 (excluding P85). Each port can be set independently for input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. The N channel open drain ports P60 to P63, P70 to P77, P80 to P84, P130 to P137 and P85 (input only port) do not build internal pull-up resistance. Fig.UA-1 to UA-6 show the configurations of programmable I/O ports. Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices. To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A con- verter), they function as outputs regardless of the contents of the direction registers. When pins are used as the outputs for the D-A converter, do not set the direction registers to output mode. See the descriptions of the respective functions for how to set up the built-in peripheral devices. (1) Direction registers Fig.UA-7 shows the configurations of direction registers. These registers are used to choose the direction of the programmable I/O ports. Each bit in these registers corresponds one for one to each I/O pin. Note: There is no direction register bit for P8 (2) Port registers Fig.UA-8 shows the configurations of port registers. These registers are used to write and read data for input and output to and from exterior. A port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit in port registers corresponds one for one to each I/O pin. (3) Pull-up control registers Fig.UA-9 and UA-10 shows the configurations of pull-up control registers. The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. (4) Port control register Fig.UA-11 shows the configurations of port control register 0, 1. Fig.UA-12 shows the configuraitons of port control register 2, 3. The bit 0 of port control resister 0 is used to read port P1 as follows: 0 : When port P1 is input port, port input level is read. When port P1 is output port , the contents of port P1 register is read. 1 : The contents of port P1 register is read always. (neither input port nor output port)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERPort 221 Rev.1.0 The P0, P1, P40 to P46, P11 and P14 output type, CMOS or N channel open drain, are set by bit 0 to 6 of port control register 1 and bit 0 to 2 of port control register 3. 0 : CMOS output 1 : N channel open drain output Exception: P42 output type is N channel open drain if either bit 4 of port control register 1 or bit 2 of port control register 3 is set to “1”. Bit 7 of port control register1 functions as below 0 : P40/P43 output is cleared by software only 1 : P40/P43 output is cleared by software or when output buffer 0 is read by host side. The driving ability of N channel output transistors for P140 to P143 can be selected by bit 6 of port control register 2 controls as below: 0 : Driving ability of N channel open drain output transistor is LOW 1 : Driving ability of N channel open drain output transistor is HIGH (5) Port P4/P7 input register Fig.UA-13 shows the configurations of P4 and P7 input register. By reading the registers, the input level of the corresponding pins can be known regardless the input/output mode.These two registers can be read regardless port direction setting. And the ports level will be read out. Port4 : Bit 0 to bit6's level will be read out. And bit7 is always “0”. Port7 : Bit 0 to bit5's level will be read out. And bit6,7 is always “0”. (6) Port function selection register 0,1 Fig.UA-14 shows the configurations of port function selection register 0,1. The port functions of UART0 to UART2 output, TimerA0 to TimerA2 output, TimerB3,B4 input or external interrupt INT6 to INT12 input can be switched by setting these two registers. And by setting bit6,7 of port function selection register 1, the same frequency clock with f(X IN) can be output from P66 and P67.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 222 Rev.1.0 Fig.UA-1 Programmable I/O ports (1) Data bus Pull-up selection Port latch Direction register P00 to P07 P110 to P117 P140 to P147 Output formality selection bit Input respective peripheral function Data bus Pull-up selection Port latch Direction registerP12, P16 Output formality selection bit Data bus Pull-up selection Port latch Direction register P13, P43 to P46 Output "1" Output formality selection bit Input respective peripheral function Data bus Pull-up selection Port latch Direction registerP10, P11, P14, P15, P17 P40 to P42 Output "1" Output formality selection bit (Note) symbolizes a parasitic diode. Do not apply a voltage higher than Vcc each port. (Note) (Note) (Note) (Note)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERPort 223 Rev.1.0 Fig.UA-2 Programmable I/O ports (2) Data bus Pull-up selection Port latch Direction register P126, P127 P153 to P157 Data bus Pull-up selection Port latch Direction register P47 Output "1" Input to respective peripheral function Data bus Pull-up selection Port latch Direction registerP21, P24 to P27, P50 to P57 P91, P97 P120 to P126 P160, P161 Input to respective peripheral function Data bus Pull-up selection Port latch Direction register P20, P22, P23, P30 to P37 P150 to P152, P64 to P67, P90, P92 Output "1" Note. symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. (Note) (Note) (Note) (Note)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 224 Rev.1.0 Fig.UA-3 Programmable I/O ports (3) Data bus Port latch Direction register P130 to P137 Data bus Port latch Direction register P76 to P77, P80 to P84 Input to respective peripheral function Data bus Port latch Direction register P60 to P63, P70 to P75 Output "1" Input to respective peripheral function Note. symbolizes a parasitic diode. (Note) (Note) (Note)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERPort 225 Rev.1.0 Fig.UA-4 Programmable I/O ports (4) Input to respective peripheral function Data bus Pull-up selection Port latch Direction register P100, P101 (Excepting the short dashes line section) P102 to P107 (Including the short dashes line section) Analog input Input to respective peripheral function Data bus Pull-up selection Port latch Direction register P93, P94 Analog output DA output enable Output "1" DA output enable (Note) (Note) Data bus Pull-up selection Port latch Direction register P95 Output "1" Input to respective peripheral function Analog input (Note) P102 to P107 only Data bus Pull-up selection Port latch Direction register P96 Output "1" Analog input Note symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. (Note)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 226 Rev.1.0 Fig.UA-5 Programmable I/O ports (5) Input to respective peripheral function Data bus Pull-up selection Port latch Direction registerP87 Note symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. Data bus Pull-up selection Port latch Direction register P86 Output "1" Rf Rd (Note) (Note) fc Fig.UA-6 I/O pins Note1. symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each pin. (Note1) M 1 signal input M 1 (Note1) M 0 signal input M 0 (Note1) RESET signal input RESET

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERPort 227 Rev.1.0 Fig.UA-7 Direction register Port Pi direction register (Note1) symbol Address When reset PDi(i=0-15, except 8) 03E2 16,03E316,03E616,03E716,03EA16 0016 03EB 16,03EE16,03EF16,03F316,03F616 02E216,02E316,02E616,02E716,02EA16 Bit name FunctionBit symbol W R b b6 b b b3 b b b0 PDi_0 Port Pi 0 direction register PDi_1 Port Pi 1 direction register PDi_2 Port Pi 2 direction register PDi_3 Port Pi 3 direction register PDi_4 Port Pi 4 direction register PDi_5 Port Pi 5 direction register PDi_6 Port Pi 6 direction register PDi_7 Port Pi 7 direction register 0 : Input mode (Function as an input port) 1 : Output mode (Function as an output port) (i=0-15, except 8) Port P8 direction register Symbol Address When reset PD8 03F2 16 00X000002 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 PD8_0 Port P8 0 direction register PD8_1 Port P8 1 direction register PD8_2 Port P8 2 direction register PD8_3 Port P8 3 direction register PD8_4 Port P8 4 direction register Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. PD8_6 Port P8 6 direction register PD8_7 Port P8 7 direction register 0 : Input mode (Function as an input port) 1 : Output mode (Function as an output port) 0 : Input mode (Function as an input port) 1 : Output mode (Function as an output port) Note Set bit 2 of protect register(address 000A16) to "1" before rewriting to the port P9 direction register. Port P16 direction register Symbol Address When reset PD16 02EB 16 XXXXXX00 2 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate PD16_0 Port P16 0 direction register PD16_1 Port P16 1 direction register 0 : Input mode (Function as an input port) 1 : Output mode (Function as an output port)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 228 Rev.1.0 Fig.UA-8 Port register Port Pi register Symbol Address When reset Pi(i=0 to15 03E0 16,03E116,03E416,03E516,03E816 Indeterminate ,except 8) 03E9 16,03EC16,03ED16,03F116,03F416 02E016,02E116,02E416,02E516,02E816 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 Pi_0 Port Pi 0 register Pi_1 Port Pi 1 register Pi_2 Port Pi 2 register Pi_3 Port Pi 3 register Pi_4 Port Pi 4 register Pi_5 Port Pi 5 register Pi_6 Port Pi 6 register Pi_7 Port Pi 7 register Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : "L" level data 1 : "H" level data Port P8 register Symbol Address When reset P8 03F0 16 Indeterminate Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 P8_0 Port P8 0 register P8_1 Port P8 1 register P8_2 Port P8 2 register P8_3 Port P8 3 register P8_4 Port P8 4 register P8_5 Port P8 5 register P8_6 Port P8 6 register P8_7 Port P8 7 register Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : "L" level data 1 : "H" level data Port P16 register Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate PD16_0 Port P16 0 register PD16_1 Port P16 1register Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : "L" level data 1 : "H" level data (i=0-15, except 8) Symbol Address When reset P16 02E9 16 Indeterminate

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERPort 229 Rev.1.0 Fig.UA-9 Pull-up control resiter(1) Pull-up control register 0 Symbol Address When reset PUR0 03FC 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 PU00 P0 0 to P03 pull-up PU01 P0 4 to P07 pull-up PU02 P1 0 to P13 pull-up PU03 P1 4 to P17 pull-up PU04 P2 0 to P23 pull-up PU05 P2 4 to P27 pull-up PU06 P3 0 to P33 pull-up PU07 P3 4 to P37 pull-up The corresponding port is pulled high with a pull-up register 0: Not pulled high 1: Pulled high Pull-up control register 2 Symbol Address When reset PUR2 03FE 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 PU21 P8 6, P87 pull-up(Note) PU22 P9 0 to P93 pull-up PU23 P9 4 to P97 pull-up PU24 P10 0 to P103 pull-up PU25 P10 4 to P107 pull-up Nothing is assigned. Can't write to this bit. The value, if read, turns out to be “0”. Pull-up control register 1 Symbol Address When reset PUR1 03FD 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 PU10 P4 0 to P43 pull-up PU11 P4 4 to P47 pull-up PU12 P5 0 to P53 pull-up PU13 P5 4 to P57 pull-up PU15 P6 4 to P67 pull-up The corresponding port is pulled high with a pull-up register 0: Not pulled high 1: Pulled high Nothing is assigned. (Note) Can't write to this bit. The value, if read, turns out to be “0”. Nothing is assigned. (Note) Can't write to this bit. The value, if read, turns out to be “0”. Note.Since P60 to P63 and P70 to P77 are N-channel open drain ports, internal pull-up is not available for them. Note.Since P80 to P84 are N-channel open drain ports, internal pull-up is not available for them. And P85 is input port only , also no internal pull-up is available. Nothing is assigned. Can't write to this bit. The value, if read, turns out to be “0”. The corresponding port is pulled high with a pull-up register 0: Not pulled high 1: Pulled high W R W R W R

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 230 Rev.1.0 Fig.UA-10 Pull-up control register(2) Pull-up control register 3 Symbol Address When reset PUR3 02FC 16 0016 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 PU30 P11 0 to P113 pull-up PU31 P11 4 to P117 pull-up PU32 P12 0 to P123 pull-up PU33 P12 4 to P127 pull-up PU36 P14 0 to P143 pull-up PU37 P14 4 to P147 pull-up The corresponding port is pulled high with a pull-up register 0 : Not pulled high 1 : Pulled highPull-up control register 4 Symbol Address When reset PUR4 02FD 16 0016 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 The corresponding port is pulled high with a pull-up register 0 : Not pulled high 1 : Pulled high Nothing is assigned. Can't write to this bit. The value, if read, turns out to be “0”. 0 : Not pulled high 1 : Pulled high Nothing is assigned. (Note) Can't write to this bit. The value, if read, turns out to be “0”. PU40 P15 0 to P153 pull-up PU41 P15 4 to P157 pull-up PU42 P16 0, P161 pull-up Note.Since P130 to P137 are N-channel open drain ports, internal pull-up is not available for them.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERPort 231 Rev.1.0 Fig.UA-11 Port control register 0, 1 Port control register 0 Symbol Address When reset PCR0 03FF 16 0016 Bit name FunctionBit Symbol W R b7 b6 b5 b4 b3 b2 b1 b0 PCR00 Port P1 control register 0 : When input port, read port input level. When output port, read the contents of port P1 register 1 : Read the contents of port P1 register though input/output port. Nothing is assigned. Can't write to this bit. The value, if read, turns out to be “0”. Port control register 1 Symbol Address When reset PCR1 02FE 16 0016 Bit name FunctionBit Symbol b7 b6 b5 b4 b3 b2 b1 b0 PCR10 Output type selection bit (P00 to P03) PCR11 Output type selection bit (P04-P07) PCR12 Output type selection bit (P10-P13) PCR13 Output type selection bit (P14-P17) PCR14 Output type selection bit (P40-P46) PCR15 Output type selection bit (P110-P113) PCR16 Output type selection bit (P114-P117) PCR17 P4 0,P43 output clear function selection bit 0 : CMOS 1 : N-channel open drain W R 0 : Cleared by software only 1 : Cleared by software or when output buffer is read by host side. 0 : CMOS 1 : N-channel open drain 0 : CMOS 1 : N-channel open drain 0 : CMOS 1 : N-channel open drain 0 : CMOS 1 : N-channel open drain 0 : CMOS 1 : N-channel open drain 0 : CMOS 1 : N-channel open drain

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 232 Rev.1.0 Fig.UA-12 Port control register 2, 3 Port control register 2 Symbol Address When reset PCR2 02FF 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 Reserved bit Reserved bit Reserved bit Reserved bit Reserved bit Reserved bit Nothing is assigned. Can't write to this bit. The value, if read, turns out to be “0”. Must be set to "0" W R Must be set to "0" Must be set to "0" Must be set to "0" Must be set to "0" Must be set to "0" PCR26 Drive polarity selection bit (P140 to P143) 0 : Low side 1 : High side Port control register 3 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 Nothing is assigned. Can't write to this bit. The value, if read, turns out to be “0”. PCR30 Output type selection bit (P140 - P143) 0 : CMOS 1 : N-channel open drain PCR31 0 : CMOS 1 : N-channel open drain PCR32 0 : CMOS 1 : N-channel open drain Output type selection bit (P144 - P147) Output type selection bit (P4 Symbol Address When reset PCR3 02F7 16 0016 000000

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERPort 233 Rev.1.0 Fig.UA-13 Port P4,P7 input register Port P7 input register Symbol Address When reset P7PIN 02FB 16 00XXXXXX2 Bit name FunctionBit Symbol W R b7 b6 b5 b4 b3 b2 b1 b0 P7PIN_0 Port P7 0 input register For reading P70 pin level Nothing is assigned. Can't write to this bit. The value, if read, turns out to be “0”. P7PIN_1 Port P7 1 input register For reading P71 pin level P7PIN_2 Port P7 2 input register For reading P72 pin level P7PIN_3 Port P7 3 input register For reading P73 pin level P7PIN_4 Port P7 4 input register For reading P74 pin level P7PIN_5 Port P7 5 input register For reading P75 pin level Port P4 input register Symbol Address When reset P4PIN 02FA 16 0XXXXXXX 2 Bit name FunctionBit Symbol W R b7 b6 b5 b4 b3 b2 b1 b0 P4PIN_0 Port P4 0 input register For reading P40 pin level Nothing is assigned. Can't write to this bit. The value, if read, turns out to be “0”. P4PIN_1 Port P4 1 input register For reading P41 pin level P4PIN_2 Port P4 2 input register For reading P42 pin level P4PIN_3 Port P4 3 input register For reading P43 pin level P4PIN_4 Port P4 4 input register For reading P44 pin level P4PIN_5 Port P4 5 input register For reading P45 pin level P4PIN_6 Port P4 6 input register For reading P46 pin level

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 234 Rev.1.0 Fig.UA-14 Port function register 0,1 Port function selection register 0 Symbol Address When reset PSL0 02F8 16 0016 Bit name FunctionBit Symbol b7 b6 b5 b4 b3 b2 b1 b0 PSL00 UART0 I/O pin selection bit PSL01 UART1 I/O pin selection bit PSL04 INT8 I/O pin selection bit 0 : P60-P63 1 : P10-P13 W R PSL02 UART2 I/O pin selection bit PSL03 INT7 input pin selection bit 0 : P104 1 : P15 PSL05 INT9 I/O pin selection bit PSL06 INT10 I/O pin selection bit Port function selection register 1 Symbol Address When reset PSL1 02F9 16 0016 Bit name FunctionBit Symbol b7 b6 b5 b4 b3 b2 b1 b0 PSL11 TA1 output pin selection bit PSL14 TB4 output pin selection bit 0 : P93 1 : P160 W R PSL12 TA2 output pin selection bit PSL13 TB3 output pin selection bit PSL10 TA0 output pin selection bit 0 : P40 1 : P150 0 : P41 1 : P151 0 : P42 1 : P152 Note. If this is set to "1" then port function selection register 1 (address 02F816) bit 3 to bit6 setting will be ignored. 0 : P64-P67 1 : P14-P17 0 : P70-P73 1 : P20-P23 0 : P103 1 : P14 0 : P105 1 : P16 0 : P106 1 : P17 0 : P94 1 : P161 PSL15(Note) INT6-INT11 input pin 0 : P97,P103-P107 1 : P120,P121-P125 switching bit PSL16 P6 6 : f1 output function selection bit 0 : P66 as GPIO 1 : P66 as f1 output PSL17 P6 7 : f1 output function selection bit 0 : P67 as GPIO 1 : P67 as f1 output Reserved bit Must be set to "0"

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTERPort 235 Rev.1.0 Table.UA-1 Example connection of unused pins in single-chip mode Fig.UA-15 Example connection of unused pins Port P0 to P16 (except for P85) NMI XOUT AV CC M 1 AV SS VREF Microcomputer VCC VSS In single-chip mode open (input mode) (output mode) open M 0 0.47 µF (input mode) Pin name Connection Ports P0 to P10 (excluding P85) After setting for input mode, connect every pin to VSS or VCC via a resistor; or after setting for output mode, leave these pins open. XOUT (Note) AV SS , VREF , M1 AV CC Open Connect to VCC Connect to VSS Note: With external clock input to XIN pin. NMI Connect via resistor to VCC (pull-up) Ports P11 to P16 After setting for input mode, connect every pin to VSS or VCC via a resistor; or after setting for output mode, leave these pins open.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 236 Rev.1.0 Timer A (timer mode) Usage Precaution Timer A (event counter mode) (1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. But, reading the timer Ai register with the reload timing gets “FFFF 16” by underflow or “000016” by overflow. Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a setting value to the timer. (2) When stop counting in free run type, set timer again. (1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. But, reading the timer Ai register with the reload timing gets “FFFF 16”. Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a setting value to the timer. (1) Setting the count start flag to “0” while a count is in progress causes as follows:

• The counter stops counting and a content of reload register is reloaded.
• The TAiOUT pin outputs “L” level.
• The interrupt request generated and the timer Ai interrupt request bit goes to “1”. (2) The timer Ai interrupt request bit goes to “1” if the timer's operation mode is set using any of the following procedures:
• Selecting one-shot timer mode after reset.
• Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after the above listed changes have been made. Timer A (one-shot timer mode) (1) The timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compliance with any of the following procedures:
• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after the above listed changes have been made. (2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop counting. If the TAiOUT pin is outputting an “H ” level in this instance, the output level goes to “L”, and the timer Ai interrupt request bit goes to “1”. If the TAiOUT pin is outputting an “L” level in this instance, the level does not change, and the timer Ai interrupt request bit does not becomes “1”. Timer A (pulse width modulation mode) Timer B (timer mode, event counter mode) (1) Reading the timer Bi register while a count is in progress allows reading , with arbitrary timing, the value of the counter. But, reading the timer Bi register with the reload timing gets “FFFF 16”. Reading the timer Bi register after setting a value in the timer Bi register with a count halted but before the counter starts counting gets a setting value to the timer.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 237 Rev.1.0 Stop Mode and Wait Mode A-D Converter (1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt request bit goes to “1”. (2) When the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. At this time, timer Bi interrupt request is not generated. Timer B (pulse period/pulse width measurement mode) Interrupts (1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit 0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs). In particular, when the Vref connection bit is changed from “0” to “1”, start A-D conversion after an elapse of 1 µs or longer. (2) When changing A-D operation mode, select analog input pin again. (3) Using one-shot mode or single sweep mode Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by A-D conversion interrupt request bit.) (4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1 Use the undivided main clock as the internal CPU clock. (1) Reading address 00000

• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 00000 16 will then be set to “0”. Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”. Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 00000 16 by software. (2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point at the beginning of a program. Concerning the first instruction immediately after reset, generating any interrupts including the NMI interrupt is prohibited. (3) The NMI interrupt
• As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the VCC pin via a resistor (pull-up) if unused. Be sure to work on it.
• Do not get either into stop mode with the NMI pin set to “L”. (1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock oscillation is stabilized. (2) When switching to either wait mode or stop mode, instructions occupying four bytes either from the WAIT instruction or from the instruction that sets the every-clock stop bit to “1” within the instruction queue are prefetched and then the program stops. So put at least four NOPs in succession either to the WAIT instruction or to the instruction that sets the every-clock stop bit to “1”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 238 Rev.1.0 (4) External interrupt

• When the polarity of the INT0 to INT11 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0". Example 1: INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. NOP ; Four NOP instructions are required when using HOLD function. NOP FSET I ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. MOV.W MEM, R0 ; Dummy read. FSET I ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG ; Push Flag register onto stack FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. POPC FLG ; Enable interrupts. The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. (5) Rewrite the interrupt control register
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow:
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET Noise (1) Insert the by-pass condencer to the Vcc-Vss line for preventing a noise and latch-up. Connect the by -pass condencer (about 0.1µF) between Vcc pin and Vss pin. It is distance must be shortest rather sicker line.

Electrical characteristics

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 239 Rev.1.0 Table.ZA-1 Absolute maximum ratings V VAVcc Vcc VCC =AV CC VCC =AV CC Symbol Parameter Condition Rated value Unit Supply voltage -0.3 to 4.6 -0.3 to 4.6Analog Supply voltage -0.3 to Vcc+0.3 VVI Input voltage VO -0.3 to Vcc+0.3 V P60 to P63,P70 to P77,P80 to P85 P130 to P137 -0.3 to 5.8 V output voltage Pd Ta=25 Tstg Topr mW -40 to 125 300 -20 to 85 C C P60 to P63,P70 to P77, P80 to P84 P130 to P137 -0.3 to 5.8 V C Power dissipation Operating ambient temperature Storage temperature RESET,M0,M1,V REF ,XIN,P00 to P07, P10 to P17,P20 to P27,P30 to P37, P40 to P47,P50 to P57,P64 to P67 P86,P87,P90 to P97,P100 to P107, P110 to P117,P120 to P127, P140 to P147,P150 to P157,P160,P161 P00 to P07,P10 to P17,P20 to P27, P30 to P37,P40 to P47,P50 to P57, P64 to P67,P86,P87,P90 to P97, P100 to P107,P110 to P117,P120 to P127, P140 to P147,P150 to P157,P160 ,P161,XOUT

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 240 Rev.1.0 Table.ZA-2 Recommended operating conditions (referenced to Vcc=3.0V to 3.6V,Ta= -20 to 85oC) Typ. Max. Unit Vcc Supply voltage Min. Standard V Symbol Parameter 3.0 3.6 3.3 Analog Supply voltage VccAVcc V V 0

0 Analog Supply voltage

0.8Vcc V VVcc "H" input voltage V0.8Vcc 5.5P60 to P63, P70 to P77,P80 to P84,P85,P130 to P137, PSA 0 to PSA2, PSB0 to PSB2 LAD 0 to LAD3,LFARAME,LCLK,SERIRQ,CLKRUN 0.6Vcc Vcc V I2C-BUS input level selected SMBUS input level selected SDA 0,SCL0,SDA1,SCL1,P60 to P63 0.7Vcc 5.5 1.4 5.5 V VIL 0V 0.2Vcc "L" input voltage P00 to P07, P10 to P17,P20 to P27, P30 to P37,P40 to P47, P50 to P57, P64 to P67,P86,P87,P90 to P97, P100 to P107, P110 to P117, P120 to P127,P140 to P147, P150 to P157, P160,P161,XIN, RESET, M0,M1 P00 to P07, P10 to P17,P20 to P27, P30 to P37,P40 to P47, P50 to P57, P64 to P67,P86,P87,P90 to P97, P100 to P107, P110 to P117, P120 to P127,P140 to P147, P150 to P157, P160,P161,XIN, RESET, M0,M1 V 0P60 to P63, P70 to P77,P80 to P84,P85,P130 to P137, PSA 0 to PSA2, PSB0 to PSB2 LAD 0 to LAD3,LFARAME,LCLK,SERIRQ,CLKRUN 0 0.2Vcc V I2C-BUSes input level selected SMBUS input level selected SDA 0,SCL0,SDA1,SCL1,P60 to P63 0 0.3Vcc 0 0.6 V 0.2Vcc

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 241 Rev.1.0 Table.ZA-3 Recommended operating conditions (referenced to Vcc=3.0V to 3.6V,Ta= -20 to 85oC) Typ. Max. UnitMin. Standard mAIOH (peak) "H"peak output current -10.0 Symbol Parameter mAIOL (peak) "L"peak output current 10.0 IOH (avg) "H" average output current IOL (peak) "L"peak output current P140 to P143 Driven ability:High Driven ability:Low 20.0 10.0 mA mA 0 to P07, P10 to P17,P20 to P27,P30 to P37, P40 to P47,P50 to P57,P60 to P67,P86 to P87,P90 to P97, P100 to P107, P110 to P117, P120 to P127,P140 to P147, P150 to P157,P160,P161 mA -5.0 f (XIN) Main clock input oscillation frequency f (XcIN) Subclock oscillation frequency kHz50 32.768 With wait Non wait 0 MHz MHz mAI OL (avg) "L"average output current 5.0 P00 to P07, P10 to P17,P20 to P23,P30 to P37, P40 to P47, P50 to P57,P60 to P67,P76 to P77,P80 to P84, P86 to P87, P90 to P97,P100 to P107,P110 to P117,P120 to P127, P130 to P137,P140 to P147,P150 to P157,P160,P161 P24 to P27 15.0 mA IOL (avg) "L"average output current P140 to P143 Driven ability:High Driven ability:Low 15.0 5.0 mA mA Note1 : The average output current is the average value during the 100ms period limited current. Note2 : The value are as follow: The sum of IOL (peak) of P0,P1,P2,P86 to P87,P9,P10,P11,P120 to P126,P153 to P157 P16 should be under 80mA. The sum of IOH (peak) of P0,P1,P2,P86 to P87,P9,P10,P11,P120 to P126,P153 to P157 P16 should be under 80mA. The sum of IOL (peak) of P3,P4,P5,P6,P7,P80 to P84,P13,P14,P150 to P152 should be under 80mA. The sum of IOH (peak) of P3,P4,P5,P64 to P67,P14,P150 to P152 should be under 80mA. P00 to P07, P10 to P17,P20 to P27,P30 to P37,P40 to P47, P50 to P57,P64 to P67,P86 to P87,P90 to P97,P100 to P107, P110 to P117, P120 to P127,P140 to P147,P150 to P157, P160,P161 P00 to P07, P10 to P17,P20 to P23,P30 to P37,P40 to P47, P50 to P57,P60 to P67,P76 to P77,P80 to P84, P86 to P87, P90 to P97,P100 to P107, P110 to P117,P120 to P127, P130 to P137,P144 to P147, P150 to P157,P160,P161 P24 to P27 20.0 mA

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 242 Rev.1.0 Symbol VOH VOH VOL VOL VOL VT +VT - VT +VT - IIH IIL R PULLUP R fXIN R fXCIN V RAM I CC Max. 0.5 0.5 0.5 0.5 0.5 0.5 0.8 1.8 4.0 -4.0 500.0 24.25 3.0 60.0 Unit V V V V V V V V V V µA µA kΩ M Ω M Ω V mA µA µA µA µA µA µA Parameter P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P86, P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, P140 to P147, P150 to P157, P160, P161 XOUT HIGH POWER LOWPOWER XCOUT HIGHPOWER LOWPOWER P00 to P07, P10 to P17, P20 to P23, P30 to P37, P40 to P47,P50 to P57, P60 to P67, P70 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, P130 to P137, P140 to P147, P150 to P157, P160, P161 P24 to P27 P140 to P143 HIGH POWER LOWPOWER XOUT HIGH POWER LOWPOWER XCOUT HIGHPOWER LOWPOWER TA0 IN to TA4IN, TB0IN to TB5IN, INT0 to INT11, AD TRG , CTS0, CTS1, CTS2, CLK0, CLK1, CLK 2, CLK3, CLK4, SIN3, SIN4, RXD0, RXD1, RXD 2, ICCK, NMI, KI00 to KI07 RESET P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, P120 to P127, P130 to P137, P140 to P147, P150 to P157, P160, P161, XIN, RESET, M0, M1 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, P130 to P137, P140 to P147, P150 to P157, P160, P161, XIN, RESET, M0, M1 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P86, P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, P140 to P147, P150 to P157, P160, P161 XIN XCIN When reset, the output pins are opened , the other pins are connected to Vss. Standard High output voltage High output voltage High output voltage Low output voltage Low output voltage Low output voltage Low output voltage Hysteresis Hysteresis HIGH input current Low input current Pull-up resisitance Feedback resistance Feedback resistance RAM retention voltage Power supply current Min. 2.5 2.5 2.5 0.2 0.2 66.0 2.0 Measuring condition IOH =-1mA IOH =-0.1mA IOH =-50µA With no load applied With no load applied IOL =1mA VCC =3V, IOL =3mA IOL =3mA IOL =1mA IOH =0.1mA IOH =50µA With no load applied With no load applied VI=3V VI=0V VI=0V When clock is stopped f(XIN)=8MH Z,Square wave without division f(XCIN)=32kHZ,Square wave When operation under RAM f(XCIN)=32kHZ,Square wave When operation under Flash memory f(XCIN)=32kHZ,With WAIT oscillation capacity High (Note1) f(XCIN)=32kHZ,With WAIT oscillation capacity Low (Note1) Ta=25°C When clock is stopprd Ta=85°C When clock is stopprd Typ. 3.0 1.6 120.0 3.0 10.0 12.5 40.0 300.0 4.5 2.5 Table.ZA-4 Electorical characteristice (referenced to Vcc=3.0V,Vss=0V,Ta=25oC,f(XIN)=8MHz with WAIT)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 243 Rev.1.0 Table.ZA-5 A-D conversion characteristics (referenced to Vcc=AVcc=VREF =3V,Vss=AVss=0V at Ta=25oC,f(XIN)=8MHz unless otherwise specified) Table.ZA-6 D-A conversion characteristics (referenced to Vcc=AVcc=VREF =3V,Vss=AVss=0V at Ta=25oC,f(XIN)=8MHz unless otherwise specified) tsu R O Resolution Absolute accuracy Setup time Output resistance Reference power supply input current Bits kΩ mAIVREF 1.0 1.0 20104 (Note1) µs Standard Min. Typ. Max. Resolution Absolute accuracy Bits LSB VREF =V CC Symbol Parameter Measuring condition Unit VREF =V CC =3V, Ø AD =fAD /2 R LADDER Ladder resistance kΩ10 40 Conversion time µs12.25tCONV VREF =V CC Reference voltage Analog input voltage V VIA VREF V

2.7 VCC

Min. Typ. Max.Symbol Parameter Measuring condition Unit Note1: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to "0016". The A-D converter's ladder resistance is not included. When the content of D-A register is not "00", the IVREF will also be sent even if VREF is disconnected. TCONV VIA Resolution Absolute accuracy Conversion time Analog input voltage Ladder resistance Bits LSB V kΩR LADDER 3.5 VCC0 µs Standard Min. Typ. Max.Symbol Parameter Measuring condition Unit when f(XIN) = 8MHz when f(XIN) = 4MHz 7 µs IIA Analog input current 5.0 µs 20 40 8 bit 10 bit 8 bit 10 bit 14.75 LSB µs V Table.ZA-7 Comparator characteristics (referenced to Vcc=AVcc=VREF =3V to 3.6V,Vss=AVss=0V at Ta=25oC)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 244 Rev.1.0 Table.ZA-8 External clock input Timing requirements (referenced to Vcc=3V,Vss=0V at Ta=25oC unless otherwise specified) Max. External clock rising timetr Min. External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock falling time ns ns ns tc tw(H) tw(L) tf ParameterSymbol Unit Standard ns ns 125

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 245 Rev.1.0 Table.ZA-9 Timer A input (The count input of event counter mode) Timing requirements (referenced to Vcc=3V,Vss=0V at Ta=25oC unless otherwise specified) Standard Max. nsTAiIN input "L" pulse widthtw(TAL) ns ns Unit ns ns ns ns ns ns ns ns ns ns ns ns ns TAiIN input "H" pulse widthtw(TAH) ParameterSymbol TAiIN input cycle time TAiIN input "H" pulse width TAiIN input "L" pulse width tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input "H" pulse width TAiIN input "L" pulse width tc(TA) tw(TAH) tw(TAL) tw(TAH) tw(TAL) TAiIN input "H" pulse width TAiIN input "L" pulse width tc(TA) TAiIN input cycle time TAiOUT input cycle time TAiOUT input "H" pulse width TAiOUT input "L" pulse width TAiOUT input setup time TAiOUT input hold time tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) Min. Standard Max. UnitParameterSymbol Min. Standard Max. UnitParameterSymbol Min. Standard Max. UnitParameterSymbol Min. Standard Max. UnitParameterSymbol Min. 150 600 300 300 300 150 150 150 150 3000 1500 1500 600 600 Table.ZA-10 Timer A input (The gating input of timer mode) Table.ZA-11 Timer A input (The external trigger input of one shot timer mode) Table.ZA-12 Timer A input (The external trigger input of pulse width modulation mode) Table.ZA-13 Timer A input (The up down input of event counter mode)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 246 Rev.1.0 Table.ZA-14 Timer B input (The count input of event counter mode) Timing requirements (referenced to Vcc=3V,Vss=0V at Ta=25oC unless otherwise specified) TBiINinput cycle time (single edge count) TBiINinput "H" pulse width (single edge count) TBiIN input "L" pulse width (single edge count) ns ns ns tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBL) tw(TBH) ns ns ns TBiIN input "H" pulse width (double edge count) TBiIN input "L" pulse width (double edge count) TBiIN input cycle time (double edge count) ns ns tc(TB) tw(TBH) tw(TBL) ns TBiIN input "H" pulse width TBiIN input cycle time TBiIN input "L" pulse width ns ns tc(TB) tw(TBL) ns tw(TBH) TBiIN input cycle time TBiIN input "H" pulse width TBiIN input "L" pulse width AD TRG input cycle time (The Min. of trigger) ns ns tc(AD) tw(ADL) AD TRG input "L" pulse width INTi input "H" pulse width INTi input "L" pulse width ns ns tw(INH) tw(INL) CLKi input cycle time CLKi input "H" pulse width CLKi input "L" pulse width ns ns ns tc(CK) tw(CKH) tw(CKL) td(C-Q) tsu(D-C) th(C-Q) ns ns ns TxDi hold time RxDi input setup time TxDi output delay time th(C-D) nsRxDi input hold time Standard Max. UnitParameterSymbol Min. Standard Max. UnitParameterSymbol Min. Standard Max. UnitParameterSymbol Min. Standard Max. UnitParameterSymbol Min. Standard Max. UnitParameterSymbol Min. Standard Max. UnitParameterSymbol Min. 150 160 160 300 600 300 300 600 300 300 1500 200 380 380 300 150 150 160 Table.ZA-15 Timer B input (Pulse period measurement mode) Table.ZA-16 Timer B input (Pulse width measurement mode) Table.ZA-17 A-D trigger input Table.ZA-18 Serial I/O Table.ZA-19 External interrupt INTi input

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 247 Rev.1.0 Table. ZA-20 Multi-master I2C-BUS line Symbol tBUF tHD;STA tLOW tR tHD;DAT tHIGH tF tsu;DAT tsu;STA tsu;STO Parameter Bus free time The hold time in start condition The hold time in SCL clock "0" status SCL, SDA signals' rising time Data hold time The hold time in SCL clock "1" status SCL, SDA signals' falling time Data setup time The setup time in restart condition Stop condition setup time Unit µ s µ s µ s ns µ s µ s ns ns µ s µ s Max. 300 0.9 300 Standard clock mode Min. 1.3 0.6 1.3 20+0.1Cb 0.6 20+0.1Cb 100 0.6 0.6 Max. 1000 300 High-speed clock mode Table. ZA-21 PS2 interface (referenced to Vcc = 3.0 to 3.6V, Vss = 0V, Ta =25 °C) Symbol twL twH tsu th td tv Parameter PS2 clock "L" pulse width PS2 clock "H" pulse width PS2 data setup time PS2 data hold time PS2 data delay time PS2 data valid time Unit µ s µ s µ s ns µ s µ s Max. twL-5 twL-5 Typ.Min. Timing requirements (referenced to Vcc = 3.0 to 3.6V, Vss = 0V, Ta =25 °C) Table. ZA-22 LPC bus interface/serial interrupt output StandardParameter Min. Symbol Unit LCLK clock input cycle time LCLK clock input "H" pulse width LCLK clock input "L" pulse width Input setup time LAD 3-LAD 0 LFRAME SERIRQ,CLKRUN LAD 3-LAD0,SERIRQ,CLKRUN , LFRAME input hold time LAD 3-LAD 0,SERIRQ,CLKRUN output delay time LAD 3-LAD0,SERIRQ,CLKRUN floating output delay time Typ. Max. ns ns ns ns ns ns ns ns tC(CLK) tWH(CLK) tWL(CLK) tsu(D-C) th(C-D) tV(C-D) toff(A-F) Min. 4.7 4.0 4.7 4.0 250 4.7 4.0 Standard

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 248 Rev.1.0 P10 30pF P16 P11 P12 P13 P14 P15 Fig.ZA-1 The measuring circuit for port 0 to port 16

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 249 Rev.1.0 tsu(D-C) TAiIN input TAiOUT input Inevent counter mode TBiIN input AD TRG input CLK i TxD i RxD i tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) INTi input td(C-Q) th(C-D) th(C-Q) th(TIN-UP) tsu(UP-TIN) TAiIN input (when selecting the fulling edge count) TAiIN input (when selecting the rising edge count) TAiOUT input (Up down input) Fig.ZA-2 Timing diagram (1)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 250 Rev.1.0 tBUF tHD:STA tHD:DTA tLOW tR tF tHIGH tsu:DAT tsu:STA tHD:STA tsu:STO SCL p S Sr p SDA Fig.ZA-3 Timing diagram (2) Fig.ZA-4 Timing diagram (3) PS/2 interface timing diagram CLK In receiving tWH tWL tsu DATA th 0.8VCC In transmitting CLK DATA tv 0.8VCC 0.2VCC 0.2VCC 0.8VCC 0.2VCC tWL tWH 0.8VCC 0.2VCC 0.2VCC 0.8VCC 0.2VCC 0.8VCC 0.2VCC td 0.8VCC 0.2VCC 0.8VCC 0.2VCC

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 251 Rev.1.0 Fig.ZA-5 Timing diagram (4) tWH (CLK) tWL (CLK) tC (CLK) tsu(D-C) th(C-D) tv(C-D) VIH VIL toff(A-F) LCLK LAD[3:0] SERIRQ,CLKRUN,LFRAME (Input) LAD[3:0] SERIRQ,CLKRUN,LFRAME (Active output) LAD[3:0] SERIRQ,CLKRUN,LFRAME (Floating output ) LPC bus interface/serial interrupt output timing

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 252 Rev.1.0 Table.AB-1 Feature outline of M16C/6K7 (build-in NEW DINOR flash memory version) Feature Outline Table AB-1 shows the feature outline of M16C/6K7 (build-in NEW DINOR flash memory version). Item Feature Power supply voltage 3.0-3.6V (f(X IN)=8MHz, 0 Wait) Flash memory operation mode 3 modes (parallel I/O, standard serial I/O, CPU reprogram) Erase block division User ROM area See Fig.AB-1 Boot ROM area 1 division (4K bytes) (Note1) Program method 2-byte unit Erase method Block erase Program/ erase control method Program/ erase controlled by s/w commands Number of command 5 commands Program/ erase count 100 times ROM code protect Support for parallel I/O and standard serial I/O modes Note1: The control program for standard serial I/O mode is stored in boot ROM area when shipping from factory. The area can only be erased or programmed by parallel I/O mode.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 253 Rev.1.0 Flash Memory The M16C/6K7 (build-in flash memory version) contains the NEW DINOR type flash memory, which is applied 1 power supplies VCC =3.3V when using CPU reprogram or standard serial I/O mode. For the flash memory, 3 flash memory modes are available in which to read, program and erase. They are parallel I/O mode, standard serial I/O mode and CPU reprogram mode. For parallel I/O mode, a programmer is used. For standard serial I/O and CPU reprogram modes, the flash memory is manipulated by CPU. Each mode is detailed in the pages to follow. Fig. AB-1 shows that flash memory is divided into several blocks. Erasing is in block unit. In addition to the ordinary user ROM area there is a boot ROM area to store the control program for the CPU reprogram and standard serial I/O modes. The control program for standard serial I/O mode is stored in boot ROM area when shipping from factory. User can reprogram the program to suit its own application system. The area can only be erased or programmed by parallel I/O mode. Fig.AB-1 Block diagram of flash memory version Chip name The start address of the flash memory M306K7F8L 0EF000 16 0F800016 Block 3 : 32K bytes Block 2 : 24K bytes 0FE000 16 Block 1 : 4K bytes Block 0 : 4K bytes 0FF00016 User block area 4K bytes 0FF00016 0FFFFF 16 0FFFFF 16 Boot block area Note 1: Boot ROM area can be reprogrammed only in parallel I/O mode. (Access to any other areas is inhibited.) Note 2: To specify a block, use the maximum even address in the block. Block 4 : 4K bytes0EF000 16 0F000016

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 254 Rev.1.0 CPU reprogram mode In CPU reprogram mode, the on-chip flash memory can be operated on (read, program or erase) under the control of CPU. In CPU reprogram mode, only the user ROM area shown in Fig.AB-1 can be reprogrammed. The boot ROM area cannot be reprogrammed. Make sure the program and block erase commands are issued only for each block of the user ROM area. The control program for CPU reprogram mode can be stored in either user ROM or boot ROM area. In CPU reprogram mode, because the flash memory cannot be read form CPU, the control program must be transferred to the RAM area before execution. Microcomputer mode and Boot mode The control program for CPU reprogram mode must be written into the user ROM or boot ROM area in parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard serial I/ O mode becomes disable.) See Fig.AB-1 for details about the boot ROM area. Normal microcomputer mode is entered when reset with pulling “L” of M 0. In this case, the CPU starts operating the control program in user ROM area. If the microcomputer is reset with M 0 being “H” and M1 being “L”, the CPU starts operating the control program in boot ROM area. This mode is called as “boot” mode. Block address Block address refers to the maximum even address of each block. The address is used in block erase command.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 255 Rev.1.0 Feature Outline (CPU reprogram mode) In CPU reprogram mode, the CPU erases, programs and reads the on-chip flash memory as instructed by S/W commands. The reprogram control program must be transferred to the RAM area before it can be executed. The CPU reprogram mode is accessed by writing “1” to the CPU reprogram select bit (bit 1 in address 03B7 16). S/W commands are accepted once the mode is accessed. In CPU reprogram mode, the writing and reading of the commands and data should be in even address (“0” for byte address A0) in 16-bit unit, so the 8-bit unit S/W commands should be written in even address. Commands are ignored with odd address. Use S/W commands to control flash memory programming and erasing. Whether the programming and erasing operation terminates correctly or in error can be verified by reading the status register. Fig.BB-1 shows the flash control register. Bit 0 is the RY/BY status flag exclusively used to read the operating status of the flash memory. During programming and erasing operation, it is “0”, otherwise it is “1”. Bit 1 is the CPU reprogram mode select bit. When the bit is set to “1”, CPU reprogram mode is entered S/W commands then can be accessed. In CPU reprogram mode, the CPU cannot access the on-chip flash memory directly. Therefore, use the control program in RAM to write the bit to “1”. To set the bit, it is necessary to write “0” and then write “1” in succession. The bit can be cleared to “0” by only writing the “0”. Bit 3 is the flash memory reset bit used to reset the control circuit of the on-chip flash memory. The bit is used when exiting the CPU reprogram mode and when flash memory access has failed. When the CPU reprogram mode select bit is “1”, writing “1” to the bit resets the control circuit. To release the reset, it is necessary to set the bit to “0”. If the control circuit is reset while erasing is in progress, the wait for 5 ms is needed so that the flash memory can restore to the normal operation. Bit 5 of the flash control register 0 is the user ROM select bit. It is enabled only in boot mode. When the bit is set to “1”, the accessed area is switched from boot ROM to user ROM. When CPU reprogram mode is entered in boot mode, please set this bit to “1”. The bit is disabled when program starts in user ROM. Please write the bit with the program that is not located in on-chip flash memory area. Fig.BB-2 shows a flowchart for the setting/ releasing the CPU reprogram mode.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 256 Rev.1.0 Fig.BB-1 The structure of flash memory control register and flash memory identification register Flash memory control register Symbol Address When reset FMR 03B7 16 XXXX0001 2 W R b7 b6 b5 b4 b3 b2 b1 b0 RY/BY signal status bitFMR0 Bit symbol Bit name Function RW 0: Busy (be written and erased) 1: Ready CPU reprogram mode select bit (Note 1) 0: Normal mode 1: CPU reprogram mode FMR1 0: Access to boot ROM area 1: Access to user ROM area Flash memory reset bit (Note 2) 0: Normal operation 1: Reset Nothing is assigned. When write, set “0”. When read, values is indeterminate. User ROM area select bit (Note 3) (Only enabled in boot mode) Reserved bit FMR3 FMR5 Note 1: To write “1” to the bit, it is necessary to write “0” and “1” in succession. Otherwise the bit will not be “1”. Please do not enter interrupt and DMA. Note 2: It is enabled only CPU reprogram mode select bit is “1”. After setting to “1”(reset), please write “0” in succession. Note 3: Please write this bit with program that is not located in on-chip flash memory area. /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Must be “0”. Reserved bit /LiteDiagLines/LiteDiagLines/LiteDiagLines Must be “0”. Flash memory identification register b7 b6 b5 b4 b3 b2 b1 b0 Function RW The value after reset 000000002 : M16C/6K7 Group XXXX00012 : M16C/6K5 Group (Note) Note: Address 03B416 of M16C/6K5 Group is the flash memory control register. Symbol Address When reset FTR 03B4 16 000000002 /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 257 Rev.1.0 Fig.BB-2 CPU reprogram mode set/reset flowchart Note 1: Set the main clock frequency as shown below using the main clock divide ratio select bits (bit 6 at address 000616 and bit 6 and 7 at address 000716): Not exceeding 8 MHz if wait bit (bit 7 of address 000516) = "0". (No wait for internal accessing) Note 2: For writing "1" to the bit, it is necessary to write "0" and "1" in succession. Otherwise the bit will not be "1". Please do not enter interrupt and DAM. Note 3: Be sure to execute a read command or to set flash memory reset bit before exiting the CPU reprogram mode after completing erasing or programming operation. Note 4: The bit can remain "1" too. If it is "1", user ROM area will be accessed. Start Single-chip mode or boot mode Set processor mode register (Note 1) Jump to the program that is transferred to RAM (the operation hereafter is on RAM) Transfer CPU reprogram mode control program to RAM area Program located in ROM Set CPU reprogram mode select bit="1" (write "0" and then write "1") (Note 2) Reset with read array command or the setting of the flash memory reset bit (write "1" and then write "0") (Note 3) Operate with S/W commands to erase and program. Write "0" to CPU reprogram mode select bit. (Only for boot mode) Write user ROM area select bit to "0". (Note 4) End Program located in RAM (Only for boot mode) Set user ROM area select bit to "1"

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 258 Rev.1.0 Precautions on CPU reprogram mode Described below are the precautions to be observed in programming the flash memory in CPU reprogram mode. (1) Operation speed During CPU reprogram mode, set the main clock frequency as shown below using the main clock divide ratio select bits (bit 6 at address 0006 16 and bit 6 and 7 at address 000716): Not exceeding 8MHz if wait bit (bit 7 of address 000516) = “0”. (No wait for internal accessing) (2) Instructions inhibited against use The instructions listed below cannot be used during CPU reprogram mode because they refer to the internal data of the flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction and BRK instruction (3) Interrupts inhibited against use The NMI, address match and WDC interrupts cannot be used during CPU reprogram mode because they refer to the internal data of the flash memory. If interrupts have their vectors in the variable vector table, they can be used by transferring the vector into the RAM area. (4) Reset The reset is always receivable. (5) The reprogram in user ROM area When CPU reprogram mode is entered and the block that the flash reprogram control program is located is being reprogramming, the block may not be reprogrammed correctly if the power supply is suddenly down. It is possible that the flash reprogram cannot be executed again in this case. Thus, it is recommended to use standard serial I/O mode and parallel I/O mode.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 259 Rev.1.0 Software commands Table BB-1 lists the S/W commands available. After setting the CPU reprogram mode select bit to “1”, the S/W commands can be used to specify the erasing or programming operation. Note that when entering a S/W command, the upper byte (D15–D 8) is ignored. The content of each S/W command is explained below. Read Array Command (FF16) Issuing the command code “FF16” in the 1st bus cycle enters the read array mode. When an even address is issued in one of the bus cycle that follows, the content of the address is read out at the data bus (D15–D 0), 16 bits at a time. The read array mode is retained intact until another command is written. Read Status Register Command (7016) When the command code “7016” is issued in the 1st bus cycle, the content of the status register is read out at the data bus (D7–D 0) by a read in the 2nd bus cycle. The status register is explained in the next section. Clear Status Register Command (50 16) The command is used to clear the bits SR4 and SR5 of the status register after they have been set. These bits indicate that operation has ended in error. To use this command, issue the command code “5016” in the 1st bus cycle. Table BB-1 List of software commands (CPU reprogram mode) Command Read array Read status register Clear status register Program Block erase Write Write Write Write Write X (Note 5) X X X X Data (D15–D 0) FF16 7016 5016 4016 2016 Read Write Write X WA (Note 3) BA (Note 4) Data (D15–D 0) SRD (Note 2) WD (Note 3) D0 16 The 2nd bus cycleThe 1st bus cycleCycle number Mode Address Mode Address Note 1: When a S/W command is input, the high-order byte of the data(D15–D 8) is ignored. Note 2: SRD = Status Register Data Note 3: WA = Write Address, WD = Write Data Note 4: BA = Block Address (the maximum even address of the block) Note 5: “X” can be any even address in user ROM area.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 260 Rev.1.0 Fig.BB-3 Program flowchart Program Command (40 16) Program operation starts when the command code “4016” is issued in the 1st bus cycle. If the address and data are issued in the 2nd bus cycle, program operation (data programming and verification) will start. Whether the program operation is completed can be conformed by reading the status register or the RY/BY status flag. When the program starts, the read status register mode is accessed automatically and the content of the status register can be read on the date bus (D 7–D 0). The status register bit 7 (SR7) is set to “0” at the same time when the program operation starts and is returned to “1” upon the completion of the program operation. In this case, the read status register mode remains active until the Read Array Command (FF 16) is issued. The RY/BY status flag is “0” during program operation and “1” when the program operation is completed same as the status register bit 7. After the program, reading the status register can check the result. Refer to the section where the status register is detailed. Start Write 4016 Status register read YES NO Program completed Write address Write dataWrite SR4=0? NO YES Program error SR7=1? or RY/BY=1?

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 261 Rev.1.0 Fig.BB-4 Erase flowchart Start Write 2016 Status register read YES NO Erase completed Write D016 Block address SR5=0? NO YES Erase error D0 16 : Block erase SR7=1? or RY/BY=1? Block Erase Command (2016/D016) By issuing the command code “2016” in the 1st bus cycle and the conformation command code “D0 16” and block address in the 2nd bus cycle, the erase operation specified by the block address starts (erase and erase verification). Whether the block erase command is terminated can be conformed by reading the status register or the RY/BY status flag. When the block erase operation starts, the read status register mode is accessed automatically and the content of the status register can be read out. The status register bit 7 (SR7) is set to “0” at the same time when the erase operation starts and is returned to “1” upon the completion of the erase operation. In this case, the read status register mode remains active until the Read Array Command (FF16) is written. The RY/BY status flag is “0” during erase operation and “1” when the erase operation is completed the same as the bit 7 of status register. After the block erase, reading the status register can check the result. Refer to the section where the status register is detailed.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 262 Rev.1.0 Status register The status register shows the operation status of the flash memory and whether program and erase operations end successfully or not. It can be read in the following conditions. (1) By reading an arbitrary address from the user ROM area after issuing the read status register command (70 16) (2) By reading an arbitrary address from the user ROM area in the period from the start of program or erase operation to the execution of read array command (FF 16). Table BB-2 shows the status register. The status register can be cleared in the following condition. (1) By issuing the clear status register command (50 16). (2) After reset, the status register is set to “8016”. Each bit of the register is shows below. Sequencer status (SR7) After power-on, the sequencer status is set to “1” (ready). The bit is set to “0” (busy) during program and erase operations and is set to “1” upon the completion of these operations. Erase status (SR5) Erase status indicates the status of erase operation. When erase error occurs, it is set to “1”. The bit becomes “0” when it is cleared. Program status (SR4) Program status indicates the status of program operation. When program error occurs, it is set to “1”. The bit becomes “0” when it is cleared. If “1” is set to SR5 or SR4, the program and block erase operations are not accepted. Before execution of these commands, it is necessary to execute the clear status register command (50 16) to clear the status register. If any S/W commands are not correct, both the SR5 and SR4 are set to “1”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 263 Rev.1.0 Table BB-2 Definition of each bit of status register Read status register SR4=1 and SR5=1? NO Command sequence error YES SR5=0? YES Block erase errorNO SR4=0? YES Program error NO End (block erase, program) Execute the clear status register command (5016) to clear the status register. Try to perform the operation again after conforming that the command is entered correctly. Should block erase error occur, the block cannot be used. Should program error occur, the block cannot be used. Note: When SR5 or SR4 is set to “1”, neither of the program nor block erase commands are accepted. Execute the clear status register command (5016) before executing these comm ands. Full status check By performing full status check, the execution result of erase and program operations can be known. Fig.BB-5 shows the full status check flowchart and the method to deal with the error. Fig.BB-5 Full status check flowchart and the method to deal with errors Each bit of SRD SR4 (bit4) SR5 (bit5) SR7 (bit7) SR6 (bit6) Status name Definition SR1 (bit1) SR2 (bit2) SR3 (bit3) SR0 (bit0) "1" "0" Program status Erase status Sequencer status Reserved Reserved Reserved Reserved Ready Busy Terminated in error Terminated in error Terminated normally Terminated normally Reserved --

Functions To Inhibit Rewriting Flash Memory Mitsubishi microcomputers M16C / 6K7 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 264 Rev.1.0 Functions to inhibit rewriting to the on-chip flash memory To prevent flash memory from being miss-read or miss-written, ROM code protect function for parallel I/O mode and ID code check function for standard serial mode are introduced. ROM code protect function ROM code protect function can inhibit readout from or modification to the flash memory by setting the content in ROM code protect control address (0FFFFF 16) for parallel I/O mode. Fig.BB-6 shows the content of ROM code protect control address (0FFFFF16). (The address exists in user ROM area.) If one of the pair of ROM code protect bits is set to “0”, ROM code protect is turned on, so that the flash memory is protected against the readout or modification. ROM code protect is implemented in two levels. If level 2 is selected, the flash memory is protected even against readout by a shipment inspection LSI tester, etc. When both level 1 and level 2 are set, level 2 will be selected. If both of the two ROM code protect reset bits are set to “00”, ROM code protect is turned off, so that the flash memory can be read out or modified. Once ROM code protect is turned on, the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial mode or other to rewrite these two bits. Fig.BB-6 ROM code protect control address ROM code protect control address Symbol Address When reset ROMCP 0FFFFF 16 FF16 b7 b6 b5 b4 b3 b2 b1 b0 Reserved bits Bit symbol Bit name Function Always set these bits to “1” ROM code protect level 2 set bits (Note 1,2) 0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled ROMCP2 Note 1: When ROM code protect is turned on, the on-chip flash memory is protected against readout or modification in parallel I/O mode. Note 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection LSI tester,etc. is also inhibited. Note 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and level 2. However,Since these bits can not be modified in parallel I/O mode, they should be rewritten in serial I/O mode or other modes. b3 b2 ROM code protect reset bits (Note 3) ROM code protect level 1 set bits (Note 1) 0 0: Protect removed 0 1: Protect set bits effective 1 0: Protect set bits effective 1 1: Protect set bits effective b5 b4 ROMCR 0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled b7 b6 ROMCP1

Functions To Inhibit Rewriting Flash Memory Mitsubishi microcomputers M16C / 6K7 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 265 Rev.1.0 ID code check function The function is used in standard serial I/O mode. If the flash memory is not blank, the ID code sent from serial burner is compared with that inside flash memory to check the agreement. It the ID codes do not match, the commands from serial burner are not accepted. Each ID code consists of 8-bit data, the areas of which, beginning from the 1 st byte, are 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, 0FFFFB 16. Write a program with the ID code at these addresses to the flash memory. Fig.BB-7 ROM ID code addresses Address 0FFFDC 16 to 0FFFDF16 ID1 Undefined instruction vector 0FFFE0 16 to 0FFFE316 ID2 Overflow vector 0FFFE4 16 to 0FFFE716 BRK instruction vector 0FFFE8 16 to 0FFFEB16 ID3 Address match vector 0FFFEC 16 to 0FFFEF16 ID4 Single step vector 0FFFF0 16 to 0FFFF316 ID5 Watchdog timer vector 0FFFF4 16 to 0FFFF716 ID6 DBC vector 0FFFF8 16 to 0FFFFB16 ID7 NMI vector 0FFFFC 16 to 0FFFFF16 Reset vector 4 bytes

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 266 Rev.1.0 Parallel I/O mode Parallel I/O mode is to input and output the software command, address and data in parallel to access the on-chip flash memory (read, program, erase etc.). Please use the specific device (programmer) supported for M16C/6K7 Group. Referring to the guideline etc. of each device manufacture for the usage. User ROM area and boot ROM area In parallel I/O mode, both user ROM area and boot ROM area showed in Fig.AB-1 can be reprogrammed. The access method to both areas is the same. The size of boot ROM area is 4K bytes. The addresses are allocated in 0FF000 16– 0FFFFF16. Make sure program and block erase operations are always performed within this address range. (Access to any location outside this address range is prohibited.) In the boot ROM area, erase block operation is applied to only one 4K bytes block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from Mitsubishi factory. Therefore, if the standard serial I/O mode is used, the rewriting to the boot ROM area is not necessary.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 267 Rev.1.0 Table EE-1 Pin function (Flash memory standard serial I/O mode) Pin name Name I/O VCC , VSS Power supply M0 M0 I RESET Reset input I XIN Clock input I XOUT Clock output O M1 M1 I AV CC , AVSS Analog power supply VREF Reference voltage I P00–P07 Input port P0 I P10–P17 Input port P1 I P20–P27 Input port P2 I P30–P37 Input port P3 I P40–P47 Input port P4 I P50–P57 Input port P5 I P60–P63 Input port P6 I P64 BUSY output O P65 SCLK input I P66 R XD input I P67 TXD input O P70–P77 Input port P7 I P80–P84 Input port P8 I P86,P87 P85 NMI input I P90–P97 Input port P9 I P100–P107 Input port P10 I P110–P117 Input port P11 I P120–P127 Input port P12 I P130–P137 Input port P13 I P140–P147 Input port P14 I P150–P157 Input port P15 I P160,P161 Input port P16 I Apply 3.3 ± 0.3V to VCC , apply 0V to VSS Connect to VCC Reset input pin. While reset is "L", 20 cycles or more clocks input to XIN pin are needed. Connect a ceramic resonator or crystal oscillator between XIN and XOUT . If external clock is used, input it to XIN pin and open the XOUT pin. Connect to VSS Connect AVSS to VSS , AVCC to VCC The input pin of reference voltage of AD converter Input "H", "L" or open Input "H", "L" or open Input "H", "L" or open Input "H", "L" or open Input "H", "L" or open Input "H", "L" or open Input "H", "L" or open The output pin of BUSY signal The input pin of serial clock The input pin if serial data The output pin of serial data Input "H", "L" or open Input "H", "L" or open Connect to VCC The input pin of serial data The input pin of serial data The input pin of serial data The input pin of serial data The input pin of serial data The input pin of serial data The input pin of serial data The input pin of serial data

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 268 Rev.1.0 Fig.EE-1 Pin connections for serial I/O mode BUSY RESET R XD SCLK TXD VSS VCC 1 2 3 4 5 6 7 8 91 01 11 21 31 41 51 61 71 81 92 02 12 22 32 42 5 108 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 10710610510410310210110099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 26 27 28 29 30 31 32 33 34 35 36 P00 P01 P02 P03 P04 P05 P06 P07 P13 P13 V CC V SS VREF AV SS AVcc P100/AN0 P101/AN1 P97/ADTRG /SIN4/INT60 V CCX IN X OUTV SS RESET M 7/X CIN 6/X COUT M 5/NMI 5/TA2 IN /INT 2/PS2B P46/PWM 21/OBF3 P45/PWM 11/OBF2 P47/PWM 31 P44/PWM 01/OBF1 /KI00P50 134 135 136 137 138 139 140 141 142 143 144 4/INT 1/PS2B 3/CTS /RTS /TA1 IN /INT 0/PS2B P15 P15 P15 P15 P13 P110 P16 1/TB4 1IN P15 P16 0/TB3 1IN P147/KI17 P146/KI16 P145/KI15 P144/KI14 P143/KI13 P142/KI12 P141/KI11 P140/KI10 P13 P13 P13 P13 P111 P112 P113 P114 P115 P116 P117 P120/INT61 P121/INT72 P122/INT82 6/ANEX1/S OUT4 /PWM 5/ANEX0/CLK 4/PWM VCC VSS 1/TA1 0OUT 2/R XD 1/CLK P13 P126 P125/INT111 P124/INT102 P123/INT92 P70/TXD 20/PS2A0 2/CLK /PS2A P63/TXD 00/SCL1 P65/CLK10 P66/RXD 10/TA3OUT /F1OUT0 P67/TXD 10/TA4OUT /F1OUT1 P61/CLK00/SCL0 P62/RXD 00/SDA1 P60/CTS00/RTS00/SDA0 P64/CTS10/RTS10 7/TA3 IN 1/S IN3 /INT 2/S OUT3 /INT 0/ICCK 2/TB0 IN 3/TB1 IN 0/CLK 3/INT 4/TB2 IN 1/TA4 IN 1/R XD /TA0 IN /TB5 IN /PS2A P102/AN2 P103/AN3/INT70 P107/AN7/INT110 P106/AN6/INT100 P105/AN5/INT90 P104/AN4/INT80 /CTS00/CLKS10 3/DA 0/TB3 0IN /PWM 4/DA 1/TB4 0IN /PWM P10/CTS01/RTS01 3/T XD 4/INT /CTS /RTS /CTS /CLKS 3/CTS /RTS 5/INT /CLK 0/T XD 6/INT XD 1/R XD 7/INT 101 XD 2/CLK P43/OBF01 P42/TA20OUT /GATE A20 P150/TA01OUT P151/TA11OUT P152/TA21OUT /KI01P51 /KI02P52 /KI03P53 /KI04P54 /KI05P55 /KI06P56 /CLKOUT /KI07P57 P12 /OBF Connect to oscillation circuit Mode setting method Name of signal line Value RESET VCC VSS VSS → VCC M306K7F8LRP (144PFB)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 269 Rev.1.0 Standard serial I/O mode The standard serial I/O mode inputs and outputs the S/W commands, addresses and data needed to operate (read, program, erase etc.) the on-chip flash memory with a dedicated serial programmer. Different from parallel I/O mode, in standard serial mode, CPU controls the flash memory reprogramming (uses the CPU reprogram mode) and the input of serial reprogram data etc. The standard serial I/O mode is started by connecting M 0 to “H ”, M1 to “L” with the release of reset. (To connect M0 to “L” in normal microcomputer mode.) This control program is written in boot ROM area when the product is shipped from Mitsubishi factory. Make sure that the standard serial I/O mode cannot be used if boot ROM area is written in parallel I/O mode. Fig EE-1 shows the pin connections for standard serial I/O mode. The input and output of serial data are processed in CLK 10, RxD10, TxD10, RTS10 (BUSY) 4 pins of the UART1. The CLK 10 is clock input pin, which clock is input externally. The TxD10 is CMOS output pin. The RTS10 (BUSY) pin outputs “L” when ready for reception and outputs “H ” when reception starts. The serial data are transferred in 8-bit unit. In standard serial I/O mode, only the user ROM area shown in Fig.AB-1 can be reprogrammed. Boot ROM area cannot be reprogrammed. In the standard serial I/O mode, a 7-byte ID code is used. If the flash memory is not blank, commands sent from programmer are not accepted unless the ID code matches.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 270 Rev.1.0 Outline (standard serial I/O mode) In standard serial I/O mode, S/W commands, addresses, and data etc. are input and output with the peripheral device (serial programmer) using 4-wire clock-synchronized serial I/O (UART1). In reception, S/W commands, addresses and program data are read from RxD 10 pin synchronized with the rising edge of the transfer clock that is input to the CLK10 pin. In transmission, the read data and status are output to TxD10 pin synchronized with the falling edge of the transfer clock. The TxD 10 is CMOS output pin. Transfer is in 8-bit unit with LSB first. During transmission, reception, erasing and programming, the RTS10 (BUSY) pin is “H ”. Accordingly, always start the next transfer after the RTS10 (BUSY) pin becomes “L”. The read after the input of S/W commands can get memory data and status register. Reading the status register can check the flash memory operation status, the normal/error end of erasing or programming operation. The following are the explanation of S/W commands, status register etc.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 271 Rev.1.0 S/W commands Table EE-2 lists the S/W commands. In standard serial I/O mode, the S/W commands, which transferred from RxD pin, control of erase, program and read etc. The S/W commands in standard serial I/O mode are similar with that in parallel I/O mode. ID check function, download function, version information output function, boot ROM area output function and read check data, 5 commands are added. Table EE-2 The list of S/W commands (standard serial I/O mode) Control 1 st byte 2 nd byte 3 rd byte 4 th byte 5 th byte 6 th byte – If ID command transfer unmatched

1 Page read FF 16 Address Address Data Data Data 259 th byte Not acceptable

(middle) (high) output output output data output

2 Page program 41 16 Address Address Data Data Data 259 th byte Not acceptable

(middle) (high) input input input data input

3 Block erase 20 16 Address Address D0 16 Not acceptable

(middle) (high)

4 Read 70 16 SRD SRD1 Acceptable

status register output output

5 Clear 50 16 Not acceptable

6 ID check F5 16 Address Address Address ID size ID1 –ID7 Acceptable

function (low) (middle) (high) 7 Download FA 16 Address Address Check Data No. of –ID7 Not acceptable function (low) (high) sum input times required

8 Version informationFB 16 Version Version Version Version Version –9th byte Acceptable

output function data output data output data output data output data output Version data output

9 Boot ROM area FC 16 Address Address Data Data Data –259th byte Not acceptable

output function (middle) (high) output output output data output

10 Read check FD 16 Check data Check data Not acceptable

data (low) (high) Note 1: Shading indicates transfer from flash memory on chip microcomputer to serial programmer. The else indicates transfer from serial programmer to flash memory on chip microcomputer. Note 2: SRD means status register data. SRD1 means status register 1 data. Note 3: All commands are acceptable if the flash memory is blank.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 272 Rev.1.0 The following are the descriptions of S/W commands Page read command The command reads the specified page (256 bytes) of the flash memory sequentially one byte at a time. Execute the page read command as following: (1) Transfer the “FF 16” command code in the 1st byte. (2) Transfer addresses A8– A15 and A16– A23 in the 2nd and 3rd byte respectively. (3) From the 4th byte onward, data (D7–D 0) of the page specified by the address (A23–A8) will be output sequentially from the smallest address sync with the falling edge of the clock. Fig.EE-2 Timing of page read Read status register command The command is for reading status information. When command code “7016” is sent in the 1st byte, the contents of status register (SRD) and status register 1 (SRD1) will be output in the 2nd and 3rd byte respectively sync with the falling edge of the clock. Fig.EE-3 Timing of read status register Data0 Data255 CLK 10 A8 to A15 A16 to A23FF16 RTS 10(BUSY) RxD 10 (M16C reception data) TxD 10 (M16C transmit data) SRD output SRD1 output 7016 CLK 10 RTS 10(BUSY) RxD 10 (M16C reception data) TxD 10 (M16C transmit data)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 273 Rev.1.0 Fig.EE-4 Timing of clear status register Page program command The command programs the specified page (256 bytes) of flash memory sequentially one byte a time. Execute the command as follows: (1) Transfer the command code “41 16” in the 1st byte. (2) Transfer addresses A15–A8 and A23–A16 in the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, after inputting 256 bytes program data (A7–A0) from the smallest address of the specified page, the page program operation will be executed automatically. When the reception for the next 256 bytes is setup, the RTS 10 (BUSY) signal changes from “H ” to “L”. The result of the page program can be known by reading the status register. For more detail, see the section on the status register. Fig.EE-5 Timing of page program Clear status register command The command clears the bits (SR4–SR5), which are set when operation ended in error. When command code “50 16” is sent in the 1st byte, the aforementioned bits are cleared. When the clear status register operation ends, the RTS10 (BUSY) signal changes from “H ” to “L”. 5016 CLK 10 RTS 10(BUSY) RxD 10 (M16C reception data) TxD 10 (M16C transmit data) A8 to A15 A16 to A234116 Data0 Data255 CLK 10 RTS 10(BUSY) RxD 10 (M16C reception data) TxD 10 (M16C transmit data)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 274 Rev.1.0 Block erase command The command erases the data in the specified block. Execute the command as follows: (1) Transfer the command code “20 16” in the 1st byte. (2) Transfer addresses A15–A8 and A23–A16 in the 2nd and 3rd bytes respectively. (3) After transferring the verify command code“D016” in the 4th byte, the erase operation starts for the specified block of the flash memory. Issue the biggest address of th2e specified block to A23–A8. After the completion of block erase, the RTS10 (BUSY) signal changes from “H ” to “L”. The result of the block erase can be know by reading the status register. For more detail, see the section on the status register. Fig.EE-6 Timing of block erase A8 to A15 A16 to A232016 D0 16 CLK 10 RTS 10(BUSY) RxD 10 (M16C reception data) TxD 10 (M16C transmit data)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 275 Rev.1.0 Download function The command downloads an execution program to RAM. Execute the command as follows: (1) Transfer the command code “FA 16” in the 1st byte. (2) Transfer the program size in the 2nd and 3rd bytes. (3) Transfer the checksum in the 4th byte. Check sum is calculated from all transferred data from the 5th byte onward. (4) The execution program is transferred from 5th byte onward. After the entire program data have been transferred, the downloaded execution program will be executed if the checksum matches. The program size allowed to transfer varies according to the size of on-chip RAM. Fig.EE-7 Timing of download function Data size (low) Data size (high)FA 16 Check sum Program data CLK 10 RTS 10(BUSY) RxD 10 (M16C reception data) TxD 10 (M16C transmit data) Program data

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 276 Rev.1.0 Fig.EE-8 Timing of version information output function Version information output function The version information of the control program stored in boot ROM area can be output by the function. Execute the command as follows: (1) Transfer the command code “FB 16” in the 1st byte. (2) From the 2nd byte onward, the version information will be output. The information is composed of 8 ASCII character code. Boot ROM area output function The control program stored in boot ROM area can be read out in page (256 bytes) unit by the function. Execute the command as follows: (1) Transfer the command code “FC 16” in the 1st byte. (2) Transfer addresses A15–A8 and A23–A16 in the 2nd and 3rd bytes respectively. From the 4th byte onward, the data (D7–D 0) specified in page (256 bytes) address A23–A8 will be output sequentially from the smallest address in sync with the rising edge of the clock. Fig.EE-9 Timing og boot ROM area output function FB 16 CLK 10 RTS 10(BUSY) RxD 10 (M16C reception data) TxD 10 (M16C transmit data) 'V' 'E' 'R' 'X' FC 16 CLK 10 RTS 10(BUSY) RxD 10 (M16C reception data) TxD 10 (M16C transmit data) Data0 Data255 A8 toA15 A16 toA23

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 277 Rev.1.0 Fig.EE-10 Timing of ID check function ID check function The command checks the ID code. Execute the command as follows: (1) Transfer the command code “F5 16” in the 1st byte. (2) Transfer addresses A7–A0, A15–A8 and A23–A16 of 1st ID code (ID1) in the 2nd, 3rd and 4th bytes respectively. (3) Transfer the number of the ID code in the 5 th byte. (4) From the 6th byte onward, transfer the IDs from the 1st ID code (ID1). Fig.EE-11 ID code addressed ID code If the flash memory is not blank, the input ID codes are compared with that written in flash memory. If they do not match, the input commands will not be accepted. Each ID code contains 8 bits data. Beginning from the st ID byte, the address of each ID code is 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16 respectively. Write the program with the ID codes in these addresses to the flash memory. F516 CLK 10 RTS 10(BUSY) RxD 10 (M16C reception data) TxD 10 (M16C transmit data) DF 16 FF16 0F16 IDsize ID1 ID7 Address 0FFFDC 16 to 0FFFDF16 ID1 Undefined instruction vector 0FFFE0 16 to 0FFFE316 ID2 Overflow vector 0FFFE4 16 to 0FFFE716 BRK instruction vector 0FFFE8 16 to 0FFFEB16 ID3 Address match vector 0FFFEC 16 to 0FFFEF16 ID4 Single step vector 0FFFF0 16 to 0FFFF316 ID5 Watchdog timer vector 0FFFF4 16 to 0FFFF716 ID6 DBC vector 0FFFF8 16 to 0FFFFB16 ID7 NMI vector 0FFFFC 16 to 0FFFFF16 Reset vector 4 bytes

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 278 Rev.1.0 Fig.EE-12 Timing of read check dt command Read check data Read check date command is for conforming if the reprogram data sent after page program command have been received correctly. (1) Transfer the command code “FD 16” in the 1st byte. (2) Transfer check data (low) and check data (high) in the 2nd and 3rd bytes respectively. When using read check data command, the command should be issued at first to initialize the check data. The next is to issue the page program command and related reprogram data. After that, by issuing the read check data command again, the check data for the reprogram data issued between the two read check data command can be read out. Adding the reprogram data in byte unit and then calculating the lower 2 bytes of the added data in two's complement gives out the check data. FD 16 CLK 10 RTS 10(BUSY) RxD 10 (M16C reception data) TxD 10 (M16C transmit data) Check data (low) Check data (high)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 279 Rev.1.0 Status register Status register indicates if the operation to the flash memory ends successfully or in error. It can be read by issuing the read status register command (70 16). The status register can be cleared by issuing the clear status register command (5016). Table EE-3 shows the definition of each bit of the register. After reset, status register outputs “80 16”. Table EE-3 Status register (SRD) Sequencer status (SR7) After power-on, the sequencer status is set to “1” (ready). The bit is set to “0” (busy) during program and erase operations and is set to “1” upon the completion of these operations. Erase status (SR5) Erase status indicates the status of erase operation. When erase error occurs, it is set to “1”. The bit becomes “0” when it is cleared. Program status (SR4) Program status indicates the status of program operation. When program error occurs, it is set to “1”. The bit becomes “0” when it is cleared. Symbol SR4 (D4) SR5 (D5) SR7 (D7) SR6 (D6) Status Definition SR1 (D1) SR2 (D2) SR3 (D3) SR0 (D0) "1" "0" Program status Erase status Sequencer status Reserved Reserved Reserved Reserved Reserved Ready Busy Terminated in error Terminated in error Terminated normally Terminated normally

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 280 Rev.1.0 Status register 1 (SRD1) Status register 1 indicates the status of serial communication, the result of ID codes comparison, the result of checksum comparison etc. It can be read after SDR by issuing the read status register command (70 16). The register can be cleared by issuing the clear status register command (5016). Table EE-4 shows the definition of each bit of the register. After power on, status register 1 outputs “00 16”. Table EE-4 Status register (SRD1) Boot update completed bit (SR15) The flag indicates that if the control program has been downloaded to RAM with download function. Check sum match bit (SR12) The flag indicates if the check sum is matched when downloading the control program with download function. ID check completed bits (SR11, SR10) These bits indicate the result of ID checks. Some commands cannot be accepted without the ID checks. Timeout of data reception bit (SR9) The flag indicates if timeout occurs during data reception. If the bit is set to “1” during data reception, microcomputer will discard the received data and return to wait state. Each bit of SRD SR12 (bit4) SR13 (bit5) SR15 (bit7) SR14 (bit6) Status name Definition SR9 (bit1) SR10 (bit2) SR11 (bit3) SR8 (bit0) "1" "0" Check sum match bit Reserved Boot update completed bit Reserved Timeout of data reception ID check completed bits Reserved Update completed Not update Match Mismatch

00 Not verified

01 Verified with mismatch

10 Reserved

11 Verified with match

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 281 Rev.1.0 Full status check By performing full status check, the execution result of erase and program operations can be known. Fig.EE- 13 shows the full status check flowchart and the method to deal with the error. Fig.EE-13 Full status check flowchart and the method to deal with errors Read status register SR4=1 ? and SR5=1 ? NO Command sequence error YES SR5=0? YES Block erase error NO SR4=0? YES Program error NO End (block erase, program) Execute the clear status register command (5016) to clear the status register. Try to perform the operation again after conforming that the commands is entered correctly. Should block erase error occur, the block can not be used. Should program error occur, the block can not be used. Note: When SR5 or SR4 is set to "1", neither of the program nor block erase commands are accepted. Execute the clear status register command (5016) before executing these commands.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 282 Rev.1.0 Circuit applied for standard serial I/O mode (example) The figure below shows a circuit applied for standard serial I/O mode. The control pins bary by different programmer. Refer to programmer manual for the detail. Fig.EE-14 Example circuit applied for the standard serial I/O mode Clock input BUSY output Data input Clock output CLK 10 RTS 10(BUSY) R XD 10 TXD 10 NMI M16C/6K7 (NEW DINOR type flash memory) The control pins and external circuitry vary by different programmer. Refer to programmer manual for the detail.

REVISION HISTORY M16C / 6K7 GROUP DATA SHEET Rev. Date Description Page Summary (1/1) 1.0 ’01.10.23 149 168 169 170 Misprints, omissions and text styles are revised. Table GF-1 is added. Explanation of “•OBF0 mergence function” is added. Explanation of Figure SI-5 is revised. Figure SI-6 is added. Explanation of “G Serial interrupt control register 2 SERCON2” is added. Figure SI-7 is added.

© 2001MITSUBISHI ELECTRIC CORP. New publication, effective Oct. 2001. Specifications subject to change without notice. Notes regarding these materials

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