M16C62PT

M16C62P_06 RENESAS | Alldatasheet

Document overview

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Technical content

www.renesas.com Before using this material, please visit our website to verify that this is the most updated document available. REJ09B0185-0241 M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES Rev.2.41 Revision Date:Jan 10, 2006

Keep safety first in your circuit designs! Notes regarding these materials 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with ap- propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap. 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, pro- grams, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, pro- grams and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers con- tact Renesas Technology Corp. or an authorized Renesas Technology Corp. product dis- tributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by vari- ous means, including the Renesas Technology Corp. Semiconductor home page (http:// www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all informa- tion as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liabil- ity or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or repro- duce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be im- ported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.

1. Introduction This hardware manual provides detailed information on the M16C/62P Group (M16C/62P , M16C/62PT) of microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers. 2. Register Diagram The symbols, and descriptions, used for bit function in each register are shown below. Blank: Set to “0” or “1” according to the application 0: Set to “0” 1: Set to “1” X: Nothing is assigned RW: Read and write RO: Read only WO: Write only −: Nothing is assigned

• Reserved bit Reserved bit. Set to specified value.
• Nothing is assigned Nothing is assigned to the bit concerned. As the bit may be use for future functions, set to “0” when writing to this bit.
• Do not set to this value The operation is not guaranteed when a value is set.
• Function varies depending on mode of operation Bit function varies depending on peripheral function mode. Refer to respective register for each mode. XXX Register Symbol Address After Reset XXX XXX 00h Bit NameBit Symbol RW b7 b6 b5 b4 b3 b2 b1 b0 XXX Bit 1 0: XXX 0 1: XXX 1 0: Avoid this setting 1 1: XXX b1 b0 XXX1 XXX0 XXX4 Reserved Bit XXX5 XXX7 XXX6 Function Nothing is assigned. When write, should set to “0”. When read, its content is indeterminate. XXX Bit Function varies depending on each operation mode Must set to “0” (b3) (b2) RW RW RW RW WO RW RO XXX Bit 0: XXX 1: XXX

1. M16C Family Documents The following documents were prepared for the M16C family. (1) NOTES: 1. Before using this material, please visit the our website to confirm that this is the most current document available. Document Contents Short Sheet Hardware overview Data Sheet Hardware overview and electrical characteristics Hardware Manual Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, timing charts) Software Manual Detailed description of assembly instructions and microcomputer performance of each instruction Application Note • Application examples of peripheral functions

• Sample programs
• Introduction to the basic functions in the M16C family
• Programming method with Assembly and C languages RENESAS TECHNICAL UPDATE Preliminary report about the specification of a product, a document, etc.

1. Overview 1 2. Central Processing Unit (CPU) 30 3. Memory 33 4. Special Function Register (SFR) 34 5. Reset 40 Table of Contents

1. Voltage Detection Circuit 45 7. Processor Mode 54 8. Bus 59 9. Memory Space Expansion Function 72

1. Clock Generation Circuit 82

10.2.2 Peripheral Function Clock (f1, f2 , f8, f32, f1SIO, f2SIO, f8SIO,

10.6.2 Operation When CM 27 bit = 0 (Oscillation Stop and Re-oscillation

1. Protection 105 12. Interrupt 106

1. Watchdog Timer 124 14. DMAC 126 15. Timers 137

1. Three-Phase Motor Control Timer Function 165 17. Serial Interface 176 18. A/D Converter 233

1. D/A Converter 251 20. CRC Calculation 253 21. Programmable I/O Ports 255

21.3 Pull-up Control Register 0 to Pull-up Control Register 3

1. Flash Memory Version 270

22.3.3 Flash memory Control Register (FIDR, FMR0 and FMR1 registers)276

1. Electrical Characteristics 304

1. Precautions 359

24.13 Electric Characteristic Differences Between Mask ROM

24.15.14Regarding Programming/Erasing Endurance and Execution Time ..381 25. Differences Depending on Manufacturing Period 383 Appendix 1. Package Dimensions 385 Appendix 2. Difference between M16C/62P and M16C/30P 387 Register Index 390

NOTES: 1. Blank columns are all reserved space. No access is allowed. Address Register Symbol Page 0000h 0001h 0002h 0003h 0004h Processor Mode Register 0 PM0 56 0005h Processor Mode Register 1 PM1 57 0006h System Clock Control Register 0 CM0 84 0007h System Clock Control Register 1 CM1 85 0008h Chip Select Control Register CSR 61 0009h Address Match Interrupt Enable Register AIER 123 000Ah Protect Register PRCR 105 000Bh Data Bank Register DBR 73 000Ch Oscillation Stop Detection Register CM2 86 000Dh 000Eh Watchdog Timer Start Register WDTS 125 000Fh Watchdog Timer Control Register WDC 53, 125 0010h Address Match Interrupt Register 0 RMAD0 123 0011h 0012h 0013h 0014h Address Match Interrupt Register 1 RMAD1 123 0015h 0016h 0017h 0018h 0019h Voltage Detection Register 1 VCR1 46 001Ah Voltage Detection Register 2 VCR2 46 001Bh Chip Select Expansion Control Register CSE 68 001Ch PLL Control Register 0 PLC0 88 001Dh 001Eh Processor Mode Register 2 PM2 87 001Fh Low Voltage Detection Interrupt Register D4INT 47 0020h DMA0 Source Pointer SAR0 131 0021h 0022h 0023h 0024h DMA0 Destination Pointer DAR0 131 0025h 0026h 0027h 0028h DMA0 Transfer Counter TCR0 131 0029h 002Ah 002Bh 002Ch DMA0 Control Register DM0CON 130 002Dh 002Eh 002Fh 0030h DMA1 Source Pointer SAR1 131 0031h 0032h 0033h 0034h DMA1 Destination Pointer DAR1 131 0035h 0036h 0037h 0038h DMA1 Transfer Counter TCR1 131 0039h 003Ah 003Bh 003Ch DMA1 Control Register DM1CON 130 003Dh 003Eh 003Fh Address Register Symbol Page 0040h 0041h 0042h 0043h 0044h INT3 Interrupt Control Register INT3IC 112 0045h Timer B5 Interrupt Control Register TB5IC 111 0046h Timer B4 Interrupt Control Register, UART1 BUS Collision Detection Interrupt Control Register TB4IC, U1BCNIC 111 0047h Timer B3 Interrupt Control Register, UART0 BUS Collision Detection Interrupt Control Register TB3IC, U0BCNIC 111 0048h SI/O4 Interrupt Control Register, INT5 Interrupt Control Register S4IC, INT5IC 112 0049h SI/O3 Interrupt Control Register, IINT4 Interrupt Control Register S3IC, INT4IC 112 004Ah UART2 Bus Collision Detection Interrupt Control Register BCNIC 111 004Bh DMA0 Interrupt Control Register DM0IC 111 004Ch DMA1 Interrupt Control Register DM1IC 111 004Dh Key Input Interrupt Control Register KUPIC 111 004Eh A/D Conversion Interrupt Control Register ADIC 111 004Fh UART2 Transmit Interrupt Control Register S2TIC 111 0050h UART2 Receive Interrupt Control Register S2RIC 111 0051h UART0 Transmit Interrupt Control Register S0TIC 111 0052h UART0 Receive Interrupt Control Register S0RIC 111 0053h UART1 Transmit Interrupt Control Register S1TIC 111 0054h UART1 Receive Interrupt Control Register S1RIC 111 0055h Timer A0 Interrupt Control Register TA0IC 111 0056h Timer A1 Interrupt Control Register TA1IC 111 0057h Timer A2 Interrupt Control Register TA2IC 111 0058h Timer A3 Interrupt Control Register TA3IC 111 0059h Timer A4 Interrupt Control Register TA4IC 111 005Ah Timer B0 Interrupt Control Register TB0IC 111 005Bh Timer B1 Interrupt Control Register TB1IC 111 005Ch Timer B2 Interrupt Control Register TB2IC 111 005Dh INT0 Interrupt Control Register INT0IC 112 005Eh INT1 Interrupt Control Register INT1IC 112 005Fh INT2 Interrupt Control Register INT2IC 112 0060h 0061h 0062h 0062h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh SFR Page Reference

NOTES: 1. Blank columns are all reserved space. No access is allowed. Address Register Symbol Page 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h to 01AFh 01B0h 01B2h 01B3h 01B4h Flash Identification Register FIDR 276 01B5h Flash Memory Control Register 1 FMR1 278 01B6h 01B7h Flash Memory Control Register 0 FMR0 277 01B8h Address Match Interrupt Register 2 RMAD2 123 01B9h 01BAh 01BBh Address Match Interrupt Enable Register 2 AIER2 123 01BCh Address Match Interrupt Register 3 RMAD3 123 01BDh 01BEh 01BFh 01C0h to 02AFh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh Peripheral Clock Select Register PCLKR 87 025Fh 0260h 0261h 0262h 0263h 0264h 0265h 0266h 0267h 0268h 0269h 026Ah to 0335h 0336h 0337h 0338h 0339h 033Ah 033Bh 033Ch 033Dh 033Eh 033Fh Address Register Symbol Page 0340h Timer B3, 4, 5 Count Start Flag TBSR 158 0341h 0342h Timer A1-1 Register TA11 169 0343h 0344h Timer A2-1 Register TA21 169 0345h 0346h Timer A4-1 Register TA41 169 0347h 0348h Three-Phase PWM Control Register 0 INVC0 167 0349h Three-Phase PWM Control Register 1 INVC1 168 034Ah Three-Phase Output Buffer Register 0 IDB0 170 034Bh Three-Phase Output Buffer Register 1 IDB1 170 034Ch Dead Time Timer DTT 171 034Dh Timer B2 Interrupt Occurrence Frequency Set Counter ICTB2 169 034Eh 034Fh 0350h Timer B3 Register TB3 157 0351h 0352h Timer B4 Register TB4 157 0353h 0354h Timer B5 Register TB5 157 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh Timer B3 Mode Register TB3MR 157 035Ch Timer B4 Mode Register TB4MR 157 035Dh Timer B5 Mode Register TB5MR 157 035Eh Interrupt Factor Select Register 2 IFSR2A 120 035Fh Interrupt Factor Select Register IFSR 120 0360h SI/O3 Transmit/Receive Register S3TRR 229 0361h 0362h SI/O3 Control Register S3C 228 0363h SI/O3 Bit Rate Generator S3BRG 229 0364h SI/O4 Transmit/Receive Register S4TRR 229 0365h 0366h SI/O4 Control Register S4C 228 0367h SI/O4 Bit Rate Generator S4BRG 229 0368h 0369h 036Ah 036Bh 036Ch UART0 Special Mode Register 4 U0SMR4 188 036Dh UART0 Special Mode Register 3 U0SMR3 187 036Eh UART0 Special Mode Register 2 U0SMR2 187 036Fh UART0 Special Mode Register U0SMR 186 0370h UART1 Special Mode Register 4 U1SMR4 188 0371h UART1 Special Mode Register 3 U1SMR3 187 0372h UART1 Special Mode Register 2 U1SMR2 187 0373h UART1 Special Mode Register U1SMR 186 0374h UART2 Special Mode Register 4 U2SMR4 188 0375h UART2 Special Mode Register 3 U2SMR3 187 0376h UART2 Special Mode Register 2 U2SMR2 187 0377h UART2 Special Mode Register U2SMR 186 0378h UART2 Transmit/Receive Mode Register U2MR 183 0379h UART2 Bit Rate Generator U2BRG 182 037Ah UART2 Transmit Buffer Register U2TB 181 037Bh 037Ch UART2 Transmit/Receive Control Register 0 U2C0 184 037Dh UART2 Transmit/Receive Control Register 1 U2C1 185 037Eh UART2 Receive Buffer Register U2RB 181 037Fh

NOTES: 1. Blank columns are all reserved space. No access is allowed. Address Register Symbol Page 0380h Count Start Flag TABSR 141, 158 0381h Clock Prescaler Reset Fag CPSRF 143, 158 0382h One-Shot Start Flag ONSF 142 0383h Trigger Select Register TRGSR 142 0384h Up-Down Flag UDF 141 0385h 0386h Timer A0 Register TA0 140 0387h 0388h Timer A1 Register TA1 140 0389h 038Ah Timer A2 Register TA2 140 038Bh 038Ch Timer A3 Register TA3 140 038Dh 038Eh Timer A4 Register TA4 140 038Fh 0390h Timer B0 Register TB0 157 0391h 0392h Timer B1 Register TB1 157 0393h 0394h Timer B2 Register TB2 157 0395h 0396h Timer A0 Mode Register TA0MR 140 0397h Timer A1 Mode Register TA1MR 140 0398h Timer A2 Mode Register TA2MR 140 0399h Timer A3 Mode Register TA3MR 140 039Ah Timer A4 Mode Register TA4MR 140 039Bh Timer B0 Mode Register TB0MR 157 039Ch Timer B1 Mode Register TB1MR 157 039Dh Timer B2 Mode Register TB2MR 157 039Eh Timer B2 Special Mode Register TB2SC 170 039Fh 03A0h UART0 Transmit/Receive Mode Register U0MR 183 03A1h UART0 Bit Rate Generator U0BRG 182 03A2h UART0 Transmit Buffer Register U0TB 181 03A3h 03A4h UART0 Transmit/Receive Control Register 0 U0C0 184 03A5h UART0 Transmit/Receive Control Register 1 U0C1 185 03A6h UART0 Receive Buffer Register U0RB 181 03A7h 03A8h UART1 Transmit/Receive Mode Register U1MR 183 03A9h UART1 Bit Rate Generator U1BRG 182 03AAh UART1 Transmit Buffer Register U1TB 181 03ABh 03ACh UART1 Transmit/Receive Control Register 0 U1C0 184 03ADh UART1 Transmit/Receive Control Register 1 U1C1 185 03AEh UART1 Receive Buffer Register U1RB 181 03AFh 03B0h UART Transmit/Receive Control Register 2 UCON 186 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h DMA0 Request Factor Select Register DM0SL 128 03B9h 03BAh DMA1 Request Factor Select Register DM1SL 129 03BBh 03BCh CRC Data Register CRCD 253 03BDh 03BEh CRC Input Register CRCIN 253 03BFh Address Register Symbol Page 03C0h A/D Register 0 AD0 237 03C1h 03C2h A/D Register 1 AD1 237 03C3h 03C4h A/D Register 2 AD2 237 03C5h 03C6h A/D Register 3 AD3 237 03C7h 03C8h A/D Register 4 AD4 237 03C9h 03CAh A/D Register 5 AD5 237 03CBh 03CCh A/D Register 6 AD6 237 03CDh 03CEh A/D Register 7 AD7 237 03CFh 03D0h 03D1h 03D2h 03D3h 03D4h A/D Control Register 2 ADCON2 236 03D5h 03D6h A/D Control Register 0 ADCON0 235 03D7h A/D Control Register 1 ADCON1 235 03D8h D/A Register 0 DA0 252 03D9h 03DAh D/A Register 1 DA1 252 03DBh 03DCh D/A Control Register DACON 252 03DDh 03DEh Port P14 Control Register PC14 264 03DFh Pull-Up Control Register 3 PUR3 264 03E0h Port P0 Register P0 263 03E1h Port P1 Register P1 263 03E2h Port P0 Direction Register PD0 262 03E3h Port P1 Direction Register PD1 262 03E4h Port P2 Register P2 263 03E5h Port P3 Register P3 263 03E6h Port P2 Direction Register PD2 262 03E7h Port P3 Direction Register PD3 262 03E8h Port P4 Register P4 263 03E9h Port P5 Register P5 263 03EAh Port P4 Direction Register PD4 262 03EBh Port P5 Direction Register PD5 262 03ECh Port P6 Register P6 263 03EDh Port P7 Register P7 263 03EEh Port P6 Direction Register PD6 262 03EFh Port P7 Direction Register PD7 262 03F0h Port P8 Register P8 263 03F1h Port P9 Register P9 263 03F2h Port P8 Direction Register PD8 262 03F3h Port P9 Direction Register PD9 262 03F4h Port P10 Register P10 263 03F5h Port P11 Register P11 263 03F6h Port P10 Direction Register PD10 262 03F7h Port P11 Direction Register PD11 262 03F8h Port P12 Register P12 263 03F9h Port P13 Register P13 263 03FAh Port P12 Direction Register PD12 262 03FBh Port P13 Direction Register PD13 262 03FCh Pull-Up Control Register 0 PUR0 265 03FDh Pull-Up Control Register 1 PUR1 265 03FEh Pull-Up Control Register 2 PUR2 266 03FFh Port Control Register PCR 266

Rev.2.41 Jan 10, 2006 Page 1 of 390 REJ09B0185-0241 M16C/62P Group (M16C/62P, M16C/62PT) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1. Overview The M16C/62P Group (M16C/62P, M16C/62PT) of single-chip microcomputers are built using the high performance silicon gate CMOS process using a M 16C/60 Series CPU core and are packaged in a 80-pin, 100-pin and 128-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. In addition, this microcomputer contains a multiplier and DMAC which combined with fast instruction processing capability, makes it suitable for control of various OA, communication, and industrial equipment which requires high- speed arithmetic/logic operations.

1.1 Applications

Audio, cameras, television, home applia nce, office/communications/portable /industrial equipm ent, automobile, etc. Specifications written in this ma nual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition.

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 2 of 390 REJ09B0185-0241

1.2 Performance Outline

Table 1.1 to 1.3 list Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(128-pin version). NOTES: 1. I 2C bus is a registered trademark of Koninklijke Philips Electronics N. V. 2. IEBus is a registered trademark of NEC Electronics Corporation. 3. See Table 1.8 Product Code for the program and erase endurance, and operating ambient temperature. In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release schedule. 4. All options are on request basis. Table 1.1 Performance Outline of M16C/62P Gr oup (M16C/62P, M16C/62PT)(128-pin version) Item Performance M16C/62P CPU Number of Basic Inst ructions 91 instructions Minimum Instruction Execution Time 41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V) 100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V) Operating Mode Single-chip, memory expansion and microprocessor mode Address Space 1 Mbyte (Available to 4 Mbytes by memory space expansion function) Memory Capacity See Table 1.4 to 1.5 Product List Peripheral Function Port Input/Output : 113 pins, Input : 1 pin Multifunction Timer Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels, Three phase motor control circuit Serial Interface 3 channels Clock synchronous, UART, I 2C bus(1), IEBus(2) 2 channels Clock synchronous A/D Converter 10-bit A/D converter: 1 circuit, 26 channels D/A Converter 8 bits x 2 channels DMAC 2 channels CRC Calculation Circuit CCITT-CRC Watchdog Timer 15 bits x 1 channel (with prescaler) Interrupt Internal: 29 sources, External: 8 sources, Software: 4 sources, Priority level: 7 levels Clock Generation Circuit 4 circuits Main clock generation circuit (*), Subclock generation circuit (*), On-chip oscillator, PLL synthesizer (*)Equipped with a built-in feedback resistor. Oscillation Stop Detection Function Stop detection of main clock oscillation, re-oscillation detection function Voltage Detection Circuit Available (option (4)) Electric Characteristics Supply Voltage VCC1=3.0 to 5.5 V, VCC2=2.7V to VCC1 (f(BCLK=24MHz) VCC1=2.7 to 5.5 V, VCC2=2.7V to VCC1 (f(BCLK=10MHz) Power Consumption 14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz) 8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz) 1.8µA (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode) 0.7µA (VCC1=VCC2=3V, stop mode) Flash memory version Program/Erase Supply Voltage 3.3±0.3 V or 5.0±0.5 V Program and Erase Endurance 100 times (all area) or 1,000 times (user ROM area without block A and block 1) / 10,000 times (block A, block 1) (3) Operating Ambient Temperature -20 to 85 °C, -40 to 85°C (3) Package 128-pin plastic mold LQFP

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 3 of 390 REJ09B0185-0241 NOTES: 1. I 2C bus is a registered trademark of Koninklijke Philips Electronics N. V. 2. IEBus is a registered trademark of NEC Electronics Corporation. 3. See Table 1.8 and 1.9 Product Code for the program and erase endurance, and operating ambient temperature. In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release schedule. 4. Use the M16C/62PT on VCC1=VCC2 5. All options are on request basis. Table 1.2 Performance Outline of M16C/62P Gr oup (M16C/62P, M16C/62PT)(100-pin version) Item Performance M16C/62P M16C/62PT (4) CPU Number of Basic Instructions 91 instructions Minimum Instruction Execution Time 41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V) 100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V) Operating Mode Single-chip, memory expansion and microprocessor mode Single-chip Address Space 1 Mbyte (Available to 4 Mbytes by memory space expansion function)

1 Mbyte

Memory Capacity See Table 1.4 to 1.7 Product List Peripheral Function Port Input/Output : 87 pins, Input : 1 pin Multifunction Timer Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels, Three phase motor control circuit Serial Interface 3 channels Clock synchronous, UART, I2C bus(1), IEBus(2) 2 channels Clock synchronous A/D Converter 10-bit A/D converter: 1 circuit, 26 channels D/A Converter 8 bits x 2 channels DMAC 2 channels CRC Calculation Circuit CCITT-CRC Watchdog Timer 15 bits x 1 channel (with prescaler) Interrupt Internal: 29 sources, External: 8 sources, Software: 4 sources, Priority level: 7 levels Clock Generation Circuit 4 circuits Main clock generation circuit (*), Subclock generation circuit (*), On-chip oscillator, PLL synthesizer (*)Equipped with a built-in feedback resistor. Oscillation Stop Detection Function Stop detection of main clock oscillation, re-oscillation detection function Voltage Detection Circuit Available (option (5))A b s e n t Electric Characteristics Supply Voltage VCC1=3.0 to 5.5 V, VCC2=2.7V to VCC1 (f(BCLK=24MHz) VCC1=2.7 to 5.5 V, VCC2=2.7V to VCC1 (f(BCLK=10MHz) VCC1=VCC2=4.0 to 5.5V (f(BCLK=24MHz) Power Consumption 14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz) 8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz) 1.8µA (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode) 0.7 µA (VCC1=VCC2=3V, stop mode) 14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz) 2.0µA (VCC1=VCC2=5V, f(XCIN)=32kHz, wait mode) 0.8µA (VCC1=VCC2=5V, stop mode) Flash memory version Program and Erase Endurance 100 times (all area) or 1,000 times (user ROM area without block A and block 1) / 10,000 times (block A, block 1) (3) Operating Ambient Temperature -20 to 85 °C, -40 to 85°C (3) T version : -40 to 85°C V version : -40 to 125°C Package 100-pin plastic mold QFP, LQFP

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 4 of 390 REJ09B0185-0241 NOTES: 1. I 2C bus is a registered trademark of Koninklijke Philips Electronics N. V. 2. IEBus is a registered trademark of NEC Electronics Corporation. 3. See Table 1.8 and 1.9 Product Code for the program and erase endurance, and operating ambient temperature. In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release schedule. 4. All options are on request basis. Table 1.3 Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(80-pin version) Item Performance M16C/62P M16C/62PT (4) CPU Number of Basic Instructions 91 instructions Minimum Instruction Execution Time 41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V) 100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V) Operating Mode Single-chip mode Address Space 1 Mbyte Memory Capacity See Table 1.4 to 1.7 Product List Peripheral Function Port Input/Output : 70 pins, Input : 1 pin Multifunction Timer Timer A : 16 bits x 5 channels (Timer A1 and A2 are internal timer), Timer B : 16 bits x 6 channels (Timer B1 is internal timer) Serial Interface 2 channels Clock synchronous, UART, I2C bus(1), IEBus(2) 1 channel Clock synchronous, I2C bus(1), IEBus(2) 2 channels Clock synchronous (1 channel is only transmission) A/D Converter 10-bit A/D converter: 1 circuit, 26 channels D/A Converter 8 bits x 2 channels DMAC 2 channels CRC Calculation Circuit CCITT-CRC Watchdog Timer 15 bits x 1 channel (with prescaler) Interrupt Internal: 29 sources, External: 5 sources, Software: 4 sources, Priority level: 7 levels Clock Generation Circuit 4 circuits Main clock generation circuit (*), Subclock generation circuit (*), On-chip oscillator, PLL synthesizer (*)Equipped with a built-in feedback resistor. Oscillation Stop Detection Function Stop detection of main clock oscillation, re-oscillation detection function Voltage Detection Circuit Available (option (4))A b s e n t Electric Characteristics Supply Voltage VCC1=3.0 to 5.5 V, (f(BCLK=24MHz) VCC1=2.7 to 5.5 V, (f(BCLK=10MHz) VCC1=4.0 to 5.5V, (f(BCLK=24MHz) Power Consumption 14 mA (VCC1=5V, f(BCLK)=24MHz) 8 mA (VCC1=3V, f(BCLK)=10MHz) 1.8 µA (VCC1=3V, f(XCIN)=32kHz, wait mode) 0.7µA (VCC1=3V, stop mode) 14 mA (VCC1=5V, f(BCLK)=24MHz) 2.0µA (VCC1=5V, f(XCIN)=32kHz, wait mode) 0.8µA (VCC1=5V, stop mode) Flash memory version Program and Erase Endurance 100 times (all area) or 1,000 times (user ROM area without block A and block 1) / 10,000 times (block A, block 1) (3) Operating Ambient Temperature -20 to 85 °C, -40 to 85°C (3) T version : -40 to 85°C V version : -40 to 125°C Package 80-pin plastic mold QFP

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 5 of 390 REJ09B0185-0241

1.3 Block Diagram

Figure 1.1 is a M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram, Figure 1.2 is a M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram. Figure 1.1 M16C/62P Group (M16C/62P, M16C/62P T) 128-pin and 100-pin version Block Diagram Output (timer A): 5 Input (timer B): 6 Internal peripheral functions Watchdog timer (15 bits) DMAC (2 channels) D/A converter (8 bits X 2 channels) Memory ROM (1) RAM (2) A/D converter (10 bits X 8 channels Expandable up to 26 channels) UART or clock synchronous serial I/O (8 bits X 3 channels) System clock generation circuit XIN-XOUT XCIN-XCOUT PLL frequency synthesizer On-chip oscillator M16C/60 series16-bit CPU core Port P0 Port P1 Port P2 8 8 8 8 Port P6 R0LR0H R1H R1L FB SB ISP USP INTB CRC arithmetic circuit (CCITT ) (Polynomial : X16+X12+X5+1) Multiplier 788 Port P10 Port P9 Port P8_5 Port P8 Port P7 NOTES : 1. ROM size depends on microcomputer type. 2. RAM size depends on microcomputer type. 3. Ports P11 to P14 exist only in 128-pin version. 4. Use M16C/62PT on VCC1= VCC2. Port P5 Port P4Port P3 Clock synchronous serial I/O (8 bits X 2 channels) PC FLG Timer (16-bit) Three-phase motor control circuit 8 8 82 Port P11 Port P12Port P14 Port P13 (3) <VCC2 ports>(4) <VCC1 ports>(4) <VCC1 ports>(4) <VCC2 ports>(4)<VCC1 ports>(4) (3) (3) (3)

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 6 of 390 REJ09B0185-0241 Figure 1.2 M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram Timer (16-bit) Output (timer A): 5 Input (timer B): 6 Internal peripheral functions Watchdog timer (15 bits) DMAC (2 channels) D/A converter (8 bits X 2 channels) A/D converter (10 bits X 8 channels Expandable up to 26 channels) UART or clock synchronous serial I/O (2 channels) UART (1 channel) System clock generation circuit XIN-XOUT XCIN-XCOUT PLL frequency synthesizer On-chip oscillator M16C/60 series16-bit CPU core Port P0 Port P2 Port P3 Port P4 Port P5 Port P6 CRC arithmetic circuit (CCITT ) (Polynomial : X16+X12+X5+1) Memory 4778 Port P10 Port P9 Port P8 Port P7Port P8_5 ROM (1) RAM (2) NOTES : 1. ROM size depends on microcomputer type. 2. RAM size depends on microcomputer type. 3. To use a UART2, set the CRD bit in the U2C0 register to “1” (CTS/RTS function disabled). 4. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Set the direction bits in these ports to “1” (output mode), and set the output data to “0” (“L”) using the program. Clock synchronous serial I/O (8 bits X 2 channels) R0LR0H R1H R1L SB FLG USP ISP INTB PC Multiplier FB (4) (4) (3)

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 7 of 390 REJ09B0185-0241

1.4 Product List

Product Code of Flash Memory version and ROMless vers ion for M16C/62P, and Table 1.9 lists the Product Code of Flash Memory version for M16C/62PT. Figure 1.4 s hows the Marking Diagram of Flash Memory version and ROM-less version for M16C/62P (Top View), and Fi gure 1.5 shows the Marking Diagram of Flash Memory version for M16C/62PT (Top View) at the time of ROM order. (D): Under development NOTES: 1. The old package type numbers of each package type are as follows. PLQP0128KB-A : 128P6Q-A, PRQP0100JB-A : 100P6S-A, PLQP0100KB-A : 100P6Q-A, PRQP0080JA-A : 80P6S-A Table 1.4 Product List (1) (M16C/62P) As of Dec. 2005 Type No. ROM Capacity RAM Capacity Package Type (1) Remarks M30622M6P-XXXFP 48 Kbytes 4 Kbytes PRQP0100JB-A Mask ROM version M30622M6P-XXXGP PLQP0100KB-A M30622M8P-XXXFP 64 Kbytes 4 Kbytes PRQP0100JB-A M30622M8P-XXXGP PLQP0100KB-A M30623M8P-XXXGP PRQP0080JA-A M30622MAP-XXXFP 96 Kbytes 5 Kbytes PRQP0100JB-A M30622MAP-XXXGP PLQP0100KB-A M30623MAP-XXXGP P RQP0080JA-A M30620MCP-XXXFP 128 Kbytes 10 Kbytes PRQP0100JB-A M30620MCP-XXXGP P LQP0100KB-A M30621MCP-XXXGP P RQP0080JA-A M30622MEP-XXXFP 192 Kbytes 12 Kbytes PRQP0100JB-A M30622MEP-XXXGP PLQP0100KB-A M30623MEP-XXXGP PLQP0128KB-A M30622MGP-XXXFP 256 Kbytes 12 Kbytes PRQP0100JB-A M30622MGP-XXXGP PLQP0100KB-A M30623MGP-XXXGP PLQP0128KB-A M30624MGP-XXXFP 20 Kbytes PRQP0100JB-A M30624MGP-XXXGP PLQP0100KB-A M30625MGP-XXXGP PLQP0128KB-A M30622MWP-XXXFP 320 Kbytes 16 Kbytes PRQP0100JB-A M30622MWP-XXXGP P LQP0100KB-A M30623MWP-XXXGP P LQP0128KB-A M30624MWP-XXXFP 24 Kb ytes PRQP0100JB-A M30624MWP-XXXGP P LQP0100KB-A M30625MWP-XXXGP P LQP0128KB-A M30626MWP-XXXFP 31 Kb ytes PRQP0100JB-A M30626MWP-XXXGP P LQP0100KB-A M30627MWP-XXXGP P LQP0128KB-A

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 8 of 390 REJ09B0185-0241 (D): Under development NOTES: 1. The old package type numbers of each package type are as follows. PLQP0128KB-A : 128P6Q-A, PRQP0100JB-A : 100P6S-A, PLQP0100KB-A : 100P6Q-A, PRQP0080JA-A : 80P6S-A 2. In the flash memory version, there is 4K bytes area (block A). 3. Please use M3062LFGPFP and M3062LFGPGP for your new system instead of M30624FGPFP and M30624FGPGP. The M16C/62P Group (M16C/62P, M16C/62PT) hardware manual is still good for M30624FGPFP and M30624FGPGP. Table 1.5 Product List (2) (M16C/62P) As of Dec. 2005 Type No. ROM Capacity RAM Capacity Package Type (1) Remarks M30622MHP-XXXFP 384 Kbytes 16 Kbyt es PRQP0100JB-A Mask ROM version M30622MHP-XXXGP PLQP0100KB-A M30623MHP-XXXGP PLQP0128KB-A M30624MHP-XXXFP 24 Kbytes PRQP0100JB-A M30624MHP-XXXGP PLQP0100KB-A M30625MHP-XXXGP PLQP0128KB-A M30626MHP-XXXFP 31 Kbytes PRQP0100JB-A M30626MHP-XXXGP PLQP0100KB-A M30627MHP-XXXGP PLQP0128KB-A M30626MJP-XXXFP (D) 512 Kbytes 31 Kbytes PRQP0100JB-A M30626MJP-XXXGP ( D) PLQP0100KB-A M30627MJP-XXXGP ( D) PLQP0128KB-A M30622F8PFP 64K+4 Kbytes 4 Kbytes PRQP0100JB-A Flash memory version (2)M30622F8PGP PLQP0100KB-A M30623F8PGP PRQP0080JA-A M30620FCPFP 128K+4 Kbytes 10 Kbytes PRQP0100JB-A M30620FCPGP PLQP0100KB-A M30621FCPGP PRQP0080JA-A M3062LFGPFP (3) (D) 256K+4 Kbytes 20 Kbytes PRQP0100JB-A M3062LFGPGP(3) (D) PLQP0100KB-A M30625FGPGP PLQP0128KB-A M30626FHPFP 384K+4 Kbytes 31 Kbytes PRQP0100JB-A M30626FHPGP PLQP0100KB-A M30627FHPGP PLQP0128KB-A M30626FJPFP 512K+4 Kbytes 31 Kbytes PRQP0100JB-A M30626FJPGP PLQP0100KB-A M30627FJPGP PLQP0128KB-A M30622SPFP − 4 Kbytes PRQP0100JB-A ROM-less version M30622SPGP PLQP0100KB-A M30620SPFP 10 Kbytes PRQP0100JB-A M30620SPGP PLQP0100KB-A M30624SPFP (D) − 20 Kbytes PRQP0100JB-A M30624SPGP (D) PLQP0100KB-A M30626SPFP (D) 31 Kbytes PRQP0100JB-A M30626SPGP (D) PLQP0100KB-A M30624FGPFP 256K+4 Kbytes 20 Kbytes PRQP0100JB-A Flash memory version M30624FGPGP PLQP0100KB-A

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 9 of 390 REJ09B0185-0241 (D): Under development (P): Under planning NOTES: 1. The old package type numbers of each package type are as follows. PRQP0100JB-A : 100P6S-A, PLQP0100KB-A : 100P6Q-A, PRQP0080JA-A : 80P6S-A 2. In the flash memory version, there is 4K bytes area (block A). Table 1.6 Product List (3) (T version (M16C/62PT)) As of Dec. 2005 Type No. ROM Capacity RAM Capacity Package Type (1) Remarks M3062CM6T-XXXFP (D) 48 Kbytes 4 Kbytes PRQP0100JB-A Mask ROM version T Version (High reliability 85°C version) M3062CM6T-XXXGP (D) PLQP0100KB-A M3062EM6T-XXXGP (P) PRQP0080JA-A M3062CM8T-XXXFP (D) 64 Kbyt es 4 Kbytes PRQP0100JB-A M3062CM8T-XXXGP (D) PLQP0100KB-A M3062EM8T-XXXGP (P) PRQP0080JA-A M3062CMAT-XXXFP (D) 96 Kbytes 5 Kbytes PRQP0100JB-A M3062CMAT-XXXGP (D) PLQP0100KB-A M3062EMAT-XXXGP (P) PRQP0080JA-A M3062AMCT-XXXFP (D) 128 Kbytes 10 Kbytes PRQP0100JB-A M3062AMCT-XXXGP (D) PLQP0100KB-A M3062BMCT-XXXGP (P) PRQP0080JA-A M3062CF8TFP (D) 64 K+4 Kbytes 4 Kbytes PRQP0100JB-A Flash memory version (2) M3062CF8TGP PLQP0100KB-A M3062AFCTFP (D) 128K+4 Kbytes 10 Kbytes PRQP0100JB-A M3062AFCTGP (D) PLQP0100KB-A M3062BFCTGP (P) PRQP0080JA-A M3062JFHTFP (D) 384K+4 Kbytes 31 Kbytes PRQP0100JB-A M3062JFHTGP (D) PLQP0100KB-A

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 10 of 390 REJ09B0185-0241 (D): Under development (P): Under planning NOTES: 1. The old package type numbers of each package type are as follows. PLQP0128KB-A : 128P6Q-A, PRQP0100JB-A : 100P6S-A, PLQP0100KB-A : 100P6Q-A, PRQP0080JA-A : 80P6S-A 2. In the flash memory version, there is 4K bytes area (block A). Table 1.7 Product List (4) (V version (M16C/62PT)) As of Dec. 2005 Type No. ROM Capacity RAM Capacity Package Type (1) Remarks M3062CM6V-XXXFP (P) 48 Kbytes 4 Kbytes PRQP0100JB-A Mask ROM version V Version (High reliability 125°C version) M3062CM6V-XXXGP ( P) PLQP0100KB-A M3062EM6V-XXXGP (P) PRQP0080JA-A M3062CM8V-XXXFP (P) 64 Kbyt es 4 Kbytes PRQP0100JB-A M3062CM8V-XXXGP ( P) PLQP0100KB-A M3062EM8V-XXXGP (P) PRQP0080JA-A M3062CMAV-XXXFP (P) 96 Kbyt es 5 Kbytes PRQP0100JB-A M3062CMAV-XXXGP (P) PLQP0100KB-A M3062EMAV-XXXGP (P) PRQP0080JA-A M3062AMCV-XXXFP (D) 128 Kbyt es 10 Kbytes PRQP0100JB-A M3062AMCV-XXXGP (D) PLQP0100KB-A M3062BMCV-XXXGP (P) PRQP0080JA-A M3062AFCVFP (D) 128K+4 Kbytes 10 Kbytes PRQP0100JB-A Flash memory version (2) M3062AFCVGP (D) PLQP0100KB-A M3062BFCVGP (P) PRQP0080JA-A M3062JFHVFP (P) 384K+4 Kbytes 31 Kbytes PRQP0100JB-A M3062JFHVGP (P) PLQP0100KB-A

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 11 of 390 REJ09B0185-0241 Figure 1.3 Type No., Memory Size, and Package Package type: FP : Package PRQP0100JB-A (100P6S-A) GP : Package PRQP0080JA-A (80P6S-A), PLQP0100KB-A (100P6Q-A), PLQP0128KB-A (128P6Q-A), ROM No. Omitted for flash memory version and ROMless version Memory type: M: Mask ROM version F: Flash memory version S: ROM-less version Type No. M 3 0 6 2 6 M H P - X X X F P M16C/62(P) Group M16C Family Shows RAM capacity, pin count, etc Numeric, Alphabet (L) : M16C/62P Alphabet (L is excluded.) : M16C/62PT ROM capacity: 6: 48 Kbytes 8: 64 Kbytes A: 96 Kbytes C: 128 Kbytes E: 192 Kbytes G: 256 Kbytes W: 320 Kbytes H: 384 Kbytes J: 512 Kbytes Classification P : M16C/62P T : T version (M16C/62PT) V : V version (M16C/62PT)

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 12 of 390 REJ09B0185-0241 Figure 1.4 Marking Diagram of Flash Memory version and ROM-less version for M16C/62P (Top View) Table 1.8 Product Code of Flash Memory version and ROMless version for M16C/62P Product Code Package Internal ROM (User ROM Area Without Block A, Block 1) Internal ROM (Block A, Block 1) Operating Ambient TemperatureProgram and Erase Endurance Temperature Range Program and Erase Endurance Temperature Range Flash memory Version D3 Lead- included 100 0 °C to 60°C 100 0 °C to 60°C- 4 0 °C to 85°C D5 -20°C to 85°C D7 1,000 10,000 -40 °C to 85°C- 4 0 °C to 85°C D9 -20°C to 85°C- 2 0 °C to 85°C U3 Lead-free 100 100 0 °C to 60°C- 4 0 °C to 85°C U5 -20°C to 85°C U7 1,000 10,000 -40 °C to 85°C- 4 0 °C to 85°C U9 -20°C to 85°C- 2 0 °C to 85°C ROM-less version D3 Lead- included D5 -20°C to 85°C U3 Lead-free −− − − -40°C to 85°C U5 -20°C to 85°C M1 6 C M 30626FH PFP BD 5 XXXXXXX Type No. (See Figure 1.3 Type No., Memory Size, and Package) Chip version and product code B : Shows chip version. Henceforth, whenever it changes a version, it continues with B, C, and D. D5 : Shows Product code. (See table 1.8 Product Code) Date code seven digits The product without marking of chip version of the flash memory version and the ROMless version corresponds to the chip version “A”.

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 13 of 390 REJ09B0185-0241 Figure 1.5 Marking Diagram of Flash Memory version for M16C/62PT (Top View) Table 1.9 Product Code of Flash Memory version for M16C/62PT Product Code Package Internal ROM (User ROM Area Without Block A, Block 1) Internal ROM (Block A, Block 1) Operating Ambient TemperatureProgram and Erase Endurance Temperature Range Program and Erase Endurance Temperature Range Flash memory Version T Version B Lead- included 100 0 °C to 60°C1 0 0 0 °C to 60°C- 4 0 °C to 85°C V Version -40°C to 125°C T Version B7 1,000 10,000 -40 °C to 85°C- 4 0 °C to 85°C V Version -40°C to 125°C- 4 0 °C to 125°C T Version U Lead-free 100 100 0 °C to 60°C- 4 0 °C to 85°C V Version -40°C to 125°C T Version U7 1,000 10,000 -40 °C to 85°C- 4 0 °C to 85°C V Version -40°C to 125°C- 4 0 °C to 125°C M1 6 C M30 6 2 J F HT FP YY Y XXXXXXX Type No. (See Figure 1.3 Type No., Memory Size, and Package) Date code seven digits NOTES: 1. : Blank Product code. (See table 1.9 Product Code) “ ” : Product code “B” “ P B F ” : Product code “U” “ B 7 ” : Product code “B” “ U 7 ” : Product code “U7”

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 14 of 390 REJ09B0185-0241

1.5 Pin Configuration

Figures 1.6 to 1.9 show the Pin Configuration (Top View). Figure 1.6 Pin Configuration (Top View) 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 12 22 32 42 52 62 72 82 93 0 737475767778798081828384858687888990919293949596979899100101102 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 63104 105 106 107 108 31 32 33 34 35 36 37 66676869707172 64103 P0_0/AN0_0/D0 P0_1/AN0_1/D1 P0_2/AN0_2/D2 P0_3/AN0_3/D3 P0_4/AN0_4/D4 P0_5/AN0_5/D5 P0_6/AN0_6/D6 P0_7/AN0_7/D7 P1_0/D8 P1_1/D9 P1_2/D10 AVSS VCC1 XIN XOUT VSS RESET CNVSS P8_7/XCIN P8_6/XCOUT BYTE P7_4/TA2OUT/W P7_6/TA3OUT P5_6/ALE P7_7/TA3IN P5_5/HOLD P5_4/HLDA P5_3/BCLK P5_2/RD P5_7/RDY/CLKOUT P4_7/CS3 P6_3/TXD0/SDA0 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 P6_1/CLK0 P6_2/RXD0/SCL0 P10_0/AN0 P10_1/AN1 P10_2/AN2 P10_3/AN3 P9_3/DA0/TB3IN P9_4/DA1/TB4IN P9_5/ANEX0/CLK4 P9_6/ANEX1/SOUT4 P9_1/TB1IN/SIN3 P9_2/TB2IN/SOUT3 P8_0/TA4OUT/U P6_0/CTS0/RTS0 P6_4/CTS1/RTS1/CTS0/CLKS1 P8_2/INT0 P8_3/INT1 P8_5/NMI P4_5/CS1 P4_6/CS2 P4_4/CS0 P5_0/WRL/WR P5_1/WRH/BHE P9_0/TB0IN/CLK3 P7_2/CLK2/TA1OUT/V P7_1/RXD2/SCL2/TA0IN/TB5IN (1) P7_0/TXD2/SDA2/TA0OUT (1) P8_4/INT2/ZP P8_1/TA4IN/U P7_3/CTS2/RTS2/TA1IN/V P7_5/TA2IN/W P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 VREF AVCC P9_7/ADTRG/SIN4 P14_1 P14_0 P13_7 P13_6 P13_5 P13_4 P1_3/D11 P1_4/D12 P2_0/AN2_0/A0(/D0/-) P2_1/AN2_1/A1(/D1/D0) P2_2/AN2_2/A2(/D2/D1) P2_3/AN2_3/A3(/D3/D2) P2_4/AN2_4/A4(/D4/D3) P2_5/AN2_5/A5(/D5/D4) P2_6/AN2_6/A6(/D6/D5) P2_7/AN2_7/A7(/D7/D6) P3_0/A8(/-/D7) P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17 P4_2/A18 P4_3/A19 VCC2 VSS P1_5/D13/INT3 P1_6/D14/INT4 P1_7/D15/INT5 P12_4 P12_3 P11_3 P11_2 P11_1 P11_0 VCC1 VSS P13_0 P13_1 P13_2 P13_3 P12_5 P12_6 P12_7 P11_4 P11_5 P11_6 P11_7 P12_2 P12_1 P12_0 <VCC2> (2) <VCC1> (2) M16C/62P Group (M16C/62P) NOTES: 1. P7_0 and P7_1 are N channel open-drain output pins. 2. Use the M16C/62PT on VCC1=VCC2. PIN CONFIGURATION (top view)

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 15 of 390 REJ09B0185-0241 Table 1.10 Pin Characteristics for 128-Pin Package (1) Pin No. Control Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin 1V R E F 2A V C C

3 P9_7 SIN4 ADTRG

4 P9_6 SOUT4 ANEX1

5 P9_5 CLK4 ANEX0

6P 9 _ 4 T B 4 I N D A 1 7P 9 _ 3 T B 3 I N D A 0

8 P9_2 TB2IN SOUT3

9 P9_1 TB1IN SIN3

10 P9_0 TB0IN CLK3

11 P14_1

12 P14_0

13 BYTE

14 CNVSS

15 XCIN P8_7

16 XCOUT P8_6

17 RESET

18 XOUT

19 VSS

20 XIN

21 VCC1

22 P8_5 NMI

23 P8_4 INT2 ZP

24 P8_3 INT1

25 P8_2 INT0

26 P8_1 TA4IN/U

27 P8_0 TA4OUT/U

28 P7_7 TA3IN

29 P7_6 TA3OUT

30 P7_5 TA2IN/W

31 P7_4 TA2OUT/W

32 P7_3 TA1IN/V CTS2/RTS2

33 P7_2 TA1OUT/V CLK2

34 P7_1 TA0IN/TB5IN RXD2/SCL2

35 P7_0 TA0OUT TXD2/SDA2

36 P6_7 TXD1/SDA1

37 VCC1

38 P6_6 RXD1/SCL1

39 VSS

40 P6_5 CLK1

41 P6_4 CTS1

/RTS1/CTS0/CLKS1

42 P6_3 TXD0/SDA0

43 P6_2 RXD0/SCL0

44 P6_1 CLK0

45 P6_0 CTS0

/RTS0

46 P13_7

47 P13_6

48 P13_5

49 P13_4

50 P5_7 RDY

/CLKOUT

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 16 of 390 REJ09B0185-0241 Table 1.11 Pin Characteristics for 128-Pin Package (2) Pin No. Control Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin

51 P5_6 ALE

52 P5_5 HOLD

53 P5_4 HLDA

54 P13_3

55 P13_2

56 P13_1

57 P13_0

58 P5_3 BCLK

59 P5_2 RD

60 P5_1 WRH/BHE

61 P5_0 WRL/WR

62 P12_7

63 P12_6

64 P12_5

65 P4_7 CS3

66 P4_6 CS2

67 P4_5 CS1

68 P4_4 CS0

69 P4_3 A19

70 P4_2 A18

71 P4_1 A17

72 P4_0 A16

73 P3_7 A15

74 P3_6 A14

75 P3_5 A13

76 P3_4 A12

77 P3_3 A11

78 P3_2 A10

79 P3_1 A9

80 P12_4

81 P12_3

82 P12_2

83 P12_1

84 P12_0

85 VCC2

86 P3_0 A8(/-/D7)

87 VSS

88 P2_7 AN2_7 A7(/D7/D6)

89 P2_6 AN2_6 A6(/D6/D5)

90 P2_5 AN2_5 A5(/D5/D4)

91 P2_4 AN2_4 A4(/D4/D3)

92 P2_3 AN2_3 A3(/D3/D2)

93 P2_2 AN2_2 A2(/D2/D1)

94 P2_1 AN2_1 A1(/D1/D0)

96 P1_7 INT5

97 P1_6 INT4 D14

98 P1_5 INT3 D13

99 P1_4 D12

100 P1_3 D11

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 17 of 390 REJ09B0185-0241 Table 1.12 Pin Characteristics for 128-Pin Package (3) Pin No. Control Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin

101 P1_2 D10

102 P1_1 D9

103 P1_0 D8

104 P0_7 AN0_7 D7

105 P0_6 AN0_6 D6

106 P0_5 AN0_5 D5

107 P0_4 AN0_4 D4

108 P0_3 AN0_3 D3

109 P0_2 AN0_2 D2

110 P0_1 AN0_1 D1

111 P0_0 AN0_0 D0

112 P11_7

113 P11_6

114 P11_5

115 P11_4

116 P11_3

117 P11_2

118 P11_1

119 P11_0

120 P10_7 KI3

121 P10_6 KI2 AN6

122 P10_5 KI1 AN5

123 P10_4 KI0 AN4

124 P10_3 AN3

125 P10_2 AN2

126 P10_1 AN1

127 AVSS

128 P10_0 AN0

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 18 of 390 REJ09B0185-0241 Figure 1.7 Pin Configuration (Top View) 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 12 22 32 42 52 62 72 82 93 0 515253545556575859606162636465666768697071727374757677787980 100 P0_0/AN0_0/D0 P0_1/AN0_1/D1 P0_2/AN0_2/D2 P0_3/AN0_3/D3 P0_4/AN0_4/D4 P0_5/AN0_5/D5 P0_6/AN0_6/D6 P0_7/AN0_7/D7 P1_0/D8 P1_1/D9 P1_2/D10 P1_3/D11 P1_4/D12 VREF AVSS VCC1 XIN XOUT VSS RESET CNVSS P8_7/XCIN P8_6/XCOUT BYTE P2_0/AN2_0/A0(/D0/-) P2_1/AN2_1/A1(/D1/D0) P2_2/AN2_2/A2(/D2/D1) P2_3/AN2_3/A3(/D3/D2) P2_4/AN2_4/A4(/D4/D3) P2_5/AN2_5/A5(/D5/D4) P2_6/AN2_6/A6(/D6/D5) P2_7/AN2_7/A7(/D7/D6) P3_0/A8(/-/D7) P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17 P4_2/A18 P4_3/A19 P7_4/TA2OUT/W P7_6/TA3OUT P5_6/ALE P7_7/TA3IN P5_5/HOLD P5_4/HLDA P5_3/BCLK P5_2/RD VCC2 VSS P5_7/RDY/CLKOUT P4_5/CS1 P4_6/CS2 P4_7/CS3 AVCC P6_3/TXD0/SDA0 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 P6_1/CLK0 P6_2/RXD0/SCL0 P10_0/AN0 P10_1/AN1 P10_2/AN2 P10_3/AN3 P9_3/DA0/TB3IN P9_4/DA1/TB4IN P9_5/ANEX0/CLK4 P9_6/ANEX1/SOUT4 P9_1/TB1IN/SIN3 P9_2/TB2IN/SOUT3 P8_0/TA4OUT/U P6_0/CTS0/RTS0 P6_4/CTS1/RTS1/CTS0/CLKS1 P7_2/CLK2/TA1OUT/V P8_2/INT0 P7_1/RXD2/SCL2/TA0IN/TB5IN (1) P8_3/INT1 P8_5/NMI P9_7/ADTRG/SIN4 P4_4/CS0 P5_0/WRL/WR P5_1/WRH/BHE P9_0/TB0IN/CLK3 P7_0/TXD2/SDA2/TA0OUT (1) P8_4/INT2/ZP P8_1/TA4IN/U P7_3/CTS2/RTS2/TA1IN/V P7_5/TA2IN/W P1_5/D13/INT3 P1_6/D14/INT4 P1_7/D15/INT5 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 <VCC2> (2) <VCC1> (2) M16C/62P Group (M16C/62P, M16C/62PT) NOTES: 1. P7_0 and P7_1 are N channel open-drain output pins. 2. Use the M16C/62PT on VCC1=VCC2. PIN CONFIGURATION (top view)

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 19 of 390 REJ09B0185-0241 Figure 1.8 Pin Configuration (Top View) 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 51525354555657585960616263646566676869707172737475 100 P0_0/AN0_0/D0 P0_1/AN0_1/D1 P0_2/AN0_2/D2 P0_3/AN0_3/D3 P0_4/AN0_4/D4 P0_5/AN0_5/D5 P0_6/AN0_6/D6 P0_7/AN0_7/D7 P1_0/D8 P1_1/D9 P1_2/D10 P1_3/D11 P1_4/D12 VREF AVSS VCC1 XIN XOUT VSS RESET CNVSS P8_7/XCIN P8_6/XCOUT BYTE P2_0/AN2_0/A0(/D0/-) P2_1/AN2_1/A1(/D1/D0) P2_2/AN2_2/A2(/D2/D1) P2_3/AN2_3/A3(/D3/D2) P2_4/AN2_4/A4(/D4/D3) P2_5/AN2_5/A5(/D5/D4) P2_6/AN2_6/A6(/D6/D5) P2_7/AN2_7/A7(/D7/D6) P3_0/A8(/-/D7) P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17 P4_2/A18 P4_3/A19 P7_4/TA2OUT/W P7_6/TA3OUT P5_6/ALE P7_7/TA3IN P5_5/HOLD P5_4/HLDA P5_3/BCLK P5_2/RD VCC2 VSS P5_7/RDY/CLKOUT P4_5/CS1 P4_6/CS2 P4_7/CS3 AVCC P6_3/TXD0/SDA0 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 P6_1/CLK0 P6_2/RXD0/SCL0 P10_0/AN0 P10_1/AN1 P10_2/AN2 P10_3/AN3 P9_3/DA0/TB3IN P9_4/DA1/TB4IN P9_5/ANEX0/CLK4 P9_6/ANEX1/SOUT4 P9_1/TB1IN/SIN3 P9_2/TB2IN/SOUT3 P8_0/TA4OUT/U P6_0/CTS0/RTS0 P6_4/CTS1/RTS1/CTS0/CLKS1 P8_2/INT0 P8_3/INT1 P8_5/NMI P9_7/ADTRG/SIN4 P4_4/CS0 P5_0/WRL/WR P5_1/WRH/BHE P9_0/TB0IN/CLK3 P8_4/INT2/ZP P7_2/CLK2/TA1OUT/V P7_1/RXD2/SCL2/TA0IN/TB5IN (1) P7_0/TXD2/SDA2/TA0OUT (1) P7_5/TA2IN/W P7_3/CTS2/RTS2/TA1IN/V P1_5/D13/INT3 P1_6/D14/INT4 P1_7/D15/INT5 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P8_1/TA4IN/U <VCC2> (2) <VCC1> (2) NOTES: 1. P7_0 and P7_1 are N channel open-drain output pins. 2. Use the M16C/62PT on VCC1=VCC2. PIN CONFIGURATION (top view) M16C/62P Group (M16C/62P, M16C/62PT)

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 20 of 390 REJ09B0185-0241 Table 1.13 Pin Characteristics for 100-Pin Package (1) Pin No. Control Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control PinFP GP 1 99 P9_6 SOUT4 ANEX1 2 100 P9_5 CLK4 ANEX0

31 P9_4 TB4IN DA1

4 2 P9_3 TB3IN DA0 5 3 P9_2 TB2IN SOUT3 6 4 P9_1 TB1IN SIN3 7 5 P9_0 TB0IN CLK3

86 B Y T E

10 8 XCIN P8_7 11 9 XCOUT P8_6 12 10 RESET 13 11 XOUT 14 12 VSS 15 13 XIN 16 14 VCC1 17 15 P8_5 NMI 18 16 P8_4 INT2 ZP 19 17 P8_3 INT1 20 18 P8_2 INT0 21 19 P8_1 TA4IN/U 22 20 P8_0 TA4OUT/U 23 21 P7_7 TA3IN 24 22 P7_6 TA3OUT 25 23 P7_5 TA2IN/W 26 24 P7_4 TA2OUT/W 27 25 P7_3 TA1IN/V CTS2/RTS2 28 26 P7_2 TA1OUT/V CLK2 29 27 P7_1 TA0IN/TB5IN RXD2/SCL2 30 28 P7_0 TA0OUT TXD2/SDA2 31 29 P6_7 TXD1/SDA1 32 30 P6_6 RXD1/SCL1 33 31 P6_5 CLK1 34 32 P6_4 CTS1 /RTS1/CTS0/CLKS1 35 33 P6_3 TXD0/SDA0 36 34 P6_2 RXD0/SCL0 37 35 P6_1 CLK0 38 36 P6_0 CTS0 /RTS0 39 37 P5_7 RDY/CLKOUT 40 38 P5_6 ALE 41 39 P5_5 HOLD 42 40 P5_4 HLAD 43 41 P5_3 BCLK 44 42 P5_2 RD 45 43 P5_1 WRH/BHE 46 44 P5_0 WRL/WR 47 45 P4_7 CS3 48 46 P4_6 CS2 49 47 P4_5 CS1 50 48 P4_4 CS0

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 21 of 390 REJ09B0185-0241 Table 1.14 Pin Characteristics for 100-Pin Package (2) Pin No. Control Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control PinFP GP 51 49 P4_3 A19 52 50 P4_2 A18 53 51 P4_1 A17 54 52 P4_0 A16 55 53 P3_7 A15 56 54 P3_6 A14 57 55 P3_5 A13 58 56 P3_4 A12 59 57 P3_3 A11 60 58 P3_2 A10 61 59 P3_1 A9 62 60 VCC2 64 62 VSS 65 63 P2_7 AN2_7 A7(/D7/D6) 66 64 P2_6 AN2_6 A6(/D6/D5) 67 65 P2_5 AN2_5 A5(/D5/D4) 68 66 P2_4 AN2_4 A4(/D4/D3) 69 67 P2_3 AN2_3 A3(/D3/D2) 70 68 P2_2 AN2_2 A2(/D2/D1) 71 69 P2_1 AN2_1 A1(/D1/D0) 73 71 P1_7 INT5 D15 74 72 P1_6 INT4 D14 75 73 P1_5 INT3 D13 76 74 P1_4 D12 77 75 P1_3 D11 78 76 P1_2 D10 79 77 P1_1 D9 80 78 P1_0 D8 81 79 P0_7 AN0_7 D7 82 80 P0_6 AN0_6 D6 83 81 P0_5 AN0_5 D5 84 82 P0_4 AN0_4 D4 85 83 P0_3 AN0_3 D3 86 84 P0_2 AN0_2 D2 87 85 P0_1 AN0_1 D1 88 86 P0_0 AN0_0 D0 89 87 P10_7 KI3 AN7 90 88 P10_6 KI2 AN6 91 89 P10_5 KI1 AN5 92 90 P10_4 KI0 AN4 93 91 P10_3 AN3 94 92 P10_2 AN2 95 93 P10_1 AN1 96 94 AVSS 97 95 P10_0 AN0 98 96 VREF 99 97 AVCC 100 98 P9_7 SIN4 ADTRG

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 22 of 390 REJ09B0185-0241 Figure 1.9 Pin Configuration (Top View) 44454647484950515253545557585960 P4_2 P3_0 P3_1 P3_2 P3_3 P3_4 P3_5 P3_6 P3_7 P4_0 P4_1 P0_0/AN0_0 P0_1/AN0_1 P0_2/AN0_2 P0_3/AN0_3 P0_4/AN0_4 P0_5/AN0_5 P0_6/AN0_6 P0_7/AN0_7 P10_1/AN1 P10_2/AN2 P10_3/AN3 P10_4/AN4/KI0 P10_5/AN5/KI1 P10_6/AN6/KI2 P10_7/AN7/KI3 P2_0/AN2_0 P2_1/AN2_1 P2_2/AN2_2 P2_4/AN2_4 P2_5/AN2_5 P2_6/AN2_6 P2_7/AN2_7 P2_3/AN2_3 M16C/62P Group (M16C/62P, M16C/62PT) NOTES: 1. P7_0 and P7_1 are N channel open-drain output pins. PIN CONFIGURATION (top view) 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 7 VCC1 XIN XOUT VSS RESET CNVSS(BYTE) P8_7/XCIN P8_6/XCOUT P9_3/DA0/TB3IN P9_4/DA1/TB4IN P9_5/ANEX0/CLK4 P8_2/INT0 P8_3/INT1 P8_1/TA4IN P8_4/INT2/ZP P8_0/TA4OUT P8_5/NMI VREF AVSS AVCC P10_0/AN0 P9_6/ANEX1/SOUT4 P9_0/TB0IN/CLK3 P9_7/ADTRG/SIN4 P9_2/TB2IN/SOUT3 18 19 20

26 P6_5/CLK1

P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 P7_1/RXD2/SCL2/TA0IN/TB5IN (1) P7_0/TXD2/SDA2/TA0OUT (1) P7_6/TA3OUT P7_7/TA3IN 414243 P4_3 P5_6 P5_5 P5_4 P5_3 P5_2 P5_7/CLKOUT P6_3/TXD0/SDA0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_0/CTS0/RTS0 P6_4/CTS1/RTS1/CTS0/CLKS1 P5_0 P5_1

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 23 of 390 REJ09B0185-0241 Table 1.15 Pin Characteristics for 80-Pin Package (1) Pin No. Control Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin

1 P9_5 CLK4 ANEX0

2P 9 _ 4 T B 4 I N D A 1

3 P9_3 TB3IN DA0

4 P9_2 TB2IN SOUT3

5 P9_0 TB0IN CLK3

6 CNVSS

(BYTE) 7X C I N P 8 _ 7 8X C O U T P 8 _ 6

9 RESET

10 XOUT

11 VSS

12 XIN

13 VCC1

14 P8_5 NMI

15 P8_4 INT2 ZP

16 P8_3 INT1

17 P8_2 INT0

18 P8_1 TA4IN

19 P8_0 TA4OUT

20 P7_7 TA3IN

21 P7_6 TA3OUT

22 P7_1 TA0IN/TB5IN RXD2/SCL2

23 P7_0 TA0OUT TXD2/SDA2

24 P6_7 TXD1/SDA1

25 P6_6 RXD1/SCL1

26 P6_5 CLK1

27 P6_4 CTS1

/RTS1/CTS0/CLKS1

28 P6_3 TXD0/SDA0

29 P6_2 RXD0/SCL0

30 P6_1 CLK0

31 P6_0 CTS0

/RTS0

32 P5_7 CLKOUT

33 P5_6

34 P5_5

35 P5_4

36 P5_3

37 P5_2

38 P5_1

39 P5_0

40 P4_3

41 P4_2

42 P4_1

43 P4_0

44 P3_7

45 P3_6

46 P3_5

47 P3_4

48 P3_3

49 P3_2

50 P3_1

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 24 of 390 REJ09B0185-0241 Table 1.16 Pin Characteristics for 80-Pin Package (2) Pin No. Control Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin

51 P3_0

52 P2_7 AN2_7

53 P2_6 AN2_6

54 P2_5 AN2_5

55 P2_4 AN2_4

56 P2_3 AN2_3

57 P2_2 AN2_2

58 P2_1 AN2_1

59 P2_0 AN2_0

60 P0_7 AN0_7

61 P0_6 AN0_6

62 P0_5 AN0_5

63 P0_4 AN0_4

64 P0_3 AN0_3

65 P0_2 AN0_2

66 P0_1 AN0_1

67 P0_0 AN0_0

68 P10_7 KI3

69 P10_6 KI2 AN6

70 P10_5 KI1 AN5

71 P10_4 KI0 AN4

72 P10_3 AN3

73 P10_2 AN2

74 P10_1 AN1

75 AVSS

76 P10_0 AN0

77 VREF

78 AVCC

79 P9_7 SIN4 ADTRG

80 P9_6 SOUT4 ANEX1

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 25 of 390 REJ09B0185-0241

1.6 Pin Description

I : Input O : Output I/O : Input and output Power Supply : Power supplies which relate to the external bus pins are separated as VCC2, thus they can be interfaced using the different voltage as VCC1. NOTES: 1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted. 3. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked. 4. Bus control pins in M16C/62PT cannot be used. Table 1.17 Pin Description (100-pin and 128-pin Version) (1) Signal Name Pin Name I/O Type Power Supply(3)

Description

VCC1,VCC2 VSS I − Apply 2.7 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS pin. The VCC apply condition is that VCC1 ≥ VCC2. (1, 2) Analog power supply input AVCC AVSS I VCC1 Applies the power supply for the A/D converter. Connect the AVCC pin to VCC1. Connect the AVSS pin to VSS. Reset input RESET IV C C 1 The microcomputer is in a reset state when applying “L” to the this pin. CNVSS CNVSS I VCC1 Switches processor mode. C onnect this pin to VSS to when after a reset to start up in single-chip mode. Connect this pin to VCC1 to start up in microprocessor mode. External data bus width select input BYTE I VCC1 Switches the data bus in exter nal memory space. The data bus is 16 bits long when the this pin is held "L" and 8 bits long when the this pin is held "H". Set it to either one. Connect this pin to VSS when an single-chip mode. Bus control pins (4) D0 to D7 I/O VCC2 Inputs and outputs data (D0 to D7) when these pins are set as the separate bus. D8 to D15 I/O VCC2 Inputs and outputs data (D8 to D15) when external 16-bit data bus is set as the separate bus. A0 to A19 O VCC2 Output address bits (A0 to A19). A0/D0 to A7/D7 I/O VCC2 Input and output data (D0 to D7) and output address bits (A0 to A7) by timesharing when external 8-bit data bus are set as the multiplexed bus. A1/D0 to A8/D7 I/O VCC2 Input and output data (D0 to D7 ) and output address bits (A1 to A8) by timesharing when external 16-bit data bus are set as the multiplexed bus. CS0 to CS3 O VCC2 Output CS0 to CS3 signals. CS0 to CS3 are chip-select signals to specify an external space. WRL/WR WRH/BHE RD O VCC2 Output WRL , WRH, (WR, BHE), RD signals. WRL and WRH or BHE and WR can be switched by program.

• WRL, WRH and RD are selected The WRL signal becomes "L" by writing data to an even address in an external memory space. The WRH signal becomes "L" by writing data to an odd address in an external memory space. The RD pin signal becomes "L" by reading data in an external memory space.
• WR, BHE and RD are selected The WR signal becomes "L" by writing data in an external memory space. The RD signal becomes "L" by reading data in an external memory space. The BHE signal becomes "L" by accessing an odd address. Select WR, BHE and RD for an external 8-bit data bus. ALE O VCC2 ALE is a signal to latch the address. HOLD I VCC2 While the HOLD pin is held "L", the microcomputer is placed in a hold state. HLDA O VCC2 In a hold state, HLDA outputs a "L" signal. RDY I VCC2 While applying a "L" signal to the RDY pin, the microcomputer is placed in a wait state.

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 26 of 390 REJ09B0185-0241 I : Input O : Output I/O : Input and output NOTES: 1. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked. 2. This pin function in M16C/62PT cannot be used. 3. Ask the oscillator maker the oscillation characteristic. Table 1.18 Pin Description (100-pin and 128-pin Version) (2) Signal Name Pin Name I/O Type Power Supply(1) XIN I VCC1 I/O pins for the main clock generation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT (3). To use the external clock, input the clock from XIN and leave XOUT open.Main clock output XOUT O VCC1 Sub clock input XCIN I VCC1 I/O pins for a sub clock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT (3). To use the external clock, input the clock from XCIN and leave XCOUT open. Sub clock output XCOUT O VCC1 BCLK output (2) BCLK O VCC2 Outputs the BCLK signal. Clock output CLKOUT O VCC2 The clock of the same cycle as fC, f8, or f32 is outputted. INT interrupt input INT0 to INT2 I VCC1 Input pins for the INT interrupt. NT3 to INT5 I VCC2 NMI interrupt input NMI I VCC1 Input pin for the NMI interrupt. Pin states can be read by the P8_5 bit in the P8 register. Key input interrupt input KI0 to KI3 I VCC1 Input pins for the key input interrupt. Timer A TA0OUT to TA4OUT I/O VCC1 These are timer A0 to timer A4 I/O pins. (however, output of TA0OUT for the N-channel open drain output.) TA0IN to TA4IN I VCC1 These are timer A0 to timer A4 input pins. ZP I VCC1 Input pin for the Z-phase. Timer B TB0IN to TB5IN I VCC1 These are timer B0 to timer B5 input pins. Three-phase motor control output U, U, V, V, W, W O VCC1 These are Three-phase motor control output pins. Serial interface CTS0 to CTS2 I VCC1 These are send control input pins. RTS0 to RTS2 O VCC1 These are receive control output pins. CLK0 to CLK4 I/O VCC1 These are transfer clock I/O pins. RXD0 to RXD2 I VCC1 These are serial data input pins. SIN3, SIN4 I VCC1 These are serial data input pins. TXD0 to TXD2 O VCC1 These are serial data output pins . (however, output of TXD2 for the N-channel open drain output.) SOUT3, SOUT4 O VCC1 These are serial data output pins. CLKS1 O VCC1 This is output pin for trans fer clock output from multiple pins function. I2C mode SDA0 to SDA2 I/O VCC1 These are serial data I/O pins. (however, output of SDA2 for the N- channel open drain output.) SCL0 to SCL2 I/O VCC1 These are transfer clock I/O pins. (however, output of SCL2 for the N-channel open drain output.)

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 27 of 390 REJ09B0185-0241 I : Input O : Output I/O : Input and output NOTES: 1. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked. 2. Ports P11 to P14 in M16C/62P (100-pin version) and M16C/62PT (100-pin version) cannot be used. Table 1.19 Pin Description (100-pin and 128-pin Version) (3) Signal Name Pin Name I/O Type Power Supply(1) VREF I VCC1 Applies the reference voltage for the A/D converter and D/A converter. A/D converter AN0 to AN7, AN0_0 to AN0_7, AN2_0 to AN2_7 I VCC1 Analog input pins for the A/D converter. ADTRG I VCC1 This is an A/D trigger input pin. ANEX0 I/O VCC1 This is the extended analog in put pin for the A/D converter, and is the output in external op-amp connection mode. ANEX1 I VCC1 This is the extended analog input pin for the A/D converter. D/A converter DA0, DA1 O VCC1 This is the output pin for the D/A converter. I/O port P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7 (2), P13_0 to P13_7 (2) I/O VCC2 8-bit I/O ports in CMOS, having a direction register to select an input or output. Each pin is set as an input port or output port. An input port can be set for a pull-up or for no pull-up in 4-bit unit by program. P6_0 to P6_7, P7_0 to P7_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7 (2) I/O VCC1 8-bit I/O ports having equivalent functions to P0. (however, output of P7_0 and P7_1 for the N-channel open drain output.) P8_0 to P8_4, P8_6, P8_7, P14_0, P14_1 (2) I/O VCC1 I/O ports having equivalent functions to P0. Input port P8_5 I VCC1 Input pin for the NMI interrupt. Pin states can be read by the P8_5 bit in the P8 register.

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 28 of 390 REJ09B0185-0241 I : Input O : Output I/O : Input and output NOTES: 1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted. 2. In M16C/62PT, apply 4.0 to 5.5 V to the VCC1 pin. 3. Ask the oscillator maker the oscillation characteristic. Table 1.20 Pin Description (80-pin Version) (1) (1) Signal Name Pin Name I/O Type Power Supply VCC1, VSS I − Apply 2.7 to 5.5 V to the VCC1 pin and 0 V to the VSS pin. (1, 2) Analog power supply input AVCC AVSS I VCC1 Applies the power supply for the A/D converter. Connect the AVCC pin to VCC1. Connect the AVSS pin to VSS. Reset input RESET IV C C 1 The microcomputer is in a reset state when applying “L” to the this pin. CNVSS CNVSS (BYTE) IV C C 1 Switches processor mode. Connect this pin to VSS to when after a reset to start up in single-chip mode. Connect this pin to VCC1 to start up in microprocessor mode. As for the BYTE pin of the 80-pin versions, pull-up processing is performed within the microcomputer. Main clock input XIN I VCC1 I/O pins for the main clock generation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT (3). To use the external clock, input the clock from XIN and leave XOUT open. Main clock output XOUT O VCC1 Sub clock input XCIN I VCC1 I/O pins for a sub cl ock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT (3). To use the external clock, input the clock from XCIN and leave XCOUT open. Sub clock output XCOUT O VCC1 Clock output CLKOUT O VCC2 The clock of the same cycle as fC, f8, or f32 is outputted. INT interrupt input INT0 to INT2 I VCC1 Input pins for the INT interrupt. NMI interrupt input NMI I VCC1 Input pin for the NMI interrupt. Key input interrupt input KI0 to KI3 I VCC1 Input pins for the key input interrupt. Timer A TA0OUT, TA3OUT, TA4OUT I/O VCC1 These are Timer A0,Timer A3 and Timer A4 I/O pins. (however, output of TA0OUT for the N-channel open drain output.) TA0IN, TA3IN, TA4IN I VCC1 These are Timer A0, Timer A3 and Timer A4 input pins. ZP I VCC1 Input pin for the Z-phase. Timer B TB0IN, TB2IN to TB5IN I VCC1 These are Timer B0, Timer B2 to Timer B5 input pins. Serial interface CTS0 to CTS1 I VCC1 These are send control input pins. RTS0 to RTS1 O VCC1 These are receive control output pins. CLK0, CLK1, CLK3, CLK4 I/O VCC1 These are transfer clock I/O pins. RXD0 to RXD2 I VCC1 These are serial data input pins. SIN4 I VCC1 This is serial data input pin. TXD0 to TXD2 O VCC1 These are serial data output pins. (however, output of TXD2 for the N-channel open drain output.) SOUT3, SOUT4 O VCC1 These are serial data output pins. CLKS1 O VCC1 This is output pin for transfe r clock output from multiple pins function. I 2C mode SDA0 to SDA2 I/O VCC1 These are serial data I/O pins. (however, output of SDA2 for the N-channel open drain output.) SCL0 to SCL2 I/O VCC1 These are transfer clock I/O pins. (however, output of SCL2 for the N-channel open drain output.)

M16C/62P Group (M16C/62P , M16C/62PT) 1. Overview Rev.2.41 Jan 10, 2006 Page 29 of 390 REJ09B0185-0241 I : Input O : Output I/O : Input and output NOTES: 1. There is no external connections for port P1, P4_4 to P 4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Set the direction bits in these ports to “1” (output mode), and set the output data to “0” (“L”) using the program. Table 1.21 Pin Description (80-pin Version) (2) Signal Name Pin Name I/O Type Power Supply(1) VREF I VCC1 Applies the reference voltage for the A/D converter and D/A converter. A/D converter AN0 to AN7, AN0_0 to AN0_7, AN2_0 to AN2_7 I VCC1 Analog input pins for the A/D converter. ADTRG I VCC1 This is an A/D trigger input pin. ANEX0 I/O VCC1 This is the extended analog in put pin for the A/D converter, and is the output in external op-amp connection mode. ANEX1 I VCC1 This is the extended analog input pin for the A/D converter. D/A converter DA0, DA1 O VCC1 This is the output pin for the D/A converter. I/O port (1) P0_0 to P0_7, P2_0 to P2_7, P3_0 to P3_7, P5_0 to P5_7, P6_0 to P6_7, P10_0 to P10_7 I/O VCC1 8-bit I/O ports in CMOS, having a direction register to select an input or output. Each pin is set as an input port or output port. An input port can be set for a pull-up or for no pull-up in 4-bit unit by program. P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7 I/O VCC1 I/O ports having equivalent functions to P0. P4_0 to P4_3, P7_0, P7_1, P7_6, P7_7 I/O VCC1 I/O ports having equivalent functions to P0. (however, output of P7_0 and P7_1 for the N-channel open drain output.) Input port P8_5 I VCC1 Input pin for the NMI interrupt. Pin states can be read by the P8_5 bit in the P8 register.

M16C/62P Group (M16C/62P , M16C/62PT) 2. Central Processing Unit (CPU) Rev.2.41 Jan 10, 2006 Page 30 of 390 REJ09B0185-0241 2. Central Processi ng Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks. Figure 2.1 Central Processing Unit Register

2.1 Data Registers (R 0, R1, R2 and R3)

The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are the same as R0. The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers. R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit data register (R2R0). R3R1 is the same as R2R0. Data Registers (1) Address Registers (1) Frame Base Registers (1) Program Counter Interrupt Table Register User Stack Pointer Interrupt Stack Pointer Static Base Register Flag Register NOTES: 1. These registers comprise a register bank. There are two register banks. R0H b15 b8b7 b0 INTBH USP ISP SB CDZSBOIUIPL R0L R1H R1L b31 FB b19 INTBL b15 b0 PC b19 b0 b15 b0 FLG b15 b0 b15 b0b7b8 Reserved Area Carry Flag Debug Flag Zero Flag Sign Flag Register Bank Select Flag Overflow Flag Interrupt Enable Flag Stack Pointer Select Flag Reserved Area Processor Interrupt Priority Level

M16C/62P Group (M16C/62P , M16C/62PT) 2. Central Processing Unit (CPU) Rev.2.41 Jan 10, 2006 Page 31 of 390 REJ09B0185-0241

2.2 Address Registers (A0 and A1)

The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).

2.3 Frame Base Register (FB)

FB is configured with 16 bits, and is used for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB is configured with 20 bits, indicating the start address of an interrupt vector table.

2.5 Program Counter (PC)

PC is configured with 20 bits, indicating the address of an instruction to be executed.

2.6 User Stack Pointer (USP) a nd Interrupt Stack Pointer (ISP)

Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG .

2.7 Static Base Register (SB)

SB is configured with 16 bits, and is used for SB relative addressing.

2.8 Flag Register (FLG)

FLG consists of 11 bits, indicating the CPU status.

2.8.1 Carry Flag (C Flag)

This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.

2.8.2 Debug Flag (D Flag)

The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.

2.8.3 Zero Flag (Z Flag)

This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.

2.8.4 Sign Flag (S Flag)

This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.

2.8.5 Register Bank Se lect Flag (B Flag)

Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.

2.8.6 Overflow Flag (O Flag)

This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.

2.8.7 Interrupt Enable Flag (I Flag)

This flag enables a maskable interrupt. Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag is cleared to “0” when the interrupt request is accepted.

M16C/62P Group (M16C/62P , M16C/62PT) 2. Central Processing Unit (CPU) Rev.2.41 Jan 10, 2006 Page 32 of 390 REJ09B0185-0241

2.8.8 Stack Pointer Select Flag (U Flag)

ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”. The U flag is cleared to “0” when a hardware interrupt request is accepte d or an INT instru ction for software interrupt Nos. 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than IPL, the interrupt is enabled.

2.8.10 Reserved Area

When write to this bit, write “0”. When read, its content is indeterminate.

M16C/62P Group (M16C/62P, M16C/62PT) 3. Memory Rev.2.41 Jan 10, 2006 Page 33 of 390 REJ09B0185-0241 3. Memory Figure 3.1 is a Memory Map of the M16C/62P group. The address space extends the 1M bytes from address 00000h to FFFFFh. The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 64-Kbyte internal ROM is allocated to the addresses from F0000h to FFFFFh. As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh. 4-Kbyte space is mainly for storing data. In addition to storing data, 4-Kbyte space also can store programs. The fixed interrupt vector table is allocated to the addres ses from FFFDCh to FFFFFh. Therefore, store the start address of each interrupt routine here. The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a 10-Kbyte internal RAM is allocated to the addresses from 00400h to 02BFFh. In addition to storing data, the internal RAM also stores the stack used when calling subroutines and when interrupts are generated. The SRF is allocated to th e addresses from 00000h to 003FFh. Peripheral f unction control registers are located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot be used by users. The special page vector table is allocat ed to the addresses from FFE00h to FF FDBh. This vector is used by the JMPS or JSRS instruction. For details, refer to the M16C/60 and M16C/20 Series Software Manual. In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be used by users. Use M16C/62P (80-pin version) and M16C/62PT in single -chip mode. The memory expansion and microprocessor modes cannot be used Figure 3.1 Memory Map 00000h XXXXXh External area Internal ROM (program area) (5) SFR Internal RAM Reserved area (1) Reserved area (2) FFFDCh NOTES: 1. During memory expansion and microprocessor modes, can be used. 2. In memory expansion mode, can be used. 3. As for the flash memory version, 4-Kbyte space (block A) exists. 4. Shown here is a memory map for the case where the PM10 bit in the PM1 register is “1” and the PM13 bit in the PM1 register is “1”. 5. When using the masked ROM version, write nothing to internal ROM area. Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer Reset Special page vector table DBC NMI

4 Kbytes 013FFh

10 Kbytes

5 Kbytes

12 Kbytes

96 Kbytes

48 Kbytes

64 Kbytes

256 Kbytes

128 Kbytes

192 Kbytes D0000h

320 Kbytes

384 Kbytes

512 Kbytes 80000h

24 Kbytes

20 Kbytes

31 Kbytes

Internal RAM Internal ROM (3) 043FFh16 Kbytes FFE00h FFFFFh Internal ROM (data area) (3) 0FFFFh 0F000h

M16C/62P Group (M16C/62P , M16C/62PT) 4. Special Function Register (SFR) Rev.2.41 Jan 10, 2006 Page 34 of 390 REJ09B0185-0241 4. Special Function Register (SFR) SFR(Special Function Register) is the c ontrol register of peripheral functions. Tables 4.1 to 4.6 list the SFR information. NOTES: 1. The blank areas are reserved and cannot be accessed by users. 2. The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset. 3. The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset. 4. The WDC5 bit is “0” (cold start) immediately after power-on. I t can only be set to “1” in a program. 5. This register does not change at software reset, watchdog timer reset and oscillation stop detection reset. 6. This register in M16C/62PT cannot be used. X : Nothing is mapped to this bit Table 4.1 SFR Information (1) (1) Address Register Symbol After Reset 0000h 0001h 0002h 0003h 0004h Processor Mode Register 0 (2) PM0 00000000b(CNVSS pin is “L”) 00000011b(CNVSS pin is “H”) 0005h Processor Mode Register 1 PM1 00001000b 0006h System Clock Control Register 0 CM0 01001000b 0007h System Clock Control Register 1 CM1 00100000b 0008h Chip Select Control Register (6) CSR 00000001b 0009h Address Match Interrupt Enable Register AIER XXXXXX00b 000Ah Protect Register PRCR XX000000b 000Bh Data Bank Register (6) DBR 00h 000Ch Oscillation Stop Detection Register (3) CM2 0X000000b 000Dh 000Eh Watchdog Timer Start Register WDTS XXh 000Fh Watchdog Timer Control Register WDC 00XXXXXXb (4) 0010h Address Match Interrupt Register 0 RMAD0 00h 0011h 00h 0012h X0h 0013h 0014h Address Match Interrupt Register 1 RMAD1 00h 0015h 00h 0016h X0h 0017h 0018h 0019h Voltage Detection Register 1 (5, 6) VCR1 00001000b 001Ah Voltage Detection Register 2 (5, 6) VCR2 00h 001Bh Chip Select Expansion Control Register (6) CSE 00h 001Ch PLL Control Register 0 PLC0 0001X010b 001Dh 001Eh Processor Mode Register 2 PM2 XXX00000b 001Fh Low Voltage Detection Interrupt Register (6) D4INT 00h 0020h DMA0 Source Pointer SAR0 XXh 0021h XXh 0022h XXh 0023h 0024h DMA0 Destination Pointer DAR0 XXh 0025h XXh 0026h XXh 0027h 0028h DMA0 Transfer Counter TCR0 XXh 0029h XXh 002Ah 002Bh 002Ch DMA0 Control Register DM0CON 00000X00b 002Dh 002Eh 002Fh 0030h DMA1 Source Pointer SAR1 XXh 0031h XXh 0032h XXh 0033h 0034h DMA1 Destination Pointer DAR1 XXh 0035h XXh 0036h XXh 0037h 0038h DMA1 Transfer Counter TCR1 XXh 0039h XXh 003Ah 003Bh 003Ch DMA1 Control Register DM1CON 00000X00b 003Dh 003Eh 003Fh

M16C/62P Group (M16C/62P , M16C/62PT) 4. Special Function Register (SFR) Rev.2.41 Jan 10, 2006 Page 35 of 390 REJ09B0185-0241 NOTES: 1. The blank areas are reserved an d cannot be accessed by users. X : Nothing is mapped to this bit Table 4.2 SFR Information (2) (1) Address Register Symbol After Reset 0040h 0041h 0042h 0043h 0044h INT3 Interrupt Control Register INT3IC XX00X000b 0045h Timer B5 Interrupt Control Register TB5IC XXXXX000b 0046h Timer B4 Interrupt Control Register, UART1 BUS Collision Detection Interrupt Control Register TB4IC, U1BCNIC XXXXX000b 0047h Timer B3 Interrupt Control Register, UART0 BUS Collision Detection Interrupt Control Register TB3IC, U0BCNIC XXXXX000b 0048h SI/O4 Interrupt Control Register, INT5 Interrupt Control Register S4IC, INT5IC XX00X000b 0049h SI/O3 Interrupt Control Register, INT4 Interrupt Control Register S3IC, INT4IC XX00X000b 004Ah UART2 Bus Collision Detection Interrupt Control Register BCNIC XXXXX000b 004Bh DMA0 Interrupt Control Register DM0IC XXXXX000b 004Ch DMA1 Interrupt Control Register DM1IC XXXXX000b 004Dh Key Input Interrupt Control Register KUPIC XXXXX000b 004Eh A/D Conversion Interrupt Control Register ADIC XXXXX000b 004Fh UART2 Transmit Interrupt Control Register S2TIC XXXXX000b 0050h UART2 Receive Interrupt Control Register S2RIC XXXXX000b 0051h UART0 Transmit Interrupt Control Register S0TIC XXXXX000b 0052h UART0 Receive Interrupt Control Register S0RIC XXXXX000b 0053h UART1 Transmit Interrupt Control Register S1TIC XXXXX000b 0054h UART1 Receive Interrupt Control Register S1RIC XXXXX000b 0055h Timer A0 Interrupt Control Register TA0IC XXXXX000b 0056h Timer A1 Interrupt Control Register TA1IC XXXXX000b 0057h Timer A2 Interrupt Control Register TA2IC XXXXX000b 0058h Timer A3 Interrupt Control Register TA3IC XXXXX000b 0059h Timer A4 Interrupt Control Register TA4IC XXXXX000b 005Ah Timer B0 Interrupt Control Register TB0IC XXXXX000b 005Bh Timer B1 Interrupt Control Register TB1IC XXXXX000b 005Ch Timer B2 Interrupt Control Register TB2IC XXXXX000b 005Dh INT0 Interrupt Control Register INT0IC XX00X000b 005Eh INT1 Interrupt Control Register INT1IC XX00X000b 005Fh INT2 Interrupt Control Register INT2IC XX00X000b 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh

M16C/62P Group (M16C/62P , M16C/62PT) 4. Special Function Register (SFR) Rev.2.41 Jan 10, 2006 Page 36 of 390 REJ09B0185-0241 NOTES: 1. The blank areas are reserved an d cannot be accessed by users. 2. This register is included in the flash memory version. X : Nothing is mapped to this bit Table 4.3 SFR Information (3) (1) Address Register Symbol After Reset 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h to 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h Flash Identification Register (2) FIDR XXXXXX00b 01B5h Flash Memory Control Register 1 (2) FMR1 0X00XX0Xb 01B6h 01B7h Flash Memory Control Register 0 (2) FMR0 00000001b 01B8h Address Match Interrupt Register 2 RMAD2 00h 01B9h 00h 01BAh XXh 01BBh Address Match Interrupt Enable Register 2 AIER2 XXXXXX00b 01BCh Address Match Interrupt Register 3 RMAD3 00h 01BDh 00h 01BEh XXh 01C0h to 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh Peripheral Clock Select Register PCLKR 00000011b 025Fh 0260h to 032Fh 0330h 0331h 0332h 0333h 0334h 0335h 0336h 0337h 0338h 0339h 033Ah 033Bh 033Ch 033Dh 033Eh 033Fh

M16C/62P Group (M16C/62P , M16C/62PT) 4. Special Function Register (SFR) Rev.2.41 Jan 10, 2006 Page 37 of 390 REJ09B0185-0241 NOTES: 1. The blank areas are reserved an d cannot be accessed by users. X : Nothing is mapped to this bit Table 4.4 SFR Information (4) (1) Address Register Symbol After Reset 0340h Timer B3, 4, 5 Count Start Flag TBSR 000XXXXXb 0341h 0342h Timer A1-1 Register TA11 XXh 0343h XXh 0344h Timer A2-1 Register TA21 XXh 0345h XXh 0346h Timer A4-1 Register TA41 XXh 0347h XXh 0348h Three-Phase PWM Control Register 0 INVC0 00h 0349h Three-Phase PWM Control Register 1 INVC1 00h 034Ah Three-Phase Output Buffer Register 0 IDB0 00h 034Bh Three-Phase Output Buffer Register 1 IDB1 00h 034Ch Dead Time Timer DTT XXh 034Dh Timer B2 Interrupt Occurrence Frequency Set Counter ICTB2 XXh 034Eh 034Fh 0350h Timer B3 Register TB3 XXh 0351h XXh 0352h Timer B4 Register TB4 XXh 0353h XXh 0354h Timer B5 Register TB5 XXh 0355h XXh 0356h 0357h 0358h 0359h 035Ah 035Bh Timer B3 Mode Register TB3MR 00XX0000b 035Ch Timer B4 Mode Register TB4MR 00XX0000b 035Dh Timer B5 Mode Register TB5MR 00XX0000b 035Eh Interrupt Factor Select Register 2 IFSR2A 00XXXXXXb 035Fh Interrupt Factor Select Register IFSR 00h 0360h SI/O3 Transmit/Receive Register S3TRR XXh 0361h 0362h SI/O3 Control Register S3C 01000000b 0363h SI/O3 Bit Rate Generator S3BRG XXh 0364h SI/O4 Transmit/Receive Register S4TRR XXh 0365h 0366h SI/O4 Control Register S4C 01000000b 0367h SI/O4 Bit Rate Generator S4BRG XXh 0368h 0369h 036Ah 036Bh 036Ch UART0 Special Mode Register 4 U0SMR4 00h 036Dh UART0 Special Mode Register 3 U0SMR3 000X0X0Xb 036Eh UART0 Special Mode Register 2 U0SMR2 X0000000b 036Fh UART0 Special Mode Register U0SMR X0000000b 0370h UART1 Special Mode Register 4 U1SMR4 00h 0371h UART1 Special Mode Register 3 U1SMR3 000X0X0Xb 0372h UART1 Special Mode Register 2 U1SMR2 X0000000b 0373h UART1 Special Mode Register U1SMR X0000000b 0374h UART2 Special Mode Register 4 U2SMR4 00h 0375h UART2 Special Mode Register 3 U2SMR3 000X0X0Xb 0376h UART2 Special Mode Register 2 U2SMR2 X0000000b 0377h UART2 Special Mode Register U2SMR X0000000b 0378h UART2 Transmit/Receive Mode Register U2MR 00h 0379h UART2 Bit Rate Generator U2BRG XXh 037Ah UART2 Transmit Buffer Register U2TB XXh 037Bh XXh 037Ch UART2 Transmit/Receive Control Register 0 U2C0 00001000b 037Dh UART2 Transmit/Receive Control Register 1 U2C1 00000010b 037Eh UART2 Receive Buffer Register U2RB XXh 037Fh XXh

M16C/62P Group (M16C/62P , M16C/62PT) 4. Special Function Register (SFR) Rev.2.41 Jan 10, 2006 Page 38 of 390 REJ09B0185-0241 NOTES: 1. The blank areas are reserved an d cannot be accessed by users. 2. Bit 5 in the Up-down flag is “0” by reset. However, The values in these bits when read are indeterminate. X : Nothing is mapped to this bit Table 4.5 SFR Information (5) (1) Address Register Symbol After Reset 0380h Count Start Flag TABSR 00h 0381h Clock Prescaler Reset Fag CPSRF 0XXXXXXXb 0382h One-Shot Start Flag ONSF 00h 0383h Trigger Select Register TRGSR 00h 0384h Up-Down Flag UDF 00h (2) 0385h 0386h Timer A0 Register TA0 XXh 0387h XXh 0388h Timer A1 Register TA1 XXh 0389h XXh 038Ah Timer A2 Register TA2 XXh 038Bh XXh 038Ch Timer A3 Register TA3 XXh 038Dh XXh 038Eh Timer A4 Register TA4 XXh 038Fh XXh 0390h Timer B0 Register TB0 XXh 0391h XXh 0392h Timer B1 Register TB1 XXh 0393h XXh 0394h Timer B2 Register TB2 XXh 0395h XXh 0396h Timer A0 Mode Register TA0MR 00h 0397h Timer A1 Mode Register TA1MR 00h 0398h Timer A2 Mode Register TA2MR 00h 0399h Timer A3 Mode Register TA3MR 00h 039Ah Timer A4 Mode Register TA4MR 00h 039Bh Timer B0 Mode Register TB0MR 00XX0000b 039Ch Timer B1 Mode Register TB1MR 00XX0000b 039Dh Timer B2 Mode Register TB2MR 00XX0000b 039Eh Timer B2 Special Mode Register TB2SC XXXXXX00b 039Fh 03A0h UART0 Transmit/Receive Mode Register U0MR 00h 03A1h UART0 Bit Rate Generator U0BRG XXh 03A2h UART0 Transmit Buffer Register U0TB XXh 03A3h XXh 03A4h UART0 Transmit/Receive Control Register 0 U0C0 00001000b 03A5h UART0 Transmit/Receive Control Register 1 U0C1 00XX0010b 03A6h UART0 Receive Buffer Register U0RB XXh 03A7h XXh 03A8h UART1 Transmit/Receive Mode Register U1MR 00h 03A9h UART1 Bit Rate Generator U1BRG XXh 03AAh UART1 Transmit Buffer Register U1TB XXh 03ABh XXh 03ACh UART1 Transmit/Receive Control Register 0 U1C0 00001000b 03ADh UART1 Transmit/Receive Control Register 1 U1C1 00XX0010b 03AEh UART1 Receive Buffer Register U1RB XXh 03AFh XXh 03B0h UART Transmit/Receive Control Register 2 UCON X0000000b 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h DMA0 Request Factor Select Register DM0SL 00h 03B9h 03BAh DMA1 Request Factor Select Register DM1SL 00h 03BBh 03BCh CRC Data Register CRCD XXh 03BDh XXh 03BEh CRC Input Register CRCIN XXh 03BFh

M16C/62P Group (M16C/62P , M16C/62PT) 4. Special Function Register (SFR) Rev.2.41 Jan 10, 2006 Page 39 of 390 REJ09B0185-0241 NOTES: 1. The blank areas are reserved an d cannot be accessed by users. 2. At hardware reset 1 or hardware reset 2, the register is as follows:

• “00000000b” where “L” is inputted to the CNVSS pin
• “00000010b” where “H” is inputted to the CNVSS pin At software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows:
• “00000000b” where the PM01 to PM00 bits in the PM0 register are “00b” (single-chip mode).
• “00000010b” where the PM01 to PM00 bits in the PM0 register are “01b” (memory expansion mode) or “11b” (microprocessor mode). 3. These registers do not exist in M16C/62P ( 80-pin version), and M16C/62PT (80-pin version). X : Nothing is mapped to this bit Table 4.6 SFR Information (6) (1) Address Register Symbol After Reset 03C0h A/D Register 0 AD0 XXh 03C1h XXh 03C2h A/D Register 1 AD1 XXh 03C3h XXh 03C4h A/D Register 2 AD2 XXh 03C5h XXh 03C6h A/D Register 3 AD3 XXh 03C7h XXh 03C8h A/D Register 4 AD4 XXh 03C9h XXh 03CAh A/D Register 5 AD5 XXh 03CBh XXh 03CCh A/D Register 6 AD6 XXh 03CDh XXh 03CEh A/D Register 7 AD7 XXh 03CFh XXh 03D0h 03D1h 03D2h 03D3h 03D4h A/D Control Register 2 ADCON2 00h 03D5h 03D6h A/D Control Register 0 ADCON0 00000XXXb 03D7h A/D Control Register 1 ADCON1 00h 03D8h D/A Register 0 DA0 00h 03D9h 03DAh D/A Register 1 DA1 00h 03DBh 03DCh D/A Control Register DACON 00h 03DDh 03DEh Port P14 Control Register (3) PC14 XX00XXXXb 03DFh Pull-Up Control Register 3 (3) PUR3 00h 03E0h Port P0 Register P0 XXh 03E1h Port P1 Register P1 XXh 03E2h Port P0 Direction Register PD0 00h 03E3h Port P1 Direction Register PD1 00h 03E4h Port P2 Register P2 XXh 03E5h Port P3 Register P3 XXh 03E6h Port P2 Direction Register PD2 00h 03E7h Port P3 Direction Register PD3 00h 03E8h Port P4 Register P4 XXh 03E9h Port P5 Register P5 XXh 03EAh Port P4 Direction Register PD4 00h 03EBh Port P5 Direction Register PD5 00h 03ECh Port P6 Register P6 XXh 03EDh Port P7 Register P7 XXh 03EEh Port P6 Direction Register PD6 00h 03EFh Port P7 Direction Register PD7 00h 03F0h Port P8 Register P8 XXh 03F1h Port P9 Register P9 XXh 03F2h Port P8 Direction Register PD8 00X00000b 03F3h Port P9 Direction Register PD9 00h 03F4h Port P10 Register P10 XXh 03F5h Port P11 Register (3) P11 XXh 03F6h Port P10 Direction Register PD10 00h 03F7h Port P11 Direction Register (3) PD11 00h 03F8h Port P12 Register (3) P12 XXh 03F9h Port P13 Register (3) P13 XXh 03FAh Port P12 Direction Register (3) PD12 00h 03FBh Port P13 Direction Register (3) PD13 00h 03FCh Pull-Up Control Register 0 PUR0 00h 03FDh Pull-Up Control Register 1 PUR1 00000000b (2) 00000010b (2) 03FEh Pull-Up Control Register 2 PUR2 00h 03FFh Port Control Register PCR 00h

M16C/62P Group (M16C/62P , M16C/62PT) 5. Reset Rev.2.41 Jan 10, 2006 Page 40 of 390 REJ09B0185-0241 5. Reset Hardware reset 1, brown-out detection reset (hardware reset 2), software reset, watchdog timer reset and oscillation stop detection reset are available to reset the microcomputer.

5.1 Hardware Reset 1

The microcomputer resets pins, the CPU and SFR by setting the RESET pin. If the suppl y voltage meets the recommended operating conditions, the microcomputer resets all pins when an “L” signal is applied to the RESET pin (see Table 5.1 Pin Status When RESET Pin Level is “L”). The oscillation circuit is also reset and the main clock starts oscillation. The microco mputer resets the CPU and SFR when the signal applied to the RESET pin changes low (“L”) to high (“H”). Th e microcomputer executes the program in an address indicated by the reset vector. The internal RAM is not reset. Wh en an “L” signal is applied to the RESET pin while writing data to the internal RAM, the internal RAM is in an indeterminate state. RESET Pin Level is “L”. Figure 5.3 shows CPU Register Status After Reset. Refer to 4. Special Function Register (SFR) for SFR states after reset.

5.1.1 Reset on a Stable Supply Voltage

(1) Apply “L” to the RESET pin (2) Apply 20 or more clock cycles to the XIN pin (3) Apply an “H” signal to the RESET pin

5.1.2 Power-on Reset

(1) Apply “L” to the RESET pin (2) Raise the supply voltage to the recommended operating level (3) Insert td(P-R) ms as wait time for the internal voltage to stabilize (4) Apply 20 or more clock cycles to the XIN pin (5) Apply “H” to the RESET pin Figure 5.1 Example Reset Circuit RESET VCC1 RESET VCC1 Recommended operation voltage 0.2VCC1 or below 0.2VCC1 or below Supply a clock with td(P-R) + 20 or more cycles to the XIN pin NOTES: 1. If VCC1>VCC2, the VCC2 voltage must be lower than that of VCC1 when the power is being turned on or off.

M16C/62P Group (M16C/62P , M16C/62PT) 5. Reset Rev.2.41 Jan 10, 2006 Page 41 of 390 REJ09B0185-0241 Figure 5.2 Reset Sequence td(P-R) More than 20 cycles are needed BCLK Address Address Address Microprocessor mode BYTE = H Microprocessor mode BYTE = L Single chip mode XIN RESET RD WR CS0 RD WR CS0 Content of reset vector BCLK 28cycles FFFFCh FFFFDh FFFFEh Content of reset vector FFFFCh FFFFEh Content of reset vector FFFFEh FFFFCh VCC1, VCC2

M16C/62P Group (M16C/62P , M16C/62PT) 5. Reset Rev.2.41 Jan 10, 2006 Page 42 of 390 REJ09B0185-0241 NOTES: 1. Shown here is the valid pin state when the inte rnal power supply voltage has stabilized after power on. When CNVSS = VCC1, the pin state is indetermin ate until the internal power supply voltage stabilizes. 2. P11, P12, P13, P14_0, P14_1 pins exist in 128-pin version.

5.2 Brown-out Detection Reset (Hardware Reset 2)

The microcomputer resets pins, the CPU or SFR by setting the built-in voltage detect circuit. The voltage detect circuit monitors the voltage applied to the VCC1 pin. When the VC26 bit in the VCR2 register is set to “1” (reset level detect circuit enabled), the microcomputer resets pins, the CPU and SFR as soon as the voltage that is applied to the VCC1 pin drops to Vdet3 or below. The microcomputer resets pins and it is in a reset stat e when the voltage that is applied to the VCC1 pin is Vdet3 or below. The microcomputer resets pins, CPU and SFR with Vdet3r or above and it executes the program from the address determined by the reset v ector. The microcomputer executes the program after detecting Vdet3r and waiting td(S-R) ms. The same pins and registers are reset by the hardware reset 1 and brown-out detection reset (hardware reset 2), and are also placed in the same reset state. The microcomputer cannot exit stop mode by the brown-out detection reset (hardware reset 2). Table 5.1 Pin Status When RESET Pin Level is “L” Pin Name Status CNVSS = VSS CNVSS = VCC1 (1) BYTE = VSS BYTE = VCC1 P0 Input port Data input Data input P1 Input port Data input Input port P2, P3, P4_0 to P4_3 Input port Address output (underfined) Address output (underfined) P4_4 Input port CS0 output (“H” is output) CS0 output (“H” is output) P4_5 to P4_7 Input port Input port (P ulled high) Input port (Pulled high) P5_0 Input port WR output (“H” is output) WR output (“H” is output) P5_1 Input port BHE output (undefined) BHE output (undefined) P5_2 Input port RD output (“H” is output) RD output (“H” is output) P5_3 Input port BCLK output BCLK output P5_4 Input port HLDA output (The output value depends on the input to the HOLD pin) HLDA output (The output value depends on the input to the HOLD pin) P5_5 Input port HOLD input HOLD input P5_6 Input port ALE output (“L” is output) ALE output (“L” is output) P5_7 Input port RDY input RDY input P6, P7, P8_0 to P8_4, Input port Input port Input port P11, P12, P13, P14_0, P14_1 (2) Input port Input port Input port

M16C/62P Group (M16C/62P , M16C/62PT) 5. Reset Rev.2.41 Jan 10, 2006 Page 43 of 390 REJ09B0185-0241

5.3 Software Reset

The microcomputer resets pins, the CPU and SFR when the PM03 bit in the PM0 register is set to “1” (microcomputer reset). Then the microcomputer executes the program in an address determined by the reset vector. Set the PM03 bit to “1” while the main clock is selected as the CPU clock and the main clock oscillation is stable. In the software reset, the microcomputer do es not reset a part of the SFR. Refer to 4. Special Function Register (SFR) for details. Processor mode remains unchanged since the PM01 to PM00 bits in the PM0 register are not reset.

5.4 Watchdog Timer Reset

The microcomputer resets pins, the CPU and SFR when the CM 06 bit in the CM0 register is set to “1” (reset) and the watchdog timer underflows. Then the microcomputer executes the program in an address determined by the reset vector. In the watchdog timer reset, the microcompute r does not reset a part of the SFR. Refer to 4. Special Function Register (SFR) for details. Processor mode remains unchanged since the PM01 to PM00 bits in the PM0 register are not reset.

5.5 Oscillation Stop Detection Reset

The microcomputer resets and stops pins, the CPU and SF R when the CM27 bit in the CM2 register is 0, if it detects main clock oscillation circuit stop. Refer to 10.6 Oscillation Stop and Re-oscillation Detect Function for details. In the oscillation stop detection reset, the microcomp uter does not reset a part of the SFR. Refer to 4. Special Function Register (SFR) for details. Processor mode remains unchan ged since the PM01 to PM00 bits in the PM0 register are not reset.

M16C/62P Group (M16C/62P , M16C/62PT) 5. Reset Rev.2.41 Jan 10, 2006 Page 44 of 390 REJ09B0185-0241

5.6 Internal Space

Figure 5.3 shows CPU Register Status After Reset. Refer to 4. Special Function Register (SFR) for SFR states after reset. Figure 5.3 CPU Register Status After Reset b15 b0 Data Register(R0) Address Register(A0) Frame Base Register(FB) Program Counter(PC) Interrupt Table Register(INTB) User Stack Pointer(USP) Interrupt Stack Pointer(ISP) Static Base Register(SB) Flag Register(FLG) 0000h 0000h 0000h CDZSBOIUIPL 0000h 0000h 0000h 0000h 0000h b19 b0 Content of addresses FFFFEh to FFFFCh b15 b0 b15 b0 b15 b0b7b8 00000h Data Register(R1) Data Register(R2) Data Register(R3) Address Register(A1) 0000h 0000h 0000h

M16C/62P Group (M16C/62P , M16C/62PT) 6. Voltage Detection Circuit Rev.2.41 Jan 10, 2006 Page 46 of 390 REJ09B0185-0241 Figure 6.2 VCR1 and VCR2 Registers Voltage Detection Register 1 Address After Reset (2) 0019h 00001000b Bit Symbol Function RW —S e t t o “ 0 ” (b2-b0) —S e t t o “ 0 ” (b7-b4) NOTES : The VC13 bit is useful w hen the VC27 bit in the VCR2 register is set to “1” (low voltage detection circuit enable). The VC13 bit is alw ays “1” (VCC1 ≥ Vdet4) w hen the VC27 bit is set to “0” (low voltage detection circuit disable). This register dose not change at softw are reset, w atchdog timer reset and oscillation stop detection reset. Bit Name VC R 1 Symbol0 0 : VCC1 < Vdet4 1 : VCC1 ≥ Vdet4 0000 RWReserved Bit Low Voltage Monitor Flag (1) b7 b6 b5 b4 b3 b2 b1 RWReserved Bit ROVC 13 Voltage Detection Register 2 (1) Address After Reset (5) 001Ah 00h Bit Symbol Function RW —S e t t o “ 0 ” (b5-b0) NOTES : To use low voltage detection (hardw are reset 2), set the VC26 bit to “1” (reset level detection circuit enable). Write to this register after setting the PRC3 bit in the PRCR register to “1” (w rite enable). Bit Name VC R 2 Symbol00 0 : Disable reset level detection circuit 1 : Enable reset level detection circuit 000 b3 b2 b1 b0b7 b6 b5 b4 RWVC 26 RWReserved Bit Reset Level Monitor Bit (2, 3, 6) RWLow Voltage Monitor Bit (4, 6) VC 27 0 : Disable low voltage detection circuit 1 : Enable low voltage detection circuit VC26 bit is disabled in stop mode (the microcomputer is not reset even if the voltage input to VCC1 pin becomes low er than Vdet3). Where the VC13 bit in the VCR1 register and D42 bit in the D4INT register are used or the D40 bit is set to “1” (low voltage detection interrupt enable), set the VC27 bit to “1” (low voltage detection circuit enable). This register dose not change at softw are reset, w atchdog timer reset and oscillation stop detection reset. The detection circuit dose not start operation until td(E-A) elapses after the VC26 bit, or VC27 bit is set to “1”.

M16C/62P Group (M16C/62P , M16C/62PT) 6. Voltage Detection Circuit Rev.2.41 Jan 10, 2006 Page 47 of 390 REJ09B0185-0241 Figure 6.3 D4INT Register Low Voltage Detection Interrupt Register (1) Symbol Address After Reset D4INT 001Fh 00h Bit Symbol Bit Name Function RW NOTES : b7 b6 b5 b4 b3 b2 b1 b0 D40 Low Voltage Detection Interrupt Enable Bit (5) 0 : Disable 1 : Enable RW D41 STOP Mode Deactivation Control Bit (4) 0 : Disable (do not use the Low voltage detection interrupt to get out of stop mode) 1 : Enable (use the low voltage detection interrupt to get out of stop mode) RW D42 Voltage Change Detection Flag (2) 0 : Not detected 1 : Vdet4 passing detection RW (3) D43 WDT Overflow Detect Flag 0 : Not detected 1 : Detected RW (3) DF0 Sampling Clock Select Bit b5 b4 0 0 : CPU clock divided by 8 0 1 : CPU clock divided by 16 1 0 : CPU clock divided by 32 1 1 : CPU clock divided by 64 RW DF1 RW (b7-b6) Nothing is assigned. When w rite, set to “0”. When read, their contents are “0”. — Write to this register after setting the PRC3 bit in the PRCR register to “1” (w rite enable). Useful w hen the VC27 bit in the VCR2 register is set to “1” (low voltage detection circuit enabled). If the VC27 bit is set to “0” (low voltage detection circuit disabled), the D42 bit is set to “0” (Not detect). This bit is set to “0” by w riting a “0” in a program. (Writing a “1” has no effect.) If the low voltage detection interrupt needs to be used to get out of stop mode again after once used for that purpose, reset the D41 bit by w riting a “0” and then a “1”. The D40 bit is effective w hen the VC27 bit = 1. To set the D40 bit to “1”, set bits in the follow ing order. (a) Set the VC27 bit to “1”. (b) Wait for td(E-A) until the detection circuit is actuated. (c) Wait for the sampling time. (See Table 6.2 Sampling Period .) (d) Set the D40 bit to “1”.

M16C/62P Group (M16C/62P , M16C/62PT) 6. Voltage Detection Circuit Rev.2.41 Jan 10, 2006 Page 48 of 390 REJ09B0185-0241 Figure 6.4 Typical Operation of Brown- out Detection Reset (Hardware Reset 2) Vdet4 Vdet3 5.0V 5.0V VCC1 Internal Reset Signal VC13 bit in VCR1 register VC26 bit in VCR2 register (1) VC27 bit in VCR2 register Set to “1” by program (reset level detect circuit enable) Set to “1” by program (Low voltage detection circuit enable) VSS Indefinite Indefinite Indefinite RESET Vdet3s Vdet3r NOTES : 1. VC26 bit is invalid (the microcomputer is not reset even if input voltage of VCC1 pin becomes lower than Vdet3).

M16C/62P Group (M16C/62P , M16C/62PT) 6. Voltage Detection Circuit Rev.2.41 Jan 10, 2006 Page 49 of 390 REJ09B0185-0241

6.1 Low Voltage Detection Interrupt

If the D40 bit in the D4INT register is set to “1” (low voltage detection interrupt enabled), the low voltage detection interrupt request is generated when the voltage applied to the VCC1 pin is above or below Vdet4. The low voltage detection interrupt shares the same in terrupt vector with the watchdog timer interrupt and oscillation stop, re-oscillation detection interrupt. Set the D41 bit in the D4INT register to “1” (enabled) to use the low voltage detection interrupt to exit stop mode. The D42 bit in the D4INT register is set to “1” as soon as the voltage applied to the VCC1 pin reaches Vdet4 due to the voltage rise and voltage drop. When the D42 bit changes “0” to “1”, the low voltage detection interrupt request is generated. Set the D42 bit to “0” by program. However, when the D41 bit is set to “1” and the microcomputer is in stop mode, the low voltage detection interrupt request is generated regardless of the D42 bit state if the voltage applied to the VCC1 pin is detected to be above Vdet4. The microcomputer then exits stop mode. Table 6.1 shows Low V oltage Detection Interrupt Request Generation Conditions. The DF1 to DF0 bits in the D4INT register determine the sampling period that detects the voltage applied to the VCC1 pin reaches Vdet4. Table 6.2 shows the Sampling Periods. 1. The status except the wait mode and stop mo de is handled as the normal mode. (Refer to 10. Clock Generation Circuit) 2. Refer to 6.2 Limitations on Exiting Stop Mode, 6.3 Limitations on Exiting Wait Mode. 3. An interrupt request for voltage reduction is gen erated a sampling time after the value of the VC13 bit has changed. See the Figure 6.6 Low Voltage Detection Interrupt Generation Circuit Operation Example for details. Table 6.1 Low Voltage Detection Interrupt Request Generation Conditions Operating Mode VC27 Bit D40 Bit D41 Bit D42 Bit CM02 Bit VC13 Bit Normal Operating Mode (1) − 0 to 1 − 0 to 1 (3) 1 to 0 (3) Wait Mode (2) − 0 to 1 0 0 to 1 (3) 1 to 0 (3) 1 − 1 0 to 1 Stop Mode (2) − 0 0 to 1 Table 6.2 Sampling Periods CPU Clock (D4INT clock) (MHz) Sampling Clock (µs) DF1 to DF0=00 (CPU clock divided by 8) DF1 to DF0=01 (CPU clock divided by 16) DF1 to DF0=10 (CPU clock divided by 32) DF1 to DF0=11 (CPU clock divided by 64) 16 3.0 6.0 12.0 24.0

M16C/62P Group (M16C/62P , M16C/62PT) 6. Voltage Detection Circuit Rev.2.41 Jan 10, 2006 Page 51 of 390 REJ09B0185-0241

6.2 Limitations on Exiting Stop Mode

The low voltage detection interrupt is immediately gene rated and the microcomputer exits stop mode if the CM10 bit in the CM1 register is set to “1” under the conditions below.

• the VC27 bit in the VCR2 register is set to “1” (low voltage detection circuit enabled),
• the D40 bit in the D4INT register is set to “1” (low voltage detection interrupt enabled),
• the D41 bit in the D4INT register is set to “1” (low voltage detection interrupt is used to exit stop mode), and
• the voltage applied to the VCC1 pin is higher than Vdet4 (the VC13 bit in the VCR1 register is “1”) If the microcomputer is set to enter stop mode when the voltage applied to the VCC1 pin drops below Vdet4 and to exit stop mode when the voltage applied rises to Vdet4 or above, set the CM10 bit to “1” when VC13 bit is “0” (VCC1 < Vdet4).

6.3 Limitations on Exiting Wait Mode

The low voltage detection interrupt is immediately generated and the microcomputer exits wait mode If WAIT instruction is executed under the conditions below.

• the CM02 bit in the CM0 register is set to “1” (stop peripheral function clock),
• the VC27 bit in the VCR2 register is set to “1” (low voltage detection circuit enabled),
• the D40 bit in the D4INT register is set to “1” (low voltage detection interrupt enabled),
• the D41 bit in the D4INT register is set to “1” (low voltage detection interrupt is used to exit wait mode), and
• the voltage applied to the VCC1 pin is higher than Vdet4 (the VC13 bit in the VCR1 register is “1”) If the microcomputer is set to enter wait mode when the voltage applied to the VCC1 pin drops below Vdet4 and to exit wait mode when the voltage applied rises to Vdet4 or above, perform WAIT instruction when VC13 bit is “0” (VCC1 < Vdet4).

M16C/62P Group (M16C/62P , M16C/62PT) 6. Voltage Detection Circuit Rev.2.41 Jan 10, 2006 Page 52 of 390 REJ09B0185-0241

6.4 Cold Start-up / Warm Start-up Determine Function

As for the cold start-up/warm start-up determine function, the WDC5 flag in the WDC register determines either cold start-up (reset process) when power-on or warm start-up (reset process) when reset signal is applied during the microcomputer running. Default value of the WDC5 bit is “0” (cold start-up) when power-on. It is set to “1” (warm start-up) by writing desired values to the WDC register. The WDC bit is not reset, regardless of a software reset or a reset operation. Figure 6.7 shows Cold Start-up/Warm Start-up Determin e Function Block Diagram. Figure 6.8 shows the Cold Start-up/Warm Start-up Determine Function Operation Example. Figure 6.9 shows WDC Register. Figure 6.7 Cold Start-up/Warm Start-up Determine Function Block Diagram Figure 6.8 Cold Start-up/Warm Start-up Determine Function Operation Example Write to WDC register S R Q WARM/COLD WDC5 Bit (Cold start, warm start) Internal power on reset “1” is held even if RESET becomes 0V. Program start Pch transistor ON (about 4V) CPU reset is deasserted Set to “1” by program Becomes “0” on the rising edge of VCC “1” “0” VCC RESET Reset Sequence (16MHz, about 20 µsec.) WDC5 Flag NOTES: 1. The timing of which WDC5 is set is affected by how the RESET signal rises (Time lag between T1 and T2). T > 100 µsec.

M16C/62P Group (M16C/62P , M16C/62PT) 6. Voltage Detection Circuit Rev.2.41 Jan 10, 2006 Page 53 of 390 REJ09B0185-0241 Figure 6.9 WDC Register Watchdog Timer Control Register Symbol Address After Reset WDC 000Fh 00XXXXXXb (2) Bit Symbol Bit Name Function RW NOTES : WDC5 RW (b4-b0) ROHigh-order Bit of Watchdog Timer Cold Start / Warm Start Discrimination Flag (1, 2) 0 : Cold Start 1 : Warm Start b7 b6 b5 b4 b3 b2 b1 b0 The WDC5 bit is set to “0” (cold start) w hen pow er is turned on and can be set to “1” by program only. WDC7 (b6) Reserved Bit Set to “0” Prescaler Select Bit 0 : Divided by 16 1 : Divided by 128 RW RW Writing to the WDC register factors the WDC5 bit to be set to “1” (w arm start). If the voltage applied to VCC1 is less than 4.0 V, either w rite to this register w hen the CPU clock frequency is 2 MHz or w rite tw ice.

M16C/62P Group (M16C/62P , M16C/62PT) 7. Processor Mode Rev.2.41 Jan 10, 2006 Page 54 of 390 REJ09B0185-0241 7. Processor Mode

7.1 Types of Processor Mode

Three processor modes are available to choose from: single-chip mode, memory expansion mode, and microprocessor mode. Table 7.1 shows the Features of Processor Modes. NOTES: 1. Refer to 8. Bus. Table 7.1 Features of Processor Modes Processor Modes Access Space Pins which are Assigned I/O Ports Single-Chip Mode SFR, Internal RAM, Internal RO M All pins are I/O ports or peripheral function I/O pins Memory Expansion Mode SFR, Internal RAM, Internal ROM, External Area (1) Some pins serve as bus control pins (1) Microprocessor Mode SFR, Internal RAM, External Area (1) Some pins serve as bus control pins (1) The M16C/62P (80-pin version) and M16C/62PT do not use memory expansion mode, and microprocessor mode. Note

M16C/62P Group (M16C/62P , M16C/62PT) 7. Processor Mode Rev.2.41 Jan 10, 2006 Page 55 of 390 REJ09B0185-0241

7.2 Setting Processor Modes

Processor mode is set by using the CNVSS pin and the PM01 to PM00 bits in the PM0 register. Table 7.2 shows the Processor Mode Af ter Hardware Reset. Table 7.3 show s the PM01 to PM00 Bits Set Values and Processor Modes. NOTES: 1. If the microcomputer is reset in hardware by applying VCC1 to the CNVSS pin (hardware reset 1 or brown-out detection reset (hardware reset 2)), the internal ROM cannot be accessed regardless of PM10 to PM00 bits. 2. The multiplexed bus cannot be assigned to the entire CS space. Rewriting the PM01 to PM00 bits places the microcomput er in the corresponding pr ocessor mode regardless of whether the input level on the CNVSS pin is “H” or “L”. Note, however, that the PM01 to PM00 bits cannot be rewritten to “01b” (memory expansion mode) or “11b” (microprocessor mode) at the same time the PM07 to PM02 bits are rewritten. Note also that these bits cannot be rewritten to enter microprocessor mode in the internal ROM, nor can they be rewritten to exit microprocessor mode in areas overlapping the internal ROM. If the microcomputer is reset in hard ware by applying VCC1 to the CNVSS pin (hardware reset 1 or brown-out detection reset (hardware reset 2)), the internal ROM cannot be accessed regardless of PM01 to PM00 bits. Figures 7.1 and 7.2 show the PM0 Register and PM1 Register. Figure 7.3 show the Memory Map in Single Chip Mode. Table 7.2 Processor Mode After Hardware Reset CNVSS Pin Input Level Processor Modes VSS Single-Chip Mode VCC1 (1, 2) Microprocessor Mode Table 7.3 PM01 to PM00 Bits Set Values and Processor Modes PM01 to PM00 Bits Processor Modes 00b Single-Chip Mode 01b Memory Expansion Mode 10b Do not set 11b Microprocessor Mode

M16C/62P Group (M16C/62P , M16C/62PT) 7. Processor Mode Rev.2.41 Jan 10, 2006 Page 56 of 390 REJ09B0185-0241 Figure 7.1 PM0 Register Processor Mode Register 0 (1) Symbol Address After Reset PM0 0004h 00000000b (CNVSS pin = L) 00000011b (CNVSS pin = H) Bit Symbol Bit Name Function RW 0 : RD ___ , BHE , WR ____ 1 : RD ___ , WRH , WRL b5 b4 0 0 : Multiplexed bus is unused (Separate bus in the entire CS ___ space) 0 1 : Allocated to CS2 space 1 0 : Allocated to CS1 space 1 1 : Allocated to the entire CS ___ space (3) NOTES : RW PM06 PM00 RW PM02 R/W Mode Select Bit (2) RW PM01 RW RW b7 b6 b5 b4 RW RW b3 b2 b1 b0 b1 b0 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Do not set 1 1 : Microprocessor mode Processor Mode Bit (4) Multiplexed Bus Space Select Bit (2) 0 : Address output 1 : Port function (Address is not output) Port P4_0 to P4_3 Function Select Bit (2) Write to this register after setting the PRC1 bit in the PRCR register to “1” (w rite enable). RWSetting this bit to “1” resets the microcomputer. When read, its content is “0”. Softw are Reset BitPM03 0 : BCLK is output 1 : BCLK is not output (Pin is left high-impedance) BCLK Output Disable Bit (2) PM07 PM04 PM05 To set the PM01 to PM00 bits are “01b” and the PM05 to PM04 bits are “11b” (multiplexed bus assigned to the entire Effective w hen the PM01 to PM00 bits are set to “01b” (memory expansion mode) or “11b” (microprocessor mode). The PM01 to PM00 bits do not change at softw are reset, w atchdog timer reset and oscillation stop detection reset. CS ___ space), apply an “H” signal to the BYTE pin (external data bus is 8 bits w ide). While the CNVSS pin is held “H” (= VCC1), do not rew rite the PM05 to PM04 bits to “11b” after reset. If the PM05 to PM04 bits are set to “11b” during memory expansion mode, P3_1 to P3_7 and P4_0 to P4_3 become I/O ports, in w hich case the accessible area for each CS ___ is 256 bytes.

M16C/62P Group (M16C/62P , M16C/62PT) 7. Processor Mode Rev.2.41 Jan 10, 2006 Page 57 of 390 REJ09B0185-0241 Figure 7.2 PM1 Register Processor Mode Register 1 (1) Symbol Address After Reset PM1 0005h 0X001000b Bit Symbol Bit Name Function RW NOTES : Address 04000h to 07FFFh are reserved Address 80000h to CFFFFh are reserved (Memory expansion mode) The entire area is usable Access Area Ex ter nal RA M ROMInternal Up to Addresses 00400h to 03FFFh (15 Kbytes) Up to Addresses D0000h to FFFFFh (192 Kbytes) Address 04000h to 07FFFh are usable Address 80000h to CFFFFh are usable PM13=0 PM13=1 The entire area is usable PM12 bit is set to “1” by w riting a “1” in a program (w riting a “0” has no effect). When PM17 bit is set to “1” (w ith w ait state), one w ait state is inserted w hen accessing the internal RAM, or internal ROM. When PM17 bit is set to “1” and accesses an external area, set the CSiW bit in the CSR register (i=0 to 3) to “0” (w ith w ait state). The PM13 bit is automatically set to “1” w hen the FMR01 bit in the FMR0 register is “1” (CPU rew rite mode). The access area is changed by the PM13 bit as listed in the table below . RW PM11 RW PM13 RW Memory Area Expansion Bit (3) Port P3_7 to P3_4 Function Select Bit (3) Internal Reserved Area Expansion Bit (6) 0 : Address output 1 : Port function (NOTE 7) 0 : No w ait state 1 : With w ait state (1 w ait) Res erv ed Bit Wait Bit (5) PM15 b5 b4 0 0 : 1-Mbyte mode (Do not expand) 0 1 : Do not set 1 0 : Do not set 1 1 : 4-Mbyte mode b3 b2 b1 b0b7 b6 b5 b4 PM10 RW PM12 Watchdog Timer Function Select Bit 0 : Watchdog timer interrupt 1 : Watchdog timer reset (4) RW CS2 A rea Sw itc h Bit (Data Block Enable Bit) (2) 0 : 08000h to 26FFFh (Block A disable) 1 : 10000h to 26FFFh (Block A enable) Set the PM10 bit to “0” for Mask ROM version. For flash memory version, the PM10 bit controls w hether Block A is enabled or disabled. When the PM10 bit is set to “1”, 0F000h to 0FFFFh can be used as internal ROM area. In addition, the PM10 bit is automatically set to “1” w hile the FMR01 bit in the FMR0 register is set to “1” (CPU rew rite mode). Effective w hen the PM01 to PM00 bits are set to “01b” (memory expansion mode) or “11b” (microprocessor mode). Write to this register after setting the PRC1 bit in the PRCR register to “1” (w rite enable). PM14 RW PM17 RW (b6) RWSet to “0”.

M16C/62P Group (M16C/62P , M16C/62PT) 7. Processor Mode Rev.2.41 Jan 10, 2006 Page 58 of 390 REJ09B0185-0241 Figure 7.3 Memory Map in Single Chip Mode Single-Chip Mode SFR Internal RAM Can not use Internal ROM 00000h 00400h XXXXXh YYYYYh FFFFFh NOTES : 1. For the mask ROM version, set the PM10 bit to “0” (08000h to 26FFFh for CS2 area). 2. If PM13 bit is set to “0”, 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used. PM13=0 PM13=1 Capacity Address YYYYYh

128 Kbytes E0000h

256 Kbytes D0000h (2)

12 Kbytes 033FFh

20 Kbytes 03FFFh(2)

10 Kbytes 02BFFh

24 Kbytes 03FFFh(2)

384 Kbytes D0000h (2)

512 Kbytes D0000h (2)

5 Kbytes 017FFh

31 Kbytes 03FFFh(2)

48 Kbytes F4000h

64 Kbytes F0000h

96 Kbytes E8000h

320 Kbytes D0000h (2)

256 Kbytes C0000h

20 Kbytes 053FFh

24 Kbytes 063FFh

384 Kbytes A0000h

31 Kbytes 07FFFh

320 Kbytes B0000h

16 Kbytes 043FFh

16 Kbytes 03FFFh(2)

Capacity Capacity Address YYYYYhAddress XXXXXh

M16C/62P Group (M16C/62P , M16C/62PT) 8. Bus Rev.2.41 Jan 10, 2006 Page 59 of 390 REJ09B0185-0241 8. Bus During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform data input/ output to and from external devices. These bus co ntrol pins include A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/ WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK.

8.1 Bus Mode

The bus mode, either multiplex ed or separate, can be selected using the PM05 to PM04 bits in the PM0 register. Table 8.1 shows the Difference Between a Separate Bus and Multiplexed Bus.

8.1.1 Separate Bus

In this bus mode, data and address are separate.

8.1.2 Multiplexed Bus

In this bus mode, data and address are multiplexed.

8.1.2.1 When the input level on BYTE pin is high (8-bit data bus)

D0 to D7 and A0 to A7 are multiplexed.

8.1.2.2 When the input level on BYTE pin is low (16-bit data bus)

D0 to D7 and A1 to A8 are multiplexed. D8 to D15 are not multiplexed. Do not use D8 to D15. External devices connecting to a multiplexed bus ar e allocated to only the even a ddresses of the microcomputer. Odd addresses cannot be accessed. NOTES: 1. See Table 8.6 Pin Functions for Each Processor Mode for bus control signals other than the above. Setting Processor Modes. 2. It changes with a setup of PM05 to PM04, and area to access. See Table 8.6 Pin Functions for Each Processor Mode for details. Table 8.1 Difference Between a Separate Bus and Multiplexed Bus Pin Name (1) Separate Bus Multiplex Bus BYTE = H BYTE = L P0_0 to P0_7/D0 to D7 D0 to D7 (NOTE 2) (NOTE 2) P1_0 to P1_7/D8 to D15 D8 to D15 I/O Port P1_0 to P1_7 (NOTE 2) P2_0/A0 (/D0/-) A0 A0 D0 A0 P2_1 to P2_7/A1 to A7 (/D1 to D7/D0 to D6) A1 to A7 A1 to A7 D1 to D7 A1 to A7 D0 to D6 P3_0/A8 (/-/D7) A8 A8 A8 D7 The M16C/62P (80-pin version) and M16C/62PT do not use bus control pins. Note

M16C/62P Group (M16C/62P , M16C/62PT) 8. Bus Rev.2.41 Jan 10, 2006 Page 60 of 390 REJ09B0185-0241

8.2 Bus Control

The following describes the signals needed for accessing external devices and the functionality of software wait.

8.2.1 Address Bus

The address bus consists of 20 lines, A0 to A19. The address bus width can be chosen to be 12, 16 or 20 bits by using the PM06 bit in the PM0 register and the PM11 bit in the PM1 register. Table 8.2 shows the PM06 and PM11 Bits Set Value and Address Bus Width. NOTES: 1. No values other than th ose shown above can be set. When processor mode is changed from single-chip mode to memory extension mode, the address bus is indeterminate until any external area is accessed.

8.2.2 Data Bus

When input on the BYTE pin is high (data bus is 8 bits wide), 8 lines D0 to D7 comprise the data bus; when input on the BYTE pin is low(data bus is 16 bits wide), 16 lines D0 to D15 comprise the data bus. Do not change the input level on the BYTE pin while in operation.

8.2.3 Chip Select Signal

The chip select (hereafter referred to as the CSi ) signals are output from the CSi (i = 0 to 3) pins. These pins can be chosen to function as I/O ports or as CS by using the CSi bit in the CSR register. Figure 8.1 shows the CSR Register. During 1-Mbyte mode, the external area can be separated into up to 4 by the CSi signal which is output from the CSi pin. During 4-Mbyte mode, CSi signal or bank number is output from the CSi pin. Refer to 9. Memory Space Expansion Function. Figure 8.2 shows the Example of Address Bus and CSi Signal Output in 1-Mbyte mode. Table 8.2 PM06 and PM11 Bits Set Value and Address Bus Width Set Value (1) Pin Function Address Bus Width PM11=1 P3_4 to P3_7 12 bits PM06=1 P4_0 to P4_3 PM11=0 A12 to A15 16 bits PM06=1 P4_0 to P4_3 PM11=0 A12 to A15 20 bits PM06=0 A16 to A19

M16C/62P Group (M16C/62P , M16C/62PT) 8. Bus Rev.2.41 Jan 10, 2006 Page 61 of 390 REJ09B0185-0241 Figure 8.1 CSR Register Chip Select Control Register Address After Reset 0008h 00000001b Bit Symbol Function RW NOTES : Where the RDY signal is used in the area indicated by CSi ____ (i = 0 to 3) or the multiplex bus is used, set the CSiW bit to (w ith w ait state). If the PM17 bit in the PM1 register is set to “1” (w ith w ait state), set the CSiW bit to “0” (w ith w ait state). When the CSiW bit = 0 (w ith w ait state), the number of w ait states can be selected using the CSEi1W to CSEi0W bits in the CSE register. RWCS3W 0 : With w ait state 1 : Without w ait state (1, 2, 3) CS1 ____ Wait Bit CS2 ____ Wait Bit CS3 ____ Wait Bit CS2W CS1W RW RW CS1 CS2 CS3 CS0W b7 b6 b5 b4 b3 b2 b1 b0 Symbol RW0 : Chip select output disabled (functions as I/O port) 1 : Chip select output enabled CS0 CS0 ____ Output Enable Bit Bit Name CSR RW RW RW RWCS0 ____ Wait Bit CS2 ____ Output Enable Bit CS1 ____ Output Enable Bit CS3 ____ Output Enable Bit

M16C/62P Group (M16C/62P , M16C/62PT) 8. Bus Rev.2.41 Jan 10, 2006 Page 62 of 390 REJ09B0185-0241 Figure 8.2 Example of Address Bus and CSi Signal Output in 1-Mbyte mode Example 1 BCLK Read signal Data bus Address bus CSi Access to the external area indicated by CSi Access to the external area indicated by CSj Address Data CSj Data BCLK Read signal Data bus Address bus CSi Access to the external area indicated by CSi Access to the internal ROM or internal RAM Address Data BCLK Read signal Data bus Address bus CSi Access to the external area indicated by CSi Access to the same external area Address Data Data BCLK Read signal Data bus Address bus CSi Access to the external area indicated by CSi No access Address Data Address Address Shown above is the case where separate bus is selected and the area is accessed for read without wait states. i = 0 to 3, j = 0 to 3 (not including i, however) To access the external area indicated by CSj in the next cycle after accessing the external area indicated by CSi The address bus and the chip select signal both change state between these two cycles. Example 2 To access the internal ROM or internal RAM in the next cycle after accessing the external area indicated by CSi The chip select signal changes state but the address bus does not change state Example 4 Not to access any area (nor instruction prefetch generated) in the next cycle after accessing the external area indicated by CSi Neither the address bus nor the chip select signal changes state between these two cycles Example 3 To access the external area indicated by CSi in the next cycle after accessing the external area indicated by the same CSi The address bus changes state but the chip select signal does not change state NOTES : 1. These examples show the address bus and chip select signal when accessing areas in two successive cycles. The chip select bus cycle may be extended more than two cycles depending on a combination of these examples.

M16C/62P Group (M16C/62P , M16C/62PT) 8. Bus Rev.2.41 Jan 10, 2006 Page 63 of 390 REJ09B0185-0241

8.2.4 Read and Write Signals

When the data bus is 16 bits wide, the read and write signals can be chosen to be a combination of RD , BHE and WR or a combination of RD , WRL and WRH by using the PM02 bit in the PM0 register. When the data bus is 8 bits wide, use a combination of RD, WR and BHE. Table 8.3 shows the Operation of RD, WRL, and WRH Signals. Table 8.4 shows the Operation of RD , WRL, and BHE Signals.

8.2.5 ALE Signal

The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the ALE signal falls. Figure 8.3 ALE Signal, Address Bus, Data Bus Table 8.3 Operation of RD , WRL and WRH Signals Data Bus Width RD WRL WRH Status of External Data Bus 16-bit (BYTE pin input = L) L H H Read data H L H Write 1 byte of data to an even address H H L Write 1 byte of data to an odd address H L L Write data to both even and odd addresses Table 8.4 Operation of RD , WRL and BHE Signals Data Bus Width RD WRL BHE A0 Status of External Data Bus 16-bit (BYTE pin input = L) H L L H Write 1 byte of data to an odd address L H L H Read 1 byte of data from an odd address H L H L Write 1 byte of data to an even address L H H L Read 1 byte of data from an even address H L L L Write data to both even and odd addresses L H L L Read data from both even and odd addresses 8-bit (BYTE pin input = H) H L Not used H or L Write 1 byte of data L H Not used H or L Read 1 byte of data When BYTE Pin Input = H When BYTE Pin Input = L ALE Address Data Address (1) A0/D0 to A7/D7 A8 to A19 ALE Address Data Address A1/D0 to A8/D7 A9 to A19 AddressA0 NOTES : 1. If the entire CS space is assigned a multiplexed bus, these pins function as I/O ports.

M16C/62P Group (M16C/62P , M16C/62PT) 8. Bus Rev.2.41 Jan 10, 2006 Page 64 of 390 REJ09B0185-0241

8.2.6 RDY Signal

This signal is provided fo r accessing external devices which need to be accessed at low speed. If input on the RDY pin is asserted low at the last falling edge of BCLK of the bus cycle, one wait state is inserted in the bus cycle. While in a wait state, the following signals retain the state in which they were when the RDY signal was acknowledged. A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE, ALE, HLDA Then, when the input on the RDY pin is detected high at the falling edge of BCLK, the remaining bus cycle is executed. Figure 8.4 shows Example in which the Wait State was Inserted into Read Cycle by RDY Signal. To use the RDY signal, set the corresponding bit (CS3W to CS0W bits) in the CSR register to “0” (with wait state). When not using the RDY signal, the RDY pin must be pulled-up. Figure 8.4 Example in which Wait State was Inserted into Read Cycle by RDY Signal BCLK RD CSi (i=0 to 3) RDY tsu(RDY - BCLK) BCLK RD CSi (i=0 to 3) RDY tsu(RDY - BCLK) In an instance of separate bus In an instance of multiplexed bus : Wait using RDY signal : Wait using software Shown above is the case where CSEi1W to CSEi0W (i = 0 to 3) bits in the CSE register are “ 00b” (one wait state). Accept timing of RDY signal Accept timing of RDY signal

M16C/62P Group (M16C/62P , M16C/62PT) 8. Bus Rev.2.41 Jan 10, 2006 Page 65 of 390 REJ09B0185-0241

8.2.7 HOLD Signal

This signal is used to transfer control of the bus from the CPU or DMAC to an external circuit. When the input on HOLD pin is pulled low, the microcomputer is placed in a hold state after the bus access then in process finishes. The microcomputer remains in the hold state while the HOLD pin is held low, during which time the HLDA pin outputs a low-level signal. Table 8.5 shows the Microcomputer Status in Hold State. Bus-using priorities are given to HOLD , DMAC, and CPU in order of decreas ing precedence. However, if the CPU is accessing an odd address in wo rd units, the DMAC cannot gain cont rol of the bus du ring two separate accesses. Figure 8.5 Bus-Using Priorities NOTES: 1. P11 to P14 are included in the 128-pin version. 2. When I/O port function is selected. 3. The watchdog timer dose not stop when the PM22 bit in the PM2 register is set to “1” (the count source for the watchdog timer is the on-chip oscillator clock). 8.2.8 8.2.8 BCLK Output If the PM07 bit in the PM0 register is set to “0” (output enable), a clock with the same frequency as that of the CPU clock is output as BCLK from the BCLK pin. Refer to 10.2 CPU Clock and Peripheral Function Clock. Table 8.5 Microcomputer Status in Hold State Item Status BCLK Output A0 to A19, D0 to D15, CS0 to CS3, RD, WRL,WRH, WR, BHE High-impedance I/O ports P0, P1, P3, P4 (2) High-impedance P6 to P14 (1) Maintains status when HOLD signal is received HLDA Output “L” Internal Peripheral Circuits O N (but watchdog timer stops)(3) ALE Signal Undefined HOLD > DMAC > CPU

M16C/62P Group (M16C/62P , M16C/62PT) 8. Bus Rev.2.41 Jan 10, 2006 Page 66 of 390 REJ09B0185-0241 I/O ports : Function as I/O ports or peripheral function I/O pins. NOTES: 1. To set the PM01 to PM00 bits are set to “01b” and the PM05 to PM04 bits are set to “11b” (multiplexed bus assigned to the entire CS space), apply “H” to the BYTE pin (external data bus 8 bits wide). While the CNVSS pin is held “H” (= VCC1), do not rewrite the PM05 to PM04 bits to “11b” after reset. If the PM05 to PM04 bits are set to “11b” during memory expansion mode, P3_1 to P3_7 and P4_0 to P4_3 become I/O ports, in which case the accessible area for each CS is 256 bytes. 2. In separate bus mode, these pins serve as the address bus. 3. If the data bus is 8 bits wide, make sure the PM02 bit is set to “0” (RD , BHE, WR). 4. When accessing the area that uses a multiplexed bus, these pins output an indeterminate value during a write. Table 8.6 Pin Functions for Each Processor Mode Processor Mode Memory Expansion Mode or Microprocessor Mode Memory Expansion Mode PM05 to PM04 bits 00b(separate bus) bits 01b(CS2 is for multiplexed bus and others are for separate bus) 10b(CS1 is for multiplexed bus and others are for separate bus) 11b (multiplexed bus for the entire space) (1) Data Bus Width BYTE Pin 8 bits “H” 16 bits “L” 8 bits “H” 16 bits “L” 8 bits “H” P0_0 to P0_7 D0 to D7 D0 to D7 D0 to D7 (4) D0 to D7 (4) I/O ports P1_0 to P1_7 I/O ports D8 to D15 I/O ports D8 to D15 (4) I/O ports P2_0 A0 A0 A0/D0 (2) A0 A0/D0 P2_1 to P2_7 A1 to A7 A1 to A7 A1 to A7 /D1 to D7 (2) A1 to A7 /D0 to D6 (2) A1 to A7 /D1 to D7 P3_0 A8 A8 A8 A8/D7 (2) A8 P3_1 to P3_3 A9 to A11 I/O ports P3_4 to P3_7 PM11=0 A12 to A15 I/O ports PM11=1 I/O ports P4_0 to P4_3 PM06=0 A16 to A19 I/O ports PM06=1 I/O ports P4_4 CS0=0 I/O ports CS0=1 CS0 P4_5 CS1=0 I/O ports CS1=1 CS1 P4_6 CS2=0 I/O ports CS2=1 CS2 P4_7 CS3=0 I/O ports CS3=1 CS3 P5_0 PM02=0 WR PM02=1 − (3) WRL − (3) WRL − (3) P5_1 PM02=0 BHE PM02=1 − (3) WRH − (3) WRH − (3) P5_2 RD P5_3 BCLK P5_4 HLDA P5_5 HOLD P5_6 ALE P5_7 RDY

M16C/62P Group (M16C/62P , M16C/62PT) 8. Bus Rev.2.41 Jan 10, 2006 Page 67 of 390 REJ09B0185-0241

8.2.9 External Bus Status When Internal Area Accessed

Table 8.7 shows the External Bus Status When Internal Area Accessed. Table 8.7 External Bus Status When Internal Area Accessed Item SFR Accessed Intern al ROM, RAM Accessed A0 to A19 Address output Maintain status before accessed address of external area or SFR D0 to D15 When Read High-impedance High-impedance When Write Output data Undefined RD, WR, WRL, WRH RD, WR, WRL, WRH output Output “H” BHE BHE output Maintain status before accessed status of external area or SFR CS0 to CS3 Output “H” Output “H” ALE Output “L” Output “L”

M16C/62P Group (M16C/62P , M16C/62PT) 8. Bus Rev.2.41 Jan 10, 2006 Page 68 of 390 REJ09B0185-0241

8.2.10 Software Wait

Software wait states can be inserted by using the PM17 bit in the PM1 register, the CS0W to CS3W bits in the CSR register, and the CSE register. The SFR area is un affected by these control bits. This area is always accessed in 2 BCLK or 3 BCLK cycles as determined by the PM20 bit in the PM2 register. See Table 8.8 Bit and Bus Cycle Related to Software Wait for details. To use the RDY signal, set the corresponding CS3W to CS0W bit to “0” (with wait state). Figure 8.6 shows the Typical Bus Timings Using Software Wait. Figure 8.6 CSE Register Chip Select Expansion Control Register Address After Reset 001Bh 00h Bit Symbol Function RW NOTES : b3 b2 0 0 : 1 w ait 0 1 : 2 w aits 1 0 : 3 w aits 1 1 : Do not set b7 b6 0 0 : 1 w ait 0 1 : 2 w aits 1 0 : 3 w aits 1 1 : Do not set CS2 Wait Expansion Bit (1) CS1 Wait Expansion Bit (1) RW RW RW RW RW RW Bit Name CSE RWCSE00W CS0 Wait Expansion Bit (1) b1 b0 0 0 : 1 w ait 0 1 : 2 w aits 1 0 : 3 w aits 1 1 : Do not set RW Symbol b3 b2 b1 b0b7 b6 b5 b4 CSE01W CSE10W CSE11W CSE20W Set the CSiW bit (i = 0 to 3) in the CSR register to “0” (w ith w ait state) before w riting to the CSEi1W to CSEi0W bits. If the CSiW bit needs to be set to “1” (w ithout w ait state), set the CSEi1W to CSEi0W bits to “00b” before setting it. CSE31W CS3 Wait Expansion Bit (1) CSE30W CSE21W b5 b4 0 0 : 1 w ait 0 1 : 2 w aits 1 0 : 3 w aits 1 1 : Do not set

M16C/62P Group (M16C/62P , M16C/62PT) 8. Bus Rev.2.41 Jan 10, 2006 Page 69 of 390 REJ09B0185-0241 NOTES: 1. To use the RDY signal, set this bit to “0”. 2. To access in multiplexed bus mode, set the corresponding bit of CS0W to CS3W to “0” (with wait state). 3. When the selected CPU clock sour ce is the PLL clock, the number of wait cycles can be altered by the PM20 bit in the PM2 register. When using a 16 MHz or higher PLL clock, be sure to set the PM20 bit to “0” (2 wait cycles). 4. After reset, the PM17 bit is set to “0” (without wait state), all of the CS0W to CS3W bits are set to “0” (with wait state), and the CSE register is set to “00h” (one wait state for CS0 to CS3). Therefore, the internal RAM and internal ROM are accessed with no wait states, and all external areas are accessed with one wait state. 5. When PM17 bit is set to “1” and accesses an external area, set the CSiW (i=0 to 3) bits to “0” (with wait state). Table 8.8 Bit and Bus Cycle Related to Software Wait Area Bus Mode PM2 Register PM20 Bit PM1 Register PM17 Bit (5) CSR Register CS3W Bit (1) CS2W Bit (1) CS1W Bit (1) CS0W Bit (1) CSE Register CSE31W to CSE30W Bit CSE21W to CSE20W Bit CSE11W to CSE10W Bit CSE01W to CSE00W Bit Software Wait Bus Cycle SFR − 1 −− − − 2 BCLK cycles (3) − 0 −− − − 3 BCLK cycles (3) Internal RAM, ROM −− 0 −− No wait 1 BCLK cycle (4) −− 1 −− 1 wait 2 BCLK cycles External Area Separate Bus − 0 1 00b No wait 1 BCLK cycle (read)

2 BCLK cycles

(write) −− 0 00b 1 wait 2 BCLK cycle (4) −− 0 01b 2 waits 3 BCLK cycles −− 0 10b 3 waits 4 BCLK cycle − 1 0 00b 1 wait 2 BCLK cycle Multiplexed Bus (2) −− 0 00b 1 wait 3 BCLK cycles −− 0 01b 2 waits 3 BCLK cycles −− 0 10b 3 waits 4 BCLK cycles − 1 0 00b 1 wait 3 BCLK cycles

M16C/62P Group (M16C/62P , M16C/62PT) 8. Bus Rev.2.41 Jan 10, 2006 Page 70 of 390 REJ09B0185-0241 Figure 8.7 Typical Bus Timings Using Software Wait (1) BCLK Read signal Write signal Data bus Address bus Address Address Output Input Address Address Bus cycle (1) Bus cycle (1) (1) Separate Bus, No Wait Setting (2) Separate Bus, 1-Wait Setting Output Input NOTES : 1. These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in succession. Bus cycle (1) Bus cycle (1) (3) Separate Bus, 2-Wait Setting Output Address Address Bus cycle (1) Bus cycle (1) Input BCLK BCLK CS Read signal Write signal Data bus Address bus CS CS Read signal Write signal Data bus Address bus

M16C/62P Group (M16C/62P , M16C/62PT) 8. Bus Rev.2.41 Jan 10, 2006 Page 71 of 390 REJ09B0185-0241 Figure 8.8 Typical Bus Timings Using Software Wait (2) Address Address Data output Address Address Input Bus cycle (1) Bus cycle (1) (1) Separate Bus, 3-Wait Setting Read signal Write signal Address bus/ Data bus CS Address bus ALE (3) Multiplexed Bus, 3-Wait Setting Output NOTES : 1. These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in succession. Bus cycle (1) Bus cycle (1) Input Address Address Address bus/ Data bus Address Address Data output Address Address Input ALE Bus cycle (1) (2) Multiplexed Bus, 1- or 2-Wait Setting Bus cycle (1) BCLK CS BCLK CS BCLK Write signal Read signal Data bus Address bus Write signal Read signal Address bus

M16C/62P Group (M16C/62P , M16C/62PT) 9. Memory Space Expansion Function Rev.2.41 Jan 10, 2006 Page 72 of 390 REJ09B0185-0241 9. Memory Space Expansion Function The following describes a memory space extension function. During memory expansion or microprocessor mode, the memory space ex pansion function allows the access space to be expanded using the appropriate register bits. Table 9.1 shows The Way of Setting Memory Space Expansion Function, Memory Space. 9.1 1-Mbyte Mode In this mode, the memory space is 1 Mbytes. In 1-Mbyte mode, the external area to be accessed is specified using the CSi (i = 0 to 3) signals (hereafter referred to as the CSi area). Figures 9.2 to 9.3 show the Memory Mapping and CS Area in 1-Mbyte mode. 9.2 4-Mbyte Mode In this mode, the memory space is 4 Mbytes. Figure 9.1 sh ows the DBR Register. The BS R2 to BSR0 bits in the DBR register select a bank number which is to be accessed to read or write data. Se tting the OFS bit to “1” (with offset) allows the accessed address to be offset by 40000h. In 4-Mbyte mode, the CSi (i=0 to 3) pin functions differently for each area to be accessed. 9.2.1 9.2.1 Addresses 04000h to 3FFFFh, C0000h to FFFFFh

• The CSi signal is output from the CSi pin (same operation as 1-Mbyte mode. However, the last address of CS1 area is 3FFFFh). 9.2.2 9.2.2 Addresses 40000h to BFFFFh
• The CS0 pin outputs “L”
• The CS1 to CS3 pins output the value of setting as the BSR2 to BSR0 bits (bank number) Figures 9.4 to 9.5 show the Memory Mapping and CS Area in 4-Mbyte mode. Note that banks 0 to 6 are data-only areas. Locate the program in bank 7 or the CSi area. Table 9.1 The Way of Setting Memory Space Expansion Function, Memory Space Memory Space Expansion Function How to Set (PM15 to PM14) Memory Space 1-Mbyte Mode 00b 1 Mbyte (no expansion) 4-Mbyte Mode 11b 4 Mbytes The M16C/62P (80-pin version) and M16C/62PT do not use the memory space expansion function. Note

M16C/62P Group (M16C/62P , M16C/62PT) 9. Memory Space Expansion Function Rev.2.41 Jan 10, 2006 Page 73 of 390 REJ09B0185-0241 Figure 9.1 DBR Register Data Bank Register (1) Symbol Address After Reset DBR 000Bh 00h Bit Symbol Bit Name RW NOTES : b7 b6 b5 b4 b3 b2 b1 b0 (b1-b0) —Nothing is assigned. When w rite, set to “0”. When read, their contents are “0”. Function OFS Of fset Bit RW0 : Not offset 1 : Offset BSR0 RWb5 b4 b3 0 0 1 : Bank 1 0 1 1 : Bank 3 1 0 1 : Bank 5 1 1 1 : Bank 7 b5 b4 b3 0 0 0 : Bank 0 0 1 0 : Bank 2 1 0 0 : Bank 4 1 1 0 : Bank 6 Bank Selection Bits BSR1 RW BSR2 RW (b7-b6) Nothing is assigned. When w rite, set to “0”. When read, their contents are “0”. — Effective w hen the PM01 to PM00 bits in the PM0 register are set to “01b” (memory expansion mode) or “11b” (m icroprocessor m ode).

M16C/62P Group (M16C/62P , M16C/62PT) 9. Memory Space Expansion Function Rev.2.41 Jan 10, 2006 Page 74 of 390 REJ09B0185-0241 Figure 9.2 Memory Mapping and CS Area in 1-Mbyte mode (PM13=0) Microprocessor mode 00000h 00400h XXXXXh YYYYYh FFFFFh D0000h 08000h Memory expansion mode SFR Internal RAM Internal ROM Reserved area Reserved area CS3 (16 Kbytes) CS2 (PM10=0: 124 Kbytes) CS1 (32 Kbytes) CS0 (Microprocessor mode:832 Kbytes) 28000h 30000h 04000h Reserved area27000h Capacity Address YYYYYh

256 Kbytes D0000h(1)

20 Kbytes 03FFFh(1)

24 Kbytes 03FFFh(1)

384 Kbytes D0000h(1)

512 Kbytes D0000h(1)

PM13=0 Reserved, external area(2) External area 10000h SFR Internal RAM Reserved area Reserved area Reserved, external area(2) External area CS2 (PM10=1: 92 Kbytes) CS0 (Memory expansion mode:640 Kbytes ) Internal RAM Internal ROM CS0 Memory expansion mode 30000h to CFFFFh External Area CS1 Microprocessor mode 30000h to FFFFFh 28000h to 2FFFFh CS2 When PM10=0 08000h to 26FFFh When PM10=1 10000h to 26FFFh CS3 04000h to 07FFFh

31 Kbytes 03FFFh(1)

320 Kbytes D0000h(1)

16 Kbytes 03FFFh(1)

NOTES : 1. If PM13 bit in the PM1 register is set to “0”, 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used. 2. For flash memory version, when the PM10 bit in the PM1 register is set to “1”, 0F000h to 0FFFFh can be used as internal ROM area.

M16C/62P Group (M16C/62P , M16C/62PT) 9. Memory Space Expansion Function Rev.2.41 Jan 10, 2006 Page 75 of 390 REJ09B0185-0241 Figure 9.3 Memory Mapping and CS Area in 1-Mbyte mode (PM13=1) Microprocessor mode 00000h 00400h XXXXXh YYYYYh FFFFFh 80000h 08000h Memory expansion mode SFR Internal RAM Internal ROM Reserved area Reserved, external area(1) CS2 (PM10=0: 124 Kbytes) CS1 (32 Kbytes) CS0 (Microprocessor mode : 832 Kbytes) 28000h 30000h Reserved area27000h Capacity Address YYYYYh PM13=1 External area 10000h SFR Internal RAM Reserved area Reserved area External area CS2 (PM10=1: 92 Kbytes) CS0 (Memory expansion mode : 320 Kbytes ) Internal RAM Internal ROM CS0 Memory expansion mode 30000h to 7FFFFh External area CS1 Microprocessor mode 30000h to FFFFFh 28000h to 2FFFFh CS2 When PM10=0 08000h to 26FFFh When PM10=1 10000h to 26FFFh CS3 No area4 Kbytes 013FFh Reserved, external area(1) NOTES : 1. For flash memory version, when the PM10 bit in the PM1 register is set to “1”, 0F000h to 0FFFFh can be used as internal ROM area.

M16C/62P Group (M16C/62P , M16C/62PT) 9. Memory Space Expansion Function Rev.2.41 Jan 10, 2006 Page 76 of 390 REJ09B0185-0241 Figure 9.4 Memory Mapping and CS Area in 4-Mbyte mode (PM13=0) Microprocessor mode 00000h 00400h XXXXXh YYYYYh FFFFFh D0000h 08000h Memory expansion mode SFR Internal RAM Internal ROM Reserved area Reserved area CS3 (16 Kbytes) CS2 (PM10=0 : 124 Kbytes) CS1 (96 Kbytes) CS0 (Microprocessor mode : 256 Kbytes) 28000h 40000h 04000h Reserved area27000h PM13=0 Reserved, external area(3) External area 10000h SFR Internal RAM Reserved area Reserved area External area CS2 (PM10=1 : 92 Kbytes) CS0 (Memory expansion mode : 64 Kbytes ) CS0 Memory expansion mode C0000h to CFFFFh External area CS1 Microprocessor mode C0000h to FFFFFh 28000h to 3FFFFh CS2 When PM10=0 08000h to 26FFFh When PM10=1 10000h to 26FFFh CS3 04000h to 07FFFh C0000h Other than the CS area (512 Kbytes X 8 banks) 40000h to BFFFFh Other than the CS area(1) NOTES : 1. The CS0 pin outputs a low signal, and the CS1 to CS3 pins output a bank number. 2. If PM13 bit in the PM1 register is set to “0”, 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used. 3. For flash memory version, when the PM10 bit in the PM1 register is set to “1”, 0F000h to 0FFFFh can be used as internal ROM area. Capacity Address YYYYYh

31 Kbytes 03FFFh (2)

Reserved, external area(3)

M16C/62P Group (M16C/62P , M16C/62PT) 9. Memory Space Expansion Function Rev.2.41 Jan 10, 2006 Page 77 of 390 REJ09B0185-0241 Figure 9.5 Memory Mapping and CS Area in 4-Mbyte mode (PM13=1) Microprocessor mode 00000h 00400h XXXXXh YYYYYh FFFFFh C0000h 08000h Memory expansion mode SFR Internal RAM Internal ROM Reserved area Reserved area CS2 (PM10=0: 124 Kbytes) CS1 (96 Kbytes) CS0 (Microprocessor mode : 256 Kbytes) 28000h 40000h Reserved area27000h PM13=1 External area 10000h SFR Internal RAM Reserved area Reserved area External area CS2 (PM10=1: 92 Kbytes) Other than the CS area(Microprocessor mode : 512 Kbytes X 8 banks) CS0 External area CS1 Microprocessor mode C0000h to FFFFFh 28000h to 3FFFFh CS2 When PM10=0 08000h to 26FFFh When PM10=1 10000h to 26FFFh CS3 No area 80000h Other than the CS area (Memory expansion mode:256 Kbytes X 8 banks)* *Two 256 Kbytes X 8 banks can be used by changing the offset. Other than the CS area (1) Memory expansion mode 40000h to 7FFFFh Microprocessor mode 40000h to BFFFFh NOTES : 1. The CS0 pin outputs a low signal, and the CS1 to CS3 pins output a bank number. 2. For flash memory version, when the PM10 bit in the PM1 register is set to “1”, 0F000h to 0FFFFh can be used as internal ROM area. Capacity Address YYYYYh Reserved, external area(2) Reserved, external area(2)

M16C/62P Group (M16C/62P , M16C/62PT) 9. Memory Space Expansion Function Rev.2.41 Jan 10, 2006 Page 79 of 390 REJ09B0185-0241 Figure 9.7 Relationship Between Addresses on 4-Mbyte ROM and Those on Microcomputer (1) 000000h 080000h 100000h 180000h 200000h 280000h 380000h 3FFFFFh 40000h BFFFFh 3C0000h 340000h 2C0000h 240000h 1C0000h 140000h 0C0000h 040000h bank 0 (512 Kbytes) bank 1 (512 Kbytes) bank 1 (512 Kbytes) bank 2 (512 Kbytes) bank 2 (512 Kbytes) bank 3 (512 Kbytes) bank 3 (512 Kbytes) bank 4 (512 Kbytes) bank 4 (512 Kbytes) bank 5 (512 Kbytes) bank 5 (512 Kbytes) bank 6 (512 Kbytes) bank 6 (512 Kbytes) bank 7 (512 Kbytes) Data Program or data OFS bit in DBR register = 0 OFS bit in DBR register = 1 300000h bank 0 (512 Kbytes) 40000h 40000h 40000h 40000h 40000h 40000h 40000h BFFFFh BFFFFh BFFFFh BFFFFh BFFFFh BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh Program or data BFFFFh A18 CS Output Address OutputOFS Access Area Output from the Microcomputer Pins CS3 CS2 CS1 A19 A17 A16 A15 to A0 Bank Number 7 0 D0000h Internal ROM access 40000h 0 0000h 000000h000100 Internal ROM accessDFFFFh A20 A19 A18 N.C. A17 A16 A15 to A0 Address Input for 4-Mbyte ROM Address input for 4-Mbyte ROM A21 Internal ROM accessD0000h Internal ROM accessDFFFFh 040000h000100040000h 0000h 080000h001010040000h 0000h 0C0000h001100040000h 0000h 100000h010010040000h 0000h 140000h010100040000h 0000h 180000h011010040000h 0000h 1C0000h011100040000h 0000h 200000h100010040000h 0000h 240000h100100040000h 0000h 280000h101010040000h 0000h 2C0000h101100040000h 0000h 300000h110010040000h 0000h 340000h110100040000h 0000h 40000h 380000h1 1 1 0 1 0 0 0000h 80000h 3C0000h1 1 1 1 0 0 0 0000h C0000h 3C0000h1 1 1 1 1 0 0 0000h BFFFFh FFFFh0001011 07FFFFh 0010111BFFFFh FFFFh 0BFFFFh 0011011BFFFFh FFFFh 0FFFFFh 0100111BFFFFh FFFFh 13FFFFh 0101011BFFFFh FFFFh 17FFFFh 0110111BFFFFh FFFFh 1BFFFFh 0111011BFFFFh FFFFh 1FFFFFh 1000111BFFFFh FFFFh 23FFFFh 1001011BFFFFh FFFFh 27FFFFh 1010111BFFFFh FFFFh 2BFFFFh 1011011BFFFFh FFFFh 2FFFFFh 1100111BFFFFh FFFFh 33FFFFh 1101011BFFFFh FFFFh 37FFFFh 1110111BFFFFh FFFFh 3BFFFFh 11101117FFFFh FFFFh 3BFFFFh 1111011BFFFFh FFFFh 3FFFFFh 1111100CFFFFh FFFFh 3CFFFFh N.C.: No connected ROM address Microcomputer address Memory expansion mode where PM13 =0

M16C/62P Group (M16C/62P , M16C/62PT) 9. Memory Space Expansion Function Rev.2.41 Jan 10, 2006 Page 80 of 390 REJ09B0185-0241 Figure 9.8 Relationship Between Addresses on 4-Mbyte ROM and Those on Microcomputer (2) 000000h 080000h 100000h 180000h 200000h 280000h 380000h 3FFFFFh 3C0000h 340000h 2C0000h 240000h 1C0000h 140000h 0C0000h 040000h Data OFS bit in DBR register = 0 OFS bit in DBR register = 1 300000h Program or data A18 CS Output Address OutputOFS Access Area Output from the Microcomputer Pins CS3 CS2 CS1 A19 A17 A16 A15 to A0 Bank Number 7 0 Internal ROM access 40000h 0 0000h 000000h0001 00 Internal ROM access 040000h00010 0040000h 0000h 080000h00101 0040000h 0000h 0C0000h00110 0040000h 0000h 100000h01001 0040000h 0000h 140000h01010 0040000h 0000h 180000h01101 0040000h 0000h 1C0000h01110 0040000h 0000h 200000h10001 0040000h 0000h 240000h10010 0040000h 0000h 280000h10101 0040000h 0000h 2C0000h10110 0040000h 0000h 300000h11001 0040000h 0000h 340000h11010 0040000h 0000h 40000h 380000h1 1 1 0 1 0 0 0000h 80000h Internal ROM access 3C0000h1 1 1 1 0 0 0 0000h 7FFFFh FFFFh00001 11 03FFFFh 00010 117FFFFh FFFFh 07FFFFh 00101 117FFFFh FFFFh 0BFFFFh 00110 117FFFFh FFFFh 0FFFFFh 01001 117FFFFh FFFFh 13FFFFh 01010 117FFFFh FFFFh 17FFFFh 01101 117FFFFh FFFFh 1BFFFFh 01110 117FFFFh FFFFh 1FFFFFh 10001 117FFFFh FFFFh 23FFFFh 10010 117FFFFh FFFFh 27FFFFh 10101 117FFFFh FFFFh 2BFFFFh 10110 117FFFFh FFFFh 2FFFFFh 11001 117FFFFh FFFFh 33FFFFh 11010 117FFFFh FFFFh 37FFFFh 11101 117FFFFh FFFFh 3BFFFFh FFFFFh Internal ROM access 1 1 1 1 0 1 1 FFFFh 3FFFFFh A20 A19 A18 N.C. A17 A16 A15 to A0 Address Input for 4-Mbyte ROM Address input for 4-Mbyte ROM A21 7FFFFh bank 0 (256 Kbytes) bank 1 (256 Kbytes) bank 2 (256 Kbytes) bank 3 (256 Kbytes) bank 4 (256 Kbytes) bank 5 (256 Kbytes) bank 6 (256 Kbytes) bank 7 (256 Kbytes) 40000h 7FFFFh 40000h 7FFFFh 40000h 7FFFFh 40000h 7FFFFh 40000h 7FFFFh 40000h 7FFFFh 40000h 7FFFFh 40000h 7FFFFh bank 0 (256 Kbytes) bank 1 (256 Kbytes) bank 2 (256 Kbytes) bank 3 (256 Kbytes) bank 4 (256 Kbytes) bank 5 (256 Kbytes) bank 6 (256 Kbytes) bank 7 (256 Kbytes) 40000h 7FFFFh 40000h 7FFFFh 40000h 7FFFFh 40000h 7FFFFh 40000h 7FFFFh 40000h 7FFFFh 40000h 7FFFFh 40000h 7 1 40000h 80000h 7FFFFh FFFFFh N.C.: No connected ROM address Microcomputer address Memory expansion mode where PM13 =1 Program only

M16C/62P Group (M16C/62P , M16C/62PT) 9. Memory Space Expansion Function Rev.2.41 Jan 10, 2006 Page 81 of 390 REJ09B0185-0241 Figure 9.9 Relationship Between Addresses on 4-Mbyte ROM and Those on Microcomputer (3) 000000h 080000h 100000h 180000h 200000h 280000h 380000h 3FFFFFh 40000h BFFFFh 3C0000h 340000h 2C0000h 240000h 1C0000h 140000h 0C0000h 040000h bank 0 (512 Kbytes) bank 1 (512 Kbytes) bank 1 (512 Kbytes) bank 2 (512 Kbytes) bank 2 (512 Kbytes) bank 3 (512 Kbytes) bank 3 (512 Kbytes) bank 4 (512 Kbytes) bank 4 (512 Kbytes) bank 5 (512 Kbytes) bank 5 (512 Kbytes) bank 6 (512 Kbytes) bank 6 (512 Kbytes)bank 7 (512 Kbytes) Data Program or data OFS bit in DBR register = 0 OFS bit in DBR register = 1 300000h bank 0 (512 Kbytes)40000h 40000h 40000h 40000h 40000h 40000h 40000h BFFFFh BFFFFh BFFFFh BFFFFh BFFFFh BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh Program or data FFFFFh A18 CS Output Address OutputOFS Access Area Output from the Microcomputer Pins CS3 CS2 CS1 A19 A17 Bank Number 7 0 40000h 000 0 10 000 1 0040000h 001 0 1040000h 001 1 0040000h 010 0 1040000h 010 1 0040000h 011 0 1040000h 011 1 0040000h 100 0 1040000h 100 1 0040000h 101 0 1040000h 101 1 0040000h 110 0 1040000h 110 1 0040000h 40000h 111 0 10 80000h 111 1 00 C0000h 111 1 10 BFFFFh 000 1 01 001 0 11BFFFFh 001 1 01BFFFFh 010 0 11BFFFFh 010 1 01BFFFFh 011 0 11BFFFFh 011 1 01BFFFFh 100 0 11BFFFFh 100 1 01BFFFFh 101 0 11BFFFFh 101 1 01BFFFFh 110 0 11BFFFFh 110 1 01BFFFFh 111 0 11BFFFFh 111 0 117FFFFh 111 1 01BFFFFh 111 1 11FFFFFh 7FFFFh C0000h ROM address Microcomputer address A16 A15 to A0 0000h 000000h0 040000h0 0000h 080000h0 0000h 0C0000h0 0000h 100000h0 0000h 140000h0 0000h 180000h0 0000h 1C0000h0 0000h 200000h0 0000h 240000h0 0000h 280000h0 0000h 2C0000h0 0000h 300000h0 0000h 340000h0 0000h 380000h0 0000h 3C0000h0 0000h 3C0000h0 0000h FFFFh1 07FFFFh

1 FFFFh 0BFFFFh

1 FFFFh 0FFFFFh

1 FFFFh 13FFFFh

1 FFFFh 17FFFFh

1 FFFFh 1BFFFFh

1 FFFFh 1FFFFFh

1 FFFFh 23FFFFh

1 FFFFh 27FFFFh

1 FFFFh 2BFFFFh

1 FFFFh 2FFFFFh

1 FFFFh 33FFFFh

1 FFFFh 37FFFFh

1 FFFFh 3BFFFFh

1 FFFFh 3FFFFFh

A20 A19 A18 N.C. A17 Address Input for 4-Mbyte ROM A21 N.C.: No connected A16 A15 to A0 Address Input for 4-Mbyte ROM Microprocessor mode

M16C/62P Group (M16C/62P , M16C/62PT) 10. Clock Generation Circuit Rev.2.41 Jan 10, 2006 Page 82 of 390 REJ09B0185-0241 10. Clock Generation Circuit

10.1 Types of the Clo ck Generation Circuit

4 circuits are incorporated to generate the system clock signal :

• Main clock oscillation circuit
• Sub clock oscillation circuit
• On-chip oscillator
• PLL frequency synthesizer Table 10.1 lists the Clock Generation Circuit Specifications. Figure 10.1 shows the Clock Generation Circuit. Figures 10.2 to 10.6 show the clock-related registers. Table 10.1 Clock Generation Circuit Specifications Item Main Clock Oscillation Circuit Sub Clock Oscillation Circuit On-chip oscillator PLL frequency synthesizer Use of Clock • CPU clock source
• Peripheral function clock source
• CPU clock source
• Timer A, B's clock source
• CPU clock source
• Peripheral function clock source
• CPU and peripheral function clock sources when the main clock stops oscillating
• CPU clock source
• Peripheral function clock source Clock Frequency 0 to 16 MHz 32.768 kHz About 1 MHz 10 to 24MHz Usable Oscillator • Ceramic oscillator
• Crystal oscillator
• Crystal oscillator −− Pins to Connect Oscillator XIN, XOUT XCIN, XCOUT −− Oscillation Stop, Restart Function Presence Presence Presence Presence Oscillator Status After Reset Oscillating Stopped Stopped Stopped Other Externally derived clock can be input −−

M16C/62P Group (M16C/62P , M16C/62PT) 10. Clock Generation Circuit Rev.2.41 Jan 10, 2006 Page 83 of 390 REJ09B0185-0241 Figure 10.1 Clock Generation Circuit fC32 CM02, CM04, CM05, CM06, CM07: Bits in CM0 register CM10, CM11, CM16, CM17: Bits in CM1 register PCLK0, PCLK1: Bits in PCLKR register CM21, CM27 : Bits in CM2 register Main clock generating circuit fC CM02 CM04 CM10=1(stop mode) QS R WAIT instruction CM05 QS R NMI Interrupt request level judgment output RESET Software reset fC CPU clock CM07=0 CM07=1 Dividera d 1/2 1/2 1/2 1/2 CM06=0 CM17 to CM16=00b CM06=0 CM17 to CM16=01b CM06=0 CM17 to CM16=10b CM06=1 CM06=0 CM17 to CM16=11b d a Details of divider Sub-clock generating circuit XCIN XCOUT XOUTXIN f32 cb b c f32SIO f8SIO fAD e e 1/2 1/4 1/8 1/16 PCLK0=1 PLL frequency synthesizer CM21=1 CM11 CM21=0 On-chip oscillator PLL clock Sub-clock On-chip oscillator clock BCLK PCLK0=0 f1SIO PCLK1=1 PCLK1=0 f2SIO Main clock CLKOUT PM01 to PM00=00b, CM01 to CM00=01b PM01 to PM00=00b, CM01 to CM00=10b CM01 to CM00=00b I/O ports PM01 to PM00=00b, CM01 to CM00=11b CM21 Oscillation stop, re-oscillation detection circuit D4INT clock Oscillation stop detection resetMain clock Oscillation Stop, Re-Oscillation Detection Circuit Oscillation stop detection reset CM21 switch signal CM27=0 CM27=1 Charge, discharge circuit Reset generating circuit Oscillation stop, re-oscillation detection interrupt generating circuit Pulse generation circuit for clock edge detection and charge, discharge control Charge pump Voltage control oscillator (VCO) PLL Clock Main clock 1/2Programmable counter Internal lowpass filter PLL Frequency Synthesizer Phase compar ator

M16C/62P Group (M16C/62P , M16C/62PT) 10. Clock Generation Circuit Rev.2.41 Jan 10, 2006 Page 84 of 390 REJ09B0185-0241 Figure 10.2 CM0 Register System Clock Control Register 0 (1) Symbol Address After Reset CM0 0006h 01001000b Bit Symbol Bit Name Function RW NOTES : 10. 11. 12. 13. 14. b7 b6 b5 b4 b3 b2 b1 b0 CM02 WAIT Mode Peripheral Function Clock Stop Bit (10) 0 : Peripheral function clock does not stop in w ait mode 1 : Peripheral function clock stops in w ait mode (8) RW CM03 XCIN-XCOUT Drive Capacity Select Bit (2) 0 : LOW 1 : HIGH RW CM04 Port XC Select Bit (2) 0 : I/O ports P8_6, P8_7 1 : XCIN-XCOUT oscillation function (9) RW CM05 Main Clock Stop Bit (3, 10, 12, 13) 0 : On 1 : O ff (4, 5) RW CM07 System C lock Select Bit (6, 10, 11, 12) 0 : Main clock, PLL clock, or on-chip oscillator clock 1 : Sub clock RW CM06 Main Cloc k Div is ion Select Bit 0 (7, 13, 14) 0 : CM16 and CM17 enabled 1 : Division-by-8 mode RW To use the main clock as the clock source for the CPU clock, set bits as follow s. (a) Set the CM05 bit to “0” (oscillate). (b) Wait the main clock oscillation stabilizes. (c) Set the CM11, CM21 and CM07 bits to “0”. When the PM21 bit in the PM2 register is set to “1” (disable clock modification), this bit remains unchanged even if w riting to the CM02, CM05, and CM07 bits. When setting the PM21 bit to “1”, set the CM07 bit to “0” (main clock) before setting the PM21 bit to “1”. The CM03 bit is set to “1” (high) w hile the CM04 bit is set to “0” (I/O port) or w hen entering stop mode. This bit is provided to stop the main clock w hen the low pow er consumption mode or on-chip oscillator low pow er dissipation mode is selected. This bit cannot be used for detection as to w hether the main clock stops or not. To stop the main clock, set bits as follow s: (a) Set the CM07 bit to “1” (sub clock selected) or the CM21 bit in the CM2 register to “1” (On-chip oscillator selected) w ith the sub-clock stably oscillates. (b) Set the CM20 bit in the CM2 register to “0” (Oscillation stop, re-oscillation detection function disabled). (c) Set the CM 05 bit to “1” (Stop). To use a sub-clock, set this bit to “1”. Also make sure ports P8_6 and P8_7 are directed for input, w ith no pull-ups. During external clock input, Set the CM05 bit to “0” (oscillate). When CM05 bit is set to “1”, the XOUT pin is held “H”. Because the internal feedback resistor remains connected, the XIN pin is pulled “H” to the same level as XOUT via the feedback resistor. After setting the CM04 bit to “1” (XCIN-XCOUT oscillator function), w ait until the sub-clock oscillates stably before sw itching the CM07 bit from “0” to “1” (sub-clock). When entering stop mode from high-speed or middle-speed mode, on-chip oscillator mode or on-chip oscillator low pow er mode, the CM06 bit is set to “1” (divide-by-8 mode). To return from on-chip oscillator mode to high-speed or middle-speed mode, set the CM06 and CM15 bits to “1”. Rew rite this register after setting the PRC0 bit in the PRCR register to “1” (w rite enable). CM01 RW b1 b0 0 0 : I/O port P5_7 0 1 : Output fC 1 0 : Output f8 1 1 : Output f32 Clock Output Function Select Bit (Valid only in single-chip mode) CM00 RW When the CM21 bit is set to “0” (on-chip oscillator stops) and the CM05 bit is set to “1” (main clock stops), the CM06 bit is fixed to “1” (divide-by-8 mode) and the CM15 bit is fixed to “1” (drive capacity High). The fC32 clock does not stop. In low -speed mode or low pow er consumption mode, do not set this bit to “1” (peripheral clock stops in w ait mode).

M16C/62P Group (M16C/62P , M16C/62PT) 10. Clock Generation Circuit Rev.2.41 Jan 10, 2006 Page 85 of 390 REJ09B0185-0241 Figure 10.3 CM1 Register System Clock Control Register 1 (1) Symbol Address After Reset CM1 0007h 00100000b Bit Symbol Bit Name Function RW NOTES : After setting the PLC07 bit in the PLC0 register to “1” (PLL operation), w ait tsu (PLL) elapses before setting the CM11 bit to “1” (PLL clock). When the PM21 bit in the PM2 register is set to “1” (disable clock modification), this bit remains unchanged even if w riting to the CM10, CM11 bits. When the PM22 bit in the PM2 register is set to “1” (on-chip oscillator clock is selected as w atchdog timer count source), this bit remains unchanged even if w riting to the CM10 bit. This bit is valid w hen the CM07 bit is set to “0” and the CM21 bit is set to “0”. CM11 System Clock Select Bit 1 (6, 7) 0 : Main clock 1 : PLL clock (5) RW (b4-b2) Reserved Bit Set to “0” b3 b2 b1 b0b7 b6 b5 b4 000 CM10 All Clock Stop Control Bit (4, 6) 0 : Clock on 1 : All clocks off (stop mode) RW RW CM15 XIN-XOUT Drive Capacity Select Bit (2) 0 : LOW 1 : HIGH RW CM17 RW b7 b6 0 0 : No division mode 0 1 : Divide-by-2 mode 1 0 : Divide-by-4 mode 1 1 : Divide-by-16 mode M ain C lock D ivision Select Bit 1 (3) CM16 RW Rew rite this register after setting the PRC0 bit in the PRCR register to “1” (w rite enable). When entering stop mode from high-speed or middle-speed mode, or the CM05 bit is set to “1” (main clock stops) in low speed mode, the CM15 bit is set to “1” (drive capacity high). This bit is valid w hen the CM06 bit is set to “0” (CM16 and CM17 bits enabled). If the CM10 bit is set to “1” (stop mode), XOUT is held “H” and the internal feedback resistor is disconnected. The XCIN and XCOUT pins are in high-impedance state. When the CM11 bit is set to “1” (PLL clock), or the CM20 bit in the CM2 register is set to “1” (oscillation stop, re-oscillation detection function enabled), do not set the CM10 bit to “1”.

M16C/62P Group (M16C/62P , M16C/62PT) 10. Clock Generation Circuit Rev.2.41 Jan 10, 2006 Page 86 of 390 REJ09B0185-0241 Figure 10.4 CM2 Register Oscillation Stop Detection Register (1) Symbol Address After Reset CM2 000Ch 0X000000b (11) Bit Symbol Bit Name Function RW NOTES : 10. 11. 12. CM21 RW CM20 RW Oscillation Stop, Re-Oscillation Detection Enable Bit (7, 9, 10,11) 0: Oscillation stop, re-oscillation detection function disabled 1: Oscillation stop, re-oscillation detection function enabled 0: Main clock or PLL clock 1: On-chip oscillator clock (On-chip oscillator oscillates) Where the CM20 bit is set to “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is “1” (oscillation stop, re-oscillation detection interrupt), and the CM11 bit is set to “1” (PLL clock is selected as the CPU clock source), the CM21 bit remains unchanged even if a main clock stop is detected. When the CM22 bit is set to “0” under these conditions, an oscillation stop, a re-oscillation detection interrupt request is generated at main clock stop detection. Set the CM21 bit to “1” (on-chip oscillator clock) in the interrupt routine. System Clock Select Bit 2 Nothing is assigned. When w rite, set to “0”. When read, its content is “0”. When the CM21 bit is set to “0” (on-chip oscillator stops) and the CM05 bit is set to “1” (main clock stops), the CM06 bit is fixed to “1” (divide-by-8 mode) and the CM15 bit is fixed to “1” (drive capacity High). Set the CM20 bit in the CM2 register to “0” (disabled) before setting the CM05 bit in the CM0 register to “1” (main clock stops). The CM20, CM21 and CM27 bits remain unchanged at the oscillation stop detection reset. When the CM20 bit is set to “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is set to “1” (oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock, the CM21 bit is set to “1” (on-chip oscillator clock) if the main clock stop is detected. If the CM20 bit is set to “1” and the CM23 bit is set to “1” (main clock stops), do not set the CM21 bit to “0”. Set the CM20 bit to “0” (disabled) before entering stop mode. Exit stop mode before setting the CM20 bit back to “1” (enabled). This bit is set to “1” w hen the main clock stop is detected and the main clock re-oscillation is detected. When this flag changes state from “0” to “1”, an oscillation stop or a re-oscillation detection interrupt is generated. Use this bit in an interrupt routine to determine the factors of interrupts betw een the oscillation stop and re-oscillation detection interrupt and the w atchdog timer interrupt. This bit is set to “0” by w riting “0” in a program. (This bit remains unchanged even if w riting “1”. Nor is it set to “0” w hen an oscillation stop or a re-oscillation detection interrupt request is acknow ledged.) When the CM22 bit is set to “1” and an oscillation stop or a re-oscillation is detected, an oscillation stop or a re- oscillation detection interrupt is not generated. Determine the main clock status by reading the CM23 bit several times in an oscillation stop or a re-oscillation detection interrupt routine This bit is valid w hen the CM07 bit in the CM0 register is set to “0”. When the PM21 bit in the PM2 register is set to “1” (disable clock modification), this bit remains unchanged even if w riting to the CM20 bit. CM27 Operation Select Bit (w hen an oscillation stop, re-oscillation is detected) (11) 0: Oscillation stop detection reset 1: Oscillation stop, re-oscillation detection interrupt RW (b6) Rew rite this register after setting the PRC0 bit in the PRCR register to “1” (w rite enable). Set to “0” RW CM23 XIN Monitor Flag (5) 0: Main clock oscillates 1: Main clock stops RO (b5-b4) Res erv ed Bit CM22 Oscillation Stop, Re-Oscillation Detection Flag (4) 0: Main clock stops, re-oscillation not detected 1: Main clock stops, re-oscillation detected RW b3 b2 b1 b0b7 b6 b5 b4

M16C/62P Group (M16C/62P , M16C/62PT) 10. Clock Generation Circuit Rev.2.41 Jan 10, 2006 Page 87 of 390 REJ09B0185-0241 Figure 10.5 PCLKR Register and PM2 Register Processor Mode Register 2 (1) Symbol Address After Reset PM2 001Eh XXX00000b Bit Symbol Bit Name Function RW NOTES : b7 b6 b5 b4 b3 b2 b1 b0 PM22 WDT Count Source Protective Bit (3, 5) 0 : CPU clock is used for the w atchdog timer count source 1 : On-chip oscillator clock is used for the w atchdog timer count source RW Set to “0” RW— (b4-b3) Res erv ed Bit Setting the PM22 bit to “1” results in the follow ing conditions:

• The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the w atchdog timer count source.
• The CM10 bit is disabled against w rite. (Writing a “1” has no effect, nor is stop mode entered.)
• The w atchdog timer does not stop w hen in w ait mode or hold state. (b7-b5) Write to this register after setting the PRC1 bit in the PRCR register to “1” (w rite enable). Nothing is assigned. When w rite, set to “0”. When read, their contents are indeterminate. The PM20 bit become effective w hen PLC07 bit in the PLC0 register is set to “1” (PLL on). Change the PM20 bit w hen the PLC07 bit is set to “0” (PLL off). Set the PM20 bit to “0” (2 w aits) w hen PLL clock > 16MHz. Once this bit is set to “1”, it cannot be cleared to “0” in a program. If the PM21 bit is set to “1”, w riting to the follow ing bits has no effect: CM02 bit in CM0 register CM05 bit in CM0 register (main clock does not stop) CM07 bit in CM0 register (clock source for the CPU clock does not change) CM10 bit in CM1 register (stop mode is not entered) CM11 bit in CM1 register (clock source for the CPU clock does not change) CM20 bit in CM2 register (oscillation stop, re-oscillation detection function settings do not change) All bits in PLC0 register (PLL frequency synthesizer settings do not change) Be aw are that the WAIT instruction cannot be executed w hen the PM21 bit = 1. PM21 RW PM20 RW Specifying Wait w hen Accessing SFR at PLL Operation (2) 0 : 2 w aits 1 : 1 w aits 0 : Clock is protected by PRCR register 1 : Clock modification disabled System Clock Protective Bit (3, 4) Peripheral Clock Select Register (1) Symbol Address After Reset PCLKR 025Eh 00000011b Bit Symbol Bit Name Function RW NOTES : 1. Write to this register after setting the PRC0 bit in the PRCR register to “1” (w rite enable). (b7-b2) Reserved bit Set to “0” RW PCLK1 SI/O Clock Select Bit (Clock source for UART0 to UART2, SI/O3, and SI/O4) 0 : f2SIO 1 : f1SIO RW PCLK0 Timers A, B Clock Select Bit (Clock source for Timers A , B, and the dead timer) 0 : f2 1 : f1 RW 000000 b7 b6 b5 b4 b3 b2 b1 b0

M16C/62P Group (M16C/62P , M16C/62PT) 10. Clock Generation Circuit Rev.2.41 Jan 10, 2006 Page 88 of 390 REJ09B0185-0241 Figure 10.6 PLC0 Register PLL Control Register 0 (1, 2) Symbol Address After Reset PLC0 001Ch 0001X010b Bit Symbol Bit Name Function RW NOTES : PLC07 (b6-b5) Reserved Bit Set to “0” Write to this register after setting the PRC0 bit in the PRCR register to “1” (w rite enable). When the PM21 bit in the PM2 register is “1” (clock modification disable), w riting to this register has no effect. These three bits can only be modified w hen the PLC07 bit = 0 (PLL turned off). The value once w ritten to this bit cannot be modified. Before setting this bit to “1”, set the CM07 bit in the CM0 register to “0” (main clock), set the CM17 to CM16 bits in the CM1 register to “00b” (main clock undivided mode), and set the CM06 bit in the CM0 register to “0” (CM16 and CM17 bits enable). 0: PLL Off 1: PLL On Operation Enable Bit (4) Nothing is assigned. When w rite, set to “0”. When read, its content is indeterminate. Set to “1”Reserved Bit RW RW RW RW RW PLC00 RW 001 b2 b1 b0 0 0 0 : Do not set 0 0 1 : Multiply by 2 0 1 0 : Multiply by 4 0 1 1 : Multiply by 6 1 0 0 : Multiply by 8 1 0 1 : 1 1 0 : Do not set 1 1 1 : b7 b6 b5 b4 b3 b2 b1 b0 (b4) PLC01 PLC02 PLL Multiplying Factor Select Bit (3) (b3)

M16C/62P Group (M16C/62P , M16C/62PT) 10. Clock Generation Circuit Rev.2.41 Jan 10, 2006 Page 89 of 390 REJ09B0185-0241 The following describes the clocks generated by the clock generation circuit.

10.1.1 Main Clock

This clock is used as the clock source for the CPU and peripheral function clocks. This clock is used as the clock source for the CPU and peripheral function clocks. The main clock os cillator circuit is configured by connecting a resonator between the XIN and XOUT pins. The main clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator circ uit during stop mode in order to reduce the amount of power consumed in the chip. The main clock oscillator circuit may also be configured by feeding an externally generated clock to the XIN pin. Figure 10.7 shows the Examples of Main Clock Connection Circuit. After reset, the main clock divided by 8 is selected for the CPU clock. The power consumption in the chip can be reduced by setting the CM05 bit in the CM0 register to “1” (main clock oscillator circuit turned off) after switching the clock source for the CPU clock to a sub clock or on-chip oscillator clock. In this case, XOUT goes “H”. Furthermore, because the internal feedback resistor remains on, XIN is pulled “H” to XOUT via the feedback resistor. Note that if an externally generated clock is fed into the XIN pin, the main clock cannot be turned off by setting the CM05 bit to “1,” unless the sub clock is chosen as a CPU clock. If necessary, use an external circuit to turn off the clock. During stop mode, all clocks including the main clock are turned off. Refer to 10.4 Power Control. Figure 10.7 Examples of Main Clock Connection Circuit External clock Open VCC1 VSS Microcomputer (Built-in Feedback Resistor) XIN XOUT Rd(1) CIN COUT NOTES : 1. Place a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by each oscillator the oscillator manufacturer. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, place a feedback resistor between XIN and XOUT if the oscillator manufacturer recommends placing the resistor externally. VSS Oscillator Microcomputer (Built-in Feedback Resistor) XIN XOUT

M16C/62P Group (M16C/62P , M16C/62PT) 10. Clock Generation Circuit Rev.2.41 Jan 10, 2006 Page 90 of 390 REJ09B0185-0241

10.1.2 Sub Clock

The sub clock is generated by the sub clock oscillation ci rcuit. This clock is used as the clock source for the CPU clock, as well as the timer A and timer B count sour ces. In addition, an fc clock with the same frequency as that of the sub clock can be output from the CLKOUT pin. The sub clock oscillator circuit is configured by connecting a crystal resonator between the XCIN and XCOUT pins. The sub clock oscillator circuit contains a feedba ck resistor, which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. The sub clock oscillator circuit may also be configured by feeding an externally generated clock to the XCIN pin. Figure 10.8 shows the Examples of Sub Clock Connection Circuit. After reset, the sub clock is turned off. At this time, the feedback resistor is disconnected from the oscillator circuit. To use the sub clock for the CPU clock, set the CM07 bit in the CM0 register to “1” (sub clock) after the sub clock becomes oscillating stably. During stop mode, all clocks including the sub clock are turned off. Refer to 10.4 Power Control. Figure 10.8 Examples of S ub Clock Connection Circuit NOTES : 1. Place a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by each oscillator the oscillator manufacturer. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, place a feedback resistor between XCIN and XCOUT if the oscillator manufacturer recommends placing the resistor externally. External clock Open VCC1 VSS XCIN XCOUT RCd(1) CCIN CCOUT VSS Oscillator Microcomputer (Built-in Feedback Resistor) XCIN XCOUT Microcomputer (Built-in Feedback Resistor)

M16C/62P Group (M16C/62P , M16C/62PT) 10. Clock Generation Circuit Rev.2.41 Jan 10, 2006 Page 91 of 390 REJ09B0185-0241

10.1.3 On-chip Oscillator Clock

This clock, approximately 1MHz, is supplied by a on-chip oscillator. This clock is used as the clock source for the CPU and peripheral function clocks. In addition, if the PM22 bit in the PM2 register is “1” (on-chip oscillator clock for the watchdog timer count source), this clock is used as the co unt source for the watchdog timer (Refer to 13.1 Count source protective mode). After reset, the on-chip oscillator is turned off. It is turned on by setting the CM21 bit in the CM2 register to “1” (on-chip oscillator clock), and is used as the clock source for the CP U and peripheral function clocks, in place of the main clock. If the main clock stops osc illating when the CM20 bit in the CM2 register is “1” (oscillation stop, re-oscillation detection function enabled) and the CM27 bit is “1” (oscillation stop, re- oscillation detection interrupt), the on -chip oscillator automatically starts operating, supplying the necessary clock for the microcomputer.

10.1.4 PLL Clock

The PLL clock is generated PLL frequency synthesizer. This clock is used as the clock source for the CPU and peripheral function clocks. After reset, the PLL clock is turned off. The PLL frequency synthesizer is activated by setting the PLC07 bit to “1” (PLL operation). When th e PLL clock is used as th e clock source for the CPU clock, wait tsu(PLL) for the PLL clock to be stable, and then set the CM11 bit in the CM1 register to “1”. Before entering wait mode or stop mode, be sure to set the CM11 bit to “0” (CPU clock source is the main clock). Furthermore, before entering stop mode, be sure to set the PLC07 bit in the PLC0 register to “0” (PLL stops). Figure 10.9 shows the Procedure to Use PLL Clock as CPU Clock Source. The PLL clock frequency is determined by the equati on below. When the PLL clock frequency is 16 MHz or more, set the PM20 bit in the PM2 register to “0” (2 waits). PLL clock frequency=f(XIN) X (multiplying factor set by the PLC02 to PLC00 bits in the PLC0 register (However, 10 MHz PLL clock frequency 24 MHz) The PLC02 to PLC00 bits can be set only once after reset. Table 10.2 shows the Example for Setting PLL Clock Frequencies. NOTES: 1. 10MHz ≤ PLL clock frequency ≤ 24MHz. Table 10.2 Example for Setting PLL Clock Frequencies XIN (MHz) PLC02 PLC01 PLC00 Multiplying Factor PLL Clock (MHz) (1) 10 0 0 1 2 205010 4 3.33 0 1 1 6 2.5 1 0 0 8 12 0 0 1 2 246010 4 4011 6 3100 8

M16C/62P Group (M16C/62P , M16C/62PT) 10. Clock Generation Circuit Rev.2.41 Jan 10, 2006 Page 92 of 390 REJ09B0185-0241 Figure 10.9 Procedure to Use PLL Clock as CPU Clock Source Using the PLL clock as the clock source for the CPU Set the CM07 bit to “0” (main clock), the CM17 to CM16 bits to “00b” (main clock undivided), and the CM06 bit to “0” (CM16 and CM17 bits enabled). (1) Set the PLC02 to PLC00 bits (multiplying factor). (When PLL clock > 16MHz) Set the PM20 bit to “0” (2 wait states). Set the PLC07 bit to “1” (PLL operation). Wait until the PLL clock becomes stable (tsu(PLL)). Set the CM11 bit to “1” (PLL clock for the CPU clock source). END NOTES : 1. PLL operation mode can be entered from high speed mode.

M16C/62P Group (M16C/62P , M16C/62PT) 10. Clock Generation Circuit Rev.2.41 Jan 10, 2006 Page 93 of 390 REJ09B0185-0241

10.2 CPU Clock and Peri pheral Function Clock

Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the peripheral functions.

10.2.1 CPU Clock and BCLK

These are operating clocks for the CPU and watchdog timer. The clock source for the CPU clock can be chosen to be the main clock, sub clock, on-chip oscillator clock or the PLL clock. If the main clock or on-chip oscillator clock is selected as the clock source for the CPU clock, the selected clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit in CM0 register and the CM17 to CM16 bits in the CM1 register to select the divide-by-n value. When the PLL clock is selected as the clock source fo r the CPU clock, the CM06 bit should be set to “0” and the CM17 to CM16 bits to “00b” (undivided). After reset, the main clock divided by 8 provides the CPU clock. During memory expansion or microprocessor mode, a BCL K signal with the same frequency as the CPU clock can be output from the BCLK pin by setting the PM07 bit in the PM0 register to “0” (output enabled). Note that when entering stop mode from high or mi ddle speed mode, on-chip oscillator mode or on-chip oscillator low power dissipation mode, or when the CM05 bit in the CM0 register is set to “1” (main clock turned off) in low-speed mode, the CM06 bit in the CM0 register is set to “1” (divide-by-8 mode).

10.2.2 Peripheral Function Clock (f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD,

fC32) These are operating clocks for the peripheral functions. Of these, fi (i = 1, 2, 8, 32) and fiSIO are derived from the main clock, PLL clock or on-chip oscillator clock by dividing them by i. The clock fi is used for timers A a nd B, and fiSIO is used for serial I/O. The f8 and f32 clocks can be output from the CLKOUT pin. The fAD clock is produced from the main clock, PLL clock or on-chip oscillator clock, and is used for the A/D converter. When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to “1” (peripheral function clock turned off during wait mode), or when the microcomputer is in low power dissipation mode, the fi, fiSIO and fAD clocks are turned off. The fC32 clock is produced from the sub clock, and is used for timers A and B. This clock can be used when the sub clock is on.

10.3 Clock Output Function

During single-chip mode, the f8, f32 or fC clock can be output from the CLKOUT pin. Use the CM01 to CM00 bits in the CM0 register to select.

M16C/62P Group (M16C/62P , M16C/62PT) 10. Clock Generation Circuit Rev.2.41 Jan 10, 2006 Page 94 of 390 REJ09B0185-0241

10.4 Power Control

Normal operating mode, wait mode and stop mode are pr ovided as the power consumption control. All mode states, except wait mode and stop mode, are called normal operating mode in this document.

10.4.1 Normal Operating Mode

Normal operating mode is further classified into seven modes. In normal operating mode, because the CPU clock and the peripheral function clocks both are on, the CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock frequency. The higher the CPU clock frequency, the greater the processing capability. The lower the CPU clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator circuits are turned off, the power consumption is further reduced. Before the clock sources for the CPU clock can be switched over, the new clock source to which switched must be oscillating stably. If the new clock source is the main clock, sub clock or PLL clock, allow a sufficient wait time in a program until it becomes oscillating stably. Note that operating modes cannot be changed directly from low speed or low power dissipation mode to on- chip oscillator or on-chip oscillator low power dissipation mode. Nor can operating modes be changed directly from on-chip oscillator or on-chip oscillator low power dissipation mode to low speed or low power dissipation mode. Where the CPU clock source is changed from th e on-chip oscillator to the main clock, change the operating mode to the medium speed mode (divided by 8 mode) after the clock was divided by 8 (the CM06 bit in the CM0 register was set to “1”) in the on-chip oscillator mode.

10.4.1.1 High-speed Mode

The main clock divided by 1 provides the CPU clock. If the sub clock is on, fC32 can be used as the count source for Timers A and B.

10.4.1.2 PLL Operating Mode

The main clock multiplied by 2, 4, 6 or 8 provides the PLL clock, and this PLL clock serves as the CPU clock. If the sub clock is on, fC32 can be used as the count so urce for Timers A and B. PLL operating mode can be entered from high speed mode. If PLL operating mode is to be changed to wait or stop mode, first go to high speed mode before changing.

10.4.1.3 Medium-Speed Mode

The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the sub clock is on, fC32 can be used as the count source for Timers A and B.

10.4.1.4 Low-Speed Mode

The sub clock provides the CPU clock. The main clock is used as the clock sour ce for the peripheral function clock when the CM21 bit in the CM2 register is set to “0” (on-chip oscillator tu rned off), and the on-chip oscillator clock is used when the CM21 bit is set to “1” (on-chip oscillator oscillating). The fC32 clock can be used as the count source for Timers A and B.

10.4.1.5 Low Power Dissipation Mode

In this mode, the main clock is turned off after being placed in low speed mode. The sub clock provides the CPU clock. The fC32 clock can be used as the count source for Timers A and B. Simultaneously when this mode is selected, the CM06 bit becomes “1” (divided by 8 mode). In the low power dissipation mode, do not change the CM06 bit. Consequently, the medium speed (divided by 8) mode is to be selected when the main clock is operated next

10.4.1.6 On-chip Oscillator Mode

The on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The on-chip oscillator clock is also the clock source for the periphe ral function clocks. If the sub clock is on, fC32 can be used as the count source for Timers A and B. When th e operating mode is returned to the high and medium speed modes, set the CM06 bit in the CM0 register to “1” (divided by 8 mode).

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10.4.1.7 On-chip Oscillator Low Power Dissipation Mode

The main clock is turned off after being placed in on-chip oscillator mode. The CPU clock can be selected as in the on-chip oscillator mode. The on-chip oscillator clock is the clock source for the peripheral function clocks. If the sub clock is on, fC32 can be used as the count source for Timers A and B. NOTES: 1. When the CM05 bit is set to “1” (main clock turned off) in low-speed mode, the mode goes to low power dissipation mode and CM06 bit is set to “1” (divided by 8 mode) simultaneously. 2. The divide-by-n value can be selected th e same way as in on-chip oscillator mode. Table 10.3 Setting Clock Related Bit and Modes Modes CM2 Register CM1 Register CM0 Register CM21 CM11 CM17, CM16 CM07 CM06 CM05 CM04 PLL Operating Mode 0 1 00b 0 0 0 − High-Speed Mode 0 0 00b 0 0 0 − Medium- Speed Mode divided by 2 0 0 01b 0 0 0 − divided by 4 0 0 10b 0 0 0 − divided by 8 0 0 - 0 1 0 − divided by 16 0 0 11b 0 0 0 − Low-Speed Mode − 0 − 1 − 01 Low Power Dissipation Mode 0 0 − 11 (1) 1(1) 1 On-chip Oscillator Mode divided by 1 1 0 00b 0 0 0 − divided by 2 1 0 01b 0 0 0 − divided by 4 1 0 10b 0 0 0 − divided by 8 1 0 − 010 − divided by 16 1 0 11b 0 0 0 − On-chip Oscillator Low Power Dissipation Mode 10 ( N O T E 2 ) 0 ( N O T E 2 ) 1 −

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10.4.2 Wait Mode

In wait mode, the CPU clock is turn ed off, so are the CPU (because op erated by the CP U clock) and the watchdog timer. However, if the PM22 bit in the PM2 register is “1” (on-chip oscillator clock for the watchdog timer count source), the watchdog timer remains acti ve. Because the main clock, sub clock and on-chip oscillator clock all are on, the peripheral functions using these clocks keep operating.

10.4.2.1 Peripheral Functi on Clock Stop Function

If the CM02 bit in the CM0 register is “1” (peripheral function clocks turned off during wait mode), the f1, f2, f8, f32, f1SIO, f8SIO, f32SIO and fA D clocks are turned off when in wa it mode, with the power consumption reduced that much. However, fC32 remains on.

10.4.2.2 Entering Wait Mode

The microcomputer is placed into wait mode by executing the WAIT instruction. When the CM11 bit = 1 (CPU clock source is the PLL clock), be sure to clear the CM11 bit in the CM1 register to “0” (CPU clock source is the main clock) before going to wait mode. The power consumption of the chip can be reduced by clearing the PLC07 bit in the PLC0 register to “0” (PLL stops).

10.4.2.3 Pin Status During Wait Mode

Table 10.4 lists Pin Status During Wait Mode. Table 10.4 Pin Status During Wait Mode Pin Memory Expansion Mode Microprocessor Mode Single-Chip Mode A0 to A19, D0 to D15, CS0 to CS3, BHE Retains status before wait mode Does not become a bus control pin RD, WR, WRL, WRH “H” HLDA, BCLK “H” ALE “L” I/O ports Retains status before wait mode Retains status before wait mode CLKOUT When fC selected Does not become a CLKOUT pin Does not stop When f8, f32 selected Does not stop when the CM02 bit is “0”. When the CM02 bit is “1”, the status immediately prior to entering wait mode is maintained.

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10.4.2.4 Exiting Wait Mode

The microcomputer is moved out of wa it mode by a hardware reset, NMI interrupt, low voltage detection interrupt or peripheral function interrupt. If the microcomputer is to be moved out of exit wait mode by a hardware reset, NMI interrupt or low voltage detection interrupt, set the peripheral function interrupt priority ILVL2 to ILVL0 bits to “000b” (interrupts disabled) before executing the WAIT instruction. The peripheral function interrupts are affected by the CM02 bit. If CM02 bit is “0” (peripheral function clocks not turned off during wait mode), peripheral function interrupts can be used to exit wait mode. If CM02 bit is “1” (peripheral function clocks turned off during wait mode), the peripheral func tions using the peripheral function clocks stop operating, so that only the periphera l functions clocked by external signals can be used to exit wait mode. Table 10.5 lists the Interrupts to Exit Wait Mode and Use Conditions. If the microcomputer is to be moved out of wait mode by a peripheral function interrupt, set up the following before executing the WAIT instruction. (1) Set the ILVL2 to ILVL0 bits in the interrupt control register, for peripheral function interrupts used to exit wait mode. The ILVL2 to ILVL0 bits in all other interrupt cont rol registers, for peripheral function interrupts not used to exit wait mode, are set to “000b” (interrupt disable). (2) Set the I flag to “1”. (3) Start operating the peripheral functions used to exit wait mode. When the peripheral function interrupt is used, an inte rrupt routine is performed as soon as an interrupt request is acknowledged and the CPU clock is supplied again. When the microcomputer exits wait mode by the peripheral function interrupt, the CPU clock is the same clock as the CPU clock executing the WAIT instruction. Table 10.5 Interrupts to Exit Wait Mode and Use Conditions Interrupt CM02=0 CM02=1 NMI Interrupt Can be used Can be used Serial Interface Interrupt Can be used when operating with internal or external clock Can be used when operating with external clock Key Input Interrupt Can be used Can be used A/D Conversion Interrupt Can be used in one-shot mode or single sweep mode −(Do not use) Timer A Interrupt Timer B Interrupt Can be used in all modes Can be used in event counter mode or when the count source is fC32 INT Interrupt Can be used Can be used Low Voltage Detection Interrupt Can be used Can be used

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10.4.3 Stop Mode

In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocke d by these clocks stop operati ng. The least amount of power is consumed in this mode. If the voltage applied to VCC1 and VCC2 pins is VRAM or more, the internal RAM is retained. When applying 2.7 or less vo ltage to VCC1 and VCC2 pins, make sure VCC1 ≥ VCC2 ≥ VRAM. However, the peripheral functions clocked by external signals keep operating. The following interrupts can be used to exit stop mode. Table 10.6 lists Interrupts to Stop Mode and Use Conditions

10.4.3.1 Entering Stop Mode

The microcomputer is placed in to stop mode by se tting the CM10 bit in the CM1 register to “1” (all clocks turned off). At the same time, the CM06 bit in the CM0 register is set to “1” (divide-by-8 mode) and the CM15 bit in the CM1 register is set to “1” (main clock oscillator circuit drive capability high). Before entering stop mode, set the CM20 bit in the CM2 register to “0” (oscillation stop, re-oscillation detection function disable). Also, if the CM11 bit in the CM1 register is “1” (PLL clock for the CPU clock source), set the CM11 bit to “0” (main clock for the CPU clock source) and the PLC07 bit in the PLC0 register to “0” (PLL turned off) before entering stop mode.

10.4.3.2 Pin Status in Stop Mode

Table 10.7 lists Pin Status in Stop Mode. Table 10.6 Interrupts to Stop Mode and Use Conditions Interrupt Condition NMI Interrupt Can be used Key Input Interrupt Can be used INT Interrupt Can be used Timer A Interrupt Timer B Interrupt Can be used (when counting external pulses in event counter mode) Serial Interface Interrupt Can be used (when external clock is selected) Low Voltage Detection Interrupt Can be used (Refer to 6.1 Low Voltage Detection Interrupt for an Operating Condition) Table 10.7 Pin Status in Stop Mode Pin Memory Expansion Mode Microprocessor Mode Single-Chip Mode A0 to A19, D0 to D15, CS0 to CS3, BHE Retains status before stop mode Does not become a bus control pin RD, WR, WRL, WRH “H” HLDA, BCLK “H” ALE indeterminate I/O ports Retains status before stop mode Retains status before stop mode CLKOUT When fC selected Does not become a CLKOUT pin “H” When f8, f32 selected Retains status before stop mode

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10.4.3.3 Exiting Stop Mode

Stop mode is exited by a hardware reset, NMI interrupt, low voltage detection interrupt or peripheral function interrupt. When the hardware reset, NMI interrupt or low voltage detection interrupt is used to exit stop mode, set all ILVL2 to ILVL0 bits in the interrupt control registers fo r the peripheral function in terrupt to “000b” (interrupt disabled) before setting the CM10 bit to “1”. When the peripheral function interrupt is used to exit stop mode, set the CM10 bit to “1” after the following settings are completed. (1) Set the ILVL2 to ILVL0 bits in the interrupt contro l registers to decide the peripheral priority level of the peripheral function interrupt. Set the interrupt priority levels of the interrupts, not being used to exit stop mode, to “0” by setting the all ILVL2 to ILVL0 bits to “000b”. (2) Set the I flag to “1”. (3) Start operation of peripheral function being used to exit wait mode. When exiting stop mode by the peripheral function interrupt, the interrupt routine is performed when an interrupt request is generated and the CPU clock is supplied again. When stop mode is exited by the peripheral function interrupt or NMI interrupt, the CPU clock source is as follows, in accordance with the CPU clock source setting before the microcomputer had entered stop mode.

• When the sub clock is the CPU clock before entering stop mode : Sub clock
• When the main clock is the CPU clock source before entering stop mode : Main clock divided by 8
• When the on-chip oscillator clock is the CPU clock source before entering stop mode : On-chip oscillator clock divided by 8 Figure 10.10 shows the State Transition from Normal Op erating Mode to Stop Mode and Wait Mode. Figure 10.11 shows the State Transition in Normal Operating Mode. Table 10.8 shows a state transition matrix describing Allowed Transition and Setting. The vertical line shows current state and horizontal line shows state after transition. Figure 10.10 State Transition to Stop Mode and Wait Mode Reset Medium-speed mode (divided-by-8 mode) High-speed, medium- speed modeStop mode Wait mode InterruptCM10=1(6) Interrupt Normal mode Low-speed, low power dissipation mode CM10=1(6) Stop mode Interrupt Wait mode Interrupt CM10=1(6) Stop mode All oscillators stopped Interrupt Wait mode WAIT instruction Interrupt CPU operation stopped When low- speed mode When low power dissipation mode PLL operation mode (NOTES 1, 2) NOTES : 1. Do not go directly from PLL operation mode to wait or stop mode. 2. PLL operation mode can be entered from high speed mode. Similarly, PLL operation mode can be changed back to high speed mode. 3. Shown above is the case where the PM21 bit in the PM2 register = 0 (system clock protective function unused). 4. The on-chip oscillator clock divided by 8 provides the CPU clock. 5. Write to the CM0 and CM1 registers per 16 bit with CM21=0 (on-chip oscillator stops). Since the operation starts from the main clock after exiting stop mode, the time until the CPU operates can be reduced. 6. Before entering stop mode, be sure to clear the CM20 bit in the CM2 register to “ 0” (oscillation stop and oscillation restart detection function disabled). On-chip oscillator, On-chip oscillator dissipation mode Wait modeInterrupt CM10=1(6) Interrupt(4) Stop mode WAIT instruction WAIT instruction WAIT instruction CM07=0 CM06=1 CM05=0 CM11=0 CM10=1 (5)

M16C/62P Group (M16C/62P , M16C/62PT) 10. Clock Generation Circuit Rev.2.41 Jan 10, 2006 Page 100 of 390 REJ09B0185-0241 Figure 10.11 State Transition in Normal Operating Mode Main clock oscillation CPU clock : f(PLL) CM07=0 CM06=0 CM17=0 CM16=0 PLL operation mode CPU clock f(Ring) f(Ring)/2 f(Ring)/4 f(Ring)/8 f(Ring)/16 On-chip oscillator mode CPU clock f(Ring) f(Ring)/2 f(Ring)/4 f(Ring)/8 f(Ring)/16 On-chip oscillator low power dissipation mode PLC07=1 CM11=1(6) PLC07=0 CM11=0 Sub clock oscillation CPU clock : f(PLL) CM07=0 CM06=0 CM17=0 CM16=0 PLL operation mode CPU clock f(Ring) f(Ring)/2 f(Ring)/4 f(Ring)/8 f(Ring)/16 On-chip oscillator mode CPU clock f(Ring) f(Ring)/2 f(Ring)/4 f(Ring)/8 f(Ring)/16 On-chip oscillator low power dissipation modePLC07=1 CM11=1(6) PLC07=0 CM11=0 CM04=1 CM04=0 CM04=1 CM04=0 CM04=1 CM04=0 CPU clock : f(XCIN) CM07=0 Low-speed mode CM04=1 CM04=0 CPU clock : f(XIN) CM07=0 CM06=0 CM17=0 CM16=0 High-speed mode CPU clock : f(XIN)/4 CM07=0 CM06=0 CM17=1 CM16=0 Middle-speed mode (divide by 4) CPU clock : f(XIN)/16 CM07=0 CM06=0 CM17=1 CM16=1 Middle-speed mode (divide by 16) CPU clock : f(XIN) CM07=0 CM06=0 CM17=0 CM16=0 High-speed mode CPU clock : f(XIN)/2 CM07=0 CM06=0 CM17=0 CM16=1 Middle-speed mode (divide by 2) CPU clock : f(XIN)/4 CM07=0 CM06=0 CM17=1 CM16=0 Middle-speed mode (divide by 4) CPU clock : f(XIN)/8 Middle-speed mode (divide by 8) CM07=0 CM06=1 CPU clock : f(XIN)/16 CM07=0 CM06=0 CM17=1 CM16=1 Middle-speed mode (divide by 16) CPU clock : f(XIN)/2 CM07=0 CM06=0 CM17=0 CM16=1 Middle-speed mode (divide by 2) CPU clock : f(XIN)/8 Middle-speed mode (divide by 8) CM07=0 CM06=1 CPU clock : (XCIN) CM07=0 CM06=1 CM15=1 Low power dissipation mode CPU clock : f(XCIN) CM07=0 Low-speed modeCM21=0 CM21=1 CM21=0(7) CM21=1 CM05=0 CM05=1(1) CM21=0(7) CM21=1 CM05=0 CM05=1(1) On-chip oscillator clock oscillation NOTES: 1. Avoid making a transition when the CM20 bit in the CM2 register is set to “1” (oscillation stop, re-oscillation detection function enabled). Set the CM20 bit to “0” (oscillation stop, re-oscillation detection function disabled) before transiting. 2. Wait the main clock oscillation stabilizes. 3. Switch clock after oscillation of sub-clock is sufficiently stable. 4. Change CM17 and CM16 bits in the CM1 register before changing CM06 bit in the CM0 register. 5. Transit in accordance with arrow. 6. The PM20 bit in the PM2 register become effective when the PLC07 bit in the PLC0 register is set to “1” (PLL on). Change the PM20 bit when the PLC07 bit is set to “0” (PLL off). Set the PM20 bit to “0” (2 waits) when PLL clock >16MHz. 7. Set the CM06 bit to “1” (division by 8 mode) before changing back the operation mode from on-chip oscillator mode to high- or middle-speed mode. 8. When the CM21 bit in the CM2 register = 0 (on-chip oscillator turned off) and the CM05 bit in the CM0 register = 1 (main clock turned off), the CM06 bit is fixed to 1 (divide-by-8 mode) and the CM15 bit in the CM1 register is fixed to “1” (drive capability High).

M16C/62P Group (M16C/62P , M16C/62PT) 10. Clock Generation Circuit Rev.2.41 Jan 10, 2006 Page 101 of 390 REJ09B0185-0241 −: Cannot transit NOTES: 1. Avoid making a transition when the CM20 bit is set in to “1” (oscillation stop, re-oscillation detection function enabled). Set the CM20 bit to “0” (oscillation stop, re-oscillation detection function disabled) before transiting. 2. On-chip oscillator clock oscillates and stops in low-speed mode. In this mode, the on-chip oscillator can be used as peripheral function clock. Sub clock oscillates and stops in PLL operating mode. In this mode, sub clock can be used as peripheral function clock. 3. PLL operating mode can only be entered from and changed to high-speed mode. 4. Set the CM06 bit to “1” (division by 8 mode) before transi ting from on-chip oscillator mode to high- or middle-speed mode. 5. When exiting stop mode, the CM0S6 bit is set to “1” (division by 8 mode). 6. If the CM05 bit set to “1” (main clock stop), t hen the CM06 bit is set to “1” (division by 8 mode). 7. A transition can be made only when sub clock is oscillating. 8. State transitions within the same mode (d ivide-by-n values changed or subclock oscillation turned on or off) are shown in the table below. −: Cannot transit 9. ( ) : setting method. See the following table. CM04, CM05, CM06, CM07 : Bits in CM0 register CM10, CM11, CM16, CM17 : Bits in CM1 register CM20, CM21 : Bits in CM2 register PLC07 : Bits in PLC0 register Table 10.8 Allowed Transition and Setting (9) State After Transition High-Speed Mode, Middle-Speed Mode Low-Speed Mode (2) Low Power Dissipation Mode PLL Operating Mode (2) On-chip Oscillator Mode On-chip Oscillator Low Power Dissipation Mode Stop Mode Wait Mode Current State High-Speed Mode, Middle-Speed Mode (NOTE 8) (9) (NOTE 7) - (13) (NOTE 1) (17) Low-Speed Mode(2) (8) (11) (NOTE 1) (17) Low Power Dissipation Mode − (10) −− − (16) (NOTE 1) (17) PLL Operating Mode(2) (12)(NOTE 3) −− − − − − On-chip Oscillator Mode (14) (NOTE 4) −− − (NOTE 8) (11) (NOTE 1) (16) (NOTE 1) (17) On-chip Oscillator Low Power Dissipation Mode (NOTE 1) (17) Stop Mode (18)(NOTE 5) (18) (18) − (18) (NOTE 5) (18)(NOTE 5) − Sub Clock Oscillating Sub Clock Turned Off No Division Divided by Divided by Divided by Divided by No Division Divided by Divided by Divided by Divided by Sub clock Oscillating No Division (4) (5) (7) (6) (1) −−−− Sub clock Turned Off No Division (2) −−−− (4) (5) (7) (6) Setting Operation Setting Operation (1) CM04 = 0 Sub clock turned off (10) CM05 = 0 Main clock oscillating (2) CM04 = 1 Sub clock oscillating (11) CM05 = 1 Main clock turned off (3) CM06 = 0, CM17 = 0, CM16 = 0 CPU clock no division mode (12) PLC07=0, CM11=0 Main clock selected (4) CM06 = 0, CM17 = 0, CM16 = 1 CPU clock division by 2 mode (13) PLC07=1, CM11=1 PLL clock selected (5) CM06 = 0, CM17 = 1, CM16 = 0 CPU clock division by 4 mode (14) CM21=0 Main clock or PLL clock selected (6) CM06 = 0, CM17 = 1, CM16 = 1 CPU clock division by 16 mode (15) CM21=1 On-chip oscillator clock selected (7) CM06 = 1 CPU clock division by 8 mode (16) CM10=1 Transition to stop mode (8) CM07 = 0 Main clock, PLL clock, or on-chip oscillator clock selected (17) Wait Instruction Transition to wait mode (9) CM07 = 1 Sub clock selected (18) Hardware Interrupt Exit stop mode or wait mode

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10.5 System Clock Protection Function

The system clock protection function prohibits the CPU clock from changing clock sources when the main clock is selected the CPU clock source. Th is prevents the CPU clock from stopping should the program crash. This function is available when the main clock is selected as the CPU clock source. When the PM21 bit in the PM2 register is set to “1” (clock change disabled), the following bits cannot be written to:

• The CM02 bit, CM05 bit and CM07 bit in the CM0 register
• The CM10 bit and CM11 bit in the CM1 register
• The CM20 bit in the CM2 register
• All bits in the PLC0 register When using the system clock protection function, set th e CM05 bit in the CM0 register to “0” (main clock oscillation) and CM07 bit to “0” (main clock as CPU clock source) and follow the procedure below. (1) Set the PRC1 bit in the PRCR register to “1” (write enable). (2) Set the PM21 bit in the PM2 regi ster to “1” (protects the clock). (3) Set the PRC1 bit in the PRCR register to “0” (write disable). When the PM21 bit is set to “1,” do not execute the WAIT instruction.

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10.6 Oscillation Stop and Re-o scillation Detect Function

The oscillation stop and re-oscillation de tect function is such that main clock oscillation circuit stop and re- oscillation are detected. At oscillation stop, re-oscilla tion detection, reset or os cillation stop, re-oscillation detection interrupt are generated. Which is to be generated can be selected using the CM27 bit in the CM2 register. The oscillation stop detection function can be enabled and disabled by the CM20 bit in the CM2 register. Table 10.9 lists a Specification Overview of Oscillation Stop and Re-Oscillation Detect Function.

10.6.1 Operation When CM 27 bit = 0 (Oscillation Stop Detection Reset)

Where main clock stop is detected when the CM20 bit is “1” (oscillation stop, re-oscillation detection function enabled), the microcomputer is initialized, coming to a halt (oscillation stop reset; refer to 4. Special Function Register (SFR), 5. Reset). This status is reset with hardware reset 1 or hardware reset 2. Also, even when re-oscillation is detected, the microcomputer can be initialized and stopped; it is, however, necessary to avoid such usage (During main clock stop, do not set the CM20 bit to “1” and the CM27 bit to “0”).

10.6.2 Operation When CM27 bit = 0 (O scillation Stop and Re-oscillation Detect

Interrupt) Where the main clock corresponds to the CPU clock source and the CM20 bit is “1” (oscillation stop and re- oscillation detect function enabled), the system is placed in the following state if the main clock comes to a halt:

• Oscillation stop and re-oscillation detect interrupt request occurs.
• The on-chip oscillator starts oscillation, and the on-chip oscillator clock becomes the clock source for CPU clock and peripheral functions in place of the main clock.
• CM21 bit = 1 (on-chip oscillator clock for CPU clock source and clock source of peripheral function.)
• CM22 bit = 1 (main clock stop detected)
• CM23 bit = 1 (main clock stopped) Where the PLL clock corresponds to the CPU clock source and the CM20 bit is “1,” the system is placed in the following state if the main clock comes to a halt: Since the CM21 bit remains unchanged, set it to “1” (on-chip oscillator clock) inside the interrupt routine.
• Oscillation stop and re-oscillation detect interrupt request occurs.
• CM22 bit = 1 (main clock stop detected)
• CM23 bit = 1 (main clock stopped)
• CM21 bit remains unchanged Where the CM20 bit is “1”, the system is placed in the following state if the main clock re-oscillates from the stop condition:
• Oscillation stop and re-oscillation detect interrupt request occurs.
• CM22 bit = 1 (main clock re-oscillation detected)
• CM23 bit = 0 (main clock oscillation)
• CM21 bit remains unchanged Table 10.9 Specification Overview of Oscill ation Stop and Re-Oscillation Detect Function Item Specification Oscillation Stop Detectable Clock and Frequency Bandwidth f(XIN)≥2 MHz Enabling Condition for Oscillation Stop, Re-Oscillation Detection Function Set CM20 bit to “1” (enable) Operation at Oscillation Stop, Re-Oscillation Detection
• Reset occurs (when CM27 bit =0)
• Oscillation stop, re-oscillation detection interrupt generated (when CM27 bit =1)

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10.6.3 How to Use Oscillation Stop and Re-oscillation Detect Function

• The oscillation stop and re-oscillation detect interrupt shares the vector with the watchdog timer interrupt and low voltage detection interrupt. If the oscilla tion stop, re-oscillation detection and watchdog timer interrupts both are used, read the CM22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt.
• Where the main clock re-oscillated after oscillation stop, the clock source for the CPU clock and peripheral functions must be switched to the main clock in th e program. Figure 10.12 shows the Procedure to Switch Clock Source From On-chip Oscillator to Main Clock.
• Simultaneously with oscillation stop, re-oscillation detection interrupt occurrence, the CM22 bit becomes “1”. When the CM22 bit is set at “1,” oscillation st op, re-oscillation detection interrupt are disabled. By setting the CM22 bit to “0” in the program, oscillation stop, re-oscillation detection interrupt are enabled.
• If the main clock stops during low speed mode where the CM20 bit is “1”, an oscillation stop, re-oscillation detection interrupt request is generated. At the same time, the on-chip oscillator star ts oscillating. In this case, although the CPU clock is derived from the sub cl ock as it was before th e interrupt occurred, the peripheral function clocks now are derived from the on-chip oscillator clock.
• To enter wait mode while using the oscillation stop, re -oscillation detection function, set the CM02 bit to “0” (peripheral function clocks not turned off during wait mode).
• Since the oscillation stop, re-oscillation detection func tion is provided in preparation for main clock stop due to external factors, set the CM20 bit to “0” (Oscillation stop, re-oscillation detection function disabled) where the main clock is stopped or os cillated in the program, that is where the stop mode is selected or the CM05 bit is altered.
• This function cannot be used if the main clock frequency is 2 MHz or less. In that case, set the CM20 bit to “0”. Figure 10.12 Procedure to Switch Clock Source From On-chip Oscillator to Main Clock Switch the main clock CM06 bit : Bit in CM0 register CM21 to CM23 bits : Bits in CM2 register NOTES: 1. If the clock source for CPU clock is to be changed to PLL clock, set to PLL operation mode after set to high-speed mode. YES NO Determine several times whether the CM23 bit is set to “0” (main clock oscillates) Set the CM06 bit to “1” (divide-by-8) Set the CM22 bit to “0” (main clock does not stop) Set the CM21 bit to “0” (main clock as CPU clock source)(1) End

M16C/62P Group (M16C/62P , M16C/62PT) 11. Protection Rev.2.41 Jan 10, 2006 Page 105 of 390 REJ09B0185-0241 11. Protection In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Figure 11.1 shows the PRCR Register. The following lists the regi sters protected by the PRCR register.

• The PRC0 bit protects the CM0, CM1, CM2, PLC0 and PCLKR registers;
• The PRC1 bit protects the PM0, PM1, PM2, TB2SC, INVC0 and INVC1 registers;
• The PRC2 bit protects the PD9, S3C and S4C registers;
• The PRC3 bit protects the VCR2 and D4INT registers. Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0” (write protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit to “1”. Make sure no interrupts or DMA transfers will occu r between the instruction in which the PRC2 bit is set to “1” and the next instruction. The PRC0, PRC1 and PRC3 b its are not automatically cleared to “0” by writing to any address. They can only be cleared in a program. Figure 11.1 PRCR Register Protect Register Symbol Address After Reset PRCR 000Ah XX000000b Bit Symbol Bit Name Function RW NOTES : PRC3 Protect Bit 3 Enable w rite to VCR2 and D4INT registers 0 : Write protected 1 : Write enabled RW Protect Bit 0 Enable w rite to CM0, CM1, CM2, PLC0 and PCLKR registers 0 : Write protected 1 : Write enabled (b5-b4) RW PRC0 RW PRC2 Protect Bit 2 Enable w rite to PD9, S3C and S4C registers 0 : Write protected 1 : Write enabled (1) RW b7 b6 b5 b4 b3 b2 b1 b0 The PRC2 bit is set to “0” by w riting to any address after setting it to “1”. Other bits are not set to “0” by w riting to any address, and must therefore be set in a program. Reserved Bit Set to “0” PRC1 RW Protect Bit 1 Enable w rite to PM0, PM1, PM2, TB2SC, INVC0 and INVC1 registers 0 : Write protected 1 : Write enabled (b7-b6) —Nothing is assigned. When w rite, set to “0”. When read, their contents are indeterminate. The M16C/62PT do not use the PRC3 bit in the PRCR register. Note

M16C/62P Group (M16C/62P , M16C/62PT) 12. Interrupt Rev.2.41 Jan 10, 2006 Page 106 of 390 REJ09B0185-0241 12. Interrupt

12.1 Type of Interrupts

Figure 12.1 shows Type of Interrupts. Figure 12.1 Type of Interrupts

• Maskable Interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level.
• Non-Maskable Interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level. Interrupt Software (Non-maskable interrupt) Hardware Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Special (Non-maskable interrupt) Peripheral function (1) (Maskable interrupt) NOTES: 1. The peripheral functions in the microcomputer are used to generate the peripheral interrupt. 2. Do not normally use this interrupt because it is provided exclusively for use by development tools. NMI DBC (2) Watchdog timer Oscillation stop and re-oscillation detection Low voltage detection Single step (2) Address match The M16C/62P (80-pin version) do not use INT3 to INT5 interrupt of peripheral function. The M16C/62PT (100-pin version) do not use low voltage detection interrupt. The M16C/62PT (80-pin version) do not use low voltage detection interrupt and INT3 to INT5 interrupt of peripheral function. Note

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12.2 Software Interrupts

A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts.

12.2.1 Undefined Instruction Interrupt

An undefined instruction interrupt occurs when executing the UND instruction.

12.2.2 Overflow Interrupt

An overflow interrupt occurs when executing the INTO instruction with the O flag in the FLG register set to “1” (the operation resulted in an overflow). The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV , DIVU, DIVX, NEG , RMPA, SBB, SHA, SUB

12.2.3 BRK Interrupt

A BRK interrupt occurs when executing the BRK instruction.

12.2.4 INT Instruction Interrupt

An INT instruction interrupt occurs when executing the INT instruction. Software interrupt Nos. 0 to 63 can be specified for the INT instruct ion. Because software interrupt Nos. 4 to 31 are assigned to peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be executed by executing the INT instruction. In software interrupt Nos. 0 to 31, the U flag is save d to the stack during instruction execution and is cleared to “0” (ISP selected) before executing an interrupt sequence. The U flag is restored from the stack when returning from the interrupt routine. In software interrupt Nos. 32 to 63, the U flag does not change state during instruction execution, and the SP then selected is used.

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12.3 Hardware Interrupts

Hardware interrupts are classified into two types − special interrupts and peripheral function interrupts.

12.3.1 Special Interrupts

Special interrupts are non-maskable interrupts.

12.3.1.1 NMI Interrupt

An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details about the NMI interrupt, refer to the 12.7 NMI Interrupt.

12.3.1.2 DBC Interrupt

Do not normally use this interrupt because it is provided exclusively for use by development tools.

12.3.1.3 Watchdog Timer Interrupt

Generated by the watchdog timer. Once a watchdog timer in terrupt is generated, be sure to initialize the watchdog timer. For details about the watchdog timer, refer to the 13. Watchdog Timer.

12.3.1.4 Oscillation Stop and Re -oscillation Detection Interrupt

Generated by the oscillation stop and re-oscillation detection function. For details about the oscillation stop and re-oscillation detection function, refer to the 10. Clock Generation Circuit. Generated by the voltage detection circuit. For details about the voltage detection circuit, refer to the 6. Voltage Detection Circuit.

12.3.1.6 Single-Step Interrupt

Do not normally use this interrupt because it is provided exclusively for use by development tools.

12.3.1.7 Address Match Interrupt

An address match interrupt is generated immediately befo re executing the instruction at the address indicated by the RMAD0 to RMAD3 register that corresponds to on e of the AIER0 or AIER1 bit in the AIER register or the AIER20 or AIER21 bit in the AIER2 register whic h is “1” (address match interrupt enabled). For details about the address match interrupt, refer to the 12.9 Address Match Interrupt.

12.3.2 Peripheral Function Interrupts

The peripheral function interrupt occu rs when a request from the peripheral functions in the microcomputer is acknowledged. The peripheral function interrupt is a maskable interrupt. See Table 12.2 Relocatable Vector Tables about how the peripheral function interrupt occurs. Refer to the descriptions of each function for details.

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12.4 Interrupts and Interrupt Vector

One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the addr ess set in the corresponding interrupt vector. Figure 12.2 shows the Interrupt Vector. Figure 12.2 Interrupt Vector

12.4.1 Fixed Vector Tables

The fixed vector tables are allocated to the addresses from FFFDCh to FFFFFh. Table 12.1 lists the Fixed Vector Tables. In the flash memory version of microcomputer, the vector addresses (H) of fixed vectors are used by the ID code check function. For details, refer to the 22.2 Functions To Prevent Flash Memory from Rewriting. NOTES: 1. Do not normally use this interr upt because it is provided exclusively for use by development tools. 2. If the contents of address FFFE7h is FFh, progra m execution starts from the address shown by the vector in the relocatable vector table. Table 12.1 Fixed Vector Tables Interrupt Source Vector Table Addresses Address (L) to Address (H) Reference Undefined Instruction (UND instruction) FFFDCh to FFFDFh M16C/60, M16C/20 Series software manualOverflow (INTO instruction) FFFE0h to FFFE3h BRK Instruction (2) FFFE4h to FFFE7h Address Match FFFE8h to FFFEBh 12.9 Address Match Interrupt Single Step (1) FFFECh to FFFEFh Watchdog Timer, Oscillation Stop and Re-Oscillation Detection, Low Voltage Detection FFFF0h to FFFF3h 13. Watchdog Timer 10. Clock Generation Circuit 6. Voltage Detection Circuit DBC (1) FFFF4h to FFFF7h NMI FFFF8h to FFFFBh 12.7 NMI interrupt Reset FFFFCh to FFFFFh 5. Reset Middle-order address Low-order address 0 0 0 0 High-order address 0 0 0 0 0 0 0 0 Vector address (L) LSBMSB Vector address (H)

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12.4.2 Relocatable Vector Tables

The 256 bytes beginning with the start address set in th e INTB register comprise a reloacatable vector table area. Table 12.2 lists the Relocatable Vector Tables. Setting an even address in the INTB register results in the interrupt sequence being executed faster than in the case of odd addresses. NOTES: 1. Address relative to address in INTB. 2. Use the IFSR6 and IFSR7 bits in the IFSR register to select. 3. During I 2C mode, NACK and ACK interrupts comprise the interrupt source. 4. Use the IFSR26 and IFSR27 bits in the IFSR2A register to select. 5. These interrupts cannot be disabled using the I flag. 6. Bus collision detection : During IE mode, this bus co llision detection constitutes the factor of an interrupt. During I 2C mode, however, a start condition or a stop condition detection constitutes the factor of an interrupt. Table 12.2 Relocatable Vector Tables Interrupt Source Vector Address (1) Address (L) to Address (H) Software Interrupt Number Reference BRK Instruction (5) +0 to +3 (0000h to 0003h) 0 M16C/60, M16C/20 Series software manual−(Reserved) 1 to 3 INT3 +16 to +19 (0010h to 0013h) 4 12.6 INT interrupt Timer B5 +20 to +23 (0014h to 0017h) 5 15. Timers Timer B4, UART1 Bus Collision Detect (4, 6) +24 to +27 (0018h to 001Bh) 6 15. Timers 17. Serial InterfaceTimer B3, UART0 Bus Collision Detect (4, 6) +28 to +31 (001Ch to 001Fh) 7 SI/O4, INT5 (2) +32 to +35 (0020h to 0023h) 8 12.6 INT interrupt 17. Serial InterfaceSI/O3, INT4 (2) +36 to +39 (0024h to 0027h) 9 UART 2 Bus Collision Detection (6) +40 to +43 (0028h to 002Bh) 10 17. Serial Interface DMA0 +44 to +47 (002Ch to 002Fh) 11 14. DMAC DMA1 +48 to +51 (0030h to 0033h) 12 Key Input Interrupt +52 to +55 (0034h to 0037h) 13 12.8 Key Input Interrupt A/D +56 to +59 (0038h to 003Bh) 14 18. A/D Converter UART2 Transmit, NACK2 (3) +60 to +63 (003Ch to 003Fh) 15 17. Serial Interface UART2 Receive, ACK2 (3) +64 to +67 (0040h to 0043h) 16 UART0 Transmit, NACK0 (3) +68 to +71 (0044h to 0047h) 17 UART0 Receive, ACK0 (3) +72 to +75 (0048h to 004Bh) 18 UART1 Transmit, NACK1 (3) +76 to +79 (004Ch to 004Fh) 19 UART1 Receive, ACK1 (3) +80 to +83 (0050h to 0053h) 20 Timer A0 +84 to +87 (0054h to 0057h) 21 15. Timers Timer A1 +88 to +91 (0058h to 005Bh) 22 Timer A2 +92 to +95 (005Ch to 005Fh) 23 Timer A3 +96 to +99 (0060h to 0063h) 24 Timer A4 +100 to +103 (0064h to 0067h) 25 Timer B0 +104 to +107 (0068h to 006Bh) 26 Timer B1 +108 to +111 (006Ch to 006Fh) 27 Timer B2 +112 to +115 (0070h to 0073h) 28 INT0 +116 to +119 (0074h to 0077h) 29 12.6 INT interrupt INT1 +120 to +123 (0078h to 007Bh) 30 INT2 +124 to +127 (007Ch to 007Fh) 31 Software Interrupt (5) +128 to +131 (0080h to 0083h) to +252 to +255 (00FCh to 00FFh) to M16C/60, M16C/20 Series software manual

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12.5 Interrupt Control

The following describes how to enable/d isable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to nonmaskable interrupts. Use the I flag in the FLG register, IPL, and ILVL2 to ILVL 0 bits in the each interrupt control register to enable/ disable the maskable interrupts. Whether an interrupt is re quested is indicated by the IR bit in the each interrupt control register. Figure 12.3 and Figure 12.4 show the Interrupt Control Registers. Figure 12.3 Interrupt Control Registers (1) Interrupt Control Register (2) Symbol Address After Reset TB5IC 0045h XXXXX000b TB4IC/U1BCNIC(3) 0046h XXXXX000b TB3IC/U0BCNIC(3) 0047h XXXXX000b BCNIC 004Ah XXXXX000b DM0IC, DM1IC 004Bh, 004Ch XXXXX000b KUPIC 004Dh XXXXX000b AD I C 004Eh XXXXX000b S0TIC to S2TIC 0051h, 0053h, 004Fh XXXXX000b S0RIC to S2RIC 0052h, 0054h, 0050h XXXXX000b TA0IC to TA4IC 0055h to 0059h XXXXX000b TB0IC to TB2IC 005Ah to 005Ch XXXXX000b Bit Symbol Function RW NOTES : 3. Use the IFSR2A register to select. Bit Name Interrupt Priority Level Select Bit Interrupt Request Bit Nothing is assigned. When w rite, set to “0”. When read, their contents are indeterminate. (b7-b4) — This bit can only be reset by w riting “0” (Do not w rite “1”). IR 0 : Interrupt not requested 1 : Interrupt requested RW(1) RW b2 b1 b0 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 ILV L1 RW ILV L2 RW ILV L0 To rew rite the interrupt control registers, do so at a point that does not generate the interrupt request for that register. For details, refer to 24.6 Interrupt . b7 b6 b5 b4 b3 b2 b1 b0

M16C/62P Group (M16C/62P , M16C/62PT) 12. Interrupt Rev.2.41 Jan 10, 2006 Page 112 of 390 REJ09B0185-0241 Figure 12.4 Interrupt Control Registers (2) INTi (0 to 5) Interrupt Control Register (2) Symbol Address After Reset INT3IC (4) 0044h XX00X000b S4IC/INT5IC 0048h XX00X000b S3IC/INT4IC 0049h XX00X000b INT0IC to INT2IC 005Dh to 005Fh XX00X000b Bit Symbol Function RW NOTES : When the BYTE pin is low and the processor mode is memory expansion or microprocessor mode, set the LVL2 to ILV L0 Set the POL bit in the S3IC or S4IC register to “0” (falling edge) w hen the IFSR6 bit in the IFSR register = 0 (SI/O3 selected) or IFSR7 bit = 0 (SI/O4 selected), respectively. Bit Name b7 b6 b5 b4 b3 b2 b1 b0 ILV L0 RW b2 b1 b0 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 ILV L1 RW ILV L2 RW Interrupt Priority Level Select Bit IR 0: Interrupt not requested 1: Interrupt requested RW (1)Interrupt Request Bit POL 0 : Selects falling edge (3, 5) 1 : Selects rising edge RWPolarity Select Bit (b5) Set to “0” RWReserved Bit This bit can only be reset by w riting “0” (Do not w rite “1”). To rew rite the interrupt control register, do so at a point that does not generate the interrupt request for that register. For details, refer to 24.6 Interrupt . If the IFSRi bit (i = 0 to 5) in the IFSR register are “1” (both edges), set the POL bit in the INTiIC register to “0” (falling edge). (b7-b6) —Nothing is assigned. When w rite, set to “0”. When read, their contents are indeterminate.

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12.5.1 I Flag

The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the maskable interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts.

12.5.2 IR Bit

The IR bit is set to “1” (= interrupt requested) when an interrupt request is generated. Then, when the interrupt request is accepted and the CPU branches to the corresponding inte rrupt vector, the IR bit is cleared to “0” (= interrupt not requested). The IR bit can be cleared to “0” in a program. Note that do not write “1” to this bit.

12.5.3 ILVL2 to ILVL0 Bits and IPL

Interrupt priority levels can be set using the ILVL2 to ILVL0 bits. Table 12.3 shows the Settings of Interrupt Priority Le vels and Table 12.4 shows the Interrupt Priority Levels Enabled by IPL. The following are conditions under which an interrupt is accepted:

• I flag = 1
• IR bit = 1
• interrupt priority level > IPL The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are inde pendent of each other. In no case do they affect one another. Table 12.3 Settings of Interrupt Priority Levels ILVL2 to ILVL0 Bits Interrupt Priority Level Priority Order 000b Level 0 (interrupt disabled) − 001b Level 1 Low 010b Level 2 011b Level 3 100b Level 4 101b Level 5 110b Level 6 111b Level 7 High Table 12.4Interrupt Priority Levels Enabled by IPL IPL Enabled Interrupt Priority Levels 000b Interrupt levels 1 and above are enabled 001b Interrupt levels 2 and above are enabled 010b Interrupt levels 3 and above are enabled 011b Interrupt levels 4 and above are enabled 100b Interrupt levels 5 and above are enabled 101b Interrupt levels 6 and above are enabled 110b Interrupt levels 7 and above are enabled 111b All maskable interrupts are disabled

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12.5.4 Interrupt Sequence

An interrupt sequence − what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed − is described here. If an interrupt occurs du ring execution of an instruction, the pro cessor determines its priority when the execution of the instruction is completed, and transfers control to the interr upt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. The CPU behavior during the interrupt sequence is de scribed below. Figure 12.5 shows Time Required for Executing Interrupt Sequence. (1) The CPU obtains interrupt information (interrupt nu mber and interrupt request level) by reading address 000000h. Then, the IR bit applicable to the interrupt information is set to “0” (interrupt requested). (2) The FLG register, prior to an interrupt sequence, is saved to a temporary register (1) within the CPU. (3) The I, D and U flags in the FLG register become as follows:

• The I flag is set to “0” (interrupt disabled)
• The D flag is set to “0” (single-step interrupt disabled)
• The U flag is set to “0” (ISP selected) However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is executed. (4) The temporary register (1) within the CPU is saved to the stack. (5) The PC is saved to the stack. (6) The interrupt priority level of the acknowledged interrupt in IPL is set. (7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC. After the interrupt sequence is completed, an instruc tion is executed from the starting address of the interrupt routine. NOTES: 1.Temporary register cannot be modified by users. Figure 12.5 Time Required for Executing Interrupt Sequence Indeterminate(1) 123456789 1 0 1 1 12 13 14 15 16 17 18 Indeterminate(1) SP-2

contents

0000h Indeterminate(1) SP-2 SP-4 vec vec+2 PC CPU clock Address bus Data bus WR(2) RD NOTES : 1. The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is ready to accept instructions. 2. The WR signal timing shown here is for the case where the stack is located in the internal RAM.

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12.5.5 Interrupt Response Time

Figure 12.6 shows the Interrupt Response Time. The interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed. Specifically, it consists of a time from when an interrupt request is generated till when the instruction then executing is completed ((a) on Figure 12.6) and a time during which the interrupt sequence is executed ((b) on Figure 12.6). Figure 12.6 Interrupt Response Time

12.5.6 Variation of IPL when In terrupt Request is Accepted

When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed in Table 12.5 is set in the IPL. Table 12.5 lists the IPL Level That is Set to IPL Wh en a Software or Special Interrupt is Accepted. Table 12.5 IPL Level That is Set to IPL When a Software or Special Interrupt is Accepted Interrupt Sources Level that is Set to IPL Watchdog Timer, NMI, Oscillation Stop and Re-Oscillation Detection, Low Voltage Detection Software, Address Match, DBC, Single-Step Not changed Instruction Interrupt sequence Instruction in interrupt routine Time Interrupt response time (a) (b) Interrupt request acknowledgedInterrupt request generated (a) A time from when an interrupt request is generated till when the instruction then executing is completed. The length of this time varies with the instruction being executed. The DIVX instruction requires the longest time, which is equal to 30 cycles (without wait state, the divisor being a register). (b) A time during which the interrupt sequence is executed. For details, see the table below. Note, however, that the values in this table must be increased 2 cycles for the DBC interrupt and 1 cycle for the address match and single-step interrupts. Interrupt Vector Address Even Even Odd Odd SP Value 16-Bit Bus, Without Wait 18 cycles 19 cycles 19 cycles 20 cycles 8-Bit Bus, Without Wait 20 cycles 20 cycles 20 cycles 20 cycles Even Odd Even Odd

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12.5.7 Saving Registers

In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure 12.7 shows the Stack Status Before and After Acceptance of Interrupt Request. The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use the PUSHM instruction, and all registers except SP can be saved with a single instruction. Figure 12.7 Stack Status Before and After Acceptance of Interrupt Request Address Content of previous stack Stack [SP] SP value before interrupt request is accepted. m m − 1 m − 2 m − 3 m − 4 Stack status before interrupt request is acknowledged Stack status after interrupt request is acknowledged Content of previous stackm + 1 MSB LSB m m − 1 m − 2 m − 3 m − 4 Address FLGL Content of previous stack Stack FLGH PCH [SP] New SP value Content of previous stackm + 1 MSB LSB PCL PCM PCH : 4 high-order bits of PC PCM : 8 middle-order bits of PC PCL : 8 low-order bits of PC FLGH : 4 high-order bits of FLG FLGL : 8 low-order bits of FLG

M16C/62P Group (M16C/62P , M16C/62PT) 12. Interrupt Rev.2.41 Jan 10, 2006 Page 117 of 390 REJ09B0185-0241 The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP (1), at the time of acceptance of an interrupt request , is even or odd. If the stack pointer (1) is even, the FLG register and the PC are saved,16 bits at a time. If odd, they are save d in two steps, 8 bits at a time. Figure 12.8 shows the Operation of Saving Register. NOTES: 1.When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated by the U flag. Otherwise, it is the ISP. Figure 12.8 Operation of Saving Register (2) SP contains odd number [SP] (Odd) [SP] − 1 (Even) [SP] − 2(Odd) [SP] − 3 (Even) [SP] − 4(Odd) [SP] − 5 (Even) Address Sequence in which order registers are saved (2) (1) Finished saving registers in four operations. (3) (4) (1) SP contains even number [SP] (Even) [SP] − 1(Odd) [SP] − 2 (Even) [SP] − 3(Odd) [SP] − 4 (Even) [SP] − 5 (Odd) NOTES : 1. [SP] denotes the initial value of the SP when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. Address PCM Stack FLGL PCL Sequence in which order registers are saved (2) Saved simultaneously, all 16 bits (1) Saved simultaneously, all 16 bits Finished saving registers in two operations. PCM Stack FLGL PCL Saved, 8 bits at a time PCH : 4 high-order bits of PC PCM : 8 middle-order bits of PC PCL : 8 low-order bits of PC FLGH : 4 high-order bits of FLG FLGL : 8 low-order bits of FLG FLGH FLGH PCH PCH

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12.5.8 Returning from an Interrupt Routine

The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine. Thereafter the CPU returns to the program which was being executed before accepting the interrupt request. Return the other registers saved by a program within the interrupt routine using the POPM or similar instruction before executing the REIT instruction. Register bank is switched back to the bank used prior to the interrupt sequence by the REIT instruction.

12.5.9 Interrupt Priority

If two or more interrupt requests are sampled at th e same sampling points (a timing to detect whether an interrupt request is generated or not), the interrupt with the highest priority is acknowledged. For maskable interrupts (peripheral functions interrupt), any desired priority level can be selected using the ILVL2 to ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware, with the highest priority interrupt accepted. The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 12.9 shows the Hardware Interrupt Priority. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine. Figure 12.9 Hardware Interrupt Priority Reset Watchdog Timer Oscillation Stop and Re-Oscillation Detection, Low Voltage Detection Peripheral Function Single Step Address Match High Low NMI DBC

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12.5.10 Interrupt Priority Level Select Circuit

The interrupt priority level select circuit selects the highest priority interrupt when two or more interrupt requests are sampled at the same sampling point. Figure 12.10 shows the Interrupts Priority Select Circuit. Figure 12.10 Interrupts Priority Select Circuit Timer A2 UART1 reception, ACK1 UART0 reception, ACK0 UART2 reception, ACK2 A/D conversion DMA1 UART 2 bus collision SI/O4, INT5 UART1 transmission, NACK1 UART0 transmission, NACK0 UART2 transmission, NACK2 Key input interrupt DMA0 IPL I flag Watchdog timer DBC NMI Interrupt request accepted Lowest Priority of peripheral function interrupts (if priority levels are same) Timer B3, UART0 bus collision Address match Interrupt request level resolution output to clock generating circuit (Figure 10.1 Clock Generation Circuit) SI/O, INT4 Timer B1 INT2 INT0 Timer B4, UART1 bus collision INT3 Timer B2 Timer B0 Timer A3 INT1 Level 0 (initial value)Priority level of each interrupt Highest Timer A1 Timer A4 Timer B5 Timer A0 Oscillation stop and re-oscillation detection Low voltage detection

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12.6 INT Interrupt

INTi interrupt (i=0 to 5) is triggered by the edges of exte rnal inputs. The edge polarity is selected using the IFSRi bit in the IFSR register. INT4 and INT5 share the interrupt vector and in terrupt control register with SI/O3 and SI/O4, respectively. To use the INT4 interrupt, set the IFSR6 bit in the IFSR register to “1” (= INT4). To use the INT5 interrupt, set the IFSR7 bit in the IFSR register to “1” (= INT5). After modifying the IFSR6 or IFSR7 bit, clear the corresponding IR bit to “0” (= interr upt not requested) before enabling the interrupt. Figure 12.11 shows the IFSR and IFSR2A Registers. Figure 12.11 IFSR and IFSR2A Registers Interrupt Factor Select Register Symbol Address After R eset IFSR 035Fh 00h Bit Symbol Bit Name Function RW 0 : SI/O3 (3) 1 : INT4 0 : SI/O4 (3) 1 : INT5 NOTES : 3. When setting this bit to “0” (= SI/O3, SI/O4), make sure the POL bit in the S3IC and S4IC registers are set to “0” (= falling edge). I NT2 I nterrupt P olarity Sw itching Bit 0 : One edge 1 : Both edges (1) RW 0 : One edge 1 : Both edges (1) During memory expansion and microprocessor modes, w hen the data bus is 16 bits w ide (BYTE pin is "L"), set this bit to “0” (= SI/O3, SI/O4). 0 : One edge 1 : Both edges (1) I NT4 I nterrupt P olarity Sw itching Bit IFSR6 When setting this bit to “1” (= both edges), make sure the POL bit in the INT0IC to INT5IC register are set to “0” (= falling edge). IFSR7 RW RW IFSR0 Interrupt Request Factor Select Bit (2) IFSR3 I NT3 I nterrupt P olarity Sw itching Bit IFSR5 I NT5 I nterrupt P olarity Sw itching Bit IFSR4 b3 b2 b1 b0b7 b6 b5 b4 RW IFSR1 RW IFSR2 RW0 : One edge 1 : Both edges (1) INT0 Interrupt Polarity Sw itching Bit 0 : One edge 1 : Both edges (1) I NT1 I nterrupt P olarity Sw itching Bit 0 : One edge 1 : Both edges (1) RW Interrupt Request Factor Select Bit (2) RW Interrupt Factor Select Register 2 Symbol Address After Reset IFSR2A 035Eh 00XXXXXXb Bit Symbol Bit Name Function RW NOTES : Timer B3 and UART0 bus collision detection share the vector and interrupt control register. When using Timer B3 interrupt, clear the IFSR26 bit to “0” (Timer B3). When using UART0 bus collision detection, set the IFSR26 bit to “1”. Timer B4 and UART1 bus collision detection share the vector and interrupt control register. When using Timer B4 interrupt, clear the IFSR27 bit to “0” (Timer B4). When using UART1 bus collision detection, set the IFSR27 bit to “1”. Nothing is assigned. When w rite, set to “0”. When read, their contents are indeterminate. b3 b2 b0b7 b6 b5 b4 IFSR27 0 : Timer B3 1 : UART0 bus collision detection RW (b5-b0) — IFSR26 RW 0 : Timer B4 1 : UART1 bus collision detection Interrupt Request Factor Select Bit (2) Interrupt Request Factor Select Bit (1)

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12.7 NMI Interrupt

An NMI interrupt is generated when input on the NMI pin changes state from high to low. The NMI interrupt is a non-maskable interrupt. The input level of this NMI interrupt input pin can be read by accessing the P8_5 bit in the P8 register. This pin cannot be used as an input port.

12.8 Key Input Interrupt

Of P10_4 to P10_7, a key input interrupt is generated when input on any of the P10_4 to P10_7 pins which has had the PD10_4 to PD10_7 bits in the PD10 register set to “0” (= input) goes low. Key input interrupts can be used as a key-on wake up function, the function which gets the microcomputer out of wait or stop mode. However, if you intend to use the key input interrupt, do not use P10_4 to P10_7 as analog input ports. Figure 12.12 shows the block diagram of the Key Input Interrupt. Note, however, that while input on any pin which has had the PD10_4 to PD10_7 bits set to “0” (= input mode) is pulled low, i nputs on all other pins of the port are not detected as interrupts. Figure 12.12 Key Input Interrupt Interrupt control circuit KUPIC register Key input interrupt request Pull-up transistor Pull-up transistor Pull-up transistor Pull-up transistor PU25 bit in PUR2 register PD10_7 bit in PD10 register PD10_7 bit in PD10 register PD10_6 bit in PD10 register PD10_5 bit in PD10 register PD10_4 bit in PD10 register KI3 KI2 KI1 KI0

M16C/62P Group (M16C/62P , M16C/62PT) 12. Interrupt Rev.2.41 Jan 10, 2006 Page 122 of 390 REJ09B0185-0241

12.9 Address Match Interrupt

An address match interrupt is generated immediately befo re executing the instruction at the address indicated by the RMADi register (i=0 to 3). Set th e start address of any in struction in the RMADi re gister. Use the AIER0 and AIER1 bits in the AIER register and AIER20 and AIER21 bits in the AIER2 register to enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag and IPL. For address match interrupts, the value of the PC that is saved to the stack area va ries depending on the instruction being executed (refer to 12.5.7 Saving Registers). (The value of the PC that is saved to the stack area is not the correct return address.) Therefore, follow one of the methods described below to return from the address match interrupt.

• Rewrite the content of the stack and then use the REIT instruction to return.
• Restore the stack to its previous st ate before the interrupt request wa s accepted by using the POP or similar other instruction and then use a jump instruction to return. Table 12.6 shows the Value of the PC that is Saved to the Stack Area when an Address Match Interrupt Request is Accepted Figure 12.13 shows the AIER, AIER2 and RMAD0 to RMAD3 Registers. Value of the PC that is saved to the stack area : Refer to 12.5.7 Saving Registers. Table 12.6 Value of the PC that is Saved to the Stack Area when an Address Match Interrupt Request is Accepted Instruction at the Address Indicated by the RMADi Register Value of the PC that is saved to the stack area
• 16-bit op-code instruction
• Instruction shown below among 8-bit operation code instructions ADD.B:S #IMM8,dest SUB.B:S #I MM8,dest AND.B:S #IMM8,dest OR.B:S #IMM8,dest MOV.B:S #I MM8,dest STZ.B:S #IMM8,dest STNZ.B:S #IMM8,dest STZX .B:S #IMM81,#IMM82,dest CMP.B:S #IMM8,dest PUSHM src POPM dest JMPS #IMM8 JSRS #IMM8 MOV.B:S #IMM,dest (However, dest=A0 or A1) The address indicated by the RMADi register +2 Instructions other than the above The address indicated by the RMADi register +1 Table 12.7 Relationship Between Address Match Interrupt Sources and Associated Registers Address Match Interrupt sources Address Match Inte rrupt Enable Bit Address Match Interrupt Register Address Match Interrupt 0 AIER0 RMAD0 Address Match Interrupt 1 AIER1 RMAD1 Address Match Interrupt 2 AIER20 RMAD2 Address Match Interrupt 13 AIER21 RMAD3

M16C/62P Group (M16C/62P , M16C/62PT) 12. Interrupt Rev.2.41 Jan 10, 2006 Page 123 of 390 REJ09B0185-0241 Figure 12.13 AIER, AIER2 and RMAD0 to RMAD3 Registers Address Match Interrupt Enable Register Symbol Address After Reset AI E R 0009h XXXXXX00b Bit Symbol Bit Name Function RW Nothing is assigned. When w rite, set to “0”. When read, their contents are indeterminate. Address Match Interrupt 0 Enable Bit 0 : Interrupt disabled 1 : Interrupt enabled b3 b2 b1 b0b7 b6 b5 b4 (b7-b2) 0 : Interrupt disabled 1 : Interrupt enabled AI E R 0 RW AI E R 1 RWAddress Match Interrupt 1 Enable Bit Address Match Interrupt Enable Register 2 Symbol Address After Reset AI E R 2 01BBh XXXXXX00b Bit Symbol Bit Name Function RW Nothing is assigned. When w rite, set to “0”. When read, their contents are indeterminate. Address Match Interrupt 2 Enable Bit 0 : Interrupt disabled 1 : Interrupt enabled b3 b2 b1 b0b7 b6 b5 b4 (b7-b2) 0 : Interrupt disabled 1 : Interrupt enabled AI E R 20 RW AI E R 21 RWAddress Match Interrupt 3 Enable Bit Address Match Interrupt Register i (i = 0 to 3) Symbol Address After Reset RMA D0 0012h to 0010h X00000h RMA D1 0016h to 0014h X00000h RMA D2 01BAh to 01B8h X00000h RMA D3 01BEh to 01BCh X00000h Setting Range RW Nothing is assigned. When w rite, set to “0”. When read, their contents are indeterminate. b0b7 (b16) (b19) (b23) (b15) (b8) RW Function Address setting register for address match interrupt 00000h to FFFFFh

M16C/62P Group (M16C/62P , M16C/62PT) 13. Watchdog Timer Rev.2.41 Jan 10, 2006 Page 125 of 390 REJ09B0185-0241 Figure 13.2 WDC and WDTS Register

13.1 Count source protective mode

In this mode, a on-chip oscillator clock is used for the watchdog timer count source. The watchdog timer can be kept being clocked even when CPU clock stops as a result of run-away. Before this mode can be used, the following register settings are required: (1) Set the PRC1 bit in the PRCR register to “1” (enable writes to PM1 and PM2 registers). (2) Set the PM12 bit in the PM1 register to “1” (reset when the watchdog timer underflows). (3) Set the PM22 bit in the PM2 register to “1” (on-chip oscillator clock used for the watchdog timer count source). (4) Set the PRC1 bit in the PRCR register to “0” (disable writes to PM1 and PM2 registers). (5) Write to the WDTS register (watchdog timer starts counting). Setting the PM22 bit in the PM register to “1” results in the following conditions.

• The on-chip oscillator starts oscillating, and the on -chip oscillator clock becomes the watchdog timer count source.
• The CM10 bit in the CM1 register is disabled agains t write (Writing a “1” has no effect, nor is stop mode entered).
• The watchdog timer does not stop when in wait mode or hold state. Watchdog timer period = Watchdog timer count (32768) On-chip oscillator clock Watchdog Timer Control Register Symbol Address After Reset WDC 000Fh 00XXXXXXb (2) Bit Symbol Bit Name Function RW NOTES : WDC5 RW (b4-b0) ROHigh-order Bit of Watchdog Timer Cold Start / Warm Start Discrimination Flag (1, 2) 0 : Cold Start 1 : Warm Start b7 b6 b5 b4 b3 b2 b1 b0 The WDC5 bit is set to “0” (cold start) w hen pow er is turned on and can be set to “1” by program only. WDC7 (b6) Reserved Bit Set to “0” Prescaler Select Bit 0 : Divided by 16 1 : Divided by 128 RW RW Writing to the WDC register factors the WDC5 bit to be set to “1” (w arm start). If the voltage applied to VCC1 is less than 4.0 V, either w rite to this register w hen the CPU clock frequency is 2 MHz or w rite tw ice. Watchdog Timer Start Register (1) Symbol Address After Reset WDTS 000Eh Indeterminate RW NOTES : Function The w atchdog timer is initialized and starts counting after a w rite instruction to this register. The w atchdog timer value is alw ays initialized to “7FFFh” regardless of w hatever value is w ritten. b0b7 Write to the WDTS register after the w atchdog timer interrupt occurs. WO

M16C/62P Group (M16C/62P , M16C/62PT) 14. DMAC Rev.2.41 Jan 10, 2006 Page 126 of 390 REJ09B0185-0241 14. DMAC The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention. Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit) data from the source address to the destination a ddress. The DMAC uses the same data bus as used by the CPU. Because the DMAC has higher priority of bus control than the CPU and because it makes use of a cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time after a DMA request is generated. Figure 14.1 related registers. Figure 14.1 DMAC Block Diagram A DMA request is generated by a write to the DSR bit in the DMiSL register (i = 0 to 1), as well as by an interrupt request which is generated by any fu nction specified by the DMS and DSEL3 to DSEL0 bits in the DMiSL register. However, unlike in the case of interrupt requests, DMA requests are not affected by the I flag and the interrupt control register, so that even when interrupt requests are disabled and no interrupt request can be accepted, DMA requests are always accepted. Furthermore, because the DMAC does not affect interrupts, the IR bit in the interrupt control register does not change state due to a DMA transfer. A data transfer is initiated each time a DMA request is generated when the DMAE bit in the DMiCON register = 1 (DMA enabled). However, if the cycle in which a DMA request is generated is faster than the DMA transfer cycle, the number of transfer requests generated and the number of times data is transferred may not match. Refer to 14.4 DMA Request for details. NOTES : 1. Pointer is incremented by a DMA request. Address bus Data bus low-order bits Data bus high-order bits DMA latch high-order bits DMA latch low-order bits DMA0 source pointer SAR0(20) DMA0 destination pointer DAR0 (20) DMA0 forward address pointer (20) (1) DMA1 destination pointer DAR1 (20) DMA1 source pointer SAR1 (20) DMA1 forward address pointer (20) (1) (addresses 0022h to 0020h) (addresses 0026h to 0024h) (addresses 0032h to 0030h) (addresses 0036h to 0034h) DMA0 transfer counter reload register TCR0 (16) DMA0 transfer counter TCR0 (16) DMA1 transfer counter reload register TCR1 (16) DMA1 transfer counter TCR1 (16) (addresses 0029h, 0028h) (addresses 0039h, 0038h)

M16C/62P Group (M16C/62P , M16C/62PT) 14. DMAC Rev.2.41 Jan 10, 2006 Page 127 of 390 REJ09B0185-0241 NOTES: 1. DMA transfer is not effective to any interrupt. DMA transf er is affected neither by the I flag nor by the interrupt control register. 2. The selectable factors of DMA requests differ with each channel. 3. Make sure that no DMAC-related registers (add resses 0020h to 003Fh) are accessed by the DMAC. Table 14.1 DMAC Specifications Item Specification No. of Channels 2 (cycle steal method) Transfer Memory Space • From any address in the 1-Mbyte space to a fixed address

• From a fixed address to any address in the 1-Mbyte space
• From a fixed address to a fixed address Maximum No. of Bytes Transferred 128 Kbytes (with 16-bit transfers) or 64 Kbytes (with 8-bit transfers) DMA Request Factors (1, 2) Falling edge of INT0 or INT1 Both edge of INT0 or INT1 Timer A0 to timer A4 interrupt requests Timer B0 to timer B5 interrupt requests UART0 transfer, UART0 reception interrupt requests UART1 transfer, UART1 reception interrupt requests UART2 transfer, UART2 reception interrupt requests SI/O3, SI/O4 interrupt requests A/D conversion interrupt requests Software triggers Channel Priority DMA0 > DMA1 (DMA0 takes precedence) Transfer Unit 8 bits or 16 bits Transfer Address Direction forward or fixed (The source and destination addresses cannot both be in the forward direction.) Transfer Mode Single Transfer Transfer is complet ed when the DMAi transfer counter (i = 0 to 1) underflows after reaching the terminal count. Repeat Transfer When the DMAi transfer counter underflows, it is reloaded with the value of the DMAi transfer counter reload register and a DMA transfer is continued with it. DMA Interrupt Request Generation Timing W hen the DMAi transfer counter underflowed DMA Start up Data transfer is initiated each time a DMA request is generated when the DMAE bit in the DMAiCON register = 1 (enabled). DMA Shutdown Single Transfer • When the DMAE bit is set to “0” (disabled)
• After the DMAi transfer counter underflows Repeat Transfer When the DMAE bit is set to “0” (disabled) Reload Timing for Forward Address Pointer and Transfer Counter When a data transfer is started after setting the DMAE bit to “1” (enabled), the forward address pointer is reloaded with the value of the SARi or the DARi pointer whichever is specified to be in the forward direction and the DMAi transfer counter is reloaded with the value of the DMAi transfer counter reload register. DMA Transfer Cycles Minimum 3 cycl es between SFR and internal RAM

M16C/62P Group (M16C/62P , M16C/62PT) 14. DMAC Rev.2.41 Jan 10, 2006 Page 128 of 390 REJ09B0185-0241 Figure 14.2 DM0SL Register DMA0 Request Factor Select Register Symbol DM0SL Bit Symbol RW NOTES : 1 0 1 1 b After R eset 00h Address 03B8h 1 0 0 1 b 1 0 1 0 b Timer B2 UART0 Transmit 0 1 1 1 b 1 0 0 0 b Timer B0 Timer B1 0 1 0 1 b 0 1 1 0 b Timer A3 Timer A4 0 0 1 0 b 0 0 1 1 b 0 1 0 0 b Timer A2 Timer A0 Timer A1 DSEL3 to DSEL0 0 0 0 0 b 0 0 0 1 b DMS=0(Basic Factor of Request) Falling Edge of INT0 Pin Softw are Trigger DSR Softw are DMA Request Bit A DMA request is generated by setting this bit to “1” w hen the DMS bit is “0” (basic factor) and the DSEL3 to DSEL0 bits are “0001b” (softw are trigger). The value of this bit w hen read is “0”. RW DMS DMA Request Factor Expansion Select Bit 0: Basic factor of request 1: Extended factor of request RW RW (b5-b4) Nothing is assigned. When w rite, set to “0”. When read, their content are “0”. — RW DSEL1 RW DSEL2 RW Function DSEL0 DMA Request Factor Select Bit (NOTE 1) DSEL3 Bit Name The factors of DMA0 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the manner described below . b7 b6 b5 b4 b3 b2 b1 b0 1 1 0 0 b 1 1 0 1 b 1 1 1 0 b 1 1 1 1 b UA RT0 Rec eiv e UART2 Transmit UA RT2 Rec eiv e A/D Conversion UART1 Transmit DMS=1(Extended Factor of Request) Tw o Edges of INT0 Pin Timer B3 Timer B4 Timer B5

M16C/62P Group (M16C/62P , M16C/62PT) 14. DMAC Rev.2.41 Jan 10, 2006 Page 129 of 390 REJ09B0185-0241 Figure 14.3 DM1SL Register DMA1 Request Factor Select Register Symbol DM1SL Bit Symbol RW NOTES : 1 1 1 0 b A/D Conversion — 1 1 1 1 b UART1 Receive/ACK1 — 1 1 0 0 b UART2 Transmit — 1 1 0 1 b UART2 Receive/ACK2 — 1 0 1 0 b UART0 Transmit — 1 0 1 1 b UART0 Receive/ACK0 — 1 0 0 0 b Timer B1 — 1 0 0 1 b Timer B2 — 0 1 1 0 b Timer A4 SI/O4 0 1 1 1 b Timer B0 Tw o Edges of INT1 Pin 0 1 0 0 b Timer A2 — 0 1 0 1 b Timer A3 SI/O3 0 0 1 0 b Timer A0 — 0 0 1 1 b Timer A1 — 0 0 0 0 b Falling Edge of INT1 Pin — 0 0 0 1 b Softw are Trigger — The factors of DMA1 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the manner described below . DSEL3 to DSEL0 DMS=0(Basic Factor of Request) DMS=1(Extended Factor of Request) RW b7 b6 b5 b4 DSEL3 RW b3 b2 b1 b0 DSEL1 RW DSEL2 RW Address 03BAh After R eset 00h RW DMA Request factor Select Bit (b5-b4) DMA Request Factor Expansion Select Bit (NOTE 1) Nothing is assigned. When w rite, set to “0”. When read, their contents are “0”. DSEL0 RW DSR Softw are DMA Request Bit Bit Name 0: Basic factor of request 1: Extended factor of request A DMA request is generated by setting this bit to “1” w hen the DMS bit is “0” (basic factor) and the DSEL3 to DSEL0 bits are “0001b” (softw are trigger). The value of this bit w hen read is “0”. DMS Function

M16C/62P Group (M16C/62P , M16C/62PT) 14. DMAC Rev.2.41 Jan 10, 2006 Page 130 of 390 REJ09B0185-0241 Figure 14.4 DM0CON and DM1CON Register DMAi Control Register (i=0,1) Symbol Address After Reset DM0CON 002Ch 00000X00b DM1CON 003Ch 00000X00b Bit Symbol Bit Name Function RW NOTES : The DMAS bit can be set to “0” by w riting “0” in a program (This bit remains unchanged even if “1” is w ritten). At least one of the DAD and DSD bits must be “0” (address direction fixed). (b7-b6) —Nothing is assigned. When w rite, set to “0”. When read, their contents are “0”. b7 b6 b5 b4 b3 b2 b1 b0 RW RW DMA S RW(1) Source Address Direction Select Bit (2) 0 : Fixed 1 : Forw ard DMA E RW DA D DMBIT Destination Address Direction Select Bit (2) 0 : Fixed 1 : Forw ard 0 : Disabled 1 : Enabled DMA SL RW DSD RW Transfer Unit Bit Select Bit 0 : 16 bits 1 : 8 bits Repeat Transfer Mode Select Bit 0 : Single transfer 1 : Repeat transfer DMA Request Bit 0 : DMA not requested 1 : DMA requested DMA Enable Bit

M16C/62P Group (M16C/62P , M16C/62PT) 14. DMAC Rev.2.41 Jan 10, 2006 Page 131 of 390 REJ09B0185-0241 Figure 14.5 SAR0, SAR1, DAR0, DA R1, TCR0 and TCR1 Registers DMAi Source Pointer (i = 0, 1) (1) Symbol Address After Reset SAR0 0022h to 0020h Indeterminate SAR1 0032h to 0030h Indeterminate Setting Range RW NOTES : RW Function Set the source address of transfer 00000h to FF FFFh (b23) If the DSD bit in the DMiCON register is “0” (fixed), this register can only be w ritten to w hen the DMAE bit in the DMiCON register is “0” (DMA disabled). If the DSD bit is “1” (forw ard direction), this register can be w ritten to at any time. If the DSD bit is “1” and the DMAE bit is “1” (DMA enabled), the DMAi forw ard address pointer can be read from this register. Otherw ise, the value w ritten to it can be read. b7 b0 Nothing is assigned. When w rite, set “0”. When read, their contents are “0”. (b15) (b8) (b19) (b16) DMAi Destination Pointer (i = 0, 1) (1) Symbol Address After Reset DA R0 0026h to 0024h Indeterminate DA R1 0036h to 0034h Indeterminate Setting Range RW NOTES : (b23) (b19) (b16) (b15) (b8) b0 b7 Function Set the destination address of transfer 00000h to FFFFFh RW Nothing is assigned. When w rite, set “0”. When read, their contents are “0”. — If the DAD bit in the DMiCON register is “0” (fixed), this register can only be w ritten to w hen the DMAE bit in the DMiCON register is “0”(DMA disabled). If the DAD bit is “1” (forw ard direction), this register can be w ritten to at any time. If the DAD bit is “1” and the DMAE bit is “1” (DMA enabled), the DMAi forw ard address pointer can be read from this register. Otherw ise, the value w ritten to it can be read. DMAi Transfer Counter (i = 0, 1) Symbol Address After Reset TCR0 0029h to 0028h Indeterminate TCR1 0039h to 0038h Indeterminate Setting Range RW (b8) b0 b0 (b15) RW 0000h to FFFFh Function Set the transfer count minus 1. The w ritten value is stored in the DMAi transfer counter reload register, and w hen the DMAE bit in the DMiCON register is set to “1” (DMA enabled) or the DMAi transfer counter underflow s w hen the DMASL bit in the DMiCON register is “1” (repeat transfer), the value of the DMAi transfer counter reload register is transferred to the DMAi transfer counter. When read, the DMAi transfer counter is read.

M16C/62P Group (M16C/62P , M16C/62PT) 14. DMAC Rev.2.41 Jan 10, 2006 Page 132 of 390 REJ09B0185-0241

14.1 Transfer Cycles

The transfer cycle consists of a memo ry or SFR read (source read) bus cycl e and a write (destination write) bus cycle. The number of read and write bu s cycles is affected by the source and destination addresses of transfer. During memory extension and microproce ssor modes, it is also affected by th e BYTE pin level. Furthermore, the bus cycle itself is extended by a software wait or RDY signal.

14.1.1 Effect of Source and Destination Addresses

If the transfer unit and data bus both are 16 bits and th e source address of transfer begins with an odd address, the source read cycle consists of one more bus cycle th an when the source address of transfer begins with an even address. Similarly, if the transfer unit and data bus both are 16 bits and the destination address of transfer begins with an odd address, the destination write cy cle consists of one more bus cycle than when the destination address of transfer begins with an even address.

14.1.2 Effect of BYTE Pin Level

During memory extension and microprocessor modes, if 16 bits of data are to be transferred on an 8-bit data bus (input on the BYTE pin = high), the operation is accomplished by transferring 8 bits of data twice. Therefore, this operation requires two bus cycles to read data and two bus cycles to write data. Furthermore, if the DMAC is to access the internal area (internal ROM, internal RAM, or SFR), unlike in the case of the CPU, the DMAC does it through the data bus width selected by the BYTE pin.

14.1.3 Effect of Software Wait

For memory or SFR accesses in which one or more software wait states are inserted, the number of bus cycles required for that access increases by an amount equal to software wait states.

14.1.4 Effect of RDY Signal

During memory extension and microprocessor modes, DMA transfers to and from an external area are affected by the RDY signal. Refer to 8.2.6 RDY Signal. Figure 14.6 shows the exampl e of the Transfer Cycles for Source Read . For convenience, th e destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the destination write cycle is subj ect to the same conditions as the source read cycle, with the transfer cycle changing accordingly. When calculating transfer cycles, take into consideration each c ondition for the s ource read and the destination write cycle, respectively. For example, when data is transferred in 16 bit units using an 8-bit bus ((2) on Figure 14.6), two source read bus cycles and two destination write bus cycles are required.

M16C/62P Group (M16C/62P , M16C/62PT) 14. DMAC Rev.2.41 Jan 10, 2006 Page 133 of 390 REJ09B0185-0241 Figure 14.6 Transfer Cycles for Source Read BCLK Address bus RD signal WR signal Data bus CPU use CPU useSource Destination Dummy cycle (1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address BCLK Address bus RD signal WR signal Data bus CPU use CPU useSource Destination Dummy cycle (3) When the source read cycle under condition (1) has one wait state inserted BCLK Address bus RD signal WR signal Data bus CPU use CPU useSource Destination Dummy cycleSource + 1 (2) When the transfer unit is 16 bits and the source address of transfer is an odd address, or when the transfer unit is 16 bits and an 8-bit bus is used BCLK Address bus RD signal WR signal Data bus CPU use CPU useSource Destination Dummy cycleSource + 1 (4) When the source read cycle under condition (2) has one wait state inserted NOTES : 1. The same timing changes occur with the respective conditions at the destination as at the source. CPU useSource Destination Dummy cycleCPU use CPU use CPU useSource Destination Dummy cycle Source + 1 CPU use CPU useSource Destination Dummy cycle CPU use CPU useSource Destination Dummy cycleSource + 1

M16C/62P Group (M16C/62P , M16C/62PT) 14. DMAC Rev.2.41 Jan 10, 2006 Page 134 of 390 REJ09B0185-0241

14.2 DMA Transfer Cycles

Any combination of even or odd transfer read and write addresses is possible. Tabl e 14.2 lists the DMA Transfer Cycles. Table 14.3 lists the Coefficient j, k. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles × j + No. of write cycles × k — : This condition does not exist. NOTES: 1. Depends on the set value of CSE register. 2. Depends on the set value of PM20 bit in the PM2 register. Table 14.2 DMA Transfer Cycles Transfer Unit Bus Width Access Address Single-Chip Mode Memory Expansion Mode Microprocessor Mode No. of Read Cycles No. of Write Cycles No. of Read Cycles No. of Write Cycles 8-bit Transfers (DMBIT= 1) 16-bit (BYTE= L) E v e n 1111 O d d 1111 8-bit (BYTE = H) Even — — 1 1 Odd — — 1 1 16-bit Transfers (DMBIT= 0) 16-bit (BYTE = L) E v e n 1111 O d d 2222 8-bit (BYTE = H) Even — — 2 2 Odd — — 2 2 Table 14.3 Coefficient j, k Internal Area External Area Internal ROM, RAM SFR Separate Bus Multiplex Bus No Wait With Wait 1-Wait (2) 2-Wait (2) No Wait With Wait (1) With Wait (1) 1-Wait 2-Wait 3-Wait 1-Wait 2-Wait 3-Wait j 1 2 231234334 k 1 2 232234334

M16C/62P Group (M16C/62P , M16C/62PT) 14. DMAC Rev.2.41 Jan 10, 2006 Page 135 of 390 REJ09B0185-0241

14.3 DMA Enable

When a data transfer starts after setting the DMAE bit in the DMiCON register (i = 0, 1) to “1” (enabled), the DMAC operates as follows: (1) Reload the forward address pointer with the SARi register value when the DSD bit in the DMiCON register is “1” (forward) or the DARi register value when the DAD bit in the DMiCON register is “1” (forward). (2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value. If the DMAE bit is set to “1” again while it remains set, the DMAC performs the above operation. However, if a DMA request may occur simultaneously when the DMAE bit is being written, follow the steps below. Step 1: Write “1” to the DMAE bit and DMAS bit in the DMiCON register simultaneously. Step 2: Make sure that the DMAi is in an initial state as described above (1) and (2) in a program. If the DMAi is not in an initial state, the above steps should be repeated.

14.4 DMA Request

The DMAC can generate a DMA request as triggered by the factor of request that is selected with the DMS and DSEL3 to DSEL0 bits in the DMiSL register (i = 0, 1) on either channel. Table 14.4 lists the Timing at Which the DMAS Bit Changes State. Whenever a DMA request is generated, the DMAS bit is se t to “1” (DMA requested) regardless of whether or not the DMAE bit is set. If the DMAE bit was set to “1” (enabled) when this occurred, the DMAS bit is set to “0” (DMA not requested) immediately before a data transfer starts. This bit cannot be set to “1” in a program (it can only be set to “0”). The DMAS bit may be set to “1” when the DMS or the DSEL3 to DSEL0 bits change state. Therefore, always be sure to set the DMAS bit to “0” after changing the DMS or the DSEL3 to DSEL0 bits. Because if the DMAE bit is “1”, a data transfer starts immediately after a DMA request is generated, the DMAS bit in almost all cases is “0” when read in a program. Read the DMAE bit to determine whether the DMAC is enabled. Table 14.4 Timing at Which the DMAS Bit Changes State DMA Factor DMAS Bit of the DMiCON Register Timing at which the bit is set to “1” Timing at which the bit is set to “0” Software Trigger When the DS R bit in the DMiSL register is set to “1”

• Immediately before a data transfer starts
• When set by writing “0” in a program Peripheral Function When the interrupt control register for the peripheral function that is selected by the DSEL3 to DSEL0 and DMS bits in the DMiSL register has its IR bit set to “1”

M16C/62P Group (M16C/62P , M16C/62PT) 14. DMAC Rev.2.41 Jan 10, 2006 Page 136 of 390 REJ09B0185-0241

14.5 Channel Priori ty and DMA Transfer Timing

If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are detected active in the same sampling period (one period from a falling edge to the next falling edge of BCLK), the DMAS bit on each channel is set to “1” (DMA requested) at the same time. In this case, the DMA requests are arbitrated according to the channel priority, DMA0 > DMA1. The following describes DMAC operation when DMA0 and DMA1 requests are detected active in the same sampling period. Figure 14.7 shows an example of DMA Transfer by External Factors. DMA0 request having priority is received first to star t a transfer when a DMA0 request and DMA1 request are generated simultaneously. After one DMA0 transfer is comp leted, a bus arbitration is returned to the CPU. When the CPU has completed one bus access, a DMA1 transfer st arts. After one DMA1 transfer is completed, the bus arbitration is again returned to the CPU. In addition, DMA requests cannot be counted up since each channel has one DMAS bit. Therefore, when DMA requests, as DMA1 in Figure 14.7, occurs more than one time, the DMAS bit is set to “0” as soon as getting the bus arbitration. The bus arbitration is returned to the CPU when one transfer is completed. Refer to 8.2.7 Hold Signal for details about bus arbitration between the CPU and DMA. Figure 14.7 DMA Transfer by External Factors BCLK DMA0 DMA1 DMA0 request bit DMA1 request bit CPU INT0 INT1 Bus arbitration An example where DMA requests for external factors are detected active at the same

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 137 of 390 REJ09B0185-0241 15. Timers Eleven 16-bit timers, each capable of op erating independently of the others, ca n be classified by function as either Timer A (five) and Timer B (six). The count source for each timer acts as a cloc k, to control such timer operations as counting, reloading, etc. Figures 15.1 and 15.2 show block diagrams of Timer A and Timer B configuration, respectively. Figure 15.1 Timer A Configuration 1/32 fC32 f1 or f2 f32

• Main clock
• PLL clock
• On-chip oscillator clock XCIN Set the CPSR bit in the CPSRF register to “1” (= prescaler reset) Reset Clock prescaler NOTES : 1. Be aware that TA0IN shares the pin with RXD2 and TB5IN. f2 PCLK0 bit = 0 PCLK0 bit = 1 00: Timer mode 10: One-shot timer mode 11: PWM mode 01: Event counter modeTA0IN TA1IN TA2IN TA3IN TA4IN Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer A0 interrupt Timer A1 interrupt Timer A2 interrupt Timer A3 interrupt Timer A4 interrupt Noise filter Noise filter Noise filter Noise filter Noise filter TCK1 to TCK0 00: Timer mode 10: One-shot tiemr mode 11: PWM mode 00: Timer mode 10: One-shot timer mode 11: PWM mode 00: Timer mode 10: One-shot timer mode 11: PWM mode 00: Timer mode 10: One-shot timer mode 11: PWM mode 01: Event counter mode 01: Event counter mode 01: Event counter mode 01: Event counter mode TCK1 to TCK0 TCK1 to TCK0 TCK1 to TCK0 TCK1 to TCK0 TMOD1 to TMOD0 TMOD1 to TMOD0 TMOD1 to TMOD0 TA0TGH to TA0TGL Timer B2 overflow or underflow TCK1 to TCK0, TMOD1 to TMOD0 : Bits in TAiMR register (i=0 to 4) TAiGH to TAiGL: Bits in ONSF register and TRGSR register TA1TGH to TA1TGL TA2TGH to TA2TGL TA3TGH to TA3TGL TA4TGH to TA4TGL TMOD1 to TMOD0 TMOD1 to TMOD0 f8 f32 fC32f1 or f2 The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include TA1IN, TA1OUT, TA2IN, TA2OUT and TB pins. Do not use the function which needs these pins. Note

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 138 of 390 REJ09B0185-0241 Figure 15.2 Timer B Configuration NOTES : 1. Be aware that TB5IN shares the pin with RXD2 and TA0IN. TB0IN TB1IN TB2IN Timer B0 Timer B0 interrupt Noise filter Timer B2 overflow or underflow (to a count source of Timer A) TB3IN TB4IN TB5IN Timer B3 interrupt Timer B1 interrupt Timer B2 interrupt Timer B4 interrupt Timer B5 interrupt TCK1 to TCK0 Timer B1 TCK1 to TCK0 Noise filter Timer B2 TCK1 to TCK0 Noise filter Timer B3 TCK1 to TCK0 Noise filter TCK1 to TCK0 Timer B4Noise filter TCK1 to TCK0 Timer B5Noise filter 01: Event counter mode 00: Timer mode 10: Pulse period / pulse width measurement mode TCK1 TMOD1 to TMOD0 01: Event counter mode 00: Timer mode 10: Pulse period / pulse width measurement mode TCK1 01: Event counter mode 00: Timer mode 10: Pulse period / pulse width measurement mode TCK1 01: Event counter mode 00: Timer mode 10: Pulse period / pulse width measurement mode TCK1 01: Event counter mode 00: Timer mode 10: Pulse period / pulse width measurement mode TCK1 01: Event counter mode 00: Timer mode 10: Pulse period / pulse width measurement mode TCK1 TCK1 to TCK0, TMOD1 to TMOD0 : Bits in TBiMR register (i=0 to 5) TMOD1 to TMOD0 TMOD1 to TMOD0 TMOD1 to TMOD0 TMOD1 to TMOD0 TMOD1 to TMOD0 1/32 fC32XCIN Reset Clock prescaler f32 f1 or f2· Main clock

• PLL clock
• On-chip oscillator clock Set the CPSR bit in the CPSRF register to “1” (= prescaler reset) f2 PCLK0 bit = 0 PCLK0 bit = 1 f8 f32 fC32f1 or f2

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 139 of 390 REJ09B0185-0241

15.1 Timer A

supports the following four modes. Except in event counter mode, Timers A0 to A4 all have the same function. Use the TMOD1 to TMOD0 bits in the TAiMR register (i = 0 to 4) to select the desired mode.

• Timer Mode: The timer counts an internal count source.
• Event Counter Mode: The timer counts pulses from an external device or overflows and underflows of other timers.
• One-shot Timer Mode: The timer outputs a pulse only once be fore it reaches the minimum count “0000h”.
• Pulse Width Modulation (PWM) Mode: The timer outputs pulses in a given width successively. Figure 15.3 Timer A Block Diagram TAi Addresses TAj TAk Timer A0 0387h - 0386h Timer A4 Timer A1 Timer A1 0389h - 0388h Timer A0 Timer A2 Timer A2 038Bh - 038Ah Timer A1 Timer A3 Timer A3 038Dh - 038Ch Timer A2 Timer A4 Timer A4 038Fh - 038Eh Timer A3 Timer A0 f1 or f2 f32 fC32 TAiS Increment / decrement Select Count Source
• Timer (gate function): TMOD1 to TMOD0=00, MR2=1
• Timer :TMOD1 to TMOD0=00, MR2=0
• One-Shot Timer :TMOD1 to TMOD0=10
• Pulse Width Modulation :TMOD1 to TMOD0=11 TAiIN
• Event counter :TMOD1 to TMOD0=01 Select clock TAj Overflow (1) Pulse Output Toggle Flip Flop TAiOUT Always decrement except in event counter mode 8 low-order bits Counter Low-Order Bits of Data Bus TAiUD Decrement TAk Overflow (1) Polarity Selector TCK1 to TCK0 TB2 Overflow (1) TAiTGH to TAiTGL MR2 TMOD1 to TMOD0 TCK1 to TCK0, TMOD1 to TMOC0, MR2 to MR1 : Bits in TAiMR register TAiTGH to TAiTGL : Bits in ONSF register if i=0 or bits in TRGSR register if i=1 to 4 TAiS : Bits in the TABSR register TAiUD : Bits in the UDF register TMOD1 to TMOD0, MR2 i=0 to 4 j=i-1, however, j=4 if i=0 k=i+1, however, k=0 if i=4 8 high- order bits To external trigger circuit High-Order Bits of Data Bus Reload Register NOTES: 1. Overflow or underflow The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include TA1IN and TA1OUT pins of Timer A1, and TA2IN and TA2OUT pins of Timer A2. [Precautions when using Timer A1 and Timer A2]
• Timer Mode The Gate Function and the Pulse Output Function cannot be used. Set the MR2 to MR0 bits in the TA1MR and TA2MR registers to “000b” when using Timer Mode.
• Event Counter Mode The Pulse Output Function cannot be used and external input signals cannot be counted. Two-phase Pulse Signal of Timer A2 cannot be used. Set the MR2 to MR0 bits in the TA1MR and TA2MR registers to “000b” when using the Event Counter Mode.
• One-shot Timer Mode The Pulse Output Function cannot be used and count start by the external trigger cannot be counted. Set the MR1 to MR0 bits in the TA1MR and TA2MR registers to “00b” when using the One-shot Timer Mode.
• Pulse Width Modulation Mode PWM pulse cannot be outputted. Note

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 140 of 390 REJ09B0185-0241 Figure 15.4 TAiMR and TAi Registers Timer Ai Mode Register (i=0 to 4) Address After Reset 0396h to 039Ah 00h Bit Symbol Function RW RW b3 b2 b1 b0 Bit Name Operation Mode Select Bit TA0MR to TA4MR Symbol b7 b6 b5 b4 TCK1 RW RW RW MR1 TCK0 RW MR3 Count Source Select Bit Function varies w ith each operation mode TMOD1 MR2 RW RW MR0 RW b1 b0 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse w idth modulation (PWM) mode — Function varies w ith each operation mode TMOD0 Timer Ai Register (i= 0 to 4) (1) Symbol Address After Reset TA0 0387h, 0386h Indeterminate TA1 0389h, 0388h Indeterminate TA2 038Bh, 038Ah Indeterminate TA3 038Dh, 038Ch Indeterminate TA4 038Fh, 038Eh Indeterminate Setting Range RW NOTES : (b15) b7 b0 (b8) RW0000h to FFFFh Mode Function Divide the count source by n + 1 w here n = set value Timer Mode 0000h to FFFEh(3, 4) WO 00h to FEh (High-order address) 00h to FFh (Low -order address) (3, 4) WO If the TAi register is set to “0000h”, the pulse w idth modulator does not w ork, the output level on the TAiOUT pin remains low , and timer Ai interrupt requests are not generated either. The same applies w hen the 8 high-order bits of the timer TAi register are set to “00h” w hile operating as an 8-bit pulse w idth modulator. Puls e Width Modulation Mode (8-Bit P WM ) Use the MOV instruction to w rite to the TAi register. The timer counts pulses from an external device or overflow s or underflow s in other timers. Modify the pulse w idth as follow s: PWM period: (28 – 1) × (m + 1)/ fj High level PWM pulse w idth: (m + 1)n / fj w here n = high-order address set value, m = low -order address set value, fj = count source frequency The register must be accessed in 16-bit units. If the TAi register is set to “0000h”, the counter does not w ork and timer Ai interrupt requests are not generated either. Furthermore, if “pulse output” is selected, no pulses are output from the TAiOUT pin. Puls e Width Modulation Mode (16-Bit PWM) Event Counter Mode Divide the count source by FFFFh – n + 1 w here n = set value w hen counting up or by n + 1 w hen counting dow n (5) Divide the count source by n w here n = set value and factor the timer to stop Modify the pulse w idth as follow s: PWM period: (216 – 1) / fj High level PWM pulse w idth: n / fj w here n = set value, fj = count source frequency One-Shot Timer Mode 0000h to FFFFh RW 0000h to FFFFh (2, 4) WO

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 141 of 390 REJ09B0185-0241 Figure 15.5 TABSR and UDF Registers Count Start Flag Address After Reset 0380h 00h Bit Symbol Function RW Bit Name TABSR Symbol b3 b2 b1 b0b7 b6 b5 b4 RW RW RW TA3S TB1S RW TB0S 0 : Stops counting 1 : Starts counting RW RW RW RW Timer A4 Count Start Flag Timer B1 Count Start Flag Timer A2 Count Start Flag Timer A3 Count Start Flag Timer B2 Count Start Flag TA0S TA1S TA4S TA2S Timer B0 Count Start Flag TB2S Timer A0 Count Start Flag Timer A1 Count Start Flag Up/Down Flag (1) Address After Reset 0384h 00h Bit Symbol Function RW NOTES : Use MOV instruction to w rite to this register. Make sure the port direction bits for the TA2IN to TA4IN and TA2OUT to TA4OUT pins are set to “0” (input mode). When not using the tw o-phase pulse signal processing function, set the bit corresponding to Timer A2 to Timer A4 to “0”. TA4P WOTimer A4 Tw o-Phase Pulse Signal Processing Select Bit RW Timer A4 Up/Dow n Flag RW TA0UD TA1UD TA4UD TA2UD RW RW Timer A0 Up/Dow n Flag Timer A1 Up/Dow n Flag WO TA3UD TA3P WO TA2P Timer A3 Tw o-Phase Pulse Signal Processing Select Bit Timer A2 Tw o-Phase Pulse Signal Processing Select Bit Timer A3 Up/Dow n Flag RW b0b7 b6 b5 b4 b3 b2 b1 0 : Dow n count 1 : Up count Enabled by setting the MR2 bit in the TAiMR register to “0” (=sw itching source in UDF register) during event counter mode. 0 : tw o-phase pulse signal processing disabled 1 : tw o-phase pulse signal processing enabled (2, 3) Bit Name UDF Symbol Timer A2 Up/Dow n Flag

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 142 of 390 REJ09B0185-0241 Figure 15.6 ONSF, RGSR Registers One-Shot Start Flag Symbol Address After Reset ONSF 0382h 00h Bit Symbol Bit Name Function RW Z-Phase Input Enable Bit NOTES : TA4OS TAZIE RW RW The timer starts counting by setting this bit to “1” w hile the TMOD1 to TMOD0 bits in the TAiMR register i = 0 to 4) = 10b (= one-shot timer mode) and the MR2 bit in the TAiMR register = 0 (=TAiOS bit enabled). When read, its content is 0”. Timer A3 One-Shot Start Flag Timer A4 One-Shot Start Flag TA3OS RW TA2OS b7 b6 0 0 : Input on TA0IN is selected (1) 0 1 : TB2 is selected (2) 1 0 : TA4 is selected (2) 1 1 : TA1 is selected (2) Timer A0 Event/Trigger Select Bit TA0TGH RW TA0TGL RW Timer A2 One-Shot Start Flag RW TA1OS Timer A1 One-Shot Start Flag RW TA0OS Timer A0 One-Shot Start Flag RW 0 : Z-phase input disabled 1 : Z-phase input enabled Make sure the PD7_1 bit in the PD7 register is set to “0” (= input mode). Overflow or underflow . b7 b6 b5 b4 b3 b2 b1 Trigger Select Register Symbol Address After Reset TRGSR 0383h 00h Bit Symbol Bit Name Function RW NOTES : TA1TGH b3 b2 0 0 : Input on TA2IN is selected (1) 0 1 : TB2 is selected (2) 1 0 : TA1 is selected (2) 1 1 : TA3 is selected (2) b5 b4 0 0 : Input on TA3IN is selected (1) 0 1 : TB2 is selected (2) 1 0 : TA2 is selected (2) 1 1 : TA4 is selected (2) TA3TGL TA3TGH RW RW Timer A3 Event/Trigger Select Bit b7 b6 0 0 : Input on TA4IN is selected (1) 0 1 : TB2 is selected (2) 1 0 : TA3 is selected (2) 1 1 : TA0 is selected (2) Timer A4 Event/Trigger Select Bit TA4TGH RW TA4TGL RW RW Timer A1 Event/Trigger Select Bit Timer A2 Event/Trigger Select Bit TA1TGL RW TA2TGH RW TA2TGL RW b1 b0 0 0 : Input on TA1IN is selected (1) 0 1 : TB2 is selected (2) 1 0 : TA0 is selected (2) 1 1 : TA2 is selected (2) Make sure the port direction bits for the TA1IN to TA4IN pins are set to “0” (= input mode). Overflow or underflow . b7 b6 b5 b4 b3 b2 b1 b0

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 143 of 390 REJ09B0185-0241 Figure 15.7 CPSRF Register Clock Prescaler Reset Flag Symbol Address After Reset CPSRF 0381h 0XXXXXXXb Bit Symbol Bit Name Function RW b7 b6 b5 b4 b3 b2 b1 b0 (b6-b0) Nothing is assigned. When w rite, set to “0”. When read, their contents are indeterminate. — CPSR Clock Prescaler Reset Flag Setting this bit to “1” initializes the prescaler for the timekeeping clock. (When read, its content is “0”.) RW

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 144 of 390 REJ09B0185-0241

15.1.1 Timer Mode

In timer mode, the timer counts a count source generated internally (see Table 15.1). Figure 15.8 shows TAiMR Register in Timer Mode. Table 15.1 Specifications in Timer Mode Item Specification Count source f1, f2, f8, f32, fC32 Count Operation • Down-count

• When the timer underflows, it reloads the reload register contents and continues counting Divide Ratio 1/(n+1) n: set value of TAi register (i= 0 to 4) 0000h to FFFFh Count Start Condition Set TAiS bit in T ABSR register to “1” (= start counting) Count Stop Condition Set TAiS bit to “0” (= stop counting) Interrupt Request Generation Timing Timer underflow TAiIN Pin Function I/O port or gate input TAiOUT Pin Function I/O port or pulse output Read from Timer Count value can be read by reading TAi register Write to Timer • When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input) Value written to TAi register is written to only reload register (Transferred to counter when reloaded next) Select Function • Gate function Counting can be started and stopped by an input signal to TAiIN pin
• Pulse output function Whenever the timer underflows, the output polarity of TAiOUT pin is inverted. When TAiS bit is set to “0” (stop counting), the pin outputs a low.

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 145 of 390 REJ09B0185-0241 Figure 15.8 TAiMR Register in Timer Mode Timer Ai Mode Register (i=0 to 4) Address After Reset 0396h to 039Ah 00h Bit Symbol Function RW NOTES : RW RW RW RW RW b7 b6 b5 b4 Symbol00 b3 b2 b1 b0 RWb1 b0 0 0 : Timer mode TMOD0 TA0MR to TA4MR Bit Name Operation Mode Select Bit TMOD1 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (1) (TAiOUT pin is a pulse output pin) Pulse Output Function Select Bit MR2 RW b4 b3 0 0 : Gate function not available 0 1 : (TAiIN pin functions as I/O port) 1 0 : Counts w hile input on the TAiIN pin is low (2) 1 1 : Counts w hile input on the TAiIN pin is high (2) Gate Function Select Bit MR1 MR0 Selected by PCLK0 bit in the PCLKR register. TA0OUT pin is N-channel open drain output. RW MR3 Count Source Select Bit b7 b6 0 0 : f1 or f2 (3) 0 1 : f8 1 0 : f32 1 1 : fC32TCK1 TCK0 Set to “0” in timer mode The port direction bit for the TAiIN pin is set to “0” (= input mode).

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 146 of 390 REJ09B0185-0241

15.1.2 Event Counter Mode

In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Timer A2, A3 and A4 can count two-phase external signals. Table 15.2 lists Specifications in Event Counter Mode (when not processing two-phase pulse signal). Table 15.3 lists Specifications in Event Counter Mode (when processing two-phase pulse signal with Timer A2, A3 and A4). Figure 15.9 shows TAiMR Register in Event Counter Mode (when not using two-phase pulse signa l processing). Figure 15.10 shows TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase pulse signal processing with Timer A2, A3 and A4). Table 15.2 Specifications in Event Counter Mode (when not processing two-phase pulse signal) Item Specification Count Source • External signals input to TAiIN pin (i=0 to 4) (effective edge can be selected in program)

• Timer B2 overflows or underflows, Timer Aj (j=i-1, except j=4 if i=0) overflows or underflows, Timer Ak (k=i+1, except k=0 if i=4) overflows or underflows Count Operation • Up-count or down-count can be selected by external signal or program
• When the timer overflows or underflows, it reloads the reload register contents and continues counting. When operating in free-running mode, the timer continues counting without reloading. Divided Ratio 1/ (FFFFh - n + 1) for up-count 1/ (n + 1) for down-count n : set value of TAi register 0000h to FFFFh Count Start Condition Set TAiS bit in the TABSR register to “1” (= start counting) Count Stop Condition Set TAiS bit to “0” (= stop counting) Interrupt Request Generation Timing Timer overflow or underflow TAiIN Pin Function I/O port or count source input TAiOUT Pin Function I/O port, pulse ou tput, or up/down-count select input Read from Timer Count value can be read by reading TAi register Write to Timer • When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input) Value written to TAi register is written to only reload register (Transferred to counter when reloaded next) Select Function • Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded to it
• Pulse output function Whenever the timer underflows or underflows, the output polarity of TAiOUT pin is inverted. When TAiS bit is set to “0” (stop counting), the pin outputs a low.

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 147 of 390 REJ09B0185-0241 Figure 15.9 TAiMR Register in Event Counter Mode (when not using two-phase pulse signal processing) Address After Reset 0396h to 039Ah 00h Bit Symbol Function RW NOTES : During event counter mode, the count source can be selected using the ONSF and TRGSR registers. TA0OUT pin is N-channel open drain output. Timer Ai Mode Register (i=0 to 4) (when not using two-phase pulse signal processing) Effective w hen the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are “00b” (TAiIN pin input). Symbol TCK0 Count Polarity Select Bit (3) 0 : Counts falling edge of external signal 1 : Counts rising edge of external signal Up/Dow n Sw itching Factor Select Bit 0 : UDF register 1 : Input signal to TAiOUT pin (4) Count dow n w hen input on TAiOUT pin is low or count up w hen input on that pin is high. The port direction bit for TAiOUT pin is set to “0” (= input mode). Bit Name Operation Mode Select Bit TA0MR to TA4MR TMOD1 TCK1 RW RW RW MR1 b7 b6 b5 b4 b3 b2 b1 b0 RW MR0 RW b1 b0 0 1 : Event counter mode (1) TMOD0 RW 00 1 Can be “0” or “1” w hen not using tw o-phase pulse signal processing RW MR3 0 : Pulse is not output (TAiOUT pin functions as I/O port) 1 : Pulse is output (2) (TAiOUT pin functions as pulse output pin) Pulse Output Function Select Bit MR2 RW Count Operation Type Select Bit 0 : Reload type 1 : Free-run type Set to “0” in event counter mode

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 148 of 390 REJ09B0185-0241 NOTES: 1. Only Timer A3 is selectable. Timer A2 is fixed to normal processing operation, and Timer A4 is fixed to multiply-by-4 processing operation. Table 15.3 Specifications in Event Counter Mode (when processing two-phase pulse signal with Timer A2, A3 and A4) Item Specification Count Source • Two-phase pulse signals inpu t to TAiIN or TAiOUT pins (i=2 to 4) Count Operation • Up-count or down-count can be selected by two-phase pulse signal

• When the timer overflows or underflows, it reloads the reload register contents and continues counting. When operating in free-running mode, the timer continues counting without reloading. Divide Ratio 1/ (FFFFh - n + 1) for up-count 1/ (n + 1) for down-count n : set value of TAi register 0000h to FFFFh Count Start Condition Set TAiS bit of TA BSR register to “1” (= start counting) Count Stop Condition Set TAiS bit to “0” (= stop counting) Interrupt Request Generation Timing Timer overflow or underflow TA2IN Pin Function Two-phase pulse input TA2OUT Pin Function Two-phase pulse input Read from Timer Count value can be read by reading Timer A2, A3 or A4 register Write to Timer • When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input) Value written to TAi register is written to reload register (Transferred to counter when reloaded next) Select Function (1) • Normal processing operation (Timer A2 and Timer A3) The timer counts up rising edges or counts down falling edges on TAjIN pin when input signals on TAjOUT pin is “H”.
• Multiply-by-4 processing operation (Timer A3 and Timer A4) If the phase relationship is such that TAkIN(k=3, 4) pin goes “H” when the input signal on TAkOUT pin is “H,” the timer counts up rising and falling edges on TAkOUT and TAkIN pins. If the phase relationship is such that TAkIN pin goes “L” when the input signal on TAkOUT pin is “H,” the timer counts down rising and falling edges on TAkOUT and TAkIN pins.
• Counter initialization by Z-phase input (Timer A3) The timer count value is initialized to 0 by Z-phase input. TAjOUT Up- count Up- count Up- count Down- count Down- count Down- count TAjIN (j=2, 3) TAkOUT TAkIN (k=3, 4) Count up all edges Count up all edges Count down all edges Count down all edges

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 149 of 390 REJ09B0185-0241 Figure 15.10 TA2MR to TA4MR Registers in Even t Counter Mode (when using two-phase pulse signal processing with Timer A2, A3 and A4) Address After Reset 0398h to 039Ah 00h Bit Symbol Function RW NOTES : TMOD0 RW To use tw o-phase pulse signal processing, set this bit to “0”. Bit Name Operation Mode Select Bit RW b1 b0 0 1 : Event counter mode Tw o-phase pulse signal processing Operation Type Select Bit (1, 2) 0 : Normal processing operation 1 : Multiply-by-4 processing operation RW MR0 b2 b1 b0b7 b6 b5 b4 Timer A2 Mode Register (i=2 to 4) (when using two-phase pulse signal processing) 000101 Symbol TMOD1 TA2MR to TA4MR TCK1 bit is valid for Timer A3 mode register. No matter how this bit is set, Timer A2 and A4 alw ays operate in normal processing mode and x4 processing mode, respectively. RW RW RW MR1 TCK0 MR3 If tw o-phase pulse signal processing is desired, follow ing register settings are required:

• Set the TAiP bit in the UDF register to “1” (tw o-phase pulse signal processing function enabled).
• Set the TAiTGH and TAiTGL bits in the TRGSR register to “00b” (TAiIN pin input).
• Set the port direction bits for TAiIN and TAiOUT to “0” (input mode). To use tw o-phase pulse signal processing, set this bit to “0”. To use tw o-phase pulse signal processing, set this bit to “1”. RW MR2 RW Count Operation Type Select Bit 0 : Reload type 1 : Free-run type TCK1 To use tw o-phase pulse signal processing, set this bit to “0”.

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 150 of 390 REJ09B0185-0241

15.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing

This function initializes the timer count value to “0” by Z-phase (counter initialization) input during two-phase pulse signal processing. This function can only be used in Timer A3 event counter mode during two-phase pulse signal processing, free- running type, x4 processing, with Z-phase entered from the ZP pin. Counter initialization by Z-phase input is enabled by writing “0000h” to the TA3 register and setting the TAZIE bit in the ONSF register to “1” (= Z-phase input enabled). Counter initialization is accomplished by detecting Z-phase input edge. The active edge can be chosen to be the rising or falling edge by using the POL bit in the INT2IC register. The Z-phase pulse width applied to the INT2 pin must be equal to or greater than one clock cycle of Timer A3 count source. The counter is initialized at the next count timing af ter recognizing Z-phase input. Figure 15.11 shows the Relationship Between the Two-Phase Pulse (A phase and B phase) and the Z-Phase. If Timer A3 overflow or underflow coincides with the counter initialization by Z-phase input, a Timer A3 interrupt request is generated twice in succession. Do not use Timer A3 interrupt when using this function. Figure 15.11 Two-Phase Pulse (A phase and B phase) and the Z-Phase mm + 1 1 2 3 4 5 TA3OUT (A phase) Count source TA3IN (B phase) Timer A3 ZP (1) Input equal to or greater than one clock cycle of count source NOTES : 1. This timing diagram is for the case where the POL bit in the INT2IC register = 1 (= rising edge).

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 151 of 390 REJ09B0185-0241

15.1.3 One-shot Timer Mode

In one-shot timer mode, the timer is activated only on ce by one trigger (see Table 15.4). When the trigger occurs, the timer starts up and continues operating for a given period. Figure 15.12 shows the TAiMR Register in One-Shot Timer Mode. Table 15.4 Specifications in One-shot Timer Mode Item Specification Count Source f1, f2, f8, f32, fC32 Count Operation • Down-count

• When the counter reaches “0000h,” it stops counting after reloading a new value
• If a trigger occurs when counting, the timer reloads a new count and restarts counting Divide Ratio 1/n n : set value of TAi register (i=0 to 4) 0000h to FFFFh However, the counter does not work if the divide-by-n value is set to “0000h”. Count start Condition TAiS bit in the TABSR register = 1 (start counting) and one of the following triggers occurs.
• External trigger input from the TAiIN pin
• Timer B2 overflow or underflow, Timer Aj (j=i-1, except j=4 if i=0) overflow or underflow, Timer Ak (k=i+1, except k=0 if i=4) overflow or underflow
• The TAiOS bit in the ONSF register is set to “1”(= timer starts) Count Stop Condition • When the counter is reloaded after reaching “0000h”
• TAiS bit is set to “0” (= stop counting) Interrupt Request Generation Timing When the counter reaches “0000h” TAiIN Pin Function I/O port or trigger input TAiOUT Pin Function I/O port or pulse output Read from Timer An indeterminate value is read by reading TAi register Write to Timer • When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input) Value written to TAi register is written to only reload register (Transferred to counter when reloaded next) Select Function • Pulse output function The timer outputs a low when not counting and a high when counting.

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 152 of 390 REJ09B0185-0241 Figure 15.12 TAiMR Register in One-Shot Timer Mode Timer Ai Mode Register (i=0 to 4) Address After Reset 0396h to 039Ah 00h Bit Symbol Function RW NOTES : RW MR3 Set to “0” in one-shot timer mode TCK1 RW RW TCK0 0 : Falling edge of input signal to TAiIN pin (3) 1 : Rising edge of input signal to TAiIN pin (3) Trigger Select Bit 0 : TAiOS bit is enabled 1 : Selected by TAiTGH to TAiTGL bits Count Source Select Bit b7 b6 0 0 : f1 or f2 (4) 0 1 : f8 1 0 : f32 1 1 : fC32 TA0MR to TA4MR 01 0 Symbol b1 b0 1 0 : One-shot timer mode TMOD0 RW 0 : Pulse is not output (TAiOUT pin functions as I/O port) 1 : Pulse is output (1) (TAiOUT pin functions as a pulse output pin) Pulse Output Function Select Bit TMOD1 b7 b6 b5 b4 b3 b2 b1 b0 Bit Name Operation Mode Select Bit MR2 RW RWMR1 External Trigger Select Bit (2) RW MR0 RW Selected by PCLK0 bit in the PCLKR register. TA0OUT pin is N-channel open drain output. Effective w hen the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are “00b” (TAiIN pin input). The port direction bit for the TAiIN pin is set to “0” (= input mode).

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 153 of 390 REJ09B0185-0241

15.1.4 Pulse Width M odulation (PWM) Mode

In PWM mode, the timer outputs pulses of a given width in succession (see Table 15.5). The counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 15.13 shows TAiMR Register in PWM Mode. Figures 15.14 and 15.15 show Example of 16-bit Pulse Width Modulator Operation and Example of 8-bit Pulse Width Modulator Operation. Table 15.5 Specifications in PWM Mode Item Specification Count Source f1, f2, f8, f32, fC32 Count Operation • Down-count (operating as an 8-bit or a 16-bit pulse width modulator)

• The timer reloads a new value at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs during counting 16-bit PWM • High level width n / fj n : set value of TAi register (i=o to 4)
• Cycle time (216-1) / fj fixed fj: count source frequency (f1, f2, f8, f32, fC32) 8-bit PWM • High level width n × (m+1) / fj n : set value of TAi register high-order address
• Cycle time (28-1) × (m+1) / fj m : set value of TAi register low-order address Count Start Condition • TAiS bit of TABSR regi ster is set to “1” (= start counting)
• The TAiS bit = 1 and external trigger input from the TAiIN pin
• The TAiS bit = 1 and one of the following external triggers occurs
• Timer B2 overflow or underflow, Timer Aj (j=i-1, except j=4 if i=0) overflow or underflow, Timer Ak (k=i+1, except k=0 if i=4) overflow or underflow Count Stop Condition TAiS bit is set to “0” (= stop counting) Interrupt Request Generation Timing On the falling edge of PWM pulse TAiIN Pin Function I/O port or trigger input TAiOUT Pin Function Pulse output Read from Timer An indeterminate value is read by reading TAi register Write to Timer • When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input) Value written to TAi register is written to only reload register (Transferred to counter when reloaded next)

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 154 of 390 REJ09B0185-0241 Figure 15.13 TAiMR Register in PWM Mode Timer Ai Mode Register (i= 0 to 4) Address After Reset 0396h to 039Ah 00h Bit Symbol Function RW NOTES : RW MR2 RW RW MR1 External Trigger Select Bit (2) 0 : Falling edge of input signal to TAiIN pin (3) 1 : Rising edge of input signal to TAiIN pin (3) Trigger Select Bit 0 : Write “1” to TAiS bit in the TASF register 1 : Selected by TAiTGH to TAiTGL bits MR3 Bit Name Operation Mode Select Bit TA0MR to TA4MR Symbol TMOD1 b7 b6 b5 b4 b3 b2 b1 b0 RW MR0 b1 b0 1 1 : PWM mode (1) TMOD0 RW Pulse Output Function Select Bit (4) 0 : Pulse is not output (TAiOUT pin functions as I/O port) 1 : Pulse is output (1) (TAiOUT pin functions as a pulse output pin) RW TCK1 RWTCK0 RW 16/8-Bit PWM Mode Select Bit 0 : Functions as a 16-bit pulse w idth modulator 1 : Functions as an 8-bit pulse w idth modulator Count Source Select Bit b7 b6 0 0 : f1 or f2 (5) 0 1 : f8 1 0 : f32 1 1 : fC32 Selected by PCLK0 bit in the PCLKR register. Set this bit to “1” (Pulse is output) to output PWM pulse. TA0OUT pin is N-channel open drain output. Effective w hen the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are “00b” (TAiIN pin input). The port direction bit for the TAiIN pin is set to “0” (= input mode).

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 156 of 390 REJ09B0185-0241

15.2 Timer B

Timer B supports the following three modes. Use the TMOD1 and TMOD0 bits in the TBiMR register (i = 0 to 5) to select the desired mode.

• Timer Mode: The timer counts an internal count source.
• Event Counter Mode: The timer counts pulses from an external device or overflows or underflows of other timers.
• Pulse Period/Pulse Width Measurement Mode: The timer measures pulse period or pulse width of an external signal. Figure 15.16 Timer B Block Diagram TBi Address TBj Timer B0 0391h - 0390h Timer B2 Timer B1 0393h - 0392h Timer B0 Timer B2 0395h - 0394h Timer B1 Timer B3 0351h - 0350h Timer B5 Timer B4 0353h - 0352h Timer B3 Timer B5 0355h - 0354h Timer B4 Select Clock Source 01: Event Counter 00: Timer 10: Pulse Period and Pulse Width Measurement Reload Register 8 low-order bits 8 high- order bits Low-order Bits of Data Bus High-order Bits of Data Bus TBj Overflow TBiS Polarity Switching and Edge PulseTBiIN Counter Reset Circuit Counter TCK1 to TCK0 TMOD1 to TMOD0 TCK1 (Note 1, 2) TCK1 to TCK0, TMOD1 to TMOD0 : Bits in TAiMR register TBiS : Bits in the TABSR and the TBSR register f1 or f2 f32 fC32 i=0 to 5 NOTES : 1. Overflows or underflows. 2. j=i-1, however, j=2 when i=0 j=5 when i=3 The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include TB1IN pin of Timer B1. [Precautions when using TimerB2]
• Event Counter Mode The external input signals ca nnot be counted. Set the TCK1 bit in the TB1MR register to “1” when using the Event Counter Mode.
• Pulse Period/Pulse Width Measurement Mode This mode cannot be used. Note

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 157 of 390 REJ09B0185-0241 Figure 15.17 TBiMR and TBi Registers Timer Bi Mode Register (i=0 to 5) Address After Reset 039Bh to 039Dh 00XX0000b 035Bh to 035Dh 00XX0000b Bit Symbol Function RW RW(1) — (2) NOTES : TB3MR to TB5MR RWFunction varies w ith each operation mode RW ROMR3 MR2 MR0 MR1 TB0MR to TB2MR Symbol b7 b6 b5 b4 b3 b2 b1 b0 TMOD0 RW Bit Name Operation Mode Select Bit TMOD1 RW b1 b0 0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period measurement mode, pulse w idth measurement mode 1 1 : Do not set to this value Timer B0, Timer B3. Timer B1, Timer B2, Timer B4, Timer B5. Count Source Select Bit Function varies w ith each operation mode TCK1 RW TCK0 RW Timer Bi Register (i=0 to 5)(1) Symbol Address After Reset TB0 0391h, 0390h Indeterminate TB1 0393h, 0392h Indeterminate TB2 0395h, 0394h Indeterminate TB3 0351h, 0350h Indeterminate TB4 0353h, 0352h Indeterminate TB5 0355h, 0354h Indeterminate Function Setting Range RW NOTES : (b15) b7 b7 b0 (b8) RW0000h to FFFFh Mode Divide the count source by n + 1 w here n = set value Timer Mode The register must be accessed in 16-bit units. The timer counts pulses from an external device or overflow s or underflow s of other timers. 0000h to FFFFh RW — RO Divide the count source by n + 1 w here n = set value (2) Measures a pulse period or w idth Event Counter Mode Pulse Period Measurement Mode, Pulse Width Measurement Mode

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 158 of 390 REJ09B0185-0241 Figure 15.18 TABSR, TBSR and CPSRF Registers Count Start Flag Address After Reset 0380h 00h Bit Symbol Function RW Bit Name TABSR Symbol b3 b2 b1 b0b7 b6 b5 b4 RW RW RW TA3S TB1S RW TB0S 0 : Stops counting 1 : Starts counting RW RW RW RW Timer A4 Count Start Flag Timer B1 Count Start Flag Timer A2 Count Start Flag Timer A3 Count Start Flag Timer B2 Count Start Flag TA0S TA1S TA4S TA2S Timer B0 Count Start Flag TB2S Timer A0 Count Start Flag Timer A1 Count Start Flag Timer B3, B4, B5 Count Start Flag Address After Reset 0340h 000XXXXXb Bit Symbol Function RW b2 b1 RW RW b7 b6 b5 b4 b3 b0 Bit Name TBSR Symbol RW TB3S (b4-b0) Timer B3 Count Start Flag Timer B4 Count Start Flag TB5S Nothing is assigned. When w rite, set to “0”. When read, their contents are indeterminate. 0 : Stops counting 1 : Starts countingTB4S Timer B5 Count Start Flag Clock Prescaler Reset Flag Symbol Address After Reset CPSRF 0381h 0XXXXXXXb Bit Symbol Bit Name Function RW b7 b6 b5 b4 b3 b2 b1 b0 (b6-b0) Nothing is assigned. When w rite, set to “0”. When read, their contents are indeterminate. — CPSR Clock Prescaler Reset Flag Setting this bit to “1” initializes the prescaler for the timekeeping clock. (When read, its content is “0”.) RW

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 159 of 390 REJ09B0185-0241

15.2.1 Timer Mode

In timer mode, the timer counts a count source genera ted internally (see Tabl e 15.6). Figure 15.19 shows TBiMR Register in Timer Mode. NOTES: 1. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S bits are assigned to the bit 5 to bit 7 in the TBSR register. Figure 15.19 TBiMR Register in Timer Mode Table 15.6 Specifications in Timer Mode Item Specification Count Source f1, f2, f8, f32, fC32 Count Operation • Down-count

• When the timer underflows, it reloads the reload register contents and continues counting Divide Ratio 1/(n+1) n: set value of TB i register (i= 0 to 5) 0000h to FFFFh Count Start Condition Set TBiS bit (1) to “1” (= start counting) Count Stop Condition Set TBiS bit to “0” (= stop counting) Interrupt Request Generation Timing Timer underflow TBiIN Pin Function I/O port Read from Timer Count value can be read by reading TBi register Write to Timer • When not counting and until the 1st count source is input after counting start Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input) Value written to TBi register is written to only reload register (Transferred to counter when reloaded next) Timer Bi Mode Register (i= 0 to 5) Address After Reset 039Bh to 039Dh 00XX0000b 035Bh to 035Dh 00XX0000b Bit Symbol Function RW RW NOTES : MR2 Count Source Select Bit b7 b6 0 0 : f1 or f2 (1) 0 1 : f8 1 0 : f32 1 1 : fC32 When w rite in timer mode, set to “0”. When read in timer mode, its content is indeterminate. TCK1 b1 b0 0 0 : Timer mode TMOD0 RW b3 b2 b1 b0b7 b6 b5 b4 Symbol TMOD1 TB0MR to TB2MR RW RW RO MR1 TCK0 Has no effect in timer mode Can be set to “0” or “1” TB0MR, TB3MR registers Set to “0” in timer mode Selected by PCLK0 bit in the PCLKR register. Bit Name Operation Mode Select Bit TB3MR to TB5MR TB1MR, TB2MR, TB4MR, TB5MR registers Nothing is assigned. When w rite, set to “0”. When read, its content is indeterminate RW MR3 RW MR0 RW

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 160 of 390 REJ09B0185-0241

15.2.2 Event Counter Mode

In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers (see Table 15.7). Figure 15.20 shows TBiMR Register in Event Counter Mode. NOTES: 1. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S bits are assigned to the bit 5 to bit 7 in the TBSR register. Table 15.7 Specifications in Event Counter Mode Item Specification Count Source • External signals inpu t to TBiIN pin (i=0 to 5) (effective edge can be selected in program)

• Timer Bj overflow or underflow (j=i-1, except j=2 if i=0, j=5 if i=3) Count Operation • Down-count
• When the timer underflows, it reloads the reload register contents and continues counting Divide Ratio 1/(n+1) n: set value of TBi register 0000h to FFFFh Count Start Condition Set TBiS bit(1) to “1” (= start counting) Count Stop Condition Set TBiS bit to “0” (= stop counting) Interrupt Request Generation Timing Timer underflow TBiIN Pin Function Count source input Read from Timer Count value can be read by reading TBi register Write to Timer • When not counting and until the 1st count source is input after counting start Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input) Value written to TBi register is written to only reload register (Transferred to counter when reloaded next)

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 161 of 390 REJ09B0185-0241 Figure 15.20 TBiMR Register in Event Counter Mode Timer Bi Mode Register (i=0 to 5) Address After Reset 039Bh to 039Dh 00XX0000b 035Bh to 035Dh 00XX0000b Bit Symbol Function RW RW NOTES : Effective w hen the TCK1 bit = 0 (input from TBiIN pin). If the TCK1 bit = 1 (TBj overflow or underflow ), these bits can be set to “0” or “1”. The port direction bit for the TBiIN pin must be set to “0” (= input mode). MR3 MR2 When w rite in event counter mode, set to “0”. When read in event counter mode, its content is indeterminate. Has no effect in event counter mode. Can be set to “0” or “1”. Event Clock Select 0 : Input from TBiIN pin (2) 1 : TBj overflow or underflow (j = i – 1, how ever, j = 2 if i = 0, j = 5 if i = 3) TCK1 RW RW MR0 RW b1 b0 0 1 : Event counter mode TMOD0 RW Count Polarity Select Bit (1) b3 b2 0 0 : Counts falling edges of external signal 0 1 : Counts rising edges of external signal 1 0 : Counts falling and rising edges external signal 1 1 : Do not set to this value RW b3 b2 b1 b0b7 b6 b5 b4 RO MR1 TCK0 TB0MR, TB3MR registers Set to “0” in event counter mode TB1MR, TB2MR, TB4MR, TB5MR registers Nothing is assigned. When w rite, set to “0”. When read, its content is indeterminate. RW Bit Name Operation Mode Select Bit TB3MR to TB5MR Symbol TMOD1 TB0MR to TB2MR

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 162 of 390 REJ09B0185-0241

15.2.3 Pulse Period and Puls e Width Measurement Mode

In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an external signal (see Table 15.8). Figure 15.21 shows TBiMR Register in Pulse Period and Pulse Width Measurement Mode. Figure 15.22 shows the Operation Ti ming when Measuring a Pulse Period. Figure 15.23 shows the Operation Timing when Measuring a Pulse Width. NOTES: 1. Interrupt request is not generated when the firs t effective edge is input after the timer started counting. 2. Value read from TBi register is indeterminate unt il the second valid edge is input after the timer starts counting. 3. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S bits are assigned to the bit 5 to bit 7 in the TBSR register. Table 15.8 Specifications in Pulse Period and Pulse Width Measurement Mode Item Specification Count Source f1, f2, f8, f32, fC32 Count Operation • Up-count

• Counter value is transferred to reload register at an effective edge of measurement pulse. The counter value is set to “0000h” to continue counting. Count Start Condition Set TBiS (i=0 to 5) bit (3) to “1” (= start counting) Count Stop Condition Set TBiS bit to “0” (= stop counting) Interrupt Request Generation Timing
• When an effective edge of measurement pulse is input (1)
• Timer overflow. When an overflow occurs, MR3 bit in the TBiMR register is set to “1” (overflowed) simultaneously. MR3 bit is set to “0” (no overflow) by writing to TBiMR register at the next count timing or later after MR3 bit was set to “1”. At this time, make sure TBiS bit is set to “1” (start counting). TBiIN Pin Function Measurement pulse input Read from Timer Contents of the reload register (measurement result) can be read by reading TBi register (2) Write to Timer Value written to TBi register is written to neither reload register nor counter

M16C/62P Group (M16C/62P , M16C/62PT) 15. Timers Rev.2.41 Jan 10, 2006 Page 163 of 390 REJ09B0185-0241 Figure 15.21 TBiMR Register in Pulse Period and Pulse Width Measurement Mode Timer Bi Mode Register (i=0 to 5) Address After Reset 039Bh to 039Dh 00XX0000b 035Bh to 035Dh 00XX0000b Bit Symbol Function RW RW NOTES : TB0MR to TB2MR MR3 MR2 TCK1 b3 b2 b1 b0b7 b6 b5 b4 Symbol TMOD1 Count Source Select Bit b7 b6 0 0 : f1 or f2 (2) 0 1 : f8 1 0 : f32 1 1 : fC32 Timer Bi Overflow Flag (1) 0 : Timer did not overflow 1 : Timer has overflow ed MR0 b1 b0 1 0 : Pulse period / pulse w idth measurement mode TMOD0 Measurement Mode Select Bit TB3MR to TB5MR RW RW RW b3 b2 0 0 : Pulse period measurement (Measurement betw een a falling edge and the next falling edge of measured pulse) 0 1 : Pulse period measurement (Measurement betw een a rising edge and the next rising edge of measured pulse) 1 0 : Pulse w idth measurement (Measurement betw een a falling edge and the next rising edge of measured pulse and betw een a rising edge and the next falling edge) 1 1 : Do not set to this value RWMR1 Selected by PCLK0 bit in the PCLKR register. This flag is indeterminate after reset. When the TBiS bit = 1 (start counting), the MR3 bit is cleared to “0” (no overflow ) by w riting to the TBiMR register at the next count timing or later after the MR3 bit w as set to “1” (overflow ed). The MR3 bit cannot be set to “1” in a program. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S bits are assigned to the bit 5 to bit 7 in the TBSR register. Bit Name Operation Mode Select Bit RW RO TCK0 TB0MR, TB3MR registers Set to “0” in pulse period and pulse w idth measurement mode TB1MR, TB2MR, TB4MR, TB5MR registers Nothing is assigned. When w rite, set to “0”. When read, its content is indeterminate. RW

M16C/62P Group (M16C/62P , M16C/62PT) 16. Three-Phase Motor Control Timer Function Rev.2.41 Jan 10, 2006 Page 165 of 390 REJ09B0185-0241 16. Three-Phase Motor Control Timer Function Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table 16.1 lists the Three-phase Motor Control Timer Functions Specifications. Figure 16 .1 shows the Three-phase Motor Control Timer Functions Block Diagram. Also, the related registers are shown on Figure 16.2 to Figure 16.8. NOTES: 1. Forced cutoff with NMI input is effective when the IVPCR1 bi t in the TB2SC register is set to “1” (three-phase output forcible cutoff by NMI input enabled). If an “L” signal is applied to the NMI pin when the IVPCR1 bit is “1,” the related pins go to a high-impedance state regardless of which functions of those pins are being used. Related pins P7_2/CLK2/TA1OUT/V, P7_3/CTS2 /RTS2/TA1IN/V, P7_4/TA2OUT/W, P7_5/TA2IN/W, P8_0/TA4OUT/U, P8_1/TA4IN/U Table 16.1 Three-phase Motor Control Timer Functions Specifications Item Specification Three-Phase Waveform Output Pin Six pins (U, U, V, V, W, W) Forced Cutoff Input(1) Input “L” to NMI pin Used Timers Timer A4, A1, A2 (us ed in the one-shot timer mode) Timer A4: U- and U-phase waveform control Timer A1: V- and V-phase waveform control Timer A2: W- and W-phase waveform control Timer B2 (used in the timer mode) Carrier wave cycle control Dead time timer (3 eight-bit timer and shared reload register) Dead time control Output Waveform Triangula r wave modulation, Sawtooth wave modification Enable to output “H” or “L” for one cycle Enable to set positive-phase level and negative-phase level respectively Carrier Wave Cycle Triangular wave m odulation: count source x (m+1) x 2 Sawtooth wave modulation: count source x (m+1) m: Setting value of TB2 register, 0000h to FFFFh Count source: f1, f2, f8, f32, fC32 Three-Phase PWM Output Width Triangular wave modulation: count source x n x 2 Sawtooth wave modulation: count source x n n: Setting value of TA4, TA1 and TA2 register (of TA4, TA41, TA1, TA11, TA2 and TA21 registers when setting the INV11 bit to “1”), 0001h to FFFFh Count source: f1, f2, f8, f32, fC32 Dead Time Count source x p, or no dead time p: Setting value of DTT register, 01h to FFh Count source: f1, f2, f1 divided by 2, f2 divided by 2 Active Level Enable to select “H” or “L” Positive and Negative-Phase Concurrent Active Disable Function Positive and negative-phases concurrent active disable function Positive and negative-phases concurrent active detect function Interrupt Frequency For Timer B2 interrupt, select a carrier wave cycle-to-cycle basis through 15 times carrier wave cycle-to-cycle basis The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not use this function. Note

M16C/62P Group (M16C/62P , M16C/62PT) 16. Three-Phase Motor Control Timer Function Rev.2.41 Jan 10, 2006 Page 166 of 390 REJ09B0185-0241 Figure 16.1 Three-phase Motor Control Timer Functions Block Diagram Timer B2 Timer B2 Underflow Circuit to set Interrupt Generation Frequency INV07 1/2f1 or f2 U-phase Output Control Circuit DUB1 bit DUB0 bit D Q T D Q T D Q T D Q T DU1 bit DU0 bit V-Phase Output Control Circuit (One-Shot Timer Mode) Timer A4 Counter Reload TA41 RegisterTA4 Register INV11 T Q (One-Shot Timer Mode) Reload TA11 RegisterTA1 Register INV11 T Q Timer A1 Counter INV06 INV06 Timer A2 Counter Reload TA21 RegisterTA2 Register INV11 T Q INV06 Dead Time Timer n = 1 to 255 Reload Register n = 1 to 255 Dead Time Timer n = 1 to 255 Dead Time Timer n = 1 to 255 D Q T D Q T W-Phase Output Control Circuit D Q T D Q T D Q T D Q T INV01 INV11 Reload Control Signal for Timer A1 ICTB2 Register n=1 to 15INV13 (Timer Mode) INV04 RESET NMI INV05 D Q T R INV02 INV03 Inverse Control INV14 U U V V W W ICTB2 Counter n=1 to 15 PWCON INV12 W-Phase Output Signal W-Phase Output Signal V-Phase Output Signal V-Phase Output Signal U-Phase Output Signal U-Phase Output Signal Trigger Trigger Trigger Trigger Three-Phase Output Shift Register (U Phase) Trigger Trigger Timer A4 One-Shot Pulse INV00 to INV07: Bits in INVC0 Register INV10 to INV15: Bits in INVC1 Register DUi, DUBi: Bits in IDBi Register (i=0,1) TA1S to TA4S: Bits in TABSR Register PWCOM: Bits in TB2SC RegisterINV00 Value to be written to INV03 bit Write signal to INV03 bit Timer B2 Interrupt Request Bit Write Signal to Timer B2 INV10 Inverse Control Inverse Control Inverse Control Inverse Control Inverse Control Start Trigger Signal for Timers A1, A2, A4 Reload Control Signal for Timer A4 Transfer Trigger(1) (One-Shot Timer Mode) When setting the TA4S bit to “0”, signal is set to “0” When setting the TA1S bit to “0”, signal is set to “0” When setting the TA1S bit to “0”, signal is set to “0” Reload Control Signal for Timer A1 Timer A1 One-Shot Pulse Timer A2 One-Shot Pulse Reload Control Signal for Timer A2 Trigger Trigger Trigger Switching to P8_0, P8_1 and P7_2 to P7_5 is not shown in this diagram. NOTES: 1. Transfer trigger is generated only when the IDB0 and IDB1 registers are set and the first timer B2 underflows, if the INV06 bit is set to “0” (triangular wave modulation).

M16C/62P Group (M16C/62P , M16C/62PT) 16. Three-Phase Motor Control Timer Function Rev.2.41 Jan 10, 2006 Page 167 of 390 REJ09B0185-0241 Figure 16.2 INVC0 Register Three-Phase Control Register 0 (1) Symbol Address After R eset INV C0 0348h 00h Bit Symbol Bit Name RW NOTES : INV06=1 Sawtooth wav e modulation mode Transf erred ev ery time a transf er trigger is generated By a transf er trigger, or the f alling edge of a one-shot pulse of the timer A1, A2 or A4 Disabled b7 b6 b5 b4 b3 b2 b1 b0 INV 03 Output Control Bit (5, 6) RW INV 02 Mode Select Bit (4, 5) RW 0 : Disables three-phase control timer output 1 : Enables three-phase control timer output INV 04 Positiv e and Negativ e-Phases Concurrent Activ e Disable Function Enable Bit RW 0 : Enables concurrent active output 1 : Disables concurrent active output INV 05 Positiv e and Negativ e-Phases Concurrent Activ e Output Detect Flag (7) RW 0 : Not detected 1 : Detected 0 : Triangular w ave modulation mode 1 : Saw tooth w ave modulation mode INV 07 Softw are Trigger Select RW Transf er trigger is generated when the INV07 bit is set to “1”. Trigger to the dead time timer is also generated when setting the INV06 bit to “1”. Its v alue is “0” when read. INV 06 Modulation Mode Select (8, 9) When the INV06 bit is set to “1”, set the INV11 bit to “0” (three-phase mode 0) and the PWCON bit in the TB2SC register to “0” (reload Timer B2 with Timer B2 underf low). Set the INV02 bit to “1” to operate the dead time timer, U-, V-and W-phase output control circuits and ICTB2 counter. When the INVC03 bit is set to “1”, the pins applied to U/V/W output three-phase PWM. The INV03 bit is set to “0” when the f ollowings conditions are all met.

• Reset
• A concurrent activ e state occurs while INV04 bit is set to “1”
• The INV03 bit is set to “0” by program The INV05 bit can not be set to “1” by program. Set the INV04 bit to “0”, as well, when setting the INV05 bit to “0”. Item INV06=0 Mode The f ollowing table describes how the INV06 bit works. The U, U , V, V , W and W ___ pins, including pins shared with other output f unctions, are all placed in high-impedance states Set the INV01 bit to “1” af ter setting the ICTB2 register. The INV00 and INV01 bits are enabled only when the INV11 bit is set to “1” (three-phase mode 1). The ICTB2 counter is incremen ted by one ev ery time Timer B2 underf lows, regardless of INV00 and INV01 bit settings, when the INV11 bit is set to “0” (three-phase m ode). When setting the INV01 bit to “1”, set Timer A1 count start f lag bef ore the f irst Timer B2 underf low. When the INV00 bit is set to “1”, the f irst interrupt is generated when Timer B2 underf lows n-1 times, if n is the value set in the ICTB2 counter. Subsequent interrupts are generated ev ery n times Timer B2 underf lows. Interrupt Enable Output Polarity Select Bit (3) Interrupt Enable Output Specification Bit (2, 3) Set the INVC0 register af ter the PRC1 bit in the PRCR register is set to “1” (write enable). Rewrite the INV00 to INV02 and INV06 bits when Timers A1, A2, A4 and B2 stop. INV 01 RW INV 00 RW RW Function 0 : The ICTB2 counter is incremented by one on the rising edge of Timer A1 reload control signal 1 : The ICTB2 counter is incremented by one on the f alling edge of Timer A1 reload control signal 0 : ICTB2 counter is incremented by one when Timer B2 underf lows 1 : Selected by the INV00 bit 0 : No three-phase control timer functions 1 : Three-phase control timer function Transf er trigger : Timer B2 underf lows and write to the INV07 bit, or write to the TB2 register when INV10 = 1 Triangular wav e modulation mode Timing to Transf er f rom the IDB0 and IDB1 Registers to Three Phase Output Shif t Register Transf erred once by generating a transf er trigger af ter setting the IDB0 and IDB1 registers Timing to Trigger the Dead Time Timer when the INV16 Bit=0 On the f alling edge of a one-shot pulse of the timer A1, A2 or A4 when the f ollowing conditions are all met.
• The INV02 bit is set to “1” (three-phase control timer f unction)
• The INV03 bit is set to “0” (three-phase control timer output disabled)
• Direction registers of each port are set to “0” (input mode) When both the INVC04 and INVC05 bits are set to “1”, the INVC03 bit is set to “0”. INV13 Bit Enabled when the INV11 bit=1 and the INV06 bit=0
• A signal applied to the NMI pin changes “H” to “L”

M16C/62P Group (M16C/62P , M16C/62PT) 16. Three-Phase Motor Control Timer Function Rev.2.41 Jan 10, 2006 Page 168 of 390 REJ09B0185-0241 Figure 16.3 INVC1 Register Three-Phase Control Register 1 (1) Symbol Address After R eset INV C1 0349h 00h Bit Symbol Bit Name RW NOTES : INV11=1 Three-phase mode 1 Us ed Enabled Enabled w hen INV11=1 and INV06=0 b7 b6 b5 b4 b3 b2 b1 b0 INV 13 Carrier Wave Detect Bit (4) RO INV 12 Dead Time Timer Count Source Select Bit RW INV 14 Output Polarity Control Bit RW0 : Active “L” of an output w aveform 1 : Active “H” of an output w aveform INV 15 Dead Time Disable Bit RW0 : Enables dead time 1 : Disables dead time RW 0 : Falling edge of a one-shot pulse of Timer A1, A2, A4 (5) 1 : Rising edge of the three-phase output shift register (U-, V-, W-phase) (b7) Res erv ed Bit RWSet to “0” The follow ing table lists how the INV11 bit w orks. When the INV06 bit is set to “1” (saw tooth w ave modulation mode), set the INV11 bit to “0” (three-phase mode 0). Also, w hen the INV11 bit is set to “0”, set the PWCON bit in the TB2SC register to “0” (Timer B2 is reloaded w hen Timer B2 underflow s). The INV13 bit is enabled only w hen the INV06 bit is set to “0” (Triangular w ave modulation mode) and the INV11 bit to “1” (three-phase mode 1). If the follow ing conditions are all met, set the INV16 bit to “1” (rising edge of the three-phase output shift register).

• The INV15 bit is set to “0” (dead time timer enabled)
• The Dij bit (i=U, V or W, j=0, 1) and DiBj bit alw ays have different values w hen the INV03 bit is set to “1”. (The positive-phase and negative-phase alw ays output opposite level signals.) If above conditions are not met, set the INV16 bit to “0” (falling edge of a one-shot pulse of Timer A1, A2, A4). Item INV11=0 Mode INV13 Bit Disabled Three-phase mode 0 Timer A1, A2 and A4 Start Trigger Select Bit Timer A1-1, A2-1 and A4-1 Control Bit (2, 3) Rew rite the INVC1 register after the PRC1 bit in the PRCR register is set to “1” (w rite enable). The timers A1, A2, A4, and B2 must be stopped during rew rite. INV 11 RW INV 10 RW 0 : Timer A1 reload control signal is “0” 1 : Timer A1 reload control signal is “1” INV 16 Dead Time Timer Trigger Select Bit Function 0 : Timer B2 underflow 1 : Timer B2 underflow and w rite to Timer B2 0 : Three-phase mode 0 1 : Three-phase mode 1 0 : f1 or f2 1 : f1 divided-by-2 or f2 divided-by-2 TA11, TA21 and TA41 Registers Not used INV00 and INV01 Bit Disabled. The ICTB2 counter is incremented w henever Timer B2 underflow s

M16C/62P Group (M16C/62P , M16C/62PT) 16. Three-Phase Motor Control Timer Function Rev.2.41 Jan 10, 2006 Page 169 of 390 REJ09B0185-0241 Figure 16.4 ICTB2, TA1, TA2, TA4, TA11, TA21 and TA41 Registers Timer B2 Interrupt Generation Frequency Set Counter (1, 2, 3) Symbol After Reset ICTB2 Indeterminate Setting Range RW NOTES : 3. If the INV00 bit is set to “1”, the first interrupt is generated w hen Timer B2 underflow s n-1 times, n being the value set in the ICTB2 counter. Subsequent interrupts are generated every n times Timer B2 underflow s. Address 034Dh Use the MOV instruction to set the ICTB2 register. WO When the INV01 bit is set to “0” (the ICTB2 counter increments w henever Timer B2 underflow s) and the setting value is n , Tim er B2 interrupt is generated every n th time Timer B2 underflow occurs. When the INV01 bit is set to “1” (the INV00 bit selects count timing of the ICTB2 counter) and setting value is n , Timer B2 interrupt is generated every n th time Timer B2 underflow meeting the condition selected in the INV00 bit occurs. b0b7 Function 1 to 15 If the INV01 bit is set to “1”, set the ICTB2 register w hen the TB2S bit is set to “0” (Timer B2 counter stopped). If the INV01 bit is set to “0” and the TB2S bit to “1” (Timer B2 counter start), do not set the ICTB2 register w hen Timer B2 underflow s. —Nothing is assigned. When w rite, set to “0”. Timer Ai, Ai-1 Register (i = 1, 2, 4) (1, 2, 3, 4, 5, 6, 7) Symbol Address After Reset TA 1, TA 2 0389h to 0388h, 038Bh to 038Ah Indeterminate TA 4 038Fh to 038Eh Indeterminate TA11, TA21 0343h to 0342h, 0345h to 0344h Indeterminate TA 41 0347h to 0346h Indeterminate Setting Range RW NOTES : WO 0000h to FFFFh Function If setting value is n , the timer stops w hen the n th count source is counted after a start trigger is generated. Positive phase changes to negative phase, and vice versa, w hen Timers A1, A2 and A4 stop. b7 b0 (b15) Follow the procedure below to set the TAi1 register. (a) Write value to the TAi1 register, (b) Wait one Tim er Ai count source cycle, and (c) Write the same value as (a) to the TAi1 register. When the INV11 bit is set to “0” (three-phase mode 0), the value of the TAi register is transferred to the reload register by a Timer Ai start trigger. When the INV11 bit is set to “1” (three-phase mode 1), the value of the TAi1 register is first transferred to the reload register by a Timer Ai start trigger. Then, the value of the TAi register is transferred by the next trigger. The values of the TAi1 and TAi registers are transferred alternately to the reload register w ith every Timer Ai start trigger. When the INV15 bit in the INVC1 register is set to “0” (dead timer enabled), phase sw itches from an inactive level to an active level w hen the dead time timer stops. Do not w rite to these registers w hen the Timer B2 underflow s. (b8) Use a 16-bit data for read and w rite. If the TAi or TAi1 register is set to “0000h”, no counters start and no Timer Ai interrupt is generated. Use the MOV instruction to set the TAi and TAi1 registers.

M16C/62P Group (M16C/62P , M16C/62PT) 16. Three-Phase Motor Control Timer Function Rev.2.41 Jan 10, 2006 Page 170 of 390 REJ09B0185-0241 Figure 16.5 TB2SC, IDB0 and IDB1 Registers Timer B2 Special Mode Register (1) Address After Reset 039Eh XXXXXX00b Bit Symbol Function RW 0 : Three-phase output forcible cutoff by NMI ____ input (high-impedance) disabled 1 : Three-phase output forcible cutoff by NMI ____ input (high-impedance) enabled NOTES : Bit Name PWCOM TB2SC Symbol b3 b2 b1b7 b6 b5 b4 RW (b7-b2) IVPCR1 Nothing is assigned. When w rite, set to “0”. When read, their contents are indeterminate. Timer B2 Reload Timing Sw itching Bit Three Phase Output Port NMI ____ 0 : Timer B2 underflow 1 : Timer A output at odd-numbered occurrences (2) Control Bit 1(3) pin w hen the IVPCR1 bit = 1, the target pins go to a high-impedance state regardless of w hich functions of those pins are being used. After forced interrupt (cutoff), input “H” to the NMI ____ pin and set IVPCR1 bit to “0”: this forced cutoff w ill be reset. RW If the INV11 bit is “0” (three-phase mode 0) or the INV06 bit is “1” (saw tooth w ave modulation mode), set this bit to “0” (Timer B2 underflow ). Related pins are U(P8_0/TA4OUT), U (P8_1/TA4IN), V(P7_2/CLK2/TA1OUT), V (P7_3/CTS2/RTS2/TA1IN), Write to this register after setting the PRC1 bit in the P RCR register to “1” (w rite enable). W(P7_4/TA2OUT), W ___ (P7_5/TA2IN). If a low -level signal is applied to the NMI ____ Three-Phase Output Buffer Register i (1) (i=0, 1) Symbol Address After R eset IDB0, IDB1 034Ah, 034Bh 00h Bit Symbol Bit Name RW U -Phase Output Buffer i V -Phase Output Buffer i W -Phase Output Buffer i NOTES : 1. Values of the IDB0 and IDB1 registers are transferred to the three-phase output shift register by a transfer trigger. After the transfer trigger occurs, the values w ritten in the IDB0 register determine each phase output signal first. Then the value w ritten in the IDB1 register on the falling edge of Timers A1, A2 and A4 one-shot pulse determines each phase output signal. DUBi RW DUi RW (b7-b6) Reserved Bit ROSet to “0” DWBi RW Write output level 0 : Active level 1 : Inactive level When read, the value of the three-phase shift register is read. U-Phase Output Buffer i DWi W-Phase Output Buffer i RW DV Bi RW DV i V-Phase Output Buffer i RW Function b3 b2 b1 b0b7 b6 b5 b4

M16C/62P Group (M16C/62P , M16C/62PT) 16. Three-Phase Motor Control Timer Function Rev.2.41 Jan 10, 2006 Page 171 of 390 REJ09B0185-0241 Figure 16.6 DTT, TB2 and TRGSR Registers Dead Time Timer (1, 2) Symbol Address After Reset DTT 034Ch Indeterminate Setting Range RW NOTES : If setting value is n , the timer stops w hen counting n times a count source selected by the INV12 after start trigger occurs. Positive or negative phase, w hich changes from inactive level to active level, shifts w hen the dead time timer stops. Function 1 to 255 The DTT register is enabled w hen the INV15 bit in the INVC1 register is set to “0” (dead time enabled). No dead time can be set w hen the INV15 bit is set to “1” (dead time disabled). The INV06 bit in the INVC0 register determines start trigger of the DTT register. b0b7 Use the MOV instruction to set the DTT register. WO Trigger Select Register Symbol Address After Reset TRGSR 0383h 00h Bit Symbol Bit Name Function RW NOTES : Set the corresponding port direction bit to “0” (input mode). Overflow or underflow . b7 b6 b5 b4 b3 b2 b1 b0 RW Timer A1 Event/Trigger Select Bit Timer A2 Event/Trigger Select Bit TA1TGL RW TA2TGH RW TA2TGL RW Set to “01b” (TB2 underflow ) before using a V-phase output control circuit TA4TGH RW TA4TGL RW RW RW Timer A3 Event/Trigger Select Bit Set to “01b” (TB2 underflow ) before using a U-phase output control circuit Timer A4 Event/Trigger Select Bit TA1TGH Set to “01b” (TB2 underflow ) before using a W-phase output control circuit b5 b4 0 0 : Input on TA3IN is selected (1) 0 1 : TB2 is selected (2) 1 0 : TA2 is selected (2) 1 1 : TA4 is selected (2) TA3TGL TA3TGH Timer B2 Register (1) Symbol Address After Reset TB2 0395h, 0394h Indeterminate Setting Range RW NOTES : (b15) b7 b7 b0 (b8) RW0000h to FFFFh Use a 16-bit data for read and w rite. Function If setting value is n , count source is divided by n +1. Timers A1, A2 and A4 start every time an underflow occurs.

M16C/62P Group (M16C/62P , M16C/62PT) 16. Three-Phase Motor Control Timer Function Rev.2.41 Jan 10, 2006 Page 172 of 390 REJ09B0185-0241 Figure 16.7 TABSR Register Count Start Flag Address After Reset 0380h 00h Bit Symbol Function RW Bit Name TABSR Symbol b3 b2 b1 b0b7 b6 b5 b4 RW RW RW TA3S TB1S RW TB0S 0 : Stops counting 1 : Starts counting RW RW RW RW Timer A4 Count Start Flag Timer B1 Count Start Flag Timer A2 Count Start Flag Timer A3 Count Start Flag Timer B2 Count Start Flag TA0S TA1S TA4S TA2S Timer B0 Count Start Flag TB2S Timer A0 Count Start Flag Timer A1 Count Start Flag

M16C/62P Group (M16C/62P , M16C/62PT) 16. Three-Phase Motor Control Timer Function Rev.2.41 Jan 10, 2006 Page 173 of 390 REJ09B0185-0241 Figure 16.8 TA1MR, TA2MR, TA4MR and TB2MR Registers Timer Ai Mode Register (i=1, 2, 4) Address After Reset 0397h, 0398h 00h 039Ah 00h Bit Symbol Function RW NOTES : 1. Selected by PCLK0 bit in the PCLKR register. Count Source Select Bit b7 b6 0 0 : f1 or f2 (1) 0 1 : f8 1 0 : f32 1 1 : fC32 RW MR3 Set to “0” w ith the three-phase motor control timer function TCK1 RW RW TCK0 Symbol Set to “0” w ith the three-phase motor control timer function Trigger Select Bit Set to “1” (selected by the TRGSR register) w ith the three-phase motor control timer function TA1MR, TA2MR Bit Name TA4MR 001001 RW MR0 RW Set to “10b” (one-shot timer mode) w ith the three- phase motor control timer function TMOD0 RW Set to “0” w ith the three-phase motor control timer function Pulse output Function Select Bit TMOD1 Operation Mode Select Bit b7 b6 b5 b4 b3 b2 b1 b0 RW RWMR1 External Trigger Select Bit MR2 Timer B2 Mode Register Address After Reset 039Dh 00XX0000b Bit Symbol Function RW NOTES : 000 b3 b2 b1 b0b7 b6 b5 b4 Symbol TMOD1 RW RW RO MR1 TCK0 Disabled w hen using the three-phase motor control timer function. When w rite, set to “0”. When read, its content is indeterminate. RW MR3 TB2MR RW MR0 RW Set to “00b” (timer mode) w hen using the three- phase motor control timer function TMOD0 RW Selected by PCLK0 bit in the PCLKR register. RW Bit Name Operation Mode Select Bit MR2 Count Source Select Bit b7 b6 0 0 : f1 or f2 (1) 0 1 : f8 1 0 : f32 1 1 : fC32 When w rite in three-phase motor control timer function, set to “0”. When read in three-phase motor control timer function, its content is indeterminate. TCK1 Set to “0” w hen using three-phase motor control timer function

M16C/62P Group (M16C/62P , M16C/62PT) 16. Three-Phase Motor Control Timer Function Rev.2.41 Jan 10, 2006 Page 174 of 390 REJ09B0185-0241 The three-phase motor control timer func tion is enabled by setting the INV02 bi t in the INVC0 register to “1”. When this function is on, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are used to control three- phase PWM outputs (U, U , V , V, W and W). The dead time is controlled by a dedicated dead time timer. Figure 16.9 shows the example of Triangular Wave Modulation Operation and Figure 16.10 shows the example of Sawtooth Wave Modulation Operation. Figure 16.9 Triangular Wave Modulation Operation Triangular Wave Signal Wave INV00, INV01: Bits in the INVC0 register INV11, INV14: Bits in the INVC1 register NOTES: 1. Internal signals. See Figure 16.1 Three-phase Motor Control Timer Functions Block Diagram . 2. Applies only when the INV11 bit is set to 1 (three-phase mode). (a) When INV11=1 (three-phase mode 1) - INV01=0 and ICTB2=2h (Timer B2 interrupt is generated with every second Timer B2 underflow) or INV01=1, INV00=1and ICTB2=1h (Timer B2 interrupt is generated on the falling edge of Timer A reload control signal) - Default value of the timer: TA41=m, TA4=m The TA4 and TA41 registers are changed whenever Timer B2 interrupt is generated. First time: TA41=n, TA4:=n. Second time: TA41=p, TA4=p. - Default value of the IDB0 and IDB1 registers DU0=1, DUB0=0, DU1=0, DUB1=1 They are changed to DU0=1, DUB0=0, DU1=1, DUB1=0 by the third Timer B2 interrupt. TB2S Bit in TABSR Register Timer B2 Timer A1 Reload Control Signal (1) Timer A4 One-Shot Pulse (1) U-Phase Output Signal (1) U-Phase Output Signal (1) U-Phase U-Phase INV14 = 0 (“L” active) U-Phase U-Phase INV14 = 1 (“H” active) m m nn pp (b) When INV11=0 (three-phase mode 0) - INV01=0, ICTB2=1h (Timer B2 interrupt is generated whenever Timer B2 underflows) - Default value of the timer: TA4=m The TA4 register is changed whenever Timer B2 interrupt is generated. First time: TA4=m. Second time: TA4=n. Third time: TA4=n. Fourth time: TA=p. Fifth time: TA4=p. - Default value of the IDB0 and IDB1 registers: DU0=1, DUB0=0, DU1=0, DUB1=1 They are changed to DU0=1, DUB0=0, DU1=1, DUB1=0 by the sixth Timer B2 interrupt. The above applies to INVC0 = 00XX11XXb and INVC1 = 010XXXX0b (X varies depending on each system.) Examples of PWM output change are qq p q p q m m n m n m n n n pp q Timer A4 Start Trigger Signal (1) TA4 Register (2) TA4-1 Register (2) Reload Register (2) r r q Dead time Dead time Rewrite the IDB0 and IDB1 registers Transfer a counter value to the three- phase shift register Triangular Waveform as a Carrier Wave

M16C/62P Group (M16C/62P , M16C/62PT) 16. Three-Phase Motor Control Timer Function Rev.2.41 Jan 10, 2006 Page 175 of 390 REJ09B0185-0241 Figure 16.10 Sawtooth Wave Modulation Operation Sawtooth Waveform as a Carrier Wave Sawtooth Wave Signal Wave INV14: Bits in the INVC1 register NOTES: 1. Internal signals. See Figure 16.1 Three-phase Motor Control Timer Functions Block Diagram. Timer B2 U-Phase Output Signal(1) U-Phase Output Signal (1) U-Phase U-Phase INV14 = 0 (“L” active) U-Phase U-Phase INV14 = 1 (“H” active) Timer A4 Start Trigger Signal(1) Timer A4 One-Shot Pulse (1) Dead time Rewrite the IDB0 and IDB1 registers Transfer the counter to the three- phase shift register Dead time The above applies to INVC0 = 01XX110Xb and INVC1 = 010XXX00b (X varies depending on each system.) The examples of PWM output change are - Default value of the IDB0 and IDB1 registers: DU0=0, DUB0=1, DU1=1, DUB1=1 They are changed to DU0=1, DUB0=0, DU1=1, DUB1=1 by the timer B2 interrupt.

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 176 of 390 REJ09B0185-0241 17. Serial Interface Serial interface is configured with 5 channels: UART0 to UART2, SI/O3 and SI/O4.

17.1 UARTi (i=0 to 2)

UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figures 17.1 to 17.3 shows the block diagram of UAR T0 to UART2. Figure 17.4 shows the UARTi Transmit/ Receive Unit. UARTi has the following modes:

• Clock synchronous serial I/O mode
• Clock asynchronous serial I/O mode (UART mode).
• Special mode 1 (I2C mode)
• Special mode 2
• Special mode 3 (Bus collision detection function, IE mode) : UART0, UART1
• Special mode 4 (SIM mode) : UART2 Figures 17.5 to 17.12 show the UARTi-related registers. Refer to tables listing each mode for register setting. The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include CLK2, CTS2/RTS2 and SIN pins. Do not use the function which needs these pins. Note The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include CLK2, CTS2/RTS2 pins of UART2. [Precautions when using UART2]
• Clock synchronous serial I/O mode Cannot be used.
• Clock asynchronous serial I/O mode (UART mode) The CTS2/RTS2 function and the external clock of transfer clock cannot be used. Set the CKDIR bit in the U2MR register to “0” and the CRD bit in the U2C0 register to “1” when using the UART mode.
• Special mode 2 The slave mode cannot be used. Se t the CKDIR bit register to “0” when using the Special mode 2.
• Special mode 3 The external clock of transfer cloc k cannot be used. Set the CKDIR bit register to “0” when using the Special mode 3.
• Special mode 4 (SIM mode) The external clock of transfer clock cannot be used. Set the CKDIR bit register to “0” when using the Special mode 4 (SIM mode). Note

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 177 of 390 REJ09B0185-0241 Figure 17.1 UART0 Block Diagram RXD0 1 / (n0+1) U0BRG register Clock synchronous type (when internal clock is selected) Clock synchronous type Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) CLK0 Clock source selection CTS0 / RTS0 f1SIO or f2SIO f8SIO f32SIO Internal External RTS0 CTS0 TXD0 Transmit/ receive unit (UART0) CLK1 to CLK0 00h 01h 10h CKDIR CKPOL UART reception UART transmission Clock synchronous type CKDIR RXD polarity reversing circuit RCSP VSS PCLK1 f1SIO or f2SIO Main clock, PLL clock, or on-chip oscillator clock 1/8 f8SIO f32SIO f1SIO f2SIO 0 SMD2 toSMD0 010, 100, 101, 110 001 010, 100, 101, 110 001 CRS 0 CRD Receive clock Transmit clock Reception control circuit Transmission control circuit TXD polarity reversing circuit CTS/RTS disabled CTS/RTS disabled CTS/RTS selected CTS0 from UART1 CLK polarity reversing circuit n0: Values set to the U0BRG register PCLK1: Bit in the PCLKR register SMD2 to SMD0, CKDIR: Bits in U0MR register CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U0C0 register CLKMD0, CLKMD1, RCSP: Bits in UCON register

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 178 of 390 REJ09B0185-0241 Figure 17.2 UART1 Block Diagram RXD1 Reception control circuit Transmission control circuit 1 / (n1+1) U1BRG register Clock synchronous type (when internal clock is selected) Clock synchronous type Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) CLK1 Clock source selection f1SIO or f2SIO f8SIO f32SIO Internal External TXD1(UART1) CLK1 to CLK0 CKDIR UART reception UART transmission Clock synchronous type CKDIR RXD polarity reversing circuit SMD2 to SMD0 010, 100, 101, 110 001 010, 100, 101, 110 001 RTS1 CTS1 Clock output pin selectCTS1 / RTS1/ CTS0 / CLKS1 VSS CRD CRS 0 0 CLKMD0 CLK polarity reversing circuit CKPOL CLKMD1 RCSP n1: Values set to the U1BRG register PCLK1: Bit in the PCLKR register SMD2 to SMD0, CKDIR: Bits in U1MR register CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U1C0 register CLKMD0, CLKMD1, RCSP: Bits in UCON register PCLK1 f1SIO or f2SIO Main clock, PLL clock, or on-chip oscillator clock 1/8 f8SIO f32SIO f1SIO f2SIO 0 Receive clock Transmit clock Transmit/ receive unit TXD polarity reversing circuit CTS0 from UART0 CTS/RTS disabled CTS/RTS disabled CTS/RTS selected

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 179 of 390 REJ09B0185-0241 Figure 17.3 UART2 Block Diagram RXD2 1 / (n2+1) U2BRG register Clock synchronous type (when internal clock is selected) Clock synchronous type Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) CLK2 Clock source selection f1SIO or f2SIO f8SIO f32SIO Internal External RTS2 CTS2 TXD2(UART2) CLK polarity reversing circuit CLK1 to CLK0 CKDIR CKPOL UART reception UART transmission Clock synchronous type CKDIR RXD polarity reversing circuit VSS SMD2 to SMD0 010, 100, 101, 110 001 010, 100, 101, 110 001 CRS CRD CTS2 / RTS2 NOTES : 1. UART2 is the N-channel open-drain output. Cannot be set to the CMOS output. n2: Values set to the U2BRG register PCLK1: Bit in PCLKR register SMD2 to SMD0, CKDIR: Bits in U2MR register CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U2C0 register CLKMD0, CLKMD1, RCSP: Bits in UCON register CTS/RTS disabled CTS/RTS disabled CTS/RTS selected Reception control circuit Transmission control circuit Receive clock Transmit clock TXD polarity reversing circuit (1) Transmit/ receive unit PCLK1 f1SIO or f2SIO Main clock, PLL clock, or on-chip oscillator clock 1/8 f8SIO f32SIO f1SIO f2SIO 0

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 180 of 390 REJ09B0185-0241 Figure 17.4 UARTi Transmit/Receive Unit SP SP PAR 2SP 1SP UART TXDi D8 D7 D6 D5 D4 D3 D2 D1 D0 2SP 1SP UART RXDi D7 D6 D5 D4 D3 D2 D1 D0D80000000 SP SP PAR SMD2 to SMD0 IOPOL STPS IOPOL UiERE PRYE SMD2 to SMD0 STPS PRYE Reverse No reverse RXD data reverse circuit Clock synchronous type PAR enabled PAR disabled UART (7 bits) UART (8 bits) Clock synchronous type UART(7 bits) UART (9 bits) Clock synchronous type UART (8 bits) UART (9 bits) UARTi receive register UiTB register UiRB register Data bus low-order bits Data bus high-order bits Logic reverse circuit + MSB/LSB conversion circuit Logic reverse circuit + MSB/LSB conversion circuit UART(7 bits) UARTi transmit register UART (8 bits) UART (9 bits) Clock synchronous type UART (7 bits) UART (8 bits) Clock synchronous type Clock synchronous type PAR disabled PAR enabled Error signal output circuit Error signal output enable Error signal output disable Reverse No reverse TXD data reverse circuiti=0 to 2 SP: Stop bit PAR: Parity bit SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in UiMR register UiERE: Bit in UiC1 register UART (9 bits)

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 181 of 390 REJ09B0185-0241 Figure 17.5 UiTB and UiRB Registers UARTi Transmit Buffer Register (i=0 to 2)(1) Symbol Address After Reset U0TB 03A3h to 03A2h Indeterminate U1TB 03ABh to 03AAh Indeterminate U2TB 037Bh to 037Ah Indeterminate RW NOTES : 1. Use MOV instruction to w rite to this register. b7 b0 (b15) (b8) Transmit data Function Nothing is assigned. When w rite, set to “0”. When read, their contents are indeterminate. — WO UARTi Receive Buffer Register (i=0 to 2) Symbol Address After Reset U0RB 03A7h to 03A6h Indeterminate U1RB 03AFh to 03AEh Indeterminate U2RB 037Fh to 037Eh Indeterminate Bit Name RW NOTES : When the SMD2 to SMD0 bits in the UiMR register = 000b (serial interface disabled) or the RE bit in the UiC1 register = 0 (reception disabled), all of the SUM, PER, FER and OER bits are set to “0” (no error). The SUM bit is set to “0” (no error) w hen all of the PER, FER and OER bits = 0 (no error). Also, the PER and FER bits are set to “0” by reading the low er byte of the UiRB register. Function b7 b0 E rror Sum Flag (1, 3) Nothing is assigned. When w rite, set to “0”. When read, their contents are “0”. Receive data (D7 to D0) Receive data (D8) 0 : Not detected 1 : Detected 0 : No overrun error 1 : Overrun error found 0 : No error 1 : Error found PER SUM P arity E rror Flag (1,3) Overrun E rror Flag (1) 0 : No framing error 1 : Framing error found Framing Error Flag (1, 3) 0 : No parity error 1 : P arity error found Arbitration Lost Detecting Flag (2) RO (b15) (b8) The ABT bit is set to “0” by w riting “0” in a program. (Writing “1” has no effect.) RO RO RO OER FER RO RO ABT Bit Symbol (b7-b0) (b8) These error flags are disabled w hen the SMD2 to SMD0 bits are set to “001b” (clock synchronous serial I/O mode) or to “010b” (I2C mode). When read, the contents are indeterminate. RW (b10-b9)

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 182 of 390 REJ09B0185-0241 Figure 17.6 UiBRG Register UARTi Bit Rate Generator Register (i=0 to 2) (1, 2, 3) Symbol Address After Reset U0BRG 03A1h Indeterminate U1BRG 03A9h Indeterminate U2BRG 0379h Indeterminate Setting Range RW NOTES : b7 b0 Write to this register after setting the CLK1 to CLK0 bits in the UiC0 register. Function Use MOV instruction to w rite to this register. WOAssuming that set value = n, UiBRG divides the count source by n + 1 00h to FFh Write to this register w hile serial interface is neither transmitting nor receiving.

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 183 of 390 REJ09B0185-0241 Figure 17.7 UiMR Register UARTi Transmit/Receiv e Mode Register (i=0 to 2) Address After Reset 03A0h, 03A8h, 0378h 00h Bit Symbol Function RW NOTES : Internal/External Clock Select Bit 0 : Internal clock 1 : External clock (1) Symbol SMD1 Bit Name U0MR to U2MR IOPOL RW RW RW CKDIR PRY E RW RWStop Bit Length Select Bit 0 : 1 stop bit 1 : 2 stop bitsSTPS b7 b6 b5 b4 b3 b2 b1 b0 SMD2 RW SMD0 RW Serial I/O Mode Select Bit (2) b2 b1 b0 0 0 0 : Serial interface disabled 0 0 1 : Clock synchronous serial I/O mode 0 1 0 : I 2C mode (3) 1 0 0 : UART mode transfer data 7 bits long 1 0 1 : UART mode transfer data 8 bits long 1 1 0 : UART mode transfer data 9 bits long Do not set except above RW To receive data, set the corresponding port direction bit for each RXDi pin to “0” (input mode). Set the corresponding port direction bit for SCL and SDA pins to “0” (input mode). Odd/Even Parity Select Bit Effective w hen PRYE = 1 0 : Odd parity 1 : Even parity PRY Parity Enable Bit TXD, RXD I/O Polarity Reverse Bit 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse Set the corresponding port direction bit for each CLKi pin to “0” (input mode).

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 184 of 390 REJ09B0185-0241 Figure 17.8 UiC0 Register UARTi Transmit/Receive Control Register 0 (i=0 to 2) After R eset 00001000b Bit Symbol RW NOTES : Selected by PCLK1 bit in the PCLKR register. Bit Name U0C0 to U2C0 Symbol CLK1 CLK0 bit in the UCON register = 0 (CTS0 /RTS0 not separated). 0 : TXDi/SDAi and SCLi pins are CMOS output 1 : TXDi/SDAi and SCLi pins are N-channel open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge 0 : LSB first 1 : MSB first RW TXEPT CKPOL RW Transmit Register Empty Flag RW 0 : CTS/ RTS ____ function enabled 1 : CTS ____ /RTS ____ function disabled (P6_0, P6_4 and P7_3 can be used as I/O ports) b7 b6 b5 b4 b3 b2 b1 b0 Effective w hen CRD = 0 CTS1 /RTS1 can be used w hen the CLKMD1 bit in the UCON register = 0 (only CLK1 output) and the RCSP Transf er Format Select Bit (3)UFORM RW TXD2/SDA2 and SCL2 are N-channel open-drain output. Cannot be set to the CMOS output. No NCH bit in U2C0 register is assigned. When w rite, set to “0”. The UFORM bit is enabled w hen the SMD2 to SMD0 bits in the UiMR register are set to “001b” (clock synchronous serial I/O mode), or “101b” (UART mode, 8-bit transfer data). Set this bit to “1” w hen the SMD2 to SMD0 bits are set to “010b” (I2C mode), and to “0” w hen the SMD2 to SMD0 bits are set to “100b” (UART mode, 7-bit transfer data) or “110b” (UART mode, 9-bit transfer data). Set the corresponding port direction bit for each CLKi pin to “0” (input mode). RO CRD CTS/ RTS Disable Bit Select Bit (4) RW UiBRG Count Source Select Bit (6) CTS/ RTS Function RW RW 1 : RTS function is selected 0 : CTS function is selected (1) 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) When changing the CLK1 to CLK0 bits, set the UiBRG register. 03A4h, 03ACh, 037Ch Address Function b1 b0 0 0 : f1SIO or f2SIO is selected (5) 0 1 : f8SI O is selected 1 0 : f32SIO is selected 1 1 : Do not set to this value CRS Data Output Select Bit (2) NCH CLK Polarity Select Bit

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 185 of 390 REJ09B0185-0241 Figure 17.9 U0C1 to U2C1 Registers UARTi Transmit/Receive Control Register 1 (i=0, 1) Address After Reset 03A5h, 03ADh 00XX0010b Bit Symbol Function RW NOTES : Receive Complete Flag Bit Name U0C1, U1C1 TI RWTransmit Enable Bit 0 : Transmission disabled 1 : Transmission enabled Nothing is assigned. When w rite, set to “0”. When read, these contents are indeterminate. RE b7 b6 b5 b4 b3 b2 b1 b0 Symbol TE (b5-b4) RI 0 : No data present in UiRB register 1 : Data present in UiRB register ROTransmit Buffer Empty Flag 0 : Data present in UiTB register 1 : No data present in UiTB register Receive Enable Bit 0 : Reception disabled 1 : Reception enabled RW The UiLCH bit is enabled w hen the SMD2 to SMD0 bits in the UiMR register are set to “001b” (clock synchronous serial I/O mode), “100b” (UART mode, 7-bit transfer data), or “101b” (UART mode, 8-bit transfer data). Set this bit to “0” w hen the SMD2 to SMD0 bits are set to “010b” (I2C mode) or “110b” (UART mode, 9-bit transfer data). RO Data Logic Select Bit (1) Error Signal Output Enable Bit 0 : No reverse 1 : Reverse 0 : Output disabled 1 : Output enabledUiERE RW UiLCH RW UART2 Transmit/Receive Control Register 1 Address After Reset 037Dh 00000010b Bit Symbol Function RW NOTES : 1. The U2LCH bit is enabled w hen the SMD2 to SMD0 bits in the U2MR register are set to “001b” (clock synchronous serial I/O mode), “100b” (UART mode, 7-bit transfer data), or “101b” (UART mode, 8-bit transfer data). Set this bit to “0” w hen the SMD2 to SMD0 bits are set to “010b” (I2C mode) or “110b” (UART mode, 9-bit transfer data). U2ERE RW U2LCH RWData Logic Select Bit (1) Error Signal Output Enable Bit 0 : No reverse 1 : Reverse 0 : Output disabled 1 : Output enabled TE U2RRM RI UART2 Continuous Receive Mode Enable Bit Transmit Buffer Empty Flag Receive Enable Bit Symbol b3 b2 b1 b0b7 b6 b5 b4 U2C1 TI U2IRS RWUART2 Transmit Interrupt Factor Select Bit 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) RWTransmit Enable bit 0 : Transmission disabled 1 : Transmission enabled RE 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled RW Receive Complete Flag Bit Name 0 : No data present in U2RB register 1 : Data present in U2RB register RO0 : Data present in U2TB register 1 : No data present in U2TB register 0 : Reception disabled 1 : Reception enabled RW RO

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 186 of 390 REJ09B0185-0241 Figure 17.10 UCON and UiSMR Registers UART Transmit/Receive Control Register 2 Address After Reset 03B0h X0000000b Bit Symbol Function RW 0 : CTS/ RTS shared pin 1 : CTS /RTS separated (CTS0 supplied from the P6_4 pin) NOTES : 1. When using multiple transfer clock output pins, make sure the follow ing conditions are met: CKDIR bit in the U1MR register = 0 (internal clock) RCSP Nothing is assigned. When w rite, set to “0”. When read, its content is indeterminate. Separate UART0 (b7) — CTS/ RTS Bit RW Effective w hen CLKMD1 = 1 0 : Clock output from CLK1 1 : Clock output from CLKS1 U0RRM UA RT0 Trans mit Interrupt Factor Select Bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) UA RT1 Trans mit Interrupt Factor Select Bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) UART0 Continuous Receive Mode Enable Bit UART1 CLK/CLKS Select Bit 1 (1) Symbol U1IRS U0IRS Bit Name UCON b7 b6 b5 b4 b3 b2 b1 b0 RW0 : Continuous receive mode disabled 1 : Continuous receive mode enable RW RW RW U1RRM UART1 Continuous Receive Mode Enable Bit CLKMD1 CLKMD0 UART1 CLK/CLKS Select Bit 0 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled RW 0 : CLK output is only CLK1 1 : Transfer clock output from multiple pins function selected RW UARTi Special Mode Register (i=0 to 2) After R eset X0000000b Bit Symbol RW (b3) (4) NOTES : RW Set to “0” 0 : No auto clear function 1 : A uto clear at occurrence of bus collision Underflow signal of Timer A3 in UART0, underflow signal of Timer A4 in UART1, underflow signal of Timer A0 in UA RT2. RW SCLL sync output enable bit RWBus Collision Detect Sampling Clock Select Bit 0 : Disable 1 : Enable 0 : Rising edge of transfer clock 1 : Underflow signal of Timer Aj (2) Address 0 : Other than I 2C mode 1 : I2C mode 0 : Update per bit 1 : Update per byte Bit Name Symbol Function IICM 036Fh, 0373h, 0377hU0SMR to U2SMR RW I2C Mode Select Bit RW RW(1)0 : STOP condition detected 1 : START condition detected (busy) b7 b6 b5 b4 b3 b2 b1 b0 LSYN (4) Auto Clear Function Select Bit of Transmit Enable Bit Arbitration Lost Detecting Flag Control Bit Bus Busy Flag ABSC S BBS ABC Reserved Bit AC SE The function of the bit 3 varies depending on the product. If the product is M3062LFGPFP or M3062LFGPGP, the bit 3 becomes the LSYN bit. If the product is other than M3062LFGPFP and M3062LFGPGP, the bit 3 is reserved. Therefore, set it to 0. (The LSYN bit is an SCLL sync output enable bit.) When the LSYN bit is set to “1” and the SCLi pin outputs an "L" level signal, the data bit, such as the P6_2 bit in the P6 register for SCL0 pin, the P6_6 bit in the P6 register for SCL1 pin, and the P7_1 bit in the P7 register for SCL2 pin, is set to “1”. Transmit Start Condition Select Bit (b7) — SSS RW Nothing is assigned. When w rite, set to “0”. When read, its content is indeterminate. 0 : Not synchronized to RXDi 1 : Synchronized to RXDi (3) The BBS bit is set to “0” by w riting “0” in a program (Writing “1” has no effect). When a transfer begins, the SSS bit is set to “0” (Not synchronized to RXDi).

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 187 of 390 REJ09B0185-0241 Figure 17.11 UiSMR2 and UiSMR3 Registers UARTi Special Mode Register 2 (i=0 to 2) After R eset X0000000b Bit Symbol RW SDA Output Disable Bit (b7) — SDHI RW Nothing is assigned. When w rite, set to “0”. When read, its content is indeterminate. 0: Enabled 1: Disabled (high-impedance) SWC2 ALS SCL Wait Output Bit 2 Clock-Synchronous Bit SCL Wait Output Bit STAC SWC b3 b2 b1 b0b7 b6 b5 b4 RWUARTi Initialization Bit RWI2C Mode Select Bit 2 0 : Disabled 1 : Enabled Address See Table 17.13 I2C Mode Functions 0 : Disabled 1 : Enabled Bit Name Symbol Function 036Eh, 0372h, 0376h IICM2 0: Transfer clock 1: “L” output RW SDA Output Stop Bit U0SMR2 to U2SMR2 CSC RW RW RW 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled UARTi special mode register 3 (i=0 to 2) After R eset 000X0X0Xb Bit Symbol RW NOTES : RW RW 0 : Without clock delay 1 : With clock delay Function 036Dh, 0371h, 0375hU0SMR3 to U2SMR3 Address b7 b6 b5 b4 b3 b2 b1 Bit Name Symbol Clock Phase Set Bit (b4) (b2) CKPH Clock Output Select Bit Nothing is assigned. When w rite, set to “0”. When read, its content is indeterminate. Nothing is assigned. When w rite, set to “0”. When read, its content is indeterminate. (b0) Nothing is assigned. When w rite, set to “0”. When read, its content is indeterminate. DL1 RW DL0 NODC 0 : CLKi is CMOS output 1 : CLKi is N-channel open drain output RW SDAi Digital Delay Setup Bit (1, 2) b7 b6 b5 0 0 0 : Without delay 0 0 1 : 1 to 2 cycle(s) of UiBR G count source 0 1 0 : 2 to 3 cycles of UiBRG count source 0 1 1 : 3 to 4 cycles of UiBRG count source 1 0 0 : 4 to 5 cycles of UiBRG count source 1 0 1 : 5 to 6 cycles of UiBRG count source 1 1 0 : 6 to 7 cycles of UiBRG count source 1 1 1 : 7 to 8 cycles of UiBRG count source The amount of delay varies w ith the load on SCLi and SDAi pins. Also, w hen using an external clock, the amount of delay increases by about 100 ns. DL2 RW The DL2 to DL0 bits are used to generate a delay in SDAi output by digital means during I 2C mode. In other than I2C mode, set these bits to “000b” (no delay).

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 188 of 390 REJ09B0185-0241 Figure 17.12 UiSMR4 Register UARTi Special Mode Register 4 (i=0 to 2) After R eset 00h Bit Symbol RW NOTES : 1. Set to “0” w hen each condition is generated. SCLHI RW AC KC SCL Output Stop Enable Bit 0 : Disabled 1 : Enabled SWC9 RWSCL Wait Bit 3 0 : SCL “L” hold disabled 1 : SCL “L” hold enabled STSPSEL 0 : Start and stop conditions not output 1 : Start and stop conditions output RW RW AC KD STPREQ RSTA REQ STAREQ RW b7 b6 b5 b4 b3 b2 b1 U0SMR4 to U2SMR4 Bit Name Symbol Function 036Ch, 0370h, 0374h Address RW RW RW ACK Data Output Enable Bit 0 : Serial interface data output 1 : ACK data output 0 : Clear 1 : Start Restart Condition Generate Bit (1) SCL,SDA Output Select Bit ACK Data Bit 0 : ACK 1 : NACK Start Condition Generate Bit (1) 0 : Clear 1 : Start Stop Condition Generate Bit (1) 0 : Clear 1 : Start

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 189 of 390 REJ09B0185-0241

17.1.1 Clock Synchronous Serial I/O Mode

The clock synchronous serial I/O mode uses a transfer cl ock to transmit and receive data. Table 17.1 lists the Clock Synchronous Serial I/O Mode Specifications. Table 17.2 lists the Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode. NOTES: 1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the CKPOL bit in the UiC0 register = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. 2. If an overrun error occurs, the receive data of UiRB register will be indeterminate. The IR bit in the SiRIC register does not change. 3. The U0IRS and U1IRS bits respectively are the bits 0 and 1 in the UCON register; the U2IRS bit is the bit 4 in the U2C1 register. Table 17.1 Clock Synchronous Serial I/O Mode Specifications Item Specification Transfer Data Format Transfer data length: 8 bits Transfer Clock • CKDIR bit in the UiMR(i=0 to 2) register = 0 (internal clock) : fj/ (2(n+1)) fj = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of UiBRG register 00h to FFh

• CKDIR bit = 1 (external clock) : Input from CLKi pin Transmission, Reception Control Selectable from CTS function, RTS function or CTS/RTS function disable Transmission Start Condition Before transmission can start, meet the following requirements (1)
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in UiTB register)
• I f C T S function is selected, input on the CTSi pin = L Reception Start Condition Before reception can start, meet the following requirements (1)
• The RE bit in the UiC1 register = 1 (reception enabled)
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register) Interrupt Request Generation Timing For transmission, one of the following conditions can be selected
• The UiIRS bit (3) = 0 (transmit buffer empty): when transferring data from the UiTB register to the UARTi transmit register (at start of transmission)
• The UiIRS bit =1 (transfer completed): when the serial interface finished sending data from the UARTi transmit register For reception
• When transferring data from the UARTi receive register to the UiRB register (at completion of reception) Error Detection Overrun error (2) This error occurs if the serial interface started receiving the next data before reading the UiRB register and received the 7th bit of the next data Select Function • CLK polarity selection Transfer data input/output can be chosen to occur synchronously with the rising or the falling edge of the transfer clock
• LSB first, MSB first selection Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected
• Continuous receive mode selection Reception is enabled immediately by reading the UiRB register
• Switching serial data logic This function reverses the logic value of the transmit/receive data
• Transfer clock output from multiple pins selection (UART1) The output pin can be selected in a program from two UART1 transfer clock pins that have been set
• Separate CTS /RTS pins (UART0) CTS0 and RTS0 are input/output from separate pins

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 190 of 390 REJ09B0185-0241 NOTES: 1. Set the bit 4 and bit 5 in the U0C1 and U1C1 register to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits in the UCON register. 2. TXD2 pin is N channel open-drain output. Se t the NCH bit in the U2C0 register to “0”. 3. Not all register bits are described above. Set those bits to “0” when writing to the registers in clock synchronous serial I/O mode. i=0 to 2 Table 17.2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode Register Bit Function UiTB (3) 0 to 7 Set transmission data UiRB (3) 0 to 7 Reception data can be read OER Overrun error flag UiBRG 0 to 7 Set a bit rate UiMR (3) SMD2 to SMD0 Set to “001b” CKDIR Select the internal clock or external clock IOPOL Set to “0” UiC0 CLK1 to CLK0 Select the coun t source for the UiBRG register CRS Select CTS or RTS to use TXEPT Transmit register empty flag CRD Enable or disable the CTS or RTS function NCH Select TXDi pin output mode (2) CKPOL Select the tran sfer clock polarity UFORM Select the LSB first or MSB first UiC1 TE Set this bit to “1” to enable transmission/reception TI Transmit buffer empty flag RE Set this bit to “1” to enable reception RI Reception complete flag U2IRS (1) Select the source of UART2 transmit interrupt U2RRM (1) Set this bit to “1” to use continuous receive mode UiLCH Set this bit to “1” to use inverted data logic UiERE Set to “0” UiSMR 0 to 7 Set to “0” UiSMR2 0 to 7 Set to “0” UiSMR3 0 to 2 Set to “0” NODC Select clock output mode 4 to 7 Set to “0” UiSMR4 0 to 7 Set to “0” UCON U0IRS, U1IRS Select th e source of UART0/UART1 transmit interrupt U0RRM, U1RRM Set this bit to “1” to use continuous receive mode CLKMD0 Select the transfer clo ck output pin when CLKMD1 = 1 CLKMD1 Set this bit to “1” to output UART1 transfer clock from two pins RCSP Set this bit to “1” to accept as input the CTS0 signal of the UART0 from the P6_4 pin

7 Set to “0”

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 191 of 390 REJ09B0185-0241 Table 17.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table 17.3 shows pin functions for the case where the multiple transfer clock output pin select function is deselected. Table 17.4 lists the P6_4 Pin Functions during clock synchronous serial I/O mode. Note that for a period from when the UARTi operating mode is selected to when tr ansfer starts, the TXDi pin outputs an “H” (If the N- channel open-drain output is selected, this pin is in a high-impedance state). : “0” or “1” NOTES: 1. In addition to this, set the CRD bit in the U0C0 register to “0” (CTS0/RTS0 enabled) and the CRS bit in the U0C0 register to “1” (RTS0 selected). 2. When the CLKMD1 bit = 1 and the CLKMD0 bit = 0, the following logic levels are output:

• High if the CLKPOL bit in the U1C0 register = 0
• Low if the CLKPOL bit = 1 Table 17.3 Pin Functions (when not select multiple transfer clock output pin function) Pin Name Function Method of Selection TXDi (i = 0 to 2) (P6_3, P6_7, P7_0) Serial Data Output (Outputs dummy data when performing reception only) RXDi (P6_2, P6_6, P7_1) Serial Data Input PD6_2 bit and PD6_6 bit in the PD6 register = 0, PD7_1 bit in the PD7 register = 0 (Can be used as an input port when performing transmission only) CLKi (P6_1, P6_5, P7_2) Transfer Clock Output CKDIR bit in the UiMR register = 0 Transfer Clock Input CKDIR bit = 1 PD6_1 bit and PD6_5 bit in the PD6 register = 0, PD7_2 bit in the PD7 register = 0 CTSi /RTSi (P6_0, P6_4, P7_3) CTS Input CRD bit in the UiC0 register = 0 CRS bit in the UiC0 register = 0 PD6_0 and PD6_4 bit in the PD6 register = 0, PD7_3 bit in the PD7 register = 0 RTS Output CRD bit = 0 CRS bit = 1 I/O Port CRD bit = 1 Table 17.4 P6_4 Pin Functions Pin Function Bit Set Value U1C0 Register UCON Register PD6 Register CRD CRS RCSP CLKMD1 CLKMD0 PD6_4 P6_4 1 − 00 − Input: 0, Output: 1 CTS1 0000 − 0 RTS1 0100 −− CTS0 (1) 0010 − 0

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 192 of 390 REJ09B0185-0241 Figure 17.13 Transmit and Receive Operation D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Tc TCLK Pulse stops because the TE bit is set to “0” Data is set in the UiTB register Data is transferred from the UiTB register to the UARTi transmit register Transfer clock TE bit in UiC1 register TI bit in UiC1 register CLKi TXDi TXEPT bit in UiC0 register “H” “L” “0” “1” “0” “1” “0” “1” CTSi IR bit in SiTIC register “0” “1” Set to “0” by an interrupt request acknowledgement or by program Pulse stops because an “H” signal is applied to CTSi 1 / fEXT Dummy data is set in the to UiTB register CLKi RXDi RTSi “H” “L” “0” “1” “0” “1” “0” “1” RE bit in UiC1 register “0” “1” Data is transferred from the UiTB register to the UARTi transmit register Read by the UiRB registerData is transferred from the UARTi receive register to the UiRB register “0” “1” D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D0 D1 D2 D3 D4 D5D7D6 “0” “1” TE bit in UiC1 register TI bit in UiC1 register OER flag in UiRB register IR bit in SiRIC register RI bit in UiC1 register i=0 to 2 Received data is taken in An “L” signal is applied when the UiRB register is read i = 0 to 2 (1) Example of Transmit Timing (when internal clock is selected) The above timing diagram applies to the case where the register bits are set as follows:

• CKDIR bit in UiMR register = 0 (internal clock)
• CRD bit in UiC0 register = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected)
• CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock)
• UiIRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty): U0IRS bit is bit 0 in UCON register U1IRS bit is bit 1 in UCON register U2IRS bit is bit 4 in U2C1 register TC = TCLK = 2(n + 1) / fj fj: frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO) n: value set to UiBRG register (2) Example of Receive Timing (when external clock is selected) Set to “0” by an interrupt request acknowledgement or by program Make sure the following conditions are met when input to the CLKi pin before receiving data is high:
• TE bit in UiC0 register = 1 (transmit enabled)
• RE bit in UiC0 register = 1 (receive enabled)
• Write dummy data to the UiTB register The above timing diagram applies to the case where the register bits are set as follows:
• CKDIR bit in UiMR register = 1 (external clock)
• CRD bit in UiC0 register = 0 (CTS/RTS enabled), CRS bit = 1 (RTS selected)
• CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock) fEXT: frequency of external clock

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 193 of 390 REJ09B0185-0241

17.1.1.1 Counter Measure for Communication Error Occurs

If a communication error occurs while transmitting or re ceiving in clock synchronous serial I/O mode, follow the procedures below.

• Resetting the UiRB register (i=0 to 2) (1) Set the RE bit in the UiC1 re gister to “0” (reception disabled) (2) Set the SMD2 to SMD0 bits in the UiMR register to “000b” (Serial interface disabled) (3) Set the SMD2 to SMD0 bits in the UiMR register to “001b” (Clock synchronous serial I/O mode) (4) Set the RE bit in the UiC1 re gister to “1” (reception enabled)
• Resetting the UiTB register (i=0 to 2) (1) Set the SMD2 to SMD0 bits in the UiMR register “000b” (Serial interface disabled) (2) Set the SMD2 to SMD0 bits in the UiMR register “001b” (Clock synchronous serial I/O mode) (3) “1” is written to RE bit in the UiC1 register (transmission enabled), regardless of the TE bit in the UiCi register

17.1.1.2 CLK Polarity Select Function

Use the CKPOL bit in the UiC0 register (i = 0 to 2) to select the transfer clock polarity. Figure 17.14 shows the Transfer Clock Polarity. Figure 17.14 Transfer Clock Polarity (2) When the CKPOL bit = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock) D1 D2 D3 D4 D5 D6 D7 D1 D2 D3 D4 D5 D6 D7 TXDi RXDi CLKi (1) When the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) D1 D2 D3 D4 D5 D6 D7D0 D1 D2 D3 D4 D5 D6 D7D0 TXDi RXDi CLKi NOTES: 1. This applies to the case where the UFORM bit in the UiC0 register = 0 (LSB first) and the UiLCH bit in the UiC1 register = 0 (no reverse). 2. When not transferring, the CLKi pin outputs a high signal. 3. When not transferring, the CLKi pin outputs a low signal. i = 0 to 2 (NOTE 2) (NOTE 3)

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 194 of 390 REJ09B0185-0241

17.1.1.3 LSB First/MSB First Select Function

Use the UFORM bit in the UiC0 register (i = 0 to 2) to select the transfer format. Figure 17.15 shows the Transfer Format. Figure 17.15 Transfer Format

17.1.1.4 Continuous Receive Mode

In continuous receive mode, receive operation becomes enable when the receive buffer register is read. It is not necessary to write dummy data into the transmit buffer register to enable receive operation in this mode. However, a dummy read of the receive buffer register is required when starting the operating mode. When the UiRRM bit (i = 0 to 2) = 1 (continuous receive mo de), the TI bit in the UiC1 register is set to “0” (data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit = 1, do not write dummy data to the UiTB register in a program. The U0RRM and U1RRM bits are th e bit 2 and bit 3 in the UCON register, respectively, and the U2RRM bit is the bit 5 in the U2C1 register. (1) When the UFORM bit in the UiC0 register = 0 (LSB first) D1 D2 D3 D4 D5 D6 D7 D1 D2 D3 D4 D5 D6 D7 TXDi RXDi CLKi (2) When the UFORM bit = 1 (MSB first) D6 D5 D4 D3 D2 D1 D0D7 D7 D6 D5 D4 D3 D2 D1 D0 TXDi RXDi CLKi NOTES: 1. This applies to the case where the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) and the UiLCH bit in the UiC1 register = 0 (no reverse). i = 0 to 2

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 195 of 390 REJ09B0185-0241

17.1.1.5 Serial Data Logic Switching Function

When the UiLCH bit in the UiC1 register (i = 0 to 2) = 1 (reverse), the data written to the UiTB register has its logic reversed before being transmitted. Similarly, the received data has it s logic reversed when read from the UiRB register. Figure 17.16 shows Serial Data Logic Switching. Figure 17.16 Serial Data Logic Switching

17.1.1.6 Transfer Clock Output From Multiple Pins (UART1)

Use the CLKMD1 to CLKMD0 bits in the UCON register to select one of the two transfer clock output pins (see Figure 17.17). This function can be used when the selected transfer clock for UART1 is an internal clock. Figure 17.17 Transfer Clock Ou tput from Multiple Pins D0 D1 D2 D3 D4 D5 D6 D7 Transfer Clock TXDi (No Reverse) “H” “L” “H” “L” TXDi (Reverse) D0 D1 D2 D3 D4 D5 D6 D7 “H” “L” (1) When The UiLCH Bit in The UiC1 Register = 0 (No Reverse) Transfer Clock “H” “L” (2) When The UiLCH Bit = 1 (Reverse) NOTES : 1. This applies to the case where the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) and the UFORM bit = 0 (LSB first). i = 0 to 2 Microcomputer TXD1 (P6_7) CLKS1 (P6_4) CLK1 (P6_5) IN CLK IN CLK NOTES : 1. This applies to the case where the CKDIR bit in the U1MR register= 0 (internal clock) and the CLKMD1 bit in the UCON register = 1 (transfer clock output from multiple pins). Transfer enabled when the CLKMD0 bit in the UCON register = 0 Transfer enabled when the CLKMD0 bit = 1

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 196 of 390 REJ09B0185-0241

17.1.1.7 CTS /RTS Function

When the CTS function is used transmit and receive oper ation start when “L” is applied to the CTSi/RTSi (i=0 to 2) pin. Transmit and receive operation begins when the CTSi /RTSi pin is held “L”. If the “L” signal is switched to “H” during a transmit or receive operation, the operation stops before the next data. When the RTS function is used, the CTSi /RTSi pin outputs on “L” signal when the microcomputer is ready to receive. The output level becomes “H” on the first falling edge of the CLKi pin.

• CRD bit in UiC0 register = 1 (disable CTS/RTS of UART0) CTSi/RTSi pin is programmable I/O function
• CRD bit = 0, CRS bit = 0 (CTS function is selected) CTSi /RTSi pin is CTS function
• CRD bit = 0, CRS bit = 1 (RTS function is selected) CTSi /RTSi pin is RTS function

17.1.1.8 CTS /RTS Separate Function (UART0)

This function separates CTS0/RTS0, outputs RTS0 from the P6_0 pin, and accepts as input the CTS0 from the P6_4 pin. To use this function, set the register bits as shown below.

• CRD bit in U0C0 register = 0 (enable CTS/RTS of UART0)
• CRS bit in U0C0 register = 1 (output RTS of UART0)
• CRD bit in U1C0 register = 0 (enable CTS/RTS of UART1)
• CRS bit in U1C0 register = 0 (input CTS of UART1)
• RCSP bit in UCON register = 1 (inputs CTS0 from the P6_4 pin)
• CLKMD1 bit in UCON register = 0 (CLKS1 not used) Note that when using the CTS/RTS separate function, CTS/RTS of UART1 separate function cannot be used. Figure 17.18 CTS /RTS Separate Function Microcomputer TXD0 (P6_3) RXD0 (P6_2) IN OUT CTS RTSCTS0 (P6_4) RTS0 (P6_0) IC CLK0 (P6_1) CLK

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 197 of 390 REJ09B0185-0241

17.1.2 Clock Asynchronous Se rial I/O (UART) Mode

The UART mode allows transmitting and receiving data after setting the de sired bit rate and transfer data format. Table 17.5 lists the UART Mode Specifications. NOTES: 1. If an overrun error occurs, the receive data of UiRB register will be indeterminate. The IR bit in the SiRIC register does not change. 2. The U0IRS and U1IRS bits are bits 0 and 1 in the UCON register. The U2IRS bit is bit 4 in the U2C1 register. 3. The timing at which the framing error flag and the parity error flag are set is detected when data is transferred from the UARTi receive register to the UiRB register. Table 17.5 UART M ode Specifications Item Specification Transfer Data Format • Character bit (transfer data): Selectable from 7, 8 or 9 bits

• Start bit: 1 bit
• Parity bit: Selectable from odd, even, or none
• Stop bit: Selectable from 1 or 2 bits Transfer Clock • CKDIR bit in the UiMR(i=0 to 2) register = 0 (internal clock) : fj/ (16(n+1)) fj = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of UiBRG register 00h to FFh
• CKDIR bit = 1 (external clock) : fEXT/(16(n+1))
• fEXT: Input from CLKi pin n :Setting value of UiBRG register 00h to FFh Transmission, Reception Control Selectable from CTS function, RTS function or CTS/RTS function disable Transmission Start Condition Before transmission can start, meet the following requirements
• The TE bit in the UiC1 register= 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in UiTB register)
• I f C T S function is selected, input on the CTSi pin = L Reception Start Condition Before reception can start, meet the following requirements
• The RE bit in the UiC1 register = 1 (reception enabled)
• Start bit detection Interrupt Request Generation Timing For transmission, one of the following conditions can be selected
• The UiIRS bit (2) = 0 (transmit buffer empty): when transferring data from the UiTB register to the UARTi transmit register (at start of transmission)
• The UiIRS bit =1 (transfer completed): when the serial interface finished sending data from the UARTi transmit register For reception
• When transferring data from the UARTi receive register to the UiRB register (at completion of reception) Error Detection • Overrun error (1) This error occurs if the serial interface started receiving the next data before reading the UiRB register and received the bit one before the last stop bit of the next data
• Framing error (3) This error occurs when the number of stop bits set is not detected
• Parity error (3) This error occurs when if parity is enabled, the number of “1” in parity and character bits does not match the number of “1” set
• Error sum flag This flag is set to “1” when any of the overrun, framing or parity errors occur Select Function • LSB first, MSB first selection Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected
• Serial data logic switch This function reverses the logic of the transmit/receive data. The start and stop bits are not reversed.
• TXD, RXD I/O polarity switch This function reverses the polarities of the TXD pin output and RXD pin input. The logic levels of all I/O data is reversed.
• Separate CTS/RTS pins (UART0) CTS0 and RTS0 are input/output from separate pins

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 198 of 390 REJ09B0185-0241 NOTES: 1. The bits used for transmit/receive data are as follows: Bit 0 to bit 6 when transfer data is 7 bits long; bit 0 to bit 7 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long. 2. Set the bit 4 to bit 5 in the U0C1 and U1C1 register s to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are included in the UCON register. 3. TXD2 pin is N channel open-drain output. Set the NCH bit in the U2C0 register to “0”. i=0 to 2 Table 17.6 Registers to Be Used and Settings in UART Mode Register Bit Function UiTB 0 to 8 Set transmission data (1) UiRB 0 to 8 Reception data can be read (1) OER,FER,PER,SUM Error flag UiBRG 0 to 7 Set a bit rate UiMR SMD2 to SMD0 Set these bits to “10 0b” when transfer data is 7 bits long Set these bits to “101b” when transfer data is 8 bits long Set these bits to “110b” when transfer data is 9 bits long CKDIR Select the internal clock or external clock STPS Select the stop bit PRY, PRYE Select whether parity is included and whether odd or even IOPOL Select the TXD/RXD input/output polarity UiC0 CLK0, CLK1 Select the count source for the UiBRG register CRS Select CTS or RTS to use TXEPT Transmit register empty flag CRD Enable or disable the CTS or RTS function NCH Select TXDi pin output mode (3) CKPOL Set to “0” UFORM LSB first or MSB first can be selected when transfer data is 8 bits long. Set this bit to “0” when transfer data is 7 or 9 bits long. UiC1 TE Set this bit to “1” to enable transmission TI Transmit buffer empty flag RE Set this bit to “1” to enable reception RI Reception complete flag U2IRS (2) Select the source of UART2 transmit interrupt U2RRM (2) Set to “0” UiLCH Set this bit to “1” to use inverted data logic UiERE Set to “0” UiSMR 0 to 7 Set to “0” UiSMR2 0 to 7 Set to “0” UiSMR3 0 to 7 Set to “0” UiSMR4 0 to 7 Set to “0” UCON U0IRS, U1IRS Select the source of UART0/UART1 transmit interrupt U0RRM, U1RRM Set to “0” CLKMD0 Invalid because CLKMD1 = 0 CLKMD1 Set to “0” RCSP Set this bit to “1” to accept as input CTS0 signal of UART0 from the P6_4 pin

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 199 of 390 REJ09B0185-0241 Table 17.7 lists the functions of the input/output pins during UART mode. Table 17.8 lists the P6_4 Pin Functions. Note that for a period from when the UARTi operating mode is selected to when transfer starts, the TXDi pin outputs an “H” (If the N-channel open-drain output is selected, this pin is in a high-impedance state). NOTES: 1. In addition to this, set the CRD bit in the U0C0 register to “0” (CTS0/RTS0 enabled) and the CRS bit in the U0C0 register to “1” (RTS0 selected). Table 17.7 I/O Pin Functions Pin Name Function Method of Selection TXDi (i = 0 to 2) (P6_3, P6_7, P7_0) Serial Data Output (“H” outputs when performing reception only) RXDi (P6_2, P6_6, P7_1) Serial Data Input PD6_2 bit and PD6_6 bit in the PD6 register = 0, PD7_1 bit in the PD7 register = 0 (Can be used as an input port when performing transmission only) CLKi (P6_1, P6_5, P7_2) Input/Output Port CKDIR bit in the UiMR register = 0 Transfer Clock Input CKDIR bit = 1 PD6_1 bit and PD6_5 bit in the PD6 register = 0, PD7_2 bit in the PD7 register = 0 CTSi /RTSi (P6_0, P6_4, P7_3) CTS Input CRD bit in the UiC0 register = 0 CRS bit in the UiC0 register = 0 PD6_0 bit and PD6_4 bit in the PD6 register = 0, PD7_3 bit in the PD7 register = 0 RTS Output CRD bit = 0 CRS bit = 1 Input/Output Port CRD bit = 1 Table 17.8 P6_4 Pin Functions Pin Function Bit Set Value U1C0 Register UCON Register PD6 Register CRD CRS RCSP CLKMD1 PD6_4 P6_4 1 − 0 0 Input: 0, Output: 1 CTS1 0000 0 RTS1 0100 − CTS0 (1) 0010 0

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 200 of 390 REJ09B0185-0241 Figure 17.19 Transmit Operation D0 D1 D2 D3 D4 D5 D6 D7ST P Parity bit TXDi CTSi “0” “1” “0” “1” “H” “0” “1” “0” “1” Set to “0” by an interrupt request acknowledgement or by program D0 D1 D2 D3 D4 D5 D6 D7ST P D0 D1ST TXDi “0” “1” “0” “1” “0” “1” Transfer Clock Tc “0” “1” Set to “0” by an interrupt request acknowledgement or by program Tc Transfer Clock Stop bit Data is set in the UiTB register Data is transferred from the UiTB register to the UARTi transmit register D0 D1 D2 D3 D4 D5 D6 D7ST D8 D0 D1 D2 D3 D4 D5 D6 D7ST D8 D0 D1STSP SP The transfer clock stops momentarily, because an “H” single is applied to the CTS pin, when the stop bit is verified. The transfer clock resumes running as soon as an “L” single is applied to the CTS pin. Data is set in the UiTB register SP Data is transferred from the UiTB register to the UARTi transmit register TE bit in UiC1 register TI bit in UiC1 register TXEPT bit in UiC0 register IR bit in SiTIC register TE bit in UiC1 register TI bit in UiC1 register TXEPT bit in UiC0 register IR bit in SiTIC register i=0 to 2 “L” Pulse stops because the TE bit is set to “0” SPSP Start bit SP (1) 8-bit Data Transmit Timing (with a parity and 1 stop bit) (1) 9-bit Data Transmit Timing (with no parity and 2 stop bits) Stop bitStart bit Stop bit TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO) fEXT : frequency of UiBRG count source (external clock) n : value set to UiBRG The above timing diagram applies to the case where the register bits are set as follows:

• PRYE bit in UiMR register = 1 (parity enabled)
• STPS bit in UiMR register = 0 (1 stop bit)
• CRD bit in UiC0 register = 0 (CTS/RTS enabled) and CRS bit = 0 (CTS selected)
• UiIRS bit = 1 (an interrupt request occurs when transmit completed): U0IRS bit is bit 0 in UCON register U1IRS bit is bit 1 in UCON register U2IRS bit is bit 4 in U2C1 register i=0 to 2 TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO) fEXT : frequency of UiBRG count source (external clock) n : value set to UiBRG The above timing diagram applies to the case where the register bits are set as follows:
• PRYE bit in UiMR register = 0 (parity disabled)
• STPS bit in UiMR register = 1 (2 stop bits)
• CRD bit in UiC0 register = 1 (CTS/RTS disabled)
• UiIRS bit = 0 (an interrupt request occurs when transmit buffer becomes empty): U0IRS bit is bit 0 in UCON register U1IRS bit is bit 1 in UCON register U2IRS bit is bit 4 in U2C1 register

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 201 of 390 REJ09B0185-0241 Figure 17.20 Receive Operation

17.1.2.1 Bit Rate

In UART mode, the frequency set by the UiBRG register (i =0 to 2) divided by 16 become the bit rates. Table 17.9 lists Example of Bit Rates and Settings. Table 17.9 Example of Bit Rates and Settings Bit Rate (bps) Count Source of UiBRG Peripheral Function Clock : 16MHz Peripheral Function Clock : 24MHz Set Value of UiBRG : n Bit Rate (bps) Set value of UiBRG : n Bit Rate (bps) 1200 f8 103 (67h) 1202 155 (9Bh) 1202 2400 f8 51 (33h) 2404 77 (4Dh) 2404 4800 f8 25 (19h) 4808 38 (26h) 4808 9600 f1 103 (67h) 9615 155 (9Bh) 9615 14400 f1 68 (44h) 14493 103 (67h) 14423 19200 f1 51 (33h) 19231 77 (4Dh) 19231 28800 f1 34 (22h) 28571 51 (33h) 28846 31250 f1 31 (1Fh) 31250 47 (2Fh) 31250 38400 f1 25 (19h) 38462 38 (26h) 38462 51200 f1 19 (13h) 50000 28 (1Ch) 51724 D0Start bit Sampled “L” UiBRG count source RXDi Transfer clock RTSi Stop bit “1” “0” “0” “1” “H” “L” “0” “1” Reception triggered when transfer clock is generated by falling edge of start bit Set to “0” by an interrupt request acknowledgement or by program Receive data taken in D7D1 Transferred from UARTi receive register to UiRB register The above timing diagram applies to the case where the register bits are set as follows:

• PRYE bit in UiMR register = 0 (parity disabled)
• STPS bit in UiMR register = 0 (1 stop bit)
• CRD bit in UiC0 register = 0 (CTSi/RTSi enabled) and CRS bit = 1 (RTSi selected) i = 0 to 2 RE bit in UiC1 register IR bit in SiRIC register RI bit in UiC1 register
• Example of Receive Timing when Transfer Data is 8 Bits Long (parity disabled, one stop bit)

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 202 of 390 REJ09B0185-0241

17.1.2.2 Counter Measure for Communication Error Occurs

If a communication error occurs while transmitting or receiving in UART mode, follow the procedures below.

• Resetting the UiRB register (i=0 to 2) (1) Set the RE bit in the UiC1 re gister to “0” (reception disabled) (2) Set the RE bit in the UiC1 re gister to “1” (reception enabled)
• Resetting the UiTB register (i=0 to 2) (1) Set the SMD2 to SMD0 bits in the UiMR register “000b” (Serial interface disabled) (2) Set the SMD2 to SMD0 bits in the UiMR register “001b”, “101b”, “110b”. (3) “1” is written to RE bit in the UiC1 register (transmission enabled), regardless of the TE bit in the UiCi register

17.1.2.3 LSB First/MSB First Select Function

As shown in Figure 17.21, use the UFORM bit in the UiC0 register to select the transfer format. This function is valid when transfer data is 8 bits long. Figure 17.21 Transfer Format (1) When the UFORM Bit in the UiC0 Register = 0 (LSB First) (2) When the UFORM Bit = 1 (MSB First) NOTES : 1. This applies to the case where the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the UiLCH bit in the UiC1 register = 0 (no reverse), the STPS bit in the UiMR register = 0 (1 stop bit) and the PRYE bit in the UiMR register = 1 (parity enabled). D1 D2 D3 D4 D5 D6 SPD0 D1 D2 D3 D4 D5 D6 SPD0 TXDi RXDi CLKi D6 D5 D4 D3 D2 D1 D0D7 TXDi RXDi CLKi ST ST D7 P D7 P SP SP ST ST P P D6 D5 D4 D3 D2 D1 D0D7 ST : Start bit P : Parity bit SP : Stop bit i = 0 to 2

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 203 of 390 REJ09B0185-0241

17.1.2.4 Serial Data Logic Switching Function

The data written to the UiTB register has its logic reve rsed before being transmitted. Similarly, the received data has its logic reversed when read from the UiRB register. Figure 17.22 shows Serial Data Logic Switching. Figure 17.22 Serial Data Logic Switching

17.1.2.5 TXD and RXD I/O Polarity Inverse Function

This function inverses the polarities of the TXDi pin output and RXDi pin in put. The logic levels of all input/ output data (including the start, stop and parity bits ) are inversed. Figure 17.23 shows the TXD and RXD I/O Polarity Inverse. Figure 17.23 TXD and RXD I/O Polarity Inverse Transfer Clock “H” “L” D0 D1 D2 D3 D4 D5 D6 D7 P SPSTTXDi (No Reverse) “H” “L” TXDi (Reverse) “H” “L” (1) When the UiLCH bit in the UiC1 Register = 0 (No Reverse) (2) When the UiLCH Bit = 1 (Reverse) Transfer Clock “H” “L” NOTES : 1. This applies to the case where the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge of the transfer clock), the UFORM bit in the UiC0 register = 0 (LSB first), the STPS bit in the UiMR register = 0 (1 stop bit) and the PRYE bit in the UiMR register = 1 (parity enabled). ST : Start bit P : Parity bit SP : Stop bit i = 0 to 2 D0 D1 D2 D3 D4 D5 D6 D7 P SPST (1) When the IOPOL Bit in the UiMR Register = 0 (No Reverse) (2) When the IOPOL Bit = 1 (Reverse) NOTES : 1. This applies to the case where the UFORM bit in the UiC0 register = 0 (LSB first), the STPS bit in the UiMR register = 0 (1 stop bit) and the PRYE bit in the UiMR register = 1 (parity enabled). ST : Start bit P : Parity bit SP : Stop bit i = 0 to 2 “H” Transfer Clock TXDi (No Reverse) RXDi (No Reverse) Transfer Clock TXDi (Reverse) RXDi (Reverse) “L” “H” “L” “H” “L” “H” “L” “H” “L” “H” “L” D0 D1 D2 D3 D4 D5 D6 D7 P SPST D0 D1 D2 D3 D4 D5 D6 D7 P SPST D0 D1 D2 D3 D4 D5 D6 D7 P SPST D0 D1 D2 D3 D4 D5 D6 D7 P SPST

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 204 of 390 REJ09B0185-0241

17.1.2.6 CTS /RTS Function

When the CTS function is used transmit operation start when “L” is applied to the CTSi /RTSi (i=0 to 2) pin. Transmit operation begins when the CTSi /RTSi pin is held “L”. If the “L” signal is switched to “H” during a transmit operation, the operation stops before the next data. When the RTS function is used, the CTSi /RTSi pin outputs on “L” signal when the microcomputer is ready to receive. The output level becomes “H” on the first falling edge of the CLKi pin.

• CRD bit in UiC0 register = 1 (disable CTS/RTS function of UART0) CTSi/RTSi pin is programmable I/O function
• CRD bit = 0, CRS bit = 0 (CTS function is selected) CTSi /RTSi pin is CTS function
• CRD bit = 0, CRS bit = 1 (RTS function is selected) CTSi /RTSi pin is RTS function

17.1.2.7 CTS /RTS Separate Function (UART0)

This function separates CTS0/RTS0, outputs RTS0 from the P6_0 pin, and accepts as input the CTS0 from the P6_4 pin. To use this function, set the register bits as shown below.

• CRD bit in U0C0 register = 0 (enable CTS/RTS of UART0)
• CRS bit in U0C0 register = 1 (output RTS of UART0)
• CRD bit in U1C0 register = 0 (enable CTS/RTS of UART1)
• CRS bit in U1C0 register = 0 (input CTS of UART1)
• RCSP bit in UCON register = 1 (inputs CTS0 from the P6_4 pin)
• CLKMD1 bit in UCON register = 0 (CLKS1 not used) Note that when using the CTS/RTS separate function, CTS/RTS of UART1 separate function cannot be used. Figure 17.24 CTS /RTS Separate Function IN OUT CTS RTS ICMicrocomputer TXD0 (P6_3) RXD0 (P6_2) CTS0 (P6_4) RTS0 (P6_0)

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17.1.3 Special Mode 1 (I 2C mode)

I2C mode is provided for use as a simplified I2C interface compatible mode. Table 17.10 lists the specifications of the I2C mode. Table 17.11 to 17.12 lists the registers used in the I 2C mode and the register values set. Table Transfer to UiRB Register and Interrupt Timing. As shown in Table 17.13, the microcomputer is placed in I 2C mode by setting the SMD2 to SMD0 bits to “010b” and the IICM bit to “1”. Because SDAi transmit output has a dela y circuit attached, SDAi output does not change state until SCLi goes low and remains stably low. NOTES: 1. When an external clock is selected, the conditions must be met while the external clock is in the high state. 2. If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit in the SiRIC register does not change. Table 17.10 I 2C Mode Specifications Item Specification Transfer Data Format Transfer data length: 8 bits Transfer Clock • During master CKDIR bit in the UiMR (i=0 to 2) register = 0 (internal clock) : fj/ (2(n+1)) fj = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of UiBRG register 00h to FFh

• During slave CKDIR bit = 1 (external clock) : Input from SCLi pin Transmission Start Condition Before transmission can start, met the following requirements (1)
• The TE bit in the UiC1 register= 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in UiTB register) Reception Start Condition Before reception can start, met the following requirements (1)
• The RE bit in UiC1 register= 1 (reception enabled)
• The TE bit in UiC1 register= 1 (transmission enabled)
• The TI bit in UiC1 register= 0 (data present in the UiTB register) Interrupt Request Generation Timing When start or stop condition is detected, acknowledge undetected, and acknowledge detected Error Detection Overrun error (2) This error occurs if the serial interface started receiving the next data before reading the UiRB register and received the 8th bit of the next data Select Function • Arbitration lost Timing at which the ABT bit in the UiRB register is updated can be selected
• SDAi digital delay No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable
• Clock phase setting With or without clock delay selectable

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 206 of 390 REJ09B0185-0241 Figure 17.25 I 2C Mode Block Diagram CLK control Falling edge detection External clock Internal clock Start/stop condition detection interrupt request Start condition detection Stop condition detection Reception register Bus busy Transmission register Arbitration Noise Filter SDAi SCLi UARTi D T Q D T Q D T Q NACK ACK UARTi UARTi UARTi R UARTi transmit, NACK interrupt request UARTi receive, ACK interrupt request, DMA1 request IICM=1 and IICM2=0 S R Q ALS R S SWC IICM=1 and IICM2=0 IICM2=1 IICM2=1 SWC2 SDHI DMA0, DMA1 request (UART1: DMA0 only) Noise Filter i=0 to 2 IICM : Bit in UiSMR register IICM2, SWC, ALS, SWC2, SDHI : Bit in UiSMR2 register STSPSEL, ACKD, ACKC : Bit in UiSMR4 register IICM=0 IICM=1 DMA0 (UART0, UART2) STSPSEL=0 STSPSEL=1 STSPSEL=1 STSPSEL=0 SDA(STSP) SCL(STSP) ACKC=1 ACKC=0 Q Port register(1) I/O port 9th bit falling edge 9th bit ACKD register Delay circuit This diagram applies to the case where the SMD2 to SMD0 bits in the UiMR register = 010b and the IICM bit in the UiSMR register = 1. NOTES : 1. If the IICM bit = 1, the pin can be read even when the PD6_2, PD6_6 or PD7_1 bit = 1 (output mode). Start and stop condition generation block

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 207 of 390 REJ09B0185-0241 NOTES: 1. Set the bit 4 and bit 5 in the U0C1 and U1C1 register to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are in the UCON register. 2. TXD2 pin is N channel open-drain output. No NCH bit in the U2C0 register is assigned. When write, set to “0”. 3. Not all register bits are described above. Set thos e bits to “0” when writing to the registers in I2C mode. 4. When using UART1 in I 2C mode and enabling the CTS/RTS separate function of UART0, set the CRD bit in the U1C0 register to “0” (CTS/RTS enable) and the CRS bit to “0” (CTS input). i=0 to 2 Table 17.11 Registers to Be Used and Settings in I2C Mode (1) Register Bit Function Master Slave UiTB (3) 0 to 7 Set transmission data Set transmission data UiRB (3) 0 to 7 Reception data can be read Reception data can be read

8 ACK or NACK is set in this bit ACK or NACK is set in this bit

ABT Arbitration lost detection flag Invalid OER Overrun error flag Overrun error flag UiBRG 0 to 7 Set a bit rate Invalid UiMR (3) SMD2 to SMD0 Set to “010b” Set to “010b” CKDIR Set to “0” Set to “1” IOPOL Set to “0” Set to “0” UiC0 CLK1, CLK0 Select the count source for the UiBRG register Invalid CRS Invalid because CRD = 1 Invalid because CRD = 1 TXEPT Transmit buffer empty flag Transmit buffer empty flag CRD (4) Set to “1” Set to “1” NCH Set to “1” (2) Set to “1” (2) CKPOL Set to “0” Set to “0” UFORM Set to “1” Set to “1” UiC1 TE Set this bit to “1” to enable transmissi on Set this bit to “1” to enable transmission TI Transmit buffer empty flag Transmit buffer empty flag RE Set this bit to “1” to enable reception Set this bit to “1” to enable reception RI Reception complete flag Reception complete flag U2IRS (1) Invalid Invalid U2RRM (1), UiLCH, UiERE Set to “0” Set to “0” UiSMR IICM Set to “1” Set to “1” ABC Select the timing at which arbitration-lost is detected Invalid BBS Bus busy flag Bus busy flag 3 to 7 Set to “0” Set to “0” UiSMR2 IICM2 See Table 17.13 I2C Mode Functions See Table 17.13 I2C Mode Functions CSC Set this bit to “1” to enable clock synchronization Set to “0” SWC Set this bit to “1” to have SCLi output fixed to “L” at the falling edge of the 9th bit of clock Set this bit to “1” to have SCLi output fixed to “L” at the falling edge of the 9th bit of clock ALS Set this bit to “1” to have SDAi output stopped when arbitration-lost is detected Set to “0” STAC Set to “0” Set this bit to “1” to initialize UARTi at start condition detection SWC2 Set this bit to “1” to have SCLi output forcibly pulled low Set this bit to “1” to have SCLi output forcibly pulled low SDHI Set this bit to “1” to disable SDAi output Set this bit to “1” to disable SDAi output

7 Set to “0” Set to “0”

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 208 of 390 REJ09B0185-0241 i=0 to 2 Table 17.12 Registers to Be Used and Settings in I2C Mode (2) Register Bit Function Master Slave UiSMR3 0, 2, 4 and NODC Set to “0” Set to “0” CKPH See Table 17.13 I2C Mode Functions See Table 17.13 I2C Mode Functions DL2 to DL0 Set the amount of SDAi digita l delay Set the amount of SDAi digital delay UiSMR4 STAREQ Set this bit to “1” to generate start condition Set to “0” RSTAREQ Set this bit to “1” to generate restart condition Set to “0” STPREQ Set this bit to “1” to generate stop condition Set to “0” STSPSEL Set this bit to “1” to output each condition Set to “0” ACKD Select ACK or NACK Select ACK or NACK ACKC Set this bit to “1” to output ACK data Set this bit to “1” to output ACK data SCLHI Set this bit to “1” to have SCLi output stopped when stop condition is detected Set to “0” SWC9 Set to “0” Set this bit to “1” to set the SCLi to “L” hold at the falling edge of the 9th bit of clock IFSR2A IFSR26, ISFR27 Se t to “1” Set to “1” UCON U0IRS, U1IRS Invalid Invalid 2 to 7 Set to “0” Set to “0”

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 209 of 390 REJ09B0185-0241 NOTES: 1. If the source or factor of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may inadvertently be set to “1” (interrupt requested). (Refer to 24.7 Interrupt) If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to clear the IR bit to “0” (interrupt not requested) after changing those bits. SMD2 to SMD0 bits in the UiMR register, IICM bit in the UiSMR register, IICM2 bit in the UiSMR2 register, CKPH bit in the UiSMR3 register 2. Set the initial value of SDAi output while the SMD2 to SMD0 bits in the UiMR register = 000b (serial interface disabled). 3. Second data transfer to UiRB regi ster (Rising edge of SCLi 9th bit) 4. First data transfer to UiRB regi ster (Falling edge of SCLi 9th bit) 5. See Figure 17.28 STSPSEL Bit Functions. 6. See Figure 17.26 Transfer to UiRB Register and Interrupt Timing. 7. When using UART0, be sure to set the IFSR26 bit in the IFSR2A register to “1” (factor of interrupt: UART0 bus collision). When using UART1, be sure to set the IFSR27 bit to “1” (factor of interrupt: UART1 bus collision). i = 0 to 2 Table 17.13 I 2C Mode Functions Function Clock Synchronous Serial I/O Mode (SMD2 to SMD0 = 001b, IICM = 0) I2C Mode (SMD2 to SMD0 = 010b, IICM = 1) IICM2 = 0 (NACK/ACK interrupt) IICM2 = 1 (UART transmit/receive interrupt) CKPH = 0 (No clock delay) CKPH = 1 (Clock delay) CKPH = 0 (No clock delay) CKPH = 1 (Clock delay) Factor of Interrupt Number 6, 7 and 10 (1, 5, 7) − Start condition detection or stop condition detection (See Table 17.14 STSPSEL Bit Functions) Factor of Interrupt Number 15, 17 and 19 (1, 6) UARTi transmission Transmission started or completed (selected by UiIRS) No acknowledgment detection (NACK) Rising edge of SCLi 9th bit UARTi transmission Rising edge of SCLi 9th bit UARTi transmission Falling edge of SCLi next to the 9th bit Factor of Interrupt Number 16, 18 and 20 (1, 6) UARTi reception When 8th bit received CKPOL = 0 (rising edge) CKPOL = 1 (falling edge) Acknowledgment detection (ACK) Rising edge of SCLi 9th bit UARTi reception Falling edge of SCLi 9th bit Timing for Transferring Data From the UART Reception Shift Register to the UiRB Register CKPOL = 0 (rising edge) CKPOL = 1 (falling edge) Rising edge of SCLi 9th bit Falling edge of SCLi 9th bit Falling and rising edges of SCLi 9th bit UARTi Transmission Output Delay Not delayed Delayed Functions of P6_3, P6_7 and P7_0 Pins TXDi output SDAi input/output Functions of P6_2, P6_6 and P7_1 Pins RXDi input SCLi input/output Functions of P6_1, P6_5 and P7_2 Pins CLKi input or output selected − (Cannot be used in I2C mode) Noise Filter Width 15ns 200ns Read RXDi and SCLi Pin Levels Possible when the corresponding port direction bit = 0 Always possible no matter how the corresponding port direction bit is set Initial Value of TXDi and SDAi Outputs CKPOL = 0 (H) CKPOL = 1 (L) The value set in the port register before setting I2C mode (2) Initial and End Values of SCLi − HL H L DMA1 Factor (6) UARTi reception Acknowledgment detection (ACK) UARTi reception Falling edge of SCLi 9th bit Store Received Data 1st to 8th bits of the received data are stored into bits 7 to 0 in the UiRB register 1st to 8th bits of the received data are stored into bits 7 to 0 in the UiRB register 1st to 7th bits of the received data are stored into bits 6 to 0 in the UiRB register. 8th bit is stored into bit 8 in the UiRB register. 1st to 8th bits are stored into bits 7 to 0 in the UiRB register (3) Read Received Data The UiRB register status is read Bits 6 to 0 in the UiRB register (4) are read as bits 7 to 1. Bit 8 in the UiRB register is read as bit 0.

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 210 of 390 REJ09B0185-0241 Figure 17.26 Transfer to UiRB Register and Interrupt Timing (3) IICM2= 1 (UART transmit/receive interrupt), CKPH= 0 (1) IICM2= 0 (ACK and NACK interrupts), CKPH= 0 (no clock delay) i=0 to 2 This diagram applies to the case where the following condition is met.

• UiMR register CKDIR bit = 0 (Slave selected) ACK interrupt (DMA1 request), NACK interrupt Transfer to UiRB register Receive interrupt (DMA1 request) Transmit interrupt Transfer to UiRB register (4) IICM2= 1, CKPH= 1 D6 D5 D4 D3 D2 D1D7SDAi SCLi D6 D5 D4 D3 D2 D1D7SDAi SCLi D6 D5 D4 D3 D2 D1 D8 (ACK, NACK)D7SDAi SCLi D8 (ACK, NACK) D8 (ACK, NACK) D6 D5 D4 D3 D2 D1 D8 (ACK, NACK)D7SDAi SCLi 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit b15
• •• b9 b8 b7 b0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UiRB register b15
• •• b9 b8 b7 b0 b15
• •• b9 b8 b7 b0 D0 D7 D6 D5 D4 D3 D2 D1 b15
• •• b9 b8 b7 b0 D0 D7 D6 D5 D4 D3 D2 D1 b15
• •• b9 b8 b7 b0 D8 D7 D6 D5 D4 D3 D2 D1 D0 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit (2) IICM2= 0, CKPH= 1 (clock delay) ACK interrupt (DMA1 request), NACK interrupt Transfer to UiRB register UiRB register Transmit interrupt Transfer to UiRB register Receive interrupt (DMA1 request) Transfer to UiRB register UiRB register UiRB register UiRB register D8 D7 D6 D5 D4 D3 D2 D1 D0

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17.1.3.1 Detection of Start and Stop Condition

Whether a start or a stop condition has been detected is determined. A start condition-detected interrupt request is generate d when the SDAi pin change s state from high to low while the SCLi pin is in the high stat e. A stop condition-detected interrupt request is generated when the SDAi pin changes state from low to high while the SCLi pin is in the high state. Because the start and stop condition-detected interrupts share the interrupt control register and vector, check the BBS bit in the UiSMR register to determine which interrupt source is requesting the interrupt. Figure 17.27 Detection of Start and Stop Condition

17.1.3.2 Output of Start and Stop Condition

A start condition is generated by setting the STAREQ bit in the UiSMR4 register (i = 0 to 2) to “1” (start). A restart condition is generated by setting the RSTAREQ bit in the UiSMR4 register to “1” (start). A stop condition is generated by setting the STPREQ bit in the UiSMR4 register to “1” (start). The output procedure is described below. (1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to “1” (start). (2) Set the STSPSEL bit in the Ui SMR4 register to “1” (output). The function of the STSPSEL bit is shown in Table 17.14 and Figure 17.28. 3 to 6 cycles < duration for setting-up (1) 3 to 6 cycles < duration for holding (1) i = 0 to 2 NOTES : 1. When the PCLK1 bit in the PCLKR register = 1, this is the cycle number of f1SIO, and the PCLK1 bit = 0, this is the cycle number of f2SIO. Duration for setting up Duration for holding SCLi SDAi (Start condition) SDA i (Stop condition)

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 212 of 390 REJ09B0185-0241 Figure 17.28 STSPSEL Bit Functions

17.1.3.3 Arbitration

Unmatching of the transmit data and SDAi pin input da ta is checked synchronously with the rising edge of SCLi. Use the ABC bit in the UiSMR register to select the timing at which the ABT bit in the UiRB register is updated. If the ABC bit = 0 (updated bitwise), the ABT bit is set to “1” at the same time unmatching is detected during check, and is cleared to “0” when not detected. In cases when the ABC bit is set to “1”, if unmatching is detected even once during check, the ABT bit is set to “1” (unmatching detected) at the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be updated bytewise, clear the ABT bit to “0” (undetected) after detecting acknowledge in the first byte, before transferring the next byte. Setting the ALS bit in the UiSMR2 register to “1” (SDA output stop enabled) factors arbitration-lost to occur, in which case the SDAi pin is placed in the high-impedance state at the same time the ABT bit is set to “1” (unmatching detected). Table 17.14 STSPSEL Bit Functions Function STSPSEL = 0 STSPSEL = 1 Output of SCLi and SDAi Pins Output of transfer clock and data Output of start/stop condition is accomplished by a program using ports (not automatically generated in hardware) Output of a start/stop condition according to the STAREQ, RSTAREQ and STPREQ bit Start/Stop Condition Interrupt Request Generation Timing Start/stop condition detection Finish generating start/stop condition Start condition detection interrupt Stop condition detection interrupt (1) When Slave CKDIR=1 (external clock) Start condition detection interrupt Stop condition detection interrupt (2) When Master CKDIR=0 (internal clock), CKPH=1 (clock delayed) SDAi SCLi Set STAREQ=1 (start) Set STPREQ=1 (start) STSPSEL bit SDAi SCLi STSPSEL bit Set to “1” in a program Set to “0” in a program Set to “1” in a program Set to “0” in a program 1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit 1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit

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17.1.3.4 Transfer Clock

Data is transmitted/received using a transfer clock like the one shown in Figure 17.26 Transfer to UiRB Register and Interrupt Timing. The CSC bit in the UiSMR2 register is used to synchr onize the internally generated clock (internal SCLi) and an external clock supplied to the SCLi pin. In cases when the CSC bit is set to “1” (clock synchronization enabled), if a falling edge on the SCLi pin is detected while the internal SCLi is high, the internal SCLi goes low, at which time the value of the UiBRG register is reloaded with and starts counting in the low-level interval. If the internal SCLi changes state from low to high while the SCLi pin is low, counting stops, and when the SCLi pin goes high, counting restarts. In this way, the UARTi transfer clock is comprised of the logical product of the internal SCLi and SCLi pin signal. The transfer clock works from a half period before the falling edge of the internal SCLi 1st bit to the rising edge of the 9th bit. To use this function, select an internal clock for the transfer clock. The SWC bit in the UiSMR2 register allows to select whether the SCLi pin should be fixed to or freed from low-level output at the falling edge of the 9th clock pulse. If the SCLHI bit in the UiSMR4 register is set to “1” (e nabled), SCLi output is turned off (placed in the high- impedance state) when a stop condition is detected. Setting the SWC2 bit in the UiSMR2 register = 1 (0 out put) makes it possible to forcibly output a low-level signal from the SCLi pin even while sending or receivi ng data. Clearing the SWC2 bit to “0” (transfer clock) allows the transfer clock to be output from or supplied to the SCLi pin, instead of outputting a low-level signal. If the SWC9 bit in the UiSMR4 register is set to “1 ” (SCL hold low enabled) when the CKPH bit in the UiSMR3 register = 1, the SCLi pin is fixed to low-level output at the falling edge of the clock pulse next to the 9th. Setting the SWC9 bit = 0 (SCL hold low disabled) frees the SCLi pin from low-level output.

17.1.3.5 SDA Output

The data written to the UiTB register bit 7 to bit 0 (D7 to D0) is sequentially output beginning with D7. The 9th bit (D8) is ACK or NACK. The initial value of SDAi transmit output can only be set when IICM = 1 (I 2C mode) and the SMD2 to SMD0 bits in the UiMR register = 000b (Serial interface disabled). The DL2 to DL0 bits in the UiSMR3 register allow to add no delays or a delay of 2 to 8 UiBRG count source clock cycles to SDAi output. Setting the SDHI bit in the UiSMR2 register = 1 (SDA output disabled) forcibly places the SDAi pin in the high-impedance state. Do not write to the SDHI bit sy nchronously with the rising edge of the UARTi transfer clock. This is because the ABT bit may inadvertently be set to “1” (detected).

17.1.3.6 SDA Input

When the IICM2 bit = 0, the 1st to 8th bits (D7 to D0) of received data are stored in the UiRB register bit 7 to bit 0. The 9th bit (D8) is ACK or NACK. When the IICM2 bit = 1, the 1st to 7th bits (D7 to D1) of received data are stored in the UiRB register bit 6 to bit 0 and the 8th bit (D0) is stored in the UiRB register bit 8. Even when the IICM2 bit = 1, providing the CKPH bit = 1, the same data as when the IICM2 bit = 0 can be read out by reading the Ui RB register after the rising edge of the corresponding clock pulse of 9th bit.

17.1.3.7 ACK and NACK

If the STSPSEL bit in the UiSMR4 register is set to “0” (start and stop conditions not generated) and the ACKC bit in the UiSMR4 register is set to “1” (ACK data output), the value of the ACKD bit in the UiSMR4 register is output from the SDAi pin. If the IICM2 bit = 0, a NACK interrupt request is generated if the SDAi pin remains high at the rising edge of the 9th bit of transmit clock pulse. An ACK interrupt reque st is generated if the SDAi pin is low at the rising edge of the 9th bit of transmit clock pulse. If ACKi is selected for the factor of DMA1 request , a DMA transfer can be activated by detection of an acknowledge.

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17.1.3.8 Initialization of Transmission/Reception

If a start condition is detected while the STAC bit = 1 (UARTi initialization enabled), the serial interface operates as described below.

• The transmit shift register is initialized, and the conten t of the UiTB register is transferred to the transmit shift register. In this way, the seri al interface starts sending data sync hronously with the next clock pulse applied. However, the UARTi output value does not ch ange state and remains the same as when a start condition was detected until the first bit of data is output synchronously with the input clock.
• The receive shift register is initia lized, and the serial interface starts receiving data synchronously with the next clock pulse applied.
• The SWC bit is set to “1” (SCL wait output enabled) . Consequently, the SCLi pin is pulled low at the falling edge of the 9th clock pulse. Note that when UARTi transmission/reception is started using this function, the TI does not change state. Note also that when using this function, the selected transfer clock should be an external clock.

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17.1.4 Special Mode 2

Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable. Table 17.15 lists the Special Mode 2 Specifications. Table 17.16 lists the Registers to Be Used and Settings in Special Mode 2. Figure 17.29 shows Serial Bus Communication Control Example (UART2). NOTES: 1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the CKPOL bit = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. 2. If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit in the SiRIC register does not change. Table 17.15 Special Mode 2 Specifications Item Specification Transfer Data Format Transfer data length: 8 bits Transfer Clock • Master mode CKDIR bit in UiMR(i=0 to 2) register = 0 (internal clock) : fj/ (2(n+1)) fj = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of UiBRG register 00h to FFh

• S l a v e m o d e CKDIR bit = 1 (external clock selected) : Input from CLKi pin Transmit/Receive Control Controlled by input/output ports Transmission Start Condition Before transmission can start, meet the following requirements (1)
• The TE bit in UiC1 register= 1 (transmission enabled)
• The TI bit in UiC1 register = 0 (data present in UiTB register) Reception Start Condition Before reception ca n start, meet the following requirements (1)
• The RE bit in UiC1 register= 1 (reception enabled)
• The TE bit in UiC1 register= 1 (transmission enabled)
• The TI bit in UiC1 register= 0 (data present in the UiTB register) Interrupt Request Generation Timing For transmission, one of the following conditions can be selected
• The UiIRS bit in UiC1 register = 0 (transmit buffer empty): when transferring data from the UiTB register to the UARTi transmit register (at start of transmission)
• The UiIRS bit =1 (transfer completed): when the serial interface finished sending data from the UARTi transmit register For reception
• When transferring data from the UARTi receive register to the UiRB register (at completion of reception) Error Detection Overrun error (2) This error occurs if the serial interface started receiving the next data before reading the UiRB register and received the 7th bit of the next data Select Function Clock phase setting Selectable from four combinations of transfer clock polarities and phases

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 216 of 390 REJ09B0185-0241 Figure 17.29 Serial Bus Communication Control Example (UART2) P1_3 P1_2 P7_0(TXD2) P7_2(CLK2) P7_1(RXD2) P9_3 P7_0(TXD2) P7_2(CLK2) P7_1(RXD2) P9_3 P7_0(TXD2) P7_2(CLK2) P7_1(RXD2) Microcomputer (Master) Microcomputer (Slave) Microcomputer (Slave)

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 217 of 390 REJ09B0185-0241 NOTES: 1. Set the bit 4 and bit 5 in the U0C0 and U1C1 register to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are in the UCON register. 2. TXD2 pin is N channel open-drain output. No NCH bit in the U2C0 register is assigned. When write, set to “0”. 3. Not all register bits are described abov e. Set those bits to “0” when writing to the registers in Special Mode 2. i = 0 to 2 Table 17.16 Registers to Be Used and Settings in Special Mode 2 Register Bit Function UiTB (3) 0 to 7 Set transmission data UiRB (3) 0 to 7 Reception data can be read OER Overrun error flag UiBRG 0 to 7 Set a bit rate UiMR (3) SMD2 to SMD0 Set to “001b” CKDIR Set this bit to “0” for master mode or “1” for slave mode IOPOL Set to “0” UiC0 CLK1, CLK0 Select the count source for the UiBRG register CRS Invalid because CRD = 1 TXEPT Transmit register empty flag CRD Set to “1” NCH Select TXDi pin output format (2) CKPOL Clock phases can be set in combination with the CKPH bit in the UiSMR3 register UFORM Set to “0” UiC1 TE Set this bit to “1” to enable transmission TI Transmit buffer empty flag RE Set this bit to “1” to enable reception RI Reception complete flag U2IRS (1) Select UART2 transmit interrupt factor U2RRM (1), UiLCH, UiERE Set to “0” UiSMR 0 to 7 Set to “0” UiSMR2 0 to 7 Set to “0” UiSMR3 CKPH Clock phases can be set in combination with the CKPOL bit in the UiC0 register NODC Set to “0” 0, 2, 4 to 7 Set to “0” UiSMR4 0 to 7 Set to “0” UCON U0IRS, U1IRS Select UART0 and UART1 transmit interrupt factor U0RRM, U1RRM Set to “0” CLKMD0 Invalid because CLKMD1 = 0 CLKMD1, RCSP, 7 Set to “0”

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 218 of 390 REJ09B0185-0241

17.1.4.1 Clock Phase Setting Function

One of four combinations of transfer clock phases a nd polarities can be selected using the CKPH bit in the UiSMR3 register and the CKPOL bit in the UiC0 register. Make sure the transfer clock polarity and phase are the same for the master and salves to be communicated. Figure 17.30 shows the Transmission and Reception Timing in Master Mode (Internal Clock). Figure 17.31 shows the Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock) while Figure 17.32 shows the Transmission and Reception Timing (CKPH=1) in Slave Mode (External Clock). Figure 17.30 Transmission and Reception Timing in Master Mode (Internal Clock) Data output timing Data input timing D0 D1 D2 D3 D4 D6 D7D5 Clock output (CKPOL=0, CKPH=0) “H” “L” Clock output (CKPOL=1, CKPH=0) “H” “L” Clock output (CKPOL=0, CKPH=1) “H” “L” Clock output (CKPOL=1, CKPH=1) “H” “L” “H” “L”

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 220 of 390 REJ09B0185-0241

17.1.5 Special Mode 3 (IE mode)

In this mode, one bit of IEBus is approximated with one byte of UART mode waveform. Table 17.17 lists the Registers to Be Used and Sett ings in IE Mode. Figure 17.33 shows the Bus Collision Detect Function-Related BitsBus Collision Detect Function-Related Bits. If the TXDi pin (i = 0 to 2) output level and RXDi pin input level do not match, a UARTi bus collision detect interrupt request is generated. Use the IFSR26 and IFSR27 bits in the IFSR2A regist er to enable the UART0/UART1 bus collision detect function. NOTES: 1. Set the bit 4 and bit 5 in the U0C0 and U1C1 registers to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are in the UCON register. 2. TXD2 pin is N channel open-drain output. No NCH bit in th e U2C0 register is assigned. When write, set to “0”. 3. Not all register bits are described above. Set those bits to “0” when writing to the registers in IE mode. i= 0 to 2 Table 17.17 Registers to Be Us ed and Settings in IE Mode Register Bit Function UiTB 0 to 8 Set transmission data UiRB (3) 0 to 8 Reception data can be read OER, FER, PER, SUM Error flag UiBRG 0 to 7 Set a bit rate UiMR SMD2 to SMD0 Set to “110b” CKDIR Select the internal clock or external clock STPS Set to “0” PRY Invalid because PRYE=0 PRYE Set to “0” IOPOL Select the TXD/RXD input/output polarity UiC0 CLK1, CLK0 Select the count source for the UiBRG register CRS Invalid because CRD=1 TXEPT Transmit register empty flag CRD Set to “1” NCH Select TXDi pin output mode (2) CKPOL Set to “0” UFORM Set to “0” UiC1 TE Set this bit to “1” to enable transmission TI Transmit buffer empty flag RE Set this bit to “1” to enable reception RI Reception complete flag U2IRS (1) Select the source of UART2 transmit interrupt U2RRM (1), UiLCH, UiERE Set to “0” UiSMR 0 to 3, 7 Set to “0” ABSCS Select the sampling timing at which to detect a bus collision ACSE Set this bit to “1” to use the auto clear function of transmit enable bit SSS Select the transmit start condition UiSMR2 0 to 7 Set to “0” UiSMR3 0 to 7 Set to “0” UiSMR4 0 to 7 Set to “0” IFSR2A IFSR26, IFSR27 Set to “1” UCON U0IRS, U1IRS Select the source of UART0/UART1 transmit interrupt U0RRM, U1RRM Set to “0” CLKMD0 Invalid because CLKMD1 = 0 CLKMD1, RCSP, 7 Set to “0”

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 221 of 390 REJ09B0185-0241 Figure 17.33 Bus Collision Detect Function-Related Bits (2) The ACSE Bit in the UiSMR Register (Auto clear of transmit enable bit) (1) The ABSCS Bit in the UiSMR Register (Bus collision detect sampling clock select) If ABSCS=0, bus collision is determined at the rising edge of the transfer clock Transfer clock Timer Aj (3) The SSS Bit in the UiSMR Register (Transmit start condition select) Transmission enable condition is met If SSS bit = 1, the serial interface starts sending data at the rising edge (1) of RXDi TXDi CLKi TXDi RXDi TXDi RXDi ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP Trigger signal is applied to the TAjIN pin If ABSCS=1, bus collision is determined when timer Aj (one-shot timer mode) underflows. TXDi RXDi ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP (i=0 to 2) Timer Aj: Timer A3 when UART0; Timer A4 when UART1; Timer A0 when UART2 Transfer clock IR bit in UiBCNIC register (1) NOTES : 1. BCNIC register when UART2. If ACSE bit = 1 (automatically clear when bus collision occurs), the TE bit is cleared to “0” (transmission disabled) when the IR bit in the UiBCNIC register= 1 (unmatching detected). If SSS bit = 0, the serial interface starts sending data one transfer clock cycle after the transmission enable condition is met. Transfer clock (NOTE 2) NOTES : 1. The falling edge of RXDi when IOPOL=0; the rising edge of RXDi when IOPOL =1. 2. The transmit condition must be met before the falling edge (1) of RXD. This diagram applies to the case where IOPOL=1 (reversed). TE bit in UiC1 register

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 222 of 390 REJ09B0185-0241

17.1.6 Special Mode 4 (SIM Mode) (UART2)

Based on UART mode, this is an SIM interface co mpatible mode. Direct an d inverse formats can be implemented, and this mode allows to output a low from the TXD2 pin when a parity error is detected. Table 17.18 lists the SIM Mode Specifications. Table 17.19 lists the Registers to Be Used and Settings in SIM Mode. NOTES: 1. If an overrun error occurs, the value of U2RB register will be indeterminate. The IR bit in the S2RIC register does not change. 2. A transmit interrupt request is generated by setting the U2IRS bit to “1” (transmission complete) and U2ERE bit to “1” (error signal output) in the U2C1 register after reset is deserted. Therefore, when using SIM mode, set the IR bit to “0” (no interrupt request) after setting these bits. 3. The timing at which the framing error flag and the parity error flag are set is detected when data is transferred from the UARTi receive register to the UiRB register. Table 17.18 SIM Mode Specifications Item Specification Transfer Data Format • Direct format

• Inverse format Transfer Clock • CKDIR bit in U2MR register = 0 (internal clock) : fi/ (16(n+1))
• fi = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of U2BRG register 00h to FFh
• CKDIR bit = 1 (external clock) : fEXT/(16(n+1)) fEXT: Input from CLK2 pin n: Setting value of U2BRG register 00h to FFh Transmission Start Condition Before transmission can start, meet the following requirements
• The TE bit in the U2C1 register = 1 (transmission enabled)
• The TI bit in the U2C1 register = 0 (data present in U2TB register) Reception Start Condition Before reception can start, meet the following requirements
• The RE bit in the U2C1 register = 1 (reception enabled)
• Start bit detection Interrupt Request Generation Timing (2)
• For transmission When the serial interface finished sending data from the U2TB transfer register (U2IRS bit =1)
• For reception When transferring data from the UART2 receive register to the U2RB register (at completion of reception) Error Detection • Overrun error (1) This error occurs if the serial interface started receiving the next data before reading the U2RB register and received the bit one before the last stop bit of the next data
• Framing error (3) This error occurs when the number of stop bits set is not detected
• Parity error (3) During reception, if a parity error is detected, parity error signal is output from the TXD2 pin. During transmission, a parity error is detected by the level of input to the RXD2 pin when a transmission interrupt occurs
• Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 223 of 390 REJ09B0185-0241 NOTES: 1. Not all register bits are described above. Set those bits to “0” when writing to the registers in SIM mode. Table 17.19 Registers to Be Us ed and Settings in SIM Mode Register Bit Function U2TB (1) 0 to 7 Set transmission data U2RB (1) 0 to 7 Reception data can be read OER,FER,PER,SUM Error flag U2BRG 0 to 7 Set a bit rate U2MR SMD2 to SMD0 Set to “101b” CKDIR Select the internal clock or external clock STPS Set to “0” PRY Set this bit to “1” for direct format or “0” for inverse format PRYE Set to “1” IOPOL Set to “0” U2C0 CLK1, CLK0 Select the count source for the U2BRG register CRS Invalid because CRD = 1 TXEPT Transmit register empty flag CRD Set to “1” NCH Set to “0” CKPOL Set to “0” UFORM Set this bit to “0” for direct format or “1” for inverse format U2C1 TE Set this bit to “1” to enable transmission TI Transmit buffer empty flag RE Set this bit to “1” to enable reception RI Reception complete flag U2IRS Set to “1” U2RRM Set to “0” U2LCH Set this bit to “0” for direct format or “1” for inverse format U2ERE Set to “1” U2SMR (1) 0 to 3 Set to “0” U2SMR2 0 to 7 Set to “0” U2SMR3 0 to 7 Set to “0” U2SMR4 0 to 7 Set to “0”

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 224 of 390 REJ09B0185-0241 Figure 17.34 Transmit and Receive Timing in SIM Mode D0 D1 D2 D3 D4 D5 D6 D7ST P Start bit Parity bit “0” “1” “0” “1” “0” “1” “0” “1” D0 D1 D2 D3 D4 D5 D6 D7ST P Tc Transfer clock SP Stop bit An “L” signal is applied from the SIM card due to a parity error An interrupt routine detects “H” or “L” An interrupt routine detects “H” or “L” D0 D1 D2 D3 D4 D5 D6 D7ST P TXD2 “0” “1” “0” “1” “0” “1” D0 D1 D2 D3 D4 D5 D6 D7ST P Tc Transfer clock SP TxD2 provides “L” output due to a parity error Transmit Waveform from the Transmitting end Read the U2RB register D0 D1 D2 D3 D4 D5 D6 D7ST PRXD2 pin level (1) D0 D1 D2 D3 D4 D5 D6 D7ST P SPSP D0 D1 D2 D3 D4 D5 D6 D7ST P D0 D1 D2 D3 D4 D5 D6 D7ST P SPSP TXD2 Parity Error signal returned from Receiving end RXD2 pin level (2) Data is transferred from the UiTB register to the UARi transmit register (Note 1) RE bit in U2C1 register RI bit in U2C0 register IR bit in S2RIC register TE bit in U2C1 register TI bit in U2C1 register TXEPT bit in U2C0 register IR bit in S2TIC register (1) Transmit Timing (2) Receive Timing SP SP Start bit Parity bit Stop bit Set to “0” by an interrupt request acknowledgement or by program TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO) fEXT : frequency of U2BRG count source (external clock) n : value set to U2BRG The above timing diagram applies to the case where data is transferred in the direct format.

• STPS bit in U2MR register = 0 (1 stop bit)
• PRY bit in U2MR register = 1 (even)
• UFORM bit in U2C0 register = 0 (LSB first)
• U2LCH bit in U2C1 register = 0 (no reverse)
• U2IRSCH bit in U2C1 register = 1 (transmit is completed) Set to “0” by an interrupt request acknowledgement or by program TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO) fEXT : frequency of U2BRG count source (external clock) n : value set to U2BRG The above timing diagram applies to the case where data is transferred in the direct format.
• STPS bit in U2MR register = 0 (1 stop bit)
• PRY bit in U2MR register = 1 (even)
• UFORM bit in U2C0 register = 0 (LSB first)
• U2LCH bit in U2C1 register = 0 (no reverse)
• U2IRSCH bit in U2C1 register = 1 (transmit is completed) NOTES: 1. Data transmission starts when BRG overflows after a value is set to the U2TB register on the rising edge of the TI bit. 2. Because the TxD2 and RxD2 pins are connected, a composite waveform, consisting of transmit waveform from the TxD2 pin and parity error signal from the receiving end, is generated. 3. Because the TxD2 and RxD2 pins are connected, a composite waveform, consisting of transmit waveform from the transmitting end and parity error signal from the TxD2 pin, is generated. Data is written to the UARTi register

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 225 of 390 REJ09B0185-0241 Figure 17.35 SIM Interface Connection

17.1.6.1 Parity Error Signal Output

The parity error signal is enabled by setting the U2ERE bit in the U2C1 register to “1”. The parity error signal is output when a parity error is detected while receiving data. This is achieved by pulling the TXD2 output low with the timing shown in Figure 17.36. If the R2RB register is read while outputting a parity error signal, the PER bit is cleared to “0” and at the same time the TXD2 output is returned high. When transmitting, a transmission-finished interrupt request is generated at the falling edge of the transfer clock pulse that immediately follows the stop bit. Therefor e, whether a parity signal has been returned can be determined by reading the port that shares the RXD2 pin in a transmission-finished interrupt routine. Figure 17.36 Parity Error Signal Output Timing Microcomputer SIM card TXD2 RXD2 ST : Start bit P : Even Parity SP : Stop bit D0 D1 D2 D3 D4 D5 D6 D7 P SPST (NOTE 1) Transfer clock RXD2 TXD2 “H” “L” “H” “L” “H” “L” “1” “0” This timing diagram applies to the case where the direct format is implemented. NOTES : 1. The output of microcomputer is in the high-impedance state (pulled up externally). IR bit in U2C1 register

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 226 of 390 REJ09B0185-0241

17.1.6.2 Format

When direct format, set the PRYE bit in the U2MR regist er to “1”, the PRY bit to “1”, the UFORM bit in the U2C0 register to “0” and the U2LCH bit in the U2C1 register to “0”. When data are transmitted, data set in the U2TB register are transmitted with the even-numbered parity, starting from D0. When data are received, received data are stored in the U2RB register, starting from D0. The even-numbered parity determines whether a parity error occurs. When inverse format, set the PRYE bit to “1”, the PRY bit to “0”, the UFORM bit to “1” and the U2LCH bit to “1”. When data are transmitted, values set in the U2TB register are logica lly inversed and are transmitted with the odd-numbered parity, starting from D7. When data are received, received data ar e logically inversed to be stored in the U2RB register, starting from D7. The odd-numbered parity determines whether a parity error occurs. Figure 17.37 SIM Interface Format P : Even parity D0 D1 D2 D3 D4 D5 D6 D7 PTXD2 TXD2 D7 D6 D5 D4 D3 D2 D1 D0 P (1) Direct format “H” “L” “H” “L” (2) Inverse format P : Odd parity “H” “L” “H” “L” Transfer clcck Transfer clcck

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 227 of 390 REJ09B0185-0241

17.2 SI/O3 and SI/O4

SI/O3 and SI/O4 are exclusive clock-synchronous serial I/Os. Figure 17.38 shows the SI/O3 and SI/O4 Block Diagram, and Figure 17.39 to Figure 17.40 show the SI/O3 and SI/O4- related registers. Table 17.20 shows the SI/O3 and SI/O4 Specifications. Figure 17.38 SI/O3 and SI/O4 Block Diagram Data bus SI/Oi interrupt request NOTES : 1. i = 3, 4. n = A value set in the SiBRG register. SiTRR register SI/O counter i SMi5 LSB MSB SMi2 SMi3 SMi3 SMi6 SMi1 to SMi0 CLKi SOUTi SINi SiBRG register SMi6 1/(n+1)1/2 Main clock, PLL clock, or on-chip oscillator clock f1SIO f8SIO f32SIO f2SIO PCLK1=0 PCLK1=1 SMi4 00b 01b 10b Clock source select Synchronous circuit CLK polarity reversing circuit The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include SIN3 pin of SI/O3. SI/O3 is only for transmission. Reception is impossible. Note

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 228 of 390 REJ09B0185-0241 Figure 17.39 SiC Register SI/Oi Control Register (i=3, 4) (1) Address After Reset 0362h 01000000b 0366h 01000000b Bit Symbol Function RW NOTES : 6. When changing the SMi1 to SMi0 bits, set the SiBRG register. SMi2 SOUTi Output Disable Bit (4) SOUTi Initial Value Set Bit Synchronous Clock Select BitSMi6 SMi7 SMi3 S I/Oi Port Select Bit SMi5 SMi4 Symbol SMi1 SMi0 Bit Name S4C S3C Internal Synchronous Clock Select Bit(6) CLK Polarity Select Bit b7 b6 b5 b4 b3 b2 b1 b0 RW0 : SOUTi output 1 : SOUTi output disable (High-Impedance) RW RW b1 b0 0 0 : Selecting f1SIO or f2SIO (5) 0 1 : Selecting f8SIO 1 0 : Selecting f32SIO 1 1 : Do not set to this value 0 : Input/output port 1 : SOUTi output, CLKi function RW 0 : LSB first 1 : MSB first RW 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge Selected by PCLK1 bit in the PCLKR register. When the SMi2 bit is set to “1,” the target pin goes to a high-impedance state regardless of w hich function of the pin is being used. RW 0 : External clock (2) 1 : Internal clock (3) Effective w hen SMi3 = 0 0 : “L” output 1 : “H” output Make s ure this regis ter is w ritten to by the nex t ins truc tion af ter s etting the PRC2 bit in the PRCR regis ter to “1” (w rite enable). RW RW Transfer Direction Select Bit Set the SMi3 bit to “1” and the corresponding port direction bit to “0” (input mode). Set the SMi3 bit to “1” (SOUTi output, CLKi function).

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 229 of 390 REJ09B0185-0241 Figure 17.40 SiBRG an d SiTRR Registers SI/Oi Bit Rate Generation Register (i=3, 4) (1, 2, 3) Symbol Address After Reset S3BRG 0363h Indeterminate S4BRG 0367h Indeterminate Setting Range RW NOTES : 3. Write to this register after setting the SMi1 to SMi0 bits in the SiC register. Function Use MOV instruction to w rite to this register. WOAssuming that set value = n, BRGi divides the count source by n + 1 00h to FFh Write to this register w hile serial interface is neither transmitting nor receiving. b0b7 SI/Oi Bit Transmit/Receiv e Register (i=3, 4) (1, 2) Symbol Address After Reset S3TRR 0360h Indeterminate S4TRR 0364h Indeterminate RW NOTES : b7 b0 To receive data, set the corresponding port direction bit for SINi to “0” (input mode). RW Write to this register w hile serial interface is neither transmitting nor receiving. Transmission/reception starts by w riting transmit data to this register. After transmission/reception finishes, reception data can be read by reading this register. Function

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 230 of 390 REJ09B0185-0241 NOTES: 1. To set SMi6 bit to “0” (external clock), follow the procedure described below.

• If the SMi4 bit = 0, write transmit data to the SiTRR register while input on the CLKi pin is high. The same applies when rewriting the SMi7 bit in the SiC register.
• If the SMi4 bit = 1, write transmit data to the SiTRR register while input on the CLKi pin is low. The same applies when rewriting the SMi7 bit.
• Because shift operation continues as long as the transfer clock is supplied to the SI/Oi circuit, stop the transfer clock after supplying eight pulses. If the SMi6 bit = 1 (internal clock), the transfer clock automatically stops. 2. Unlike UART0 to UART2, SI/Oi (i = 3 to 4) is not separated between the transfer register and buffer. Therefore, do not write the next transmit data to the SiTRR register during transmission. 3. When SMi6 bit = 1 (internal clock), SOUTi retains the last data for a 1/2 transfer clock period after completion of transfer and, thereafter, goes to a high-impedance state. However, if transmit data is written to the SiTRR register during this period, SOUTi immediately goes to a high-impedance state, with the data hold time thereby reduced. 4. When the SMi6 bit = 1 (internal cloc k), the transfer clock stops in the high state if the SMi4 bit = 0, or stops in the low state if the SMi4 bit = 1. Table 17.20 SI/O3 and SI/O4 Specifications Item Specification Transfer Data Format • Transfer data length: 8 bits Transfer Clock • SMi6 bit in SiC (i=3, 4) r egister = 1 (internal clock) : fj/ (2(n+1)) fj = f1SIO, f8SIO, f32SIO. n = Setting value of SiBRG register 00h to FFh.
• SMi6 bit = 0 (external clock) : Input from CLKi pin (1) Transmission/Reception Start Condition
• Before transmission/reception can start, meet the following requirements Write transmit data to the SiTRR register (2, 3) Interrupt Request Generation Timing
• When SMi4 bit in SiC register = 0 The rising edge of the last transfer clock pulse (4) When SMi4 = 1 The falling edge of the last transfer clock pulse (4) CLKi Pin Function I/O port, transfer clock input, transfer clock output SOUTi Pin Function I/O port, transmit data output, high-impedance SINi Pin Function I/O port, receive data input Select Function • LSB first or MSB first selection Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected
• Function for setting an SOUTi initial value set function When the SMi6 bit in the SiC register = 0 (external clock), the SOUTi pin output level while not transmitting can be selected.
• CLK polarity selection Whether transmit data is output/input timing at the rising edge or falling edge of transfer clock can be selected.

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 231 of 390 REJ09B0185-0241

17.2.1 SI/Oi Operation Timing

Figure 17.41 shows the SI/Oi Operation Timing. Figure 17.41 SI/Oi Operation Timing

17.2.2 CLK Polarity Selection

The SMi4 bit in the SiC register allows selection of th e polarity of the transfer clock. Figure 17.42 shows the Polarity of Transfer Clock. Figure 17.42 Polarity of Transfer Clock D7D0 D1 D2 D3 D4 D5 D6 i= 3, 4 0.5 to 1.0 cycle (max.)(3) SI/Oi internal clock CLKi output Signal written to the SiTRR register SOUTi output SINi input SiIC register IR bit (NOTE 2) NOTES : 1. This diagram applies to the case where the SiC register bits are set as follows: SMi2=0 (SOUTi output), SMi3=1 (SOUTi output, CLKi function), SMi4=0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock), SMi5=0 (LSB first) and SMi6=1 (internal clock) 2. When the SMi6 bit = 1 (internal clock), the SOUTi pin is placed in the high-impedance state after the transfer finishes. 3. If the SMi6 bit=0 (internal clock), the serial I/O starts sending or receiving data a maximum of 0.5 to 1.0 transfer clock cy cles after writing to the SiTRR register. "H" "L" "H" "L" "H" "L" "H" "L" "H" "L" "1" "0" (2) When the SMi4 bit = 1 (NOTE 3) D1 D2 D3 D4 D5 D6 D7 D1 D2 D3 D4 D5 D6 D7 D0SINi SOUTi CLKi (1) When the SMi4 bit in the SiC register = 0 NOTES: 1. This diagram applies to the case where the SiC register bits are set as follows: SMi5=0 (LSB first) and SMi6=1 (internal clock) 2. When the SMi6 bit=1 (internal clock), a high level is output from the CLKi pin if not transferring data. 3. When the SMi6 bit=1 (internal clock), a low level is output from the CLKi pin if not transferring data. D1 D2 D3 D4 D5 D6 D7D0 D1 D2 D3 D4 D5 D6 D7D0SINi SOUTi CLKi (NOTE 2) i=3 and 4

M16C/62P Group (M16C/62P , M16C/62PT) 17. Serial Interface Rev.2.41 Jan 10, 2006 Page 232 of 390 REJ09B0185-0241

17.2.3 Functions for Setting an S OUTi Initial Value

If the SMi6 bit in the SiC register = 0 (external clock), the SOUTi pin output can be fixed high or low when not transferring. However, the last bit value of the former data is retained be tween data and data when transmitting the continuous data. Figure 17.43 shows the timing chart for setting an SOUTi initial value and how to set it. Figure 17.43 SOUTi’s Initial Value Setting Signal written to SiTRR register SOUTi (internal) SMi7 bit SOUTi pin output SMi3 bit Setting the SOUTi initial value to “H” (2) Port selection switching (I/O port → SOUTi) (i = 3, 4) Initial value = H (3) Port output D0 (Example) When “H” Selected for SOUTi Initial Value (1) NOTES: 1. This diagram applies to the case where the bits in the SiC register are set as follows: SMi2 = 0 (SOUTi output), SMi5 = 0 (LSB first) and SMi6 = 0 (external clock) 2. SOUTi can only be initialized when input on the CLKi pin is in the high state if the SMi4 bit in the SiC register = 0 (transmit data output at the falling edge of the transfer clock) or in the low state if the SMi4 bit = 1 (transmit data output at the rising edge of the transfer clock). 3. If the SMi6 bit = 1 (internal clock) or if the SMi2 bit = 1 (SOUT output disabled), this output goes to the high-impedance state. “H” level is output from the SOUTi pin Serial transmit/reception starts Setting of the initial value of SOUTi output and starting of transmission/ reception Set the SMi7 bit to “1” (SOUTi initial value = H) Set the SMi3 bit to “1” (SOUTi pin functions as SOUTi output) Write to the SiTRR register Set the SMi3 bit to “0” (SOUTi pin functions as an I/O port)

M16C/62P Group (M16C/62P , M16C/62PT) 18. A/D Converter Rev.2.41 Jan 10, 2006 Page 233 of 390 REJ09B0185-0241 18. A/D Converter The microcomputer contains one A/D converter circuit based on 10-bit successive approximation method configured with a capacitive-coupling amplifier. The analog inputs shar e the pins with P10_0 to P10_7, P9_5, P9_6, and P0_0 to P0_7, and P2_0 to P2_7. Similarly, ADTRG input shares the pin with P9_7. Therefore, when using these inputs, make sure the corresponding port direction bits are set to “0” (= input mode). When not using the A/D converter, set the VCUT bit to “0” (= Vref unconnected), so that no current will flow from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip. The A/D conversion result is stored in the ADi register bits for ANi, AN0_i, and AN2_i pins (i = 0 to 7). Table 18.1 shows the Performance of A/D Converter. Fi gure 18.1 shows the A/D Converter Block Diagram, and Figures 18.2 and 18.3 show the A/D converter-related registers. NOTES: 1. Does not depend on use of sample and hold function. 2. φAD frequency must be 12 MHz or less. And divide the fAD if VCC1 is less than 4.0V, and φAD frequency into 10 MHz or less. When sample & hold is disabled, φAD frequency must be 250kHz or more. When sample & hold is enabled, φAD frequency must be 1MHz or more. 3. If VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins. Table 18.1 Performance of A/D Converter Item Performance Method of A/D Conversion Successive approximation (capacitive coupling amplifier) Analog input Voltage (1) 0V to AVCC (VCC1) Operating clock φAD (2) fAD/divide-by-2 of fAD/divide-by-3 of fAD/divide-by-4 of fAD/divide-by-6 of fAD/divide-by-12 of fAD Resolution 8-bit or 10-bit (selectable) Integral Nonlinearity Error When AVCC = VREF = 5V

• With 8-bit resolution: ±2LSB
• With 10-bit resolution AN0 to AN7 input, AN0_0 to AN0_7 input and AN2_0 to AN2_7 input : 3LSB ANEX0 and ANEX1 input (including mode in which external Op-Amp is connected) ±7LSB When AVCC = VREF = 3.3V
• With 8-bit resolution: ±2LSB
• With 10-bit resolution AN0 to AN7 input, AN0_0 to AN0_7 input and AN2_0 to AN2_7 input : ±5LSB ANEX0 and ANEX1 input (including mode in which external Op-Amp is connected) : ±7LSB Operating Modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 Analog Input Pins (3) 8 pins (AN0 to AN7) + 2 pins (ANEX0 and ANEX1) + 8 pins (AN0_0 to AN0_7) + 8 pins (AN2_0 to AN2_7) A/D Conversion Start Condition
• Software trigger The ADST bit in the ADCON0 register is set to “1” (A/D conversion starts)
• External trigger (retriggerable) Input on the ADTRG pin changes state from high to low after the ADST bit is set to “1” (A/D conversion starts) Conversion Speed • Without sample and hold function 8-bit resolution: 49 φAD cycles, 10-bit resolution: 59 φAD cycles
• With sample and hold function 8-bit resolution: 28 φAD cycles, 10-bit resolution: 33 φAD cycles

M16C/62P Group (M16C/62P , M16C/62PT) 18. A/D Converter Rev.2.41 Jan 10, 2006 Page 234 of 390 REJ09B0185-0241 Figure 18.1 A/D Converter Block Diagram ANEX0 ANEX1 OPA0=1 OPA1=1 PM01 to PM00=00b ADGSEL1 to ADGSEL0=10b OPA1 to OPA0=11b ADGSEL1 to ADGSEL0=00b OPA1 to OPA0=11b =000b =001b =010b =011b =100b =101b =110b =111b AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN0_0 AN0_1 AN0_2 AN0_3 AN0_4 AN0_5 AN0_6 AN0_7 Vref VIN CH2 to CH0 PM00 PM01 Decoder for channel selection AD0 register (16) Data bus low-order VREF AVSS VCUT Data bus high-order OPA1=1 Port P10 group Port P0 group PM01 to PM00=00b ADGSEL1 to ADGSEL0=10b OPA1 to OPA0=00b ADGSEL1 to ADGSEL0=00b OPA1 to OPA0=00b OPA1 to OPA0 =01b AN2_0 AN2_1 AN2_2 AN2_3 AN2_4 AN2_5 AN2_6 AN2_7 PM01 to PM00=00b ADGSEL1 to ADGSEL0=11b OPA1 to OPA0=11b PM01 to PM00=00b ADGSEL1 to ADGSEL0=11b OPA1 to OPA0=00b fAD 1/3 CKS2 1/21/2 φAD A/D conversion rate selection Resistor ladder Successive conversion register ADCON0 register ADCON1 register Comparator Decoder for A/D register AD1 register (16) AD2 register (16) AD3 register (16) AD4 register (16) AD5 register (16) AD6 register (16) AD7 register (16) ADCON2 register Port P2 group ADTRG TRG

1 A/D triggerSoftware trigger

=000b =001b =010b =011b =100b =101b =110b =111b =000b =001b =010b =011b =100b =101b =110b =111b CH2 to CH0 CH2 to CH0 (1) NOTES : 1. Port P0 group (AN0_0 to AN0_7) can be used as analog input pins even when PM01 to PM00 bits are set to “01b” (memory expansion mode) and PM05 to PM04 bits are set to “11b” (multiplex bus allocated to the entire CS space). CKS CKS1

M16C/62P Group (M16C/62P , M16C/62PT) 18. A/D Converter Rev.2.41 Jan 10, 2006 Page 235 of 390 REJ09B0185-0241 Figure 18.2 ADCON0 to ADCON1 Registers A/D Control Register 0 (1) Symbol Address After Reset AD C ON 0 03D6h 00000XXXb Bit Symbol Bit Name Function RW 0 : Softw are trigger 1 : ADTRG trigger NOTES : RW RW Frequency Select Bit 0 Refer to NOTE 3 for the ADCON2 Register AD ST RW A/D Operation Mode Select Bit 0b4 b3 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sw eep mode 1 1 : Repeat sw eep mode 0 or Repeat sw eep mode 1 CH2 RW Analog Input Pin Select Bit Function varies w ith each operation modeCH0 RW CH1 RW b3 b2 b1 b0b7 b6 b5 b4 If the ADCON0 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate. RW MD1 A/D Conversion Start Flag MD0 0 : A/D conversion disabled 1 : A/D conversion started CKS0 TRG Trigger Select Bit RW A/D Control Register 1 (1) Symbol Address After Reset AD C ON 1 03D7h 00h Symbol Address After Reset RW NOTES : 0 : Vref not connected 1 : Vref connected Function varies w ith each operation mode RW CKS1 BITS 8/10-Bit Mode Select Bit 0 : 8-bit mode 1 : 10-bit mode Frequency Select Bit 1 Refer to NOTE 3 for the ADCON2 Register If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), w ait for 1 µs or more before starting A/D conversion. b7 b6 b5 b4 b3 b2 b1 b0 SCAN0 RW SCAN1 RW MD2 RW A/D Sw eep Pin Select Bit Function varies w ith each operation mode A/D Operation Mode Select Bit 1 0 : Any mode other than repeat sw eep mode 1 1 : Repeat sw eep mode 1 If the ADCON1 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate. OPA1 RW RW VC U T Vref Connect Bit (2) RW OPA0 RWExternal Op-Amp Connection Mode Bit

M16C/62P Group (M16C/62P , M16C/62PT) 18. A/D Converter Rev.2.41 Jan 10, 2006 Page 236 of 390 REJ09B0185-0241 Figure 18.3 ADCON2 Register A/D Control Register 2 (1) Symbol A DCON2 Bit Symbol RW NOTES : CKS0 A/D Input Group Select Bit b2 b1 0 0 : Port P10 group is selected 0 1 : Do not set 1 0 : Port P0 group is selected (2) 1 1 : Port P2 group is selected If VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins. Frequency Select Bit 2 (3) (b7-b5) — 03D4h Divide-by-3 of fAD fAD Res erv ed Bit Nothing is assigned. When w rite, set to “0”. When read, their contents are “0”. After R eset 00h CKS1 The ØAD frequency must be 12 MHz or less. The selected ØAD frequency is determined by a combination of the CKS0 bit in the ADCON0 register, the CKS1 bit in the ADCON1 register, and the CKS2 bit in the ADCON2 register. Set to “0” 0: Selects fAD, fAD divided by 2, or fAD divided by 4. 1: Selects fAD divided by 3, fAD divided by 6, or fAD divided by 12. Address Bit Name Function 0 : Without sample and hold 1 : With sample and hold A/D Conversion Method Select Bit Divide-by-6 of fAD Divide-by-4 of fAD Divide-by-2 of fAD ØAD Ddivide-by-12 of fAD If the ADCON2 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate. CKS2 RW CKS2 RW RW AD GSE L0 RW AD GSE L1 RW SMP (b3) b7 b6 b5 b4 b3 b2 b1 b0

M16C/62P Group (M16C/62P , M16C/62PT) 18. A/D Converter Rev.2.41 Jan 10, 2006 Page 237 of 390 REJ09B0185-0241 Figure 18.4 AD0 to AD7 Registers A/D Register i (i=0 to 7) Symbol After Reset AD 0 Indeterminate AD 1 Indeterminate AD 2 Indeterminate AD 3 Indeterminate AD 4 Indeterminate AD 5 Indeterminate AD 6 Indeterminate AD7 Indeterminate RW RW When read, the content is indeterminate Nothing is assigned. When w rite, set to “0”. When read, their contents are “0”. Address 03C1h to 03C0h 03C3h to 03C2h 03C5h to 03C4h 03C7h to 03C6h 03C9h to 03C8h 03CBh to 03CAh 03CDh to 03CCh Function Eight low -order bits of A/D conversion result A/D conversion result 03CFh to 03CEhb7 RO RO When the BITS bit in the ADCON1 register is “1” (10-bit mode) When the BITS bit is “0” (8-bit mode) Tw o high-order bits of A/D conversion result (b15) (b8)

M16C/62P Group (M16C/62P , M16C/62PT) 18. A/D Converter Rev.2.41 Jan 10, 2006 Page 238 of 390 REJ09B0185-0241

18.1 Mode Description

18.1.1 One-Shot Mode

In one-shot mode, analog voltage applied to a selected pin is converted to a digital code once. Table 18.2 shows the One-Shot Mode Specifications. Figure 18.5 shows the ADCON0 and ADCON1 Registers (One-shot Mode). NOTES: 1. If VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins. Table 18.2 One-Shot Mode Specifications Item Specification Function The CH2 to CH0 bits in the ADCON0 register, the ADGSEL1 to ADGSEL0 bits in the ADCON2 register and the OPA1 to OPA0 bits in the ADCON1 register select a pin. Analog voltage applied to the pin is converted to a digital code once. A/D Conversion Start Condition

• When the TRG bit in the ADCON0 register is “0” (software trigger) The ADST bit in the ADCON0 register is set to “1” (A/D conversion starts)
• When the TRG bit is “1” (ADTRG trigger) Input on the ADTRG pin changes state from high to low after the ADST bit is set to “1” (A/D conversion starts) A/D Conversion Stop Condition
• Completion of A/D conversion (If a software trigger is selected, the ADST bit is cleared to “0” (A/D conversion halted))
• Set the ADST bit to “0” Interrupt Request Generation Timing Completion of A/D conversion Analog Input Pin (1) Select one pin from AN0 to AN7, AN0_0 to AN0_7, AN2_0 to AN2_7, ANEX0 to ANEX1 Reading of Result of A/D Converter Read one of the AD0 to AD7 registers that corresponds to the selected pin

M16C/62P Group (M16C/62P , M16C/62PT) 18. A/D Converter Rev.2.41 Jan 10, 2006 Page 239 of 390 REJ09B0185-0241 Figure 18.5 ADCON0 and ADCON1 Registers (One-shot Mode) A/D Control Register 0 (1) Symbol Address After Reset A DCON0 03D6h 00000XXXb Bit Symbol Bit Name Function RW 0 : Softw are trigger 1 : ADTRG trigger NOTES : A/D Operation Mode Select Bit 0 (3) b4 b3 0 0 : One-shot mode CH2 RW CKS0 RW RW TRG Trigger Select Bit RW AD ST RW CH0 RW CH1 RW Analog Input Pin Select Bit (2, 3) b2 b1 b0 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected b3 b2 b1 b0b7 b6 b5 b4 If the ADCON0 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate. After rew riting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using another instruction. RW MD1 A/D Conversion Start Flag MD0 AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same w ay as AN0 to AN7. Use the ADGSEL1 to ADGSEL0 bits in the ADCON2 register to select the desired pin. How ever, if VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins. Frequency Select Bit 0 Refer to NOTE 3 for the ADCON2 Register 0 : A/D conversion disabled 1 : A/D conversion started A/D Control Register 1 (1) Symbol Address After Reset A DCON1 03D7h 00h Symbol Address After Reset RW NOTES : OPA1 RW RW V CUT Vref Connect Bit (2) RW OPA0 RWExternal Op-Amp Connection Mode Bit b7 b6 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A/D converted 1 0 : ANEX1 input is A/D converted 1 1 : External op-amp connection mode RW SCAN1 RW MD2 RWA/D Operation Mode Select Bit 1 Set to “0” w hen one-shot mode is selected A/D Sw eep Pin Select Bit Invalid in one-shot mode b7 b6 b5 b4 Ref er to N OTE 3 for the AD CO N 2 R egister b3 b2 b1 b0 SCAN0 1 : Vref connected If the ADCON1 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate. If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), w ait for 1 µs or more before starting A/D conversion. RW CKS1 BITS 8/10-Bit Mode Select Bit 0 : 8-bit mode 1 : 10-bit mode Frequency Select Bit 1

M16C/62P Group (M16C/62P , M16C/62PT) 18. A/D Converter Rev.2.41 Jan 10, 2006 Page 240 of 390 REJ09B0185-0241

18.1.2 Repeat Mode

In repeat mode, analog voltage applied to a selected pi n is repeatedly converted to a digital code. Table 18.3 shows the Repeat Mode Specifications. Figure 18.6 shows the ADCON0 and ADCON1 Registers (Repeat Mode). NOTES: 1. If VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins. Table 18.3 Repeat Mode Specifications Item Specification Function The CH2 to CH0 bits in the ADCON0 register, the ADGSEL1 to ADGSEL0 bits in the ADCON2 register and the OPA1 to OPA0 bits in the ADCON1 register select a pin. Analog voltage applied to this pin is repeatedly converted to a digital code. A/D Conversion Start Condition

• When the TRG bit in the ADCON0 register is “0” (software trigger) The ADST bit in the ADCON0 register is set to “1” (A/D conversion starts)
• When the TRG bit is “1” (ADTRG trigger) Input on the ADTRG pin changes state from high to low after the ADST bit is set to “1” (A/D conversion starts) A/D Conversion Stop Condition Set the ADST bit to “0” (A/D conversion halted) Interrupt Request Generation timing None generated Analog Input Pin (1) Select one pin from AN0 to AN7, AN0_0 to AN0_7, AN2_0 to AN2_7, ANEX0 to ANEX1 Reading of Result of A/D Converter Read one of the AD0 to AD7 registers that corresponds to the selected pin

M16C/62P Group (M16C/62P , M16C/62PT) 18. A/D Converter Rev.2.41 Jan 10, 2006 Page 241 of 390 REJ09B0185-0241 Figure 18.6 ADCON0 and ADCON1 Registers (Repeat Mode) A/D Control Register 0 (1) Symbol Address After Reset A DCON0 03D6h 00000XXXb Bit Symbol Bit Name Function RW 0 : Softw are trigger 1 : ADTRG trigger NOTES : If the ADCON0 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same w ay as AN0 to AN7. Use the ADGSEL1 to ADGSEL0 bits in the ADCON2 register to select the desired pin. How ever, if VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins. RW MD1 A/D Conversion Start Flag MD0 Frequency Select Bit 0 AD ST b7 b6 b5 b4 b3 b2 b1 b0 RW CH0 RW CH1 RW RW TRG Trigger Select Bit RW A/D Operation Mode Select Bit 0 (3) b4 b3 0 1 : Repeat mode After rew riting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using another instruction. Ref er to N OTE 3 for the AD CON 2 R egister Analog Input Pin Select Bit (2, 3) 0 : A/D conversion disabled 1 : A/D conversion started b2 b1 b0 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selectedCH2 RW CKS0 RW A/D Control Register 1 (1) Symbol Address After Reset A DCON1 03D7h 00h Symbol Address After Reset RW NOTES : OPA1 RW RW V CUT Vref Connect Bit (2) RW OPA0 RWExternal Op-Amp Connection Mode Bit b7 b6 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A/D converted 1 0 : ANEX1 input is A/D converted 1 1 : External op-amp connection mode RW SCAN1 RW MD2 RWA/D Operation Mode Select Bit 1 Set to “0” w hen repeat mode is selected A/D Sw eep Pin Select Bit Invalid in repeat mode b7 b6 b5 b4 Ref er to N OTE 3 for the AD CO N 2 R egister b3 b2 b1 b0 SCAN0 1 : Vref connected If the ADCON1 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate. If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), w ait for 1 µs or more before starting A/D conversion. RW CKS1 BITS 8/10-Bit Mode Select Bit 0 : 8-bit mode 1 : 10-bit mode Frequency Select Bit 1

M16C/62P Group (M16C/62P , M16C/62PT) 18. A/D Converter Rev.2.41 Jan 10, 2006 Page 242 of 390 REJ09B0185-0241

18.1.3 Single Sweep Mode

In single sweep mode, analog voltage that is applied to selected pins is converted one-by-one to a digital code. Table 18.4 shows the Single Sweep Mode Specifications. Figure 18.7 shows the ADCON0 Register and ADCON1 Register (Single Sweep Mode). NOTES: 1. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7. However, if VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins. Table 18.4 Single Sweep Mode Specifications Item Specification Function The SCAN1 to SCAN0 bits in th e ADCON1 register and the ADGSEL1 to ADGSEL0 bits in the ADCON2 register select pins. Analog voltage applied to this pins is converted one-by-one to a digital code. A/D Conversion Start Condition

• When the TRG bit in the ADCON0 register is “0” (software trigger) The ADST bit in the ADCON0 register is set to “1” (A/D conversion starts)
• When the TRG bit is “1” (ADTRG trigger) Input on the ADTRG pin changes state from high to low after the ADST bit is set to “1” (A/D conversion starts) A/D Conversion Stop Condition
• Completion of A/D conversion (If a software trigger is selected, the ADST bit is cleared to “0” (A/D conversion halted))
• Set the ADST bit to “0” Interrupt Request Generation timing Completion of A/D conversion Analog Input Pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), AN0 to AN7 (8 pin) (1) Reading of Result of A/D Converter Read one of the AD0 to AD7 registers that corresponds to the selected pin

M16C/62P Group (M16C/62P , M16C/62PT) 18. A/D Converter Rev.2.41 Jan 10, 2006 Page 243 of 390 REJ09B0185-0241 Figure 18.7 ADCON0 Register and ADCO N1 Register (Single Sweep Mode) A/D Control Register 0 (1) Symbol Address After Reset A DCON0 03D6h 00000XXXb Bit Symbol Bit Name Function RW 0 : Softw are trigger 1 : ADTRG trigger NOTES : 1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate. RW MD1 A/D Conversion Start Flag MD0 Frequency Select Bit 0 Refer to NOTE 3 for the ADCON2 Re gis te r 0 : A/D conversion disabled 1 : A/D conversion started b7 b6 b5 b4 b3 b2 b1 b0 CH0 RW CH1 RW Analog Input Pin Select Bit Invalid in single sw eep mode CKS0 RW RW TRG Trigger Select Bit RW AD ST RW A/D Operation Mode Select Bit 0 b4 b3 1 0 : Single sw eep mode CH2 RW A/D Control Register 1 (1) Symbol Address After Reset A DCON1 03D7h 00h Symbol Address After Reset RW NOTES : AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same w ay as AN0 to AN7. Use the ADGSEL1 to ADGSEL0 bits in the ADCON2 register to select the desired pin. How ever, if VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins. If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), w ait for 1 µs or more before starting A/D conversion. 1 : Vref connected If the ADCON1 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate. RW CKS1 BITS 8/10-Bit Mode Select Bit 0 : 8-bit mode 1 : 10-bit mode Frequency Select Bit 1 Refer to N OTE 3 for the AD CO N 2 R egister b3 b2 b1 b0 SCAN0 b7 b6 b5 b4 RW SCAN1 RW MD2 RWA/D Operation Mode Select Bit 1 Set to “0” w hen single sw eep mode is selected A/D Sw eep Pin Select Bit (2) When single sw eep mode is selected b1 b0 0 0 : AN0 to AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) OPA1 RW RW V CUT Vref Connect Bit (3) RW OPA0 RWExternal Op-Amp Connection Mode Bit b7 b6 0 0 : ANEX0 and ANEX1 are not used 0 1 : Do not set to this value 1 0 : Do not set to this value 1 1 : External op-amp connection mode

M16C/62P Group (M16C/62P , M16C/62PT) 18. A/D Converter Rev.2.41 Jan 10, 2006 Page 244 of 390 REJ09B0185-0241

18.1.4 Repeat Sweep Mode 0

In repeat sweep mode 0, analog voltage applied to selected pins is repeatedly converted to a digital code. Table 18.5 shows the Repeat Sweep Mode 0 Specific ations. Figure 18.8 shows the ADCON0 Register and ADCON1 Registers (Repeat Sweep Mode 0). NOTES: 1. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7. However, if VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins. Table 18.5 Repeat Sweep Mode 0 Specifications Item Specification Function The SCAN1 to SCAN0 bits in th e ADCON1 register and the ADGSEL1 to ADGSEL0 bits in the ADCON2 register select pins. Analog voltage applied to the pins is repeatedly converted to a digital code. A/D Conversion Start Condition

• When the TRG bit in the ADCON0 register is “0” (software trigger) The ADST bit in the ADCON0 register is set to “1” (A/D conversion starts)
• When the TRG bit is “1” (ADTRG trigger) Input on the ADTRG pin changes state from high to low after the ADST bit is set to “1” (A/D conversion starts) A/D Conversion Stop Condition Set the ADST bit to “0” (A/D conversion halted) Interrupt Request Generation timing None generated Analog Input Pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), AN0 to AN7 (8 pin) (1) Reading of Result of A/D Converter Read one of the AD0 to AD7 registers that corresponds to the selected pin

M16C/62P Group (M16C/62P , M16C/62PT) 18. A/D Converter Rev.2.41 Jan 10, 2006 Page 245 of 390 REJ09B0185-0241 Figure 18.8 ADCON0 Register and ADCON1 Registers (Repeat Sweep Mode 0) A/D Control Register 1 (1) Symbol Address After Reset A DCON1 03D7h 00h Symbol Address After Reset RW NOTES : OPA1 RW RW V CUT Vref Connect Bit (3) RW OPA0 RWExternal Op-Amp Connection Mode Bit b7 b6 0 0 : ANEX0 and ANEX1 are not used 0 1 : Do not set to this value 1 0 : Do not set to this value 1 1 : External op-amp connection mode RW SCAN1 RW MD2 RWA/D Operation Mode Select Bit 1 Set to “0” w hen repeat sw eep mode 0 is selected A/D Sw eep Pin Select Bit (2) When repeat sw eep mode 0 is selected b1 b0 0 0 : AN0 to AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) b7 b6 b5 b4 Frequency Select Bit 1 Refer to NOTE 3 for the ADCON2 Register b3 b2 b1 b0 SCAN0 AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same w ay as AN0 to AN7. Use the ADGSEL1 to ADGSEL0 bits in the ADCON2 register to select the desired pin. How ever, if VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins. If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), w ait for 1 µs or more before starting A/D conversion. 1 : Vref connected If the ADCON1 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate. RW CKS1 BITS 8/10-Bit Mode Select Bit 0 : 8-bit mode 1 : 10-bit mode A/D Control Register 0 (1) Symbol Address After Reset A DCON0 03D6h 00000XXXb Bit Symbol Bit Name Function RW 0 : Softw are trigger 1 : ADTRG trigger NOTES : CKS0 RW RW TRG Trigger Select Bit RW AD ST RW A/D Operation Mode Select Bit 0 b4 b3 1 1 : Repeat sw eep mode 0 or Repeat sw eep mode 1 CH0 RW CH1 RW Analog Input Pin Select Bit Invalid in repeat sw eep mode 0 CH2 RW b3 b2 b1 b0b7 b6 b5 b4 If the ADCON0 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate. RW MD1 A/D Conversion Start Flag MD0 Frequency Select Bit 0 Refer to NOTE 3 for the ADCON2 Register 0 : A/D conversion disabled 1 : A/D conversion started

M16C/62P Group (M16C/62P , M16C/62PT) 18. A/D Converter Rev.2.41 Jan 10, 2006 Page 246 of 390 REJ09B0185-0241

18.1.5 Repeat Sweep Mode 1

In repeat sweep mode 1, analog voltage selectively applied to all pins is repeatedly converted to a digital code. Table 18.6 shows the Repeat Sweep Mode 1 Specific ations. Figure 18.9 shows the ADCON0 Register and ADCON1 Register (Repeat Sweep Mode 1). NOTES: 1. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7. However, if VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins. Table 18.6 Repeat Sweep Mode 1 Specifications Item Specification Function The input voltages on all pins selected by the ADGSEL1 to ADGSEL0 bits in the ADCON2 register are A/D converted repeatedly, with priority given to pins selected by the SCAN1 to SCAN0 bits in the ADCON1 register and ADGSEL1 to ADGSEL0 bits. Example : If AN0 selected, input voltages are A/D converted in order of AN0 →AN1→AN0→AN2→AN0→AN3, and so on. A/D Conversion Start Condition

• When the TRG bit in the ADCON0 register is “0” (software trigger) The ADST bit in the ADCON0 register is set to “1” (A/D conversion starts)
• When the TRG bit is “1” (ADTRG trigger) Input on the ADTRG pin changes state from high to low after the ADST bit is set to “1” (A/D conversion starts) A/D Conversion Stop Condition Set the ADST bit to “0” (A/D conversion halted) Interrupt Request Generation timing None generated Analog Input Pins to be Given Priority when A/D Converted Select from AN0 (1 pin), AN0 to AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins) (1) Reading of Result of A/D Converter Read one of the AD0 to AD7 registers that corresponds to the selected pin

M16C/62P Group (M16C/62P , M16C/62PT) 18. A/D Converter Rev.2.41 Jan 10, 2006 Page 247 of 390 REJ09B0185-0241 Figure 18.9 ADCON0 Register and ADCO N1 Register (Repeat Sweep Mode 1) A/D Control Register 0 (1) Symbol Address After Reset A DCON0 03D6h 00000XXXb Bit Symbol Bit Name Function RW 0 : Softw are trigger 1 : ADTRG trigger NOTES : 1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate. RW MD1 A/D Conversion Start Flag MD0 Frequency Select Bit 0 Refer to NOTE 3 for the ADCON2 Register 0 : A/D conversion disabled 1 : A/D conversion started b7 b6 b5 b4 b3 b2 b1 b0 CH0 RW CH1 RW Analog Input Pin Select Bit Invalid in repeat sw eep mode 1 CH2 RW CKS0 RW RW TRG Trigger Select Bit RW AD ST RW A/D Operation Mode Select Bit 0 b4 b3 1 1 : Repeat sw eep mode 0 or Repeat sw eep mode 1 A/D Control Register 1 (1) Symbol Address After Reset A DCON1 03D7h 00h Symbol Address After Reset RW NOTES : AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same w ay as AN0 to AN7. Use the ADGSEL1 to ADGSEL0 bits in the ADCON2 register to select the desired pin. How ever, if VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins. If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), w ait for 1 µs or more before starting A/D conversion. 1 : Vref connected If the ADCON1 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate. RW CKS1 BITS 8/10-Bit Mode Select Bit 0 : 8-bit mode 1 : 10-bit mode Frequency Select Bit 1 Refer to NOTE 3 for the ADCON2 Register b3 b2 b1 b0 SCAN0 b7 b6 b5 b4 RW SCAN1 RW MD2 RWA/D Operation Mode Select Bit 1 Set to “1” w hen repeat sw eep mode 1 is selected A/D Sw eep Pin Select Bit (2) When repeat sw eep mode 1 is selected b1 b0 0 0 : AN0 (1 pins) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) OPA1 RW RW V CUT Vref Connect Bit (3) RW OPA0 RWExternal Op-Amp Connection Mode Bit b7 b6 0 0 : ANEX0 and ANEX1 are not used 0 1 : Do not set to this value 1 0 : Do not set to this value 1 1 : External op-amp connection mode

M16C/62P Group (M16C/62P , M16C/62PT) 18. A/D Converter Rev.2.41 Jan 10, 2006 Page 248 of 390 REJ09B0185-0241

18.2 Function

18.2.1 Resolution Select Function

The desired resolution can be selected using the BITS bit in the ADCON1 register. If the BITS bit is set to “1” (10-bit conversion accuracy), the A/D conversion result is stored in the bit 0 to bit 9 in the ADi register (i = 0 to 7). If the BITS bit is set to “0” (8-bit conversion accuracy), the A/D conversion result is stored in the bit 0 to bit 7 in the ADi register.

18.2.2 Sample and Hold

If the SMP bit in the ADCON2 register is set to “1” (with sample-and-hold), the conversion speed per pin is increased to 28 φAD cycles for 8-bit resolution or 33 φAD cycles for 10-bit resolution. Sample and Hold is effective in all operating modes. Select whether or not to use the Sample and Hold function before starting A/D conversion.

18.2.3 Extended Analog Input Pins

In one-shot and repeat modes, the ANEX0 and ANEX1 pins can be used as analog input pins. Use the OPA1 to OPA0 bits in the ADCON1 register to select whether or not use ANEX0 and ANEX1. The A/D conversion results of AN EX0 and ANEX1 inputs are stored in the AD0 and AD1 registers, respectively. 18.2.4 18.2.4 External Operation Am plifier (Op-Amp) Connection Mode Multiple analog inputs can be amplified using a single external op-amp via the ANEX0 and ANEX1 pins. Set the OPA1 to OPA0 bits in the ADCON1 register to “11b” (external op-amp connection mode). The inputs from ANi (i = 0 to 7) (1) are output from the ANEX0 pin. Amplify this output with an external op-amp before sending it back to the ANEX1 pin. The A/D conversion result is stored in the corresponding ADi register. The A/D conversion speed depends on the response characteris tics of the external op-amp. Figure 18.10 shows an example of How to Connect the Pins in External Op-Amp. 1. AN0_i and AN2_i can be used the same as ANi. However, if VCC2 < VCC1, do not use AN0_i and AN2_i as analog input pins. Figure 18.10 External Op-Amp Connection Resistor ladder Successive conversion register AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADGSEL1 to ADGSEL0 bits in ADCON2 register = 00b ANEX0 ANEX1 External Op-Amp ADGSEL1 to ADGSEL0 bits = 10b ADGSEL1 to ADGSEL0 bits = 11b Microcomputer AN0_0 AN0_1 AN0_2 AN0_3 AN0_4 AN0_5 AN0_6 AN0_7 AN2_0 AN2_1 AN2_2 AN2_3 AN2_4 AN2_5 AN2_6 AN2_7 Comparator

M16C/62P Group (M16C/62P , M16C/62PT) 18. A/D Converter Rev.2.41 Jan 10, 2006 Page 249 of 390 REJ09B0185-0241 18.2.5 18.2.5 Current Cons umption Reducing Function When not using the A/D converter, its resistor ladder and reference voltage input pin (VREF) can be separated using the VCUT bit in the ADCON1 register. When separated, no current will flow from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip. To use the A/D converter, set the VCUT bit to “1” (Vref connected) and then set the ADST bit in the ADCON0 register to “1” (A/D conversion start). The VCUT and ADST bits cannot be set to “1” at the same time. Nor can the VCUT bit be set to “0” (Vref unconnected) during A/D conversion. Note that this does not affect VREF for the D/A converter (irrelevant).

18.2.6 Output Impedance of Se nsor under A/D Conversion

To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 18.11 has to be completed within a specified period of time. T (sampli ng time) as the specified ti me. Let output impedance of sensor equivalent circuit be R0, internal resistance of microcomputer be R, pr ecision (error) of the A/D converter be X, and the resolution of A/D converter be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode). VC is generally And when t = T, Hence, Figure 18.11 shows Analog Input Pin and External Sensor Equivalent Circuit. When the difference between VIN and VC becomes 0.1LSB, we find impedance R0 when voltage between pins VC changes from 0 to VIN- (0.1/1024) VIN in time T. (0.1/1024) means that A/D precision drop due to insufficient capacitor charge is held to 0.1LSB at time of A/D conversion in the 10-bit mode. Actual error however is the value of absolute precision added to 0.1LSB. When f(φAD) = 10 MHz, T = 0.3 µs in the A/D conversion mode with sample & hold. Output impedance R0 for sufficiently charging capacitor C within time T is determined as follows. Thus, the allowable output impedance of the sensor equi valent circuit, making the precision (error) 0.1LSB or less, is approximately 13.9 kΩ. maximum. R0 T C X Y----ln• Y----ln= e Y----= VC VIN X Y---- VIN VIN 1 X Y----–⎝⎠ ⎛⎞=–= VC VIN 1 e ⎧⎫= R0 0.3 10 6–× 1.5 10 12– 0.1

M16C/62P Group (M16C/62P , M16C/62PT) 18. A/D Converter Rev.2.41 Jan 10, 2006 Page 250 of 390 REJ09B0185-0241 Figure 18.11 Analog Input Pin and Exte rnal Sensor Equivalent Circuit R0 R (7.8k Ω) C (1.5pF) VIN VC Sampling time φADSample and hold enabled: φADSample and hold disabled: Microcomputer Sensor equivalent circuit

M16C/62P Group (M16C/62P , M16C/62PT) 19. D/A Converter Rev.2.41 Jan 10, 2006 Page 251 of 390 REJ09B0185-0241 19. D/A Converter This is an 8-bit, R-2R type D/A converter. These are two independent D/A converters. D/A conversion is performed by writing to the DAi register (i = 0 to 1). To output the result of conversion, set the DAiE bit in the DACON register to “1 ” (output enabled). Before D/A conversion can be used, the corresponding port direction bit must be cleared to “0” (input mode). Setting the DAiE bit to “1” removes a pull-up from the corresponding port. Output analog voltage (V) is determined by a set value (n : decimal) in the DAi register. V = VREF X n/ 256 (n = 0 to 255) VREF : reference voltage shows the D/A converter related registers. Figure 19.3 shows the D/A Converter Equivalent Circuit. Figure 19.1 D/A Converter Block Diagram Table 19.1 D/A Con verter Performance Item Performance D/A Conversion Method R-2R method Resolution 8 bits Analog Output Pin 2 channels (DA0 and DA1) DA0 DA1 Data Bus Low-order DA0 Register R-2R Resistor Ladder DA0E Bit DA1 Register R-2R Resistor Ladder DA1E Bit

M16C/62P Group (M16C/62P , M16C/62PT) 20. CRC Calculation Rev.2.41 Jan 10, 2006 Page 254 of 390 REJ09B0185-0241 Figure 20.3 CRC Calculation (2) Write 0000h (initial value) b15 b0 CRCD register 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 1000 1000 Generator polynomial Data CRC code Modulo-2 operation is operation that complies with the law given below. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 -1 = 1 Setup procedure and CRC operation when generating CRC code “80C4h”

• CRC operation performed by the M16C CRC code: Remainder of a division in which the value written to the CRCIN register with its bit positions reversed is divided by the generator polynomial (1) Reverse the bit positions of the value “80C4h” by program in 1-byte units. (3) Write 01h b0b7 b15 b0 CRCIN register CRCD register1189h Two cycles later, the CRC code for “80h”, i.e., 9188h, has its bit positions reversed to become “1189h” which is stored in the CRCD register.
• Details of CRC operation As shown in (3) above, bit position of “01h” (00000001b) written to the CRCIN register is inversed and becomes “10000000b”. Add “1000 0000 0000 0000 0000 0000b”, as “10000000b” plus 16 digits, to “0000 0000 0000 0000 0000 0000b”, as “0000 0000 0000 0000b” plus 8 digits as the default value of the CRCD register to perform the modulo-2 division. “0001 0001 1000 1001b (1189h)”, the remainder “1001 0001 1000 1000b (9188h)” with inversed bit position, can be read from the CRCD register. When going on to (4) above, “23h (00100011b)” written in the CRCIN register is inversed and becomes “11000100b”. Add “1100 0100 0000 0000 0000 0000b”, as “11000100b” plus 16 digits, to “1001 0001 1000 1000 0000 0000b”, as “1001 0001 1000 1000b” plus 8 digits as a remainder of (3) left in the CRCD register to perform the modulo-2 division. “0000 1010 0100 0001b (0A41h)”, the remainder with inversed bit position, can be read from CRCD register.
• Setting procedure Generator polynomial: X 16 + X12 + X5 + 1 (1 0001 0000 0010 0001b) (4) Write 23h b0b7 b15 b0 0A41h CRCIN register CRCD register Two cycles later, the CRC code for “80C4h”, i.e., 8250h, has its bit positions reversed to become “0A41h” which is stored in the CRCD register.

M16C/62P Group (M16C/62P , M16C/62PT) 21. Programmable I/O Ports Rev.2.41 Jan 10, 2006 Page 255 of 390 REJ09B0185-0241 21. Programmable I/O Ports The programmable input/output ports (hereafter referred to simp ly as I/O ports) consist of 113 lines P0 to P14 for the 128-pin version, 87 lines P0 to P10 for the 100-pin version, or 70 lines P0 to P10 for the 80-pin version. Each port can be set for input or output every line by using a direction register, and can also be chosen to be or not be pulled high every 4 lines. P8_5 is an input-only port and does not have a pull-up resistor. Port P8_5 shares the pin with NMI , so that the NMI input level can be read from the P8 register P8_5 bit. Table 21.1 lists the Number of Pins of the Programmable I/ O Ports of Each Package. Figure 21.1 to Figure 21.5 show the I/O ports. Figure 21.6 shows the I/O Pins. Each pin functions as an I/O port, a peripheral function input/output, or a bus control pin. For details on how to set peripheral functions, refer to each fu nctional description in this manual. If any pin is used as a peripheral function input or D/A converter output pin, set the direction bit for that pin to “0” (input mode). Any pin used as an output pin for peripheral functions other than the D/A converter is directed for output no matter how the corresponding direction bit is set. When using any pin as a bus control pin, refer to 8.2 Bus Control. P0 to P5, P12, and P13 are capable of VCC2-level input/output; P6 to P11 and P14 are capable of VCC1- level input/ output. NOTES: 1. There is no connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Table 21.1 Number of Pins of the Programmable I/O Ports of Each Package 128-pin Version 100-pin Version 80-pin version (1) Programmable I/O Ports P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7 (P8_5 is an input port), P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7 (P8_5 is an input port), P9_0 to P9_7, P10_0 to P10_7, P0_0 to P0_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_3, P5_0 to P5_7, P6_0 to P6_7, P8_0 to P8_4, P8_6, P8_7 (P8_5 is an input port), P9_0, P9_2 to P9_7, P10_0 to P10_7, Total 113 pins 87 pins 70 pins There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in the M16C/62P (80-pin version) and the M16C/62PT (80-pin version). Set the direction bits in these ports to “1” (output mode), and set the output data to “0” (“L”) using the program. Moreover, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0 and P14_1 pins do not exist. Therefore, P11 to P13, PC14 and PUR13 register do not exist. Note

M16C/62P Group (M16C/62P , M16C/62PT) 21. Programmable I/O Ports Rev.2.41 Jan 10, 2006 Page 256 of 390 REJ09B0185-0241

21.1 Port Pi Direction Register (PDi Register, i = 0 to 13)

Figure 21.7 shows the PDi Registers. This register selects whether the I/O port is to be used for input or output. The bits in this register correspond one for one to each port. During memory extension and microprocessor modes, the PDi registers for the pins functioning as bus control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and BCLK) cannot be modified. No direction register bit for P8_5 is available.

21.2 Port Pi Register (Pi Register, i = 0 to 13)

Figure 21.8 shows the Pi Registers. Data input/output to and from external devices are accomplished by reading and writing to the Pi register. The Pi register consists of a port latch to hold the input/output data and a circuit to read the pin status. For ports set for input mode, the input level of the pin can be read by reading the corresponding Pi register, and data can be written to the port latch by writing to the Pi register. For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and data can be written to the port latch by writing to the Pi register. The data written to the port latch is output from the pin. The bits in the Pi register correspond one for one to each port. During memory extension and microprocessor modes, the PDi registers for the pins functioning as bus control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and BCLK) cannot be modified.

21.3 Pull-up Control Register 0 to Pull -up Control Register 3 (PUR0 to PUR3

Registers) Figure 21.9 and Figure 21.11 shows the PURi Registers. The PUR0 to PUR2 register bi ts can be used to select whether or not to pull the corresponding port high in 4 bit units. The port chosen to be pulled high has a pull-up resistor connected to it when the direction bit is set for input mode. To use ports P11 to P14, set the PU37 bit in the PUR3 register to “1”. However, the pull-up control register has no effect on P0 to P3, P4_0 to P4_3, and P5 during memory extension and microprocessor modes. Although the register contents can be modified, no pull-up resistors are connected.

21.4 Port Control Register (PCR Register)

Figure 21.12 shows the PCR Register. When the P1 register is read after setting the PCR0 bit in the PCR register to “1”, the corresponding port latch can be read no matter how the PD1 register is set.

M16C/62P Group (M16C/62P , M16C/62PT) 21. Programmable I/O Ports Rev.2.41 Jan 10, 2006 Page 257 of 390 REJ09B0185-0241 Figure 21.1 I/O Ports (1) P1_0 to P1_4 P1_5 to P1_7 Data bus (NOTE 1) Analog input P0_0 to P0_7, P2_0 to P2_7 P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_4, P5_6, P11_0 to P11_7 (2), P14_0, P14_1 (2) (inside dotted-line included) (inside dotted-line not included) “1” Output Data bus Data bus Data bus Pull-up selection Direction register Direction register Direction register Direction register Port latch Port latch Port latch Port latch Pull-up selection Pull-up selection Pull-up selection (NOTE 1) (NOTE 1) (NOTE 1) Port P1 control register Port P1 control register Input to respective peripheral functions Input to respective peripheral functions NOTES: 1. Symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed VCC. VCC: VCC1 for the port P6 to P11 and P14, and VCC2 for the port P0 to P5 and P12 to P13. 2. Available in only the 128-pin version.

M16C/62P Group (M16C/62P , M16C/62PT) 21. Programmable I/O Ports Rev.2.41 Jan 10, 2006 Page 258 of 390 REJ09B0185-0241 Figure 21.2 I/O Ports (2) NOTES: 1. Symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed VCC. VCC: VCC1 for the port P6 to P11 and P14, and VCC2 for the port P0 to P5 and P12 to P13. P8_2 to P8_4 Data bus Pull-up selection Direction register Port latch Input to respective peripheral functions (NOTE 1) Output Data bus Direction register Port latch Pull-up selection (NOTE 1) Input to respective peripheral functions Switching between CMOS and Nch Data bus Pull-up selection Direction register Port latch Input to respective peripheral functions (NOTE 1)

M16C/62P Group (M16C/62P , M16C/62PT) 21. Programmable I/O Ports Rev.2.41 Jan 10, 2006 Page 259 of 390 REJ09B0185-0241 Figure 21.3 I/O Ports (3) P6_2, P6_6 Data bus Pull-up selection Direction register Port latch Input to respective peripheral functions P7_0, P7_1 Data bus Direction register Port latch Input to respective peripheral functions Output “1” P8_5 Data bus NMI interrupt input P6_3, P6_7 Output “1” Data bus Pull-up selection Direction register Port latch Switching between CMOS and Nch Switching between CMOS and Nch NOTES: 1. Symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed VCC. VCC: VCC1 for the port P6 to P11 and P14, and VCC2 for the port P0 to P5 and P12 to P13. 2. symbolizes a parasitic diode. (NOTE 1) (NOTE 1) (NOTE 1) (NOTE 2)

M16C/62P Group (M16C/62P , M16C/62PT) 21. Programmable I/O Ports Rev.2.41 Jan 10, 2006 Page 260 of 390 REJ09B0185-0241 Figure 21.4 I/O Ports (4) P9_3, P9_4 P9_6 P9_5 Data bus Direction register Pull-up selection Port latch Analog input Input to respective peripheral functions P10_0 to P10_3 (Inside dotted-line not included) P10_4 to P10_7 (Inside dotted-line included) D/A output enabled Analog output “1” Output Direction register Direction register Direction register Data bus Data bus Data bus Port latch Port latch Port latch Analog input Analog input Pull-up selection Pull-up selection Pull-up selection Input to respective peripheral functions Input to respective peripheral functions D/A output enabled “1” Output NOTES: 1. Symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed VCC. VCC: VCC1 for the port P6 to P11 and P14, and VCC2 for the port P0 to P5 and P12 to P13. (NOTE 1) (NOTE 1) (NOTE 1) (NOTE 1)

M16C/62P Group (M16C/62P , M16C/62PT) 21. Programmable I/O Ports Rev.2.41 Jan 10, 2006 Page 262 of 390 REJ09B0185-0241 Figure 21.7 PDi Registers Port Pi Direction Register (i=0 to 7 and 9 to 13) (1, 2, 3) After R eset 00h 03EAh, 03EBh, 03EEh, 03EFh 00h 00h 00h Bit Symbol RW NOTES : 3. To use ports P11 to P14, set the PU37 bit in the PUR3 register to “1” (enable). PD13 03FBh During memory extension and microprocessor modes, the PDi register for the pins functioning as bus control pins (A0 to A19, D0 to D15, CS0 to CS3 , RD ___ , WRL /WR ___ , WRH /BHE , ALE, RDY , HOLD , HLDA and BCLK) cannot be modified. Make sure the PD9 register is w ritten to by the next instruction after setting the PRC2 bit in the PRCR register to “1” (w rite enabled). PDi_6 RW PDi_5 Port Pi_6 Direction Bit Address RW Port Pi_5 Direction Bit PD9 to PD12 Symbol PD0 to PD3 PD4 to PD7 03E2h, 03E3h, 03E6h, 03E7h RW PDi_3 RW PDi_2 b7 b6 b5 b4 b3 b2 b1 b0 RW 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) (i = 0 to 7 and 9 to 13) Port Pi_0 Direction Bit Port Pi_1 Direction Bit Port Pi_2 Direction Bit Port Pi_3 Direction Bit Port Pi_4 Direction Bit RW RW RW PDi_0 Port Pi_7 Direction BitPDi_7 03F3h, 03F6h, 03F73h, 03FAh FunctionBit Name PDi_1 PDi_4 Port P8 Direction Register After R eset 00X00000b Bit Symbol RW Nothing is assigned. When w rite, set to “0”. When read, its content is indeterminate. 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) PD8_6 Bit Name PD8_1 RW (b5) Por t P8_6 Dir ec tion Bit PD8_4 RW RW PD8_3 RW Symbol PD8 PD8_2 Address 03F2h RW Function b3 b2 b1 b0b7 b6 b5 b4 Por t P8_7 Dir ec tion BitPD8_7 RW Por t P8_0 Dir ec tion Bit Por t P8_1 Dir ec tion Bit Por t P8_2 Dir ec tion Bit Por t P8_3 Dir ec tion Bit Por t P8_4 Dir ec tion Bit PD8_0 RW

M16C/62P Group (M16C/62P , M16C/62PT) 21. Programmable I/O Ports Rev.2.41 Jan 10, 2006 Page 263 of 390 REJ09B0185-0241 Figure 21.8 Pi Registers Port P8 Register After R eset Indeterminate Bit Symbol RW RW Function RW P8_5 Port P8_6 Bit RO P8_4 RW P8_6 Bit Name P8_2 Address 03F0h P8_1 RW b3 b2 b1 b0 The pin level on any I/O port w hich is set for input mode can be read by reading the corresponding bit in this register. The pin level on any I/O port w hich is set for output mode can be controlled by w riting to the corresponding bit in this register (except for P8_5) 0 : “L” level 1 : “H” level RW P8_3 RW Symbol b7 b6 b5 b4 Port P8_7 BitP8_7 RW Port P8_0 Bit Port P8_1 Bit Port P8_2 Bit Port P8_3 Bit Port P8_4 Bit P8_0 Port P8_5 Bit Port Pi Register (i=0 to 7 and 9 to 13) (2, 3) After R eset Indeterminate Indeterminate Indeterminate Indeterminate Bit Symbol RW NOTES : Since P7_0 and P7_1 are N-channel open drain ports, the data is high-impedance. Pi_6 RW Pi_5 Por t Pi_6 Bit Por t Pi_5 Bit RW Pi_4 RW RW Pi_3 RW Symbol P0 to P3 P4 to P7 Pi_2 Address 03E0h, 03E1h, 03E4h, 03E5h 03E8h, 03E9h, 03ECh, 03EDh Pi_1 RW b3 b2 b1 b0 03F9h RW FunctionBit Name Pi_0 b7 b6 b5 b4 P13 Por t Pi_1 Bit Por t Pi_2 Bit Por t Pi_3 Bit Por t Pi_4 Bit To use ports P11 to P14, set the PU37 bit in the PUR3 register to “1” (enable). If this bit is set to “0” (disable), the P11 to P14 registers are cleared to “0”. P9 to P12 03F1h, 03F4h, 03F5h, 03F8h During memory extension and microprocessor modes, the Pi register for the pins functioning as bus control pins (A0 to A19, D0 to D15, CS0 to CS3 , RD ___ , WRL /WR ___ , WRH /BHE , ALE, RDY , HOLD , HLDA and BCLK) cannot be modified. Por t Pi_7 BitPi_7 RW The pin level on any I/O port w hich is set for input mode can be read by reading the corresponding bit in this register. The pin level on any I/O port w hich is set for output mode can be controlled by w riting to the orresponding bit in this register 0 : “L” level 1 : “H” level (1) (i = 0 to 7 and 9 to 13) Por t Pi_0 Bit

M16C/62P Group (M16C/62P , M16C/62PT) 21. Programmable I/O Ports Rev.2.41 Jan 10, 2006 Page 264 of 390 REJ09B0185-0241 Figure 21.9 PC14 and PUR3 Registers Pull-Up Control Register 3 (128-Pin Package) After R eset 00h Bit Symbol RW NOTES : The pin for w hich this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high. If the PU37 bit is set to “0” (unusable), the P11 to P14 registers are cleared to “0”. RW RW PU33 RW P11 to P14 EnablingPU37 PU35 P14_0, P14_1 Pull-UP RW PU34 RW PU36 0 : Not pulled high 1 : Pulled high (1) PUR3 PU32 Address 03DFh PU31 Symbol PU30 FunctionBit Name b3 b2 b1 b0b7 b6 b5 b4 RW P11_0 to P11_3 Pull-UP P11_4 to P11_7 Pull-UP P12_0 to P12_3 Pull-UP P12_4 to P12_7 Pull-UP P13_0 to P13_3 Pull-UP P13_4 to P13_7 Pull-UP RW RW 0 : Unusable (2) 1 : Usable Port P14 Control Register (128-Pin Package) After R eset XX00XXXXb Bit Symbol RW Nothing is assigned. When w rite, set to “0”. When read, their contents are indeterminate. Nothing is assigned. When w rite, set to “0”. When read, their contents are indeterminate. 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) Port P14_0 Direction Bit Port P14_1 Direction Bit RW Function PD141 RW PD140 RW (b7-b6) Bit Name RW PC14 Address 03DEh P141 The pin level on any I/O port w hich is set for input mode can be read by reading the corresponding bit in this register. The pin level on any I/O port w hich is set for output mode can be controlled by w riting to the corresponding bit in this register (except for P8_5) 0 : “L” level 1 : “H” level b3 b2 b1 b0 (b3-b2) — Symbol b7 b6 b5 b4 Por t P14_0 Bit Por t P14_1 Bit P140

M16C/62P Group (M16C/62P , M16C/62PT) 21. Programmable I/O Ports Rev.2.41 Jan 10, 2006 Page 265 of 390 REJ09B0185-0241 Figure 21.10 PUR0 and PUR1 Registers Pull-up Control Register 0 (1) After R eset 00h Bit Symbol RW NOTES : RW PU05 P3_0 to P3_3 Pull-Up P2_4 to P2_7 Pull-Up RW PU06 PU04 PU00 RW RW PU03 RW PU02 P2_0 to P2_3 Pull-Up RW RW FunctionBit Name b3 b2 b1 b0b7 b6 b5 b4 P1_4 to P1_7 Pull-Up Address 03FCh PU01 Symbol PUR0 During memory extension and microprocessor modes, the pins are not pulled high although their corresponding register contents can be modified. The pin for w hich this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high. P3_4 to P3_7 Pull-UpPU07 RW 0 : Not pulled high 1 : Pulled high (2) P0_0 to P0_3 Pull-Up P0_4 to P0_7 Pull-Up P1_0 to P1_3 Pull-Up Pull-Up Control Register 1 After R eset (5) 00000000b 00000010b Bit Symbol RW NOTES : During memory extension and microprocessor modes, the pins are not pulled high although the contents of these bits can be modified. The values after hardw are reset 1 and low voltage detection reset (hardw are reset 2) are as follow s:

• 00000000b w hen input on CNVSS pin is “L”
• 00000010b w hen input on CNVSS pin is “H” The values after softw are reset, w atchdog timer reset and oscillation stop detection reset are as follow s:
• 00000000b w hen PM01 to PM00 bits are “00b” (single-chip mode)
• 00000010b w hen PM01 to PM00 bits are “01b” (memory expansion mode) or “11b” (microprocessor mode) If the PM01 to PM00 bits in the PM0 register are set to “01b” (memory expansion mode) or “11b” (microprocessor mode) in a program during single-chip mode, the PU11 bit becomes “1”. The P7_0 and P7_1 pins do not have pull-ups. PU16 RW PU15 P7_2 to P7_3 Pull-Up (1) P6_4 to P6_7 Pull-Up RW P5_4 to P5_7 Pull-Up (2) P6_0 to P6_3 Pull-Up Symbol PUR1 PU10 PU14 RW RW PU13 RW b3 b2 b1 b0 Address 03FDh The pin for w hich this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high. b7 b6 b5 b4 RW FunctionBit Name P7_4 to P7_7 Pull-UpPU17 RW 0 : Not pulled high 1 : Pulled high (3) P4_0 to P4_3 Pull-Up (2) P4_4 to P4_7 Pull-Up (4) P5_0 to P5_3 Pull-Up (2)PU12 PU11 RW

M16C/62P Group (M16C/62P , M16C/62PT) 21. Programmable I/O Ports Rev.2.41 Jan 10, 2006 Page 267 of 390 REJ09B0185-0241 NOTES: 1. When setting the port for output mode and leave it open, be aware that the port remains in input mode until it is switched to output mode in a prog ram after reset. For this reason, the voltage level on the pin becomes indeterminate, causing the pow er supply current to increase while the port remains in input mode. Furthermore, by cons idering a possibility that the contents of the direction registers could be changed by noise or noise-induced runaway, it is re commended that the contents of the direction registers be periodically reset in software, for the increased reliability of the program. 2. Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins (within 2 cm). 3. When the ports P7_0 and P7_1 are set for output mode, make sure a low-level signal is output from the pins. The ports P7_0 and P7_1 are N-channel open-drain outputs. 4. With external clock input to XIN pin. 5. Process the port without a pin in the 80-pin version and the 100-pin version as follows. 80-pin version

• Set the direction bits in these ports to “1” (output mode), and set the output data to “0” (“L”) using the program.
• Ports P11 to P14 do not exist. 100-pin version
• After reset, PU37 bit is “0” (P11 to P14 do not used). Do not write “1” to PU37 bit. When read, value of PU37 bit is indeterminate.
• The port direction bit in the P11 to P14 can be set “0” or “1”. Table 21.2 Unassigned Pin Handling in Single-chip Mode Pin Name Connection Ports P0 to P7, P8_0 to P8_4, P8_6 to P8_7, P9 to P14 After setting for input mode, connect every pin to VSS via a resistor (pull- down); or after setting for output mode, leave these pins open. (1, 2, 3, 5) XOUT (4) Open NMI Connect via resistor to VCC1 (pull-up) AVCC Connect to VCC1 AVSS, VREF, BYTE Connect to VSS

M16C/62P Group (M16C/62P , M16C/62PT) 21. Programmable I/O Ports Rev.2.41 Jan 10, 2006 Page 268 of 390 REJ09B0185-0241 NOTES: 1. When setting the port for output mode and leave it open, be aware that the port remains in input mode until it is switched to output mode in a prog ram after reset. For this reason, the voltage level on the pin becomes indeterminate, causing the pow er supply current to increase while the port remains in input mode. Furthermore, by cons idering a possibility that the contents of the direction registers could be changed by noise or noise-induced runaway, it is re commended that the contents of the direction registers be periodically reset in software, for the increased reliability of the program. 2. Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins (within 2 cm). 3. If the CNVSS pin has the VSS level applied to it, these pins are set for input ports until the processor mode is switched over in a program after reset. For this reason, the voltage levels on these pins become indeterminate, causing the power supply current to increase while they remain set for input ports. 4. When the ports P7_0 and P7_1 are set for output mode, make sure a low-level signal is output from the pins. The ports P7_0 and P7_1 are N-channel open-drain outputs. 5. With external clock input to XIN pin. 6. If the PM07 bit in the PM0 register is set to “1 ” (BCLK not output), connect this pin to VCC2 via a resistor (pulled high). 7. Process the port without a pin in the 100-pin version as follows.

• After reset, PU37 bit is “0” (P11 to P14 do not used). Do not write “1” to PU37 bit. When read, value of PU37 bit is indeterminate.
• The port direction bit in the P11 to P14 can be set “0” or “1”. Table 21.3 Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode Pin Name Connection Ports P0 to P7, P8_0 to P8_4, P8_6 to P8_7, P9 to P14 After setting for input mode, connect every pin to VSS via a resistor (pull- down); or after setting for output mode, leave these pins open. (1, 2, 3, 4, 7) P4_5/CS1 to P4_7/CS3 Connect to VCC2 via a resistor (pulled high) by setting the corresponding direction bit in the PD4 register for CSi (i=1 to 3) to “0” (input mode) and the CSi bit in the CSR register to “0” (chip select disabled). BHE, ALE, HLDA, XOUT (5), BCLK (6) Open HOLD, RDY Connect via resistor to VCC2 (pull-up) NMI (P8_5) Connect via resistor to VCC1 (pull-up) AVCC Connect to VCC1 AVSS, VREF Connect to VSS

M16C/62P Group (M16C/62P , M16C/62PT) 21. Programmable I/O Ports Rev.2.41 Jan 10, 2006 Page 269 of 390 REJ09B0185-0241 Figure 21.13 Unassigned Pins Handling NMI XOUT AVCC BYTE AVSS VREF Microcomputer VCC1 VSS In single-chip mode Port P0 to P14 (except for P8_5) (2) NMI XOUT AVCC AVSS VREF Open Microcomputer VCC2 VSS In memory expansion mode or in microprocessor mode HOLD RDY ALE BCLK (1) BHE HLDAOpen Open Open Port P4_5 / CS1 to P4_7 / CS3 NOTES : 1. If the PM07 bit in the PM0 register is set to “1” (BCLK not output), connect this pin to VCC2 via a resistor (pulled high). 2. When not using all of the P11 to P14, the P11 to P14 pins may be left open by setting the PU37 bit in the PUR3 register to “0” (P11 to P14 unusable) without causing any problem. VCC1 VCC2 VCC1 VCC1 (Input mode) (Input mode) (Output mode) (Input mode) (Input mode) (Output mode) Port P6 to P14 (except for P8_5) (2)

M16C/62P Group (M16C/62P , M16C/62PT) 22. Flash Memory Version Rev.2.41 Jan 10, 2006 Page 270 of 390 REJ09B0185-0241 22. Flash Memory Version Aside from the built-in flash memory, the flash memory ve rsion microcomputer has the same functions as the masked ROM version. In the flash memory version, the flash memory can perform in three rewrite modes: CPU rewrite mode, standard serial I/O mode and parallel I/O mode. Table 22.1 lists specifications of the flash memory version. See Table 1.1 to Table 1.3 Performance outline of M16C/62PT group for the items not listed in Table 22.1. NOTES: 1. The boot ROM area contains a standard serial I/ O mode rewrite control program which is stored in it when shipped from the factory. This area can only be rewritten in parallel input/output mode. 2. Can be programmed in byte units in only parallel input/output mode. 3. Block 1 and block A are 10,000 times of programmi ng and erasure. All other blocks are 1,000 times of programming and erasure. 4. Definition of program and erase endurance The programming and erasure times are defined to be per-block erasure times. For example, assume a case where a 4-Kbyte block A is programmed in 2,048 operations by writing one word at a time and erased thereafter. In this case, the block is reckoned as having been programmed and erased once. If a product is 100 times of programming and erasur e, each block in it can be erased up to 100 times. When 10,000 times of programming and erasure, block 1 and block A can each be erased up to 10,000 times. All other blocks can each be erased up to 1,000 times. Table 22.1 Flash Memory Version Specifications Item Specification Flash Memory Rewrite Mode 3 modes (CPU rewr ite, standard serial I/O, parallel I/O) Erase Block User ROM Area See Figure 22.1 Flash Memory Block Diagram Boot ROM Area 1 block (4 Kbytes) (1) Program Method In units of word, in units of byte (2) Erase Method Collective erase, block erase Program and Erase Control Method Program and erase controlled by software command Protect Method The lock bit protects each block Number of Commands 8 commands Program and Erase Endurance 100 times, 1,000 times/10,000 times (option) (3, 4) Data Retention 10 years ROM Code Protection Parallel I/O and standard serial I/O modes are supported

M16C/62P Group (M16C/62P , M16C/62PT) 22. Flash Memory Version Rev.2.41 Jan 10, 2006 Page 271 of 390 REJ09B0185-0241 NOTES: 1. The PM13 bit remains set to “1” while the FMR01 bit in the FMR0 register = 1 (CPU rewrite mode enabled). The PM13 bit is reverted to its original value by cleari ng the FMR01 bit to “0” (CPU rewrite mode disabled). However, if the PM13 bit is changed during CPU rewrite mode, its changed value is not reflected until after the FMR01 bit is cleared to “0”. 2. When in CPU rewrite mode, the PM10 and PM13 bits in th e PM1 register are set to “1”. The rewrite control program can only be executed in the internal RAM or in an external area that is enabled for use when the PM13 bit = 1. When the PM13 bit = 0 and the flash memory is used in 4-Mbyte mode, the extended accessible area (40000h to BFFFFh) cannot be used. Table 22.2 Flash Memory Rewrite Modes Overview Flash Memory Rewrite Mode CPU rewrite Mode (1) Standard Serial I/O Mode Parallel I/O Mode Function The User ROM area is rewritten when the CPU executes software commands. EW0 mode: Rewrite in areas other than flash memory (2) EW1 mode: Can be rewritten in the flash memory The user ROM area is rewritten using a dedicated serial programmer. Standard serial I/O mode 1: Clock synchronous serial I/O Standard serial I/O mode 2: UART The boot ROM area and user ROM area is rewritten using a dedicated parallel programmer. Areas which can be Rewritten User ROM area User ROM area User ROM area Boot ROM area Operating Mode Single-chip mode Memory expansion mode (EW0 mode) Boot mode (EW0 mode) Boot mode Parallel I/O mode ROM Programmer None Serial programmer Parallel programmer

M16C/62P Group (M16C/62P , M16C/62PT) 22. Flash Memory Version Rev.2.41 Jan 10, 2006 Page 272 of 390 REJ09B0185-0241

22.1 Memory Map

The flash memory contains the user ROM area and the boot ROM area. The user ROM area has space to store the microcomputer operating program in single-chip mode or memory expansion mode and a separate 4-Kbyte space as the block A. Figure 22.1 shows a Flash Memory Block Diagram. The user ROM area is divided into several blocks, each of which can be protected (locked) from program or erase. The user ROM area can be rewritten in CPU rewrite, standard serial I/O and parallel I/O modes. Block A is enabled for use by setting the PM10 bit in the PM1 register to “1” (block A enabled, CS2 area at addresses 10000h to 26FFFh). The boot ROM area is located at the same addresses as the user ROM area. It can only be rewritten in parallel I/O mode (refer to 22.1.1 Boot Mode ). A program in the boot ROM area is executed after a hardware reset occurs while an “H” signal is applied to the CNVSS and P5_0 pins and an “L” signal is applied to the P5_5 pin (refer to 22.1.1 Boot Mode). A program in the user ROM area is executed after a hardware reset occurs while an “L” signal is applied to the CNVSS pin. However, the boot ROM area cannot be read. Figure 22.1 Flash Memory Block Diagram 00FFFFh Block A : 4 Kbytes00F000h

4 Kbytes0FF000h

NOTES: 1. The boot ROM area can only be rewritten in parallel input/output mode. 2. To specify a block, use an even address in that block. 3. Shown here is a block diagram during single-chip mode. 4. Block A can be made usable by setting the PM10 bit in the PM1 register to “1” (block A enabled, CS2 area allocated at addresses 10000h to 26FFFh). Block A cannot be erased by the Erase All Unlocked Block command. Use the Block Erase command to erase it. 0F0000h Block 0 to Block 5 (32+8+8+8+4+4) Kbytes 0E0000h Block 6 : 64 Kbytes 0EFFFFh 0D0000h Block 7 : 64 Kbytes 0DFFFFh 0C0000h Block 8 : 64 Kbytes 0CFFFFh 0B0000h Block 9 : 64 Kbytes 0BFFFFh 0A0000h Block 10 : 64 Kbytes 0AFFFFh 0FFFFFh 0FF000h 0FFFFFh Block 0 : 4 Kbytes Block 1 : 4 Kbytes Block 2 : 8 Kbytes 0FE000h 0FEFFFh 0FC000h 0FDFFFh Block 3 : 8 Kbytes 0FA000h 0FBFFFh Block 4 : 8 Kbytes 0F8000h 0F9FFFh Block 5 : 32 Kbytes 0F0000h 0F7FFFh User ROM area 090000h Block 11 : 64 Kbytes 09FFFFh 080000h Block 12 : 64 Kbytes 08FFFFh

M16C/62P Group (M16C/62P , M16C/62PT) 22. Flash Memory Version Rev.2.41 Jan 10, 2006 Page 273 of 390 REJ09B0185-0241

22.1.1 Boot Mode

The microcomputer enters boot mode when a hardware reset occurs while an “H” signal is applied to the CNVSS and P5_0 pins and an “L” signal is applied to the P5_5 pin. A program in the boot ROM area is executed. In boot mode, the FMR05 bit in the FMR0 register selects access to the boot ROM area or the user ROM area. The rewrite control program for standard serial I/O mode is stored in the boot ROM area before shipment. The boot ROM area can be rewritten in parallel I/O mode only. If any rewrite control program using erase-write mode (EW0 mode) is written in the boot ROM area, the flash memory can be rewritten according to the system implemented.

22.2 Functions To Prevent Flash Memory from Rewriting

The flash memory has a built-in ROM code protect functio n for parallel I/O mode and a built-in ID code check function for standard I/O mode to prevent the flash memory from reading or rewriting.

22.2.1 ROM Code Protect Function

The ROM code protect function inhibits the flash memory from being read or rewritten during parallel input/ output mode. Figure 22.2 shows the ROMCP Register. The ROMCP register is located in the user ROM area. The ROM code protect function is enabled when the ROMCR bits are set to other than “11b”. In this case, set the bit 5 to bit 0 to “111111b”. When exiting ROM code protect, eras e the block including the ROMCP1 register by the CPU rewrite mode or the standard serial I/O mode.

22.2.2 ID Code Check Function

Use the ID code check function in st andard serial I/O mode. The ID code sent from the serial programmer is compared with the ID code written in the flash memory for a match. If the ID codes do not match, commands sent from the serial programmer are not accepted. Ho wever, if the four bytes of the reset vector are “FFFFFFFFh”, ID codes are not compared, allowing all commands to be accepted. The ID codes are 7-byte data stored consecutively, starting with the first byte, into addresses 0FFFDFh, 0FFFE3h, 0FFFEBh, 0FFFEFh, 0FFFF3h, 0FFFF7h, and 0F FFFBh. The flash memory must have a program with the ID codes set in these addresses.

M16C/62P Group (M16C/62P , M16C/62PT) 22. Flash Memory Version Rev.2.41 Jan 10, 2006 Page 275 of 390 REJ09B0185-0241

22.3 CPU Rewrite Mode

In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands. The user ROM area can be rewritten with the microcomputer mounted on a board without using a parallel or serial programmer. In CPU rewrite mode, only the user ROM area shown in Figure 22.1 can be rewritten. The boot ROM area cannot be rewritten. Program and the block erase command are executed only in the user ROM area. Erase-write 0 (EW0) mode and erase-write 1 (EW1) mode are provided as CPU rewrit e mode. Table 22.3 lists differences between erase-write 0 (EW0) and erase-write 1 (EW1) modes. NOTES: 1. Do not generate an interrupt (except NMI interrupt) or DMA transfer. 2. 2. When in CPU rewrite mode, the PM10 and PM13 bits in the PM1 register are set to “1”. The rewrite control program can only be executed in the internal RAM or in an external area that is enabled for use when the PM13 bit = 1. When the PM13 bit = 0 and the flash memory is used in 4M- byte mode, the extended accessible area (40000h to BFFFFh) cannot be used. Table 22.3 EW0 Mode and EW1 Mode Item EW0 Mode EW1 Mode Operating Mode • Single-chip mod

• Memory expansion mode
• Boot mode
• Single-chip mode Space where the rewrite control program can be placed
• User ROM area
• Boot ROM area
• User ROM area Space where the rewrite control program can be executed The rewrite control program must be transferred to any space other than the flash memory (e.g., RAM) before being executed (2) The rewrite control program can be executed in the user ROM area Space which can be rewritten User ROM area User ROM area However, this excludes blocks with the rewrite control program Software Command Restriction None • Program and bl ock erase commands cannot be executed in a block having the rewrite control program.
• Erase all unlocked block command cannot be executed when the lock bit in a block having the rewrite control program is set to “1” (unlocked) or when the FMR02 bit in the FMR0 register is set to “1” (lock bit disabled).
• Read status register command cannot be used. Mode after Program or Erasing Read status register mode Read array mode CPU State during Auto Write and Auto Erase Operating Maintains hold state (I/O ports maintains the state before the command was executed) (1) Flash Memory State Detection
• Read the FMR00, FMR06 and FMR07 bits in the FMR0 register by program
• Execute the read status register command to read the SR7, SR5 and SR4 bits in the status register. Read the FMR00, FMR06 and FMR07 bits in the FMR0 register by program

M16C/62P Group (M16C/62P , M16C/62PT) 22. Flash Memory Version Rev.2.41 Jan 10, 2006 Page 276 of 390 REJ09B0185-0241

22.3.1 EW0 Mode

The microcomputer enters CPU rewrit e mode by setting the FMR01 bit in the FMR0 register to “1” (CPU rewrite mode enabled) and is ready to accept commands. EW0 mode is selected by setting the FMR11 bit in the FMR1 register to “0”. To set the FMR01 bit to “1”, set to “1” after first writing “0”. The software commands control program ming and erasing. The FMR0 register or the status register indicates whether a program or erase operation is completed as expected or not.

22.3.2 EW1 Mode

EW1 mode is selected by setting the FMR11 bit to “1” after the FMR01 bit is set to “1”. (Both bits must be set to “0” first before setting to “1”.) The FMR0 register indicates whether or not a program or erase operation has been completed as expected. The status register cannot be read in EW1 mode. When an erase/program operation is initiated the CP U halts all program execution until the operation is completed or erase-suspend is requested.

22.3.3 Flash memory Control Register (FIDR, FMR0 and FMR1 registers)

Figure 22.4 to Figure 22.6 show the FIDR, FMR0 and FMR1 Registers. Figure 22.4 FIDR Register Flash Identification Register (1) Symbol Address After Reset FIDR 01B4h XXXXXX00b Bit Symbol Bit Name Function RW NOTES : FIDR1 Flash Module Type Identification Value b7 b6 b5 b4 b3 b2 b1 This register identifies on-chip flash module type of M16C/62 Group. Note, how ever, no chip version is know n by this register. Follow the procedure described below for the identification. (a) Write “FFh” to FIDR register, (b) Read FIDR register, and (c) Check tw o low -order bits of read value. Make sure no access to external memories or other SFRs or no interrupts or DMA transfers w ill occur between the above tw o instructions (a) and (b). Nothing is assigned. When w rite, set to “0”. When read, their contents are indeterminate. RO (b7-b2) FIDR0 RO b1 b0 0 0 : M16C/62N, M3062GF8N type flash module 1 0 : M16C/62P type flash module 1 1 : M16C/62M, M16C/62A type flash

M16C/62P Group (M16C/62P , M16C/62PT) 22. Flash Memory Version Rev.2.41 Jan 10, 2006 Page 277 of 390 REJ09B0185-0241 Figure 22.5 FMR0 Register Flash Memory Control Register 0 Symbol Address After Reset FMR0 01B7h 00000001b Bit Symbol Bit Name Function RW RY /BY ___ Status Flag NOTES : Effective w hen the FMR01 bit = 1 (CPU rew rite mode). If the FMR01 bit = 0, although the FMR03 bit can be set to “1” by w riting “1” in a program, the flash memory is neither placed in low pow er mode nor initialized. This status includes w riting or reading w ith the Lock Bit Program or Read Lock Bit Status command. Write to this bit w hen the NMI ____ pin is in the high state. Also, w hile in EW0 mode, w rite to this bit from a program in than the flash memory. Enter read array mode and set this bit to “0”. Write to this bit from a program in other than the flash memory. This flag is cleared to “0” by executing the Clear Status command. RO 0 : Disables CPU rew rite mode 1 : Enables CPU rew rite mode CPU Rew rite Mode Select Bit (1) Erase Status Flag (4) 0 : Terminated normally 1 : Terminated in error RW RW RW RWUser ROM Area Select Bit (3) (Effective in Only Boot Mode) 0 : Terminated normally 1 : Terminated in error 0 : Boot ROM area is accessed 1 : User ROM area is accessed 0 : Enables lock bit 1 : Disables lock bit 0 : Enables flash memory operation 1 : Stops flash memory operation (placed in low pow er mode, flash memory initialized) Set to “0” RW FMR07 FMR00 RO0 : Busy (being w ritten or erased) 1 : Ready FMR02 FMSTP (b4) FMR05 RO To set this bit to “1,” w rite “0” and then “1” in succession. Make sure no interrupts or DMA transfers will occur before w riting “1” after w riting “0”. To set this bit to “1,” w rite “0” and then “1” in succession w hen the FMR01 bit = 1. Make sure no interrupts or no DMA transfers w ill occur before w riting “1” after w riting “0”. b3 b2 b1 b0b7 b6 b5 b4 FMR01 FMR06 Lock Bit Disable Select Bit (2) Program Status Flag (4) Flash Memory Stop Bit (3, 5) Reserved Bit

M16C/62P Group (M16C/62P , M16C/62PT) 22. Flash Memory Version Rev.2.41 Jan 10, 2006 Page 278 of 390 REJ09B0185-0241 Figure 22.6 FMR1 Register Flash Memory Control Register 1 Symbol Address After Reset FMR1 01B5h 0X00XX0Xb Bit Symbol Bit Name Function RW NOTES : Write to this bit w hen the NMI ____ pin is in the high state. The FMR01 and FMR11 bits both are cleared to “0” by setting the FMR01 bit to “0”. Reserved Bit Set to “0” RO RWSet to “0” RO 0: EW0 mode 1: EW1 mode EW1 Mode Select Bit (1) (b7) (b0) ROThe value in this bit w hen read is indeterminate (b3-b2) (b5-b4) RW Lock Bit Status Flag 0: Lock 1: Unlock The value in this bit w hen read is indeterminate To set this bit to “1,” w rite “0” and then “1” in succession w hen the FMR01 bit = 1. Make sure no interrupts or DMA transfers w ill occur before w riting “1” after w riting “0”. b3 b2 b1 b0 RW b7 b6 b5 b4 00 0 FMR11 FMR16 Reserved Bit Reserved Bit Reserved Bit

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22.3.3.1 FMR00 Bit

This bit indicates the flash memory op erating state. It is set to “0” whil e the program, block erase, erase all unlocked block, lock bit program, or read lock bit status command is being executed; otherwise, it is set to “1”.

22.3.3.2 FMR01 Bit

The microcomputer can accept commands when the FMR01 bit is set to “1” (CPU rewrite mode). Set the FMR05 bit to “1” (user ROM area access) as well if in boot mode.

22.3.3.3 FMR02 Bit

The lock bit is disabled by setting the FMR02 bit to “1” (lock bit disabled). (Refer to 22.3.6 Data Protect Function.) The lock bit is enabled by setting the FMR02 bit to “0” (lock bit enabled). The FMR02 bit does not change the lock bit status but disa bles the lock bit function. If the block erase or erase all unlocked block command is executed when the FMR02 bit is set to “1”, the lock bit status changes “0” (locked) to “1” (unlocked) after command execution is completed.

22.3.3.4 FMSTP Bit

The FMSTP bit resets the flash memory control circ uits and minimizes power consumption in the flash memory. Access to the flash memory is disabled when the FMSTP bit is set to “1”. Set the FMSTP bit by program in a space other than the flash memory.

• Set the FMSTP bit to “1” if one of the followings occurs: A flash memory access error occurs while erasing or programming in EW0 mode (FMR00 bit does not switch back to “1” (ready)).
• Low-power consumption mode or on-chip oscillator low-power consumption mode is entered Use the following the procedure to change the FMSTP bit setting. (1) Set the FMSTP bit to “1” (2) Set tps (the wait time to stabilize flash memory circuit) (3) Set the FMSTP bit to “0” (4) Set tps (the wait time to stabilize flash memory circuit) Figure 22.9 shows a Flow Chart Illustrating How To St art and Stop the Flash Memory Processing Before and After Low Power Dissipation Mode or On-chip Os cillator Low-Power Consumption Mode. Follow the procedure on this flow chart. When entering stop or wait mode, the flash memory is automatically turned off. When exiting stop or wait mode, the flash memory is turned back on. The FMR0 register does not need to be set.

22.3.3.5 FMR05 Bit

This bit selects the boot ROM or user ROM area in boot mode. Set to “0” to access (read) the boot ROM area or to “1” (user ROM access) to access (read, write or erase) the user ROM area.

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22.3.3.6 FMR06 Bit

This is a read-only bit indicating an auto program opera tion state. The FMR06 bit is set to “1” when a program error occurs; otherwise, it is set to “0”. Refer to 22.3.8 Full Status Check.

22.3.3.7 FMR07 Bit

This is a read-only bit indicating the auto erase opera tion status. The FMR07 bit is set to “1” when an erase error occurs; otherwise, it is set to “0”. For details, refer to 22.3.8 Full Status Check. Figure 22.7 shows Setting and Resetting of EW0 Mode. Figure 22.8 show Setting and Resetting of EW1 Mode.

22.3.3.8 FMR11 Bit

EW0 mode is entered by setting the FMR11 bit to “0” (EW0 mode). EW1 mode is entered by setting the FMR11 bit to “1” (EW1 mode).

22.3.3.9 FMR16 Bit

This is a read-only bit indicating the execution result of the read lock bit status command. When the block, where the read lock bit status command is executed, is locked, the FMR16 bit is set to “0”. When the block, where the read lock bit status command is executed, is unlocked, the FMR16 bit is set to “1”.

M16C/62P Group (M16C/62P , M16C/62PT) 22. Flash Memory Version Rev.2.41 Jan 10, 2006 Page 281 of 390 REJ09B0185-0241 Figure 22.7 Setting and Resetting of EW0 Mode Single-chip mode, memory expansion mode or boot mode Set CM0, CM1 and PM1 registers (1) Procedure to Enter EW0 Mode Rewrite control program Execute the read array command (3) Execute the software commands Jump to the rewrite control program transferred to a space other than the flash memory. (In the following steps, use the rewrite control program in a space other than the flash memory) Transfer the rewrite control program in CPU rewrite mode to a space other than the flash memory (5) In boot mode only Set the FMR05 bit to “0” (boot ROM area accessed) (4) Set the FMR01 bit to “0” (CPU rewrite mode disabled) In boot mode only Set the FMR05 bit to “1” (user ROM area accessed) Set the FMR01 bit to “1” (CPU rewrite mode enabled) after writing “0” (2) Jump to a desired address in the flash memory NOTES : 1. In CPU rewrite mode, set the CM06 bit in the CM0 register and CM17 to 6 bits in the CM1 register to CPU clock frequency of 10.0 MHz or less. Set the PM17 bit in the PM1 register to “1” (with wait state). 2. Set the FMR01 bit to “1” immmediately after setting it to “0” Do not generate an interrupt or a DMA transfer between setting the bit to “0” and setting it to “1”. Set the bit to “0”. Set this in a space other than flash memory while the NMI pin is held “H”. 3. Exit CPU rewrite mode after executing the read array command. 4. When CPU rewrite mode is exited while FMR05 bit is set to “1”, the user ROM area can be accessed. 5.When in CPU rewrite mode, the PM10 and PM13 bits in the PM1 register are set to “1”. The rewrite control program can only be executed in the internal RAM or in an external area that is enabled for use when the PM13 bit = 1. When the PM13 bit = 0 and the flash memory is used in 4M-byte mode, the extended accessible area (40000h to BFFFFh) cannot be used.

M16C/62P Group (M16C/62P , M16C/62PT) 22. Flash Memory Version Rev.2.41 Jan 10, 2006 Page 282 of 390 REJ09B0185-0241 Figure 22.8 Setting and Resetting of EW1 Mode Single-chip mode (1) Set the CM0, CM1, PM1 registers (2) Set the FMR01 bit to “1” (CPU rewrite mode enabled) after writing “0” Set the FMR11 bit to “1” (EW1 mode) after writing “0” (EW1 mode) (3) Program in the ROM Procedure to Enter EW1 Mode Execute the software commands Set the FMR01 bit to 0 (CPU rewrite mode disabled) NOTES: 1. In EW1 mode, do not enter memory expansion or boot mode. 2. In CPU rewrite mode, set the CM06 bit in the CM0 register and the CM17 to 6 bits in the CM1 register to CPU clock frequency of 10.0 MHz or less. Set the PM17 bit in the PM1 register to “1” (with wait state). 3. Set the FMR01 bit to “1” immediately after setting it to “0”. Do not generate an interrupt or a DMA transfer between setting the bit to “0” and setting it to “1”. Set the FMR11 bit to “1” immediately after setting it to “0” while the FMR01 bit is set to “1”. Do not generate an interrupt or a DMA transfer between setting the FMR11 bit to 0 and setting it to “1”. Set the FMR01 and FMR11 bits while “H” is applied to the NMI pin.

M16C/62P Group (M16C/62P , M16C/62PT) 22. Flash Memory Version Rev.2.41 Jan 10, 2006 Page 283 of 390 REJ09B0185-0241 Figure 22.9 Processing Before a nd After Low Power Dissipation Mode or On-chip Oscillator Low- Power Consumption Mode Start main clock oscillation Transfer the low-power consumption mode or on-chip oscillator low-power consumption mode program to a space other than the flash memory Switch clock source of the CPU clock. The main clock stops. (2) Wait until the flash memory stabilizes (tps µs) (3) Set the FMSTP bit to “0” (flash memory operation) Set the FMSTP bit to “1” (The flash memory stops operating. It is in a low-power consumption state) (1) Process in low-power consumption mode or on-chip oscillator low-power consumption mode (4) Switch clock source of the CPU clock (2) Low-power consumption mode or on-chip oscillator low-power consumption mode program Set the FMR01 bit to “0” (CPU rewrite mode disabled) Set the FMR01 bit to “1” after setting it to “0” (CPU rewrite mode enabled) Jump to a desired address in the flash memory Wait until oscillation stabilizes NOTES: 1. Set the FMSTP bit to “1” after the FMR01 bit is set to “1” (CPU rewrite mode enabled). 2. Wait until clock stabilizes to switch clock source of the CPU clock to the main clock or sub clock. 3. Add tps µs wait time by program. Do not access the flash memory during this wait time. 4. Before entering wait mode or stop mode, be sure to set the FMR01 bit to “0”. Jump to the low-power consumption mode or on-chip oscillator low-power consumption mode program transferred to a space other than the flash memory. (In the following steps, use the low-power consumption mode or on-chip oscillator low-power consumption mode program in a space other than the flash memory.)

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22.3.4 Precautions on CPU Rewrite Mode

22.3.4.1 Operating Speed

Set the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register to a CPU clock frequency of 10 MHz or less before entering CPU rewrite mode (EW0 or EW1 mode). Also, set the PM17 bit in the PM1 register to “1” (wait state).

22.3.4.2 Prohibited Instructions

The following instructions cannot be used in EW0 mode because the CPU tries to read data in the flash memory: the UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction.

22.3.4.3 Interrupts (EW0 mode)

• To use interrupts having vectors in a relocatable vect or table, the vectors must be relocated to the RAM area.
• The NMI and watchdog timer interrupts are available since the FMR0 and FMR1 registers are forcibly reset when either interrupt occurs. Allocate the jump addre sses for each interrupt service routines to the fixed vector table. Flash memory rewrite operation is suspended when the NMI or watchdog timer interrupt occurs. Execute the rewrite program again after exiting the interrupt routine.
• The address match interrupt is not available since the CPU tries to read data in the flash memory.

22.3.4.4 Interrupts (EW1 mode)

• Do not acknowledge any interrupts with vectors in th e relocatable vector table or address match interrupt during the auto program or auto erase period.
• Do not use the watchdog timer interrupt.
• The NMI interrupt is available since the FMR0 and FMR1 registers are forcibly re set when the interrupt occurs. Allocate the jump address for the interrupt service routine to the fixed vector table. Flash memory rewrite operation is suspended when the NMI interrupt occurs. Execute th e rewrite program again after exiting the interrupt service routine. To set the FMR01, FMR02 or FMR11 bit to “1”, write “1” after first setting the bit to “0”. Do not generate an interrupt or a DMA transfer between the instruction to set the bit to “0” and the instruction to set the bit to “1”. Set the bit while an “H” signal is applied to the NMI pin. If the supply voltage drops while rewriting the block wh ere the rewrite control program is stored, the flash memory cannot be rewritten because the rewrite control progr am is not correctly rewritten. If this error occurs, rewrite the user ROM area while in standard serial I/O mode or parallel I/O mode. Avoid rewriting any block in which the rewrite control program is stored. In EW1 mode, do not perform a DMA transfer while the FMR00 bit in the FMR0 register is set to “0” (auto programming or auto erasing).

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22.3.4.9 Writing Command and Data

Write commands and data to even addresses in the user ROM area.

22.3.4.10 Wait Mode

When entering wait mode, set the FMR01 bit to “0” (C PU rewrite mode disabled) before executing the WAIT instruction.

22.3.4.11 Stop Mode

When entering stop mode, the following settings are required:

• Set the FMR01 bit to “0” (CPU rewrite mode disabled). Disable DMA transfer before setting the CM10 bit to “1” (stop mode).

22.3.4.12 Low-Power Consumption Mode and On-chip Oscillator Low-power

If the CM05 bit is set to “1” (main clock stopped), do not execute the following commands:

• Program
• Block erase
• Erase all unlocked blocks
• Lock bit program
• Read lock bit status

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22.3.5 Software Commands

Software commands are described below. The command code and data must be read and written in 16-bit units, to and from even addresses in the user ROM area. When writing command c ode, the 8 high-order bits (D15 to D8) are ignored. NOTES: 1. Blocks 0 to 12 can be erased by the erase all unlocked block command. Block A cannot be erased. The block erase command must be used to erase the block A. SRD: Data in the SRD register (D7 to D0) WA: Address to be written (The address specif ied in the first bus cycle is the same even address as the address specified in the second bus cycle.) WD: 16-bit write data BA: Highest-order block address (must be an even address) X: Any even address in the user ROM space xx: 8 high-order bits of command code (ignored)

22.3.5.1 Read Array Command (FFh)

The read array command reads the flash memory. By writing command code “xxFFh” in th e first bus cycle, read array mode is entered. Content of a specified address can be read in 16-bit units after the next bus cycle. The microcomputer remains in read array mode until another command is written. Therefore, contents from multiple addresses can be read consecutively.

22.3.5.2 Read Status Re gister Command (70h)

The read status register command reads the status register (refer to 22.3.7 Status Register for detail). By writing command code “xx70h” in the first bus cycle, the status register can be read in the second bus cycle. Read an even address in the user ROM area. Do not execute this command in EW1 mode.

22.3.5.3 Clear Status Register Command (50h)

The clear status register command clea rs the status register. By writing “xx50h” in the first bus cycle, the FMR07 to FMR06 bits in the FMR0 register are set to “0 0b” and the SR5 to SR4 bits in the status register are set to “00b”. Table 22.4 Software Commands Command First Bus Cycle Second Bus Cycle Mode Address Data (D0 to D7) Mode Address Data (D0 to D7) Read Array Write X xxFFh Read Status Register Write X xx70h Read X SRD Clear Status Register Write X xx50h Program Write WA xx40h Write WA WD Block Erase Write X xx20h Write BA xxD0h Erase All Unlocked Block Write X xxA7h Write X xxD0h Lock Bit Program Write BA xx77h Write BA xxD0h Read Lock Bit Status Write X xx71h Write BA xxD0h

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22.3.5.4 Program Command (40h)

The program command writes 2-byte data to the flash memory. By writing “xx40h” in the first bus cycle and data to the write address in the second bus cycle, an auto program operation (data program and verify) will start. The address value specified in the first bus cycle must be the same even address as the write address specified in the second bus cycle. The FMR00 bit in the FMR0 register indicates whethe r an auto program operation has been completed. The FMR00 bit is set to “0” (busy) during auto program and to “1” (ready) when an auto program operation is completed. After the completion of an auto program operation, the FMR06 bit in the FMR0 register indicates whether or not the auto program operation has been completed as expected. (Refer to 22.3.8 Full Status Check.) An address that is already written cannot be altered or rewritten. Figure 22.10 shows a Flow Chart of the Program Command Programming. The lock bit protects each block from be ing programmed inadvertently. (Refer to 22.3.6 Data Protect Function.) In EW1 mode, do not execute this command on the block where the rewrite control program is allocated. In EW0 mode, the microcomputer enters read status regist er mode as soon as an auto program operation starts. The status register can be read. The SR 7 bit in the status register is set to “0” at the same time an auto program operation starts. It is set to “1” when auto program operation is completed. The microcomputer remains in read status register mode until the read array command is written. After completion of an auto program operation, the status register indicates whether or not the auto program operation has been completed as expected. Figure 22.10 Program Command NOTES: 1. Write the command code and data to even addresses. Start Program operation is completed YES NO Write the command code “xx40h” to an address to be written Write data to an address to be written FMR00=1? Full status check

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22.3.5.5 Block Erase Command

The block erase command erases each block. By writing “xx20h” in the first bus cycle and “xxD0h” to the highest-order even address of a block in the second bus cycle, an auto erase operation (erase and verify) will start in the specified block. The FMR00 bit in the FMR0 register indicates whether an auto erase operation has been completed. The FMR00 bit is set to “0” (busy) during auto eras e and to “1” (ready) when the auto erase operation is completed. After the completion of an auto erase operation, the FM R07 bit in the FMR0 register indicates whether or not the auto erase operation has been completed as expected. (Refer to 22.3.8 Full Status Check.) Figure 22.11 shows a Flow Chart of the Block Erase Command Programming. The lock bit protects each block from be ing programmed inadvertently. (Refer to 22.3.6 Data Protect Function.) In EW1 mode, do not execute this command on the bloc k where the rewrite control program is allocated. In EW0 mode, the microcomputer enters re ad status register mode as soon as an auto erase operation starts. The status register can be read. The SR7 bit in the status re gister is set to “0” at the same time an auto erase operation starts. It is set to “1” when an auto erase operation is completed. The microcomputer remains in read status register mode until the read array command or re ad lock bit status command is written. Also execute the clear status register command and block erase command at least 3 times until an erase error is not generated when an erase error is generated. Figure 22.11 Block Erase Command Write “xxD0h” to the highest-order block address Start Block erase operation is completed YES NO Write the command code “xx20h”(1) FMR00=1? NOTES: 1. Write the command code and data to even addresses. 2. Refer to “Figure 22.14 Full Status Check and Handling Procedure for Each Error”. 3. Execute the clear status register command and block erase command at least 3 times until an erase error is not generated when an erase error is generated. Full status check (2, 3)

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22.3.5.6 Erase All Unlocked Block

The erase all unlocked block command erases all blocks except the block A. By writing “xxA7h” in the first bus cycle and “xxD0h” in the second bus cycle, an auto erase (erase and verify) operation will run continuously in all blocks except the block A. The FMR00 bit in the FMR0 register indicates whether an auto erase operation has been completed. After the completion of an auto erase operation, the FM R07 bit in the FMR0 register indicates whether or not the auto erase operation has been completed as expected. The lock bit can protect each block from being programmed inadvertently. (Refer to 22.3.6 Data Protect Function.) In EW1 mode, do not execute this command when the lock bit for any block storing the rewrite control program is set to “1” (unlocked) or when the FMR02 bit in the FMR0 register is set to “1” (lock bit disabled). In EW0 mode, the microcomputer enters read status register mode as soon as an auto erase operation starts. The status register can be read. The SR7 bit in the status register is set to “0” (busy) at the same time an auto erase operation starts. It is set to “1” (ready) when an auto erase operation is completed. The microcomputer remains in read status register mode until the read array command or read lock bit status command is written. Only blocks 0 to 12 can be erased by the erase all unlocked block command. The block A cannot be erased. Use the block erase command to erase the block A.

22.3.5.7 Lock Bit Program Command

The lock bit program command sets the lock bit for a specified block to “0” (locked). By writing “xx77h” in the first bus cycle and “xxD0h” to the highest-order even address of a block in the second bus cycle, the lock bit for the specified block is set to “0”. The address valu e specified in the first bus cycle must be the same highest-order even address of a block specified in the second bus cycle. Figure 22.12 shows a Flow Chart of the Lock Bit Pr ogram Command Programming. Execute read lock bit status command to read lock bit state (lock bit data). The FMR00 bit in the FMR0 register indicates whether a lock bit program operation is completed. Refer to 22.3.6 Data Protect Function for details on lock bit functions and how to set it to “1” (unlocked). Figure 22.12 Lock Bit Program Command Start Lock bit program operation is completed YES NO Write the command code “xx77h” to the highest-order block address FMR00=1? Full status check Write “xxD0h” to the highest-order block address NOTES: 1. Write the command code and data to even addresses.

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22.3.5.8 Read Lock Bit Status Command (71h)

The read lock bit status command reads the lock bit state of a specified block. By writing “xx71h” in the first bus cycle and “xxD0h” to the highest-order even address of a block in the second bus cycle, the FMR16 bit in th e FMR1 register stores information on whether or not the lock bit of a specified block is locked. Read the FMR16 bit after the FMR00 bit in the FMR0 register is set to “1” (ready). Figure 22.13 shows a Flow Chart of the Read Lock Bit Status Command Programming. Figure 22.13 Read Lock Bit Status Command Block is not locked Write “xxD0h” to the highest-order block address Start Block is locked YES NO Write the command code “xx71h” FMR00=1? YES NO FMR16=0? NOTES: 1. Write the command code and data to even addresses.

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22.3.6 Data Protect Function

Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR02 bit to “0” (lock bit enabled). The lock bit allows each block to be individually protected (locked) against program and erase. This helps prevent data from being inadvertently written to or erased from the flash memory.

• When the lock bit status is set to “0”, the block is locked (block is protected against program and erase).
• When the lock bit status is set to “1”, the block is not locked (block can be programmed or erased). The lock bit status is set to “0” (locked) by executing the lock bit program command and to “1” (unlocked) by erasing the block. The lock bit status cannot be set to “1” by any commands. The lock bit status can be read by the read lock bit status command. The lock bit function is disabled by setting the FMR02 bit to “1”. All blocks are unlocked. However, individual lock bit status remains unchanged. The lock bit functi on is enabled by setting the FMR02 bit to “0”. Lock bit status is retained. If the block erase or erase all unlocked block command is executed while the FMR02 bit is set to “1”, the target block or all blocks are erased regardle ss of lock bit status. The lock bit stat us of each block are set to “1” after an erase operation is completed. Refer to 22.3.5 Software Commands for details on each command.

22.3.7 Status Register

The status register indicates the flash memory operation state and whether or not an erase or program operation is completed as expected. The FMR00, FMR06 and FMR07 bits in the FMR0 register indicate status register states. Table 22.5 shows the Status Register. In EW0 mode, the status register can be read when the followings occur.

• Any even address in the user ROM area is read after writing the read status register command.
• Any even address in the user ROM area is read from when the program , block erase, erase all unlocked block, or lock bit program command is executed until when the read array command is executed.

22.3.7.1 Sequence Status (SR7 and FMR00 Bits)

The sequence status indicates the flash memory operation state. It is set to “0” while the program, block erase, erase all unlocked block, lock bit program, or read lock bit status command is being executed; otherwise, it is set to “1”.

22.3.7.2 Erase Status (SR5 and FMR07 Bits)

Refer to 22.3.8 Full Status Check.

22.3.7.3 Program Status (SR4 and FMR06 Bits)

Refer to 22.3.8 Full Status Check.

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• D0 to D7: These data buses are read when the read status register command is executed.
• The FMR07 bit (SR5) and FMR06 bit (SR4) are set to “0” by executing th e clear status register command.
• When the FMR07 bit (SR5) or FMR06 bit (SR4) is se t to “1,” the program, block erase, erase all unlocked block and lock bit program commands are not accepted. Table 22.5 Status Register Bits in Status Register Bit in FMR0 Register Status name Definition Value after Reset“0” “1” SR0 (D0) − Reserved −− − SR1 (D1) − Reserved −− − SR2 (D2) − Reserved −− − SR3 (D3) − Reserved −− − SR4 (D4) FMR06 Program status Terminated normally Terminated in error 0 SR5 (D5) FMR07 Erase status Terminated normally Terminated in error 0 SR6 (D6) − Reserved −− − SR7 (D7) FMR00 Sequencer status Busy Ready 1

M16C/62P Group (M16C/62P , M16C/62PT) 22. Flash Memory Version Rev.2.41 Jan 10, 2006 Page 293 of 390 REJ09B0185-0241

22.3.8 Full Status Check

If an error occurs when a program or erase operation is completed, the FMR06 to FMR07 bits in the FMR0 register are set to “1”, indicating a specific error. Therefore, execution results can be confirmed by checking these bits (full status check). Table 22.6 lists Errors and FMR0 Register State. Figur e 22.14 shows a flow chart of the Full Status Check and Handling Procedure for Each Error. NOTES: 1. The flash memory enters read array mode by writing command code “xxFFh” in the second bus cycle of these commands. The command code written in the first bus cycle becomes invalid. 2. When the FMR02 bit is set to “1” (lock bit di sabled), no error occurs even under the conditions above. Table 22.6 Errors and FMR0 Register State FMR00 Register (Status Register) State Error Error Occurrence ConditionsFMR07 bit (SR5 bit) FMR06 bit (SR4 bit) Command Sequence error

• Command is written incorrectly
• A value other than “xxD0h” or “xxFFh” is written in the second bus cycle of the lock bit program, block erase or erase all unlocked block command (1) Erase error • The block erase command is executed on a locked block
• The block erase or erase all unlocked block command is executed on an unlock block and auto erase operation is not completed as expected (2) Program error • The program command is executed on locked blocks
• The program command is executed on unlocked blocks but program operation is not completed as expected
• The lock bit program command is executed but program operation is not completed as expected (2)

M16C/62P Group (M16C/62P , M16C/62PT) 22. Flash Memory Version Rev.2.41 Jan 10, 2006 Page 294 of 390 REJ09B0185-0241 Figure 22.14 Full Status Check and Handling Procedure for Each Error Full status check FMR06 =1 and FMR07=1? NO Command sequence error YES FMR07=0? YES Erase error NO (1) Execute the clear status register command and set the SR4 and SR5 bits to “0” (completed as expected) . (2) Rewrite command and execute again. (1) Execute the clear status register command and set the SR5 bit to “0”. (2) Execute the lock bit read status command. Set the FMR02 bit to “1” (lock bit disabled) if the lock bit in the block where the error occurred is set to “0” (locked). (3) Execute the block erase or erase all unlocked block command again. (4) Execute (1), (2) and (3) at least 3 times until an erase error is not generated. NOTE: If similar error occurs, that block cannot be used. If the lock bit is set to “1” (unlocked) in (2) above, that block cannot be used. FMR06=0? YES Program error NO Full status checkcompleted (1) Execute the clear status register command and set the SR4 bit to “0” (completed as expected) . (2) Execute the read lock bit status command and set the FMR02 bit to “1” if the lock bit in the block where the error occurred is set to 0. (3) Execute the program command again. NOTE: When a similar error occurs, that block cannot be used. If the lock bit is set to “1” in (2) above, that block cannot be used. [When a program operation is executed] [When a lock bit program operation is executed] NOTE: When either FMR06 or FMR07 bit is set to “1” (terminated by error) , the program, block erase, erase all unlocked block, lock bit program and read lock bit status commands cannot be accepted. Execute the clear status register command before each command. (1) Execute the clear status register command and set the SR4 bit to “0”. (2) Set the FMR02 bit in the FMR0 register to “1”. (3) Execute the block erase command to erase the block where the error occurred. (4) Execute the lock bit program command again. NOTE: If similar error occurs, that block cannot be used.

M16C/62P Group (M16C/62P , M16C/62PT) 22. Flash Memory Version Rev.2.41 Jan 10, 2006 Page 295 of 390 REJ09B0185-0241

22.4 Standard Serial I/O Mode

In standard serial I/O mode, the serial programmer supporting the M16C/62P Group (M16C/62P, M16C/62PT) can be used to rewrite the flash memory user ROM area in the microcomputer mounted on a board. For more information about the serial programmer, cont act your serial programmer manufacturer. Refer to the user's manual included with your serial programmer for instructions. Table 22.7 lists Pin Functions (Flash Memory Standard Serial I/O Mode). Figure 22.15 to Figure 22.18 show Pin Connections in Serial I/O Mode.

22.4.1 ID Code Check Function

The ID code check function determines whether the ID codes sent from the serial programmer matches those written in the flash memory. (Refer to 22.2 Functions To Prevent Flash Memory from Rewriting.)

M16C/62P Group (M16C/62P , M16C/62PT) 22. Flash Memory Version Rev.2.41 Jan 10, 2006 Page 296 of 390 REJ09B0185-0241 NOTES: 1. Available in only the 128-pin version. 2. When using the standard serial I/O mode, the inte rnal pull-up is enabled for the TXD1 (P6_7) pin while the RESET pin is “L”. 3. When using the standard serial I/O mode, the P0_0 to P0_7, P1_0 to P1_7 pins may become indeterminate while the P8_4 pin is “H” and the RESET pin is “L”. If this causes a program, apply “L” to the P8_4 pin. Table 22.7 Pin Functions (Flash Memory Standard Serial I/O Mode) Pin Name I/O Power Supply Description VCC1, VCC2, VSS Power Input − Apply the Flash Program, Erase Voltage to VCC1 pin and VCC2 to the VCC2 pin. The VCC apply condition is that VCC2 ≤ VCC1. Apply 0 V to VSS pin. CNVSS CNVSS I VCC1 Connect to VCC1 pin. RESET Reset Input I VCC1 Reset input pin. While RESET pin is “L” level, input a 20 cycle or longer clock to XIN pin. XIN Clock Input I VCC1 Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin. XOUT Clock Output O VCC1 BYTE BYTE I VCC1 Connect this pin to VCC1 or VSS. AVCC, AVSS Analog Power Supply Input Connect AVSS to VSS and AVCC to VCC1, respectively. VREF Reference Voltage Input I Enter the reference voltage for A/D from this pin. P0_0 to P0_7 Input Port P0 I VCC2 Input “H” or “L” level signal or open. P1_0 to P1_7 Input Port P1 I VCC2 Input “H” or “L” level signal or open. P2_0 to P2_7 Input Port P2 I VCC2 Input “H” or “L” level signal or open. P3_0 to P3_7 Input Port P3 I VCC2 Input “H” or “L” level signal or open. P4_0 to P4_7 Input Port P4 I VCC2 Input “H” or “L” level signal or open. P5_1 to P5_4, P5_6, P5_7 Input Port P5 I VCC2 Input “H” or “L” level signal or open. P5_0 CE Input I VCC2 Input “H” level signal. P5_5 EPM Input I VCC2 Input “L” level signal. P6_0 to P6_3 Input Port P6 I VCC1 Input “H” or “L” level signal or open. P6_4/RTS1 BUSY Output O VCC1 Standard serial I/O mode 1: BUSY signal output pin Standard serial I/O mode 2: Monitors the boot program operation check signal output pin. P6_5/CLK1 SCLK Input I VCC1 Standard serial I/O mode 1: Serial clock input pin Standard serial I/O mode 2: Input “L”. P6_6/RXD1 RXD Input I VCC1 Serial data input pin. P6_7/TXD1 TXD Input O VCC1 Serial data output pin. (2) P7_0 to P7_7 Input Port P7 I VCC1 Input “H” or “L” level signal or open. P8_0 to P8_3, P8_6, P8_7 Input Port P8 I VCC1 Input “H” or “L” level signal or open. P8_4 P8_4 input I VCC1 Input “L” level signal. (3) P8_5/NMI NMI Input I VCC1 Connect this pin to VCC1. P9_0 to P9_7 Input Port P9 I VCC1 Input “H” or “L” level signal or open. P10_0 to P10_7 Input Port P10 I VCC1 Input “H” or “L” level signal or open. P11_0 to P11_7 Input Port P11 I VCC1 Input “H” or “L” level signal or open. (1) P12_0 to P12_7 Input Port P12 I VCC2 Input “H” or “L” level signal or open. (1) P13_0 to P13_7 Input Port P13 I VCC2 Input “H” or “L” level signal or open. (1) P14_0, P14_1 Input Port P14 I VCC1 Input “H” or “L” level signal or open. (1)

M16C/62P Group (M16C/62P , M16C/62PT) 22. Flash Memory Version Rev.2.41 Jan 10, 2006 Page 297 of 390 REJ09B0185-0241 Figure 22.15 Pin Connections for Serial I/O Mode (1) 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 12 22 32 42 52 62 72 82 93 0 737475767778798081828384858687888990919293949596979899100101102 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 63104 105 106 107 108 31 32 33 34 35 36 37 66676869707172 64103 CNVSS VCC1 EPM VSS RESET VSS to VCC1 CE VCC2 Signal Value Mode setup method CE EPM VSS CNVSS RESET SCLK BUSY RXD TXD VCC2 VCC1 Connect oscillator circuit. M16C/62P Group (M16C/62P) Flash Memory Version

M16C/62P Group (M16C/62P , M16C/62PT) 22. Flash Memory Version Rev.2.41 Jan 10, 2006 Page 298 of 390 REJ09B0185-0241 Figure 22.16 Pin Connections for Serial I/O Mode (2) 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 515253545556575859606162636465666768697071727374757677787980 100 Connect oscillator circuit. CNVSS VCC1 EPM VSS RESET VSS to VCC1 CE VCC2 Signal Value Mode setup method VSS RXD TXD SCLK CNVSS CE EPM BUSY RESET VCC2 VCC1 M16C/62P Group (M16C/62P, M16C/62PT) Flash Memory Version

M16C/62P Group (M16C/62P , M16C/62PT) 22. Flash Memory Version Rev.2.41 Jan 10, 2006 Page 299 of 390 REJ09B0185-0241 Figure 22.17 Pin Connections for Serial I/O Mode (3) 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 12 22 32 42 5 51525354555657585960616263646566676869707172737475 10 0 CNVSS VCC1 EPM VSS RESET VSS to VCC1 CE VCC2 Signal Value Mode setup method CNVSS RESET VSS CE BUSY EPM SCLK RXD TXD VCC2 VCC1 Connect oscillator circuit. M16C/62P Group (M16C/62P, M16C/62PT) Flash Memory Version

M16C/62P Group (M16C/62P , M16C/62PT) 22. Flash Memory Version Rev.2.41 Jan 10, 2006 Page 300 of 390 REJ09B0185-0241 Figure 22.18 Pin Connections for Serial I/O Mode (4) 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 0 41424344454647484950515253545557585960 CNVSS VSS VCC1 TXD RXD SCLK BUSY RESET CE EPM Connect oscillator circuit. M16C/62P Group (M16C/62P, M16C/62PT) Flash Memory Version CNVSS VCC1 EPM VSS RESET VSS to VCC1 CE VCC2 Signal Value Mode setup method

M16C/62P Group (M16C/62P , M16C/62PT) 22. Flash Memory Version Rev.2.41 Jan 10, 2006 Page 301 of 390 REJ09B0185-0241

22.4.2 Example of Circuit Application in the Standard Serial I/O Mode

Figure 22.19 and Figure 22.20 show example of Circuit Application in Standard Serial I/O Mode 1 and Mode 2, respectively. Refer to the user's manual of your seri al programmer to handle pins controlled by the serial programmer. Figure 22.19 Circuit Application in Standard Serial I/O Mode 1 SCLK input BUSY output RXD input CNVSS P5_0(CE) P5_5(EPM) RESETReset input User reset signal Microcomputer NOTES: 1. Control pins and external circuitry will vary according to programmer. For more information, see the programmer manual. 2. In this example, modes are switched between single-chip mode and standard serial input/output mode by controlling the CNVSS input with a switch. 3. If in standard serial input/output mode 1 there is a possibility that the user reset signal will go low during serial input/output mode, break the connection between the user reset signal and RESET pin by using, for example, a jumper switch. TXD output P6_4/RTS1 P6_5/CLK1 P6_7/TXD1 P8_5/NMI P6_6/RXD1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC2

M16C/62P Group (M16C/62P , M16C/62PT) 22. Flash Memory Version Rev.2.41 Jan 10, 2006 Page 302 of 390 REJ09B0185-0241 Figure 22.20 Circuit Application in Standard Serial I/o Mode 2 Monitor output TXD output Microcomputer NOTES: 1. In this example, modes are switched between single-chip mode and standard serial input/output mode by controlling the CNVSS input with a switch. P6_4/RTS1 P6_5/CLK1 P6_7/TXD1 CNVSS P5_0(CE) P5_5(EPM) P8_5/NMI P6_6/RXD1RXD intput RESETReset input User reset signal VCC1 VCC1 VCC1 VCC2

M16C/62P Group (M16C/62P , M16C/62PT) 22. Flash Memory Version Rev.2.41 Jan 10, 2006 Page 303 of 390 REJ09B0185-0241

22.5 Parallel I/O Mode

In parallel I/O mode, the user RO M area and the boot ROM area can be rewritten by a parallel programmer supporting the M16C/62P Group (M16C/62P, M16C/62PT) . Contact your parallel programmer manufacturer for more information on the parallel programmer. Refer to th e user's manual included with your parallel programmer for instructions.

22.5.1 User ROM and Boot ROM Areas

An erase block operation in the boot ROM area is appl ied to only one 4 Kbyte block. The rewrite control program in standard serial I/O mode is written in the boot ROM area before shipment. Do not rewrite the boot ROM area if using the serial programmer. In parallel I/O mode, the boot ROM area is located in addresses 0FF000h to 0FFFFF h. Rewrite this address range only if rewriting the boot ROM area. (Do not access addresses other than addresses 0FF000h to 0FFFFFh.)

22.5.2 ROM Code Protect Function

The ROM code protect function prevents the flash memory from being read and rewritten in parallel I/O mode. (Refer to 22.2 Functions To Prevent Flash Memory from Rewriting.)

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 304 of 390 REJ09B0185-0241 23. Electrical Characteristics

23.1 Electrical Charac teristics (M16C/62P)

NOTES: 1. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Table 23.1 Absolute Maximum Ratings Symbol Parameter Condition Rated Value Unit VCC1, VCC2 Supply Voltage V CC1=AVCC −0.3 to 6.5 V VCC2 Supply Voltage V CC2 −0.3 to VCC1+0.1 V AVCC Analog Supply Voltage V CC1=AVCC −0.3 to 6.5 V VI Input Voltage RESET, CNVSS, BYTE, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1, VREF, XIN −0.3 to V CC1+0.3 (1) V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 −0.3 to V CC2+0.3 (1) V P7_0, P7_1 −0.3 to 6.5 V VO Output Voltage P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1, XOUT −0.3 to V CC1+0.3 (1) V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 −0.3 to VCC2+0.3 (1) V P7_0, P7_1 −0.3 to 6.5 V Pd Power Dissipation −40°C<Topr≤85°C 300 mW Topr Operating Ambient Temperature When the Microcomputer is Operating −20 to 85 / −40 to 85 °C Flash Program Erase 0 to 60 Tstg Storage Temperature −65 to 150 °C

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 305 of 390 REJ09B0185-0241 NOTES: 1. Referenced to V CC1 = VCC2 = 2.7 to 5.5V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified. 2. The Average Output Current is the mean value within 100ms. 3. The total I OL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14_0, and P14_1 must be 80mA max. The total IOL(peak) for ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12, and P13 must be 80mA max. The total IOH(peak) for ports P0, P1, and P2 must be −40mA max. The total IOH(peak) for ports P3, P4, P5, P12, and P13 must be −40mA max. The total IOH(peak) for ports P6, P7, and P8_0 to P8_4 must be −40mA max. The total IOH(peak) for ports P8_6, P8_7, P9, P10, P14_0, and P14_1 must be −40mA max. Set Average Output Current to 1/2 of peak. The total IOH(peak) for ports P8_6, P8_7, P9 , P10, P11, P14_0, and P14_1 must be −40mA max. As for 80-pin version, the total IOL(peak) for all ports and IOH(peak) must be 80mA. max. due to one VCC and one VSS. 4. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Table 23.2 Recommended Operating Conditions (1) (1) Symbol Parameter Standard UnitMin. Typ. Max. VCC1, VCC2 Supply Voltage (VCC1 ≥ VCC2) 2.7 5.0 5.5 V AVCC Analog Supply Voltage V CC1 V VSS Supply Voltage 0V AVSS Analog Supply Voltage 0 V VIH HIGH Input Voltage P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 0.8VCC2 VCC2 V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (during single-chip mode) 0.8VCC2 VCC2 V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (data input during memory expansion and microprocessor mode) 0.5VCC2 VCC2 V P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1, XIN, RESET, CNVSS, BYTE 0.8VCC1 VCC1 V P7_0, P7_1 0.8VCC1 6.5 V VIL LOW Input Voltage P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 00 . 2 V CC2 V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (during single-chip mode) 00 . 2 V CC2 V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (data input during memory expansion and microprocessor mode) 00 . 1 6 V CC2 V P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1, XIN, RESET , CNVSS, BYTE 00 . 2 V CC V IOH(peak) HIGH Peak Output Current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 −10.0 mA IOH(avg) HIGH Average Output Current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 −5.0 mA IOL(peak) LOW Peak Output Current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 10.0 mA IOL(avg) LOW Average Output Current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 5.0 mA

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 306 of 390 REJ09B0185-0241 NOTES: 1. Referenced to V CC1 = VCC2 = 2.7 to 5.5V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified. 2. Relationship between main clock os cillation frequency, and supply voltage. Table 23.3 Recommended Operating Conditions (2) (1) Symbol Parameter Standard UnitMin. Typ. Max. f(XIN) Main Clock Input Oscillation Frequency (2) VCC1=3.0V to 5.5V 01 6 M H z VCC1=2.7V to 3.0V 0 20×V CC1 −44 MHz f(XCIN) Sub-Clock Oscillation Frequency 32.768 50 kHz f(Ring) On-chip Oscillation Frequency 0.5 1 2 MHz f(PLL) PLL Clock Os cillation Frequency (2) VCC1=3.0V to 5.5V 10 24 MHz VCC1=2.7V to 3.0V 10 46.67×V CC1 −116 MHz f(BCLK) CPU Operation Clock 0 24 MHz tSU(PLL) PLL Frequency Synthesizer Stabilization Wait Time VCC1=5.5V 20 ms VCC1=3.0V 50 ms Main clock input oscillation frequency 16.0 0.0 f(XIN) operating maximum frequency [MHz] VCC1[V] (main clock: no division) 5.53.0 10.0 2.7 20 x VCC1-44MHz PLL clock oscillation frequency 24.0 0.0 f(PLL) operating maximum frequency [MHz] VCC1[V] (PLL clock oscillation) 5.5 10.0 2.7 3.0 46.67 x VCC1-116MHz

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 307 of 390 REJ09B0185-0241 NOTES: 1. Referenced to V CC1=AVCC=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified. 2. If V CC1 > VCC2, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins. 3. φAD frequency must be 12 MHz or less. And divide the fAD if VCC1 is less than 4.0V, and φAD frequency into 10 MHz or less. 4. When sample & hold is disabled, φAD frequency must be 250 kHz or more, in addition to the limitation in Note 3. When sample & hold is enabled, φAD frequency must be 1MHz or more, in addition to the limitation in Note 3. Table 23.4 A/D Conversion Characteristics (1) Symbol Parameter Measuring Condition Standard UnitMin. Typ. Max. − Resolution V REF=VCC1 10 Bits INL Integral Non-Linearity Error 10bit V REF= VCC1= AN0 to AN7 input, AN0_0 to AN0_7 input, AN2_0 to AN2_7 input, ANEX0, ANEX1 input ±3 LSB External operation amp connection mode ±7 LSB V REF= VCC1= 3.3V AN0 to AN7 input, AN0_0 to AN0_7 input, AN2_0 to AN2_7 input, ANEX0, ANEX1 input ±5 LSB External operation amp connection mode ±7 LSB 8bit V REF=VCC1=5V, 3.3V ±2 LSB − Absolute Accuracy 10bit V REF= VCC1= AN0 to AN7 input, AN0_0 to AN0_7 input, AN2_0 to AN2_7 input, ANEX0, ANEX1 input ±3 LSB External operation amp connection mode ±7 LSB VREF= VCC1 =3.3V AN0 to AN7 input, AN0_0 to AN0_7 input, AN2_0 to AN2_7 input, ANEX0, ANEX1 input ±5 LSB External operation amp connection mode ±7 LSB 8bit V REF=VCC1=5V, 3.3V ±2 LSB − Tolerance Level Impedance 3 k Ω DNL Differential Non-Linearity Error ±1 LSB − Offset Error ±3 LSB − Gain Error ±3 LSB R LADDER Ladder Resistance V REF=VCC1 10 40 k Ω tCONV 10-bit Conversion Time, Sample & Hold Available VREF=VCC1=5V, φAD=12MHz 2.75 µs tCONV 8-bit Conversion Time, Sample & Hold Available VREF=VCC1=5V, φAD=12MHz 2.33 µs tSAMP Sampling Time 0.25 µs VREF Reference Voltage 2.0 V CC1 V VIA Analog Input Voltage 0 V REF V

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 308 of 390 REJ09B0185-0241 NOTES: 1. Referenced to VCC1=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified. 2. This applies when using one D/A converter, with the D/A r egister for the unused D/A converter set to “00h”. The resistor ladder of the A/D converter is not included. Also, when D/A register contents are not “00h”, the IVREF will flow even if Vref id disconnected by the A/D control register. Table 23.5 D/A Conversion Characteristics (1) Symbol Parameter Measuring Condition Standard UnitMin. Typ. Max. − Resolution 8B i t s − Absolute Accuracy 1.0 % tSU Setup Time 3 µs RO Output Resistance 4 10 20 k Ω IVREF Reference Power Supply Input Current (NOTE 2) 1.5 mA

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 309 of 390 REJ09B0185-0241 NOTES: 2. n denotes the number of block erases. 3. Program and Erase Endurance refers to the num ber of times a block erase can be performed. If the program and erase endurance is n (n=100, 1,000, or 10,000), each block can be erased n times. For example, if a 4 Kbytes block A is erased after writing 1 word data 2,048 times, each to a different address, this counts as one program and erase endurance. Data cannot be written to the same address more than once without erasing the block. (Rewrite prohibited) 4. Maximum number of E/W cycles for which operation is guaranteed. 5. Topr = -40 to 85 °C (D3, D7, U3, U7) / -20 to 85 °C (D5, D9, U5, U9). 8. To reduce the number of program and erase endurance when wo rking with systems requiring numerous rewrites, write to unused word addresses within the block instead of rewrite. Erase block only after all possible addresses are used. For example, an 8-word program can be written 256 times maximum before erase becomes necessary. Maintaining an equal number of erasure between block A and block 1 will also improve efficiency. It is important to track the total number of times erasure is used. 9. Should erase error occur during block erase, attempt to ex ecute clear status register command, then block erase command at least three times until erase error disappears. 10. Set the PM17 bit in the PM1 register to “1” (wait state) when executing more than 100 times rewrites (D7, D9, U7 and U9). 11. Customers desiring E/W failure rate information should contact their Renesas technical support representative. Table 23.6 Flash Memory Version Electrical Characteristics (1) for 100 cycle products (D3, D5, U3, U5) Symbol Parameter Standard UnitMin. Typ. Max. − Program and Erase Endurance (3) 100 cycle − Word Program Time (VCC1=5.0V) 25 200 µs − Lock Bit Program Time 25 200 µs − Block Erase Time (VCC1=5.0V) 4-Kbyte block 0.3 4 s − 8-Kbyte block 0.3 4 s − 32-Kbyte block 0.5 4 s − 64-Kbyte block 0.8 4 s − Erase All Unlocked Blocks Time (2) 4×n s tPS Flash Memory Circuit Stabilization Wait Time 15 µs − Data Hold Time (5) 10 year Table 23.7 Flash Memory Versi on Electrical Characteristics (6) for 10,000 cycle products (D7, D9, U7, U9) (Block A and Block 1 (7)) Symbol Parameter Standard UnitMin. Typ. Max. − Program and Erase Endurance (3, 8, 9) 10,000 (4) cycle − Word Program Time (VCC1=5.0V) 25 µs − Lock Bit Program Time 25 µs − Block Erase Time (VCC1=5.0V) 4-Kbyte block 0.3 s tPS Flash Memory Circuit Stabilization Wait Time 15 µs − Data Hold Time (5) 10 year Table 23.8 Flash Memory Version Program / Erase Voltage and Read Operation Voltage Characteristics (at Topr = 0 to 60 °C(D3, D5, U3, U5), Topr = -40 to 85 °C(D7, U7) / Topr = Flash Program, Erase Voltage Flash Read Operation Voltage

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 310 of 390 REJ09B0185-0241 NOTES: 1. V det4 > Vdet3. 2. Where reset level detection voltage is less than 2.7 V, if the supply power voltage is greater than the reset level detection voltage, the microcomputer operates with f(BCLK) ≤ 10MHz. 3. V det3r > Vdet3 is not guaranteed. 4. The voltage detection circuit is desi gned to use when VCC1 is set to 5V. NOTES: 1. When V CC1 = 5V. Table 23.9 Low Voltage Detection Circuit Electrical Characteristics Symbol Parameter Measuring Condition Standard UnitMin. Typ. Max. Vdet3 Reset Level Detection Voltage (1, 2) 2.2 2.8 3.6 V Vdet4-Vdet3 Electric potential difference of Low Voltage Detection and Reset Level Detection 0.3 V Vdet3s Low Voltage Reset Retention Voltage 0.8 V Vdet3r Low Voltage Reset Release Voltage (3) 2.2 2.9 4.0 V Table 23.10 Power Supply Circuit Timing Characteristics Symbol Parameter Measuring Condition Standard UnitMin. Typ. Max. td(P-R) Time for Internal Power Supply Stabilization During Powering-On VCC1=2.7V to 5.5V 2 ms td(R-S) STOP Release Time 150 µs td(W-S) Low Power Dissipation Mode Wait Mode Release Time 150 µs td(S-R) Brown-out Detection Reset (Hardware Reset 2) Release Wait Time VCC1=Vdet3r to 5.5V 6 (1) 20 ms td(E-A) Low Voltage Detection Circuit Operation Start Time VCC1=2.7V to 5.5V 20 µs

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 311 of 390 REJ09B0185-0241 Figure 23.1 Power Supply Circuit Timing Diagram td(P-R) VCC1 CPU clock td(P-R) Time for Internal Power Supply Stabilization During Powering-On Interrupt for (a) Stop mode release or (b) Wait mode release CPU clock td(R-S) (a) (b) td(W-S) td(R-S) STOP Release Time td(W-S) Low Power Dissipation Mode Wait Mode Release Time td(S-R) Vdet3r VCC1 CPU clock td(S-R) Low Voltage Detection Reset (Hardware Reset 2) Release Wait Time VC26, VC27 td(E-A) td(E-A) Low Voltage Detection Circuit Operation Start Time Stop Operate Recommended operation voltage Low Voltage Detection Circuit

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 312 of 390 REJ09B0185-0241 VCC1=VCC2=5V NOTES: 1. Referenced to V CC1=VCC2=4.2 to 5.5V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(BCLK)=24MHz unless otherwise specified. 2. Where the product is used at V CC1 = 5 V and VCC2 = 3 V, refer to the 3 V version value for the pin specified value on VCC2 port side. 3. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Table 23.11 Electrical Characteristics (1) (1) Symbol Parameter Measuring Condition Standard UnitMin. Typ. Max. VOH HIGH Output Voltage (3) P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 I OH=−5mA VCC1−2.0 V CC1 VP0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 I OH=−5mA (2) VCC2−2.0 V CC2 VOH HIGH Output Voltage (3) P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 OH=−200µA VCC1−0.3 V CC1 VP0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 IOH=−200µA (2) VCC2−0.3 V CC2 VOH HIGH Output Voltage XOUT HIGHPOWER I OH=−1mA VCC1−2.0 V CC1 VLOWPOWER I OH=−0.5mA VCC1−2.0 V CC1 HIGH Output Voltage XCOUT HIGHPOWER With no load applied 2.5 VLOWPOWER With no load applied 1.6 VOL LOW Output Voltage (3) P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 IOL=5mA 2.0 VP0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 IOL=5mA (2) 2.0 VOL LOW Output Voltage (3) P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 IOL=200µA 0.45 VP0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 IOL=200µA (2) 0.45 VOL LOW Output Voltage XOUT HIGHPOWER I OL=1mA 2.0 VLOWPOWER I OL=0.5mA 2.0 LOW Output Voltage XCOUT HIGHPOWER With no load applied 0 VLOWPOWER With no load applied 0 VT+-VT- Hysteresis HOLD , RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT5, NMI, ADTRG, CTS0 to CTS2, CLK0 to CLK4, TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD2, SCL0 to SCL2, SDA0 to SDA2, SIN3, SIN4 0.2 1.0 V VT+-VT- Hysteresis RESET 0.2 2.5 V IIH HIGH Input Current (3) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, XIN, RESET , CNVSS, BYTE VI=5V 5.0 µA IIL LOW Input Current (3) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, XIN, RESET , CNVSS, BYTE VI=0V −5.0 µA RPULLUP Pull-Up Resistance (3) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 V I=0V 30 50 170 k Ω RfXIN Feedback Resistance XIN 1.5 M Ω RfXCIN Feedback Resistance XCIN 15 M Ω VRAM RAM Retention Voltage At stop mode 2.0 V

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 313 of 390 REJ09B0185-0241 NOTES: 1. Referenced to V CC1=VCC2=4.2 to 5.5V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(BCLK)=24MHz unless otherwise specified. 2. With one timer operated using fC32. 3. This indicates the memory in whic h the program to be executed exists. 4. I det is dissipation current when the following bit is set to “1” (detection circuit enabled). Idet4: VC27 bit in the VCR2 register Idet3: VC26 bit in the VCR2 register Table 23.12 Electrical Characteristics (2) (1) Symbol Parameter Measuring Condition Standard UnitMin. Typ. Max. ICC Power Supply Current (VCC1=VCC2=4.0V to 5.5V) In single-chip mode, the output pins are open and other pins are V SS Mask ROM f(BCLK)=24MHz No division, PLL operation 14 20 mA No division, On-chip oscillation 1m A Flash Memory f(BCLK)=24MHz, No division, PLL operation 18 27 mA No division, On-chip oscillation 1.8 mA Flash Memory Program f(BCLK)=10MHz, VCC1=5.0V 15 mA Flash Memory Erase f(BCLK)=10MHz, VCC1=5.0V 25 mA Mask ROM f(XCIN)=32kHz Low power dissipation mode, ROM (3) 25 µA Flash Memory f(BCLK)=32kHz Low power dissipation mode, RAM (3) 25 µA f(BCLK)=32kHz Low power dissipation mode, Flash Memory (3) 420 µA On-chip oscillation, Wait mode 50 µA Mask ROM Flash Memory f(BCLK)=32kHz Wait mode (2), Oscillation capability High 7.5 µA f(BCLK)=32kHz Wait mode (2), Oscillation capability Low 2.0 µA Stop mode Topr =25°C 0.8 3.0 µA Idet4 Low Voltage Detection Dissipation Current (4) 0.7 4 µA Idet3 Reset Area Detection Dissipation Current (4) 1.2 8 µA

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 314 of 390 REJ09B0185-0241 VCC1=VCC2=5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) NOTES: 1. The condition is V CC1=VCC2=3.0 to 5.0V. NOTES: 1. Calculated according to t he BCLK frequency as follows: 2. Calculated according to t he BCLK frequency as follows: n is ”2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting. 3. Calculated according to t he BCLK frequency as follows: n is “2” for 2-wait setting, “3” for 3-wait setting. Table 23.13 External Clock Input (XIN input) (1) Symbol Parameter Standard UnitMin. Max. tc External Clock Input Cycle Time 62.5 ns tw(H) External Clock Input HIGH Pulse Width 25 ns tw(L) External Clock Input LOW Pulse Width 25 ns tr External Clock Rise Time 15 ns tf External Clock Fall Time 15 ns Table 23.14 Memory Expansion Mode and Microprocessor Mode Symbol Parameter Standard UnitMin. Max. tac1(RD-DB) Data Input Access Time (for setting with no wait) (NOTE 1) ns tac2(RD-DB) Data Input Access Time (for setting with wait) (NOTE 2) ns tac3(RD-DB) Data Input Access Time (when accessing multiplex bus area) (NOTE 3) ns tsu(DB-RD) Data Input Setup Time 40 ns tsu(RDY-BCLK) RDY Input Setup Time 30 ns tsu(HOLD-BCLK) HOLD Input Setup Time 40 ns th(RD-DB) Data Input Hold Time 0 ns th(BCLK-RDY) RDY Input Hold Time 0 ns th(BCLK-HOLD) HOLD Input Hold Time 0 ns 0.5x10 9 n0 . 5–() x109 n0 . 5–() x109

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 315 of 390 REJ09B0185-0241 VCC1=VCC2=5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 23.15 Timer A Input (Counte r Input in Event Counter Mode) Symbol Parameter Standard UnitMin. Max. tc(TA) TAiIN Input Cycle Time 100 ns tw(TAH) TAiIN Input HIGH Pulse Width 40 ns tw(TAL) TAiIN Input LOW Pulse Width 40 ns Table 23.16 Timer A Input (G ating Input in Timer Mode) Symbol Parameter Standard UnitMin. Max. tc(TA) TAiIN Input Cycle Time 400 ns tw(TAH) TAiIN Input HIGH Pulse Width 200 ns tw(TAL) TAiIN Input LOW Pulse Width 200 ns Table 23.17 Timer A Input (External Trigger Input in One-shot Timer Mode) Symbol Parameter Standard UnitMin. Max. tc(TA) TAiIN Input Cycle Time 200 ns tw(TAH) TAiIN Input HIGH Pulse Width 100 ns tw(TAL) TAiIN Input LOW Pulse Width 100 ns Table 23.18 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Symbol Parameter Standard UnitMin. Max. tw(TAH) TAiIN Input HIGH Pulse Width 100 ns tw(TAL) TAiIN Input LOW Pulse Width 100 ns Table 23.19 Timer A Input (Counter Increment/Decrement Input in Event Counter Mode) Symbol Parameter Standard UnitMin. Max. tc(UP) TAiOUT Input Cycle Time 2000 ns tw(UPH) TAiOUT Input HIGH Pulse Width 1000 ns tw(UPL) TAiOUT Input LOW Pulse Width 1000 ns tsu(UP-TIN) TAiOUT Input Setup Time 400 ns th(TIN-UP) TAiOUT Input Hold Time 400 ns Table 23.20 Timer A Input (Two-phase Pulse Input in Event Counter Mode) Symbol Parameter Standard UnitMin. Max. tc(TA) TAiIN Input Cycle Time 800 ns tsu(TAIN-TAOUT) TAiOUT Input Setup Time 200 ns tsu(TAOUT-TAIN) TAiIN Input Setup Time 200 ns

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 316 of 390 REJ09B0185-0241 VCC1=VCC2=5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 23.21 Timer B Input (Counte r Input in Event Counter Mode) Symbol Parameter Standard UnitMin. Max. tc(TB) TBiIN Input Cycle Time (counted on one edge) 100 ns tw(TBH) TBiIN Input HIGH Pulse Width (counted on one edge) 40 ns tw(TBL) TBiIN Input LOW Pulse Width (counted on one edge) 40 ns tc(TB) TBiIN Input Cycle Time (counted on both edges) 200 ns tw(TBH) TBiIN Input HIGH Pulse Width (counted on both edges) 80 ns tw(TBL) TBiIN Input LOW Pulse Width (counted on both edges) 80 ns Table 23.22 Timer B Input (Pulse Period Measurement Mode) Symbol Parameter Standard UnitMin. Max. tc(TB) TBiIN Input Cycle Time 400 ns tw(TBH) TBiIN Input HIGH Pulse Width 200 ns tw(TBL) TBiIN Input LOW Pulse Width 200 ns Table 23.23 Timer B Input (Pulse Width Measurement Mode) Symbol Parameter Standard UnitMin. Max. tc(TB) TBiIN Input Cycle Time 400 ns tw(TBH) TBiIN Input HIGH Pulse Width 200 ns tw(TBL) TBiIN Input LOW Pulse Width 200 ns Table 23.24 A/D Trigger Input Symbol Parameter Standard UnitMin. Max. tc(AD) ADTRG Input Cycle Time 1000 ns tw(ADL) ADTRG input LOW Pulse Width 125 ns Table 23.25 Serial Interface Symbol Parameter Standard UnitMin. Max. tc(CK) CLKi Input Cycle Time 200 ns tw(CKH) CLKi Input HIGH Pulse Width 100 ns tw(CKL) CLKi Input LOW Pulse Width 100 ns td(C-Q) TXDi Output Delay Time 80 ns th(C-Q) TXDi Hold Time 0 ns tsu(D-C) RXDi Input Setup Time 70 ns th(C-D) RXDi Input Hold Time 90 ns Table 23.26 External Interrupt INTi Input Symbol Parameter Standard UnitMin. Max. tw(INH) INTi Input HIGH Pulse Width 250 ns tw(INL) INTi Input LOW Pulse Width 250 ns

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 318 of 390 REJ09B0185-0241 VCC1=VCC2=5V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) NOTES: 1. Calculated according to the BCLK frequency as follows: 2. Calculated according to the BCLK frequency as follows: 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = −CR X ln (1−V OL / VCC2) by a circuit of the right figure. For example, when V OL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time of output ”L” level is t = −30pF X 1kΩ X In(1−0.2VCC2 / VCC2) = 6.7ns. Table 23.28 Memory Expansion and Microprocessor Modes (for 1- to 3-wait setting and external area access) Symbol Parameter Standard UnitMin. Max. td(BCLK-AD) Address Output Delay Time See Figure 23.2 25 ns th(BCLK-AD) Address Output Hold Time (in relation to BCLK) 4 ns th(RD-AD) Address Output Hold Time (in relation to RD) 0 ns th(WR-AD) Address Output Hold Time (in relation to WR) (NOTE 2) ns td(BCLK-CS) Chip Select Output Delay Time 25 ns th(BCLK-CS) Chip Select Output Hold Time (in relation to BCLK) 4 ns td(BCLK-ALE) ALE Signal Output Delay Time 15 ns th(BCLK-ALE) ALE Signal Output Hold Time -4 ns td(BCLK-RD) RD Signal Output Delay Time 25 ns th(BCLK-RD) RD Signal Output Hold Time 0 ns td(BCLK-WR) WR Signal Output Delay Time 25 ns th(BCLK-WR) WR Signal Output Hold Time 0 ns td(BCLK-DB) Data Output Delay Time (in relation to BCLK) 40 ns th(BCLK-DB) Data Output Hold Time (in relation to BCLK) (3) 4n s td(DB-WR) Data Output Delay Time (in relation to WR) (NOTE 1) ns th(WR-DB) Data Output Hold Time (in relation to WR) (3) (NOTE 2) ns td(BCLK-HLDA) HLDA Output Delay Time 40 ns n0 . 5–() x109 0.5x10 9 DBi R C n is “1” for 1-wait setting, “2” for 2-wait setting and “3” for 3-wait setting. (BCLK) is 12.5MHz or less.

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 319 of 390 REJ09B0185-0241 VCC1=VCC2=5V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) NOTES: 1. Calculated according to the BCLK frequency as follows: 2. Calculated according to the BCLK frequency as follows: n is “2” for 2-wait setting, “3” for 3-wait setting. 3. Calculated according to the BCLK frequency as follows: 4. Calculated according to the BCLK frequency as follows: Table 23.29 Memory Expansion and Microprocessor Modes (for 2- to 3-wait setting, external area access and multiplex bus selection) Symbol Parameter Standard UnitMin. Max. td(BCLK-AD) Address Output Delay Time See Figure 23.2 25 ns th(BCLK-AD) Address Output Hold Time (in relation to BCLK) 4 ns th(RD-AD) Address Output Hold Time (in relation to RD) (NOTE 1) ns th(WR-AD) Address Output Hold Time (in relation to WR) (NOTE 1) ns td(BCLK-CS) Chip Select Output Delay Time 25 ns th(BCLK-CS) Chip Select Output Hold Time (in relation to BCLK) 4 ns th(RD-CS) Chip Select Output Hold Time (in relation to RD) (NOTE 1) ns th(WR-CS) Chip Select Output Hold Time (in relation to WR) (NOTE 1) ns td(BCLK-RD) RD Signal Output Delay Time 25 ns th(BCLK-RD) RD Signal Output Hold Time 0 ns td(BCLK-WR) WR Signal Output Delay Time 25 ns th(BCLK-WR) WR Signal Output Hold Time 0 ns td(BCLK-DB) Data Output Delay Time (in relation to BCLK) 40 ns th(BCLK-DB) Data Output Hold Time (in relation to BCLK) 4 ns td(DB-WR) Data Output Delay Time (in relation to WR) (NOTE 2) ns th(WR-DB) Data Output Hold Time (in relation to WR) (NOTE 1) ns td(BCLK-HLDA) HLDA Output Delay Time 40 ns td(BCLK-ALE) ALE Signal Output Delay Time (in relation to BCLK) 15 ns th(BCLK-ALE) ALE Signal Output Hold Time (in relation to BCLK) −4n s td(AD-ALE) ALE Signal Output Delay Time (in relation to Address) (NOTE 3) ns th(AD-ALE) ALE Signal Output Hold Time (in relation to Address) (NOTE 4) ns td(AD-RD) RD Signal Output Delay From the End of Address 0 ns td(AD-WR) WR Signal Output Delay From the End of Address 0 ns tdz(RD-AD) Address Output Floating Start Time 8 ns 0.5x10 9 n0 . 5–() x109 0.5x10 9 0.5x10 9

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 320 of 390 REJ09B0185-0241 Figure 23.3 Timing Diagram (1) TAiIN input TAiOUT input During event counter mode TBiIN input ADTRG input tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) th(TIN-UP) tsu(UP-TIN) TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) TAiOUT input (Up/down input) TAiIN input Two-phase pulse input in event counter mode tc(TA) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) TAiOUT input XIN input tw(H) tw(L)tr tf tc VCC1=VCC2=5V

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 321 of 390 REJ09B0185-0241 Figure 23.4 Timing Diagram (2) tsu(D-C) CLKi TXDi RXDi tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) INTi input td(C-Q) th(C-D) th(C-Q) VCC1=VCC2=5V

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 322 of 390 REJ09B0185-0241 Figure 23.5 Timing Diagram (3) Memory Expansion Mode, Microprocessor Mode (Effective for setting with wait) BCLK HOLD input HLDA input

• Measuring conditions :
• VCC1=VCC2=5V
• Input timing voltage : Determined with VIL=1.0V, VIH=4.0V
• Output timing voltage : Determined with VOL=2.5V, VOH=2.5V P0, P1, P2, P3, P4, P5_0 to P5_2 (1) (Common to setting with wait and setting without wait) NOTES: 1. These pins are set to high-impedance regardless of the input level of the BYTE pin, PM06 bit in PM0 register and PM11 bit in PM1 register. th(BCLK−HOLD)tsu(HOLD−BCLK) td(BCLK−HLDA)td(BCLK−HLDA) Hi−Z RDY input tsu(RDY−BCLK) th(BCLK−RDY) RD BCLK (Separate bus) (Multiplexed bus) WR, WRL, WRH RD (Separate bus) WR, WRL, WRH (Multiplexed bus) VCC1=VCC2=5V

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 323 of 390 REJ09B0185-0241 Figure 23.6 Timing Diagram (4) BCLK CSi td(BCLK-CS) 25ns.max ADi 25ns.max ALE 25ns.max -4ns.min RD 25ns.max th(BCLK-RD) 0ns.min th(BCLK-AD) 4ns.min th(BCLK-CS) 4ns.min Hi-Z DBi th(RD-DB) 0ns.min 0ns.min th(RD-AD) BHE tcyc Read timing td(BCLK-AD) td(BCLK-ALE) th(BCLK-ALE) tsu(DB-RD) td(BCLK-RD) 40ns.min tac1(RD-DB) Memory Expansion Mode, Microprocessor Mode (For setting with no wait) Measuring conditions

• VCC1=VCC2=5V
• Input timing voltage : VIL=0.8V, VIH=2.0V
• Output timing voltage : VOL=0.4V, VOH=2.4V WR, WRL, WRH 25ns.max th(BCLK-WR) 0ns.min BCLK CSi td(BCLK-CS) 25ns.max ADi td(BCLK-AD) 25ns.max ALE 25ns.max td(BCLK-ALE) th(BCLK-ALE) -4ns.min th(BCLK-AD) 4ns.min th(BCLK-CS) 4ns.min tcyc th(WR-AD) BHE td(BCLK-DB) 40ns.max 4ns.min th(BCLK-DB) td(DB-WR) (0.5 × tcyc-40)ns.min th(WR-DB) DBi Write timing td(BCLK-WR) Hi-Z (0.5 × tcyc-45)ns.max tcyc= 1 f(BCLK) (0.5 × tcyc-10)ns.min (0.5 × tcyc-10)ns.min VCC1=VCC2=5V

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 324 of 390 REJ09B0185-0241 Figure 23.7 Timing Diagram (5) BCLK CSi td(BCLK-CS) 25ns.max ADi td(BCLK-AD) 25ns.max ALE 25ns.max th(BCLK-ALE) -4ns.min RD 25ns.max th(BCLK-RD) 0ns.min th(BCLK-AD) 4ns.min th(BCLK-CS) 4ns.min Hi-Z DBi tsu(DB-RD) 40ns.min th(RD-DB) 0ns.min tcyc BHE Read timing WR, WRL, WRH 25ns.max th(BCLK-WR) 0ns.min BCLK CSi td(BCLK-CS) 25ns.max ADi td(BCLK-AD) 25ns.max ALE 25ns.max td(BCLK-ALE) th(BCLK-ALE) -4ns.min th(BCLK-AD) 4ns.min th(BCLK-CS) 4ns.min tcyc th(WR-AD) BHE td(BCLK-DB) 40ns.max 4ns.min th(BCLK-DB) td(DB-WR) (0.5 × tcyc-40)ns.min (0.5 × tcyc-10)ns.min th(WR-DB) DBi Write timing td(BCLK-ALE) td(BCLK-RD) td(BCLK-WR) 0ns.min th(RD-AD) tac2(RD-DB) Hi-Z Memory Expansion Mode, Microprocessor Mode (for 1-wait setting and external area access) Measuring conditions

• VCC1=VCC2=5V
• Input timing voltage : VIL=0.8V, VIH=2.0V
• Output timing voltage : VOL=0.4V, VOH=2.4V (1.5 × tcyc-45)ns.max tcyc= f(BCLK) (0.5 × tcyc-10)ns.min VCC1=VCC2=5V

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 325 of 390 REJ09B0185-0241 Figure 23.8 Timing Diagram (6) Read timing Write timing BCLK CSi ALE DBi ADi BHE WR, WRL WRH Memory Expansion Mode, Microprocessor Mode (for 2-wait setting and external area access) BCLK CSi ALE DBi ADi BHE RD tcyc td(BCLK-CS) 25ns.max td(BCLK-AD) 25ns.max td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min td(BCLK-RD) 25ns.max Hi-Z tsu(DB-RD) 40ns.min th(RD-DB) 0ns.min th(BCLK-RD) 0ns.min th(RD-AD) 0ns.min th(BCLK-AD) 4ns.min th(BCLK-CS) 4ns.min tcyc Hi-Z td(BCLK-CS) 25ns.max td(BCLK-AD) 25ns.max td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min td(BCLK-WR) 25ns.max th(BCLK-CS) 4ns.min th(BCLK-AD) 4ns.min th(WR-AD) (0.5×tcyc-10)ns.min th(BCLK-WR) 0ns.min td(BCLK-DB) 40ns.max td(DB-WR) (1.5×tcyc-40)ns.min th(BCLK-DB) 4ns.min th(WR-DB) (0.5×tcyc-10)ns.min Measuring conditions

• VCC1=VCC2=5V
• Input timing voltage : VIL=0.8V, VIH=2.0V
• Output timing voltage : VOL=0.4V, VOH=2.4V tac2(RD-DB) (2.5×tcyc-45)ns.max Tcyc= 1 f(BCLK) VCC1=VCC2=5V

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 326 of 390 REJ09B0185-0241 Figure 23.9 Timing Diagram (7) Read timing Write timing BCLK CSi ALE DBi ADi BHE WR, WRL WRH Memory Expansion Mode, Microprocessor Mode (for 3-wait setting and external area access) BCLK CSi ALE DBi ADi BHE RD tcyc td(BCLK-CS) 25ns.max td(BCLK-AD) 25ns.max td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min td(BCLK-RD) 25ns.max Hi-Z tsu(DB-RD) 40ns.min th(RD-DB) 0ns.min th(BCLK-RD) 0ns.min th(RD-AD) 0ns.min th(BCLK-AD) 4ns.min th(BCLK-CS) 4ns.min Hi-Z td(BCLK-CS) 25ns.max td(BCLK-AD) 25ns.max td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min td(BCLK-WR) 25ns.max th(BCLK-CS) 4ns.min th(BCLK-AD) 4ns.min th(WR-AD) (0.5×tcyc-10)ns.min th(BCLK-WR) 0ns.min td(BCLK-DB) 40ns.max td(DB-WR) (2.5×tcyc-40)ns.min th(BCLK-DB) 4ns.min th(WR-DB) (0.5×tcyc-10)ns.min Measuring conditions

• VCC1=VCC2=5V
• Input timing voltage : VIL=0.8V, VIH=2.0V
• Output timing voltage : VOL=0.4V, VOH=2.4V tac2(RD-DB) (3.5×tcyc-45)ns.max tcyc= 1 f(BCLK) tcyc VCC1=VCC2=5V

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 327 of 390 REJ09B0185-0241 Figure 23.10 Timing Diagram (8) Memory Expansion Mode, Microprocessor Mode (For 1- or 2-wait setting, external area access and multiplex bus selection) BCLK CSi td(BCLK-CS) 25ns.max ADi td(BCLK-AD) 25ns.max ALE th(BCLK-ALE) −4ns.min RD 25ns.max th(BCLK-RD) 0ns.min th(BCLK-AD) 4ns.min th(BCLK-CS) 4ns.mintcyc th(RD-CS) th(RD-AD) BHE ADi /DBi th(RD-DB) 0ns.min td(AD-ALE) Read timing td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min BCLK CSi td(BCLK-CS) 25ns.max ADi td(BCLK-AD) 25ns.max ALE 25ns.max th(BCLK-ALE) −4ns.min th(BCLK-AD) 4ns.min th(BCLK-CS) 4ns.min tcyc th(WR-AD) BHE td(BCLK-DB) 40ns.max 4ns.min th(BCLK-DB) td(DB-WR) th(WR-DB) ADi /DBi Data output WR,WRL, WRH Write timing Address (0.5×tcyc-10)ns.min AddressData input 40ns.min (0.5×tcyc-10)ns.min td(BCLK-ALE) td(BCLK-RD) (0.5×tcyc-10)ns.min th(WR-CS) Address td(AD-ALE) (0.5×tcyc-25)ns.min (1.5×tcyc-40)ns.min (0.5×tcyc-10)ns.min td(BCLK-ALE) (0.5×tcyc-25)ns.min Address 25ns.max tsu(DB-RD)tac3(RD-DB) (0.5×tcyc-10)ns.min td(AD-RD) 0ns.min tdZ(RD-AD) 8ns.max td(AD-WR) 0ns.min Measuring conditions

• VCC1=VCC2=5V
• Input timing voltage : VIL=0.8V, VIH=2.0V
• Output timing voltage : VOL=0.4V, VOH=2.4V th(ALE-AD) (1.5×tcyc-45)ns.max (0.5×tcyc-15)ns.min VCC1=VCC2=5V

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 328 of 390 REJ09B0185-0241 Figure 23.11 Timing Diagram (9) Read timing Write timing Memory Expansion Mode, Microprocessor Mode (For 3-wait setting, external area access and multiplex bus selection) BCLK CSi ALE RD ADi /DBi ADi BHE (no multiplex) BCLK CSi ALE ADi /DBi tcyc td(BCLK-AD) 25ns.max tcyc Data output th(BCLK-CS) 4ns.mintd(BCLK-CS) 25ns.max td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min tsu(DB-RD) 40ns.min th(RD-DB) 0ns.min th(RD-AD) (0.5×tcyc-10)ns.min th(BCLK-AD) 4ns.min td(BCLK-CS) 25ns.max td(BCLK-AD) 25ns.max th(BCLK-DB) 4ns.min th(BCLK-WR) 0ns.min th(WR-AD) (0.5×tcyc-10)ns.min th(BCLK-AD) 4ns.min th(BCLK-CS) 4ns.min td(BCLK-ALE) 25ns.max td(BCLK-WR) 25ns.max th(WR-DB) (0.5×tcyc-10)ns.min Data inputAddress Address ADi BHE (no multiplex) WR, WRL WRH Measuring conditions

• VCC1=VCC2=5V
• Input timing voltage : VIL=0.8V, VIH=2.0V
• Output timing voltage : VOL=0.4V, VOH=2.4V td(AD-ALE) (0.5×tcyc-25)ns.min td(AD-RD) 0ns.min tdZ(RD-AD) 8ns.max tac3(RD-DB) td(BCLK-DB) 40ns.max (0.5×tcyc-10)ns.min th(WR-CS) td(DB-WR) (2.5×tcyc-40)ns.min td(AD-WR) 0ns.min th(RD-CS) (0.5×tcyc-10)ns.min td(AD-ALE) (0.5×tcyc-25)ns.min th(ALE-AD) (2.5×tcyc-45)ns.max tcyc= 1 f(BCLK) (0.5×tcyc-15)ns.min th(BCLK-ALE) -4ns.min VCC1=VCC2=5V

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 329 of 390 REJ09B0185-0241 VCC1=VCC2=3V NOTES: 1. Referenced to V CC1 = VCC2 = 2.7 to 3.3V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(XIN)=10MHz no wait unless otherwise specified. 2. V CC1 for the port P6 to P11 and P14, and VCC2 for the port P0 to P5 and P12 to P13 3. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Table 23.30 Electrical Characteristics (1) (1) Symbol Parameter Measuring Condition Standard UnitMin. Typ. Max. VOH HIGH Output Voltage (3) P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 I OH=−1mA VCC1−0.5 V CC1 VP0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 I OH=−1mA (2) VCC2−0.5 V CC2 VOH HIGH Output Voltage XOUT HIGHPOWER I OH=−0.1mA VCC1−0.5 V CC1 VLOWPOWER I OH=−50µA VCC1−0.5 V CC1 HIGH Output Voltage XCOUT HIGHPOWER With no load applied 2.5 VLOWPOWER With no load applied 1.6 VOL LOW Output Voltage (3) P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 I OL=1mA 0.5 VP0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 IOL=1mA (2) 0.5 VOL LOW Output Voltage XOUT HIGHPOWER I OL=0.1mA 0.5 VLOWPOWER I OL=50µA 0.5 LOW Output Voltage XCOUT HIGHPOWER With no load applied 0 VLOWPOWER With no load applied 0 VT+-VT- Hysteresis HOLD , RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT5, NMI, ADTRG, CTS0 to CTS2, CLK0 to CLK4, TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD2, SCL0 to SCL2, SDA0 to SDA2, SIN3, SIN4 0.2 0.8 V VT+-VT- Hysteresis RESET 0.2 (0.7) 1.8 V IIH HIGH Input Current (3) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, XIN, RESET , CNVSS, BYTE VI=3V 4.0 µA IIL LOW Input Current (3) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, XIN, RESET , CNVSS, BYTE VI=0V −4.0 µA RPULLUP Pull-Up Resistance (3) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 V I=0V 50 100 500 k Ω RfXIN Feedback Resistance XIN 3.0 M Ω RfXCIN Feedback Resistance XCIN 25 M Ω VRAM RAM Retention Voltage At stop mode 2.0 V

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 330 of 390 REJ09B0185-0241 NOTES: 1. Referenced to V CC1=VCC2=2.7 to 3.3V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(BCLK)=10MHz unless otherwise specified. 2. With one timer operated using fC32. 3. This indicates the memory in whic h the program to be executed exists. 4. I det is dissipation current when the following bit is set to “1” (detection circuit enabled). Idet4: VC27 bit in the VCR2 register Idet3: VC26 bit in the VCR2 register Table 23.31 Electrical Characteristics (2) (1) Symbol Parameter Measuring Condition Standard UnitMin. Typ. Max. ICC Power Supply Current (VCC1=VCC2=2.7V to 3.6V) In single-chip mode, the output pins are open and other pins are V SS Mask ROM f(BCLK)=10MHz No division 81 1 m A No division, On-chip oscillation 1m A Flash Memory f(BCLK)=10MHz, No division 81 3 m A No division, On-chip oscillation 1.8 mA Flash Memory Program f(BCLK)=10MHz, VCC1=3.0V 12 mA Flash Memory Erase f(BCLK)=10MHz, VCC1=3.0V 22 mA Mask ROM f(XCIN)=32kHz Low power dissipation mode, ROM (3) 25 µA Flash Memory f(BCLK)=32kHz Low power dissipation mode, RAM (3) 25 µA f(BCLK)=32kHz Low power dissipation mode, Flash Memory (3) 420 µA On-chip oscillation, Wait mode 45 µA Mask ROM Flash Memory f(BCLK)=32kHz Wait mode (2), Oscillation capability High 6.0 µA f(BCLK)=32kHz Wait mode (2), Oscillation capability Low 1.8 µA Stop mode Topr =25°C 0.7 3.0 µA Idet4 Low Voltage Detection Dissipation Current (4) 0.6 4 µA Idet3 Reset Area Detection Dissipation Current (4) 0.4 2 µA

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 331 of 390 REJ09B0185-0241 VCC1=VCC2=3V Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) NOTES: 1. The condition is V CC1=VCC2=2.7 to 3.0V. 2. Calculated according to the V CC1 voltage as follows: [ns] 3. Calculated according to the V CC1 voltage as follows: [ns] 4. Calculated according to the V CC1 voltage as follows: [ns] NOTES: 1. Calculated according to t he BCLK frequency as follows: 2. Calculated according to t he BCLK frequency as follows: n is ”2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting. 3. Calculated according to t he BCLK frequency as follows: n is “2” for 2-wait setting, “3” for 3-wait setting. Table 23.32 External Clock Input (XIN input) (1) Symbol Parameter Standard UnitMin. Max. tc External Clock Input Cycle Time (NOTE 2) ns tw(H) External Clock Input HIGH Pulse Width (NOTE 3) ns tw(L) External Clock Input LOW Pulse Width (NOTE 3) ns tr External Clock Rise Time (NOTE 4) ns tf External Clock Fall Time (NOTE 4) ns Table 23.33 Memory Expansion Mode and Microprocessor Mode Symbol Parameter Standard UnitMin. Max. tac1(RD-DB) Data Input Access Time (for setting with no wait) (NOTE 1) ns tac2(RD-DB) Data Input Access Time (for setting with wait) (NOTE 2) ns tac3(RD-DB) Data Input Access Time (when accessing multiplex bus area) (NOTE 3) ns tsu(DB-RD) Data Input Setup Time 50 ns tsu(RDY-BCLK) RDY Input Setup Time 40 ns tsu(HOLD-BCLK) HOLD Input Setup Time 50 ns th(RD-DB) Data Input Hold Time 0 ns th(BCLK-RDY) RDY Input Hold Time 0 ns th(BCLK-HOLD) HOLD Input Hold Time 0 ns 10 6– 10 6– 10– VCC1 45+× 0.5x10 9 n0 . 5–() x109 n0 . 5–() x109

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 332 of 390 REJ09B0185-0241 VCC1=VCC2=3V Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 23.34 Timer A Input (Counte r Input in Event Counter Mode) Symbol Parameter Standard UnitMin. Max. tc(TA) TAiIN Input Cycle Time 150 ns tw(TAH) TAiIN Input HIGH Pulse Width 60 ns tw(TAL) TAiIN Input LOW Pulse Width 60 ns Table 23.35 Timer A Input (G ating Input in Timer Mode) Symbol Parameter Standard UnitMin. Max. tc(TA) TAiIN Input Cycle Time 600 ns tw(TAH) TAiIN Input HIGH Pulse Width 300 ns tw(TAL) TAiIN Input LOW Pulse Width 300 ns Table 23.36 Timer A Input (External Trigger Input in One-shot Timer Mode) Symbol Parameter Standard UnitMin. Max. tc(TA) TAiIN Input Cycle Time 300 ns tw(TAH) TAiIN Input HIGH Pulse Width 150 ns tw(TAL) TAiIN Input LOW Pulse Width 150 ns Table 23.37 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Symbol Parameter Standard UnitMin. Max. tw(TAH) TAiIN Input HIGH Pulse Width 150 ns tw(TAL) TAiIN Input LOW Pulse Width 150 ns Table 23.38 Timer A Input (Counter Increment/Decrement Input in Event Counter Mode) Symbol Parameter Standard UnitMin. Max. tc(UP) TAiOUT Input Cycle Time 3000 ns tw(UPH) TAiOUT Input HIGH Pulse Width 1500 ns tw(UPL) TAiOUT Input LOW Pulse Width 1500 ns tsu(UP-TIN) TAiOUT Input Setup Time 600 ns th(TIN-UP) TAiOUT Input Hold Time 600 ns Table 23.39 Timer A Input (Two-phase Pulse Input in Event Counter Mode) Symbol Parameter Standard UnitMin. Max. tc(TA) TAiIN Input Cycle Time 2 µs tsu(TAIN-TAOUT) TAiOUT Input Setup Time 500 ns tsu(TAOUT-TAIN) TAiIN Input Setup Time 500 ns

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 333 of 390 REJ09B0185-0241 VCC1=VCC2=3V Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 23.40 Timer B Input (Counte r Input in Event Counter Mode) Symbol Parameter Standard UnitMin. Max. tc(TB) TBiIN Input Cycle Time (counted on one edge) 150 ns tw(TBH) TBiIN Input HIGH Pulse Width (counted on one edge) 60 ns tw(TBL) TBiIN Input LOW Pulse Width (counted on one edge) 60 ns tc(TB) TBiIN Input Cycle Time (counted on both edges) 300 ns tw(TBH) TBiIN Input HIGH Pulse Width (counted on both edges) 120 ns tw(TBL) TBiIN Input LOW Pulse Width (counted on both edges) 120 ns Table 23.41 Timer B Input (Pulse Period Measurement Mode) Symbol Parameter Standard UnitMin. Max. tc(TB) TBiIN Input Cycle Time 600 ns tw(TBH) TBiIN Input HIGH Pulse Width 300 ns tw(TBL) TBiIN Input LOW Pulse Width 300 ns Table 23.42 Timer B Input (Pulse Width Measurement Mode) Symbol Parameter Standard UnitMin. Max. tc(TB) TBiIN Input Cycle Time 600 ns tw(TBH) TBiIN Input HIGH Pulse Width 300 ns tw(TBL) TBiIN Input LOW Pulse Width 300 ns Table 23.43 A/D Trigger Input Symbol Parameter Standard UnitMin. Max. tc(AD) ADTRG Input Cycle Time 1500 ns tw(ADL) ADTRG Input LOW Pulse Width 200 ns Table 23.44 Serial Interface Symbol Parameter Standard UnitMin. Max. tc(CK) CLKi Input Cycle Time 300 ns tw(CKH) CLKi Input HIGH Pulse Width 150 ns tw(CKL) CLKi Input LOW Pulse Width 150 ns td(C-Q) TXDi Output Delay Time 160 ns th(C-Q) TXDi Hold Time 0 ns tsu(D-C) RXDi Input Setup Time 100 ns th(C-D) RXDi Input Hold Time 90 ns Table 23.45 External Interrupt INTi Input Symbol Parameter Standard UnitMin. Max. tw(INH) INTi Input HIGH Pulse Width 380 ns tw(INL) INTi Input LOW Pulse Width 380 ns

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 335 of 390 REJ09B0185-0241 VCC1=VCC2=3V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) NOTES: 1. Calculated according to the BCLK frequency as follows: 2. Calculated according to the BCLK frequency as follows: 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = −CR X ln (1−V OL / VCC2) by a circuit of the right figure. For example, when V OL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time of output ”L” level is t = −30pF X 1kΩ X In(1−0.2VCC2 / VCC2) = 6.7ns. Table 23.47 Memory Expansion and Microprocessor Modes (for 1- to 3-wait setting and external area access) Symbol Parameter Standard UnitMin. Max. td(BCLK-AD) Address Output Delay Time See Figure 23.12 30 ns th(BCLK-AD) Address Output Hold Time (in relation to BCLK) 4 ns th(RD-AD) Address Output Hold Time (in relation to RD) 0 ns th(WR-AD) Address Output Hold Time (in relation to WR) (NOTE 2) ns td(BCLK-CS) Chip Select Output Delay Time 30 ns th(BCLK-CS) Chip Select Output Hold Time (in relation to BCLK) 4 ns td(BCLK-ALE) ALE Signal Output Delay Time 25 ns th(BCLK-ALE) ALE Signal Output Hold Time -4 ns td(BCLK-RD) RD Signal Output Delay Time 30 ns th(BCLK-RD) RD Signal Output Hold Time 0 ns td(BCLK-WR) WR Signal Output Delay Time 30 ns th(BCLK-WR) WR Signal Output Hold Time 0 ns td(BCLK-DB) Data Output Delay Time (in relation to BCLK) 40 ns th(BCLK-DB) Data Output Hold Time (in relation to BCLK) (3) 4n s td(DB-WR) Data Output Delay Time (in relation to WR) (NOTE 1) ns th(WR-DB) Data Output Hold Time (in relation to WR) (3) (NOTE 2) ns td(BCLK-HLDA) HLDA Output Delay Time 40 ns n0 . 5–() x109 0.5x10 9 DBi R C n is “1” for 1-wait setting, “2” for 2-wait setting and “3” for 3-wait setting. (BCLK) is 12.5MHz or less.

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 336 of 390 REJ09B0185-0241 VCC1=VCC2=3V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) NOTES: 1. Calculated according to the BCLK frequency as follows: 2. Calculated according to the BCLK frequency as follows: n is “2” for 2-wait setting, “3” for 3-wait setting. 3. Calculated according to the BCLK frequency as follows: 4. Calculated according to the BCLK frequency as follows: Table 23.48 Memory Expansion and Microprocessor Modes (for 2- to 3-wait setting, external area access and multiplex bus selection) Symbol Parameter Standard UnitMin. Max. td(BCLK-AD) Address Output Delay Time See Figure 23.12 50 ns th(BCLK-AD) Address Output Hold Time (in relation to BCLK) 4 ns th(RD-AD) Address Output Hold Time (in relation to RD) (NOTE 1) ns th(WR-AD) Address Output Hold Time (in relation to WR) (NOTE 1) ns td(BCLK-CS) Chip Select Output Delay Time 50 ns th(BCLK-CS) Chip Select Output Hold Time (in relation to BCLK) 4 ns th(RD-CS) Chip Select Output Hold Time (in relation to RD) (NOTE 1) ns th(WR-CS) Chip Select Output Hold Time (in relation to WR) (NOTE 1) ns td(BCLK-RD) RD Signal Output Delay Time 40 ns th(BCLK-RD) RD Signal Output Hold Time 0 ns td(BCLK-WR) WR Signal Output Delay Time 40 ns th(BCLK-WR) WR Signal Output Hold Time 0 ns td(BCLK-DB) Data Output Delay Time (in relation to BCLK) 50 ns th(BCLK-DB) Data Output Hold Time (in relation to BCLK) 4 ns td(DB-WR) Data Output Delay Time (in relation to WR) (NOTE 2) ns th(WR-DB) Data Output Hold Time (in relation to WR) (NOTE 1) ns td(BCLK-HLDA) HLDA Output Delay Time 40 ns td(BCLK-ALE) ALE Signal Output Delay Time (in relation to BCLK) 25 ns th(BCLK-ALE) ALE Signal Output Hold Time (in relation to BCLK) −4n s td(AD-ALE) ALE Signal Output Delay Time (in relation to Address) (NOTE 3) ns th(AD-ALE) ALE Signal Output Hold Time (in relation to Address) (NOTE 4) ns td(AD-RD) RD Signal Output Delay From the End of Address 0 ns td(AD-WR) WR Signal Output Delay From the End of Address 0 ns tdz(RD-AD) Address Output Floating Start Time 8 ns 0.5x10 9 0.5x10 9 0.5x10 9 0.5x10 9

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 337 of 390 REJ09B0185-0241 Figure 23.13 Timing Diagram (1) TAiIN input TAiOUT input During Event Counter Mode TBiIN input ADTRG input tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) th(TIN-UP) tsu(UP-TIN) TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) TAiOUT input (Up/down input) TAiIN input Two-Phase Pulse Input in Event Counter Mode tc(TA) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) TAiOUT input XIN input tw(H) tw(L)tr tf tc VCC1=VCC2=3V

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 338 of 390 REJ09B0185-0241 Figure 23.14 Timing Diagram (2) tsu(D-C) CLKi TXDi RXDi tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) INTi input td(C-Q) th(C-D) th(C-Q) VCC1=VCC2=3V

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 339 of 390 REJ09B0185-0241 Figure 23.15 Timing Diagram (3) Memory Expansion Mode, Microprocessor Mode (Effective for setting with wait) BCLK HOLD input HLDA output Measuring conditions :

• VCC1=VCC2=3V
• Input timing voltage : Determined with VIL=0.6V, VIH=2.4V
• Output timing voltage : Determined with VOL=1.5V, VOH=1.5V P0, P1, P2, P3, P4, P5_0 to P5_2 (1) (Common to setting with wait and setting without wait) NOTES: 1. These pins are set to high-impedance regardless of the input level of the BYTE pin, PM06 bit in PM0 register and PM11 bit in PM1 register. th(BCLK−HOLD)tsu(HOLD−BCLK) td(BCLK−HLDA)td(BCLK−HLDA) Hi−Z RDY input tsu(RDY−BCLK) th(BCLK−RDY) RD BCLK (Separate bus) (Multiplexed bus) WR, WRL, WRH RD (Separate bus) WR, WRL, WRH (Multiplexed bus) VCC1=VCC2=3V

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 340 of 390 REJ09B0185-0241 Figure 23.16 Timing Diagram (4) BCLK CSi td(BCLK-CS) 30ns.max ADi 30ns.max ALE 30ns.max -4ns.min RD 30ns.max th(BCLK-RD) 0ns.min th(BCLK-AD) 4ns.min th(BCLK-CS) 4ns.min Hi-Z DBi th(RD-DB) 0ns.min 0ns.min th(RD-AD) BHE tcyc Read timing td(BCLK-AD) td(BCLK-ALE) th(BCLK-ALE) tsu(DB-RD) td(BCLK-RD) 50ns.min tac1(RD-DB) Memory Expansion Mode, Microprocessor Mode (for setting with no wait) Measuring conditions

• VCC1=VCC2=3V
• Input timing voltage : VIL=0.6V, VIH=2.4V
• Output timing voltage : VOL=1.5V, VOH=1.5V WR, WRL, WRH 30ns.max th(BCLK-WR) 0ns.min BCLK CSi td(BCLK-CS) 30ns.max ADi td(BCLK-AD) 30ns.max ALE 30ns.max td(BCLK-ALE) th(BCLK-ALE) -4ns.min th(BCLK-AD) 4ns.min th(BCLK-CS) 4ns.min tcyc th(WR-AD) BHE td(BCLK-DB) 40ns.max 4ns.min th(BCLK-DB) td(DB-WR) (0.5 × tcyc-40)ns.min th(WR-DB) DBi Write timing td(BCLK-WR) Hi-Z (0.5 × tcyc-60)ns.max tcyc= f(BCLK) (0.5 × tcyc-10)ns.min (0.5 × tcyc-10)ns.min VCC1=VCC2=3V

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 341 of 390 REJ09B0185-0241 Figure 23.17 Timing Diagram (5) BCLK CSi td(BCLK−CS) 30ns.max ADi td(BCLK−AD) 30ns.max ALE 30ns.max th(BCLK−ALE) −4ns.min RD 30ns.max th(BCLK−RD) 0ns.min th(BCLK−AD) 4ns.min th(BCLK−CS) 4ns.min Hi−Z DBi tsu(DB−RD) 50ns.min th(RD−DB) 0ns.min tcyc BHE Read timing WR,WRL, WRH 30ns.max th(BCLK−WR) 0ns.min BCLK CSi td(BCLK−CS) 30ns.max ADi td(BCLK−AD) 30ns.max ALE 30ns.max td(BCLK−ALE) th(BCLK−ALE) −4ns.min th(BCLK−AD) 4ns.min th(BCLK−CS) 4ns.min tcyc th(WR−AD) BHE td(BCLK−DB) 40ns.max 4ns.min th(BCLK−DB) td(DB−WR) (0.5 × tcyc−40)ns.min (0.5 × tcyc−10)ns.min th(WR−DB) DBi Write timing td(BCLK−ALE) td(BCLK−RD) (0.5 × tcyc−10)ns.min td(BCLK−WR) 0ns.min th(RD−AD) tac2(RD−DB) Hi−Z Memory Expansion Mode, Microprocessor Mode (for 1-wait setting and external area access) (1.5 × tcyc−60)ns.max tcyc= 1 f(BCLK) VCC1=VCC2=3V Measuring conditions

• VCC1=VCC2=3V
• Input timing voltage : VIL=0.6V, VIH=2.4V
• Output timing voltage : VOL=1.5V, VOH=1.5V

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 342 of 390 REJ09B0185-0241 Figure 23.18 Timing Diagram (6) Read timing Write timing BCLK CSi ALE DBi ADi BHE WR, WRL WRH Memory Expansion Mode, Microprocessor Mode (for 2-wait setting and external area access) BCLK CSi ALE DBi ADi BHE RD tcyc td(BCLK-CS) 30ns.max td(BCLK-AD) 30ns.max td(BCLK-ALE) 30ns.max th(BCLK-ALE) -4ns.min td(BCLK-RD) 30ns.max Hi-Z tsu(DB-RD) 50ns.min th(RD-DB) 0ns.min th(BCLK-RD) 0ns.min th(RD-AD) 0ns.min th(BCLK-AD) 4ns.min th(BCLK-CS) 4ns.min tcyc Hi-Z td(BCLK-CS) 30ns.max td(BCLK-AD) 30ns.max td(BCLK-ALE) 30ns.max th(BCLK-ALE) -4ns.min td(BCLK-WR) 30ns.max th(BCLK-CS) 4ns.min th(BCLK-AD) 4ns.min th(WR-AD) (0.5 × tcyc-10)ns.min th(BCLK-WR) 0ns.min td(BCLK-DB) 40ns.max td(DB-WR) (1.5 × tcyc-40)ns.min th(BCLK-DB) 4ns.min th(WR-DB) (0.5 × tcyc-10)ns.min tac2(RD-DB) (2.5 × tcyc-60)ns.max tcyc= 1 f(BCLK) VCC1=VCC2=3V Measuring conditions

• VCC1=VCC2=3V
• Input timing voltage : VIL=0.6V, VIH=2.4V
• Output timing voltage : VOL=1.5V, VOH=1.5V

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 343 of 390 REJ09B0185-0241 Figure 23.19 Timing Diagram (7) Read timing Write timing BCLK CSi ALE DBi ADi BHE WR, WRL WRH Memory Expansion Mode, Microprocessor Mode (for 3-wait setting and external area access) BCLK CSi ALE DBi ADi BHE RD tcyc td(BCLK-CS) 30ns.max td(BCLK-AD) 30ns.max td(BCLK-ALE) 30ns.max th(BCLK-ALE) -4ns.min td(BCLK-RD) 30ns.max Hi-Z tsu(DB-RD) 50ns.min th(RD-DB) 0ns.min th(BCLK-RD) 0ns.min th(RD-AD) 0ns.min th(BCLK-AD) 4ns.min th(BCLK-CS) 4ns.min tcyc Hi-Z td(BCLK-CS) 30ns.max td(BCLK-AD) 30ns.max td(BCLK-ALE) 30ns.max th(BCLK-ALE) -4ns.min td(BCLK-WR) 30ns.max th(BCLK-CS) 4ns.min th(BCLK-AD) 4ns.min th(WR-AD) (0.5 × tcyc-10)ns.min th(BCLK-WR) 0ns.min td(BCLK-DB) 40ns.max td(DB-WR) (2.5 × tcyc-40)ns.min th(BCLK-DB) 4ns.min th(WR-DB) (0.5 × tcyc-10)ns.min tac2(RD-DB) (3.5 × tcyc-60)ns.max tcyc= 1 f(BCLK) VCC1 = VCC2 = 3V Measuring conditions

• VCC1=VCC2=3V
• Input timing voltage : VIL=0.6V, VIH=2.4V
• Output timing voltage : VOL=1.5V, VOH=1.5V

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 344 of 390 REJ09B0185-0241 Figure 23.20 Timing Diagram (8) Memory Expansion Mode, Microprocessor Mode (For 2-wait setting, external area access and multiplex bus selection) BCLK CSi td(BCLK-CS) 40ns.max ADi td(BCLK-AD) 40ns.max ALE th(BCLK-ALE) -4ns.min RD 40ns.max th(BCLK-RD) 0ns.min th(BCLK-AD) 4ns.min th(BCLK-CS) 4ns.mintcyc th(RD-CS) th(RD-AD) BHE ADi /DBi th(RD-DB) 0ns.min td(AD-ALE) Read timing td(BCLK-WR) 40ns.max th(BCLK-WR) 0ns.min BCLK CSi td(BCLK-CS) 40ns.max ADi td(BCLK-AD) 40ns.max ALE 40ns.max th(BCLK-ALE) -4ns.min th(BCLK-AD) 4ns.min th(BCLK-CS) 4ns.min tcyc th(WR-AD) BHE td(BCLK-DB) 50ns.max 4ns.min th(BCLK-DB) td(DB-WR) th(WR-DB) ADi /DBi Data output WR,WRL, WRH Write timing Address (0.5×tcyc-10)ns.min AddressData input 50ns.min (0.5×tcyc-10)ns.min td(BCLK-ALE) td(BCLK-RD) (0.5×tcyc-10)ns.min th(WR-CS) Address td(AD-ALE) (0.5×tcyc-40)ns.min (1.5×tcyc-50)ns.min (0.5×tcyc-10)ns.min td(BCLK-ALE) (0.5×tcyc-40)ns.min Address 40ns.max tsu(DB-RD)tac3(RD-DB) (0.5×tcyc-10)ns.min th(ALE-AD) td(AD-RD) 0ns.min tdZ(RD-AD) 8ns.max td(AD-WR) 0ns.min (1.5×tcyc-60)ns.max tcyc= 1 f(BCLK) (0.5×tcyc-15)ns.min VCC1=VCC2=3V Measuring conditions

• VCC1=VCC2=3V
• Input timing voltage : VIL=0.6V, VIH=2.4V
• Output timing voltage : VOL=1.5V, VOH=1.5V

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 345 of 390 REJ09B0185-0241 Figure 23.21 Timing Diagram (9) Read timing Write timing Memory Expansion Mode, Microprocessor Mode (For 3-wait setting, external area access and multiplex bus selection) BCLK CSi ALE RD ADi /DBi ADi BHE (No multiplex) BCLK CSi ALE ADi /DBi tcyc td(BCLK-AD) 40ns.max tcyc Data output th(BCLK-CS) 6ns.mintd(BCLK-CS) 40ns.max td(BCLK-ALE) 40ns.max th(BCLK-ALE) -4ns.min td(BCLK-RD) 40ns.max th(BCLK-RD) 0ns.min tsu(DB-RD) 50ns.min th(RD-DB) 0ns.min th(RD-AD) (0.5×tcyc-10)ns.min th(BCLK-AD) 4ns.min td(BCLK-CS) 40ns.max td(BCLK-AD) 40ns.max th(BCLK-DB) 4ns.min th(BCLK-WR) 0ns.min th(WR-AD) (0.5×tcyc-10)ns.min th(BCLK-AD) 4ns.min th(BCLK-CS) 4ns.min td(BCLK-ALE) 40ns.max td(BCLK-WR) 40ns.max th(WR-DB) (0.5×tcyc-10)ns.min Data inputAddress Address ADi BHE (No multiplex) WR, WRL WRH th(ALE-AD) td(AD-ALE) (0.5×tcyc-40)ns.min td(AD-RD) 0ns.min tdZ(RD-AD) 8ns.max tac3(RD-DB) td(BCLK-DB) 50ns.max (0.5×tcyc-10)ns.min th(WR-CS) td(DB-WR) (2.5×tcyc-50)ns.min td(AD-WR) 0ns.min th(RD-CS) (0.5×tcyc-10)ns.min td(AD-ALE) (0.5×tcyc-40)ns.min (2.5×tcyc-60)ns.max tcyc= 1 f(BCLK) th(BCLK-ALE) -4ns.min (0.5×tcyc-15)ns.min VCC1=VCC2=3V Measuring conditions

• VCC1=VCC2=3V
• Input timing voltage : VIL=0.6V, VIH=2.4V
• Output timing voltage : VOL=1.5V, VOH=1.5V

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 346 of 390 REJ09B0185-0241

23.2 Electrical Charac teristics (M16C/62PT)

NOTES: 1. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. 2. T version = −40 to 85 °C, V version= −40 to 125 °C. Table 23.49 Absolute Maximum Ratings Symbol Parameter Condition Rated Value Unit VCC1, VCC2 Supply Voltage V CC1=VCC2=AVCC −0.3 to 6.5 V AVCC Analog Supply Voltage V CC1=VCC2=AVCC −0.3 to 6.5 V VI Input Voltage RESET, CNVSS, BYTE, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1, VREF, XIN −0.3 to V CC1+0.3 (1) V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 −0.3 to V CC2+0.3 (1) V P7_0, P7_1 −0.3 to 6.5 V VO Output Voltage P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1, XOUT −0.3 to VCC1+0.3 (1) V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 −0.3 to VCC2+0.3 (1) V P7_0, P7_1 −0.3 to 6.5 V Pd Power Dissipation −40°C<Topr≤85°C 300 mW85°C<Topr≤125°C 200 Topr Operating Ambient Temperature When the Microcomputer is Operating −40 to 85 / −40 to 125 (2) °C Flash Program Erase 0 to 60 Tstg Storage Temperature −65 to 150 °C

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 347 of 390 REJ09B0185-0241 NOTES: 1. Referenced to V CC1 = VCC2 = 4.7 to 5.5V at Topr = −40 to 85°C / −40 to 125°C unless otherwise specified. T version = −40 to 85 °C, V version= −40 to 125 °C. 2. The Average Output Current is the mean value within 100ms. 3. The total I OL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, P10 P1, P14_0 and P14_1 must be 80mA max. The total IOL(peak) for ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12, and P13 must be 80mA max. The total IOH(peak) for ports P0, P1, and P2 must be −40mA max. The total IOH(peak) for ports P3, P4, P5, P12, and P13 must be −40mA max. The total IOH(peak) for ports P6, P7, and P8_0 to P8_4 must be −40mA max. The total IOH(peak) for ports P8_6, P8_7, P9 , P10, P11, P14_0, and P14_1 must be −40mA max. As for 80-pin version, the total IOL(peak) for all ports and IOH(peak) must be 80mA. max. due to one VCC and one VSS. 4. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Table 23.50 Recommended Operating Conditions (1) (1) Symbol Parameter Standard UnitMin. Typ. Max. VCC1, VCC2 Supply Voltage (VCC1 = VCC2) 4.0 5.0 5.5 V AVCC Analog Supply Voltage V CC1 V VSS Supply Voltage 0V AVSS Analog Supply Voltage 0 V VIH HIGH Input Voltage (4) P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 0.8VCC2 VCC2 V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (during single-chip mode) 0.8VCC2 VCC2 V P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1, XIN, RESET , CNVSS, BYTE 0.8VCC1 VCC1 V P7_0, P7_1 0.8VCC1 6.5 V VIL LOW Input Voltage (4) P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 00 . 2 V CC2 V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (during single-chip mode) 00 . 2 V CC2 V P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1, XIN, RESET, CNVSS, BYTE 00 . 2 V CC V IOH(peak) HIGH Peak Output Current (4) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 −10.0 mA IOH(avg) HIGH Average Output Current (4) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 −5.0 mA IOL(peak) LOW Peak Output Current (4) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 10.0 mA IOL(avg) LOW Average Output Current (4) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 5.0 mA f(XIN) Main Clock Input Oscillation Frequency VCC1=4.0V to 5.5V 01 6 M H z f(XCIN) Sub-Clock Oscillation Frequency 32.768 50 kHz f(Ring) On-chip Oscillation Frequency 0.5 1 2 MHz f(PLL) PLL Clock Os cillation Frequency VCC1=4.0V to 5.5V 10 24 MHz f(BCLK) CPU Operation Clock 0 24 MHz t SU(PLL) PLL Frequency Synthesizer Stabilization Wait Time VCC1=5.5V 20 ms

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 348 of 390 REJ09B0185-0241 NOTES: 1. Referenced to V CC1=AVCC=VREF=4.0 to 5.5V, VSS=AVSS=0V at Topr = −40 to 85°C / −40 to 125°C unless otherwise specified. T version = −40 to 85°C, V version =−40 to 125°C 2. φAD frequency must be 12 MHz or less. 3. When sample & hold is disabled, φAD frequency must be 250 kHz or more, in addition to the limitation in Note 2. When sample & hold is enabled, φAD frequency must be 1MHz or more, in addition to the limitation in Note 2. NOTES: 1. Referenced to V CC1=VREF=4.0 to 5.5V, VSS=AVSS=0V at Topr = −40 to 85°C / −40 to 125°C unless otherwise specified. T version = −40 to 85°C, V version =−40 to 125°C 2. This applies when using one D/A converter, with the D/A r egister for the unused D/A converter set to “00h”. The resistor ladder of the A/D converter is not included. Also, when D/A register contents are not “00h”, the IVREF will flow even if Vref id disconnected by the A/D control register. Table 23.51 A/D Conversion Characteristics (1) Symbol Parameter Measuring Condition Standard UnitMin. Typ. Max. − Resolution V REF=VCC1 10 Bits INL Integral Non-Linearity Error 10bit V REF= VCC1= AN0 to AN7 input, AN0_0 to AN0_7 input, AN2_0 to AN2_7 input, ANEX0, ANEX1 input ±3 LSB External operation amp connection mode ±7 LSB 8bit V REF=VCC1=5V ±2 LSB − Absolute Accuracy 10bit V REF= VCC1= AN0 to AN7 input, AN0_0 to AN0_7 input, AN2_0 to AN2_7 input, ANEX0, ANEX1 input ±3 LSB External operation amp connection mode ±7 LSB 8bit V REF=VCC1=5V ±2 LSB − Tolerance Level Impedance 3 k Ω DNL Differential Non-Linearity Error ±1 LSB − Offset Error ±3 LSB − Gain Error ±3 LSB R LADDER Ladder Resistance V REF=VCC1 10 40 k Ω tCONV 10-bit Conversion Time, Sample & Hold Function Available VREF=VCC1=5V, φAD=12MHz 2.75 µs tCONV 8-bit Conversion Time, Sample & Hold Function Available VREF=VCC1=5V, φAD=12MHz 2.33 µs tSAMP Sampling Time 0.25 µs VREF Reference Voltage 2.0 V CC1 V VIA Analog Input Voltage 0 V REF V Table 23.52 D/A Conversion Characteristics (1) Symbol Parameter Measuring Condition Standard UnitMin. Typ. Max. − Resolution 8B i t s − Absolute Accuracy 1.0 % tSU Setup Time 3 µs RO Output Resistance 4 10 20 k Ω IVREF Reference Power Supply Input Current (NOTE 2) 1.5 mA

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 349 of 390 REJ09B0185-0241 NOTES: 1. Referenced to V CC1=4.5 to 5.5V at Topr = 0 to 60 °C unless otherwise specified. 2. n denotes the number of block erases. 3. Program and Erase Endurance refers to the num ber of times a block erase can be performed. If the program and erase endurance is n (n=100, 1,000, or 10,000), each block can be erased n times. For example, if a 4 Kbytes block A is erased after writing 1 word data 2,048 times, each to a different address, this counts as one program and erase endurance. Data cannot be written to the same address more than once without erasing the block. (Rewrite prohibited) 4. Maximum number of E/W cycles for which operation is guaranteed. 5. Ta (ambient temperature)=55 °C. As to the data hold time except Ta=55 °C, please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor. 6. Referenced to V CC1 = 4.5 to 5.5V at Topr = −40 to 85 °C (B7, U7 (T version)) / −40 to 125 °C (B7, U7 (V version)) unless otherwise specified. 8. To reduce the number of program and erase endurance when wo rking with systems requiring numerous rewrites, write to unused word addresses within the block instead of rewrite. Erase block only after all possible addresses are used. For example, an 8-word program can be written 256 times maximum before erase becomes necessary. Maintaining an equal number of erasure between block A and block 1 will also improve efficiency. It is important to track the total number of times erasure is used. 9. Should erase error occur during block erase, attempt to ex ecute clear status register command, then block erase command at least three times until erase error disappears. 10. Set the PM17 bit in the PM1 register to “1” (wait state) when executing more than 100 times rewrites (B7 and U7). 11. Customers desiring E/W failure rate information should contact their Renesas technical support representative. Table 23.53 Flash Memory Version Electrical Characteristics (1) for 100 cycle products (B, U) Symbol Parameter Standard UnitMin. Typ. Max. − Program and Erase Endurance (3) 100 cycle − Word Program Time (VCC1=5.0V) 25 200 µs − Lock Bit Program Time 25 200 µs − Block Erase Time (VCC1=5.0V) 4-Kbyte block 4 0.3 4 s − 8-Kbyte block 0.3 4 s − 32-Kbyte block 0.5 4 s − 64-Kbyte block 0.8 4 s − Erase All Unlocked Blocks Time (2) 4×n s tPS Flash Memory Circuit Stabilization Wait Time 15 µs − Data Hold Time (5) 20 year Table 23.54 Flash Memory Version Electrical Characteristics (6) for 10,000 cycle products (B7, U7) (Block A and Block 1 (7)) Symbol Parameter Standard UnitMin. Typ. Max. − Program and Erase Endurance (3, 8, 9) 10,000 (4) cycle − Word Program Time (VCC1=5.0V) 25 µs − Lock Bit Program Time 25 µs − Block Erase Time (VCC1=5.0V) 4-Kbyte block 4 0.3 s tPS Flash Memory Circuit Stabilization Wait Time 15 µs − Data Hold Time (5) 20 year Table 23.55 Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics (at Topr = 0 to 60 °C(B, U), Topr = −40 to 85 °C (B7, U7 (T version)) / −40 to 125 °C (B7, U7 (V version)) Flash Program, Erase Voltage Flash Read Operation Voltage VCC1 = 5.0 V ± 0.5 V V CC1=4.0 to 5.5 V

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 350 of 390 REJ09B0185-0241 Figure 23.22 Power Supply Circuit Timing Diagram Table 23.56 Power Supply Circuit Timing Characteristics Symbol Parameter Measuring Condition Standard UnitMin. Typ. Max. td(P-R) Time for Internal Power Supply Stabilization During Powering-On VCC1=4.0V to 5.5V 2 ms td(R-S) STOP Release Time 150 µs td(W-S) Low Power Dissipation Mode Wait Mode Release Time 150 µs td(P-R) VCC1 CPU clock CPU clock td(R-S) (a) (b) td(W-S) td(P-R) Time for Internal Power Supply Stabilization During Powering-On Interrupt for (a) Stop mode release or (b)Wait mode release td(R-S) STOP Release Time td(W-S) Low Power Dissipation Mode Wait Mode Release Time Recommended operation voltage

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 351 of 390 REJ09B0185-0241 VCC1=VCC2=5V NOTES: 1. Referenced to V CC1=VCC2=4.0 to 5.5V, VSS = 0V at Topr = −40 to 85°C / −40 to 125°C, f(BCLK)=24MHz unless otherwise specified. T version = −40 to 85°C, V version =−40 to 125°C. 2. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Table 23.57 Electrical Characteristics (1) (1) Symbol Parameter Measuring Condition Standard UnitMin. Typ. Max. VOH HIGH Output Voltage (2) P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 I OH=−5mA VCC1−2.0 V CC1 VP0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 I OH=−5mA VCC2−2.0 V CC2 VOH HIGH Output Voltage (2) P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 OH=−200µA VCC1−0.3 V CC1 VP0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 IOH=−200µA VCC2−0.3 V CC2 VOH HIGH Output Voltage XOUT HIGHPOWER I OH=−1mA VCC1−2.0 V CC1 VLOWPOWER I OH=−0.5mA VCC1−2.0 V CC1 HIGH Output Voltage XCOUT HIGHPOWER With no load applied 2.5 VLOWPOWER With no load applied 1.6 VOL LOW Output Voltage (2) P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 IOL=5mA 2.0 VP0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 IOL=5mA 2.0 VOL LOW Output Voltage (2) P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 IOL=200µA 0.45 VP0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 IOL=200µA 0.45 VOL LOW Output Voltage XOUT HIGHPOWER I OL=1mA 2.0 VLOWPOWER I OL=0.5mA 2.0 LOW Output Voltage XCOUT HIGHPOWER With no load applied 0 VLOWPOWER With no load applied 0 VT+-VT- Hysteresis HOLD , RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT5, NMI, ADTRG, CTS0 to CTS2, CLK0 to CLK4, TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD2, SCL0 to SCL2, SDA0 to SDA2, SIN3, SIN4 0.2 1.0 V VT+-VT- Hysteresis RESET 0.2 2.5 V IIH HIGH Input Current (2) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, XIN, RESET , CNVSS, BYTE VI=5V 5.0 µA IIL LOW Input Current (2) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, XIN, RESET , CNVSS, BYTE VI=0V −5.0 µA RPULLUP Pull-Up Resistance (2) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 V I=0V 30 50 170 k Ω RfXIN Feedback Resistance XIN 1.5 M Ω RfXCIN Feedback Resistance XCIN 15 M Ω VRAM RAM Retention Voltage At stop mode 2.0 V

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 352 of 390 REJ09B0185-0241 NOTES: 1. Referenced to V CC1=VCC2=4.0 to 5.5V, VSS = 0V at Topr = −40 to 85°C / −40 to 125°C, f(BCLK)=24MHz unless otherwise specified. T version = −40 to 85°C, V version =−40 to 125°C. 2. With one timer operated using fC32. 3. This indicates the memory in whic h the program to be executed exists. Table 23.58 Electrical Characteristics (2) (1) Symbol Parameter Measuring Condition Standard UnitMin. Typ. Max. ICC Power Supply Current (VCC1=VCC2=4.0V to 5.5V) In single-chip mode, the output pins are open and other pins are V SS Mask ROM f(BCLK)=24MHz No division, PLL operation 14 20 mA No division, On-chip oscillation 1m A Flash Memory f(BCLK)=24MHz, No division, PLL operation 18 27 mA No division, On-chip oscillation 1.8 mA Flash Memory Program f(BCLK)=10MHz, VCC1=5.0V 15 mA Flash Memory Erase f(BCLK)=10MHz, VCC1=5.0V 25 mA Mask ROM f(XCIN)=32kHz Low power dissipation mode, ROM (3) 25 µA Flash Memory f(BCLK)=32kHz Low power dissipation mode, RAM (3) 25 µA f(BCLK)=32kHz Low power dissipation mode, Flash Memory (3) 420 µA On-chip oscillation, Wait mode 50 µA Mask ROM Flash Memory f(BCLK)=32kHz Wait mode (2), Oscillation capability High 7.5 µA f(BCLK)=32kHz Wait mode (2), Oscillation capability Low 2.0 µA Stop mode Topr =25°C 2.0 6.0 µA Stop mode Topr =85°C 20 µA Stop mode Topr =125°C TBD µA

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 353 of 390 REJ09B0185-0241 VCC1=VCC2=5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −40 to 85°C (T version) / −40 to 125°C (V version) unless otherwise specified) Table 23.59 External Clock Input (XIN input) Symbol Parameter Standard UnitMin. Max. tc External Clock Input Cycle Time 62.5 ns tw(H) External Clock Input HIGH Pulse Width 25 ns tw(L) External Clock Input LOW Pulse Width 25 ns tr External Clock Rise Time 15 ns tf External Clock Fall Time 15 ns

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 354 of 390 REJ09B0185-0241 VCC1=VCC2=5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −40 to 85°C (T version) / −40 to 125°C (V version) unless otherwise specified) Table 23.60 Timer A Input (Counte r Input in Event Counter Mode) Symbol Parameter Standard UnitMin. Max. tc(TA) TAiIN Input Cycle Time 100 ns tw(TAH) TAiIN Input HIGH Pulse Width 40 ns tw(TAL) TAiIN Input LOW Pulse Width 40 ns Table 23.61 Timer A Input (G ating Input in Timer Mode) Symbol Parameter Standard UnitMin. Max. tc(TA) TAiIN Input Cycle Time 400 ns tw(TAH) TAiIN Input HIGH Pulse Width 200 ns tw(TAL) TAiIN Input LOW Pulse Width 200 ns Table 23.62 Timer A Input (External Trigger Input in One-shot Timer Mode) Symbol Parameter Standard UnitMin. Max. tc(TA) TAiIN Input Cycle Time 200 ns tw(TAH) TAiIN Input HIGH Pulse Width 100 ns tw(TAL) TAiIN Input LOW Pulse Width 100 ns Table 23.63 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Symbol Parameter Standard UnitMin. Max. tw(TAH) TAiIN Input HIGH Pulse Width 100 ns tw(TAL) TAiIN Input LOW Pulse Width 100 ns Table 23.64 Timer A Input (Counter Increment/Decrement Input in Event Counter Mode) Symbol Parameter Standard UnitMin. Max. tc(UP) TAiOUT Input Cycle Time 2000 ns tw(UPH) TAiOUT Input HIGH Pulse Width 1000 ns tw(UPL) TAiOUT Input LOW Pulse Width 1000 ns tsu(UP-TIN) TAiOUT Input Setup Time 400 ns th(TIN-UP) TAiOUT Input Hold Time 400 ns Table 23.65 Timer A Input (Two-phase Pulse Input in Event Counter Mode) Symbol Parameter Standard UnitMin. Max. tc(TA) TAiIN Input Cycle Time 800 ns tsu(TAIN-TAOUT) TAiOUT Input Setup Time 200 ns tsu(TAOUT-TAIN) TAiIN Input Setup Time 200 ns

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 355 of 390 REJ09B0185-0241 VCC1=VCC2=5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −40 to 85°C (T version) / −40 to 125°C (V version) unless otherwise specified) Table 23.66 Timer B Input (Counte r Input in Event Counter Mode) Symbol Parameter Standard UnitMin. Max. tc(TB) TBiIN Input Cycle Time (counted on one edge) 100 ns tw(TBH) TBiIN Input HIGH Pulse Width (counted on one edge) 40 ns tw(TBL) TBiIN Input LOW Pulse Width (counted on one edge) 40 ns tc(TB) TBiIN Input Cycle Time (counted on both edges) 200 ns tw(TBH) TBiIN Input HIGH Pulse Width (counted on both edges) 80 ns tw(TBL) TBiIN Input LOW Pulse Width (counted on both edges) 80 ns Table 23.67 Timer B Input (Pulse Period Measurement Mode) Symbol Parameter Standard UnitMin. Max. tc(TB) TBiIN Input Cycle Time 400 ns tw(TBH) TBiIN Input HIGH Pulse Width 200 ns tw(TBL) TBiIN Input LOW Pulse Width 200 ns Table 23.68 Timer B Input (Pulse Width Measurement Mode) Symbol Parameter Standard UnitMin. Max. tc(TB) TBiIN Input Cycle Time 400 ns tw(TBH) TBiIN Input HIGH Pulse Width 200 ns tw(TBL) TBiIN Input LOW Pulse Width 200 ns Table 23.69 A/D Trigger Input Symbol Parameter Standard UnitMin. Max. tc(AD) ADTRG Input Cycle Time 1000 ns tw(ADL) ADTRG input LOW Pulse Width 125 ns Table 23.70 Serial Interface Symbol Parameter Standard UnitMin. Max. tc(CK) CLKi Input Cycle Time 200 ns tw(CKH) CLKi Input HIGH Pulse Width 100 ns tw(CKL) CLKi Input LOW Pulse Width 100 ns td(C-Q) TXDi Output Delay Time 80 ns th(C-Q) TXDi Hold Time 0 ns tsu(D-C) RXDi Input Setup Time 70 ns th(C-D) RXDi Input Hold Time 90 ns Table 23.71 External Interrupt INTi Input Symbol Parameter Standard UnitMin. Max. tw(INH) INTi Input HIGH Pulse Width 250 ns tw(INL) INTi Input LOW Pulse Width 250 ns

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 356 of 390 REJ09B0185-0241 VCC1=VCC2=5V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −40 to 85°C (T version) / −40 to 125°C (V version) unless otherwise specified) Figure 23.23 Ports P0 to P10 Measurement Circuit P10 30pF

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 357 of 390 REJ09B0185-0241 Figure 23.24 Timing Diagram (1) TAiIN input TAiOUT input During event counter mode TBiIN input ADTRG input tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) th(TIN-UP) tsu(UP-TIN) TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) TAiOUT input (Up/down input) TAiIN input Two-phase pulse input in event counter mode tc(TA) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) TAiOUT input XIN input tw(H) tw(L)tr tf tc VCC1=VCC2=5V

M16C/62P Group (M16C/62P , M16C/62PT) 23. Electrical Characteristics Rev.2.41 Jan 10, 2006 Page 358 of 390 REJ09B0185-0241 Figure 23.25 Timing Diagram (2) tsu(D-C) CLKi TXDi RXDi tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) INTi input td(C-Q) th(C-D) th(C-Q) VCC1=VCC2=5V

M16C/62P Group (M16C/62P , M16C/62PT) 24. Precautions Rev.2.41 Jan 10, 2006 Page 359 of 390 REJ09B0185-0241 24. Precautions

24.1 SFR

24.1.1 Register Settings

Table Table 24.1 Registers with Write-only Bits wh ich can only be written to. Set these registers with immediate values. When establishing the next value by altering the present value, write the present value to the RAM as well as to the register. Transfer the next value to the register after making changes in the RAM. Table 24.1 Registers with Write-only Bits Register Symbol Address Watchdog timer start register WDC 000E Timer A1-1 register TA11 0343 to 0342 Timer A2-1 register TA21 0345 to 0344 Timer A4-1 register TA41 0347 to 0346 Short-circuit preventionTimer DTT 034C Timer B2 Interrupt Generating Frequency Set Counter ICTB2 034D SI/03 bit rate register S3BRG 0363 SI/04 bit rateregister S4BRG 0367 UART0 bit rateregister U0BRG 03A1 UART1 bit rateregister U1BRG 03A9 UART2 bit rate register U2BRG 0379 UART0 Transmit buffer register U0TB 03A3 to 03A2 UART1 Transmit buffer register U1TB 03AB to 03AA UART2 Transmit buffer register U2TB 037B to 037A Ups and downs flag UDF 0384 Timer 0 register TA0 0387 to 0386 Timer 1 register TA1 0389 to 0388 Timer 2 register TA2 038B to 038A Timer 3 register TA3 038D to 038C Timer 4 register TA4 038F to 038E

M16C/62P Group (M16C/62P , M16C/62PT) 24. Precautions Rev.2.41 Jan 10, 2006 Page 360 of 390 REJ09B0185-0241

24.2 Reset

When supplying power to the microcomputer, the power supply voltage applied to the VCC1 pin must meet the conditions of SVCC. Figure 24.1 Timing of SV CC Symbol Parameter Standard UnitMin. Typ. Max. SVCC Power supply rising gradient (VCC1)(Voltage range 0 to 2.0) 0.05 V/ms SVCC Power supply rising gradient (VCC1) SVCC 2.0V 0V Time Voltage

M16C/62P Group (M16C/62P , M16C/62PT) 24. Precautions Rev.2.41 Jan 10, 2006 Page 361 of 390 REJ09B0185-0241

24.3 Bus

• The ROMless version can operate only in the microprocessor mode, connect the CNVSS pin to VCC1.
• When resetting CNVSS pin with “H” input, contents of internal ROM cannot be read out.

M16C/62P Group (M16C/62P , M16C/62PT) 24. Precautions Rev.2.41 Jan 10, 2006 Page 362 of 390 REJ09B0185-0241

24.4 PLL Frequency Synthesizer

Stabilize supply voltage so that the standard of the power supply ripple is met. Figure 24.2 Timing of Voltage Fluctuation Symbol Parameter Standard UnitMin. Typ. Max. f(ripple) Power supply ripple allowable frequency (VCC1)1 0 k H z VP-P(ripple) Power supply ripple allowable amplitude voltage (VCC1=5V) 0.5 V (VCC1=3V) 0.3 V VCC(|∆V /∆T|) Power supply ripple rising / falling gradient (VCC1=5V) 0.3 V/ms (VCC1=3V) 0.3 V/ms Vp-p(ripple) f(ripple) VCC1 f(ripple) Power supply ripple allowable frequency (VCC1) Vp-p(ripple) Power supply ripple allowable amplitude voltage

M16C/62P Group (M16C/62P , M16C/62PT) 24. Precautions Rev.2.41 Jan 10, 2006 Page 363 of 390 REJ09B0185-0241

24.5 Power Control

• When exiting stop mode by hardware reset, set RESET pin to “L” until a main clock oscillation is stabilized.
• Set the MR0 bit in the TAiMR register (i=0 to 4) to “0 ” (pulse is not output) to use the timer A to exit stop mode.
• When entering wait mode, insert a JMP.B instructi on before a WAIT instruction. Do not execute any instructions which can generate a write to RAM betw een the JMP.B and WAIT instructions. Disable the DMA transfers, if a DMA transfer may occur between the JMP.B and WAIT instructions. After the WAIT instruction, insert at least 4 NOP instructions. When entering wait mode, the instruction queue roadstead the instructions following WAIT, and depending on timing, some of these may execute before the microcomputer enters wait mode. Program example when entering wait mode Program Example: JMP.B L1 ; Insert JMP.B instruction before WAIT instruction L1: FSET I ; WAIT ; Enter wait mode NOP ; More than 4 NOP instructions NOP NOP NOP
• When entering stop mode, insert a JMP.B instruction immediately after executing an instruction which sets the CM10 bit in the CM1 register to “1”, and then in sert at least 4 NOP instructions. When entering stop mode, the instruction queue reads ah ead the instructions following the instruction which sets the CM10 bit to “1” (all clock stops), and, some of these may execute before the microcomputer enters stop mode or before the interrupt routine for returning from stop mode. Program example when entering stop mode Program Example: FSET I BSET CM10 ; Enter stop mode JMP.B L2 ; Insert JMP.B instruction L2: NOP ; More than 4 NOP instructions NOP NOP NOP
• Wait until the main clock oscillation stabilizes, before switching the clock source for CPU clock to the main clock. Similarly, wait until the sub clock oscillates stably be fore switching the clock source for CPU clock to the sub clock.

M16C/62P Group (M16C/62P , M16C/62PT) 24. Precautions Rev.2.41 Jan 10, 2006 Page 364 of 390 REJ09B0185-0241

• Suggestions to reduce power consumption Ports The processor retains the state of each I/O port even wh en it goes to wait mode or to stop mode. A current flows in active I/O ports. A pass current flows in input ports that high-impedance state. When entering wait mode or stop mode, set non-used ports to input and stabilize the potential. A/D converter When A/D conversion is not pe rformed, set the VCUT bit of AD iCON1 register to “0” (no VREF connection). When A/D conversion is performed, start the A/D conversion at least 1 µs or longer after setting the VCUT bit to “1” (VREF connection). D/A converter When not performing D/A conversion, set the DAiE bit (i =0, 1) of DACON register to “0” (input inhibited) and DAi register to “00h”. Stopping peripheral functions Use the CM0 register CM02 bit to stop the unnecessary peripheral functions during wait mode. However, because the peripheral function clock (fC 32) generated from the sub- clock does not stop, this measure is not conducive to reducing the power consum ption of the chip. If low speed mode or low power dissipation mode is to be changed to wait mode, set the CM02 bit to “0” (do not peripheral function clock stopped when in wait mode), before changing wait mode. Switching the oscillation-driving capacity Set the driving capacity to “LOW” when oscillation is stable.

M16C/62P Group (M16C/62P , M16C/62PT) 24. Precautions Rev.2.41 Jan 10, 2006 Page 365 of 390 REJ09B0185-0241

24.6 Protect

Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0” (write protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in which the PRC2 bit is set to “1” and the next instruction.

M16C/62P Group (M16C/62P , M16C/62PT) 24. Precautions Rev.2.41 Jan 10, 2006 Page 366 of 390 REJ09B0185-0241

24.7 Interrupt

24.7.1 Reading address 00000h

Do not read the address 00000h in a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from the address 00000h during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to “0”. If the address 00000h is read in a program, the IR bit for the interrupt which has the highest priority among the enabled interrupts is cleared to “0”. This factors a pr oblem that the interrupt is canceled, or an unexpected interrupt request is generated.

24.7.2 Setting the SP

Set any value in the SP(USP, ISP) befo re accepting an interrup t. The SP(USP, ISP) is cleared to “0000h” after reset. Therefore, if an interrupt is accepted before setting any value in the SP(USP, ISP), the program may go out of control. Especially when using NMI interrupt, set a value in the ISP at the beginning of the program. For the first and only the first instruction after reset, all interrupts including NMI interrupt are disabled.

24.7.3 The NMI Interrupt

• The NMI interrupt cannot be disabled. If this interrupt is unused, connect the NMI pin to VCC1 via a resistor (pull-up).
• The input level of the NMI pin can be read by accessing the P8_5 bi t in the P8 register. Note that the P8_5 bit can only be read when determining the pin level in NMI interrupt routine.
• Stop mode cannot be entered into while input on the NMI pin is low. This is because while input on the NMI pin is low the CM10 bit in the CM1 register is fixed to “0”.
• Do not go to wait mode while input on the NMI pin is low. This is because when input on the NMI pin goes low, the CPU stops but CPU clock remains active; theref ore, the current consumption in the chip does not drop. In this case, normal condition is restored by an interrupt generated thereafter.
• The low and high level durations of the input signal to the NMI pin must each be 2 CPU clock cycles + 300 ns or more.

M16C/62P Group (M16C/62P , M16C/62PT) 24. Precautions Rev.2.41 Jan 10, 2006 Page 367 of 390 REJ09B0185-0241

24.7.4 Changing the Interrupt Generate Factor

If the interrupt generate factor is changed, the IR bit in the interrupt control register for the changed interrupt may inadvertently be set to “1” (interrupt requested). If you changed the interrupt generate factor for an interrupt that needs to be used, be sure to clear the IR bit for that interrupt to “0” (interrupt not requested). Changing the interrupt generate factor refered to here means any act of changing th e source, polarity or timing of the interrupt assigned to each software interrupt num ber. Therefore, if a mode change of any peripheral function involves changing the generate factor, polarity or timing of an interrupt, be sure to clear the IR bit for that interrupt to “0” (interrupt not requested) after making such changes. Refer to the description of each peripheral function for details about the interrupts from peripheral functions. Figure 24.3 shows the Procedure for Changing the Interrupt Generate Factor. Figure 24.3 Procedure for Changing the Interrupt Generate Factor

24.7.5 INT Interrupt

• Either an “L” level of at least tW(INH) or an “H” level of at least tW(INL) width is necessary for the signal input to pins INT0 through INT5 regardless of the CPU operation clock.
• If the POL bit in the INT0IC to IN T5IC registers or the IFSR7 to IFSR 0 bits in the IFSR register are changed, the IR bit may inadvertently set to “1” (interrupt requested). Be sure to clear the IR bit to “0” interrupt not requested) after changing any of those register bits. IR bit: A bit in the interrupt control register fo r the interrupt whose interrupt generate factor is to be changed NOTES : 1.The above settings must be executed indi vidually. Do not execute two or more settings simultaneously (using one instruction). 2.Use the I flag for the INTi interrupt (i = 0 to 5). For the interrupts from peripheral functions other than the INTi interrupt, turn off the peripheral function that is the source of the interrupt in order not to generate an interrupt request before changing the interrupt generate factor. In this case, if the maskable interrupts can all be disabled without causing a problem, use the I flag. Otherwise, use the corresponding ILVL2 to ILVL0 bit for the interrupt whose interrupt generate factor is to be changed. 3. Refer to 18.4.6 Rewrite the Interrupt Control Register for details about the instructions to use and the notes to be taken for instruction execution. Use the MOV instruction to clear the IR bit to “0” (interrupt not requested) (3) Disable interrupts (2, 3) Change the interrupt generate factor (including a mode change of peripheral function) Enable interrupts (2, 3) Changing the interrupt source End of change

M16C/62P Group (M16C/62P , M16C/62PT) 24. Precautions Rev.2.41 Jan 10, 2006 Page 368 of 390 REJ09B0185-0241

24.7.6 Rewrite the Interrupt Control Register

(a) The interrupt contro l register for any interrupt should be mo dified in places where no requests for that interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register. (b) To rewrite the interrupt control register for any interr upt after disabling that interrupt, be careful with the instruction to be used.

• Changing any bit other than the IR bit
• Changing the IR bit Depending on the instruction used, the IR bit may not always be cleared to “0” (interrupt not requested). Therefore, be sure to use the MOV instruction to clear the IR bit. (c) When using the I flag to disable an interrupt, refer to the sample program fragments shown below as you set the I flag. (Refer to (b) for details about rewrite the interrupt control regist ers in the sample program fragments.) Examples 1 through 3 show how to prevent the I flag from being set to “1” (interrupts enabled) before the interrupt control register is rewrited, owing to the effects of the internal bus and the instruction queue buffer. Example 1:Using the NOP instruction to keep the program waiting until the interrupt control register is modified INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Set the TA0IC register to “00h”. NOP ; NOP FSET I ; Enable interrupts. The number of NOP instruction is as follows. PM20=1(1 wait) : 2, PM20=0(2 wait) : 3, when using HOLD function : 4. Example 2:Using the dummy read to keep the FSET instruction waiting INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Set the TA0IC register to “00h”. MOV.W MEM, R0 ; Dummy read FSET I ; Enable interrupts. Example 3:Using the POPC instruction to changing the I flag INT_SWITCH3: PUSHC FLG FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Set the TA0IC register to “00h”. POPC FLG ; Enable interrupts.

24.7.7 Watchdog Timer Interrupt

Initialize the watchdog timer after the watchdog timer interrupt occurs.

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24.8 DMAC

24.8.1 Write to DMAE Bi t in DMiCON Register

When both of the conditions below are met, follow the steps below. Conditions

• The DMAE bit is set to “1” again while it remains set (DMAi is in an active state).
• A DMA request may occur simultaneously when the DMAE bit is being written. Steps (1) Write “1” to the DMAE bit and DMAS bit in the DMiCON register simultaneously (1). (2) Make sure that the DMAi is in an initial state (2) in a program. If the DMAi is not in an initial state, the above steps should be repeated. NOTES: 1.The DMAS bit remains unchanged even if “1” is written. However, if “0” is written to this bit, it is set to “0” (DMA not requested). In order to prevent the DMAS bit from being modified to “0”, “1” should be written to the DMAS bit when “1” is written to the DMAE bit. In this way the state of the DMAS bit immediately before being written can be maintained. Similarly, when writing to the DMAE bit with a read-modify-write instruction, “1” should be written to the DMAS bit in order to maintain a DMA request which is generated during execution. 2.Read the TCRi register to verify whether the DMAi is in an initial state. If the read value is equal to a value which was written to the TCRi register before DMA transfer start, the DMAi is in an initial state. (If a DMA request occurs after writing to the DMAE bit, the value written to the TCRi register is “1”.) If the read value is a value in the middle of transfer, the DMAi is not in an initial state.

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24.9 Timers

24.9.1 Timer A

24.9.1.1 Timer A (Timer Mode)

The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to “1” (count starts). Always make sure the TAiMR register is modified wh ile the TAiS bit remains “0” (count stops) regardless whether after reset or not. While counting is in progress, the counter value can be read out at any time by reading the TAi register. However, if the counter is read at the same time it is reloaded, the value “FFFFh” is read. Also, if the counter is read before it starts counting after a value is set in the TAi register while not counting, the set value is read. If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go to a high- impedance state.

24.9.1.2 Timer A (Event Counter Mode)

The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the UDF register, the ON SF register TAZIE, TA0TGL and TA0TGH bits and the TRGSR register before setting the TAiS bit in the TABSR register to “1” (count starts). Always make sure the TAiMR register, the UDF register, the TAZIE, TA0TGL and TA0TGH bits in the ONSF register and the TRGSR register are modified while the TAiS bit remains “0” (count stops) regardless whether after reset or not. While counting is in progress, the counter value can be read out at any time by reading the TAi register. However, “FFFFh” can be read in underflow, while reloading, and “0000h” in overflow. When setting TAi register to a value during a counter stop, the setting value can be read before a counter starts counting. Also, if the counter is read before it starts counting after a valu e is set in the TAi register while not counting, the set value is read. If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go to a high- impedance state.

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24.9.1.3 Timer A (One-shot Timer Mode)

The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to “1” (count starts). Always make sure the TAiMR register, the TA0TGL a nd TA0TGH bits and the TRGSR register are modified while the TAiS bit remains “0” (count stops) regardless whether after reset or not. When setting TAiS bit to “0” (count stop), the followings occur:

• A counter stops counting and a content of reload register is reloaded.
• TAiOUT pin outputs “L”.
• After one cycle of the CPU clock, the IR bit in the TAiIC register is set to “1” (interrupt request). Output in one-shot timer mode synchronizes with a count source internally generated. When an external trigger has been selected, one-cycle delay of a count source as maximum occurs between a trigger input to TAiIN pin and output in one-shot timer mode. The IR bit is set to “1” when timer operating mode is set with any of the following procedures:
• Select one-shot timer mode after reset.
• Change an operating mode from timer mode to one-shot timer mode.
• Change an operating mode from event counter mode to one-shot timer mode. To use the Timer Ai interrupt (the IR bit), set the IR bit to “0” after the changes listed above have been made. When a trigger occurs, while counting, a counter relo ads the reload register to continue counting after generating a re-trigger and counting down once. To generate a trigger while counting, generate a second trigger between occurring the previous trigger and operating longer than one cycle of a timer count source. If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go to a high- impedance state.

24.9.1.4 Timer A (Pulse Width Modulation Mode)

The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to “1” (count starts). Always make sure the TAiMR register, TA0TGL and TA0TGH bits and the TRGSR register are modified while the TAiS bit remains “0” (count stops) regardless whether after reset or not. The IR bit is set to “1” when setting a timer operating mode with any of the following procedures:

• Select the PWM mode after reset.
• Change an operating mode from timer mode to PWM mode.
• Change an operating mode from event counter mode to PWM mode. To use the Timer Ai interrupt (interrupt request bit), set the IR bit to “0” by program after the above listed changes have been made. When setting TAiS register to “0” (count stop) during PWM pulse output, the following action occurs:
• Stop counting.
• When TAiOUT pin is output “H”, output level is set to “L” and the IR bit is set to “1”.
• When TAiOUT pin is output “L”, both output level and the IR bit remains unchanged. If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go to a high- impedance state.

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24.9.2 Timer B

24.9.2.1 Timer B (Timer Mode)

The timer remains idle after reset. Set the mode, count s ource, counter value, etc. using the TBiMR (i = 0 to 5) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to “1” (count starts). Always make sure the TBiMR register is modified wh ile the TBiS bit remains “0” (count stops) regardless whether after reset or not. A value of a counter, while counting, can be read in TB i register at any time. “FFFFh” is read while reloading. Setting value is read between setting values in TBi register at count stop and starting a counter.

24.9.2.2 Timer B (Event Counter Mode)

The timer remains idle after reset. Set the mode, count s ource, counter value, etc. using the TBiMR (i = 0 to 5) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to “1” (count starts). Always make sure the TBiMR register is modified wh ile the TBiS bit remains “0” (count stops) regardless whether after reset or not. The counter value can be read out on-the-fly at any time by reading the TBi register. However, if this register is read at the same time the counter is reloaded, the read va lue is always “FFFFh”. If the TBi register is read after setting a value in it while not counting but before the counter starts counting, the read value is the one that has been set in the register.

24.9.2.3 Timer B (Pulse Period/pul se Width Measurement Mode)

The timer remains idle after reset. Set the mode, count s ource, etc. using the TBiMR (i = 0 to 5) register before setting the TBiS bit in the TABSR or the TBSR register to “1” (count starts). Always make sure the TBiMR register is modified wh ile the TBiS bit remains “0” (count stops) regardless whether after reset or not. To clear the MR3 bit to “0” by writing to the TBiMR register while the TBiS bit = 1 (count starts), be sure to write the same value as previously written to the TM0D0, TM0D1, MR0, MR1, TCK0 and TCK1 bits and a 0 to the MR2 bit. The IR bit in the TBiIC register (i=0 to 5) goes to “1” (interrupt request), when an effective edge of a measurement pulse is input or Timer Bi is overflowed. The factor of interrupt request can be determined by use of the MR3 bit in the TBiMR register within the interrupt routine. If the source of interrupt cannot be id entified by the MR3 bit such as wh en the measurement pulse input and a timer overflow occur at the same time, use another timer to count the number of times Timer B has overflowed. To set the MR3 bit to “0” (no overflow), set TBiMR regi ster with setting the TBiS bit to “1” and counting the next count source after setting the MR3 bit to “1” (overflow). Use the IR bit to detect only overflows. Use the MR3 bit only to determine the interrupt factor. When a count is started and the first effective edge is input, an indetermin ate value is transferred to the reload register. At this time, Timer Bi interrupt request is not generated. A value of the counter is indeterminate at the begi nning of a count. MR3 may be set to “1” and Timer Bi interrupt request may be generated between a count start and an effective edge input. For pulse width measurement, pulse widths are succes sively measured. Use program to check whether the measurement result is an “H” level width or an “L” level width.

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24.10 Serial interface

24.10.1 Clock Synchronous Serial I/O

24.10.1.1 Transmission/reception

With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to “L” when the data-receivable st atus becomes ready, which informs the tr ansmission side that the reception has become ready. The output level of the RTSi pin goes to “H” when reception starts. So if the RTSi pin is connected to the CTSi pin on the transmission side, the circuit can transmission and reception data with consistent timing. With the internal clock, the RTS function has no effect. If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase output forcible cutoff by input on NMI pin enabled), the RTS2 and CLK2 pins go to a high-impedance state.

24.10.1.2 Transmission

When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the CKPOL bit in the UiC0 register = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.

• The TE bit in the UiC1 register= 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in UiTB register)
• If CTS function is selected, input on the CTSi pin = L

24.10.1.3 Reception

In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock. Fix settings for transmission even when using the device only for reception. Dummy data is output to the outside from the TXDi pin when receiving data. When an internal clock is selected, set the TE bit in the UiC1 register (i = 0 to 2) to 1 (transmission enabled) and write dummy data to the UiTB register, and the shift clock will thereby be generated. When an external clock is selected, set the TE bit to 1 and write dummy data to the UiTB register, and the shift clock will be generated when the external clock is fed to the CLKi input pin. When successively receiving data, if all bits of the next receive data are prepared in the UARTi receive register while the RE bit in the UiC1 register (i = 0 to 2) = 1 (data present in the UiRB register), an overrun error occurs and the OER bit in the UiRB register is set to “1” (overrun error occurred). In this case, because the content of the UiRB register is indeterminate, a corrective measure must be taken by programs on the transmit and receive sides so that the valid data before the overrun error oc curred will be retransmitted. Note that when an overrun error occurred, the IR bit in the SiRIC register does not change state. To receive data in succession, set dummy data in the lower-order byte of the UiTB register every time reception is made. When an external clock is selected, the conditions must be met while if the CKPOL bit = 0, the external clock is in the high state; if the CKPOL bit = 1, the external clock is in the low state.

• The RE bit in the UiC1 register= 1 (reception enabled)
• The TE bit in the UiC1 register= 1 (transmission enabled)
• The TI bit in the UiC1 register= 0 (data present in the UiTB register)

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24.10.2 UART

24.10.2.1 Special Mode 1(I 2C Mode)

When generating start, stop and restart conditions, set the STSPSEL bit in the UiSMR4 register to “0” and wait for more than half cycle of the transfer clock before setting each condition generate bit (STAREQ, RSTAREQ and STPREQ) from “0” to “1”.

24.10.2.2 Special Mode 2

If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase output forcible cutoff by input on NMI pin enabled), the RTS2 and CLK2 pins go to a high-impedance state.

24.10.2.3 Special M ode 4 (SIM Mode)

A transmit interrupt request is generated by setting the U2C1 register U2IRS bit to “1” (transmission complete) and U2ERE bit to “1” (error signal output) after reset is deasserted. Therefore, when using SIM mode, be sure to clear the IR bit to “0” (no interrupt request) after setting these bits.

24.10.3 SI/O3, SI/O4

The SOUTi default value which is set to the SOUTi pin by the SMi7 bit approximately 10ns may be output when changing the SMi3 bit from “0” (I/O port) to “1” (SOUTi output and CLK function) while the SMi2 bit in the SiC (i=3 and 4) to “0” (SOUTi output) and the SMi6 bit is set to “1” (internal clock). And then the SOUTi pin is held high-impedance. If the level which is output from the SOUTi pin is a pr oblem when changing the SMi3 bit from “0” to “1”, set the default value of the SOUTi pin by the SMi7 bit.

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24.11 A/D Converter

Set ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before a trigger occurs). When the VCUT bit in the ADCON1 register is change d from “0” (Vref not connected) to “1” (Vref connected), start A/D conversion after passing 1 µs or longer. To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert capacitors between the A VCC, VREF, and analog input pins (ANi(i=0 to 7), AN0_i, AN2_i) each and the A VSS pin. Similarly, insert a capacitor between the VCC1 pin and the VSS pin. Figure 24.4 is an example connection of each pin. Make sure the port direction bits for those pins that are used as analog inputs are set to “0” (input mode). Also, if the TGR bit in the ADCON0 register = 1 (external trigger), make sure the port direction bit for the ADTRG pin is set to “0” (input mode). When using key input interrupts, do not use any of the four AN4 to AN7 pins as analog inputs. (A key input interrupt request is generated when the A/D input voltage goes low.) The φAD frequency must be 12MHz or less. With out sample-and-hold function, limit the φAD frequency to 250kHz or more. With the sample and hold function, limit the φAD frequency to 1MHz or more. When changing an A/D operating mode , select analog input pin again in the CH2 to CH0 bits in the ADCON0 register and the SCAN1 to SCAN0 bits in the ADCON1 register. Figure 24.4 Use of Capacitors to Reduce Noise VCC1 VSS AVCC AVSS VREF ANi C1 C2 Microcomputer NOTES : 2. Use thick and shortest possible wiring to connect capacitors. VCC2 VSS VCC1 VCC1 VCC2 ANi: ANi, AN0_i and AN2_i (i=0 to 7)

M16C/62P Group (M16C/62P , M16C/62PT) 24. Precautions Rev.2.41 Jan 10, 2006 Page 376 of 390 REJ09B0185-0241 If VCC2 < VCC1, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins. If the CPU reads the ADi register (i = 0 to 7) at the same time the conversion result is stored in the ADi register after completion of A/D conversion, an incorrect value may be stored in the ADi register. This problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for CPU clock.

• When operating in one-shot or single-sweep mode Check to see that A/D conversion is completed before reading the target ADi register. (Check the IR bit in the ADIC register to see if A/D conversion is completed.)
• When operating in repeat mode or repeat sweep mode 0 or 1 Use the main clock for CPU clock directly without dividing it. If A/D conversion is forcibly terminated while in progress by setting the ADST bit in the ADCON0 register to “0” (A/D conversion halted), the conversion result of the A/D converter is indeterminate. The contents of ADi registers irrelevant to A/D conversion may also become indeterminate. If while A/D conversion is underway the ADST bit is cleared to “0” in a program, ignore the values of all ADi registers. When setting the ADST bit in the ADCON0 register to “0” in single-sweep mode during A/D conversion and suspending A/D conversion, disable the interrupt before setting the ADST bit to “0”. The applied intermediate potential ma y cause more increase in power consumption than other analog input pins (AN0 to AN3, AN0_0 to AN0_7 and AN2_0 to AN2_7), since the AN4 to AN7 are used with the KI0 to KI3.

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24.12 Programmable I/O Ports

If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase output forcible cutoff by input on NMI pin enabled), the P7_2 to P7_5, P8_0 and P8_1 pins go to a high-impedance state. Setting the SM32 bit in the S3C register to “1” causes the P9_2 pin to go to a high-impedance state. Similarly, setting the SM42 bit in the S4C register to “1” causes the P9_6 pin to go to a high-impedance state. The input threshold voltage of pins differs between programmable input/output ports and peripheral functions. Therefore, if any pin is shared by a programmable input/output port and a peripheral function and the input level at this pin is outside the range of re commended operating conditions VIH and VIL (neither “high” nor “low”), the input level may be determined differently depending on which side-the programmable input/output port or the peripheral function-is currently selected. When changing the PD14_i bit (i=0 to 1) in the PC14 register from “0” (input port) to “1” (output port), follow the procedures below. Setting Procedure (1) Set P14_i bit :MOV .B #00000001 b, PC14 ; P14_i bit setting (2) Change PD14_i bit to “1” by MOV instruction :MOV .B #0011 0001b, PC14 ; Change to output port Indeterminate values are read from the P3_7 to P3_4, PD3_7 to PD3_4 bits by reading the P3 and PD3 registers when the PM01 to PM00 bits in the PM0 regist er are set to “01b” (memory expansion mode) or “11b”(microprocessor mode) and setting the PM11 bit to “1”. Use the MOV instruction when rewriting the P3 and PD3 registers (including the case that the size specifier is “.W” and the P2 and PD2 registers are rewritten). When the PM01 to PM00 bits are rewritten, "L” is outp ut from the P3_7 to P3_4 pins during 0.5 cycles of the BCLK by setting the PM01 to PM00 bits in the PM0 regi ster to “01b” (memory expansion mode) or “11b” (microprocessor mode) from “00b” (single-chip mode) after setting the PM11 bit to “1”.

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24.13 Electric Characteristic Difference s Between Mask ROM and Flash Memory

Flash memory version and mask ROM version may have different characteristics, operating margin, noise tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern, etc. When switching to the mask ROM version, conduct equivalent tests as system evaluation tests conducted in the flush memory version.

24.14 Mask ROM

When using the masked ROM version, write nothing to internal ROM area.

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24.15 Flash Memory Version

24.15.1 Functions to Inhibit Rewr iting Flash Memory Rewrite

ID codes are stored in addresse s 0FFFDFh, 0FFFE3h, 0FFFEBh, 0F FFEFh, 0FFFF3h, 0FFFF7h, and 0FFFFBh. If wrong data are written to theses addresses, the flash memory cannot be read or written in standard serial I/O mode. The ROMCP register is mapped in address 0FFFFFh. If wrong data is written to this address, the flash memory cannot be read or written in parallel I/O mode. In the flash memory version of microcomputer, these ad dresses are allocated to th e vector addresses (H) of fixed vectors.

24.15.2 Stop mode

When the microcomputer enters stop mode, execute the instruction which sets the CM10 bit to “1” (stop mode) after setting the FMR01 bit to “0” (CPU rewrite mode disabled) and disabling the DMA transfer.

24.15.3 Wait mode

When shifting to wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) before executing the WAIT instruction.

24.15.4 Low power dissipation mode, on-chi p oscillator low power dissipation

If the CM05 bit is set to “1” (main clock stop), the following commands must not be executed.

• Program
• Block erase
• Erase all unlocked blocks
• Lock bit program

24.15.5 Writing command and data

Write the command code and data at even addresses.

24.15.6 Program Command

Write “xx40h” in the first bus cycle and write data to th e write address in the second bus cycle, and an auto program operation (data program and verify) will start. Make sure the address value specified in the first bus cycle is the same even address as the write address specified in the second bus cycle.

24.15.7 Lock Bit Program Command

Write “77h” in the first bus cycle and write “xxD0h” to the uppermost address of a block (even address, however) in the second bus cycle, and the lock bit for the specified block is cleare d to “0”. Make sure then address value specified in the first bus cycle is the same uppermost block address that is specified in the second bus cycle.

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24.15.8 Operation speed

Before entering CPU rewrite mode (EW0 or EW1 mode), set the CM11 bit in the CM1 register to “0” (main clock), select 10 MHz or less for CPU clock using the CM06 bit in the CM0 register and CM17 to CM16 bits in the CM1 register. Also, set the PM17 bit in the PM1 register to “1” (with wait state).

24.15.9 Instructions inhibited against use

The following instructions cannot be used in EW0 mode because the flash memory’s internal data is referenced: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction. 24.15.10Interrupts EW0 Mode

• Any interrupt which has a vector in the relocatable vector table can be used providing that its vector is transferred into the RAM area.
• The NMI and watchdog timer interrupts can be used becau se the FMR0 register and FMR1 register are initialized when one of those interrupts occurs. The jump addresses for those interrupt service routines should be set in the fixed vector table. Because the rewrite operati on is halted when a NMI or watchdog timer interrupt occurs, the rewrite program must be executed again after exiting the interrupt service routine.
• The address match interrupt cannot be used because the flash memory’s internal data is referenced. EW1 Mode
• Make sure that any interrupt which has a vector in th e variable vector table or address match interrupt will not be accepted during the auto program or auto erase period.
• Avoid using watchdog timer interrupts.
• The NMI interrupt can be used because the FMR0 regist er and FMR1 register ar e initialized when this interrupt occurs. The jump address for the interrupt service routine should be set in the fixed vector table. Because the rewrite operation is halted when a NMI interrupt occurs, the rewrite program must be executed again after exiting the interrupt service routine.

24.15.11 How to access

To set the FMR01, FMR02, or FMR11 bit to “1”, writ e “0” and then “1” in succession. This is necessary to ensure that no interrupts or DMA transfers will occur before writing “1” after writing “0”. Also only when NMI pin is “H” level. 24.15.12Writing in the user ROM area EW0 Mode

• If the power supply voltage drops while rewriting any block in which the rewrite control program is stored, a problem may occur that the rewrite control program is not correctly rewritten and, consequently, the flash memory becomes unable to be rewritten thereafter. In this case, standard serial I/O or parallel I/O mode should be used. EW1 Mode
• Avoid rewriting any block in which the rewrite control program is stored.

M16C/62P Group (M16C/62P , M16C/62PT) 24. Precautions Rev.2.41 Jan 10, 2006 Page 381 of 390 REJ09B0185-0241 24.15.13DMA transfer In EW1 mode, make sure that no DMA transfers will occur while the FMR00 bit in the FMR0 register = 0 (during the auto program or auto erase period). 24.15.14Regarding Programming/Erasing Endurance and Execution Time As the number of programming/erasur e times increases, so does the execu tion time for software commands (Program, Block Erase, Erase All Un lock Blocks, and Lock Bit Program). Especially when the number of programming/erasure times exceeds 1,000, the software command execution time is noticeably extended. Therefore, the software command wait time that is set must be greater than the maximum rated value of electrical characteristics. The software commands are suspended by hard ware reset 1, hardware reset 2, NMI interrupt, and watchdog timer interrupt. If a software command is suspended by such reset or interru pt, the block that was in process must be erased before reexecuting the suspended command.

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24.16 Noise

Connect a bypass capacitor (approximately 0.1 µF) across the VCC1 and XSS pins, and VCC2 and VSS pins using the shortest and thicker possible wiring. Figure 24.5 shows the Bypass Capacitor Connection. Figure 24.5 Bypass Capacitor Connection Bypass Capacitor Connecting Pattern Connecting Pattern Bypass Capacitor Connecting Pattern Connecting Pattern M16C/62P Group (M16C/62P, M16C/62PT) VSS VSS VCC2 VCC1

M16C/62P Group (M16C/62P , M16C/62PT) 25. Di fferences Depending on Manufacturing Period Rev.2.41 Jan 10, 2006 Page 383 of 390 REJ09B0185-0241 25. Differences Depending on Manufacturing Period Table 25.1 and Table 25.2 list the precautions are applicable or not applicable every chip version of M16C/62P flash and ROM external versions. Contact separately about the mask ROM version. √ : Applies − : Dose not apply Table 25.1 Technical Update Applicable Table of M16C/62P Flash and ROM External Versions (1) Precaution Chip Version TECHNICAL UPDATEABC Ensure that RESET must hold valid-low state during power-on. When using a reset IC, use a CMOS type IC. When using an open-drain type reset IC, insert a capacitor between the reset input and VSS. Adjust the R-C time constant between the capacitor and pull-up resistor at least 10 times longer than the VCC rising time. √−− If UART0 or UART1 are used as a slave in the I2C mode, P6_1 or P6_5 are placed in a high-impedance state. P6_1 or P6_5 cannot be used as an output port even if the PD6_1 or PD6_5 bits in the PD6 register are set to “1” (output mode). Therefore, set the PD6_1 or PD6_5 bits to “0” (Input mode). Do not enter wait mode when the main clock or on-chip oscillator clock is selected as the CPU clock of which division is set by the CM06 bit in the CM0 register, and the CM16 and CM17 bits in the CM1 register. Precaution 1.1 The CM05 bit in the CM0 register is set to “0” (main clock oscillation) and the CM02 bit is set to “1” (peripheral function clock stops in wait mode). Precaution 1.2 Do not generate an NMI interrupt after entering mode. √−− TN-M16C-108-0309 Precaution 1.3 Do not generate a voltage detection interrupt after entering mode. √−− TN-M16C-108-0309 Precaution 1.4 I/O ports (P0 to P5) will be indeterminate until internal power supply is stable, such as when the power is turned on, if “H” is applied to the CNVSS pin and “L” to the RESET pin while internal power supply is unstable. Precaution 1.1 I/O ports (P6 to P14) will be indeterminate until internal power supply is stable, such as when the power is turned on, if “H” is applied to the CNVSS pin and “L” to the RESET pin while internal power supply is unstable. Precaution 1.1 When the RESET pin is “L” in boot mode (apply “H” to the CNVSS pin and P5_0 (CE), and “L” to the P5_5 (EPM)), internal pull-up is enabled for P10_0 to P10_3, P11_0 to P11_7, P12_5 to P12_7, P13_0 to P13_7, P14_0 and P14_1 and so become “H” level. Precaution 1.2 P0_0 to P0_7 and P1_0 to P1_7 may become indeterminate when P8_4 is “H” and the RESET pin is “L” in boot mode (apply “H” to the CNVSS pin and P5_0 (CE), and “L” to P5_5 (EPM)). P0_0 to P0_7 and P1_0 to P1_7 are in a high impedance state when the RESET pin and P8_4 are “L”. Precaution 1.3

M16C/62P Group (M16C/62P , M16C/62PT) 25. Di fferences Depending on Manufacturing Period Rev.2.41 Jan 10, 2006 Page 384 of 390 REJ09B0185-0241 √ : Applies − : Dose not apply Table 25.2 Technical Update Applicable Table of M16C/62P Flash and ROM External Versions (2) Precaution Chip Version TECHNICAL UPDATEABC When supplying power to the microcomputer, the power supply voltage applied to the VCC1 pin must meet the conditions of SVCC. Do not set the CM10 bit in the CM1 register to 1 (stop mode) with setting the VC13 bit in the VCR1 register to 1 (VCC1 ≥Vdet 4) when a low voltage detection interrupt in the voltage detection circuit is used under the following settings:

• the VC27 bit in the VCR2 register to 1 (low voltage detection circuit enabled)
• the D40 bit in the D4INT register to 1 (low voltage detection interrupt enabled)
• the D41 bit to 1 (use low voltage detection interrupt to exit stop mode) Precaution 1.1 Do not generate the NMI interrupt after setting the CM10 bit in the CM1 register to “1” (stop mode) and entering stop mode. ÷-- TN-M16C-107-0309 Precaution 1.2 Do not set the CM10 bit in the CM1 register to “1” (stop mode) when the microcomputer is in low-speed mode under the following settings:
• the CM04 bit in the CM0 register is set to “1” (sub clock oscillation)
• the CM07 bit in the CM0 register is set to “1” (sub clock) Precaution 1.3 When using the sub clock (XCIN-XCOUT) as the CPU clock (BCLK) or as the timer count source, DO NOT leave the CM03 bit set to “1” (XCINXCOUT drive capacity “HIGH” ). ÷ ÷ - TN-M16C-119A/EA

M16C/62P Group (M16C/62P , M16C/62PT) Appendix 1. Package Dimensions Rev.2.41 Jan 10, 2006 Page 385 of 390 REJ09B0185-0241 Appendix 1.Package Dimensions DO NOT INCLUDE MOLD FLASH. NOTE) DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. DetailF c A A1 A2 L Index mark y x F 1 38 65102 103 128 ZE ZD D HD E HE bp ZE ZD bp HE HD y 0.10 e 0.5 c 0° 8° x L 0.35 0.5 0.65 0.05 0.125 0.2 A 1.7 15.8 16.0 16.2 21.8 22.0 22.2 A2 1.4 E 13.9 14.0 14.1 D 19.9 20.0 20.1 Reference Symbol Dimension in Millimeters Min Nom Max 0.17 0.22 0.27 0.09 0.145 0.20 0.10 0.75 0.75 0.20 0.125 1.0 P-LQFP128-14x20-0.50 0.9g MASS[Typ.] 128P6Q-APLQP0128KB-A RENESAS CodeJEITA Package Code Previous Code Terminal cross section c bp e 0.80.5 0.825 0.575 ZE ZD bp HE HD y 0.10 e 0.65 c 0° 10° L 0.4 0.6 0.8 0 0.1 0.2 A 3.05 16.5 16.8 17.1 22.5 22.8 23.1 A2 2.8 E 1 3 . 81 4 . 01 4 . 2 D 19.8 20.0 20.2 Reference Symbol Dimension in Millimeters Min Nom Max 0.25 0.3 0.4 0.13 0.15 0.2 P-QFP100-14x20-0.65 1.6g MASS[Typ.] 100P6S-APRQP0100JB-A RENESAS CodeJEITA Package Code Previous Code y Index mark 100 80 51 301 F ZE ZD e bp A HD D E HE c Detail F A1 A2 L INCLUDE TRIM OFFSET. DIMENSION "*3" DOES NOT NOTE) DO NOT INCLUDE MOLD FLASH.

M16C/62P Group (M16C/62P , M16C/62PT) Appendix 1. Package Dimensions Rev.2.41 Jan 10, 2006 Page 386 of 390 REJ09B0185-0241 Terminal cross section bp c DO NOT INCLUDE MOLD FLASH. NOTE) DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. y Index mark x 12 5 5175 100 F ZE ZD E D HD HE bp Detail F A2A1 L A c ZE ZD bp HE HD y0 . 0 8 e 0.5 c 0° 8° x L 0.35 0.5 0.65 0.05 0.1 0.15 A1 . 7 15.8 16.0 16.2 15.8 16.0 16.2 A2 1.4 E 1 3 . 91 4 . 01 4 . 1 D 1 3 . 91 4 . 01 4 . 1 Reference Symbol Dimension in Millimeters Min Nom Max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 Previous CodeJEITA Package Code RENESAS Code PLQP0100KB-A 100P6Q-A / FP-100U / FP-100UV MASS[Typ.] 0.6gP-LQFP100-14x14-0.50 e 60 41 201 F Index mark y ZE ZD c bpe A E HE D HD Detail F L A2A1 INCLUDE TRIM OFFSET. DIMENSION "*3" DOES NOT NOTE) DO NOT INCLUDE MOLD FLASH. 0.80.5 0.825 0.825 ZE ZD Previous CodeJEITA Package Code RENESAS Code PRQP0080JA-A 80P6S-A MASS[Typ.] 1.1gP-QFP80-14x14-0.65 0.20.150.13 0.40.30.25 MaxNomMin Dimension in Millimeters Symbol Reference 14.214.013.8D 14.214.013.8E 2.8A2 17.116.816.5 17.116.816.5 3.05A 0.20.10 0.80.60.4L 10°0° c 0.65e 0.10y HD HE bp

M16C/62P Group (M16C/62P , M16C/62PT) Appendix 2. Difference between M16C/62P and M16C/30P Rev.2.41 Jan 10, 2006 Page 387 of 390 REJ09B0185-0241 Appendix 2. Difference between M16C/62P and M16C/30P NOTES: 1. About the details and the electric characteristics, refer to hardware manual. Appendix Table 2.1 Function Difference (1) (1) Item M16C/62P M16C/62A Shortest instruction execution time 41.7ns (f(BCLK)=24MHz, VCC1=3.0 to 5.5V) 100ns (f(BCLK)=10MHz, VCC1=2.7 to 5.5V) 62.5ns (f(XIN)=16MHz, VCC=4.2V to 5.5V) 100ns (f(XIN)=10MHz, VCC=2.7V to 5.5V with software one-wait) Supply voltage VCC1=3.0 to 5.5V, VCC2=3.0V to VCC1 (f(BCLK)=24MHz) VCC1=VCC2=2.7 to 5.5V (f(BCLK)=10MHz) VCC=4.2V to 5.5V (f(XIN)=16MHz, without software wait) VCC=2.7V to 5.5V (f(XIN)=10MHz, with software one-wait) I/O power supply Double (VCC1, VCC2) Single (VCC) Package 80-pin, 100-pin, 128-pin plastic mold QFP 80-pin, 100-pin plastic mold QFP Voltage detection circuit Built-in Vdet3, Vdet4 detect Voltage down detect interrupt Hardware reset 2 None Clock Generating Circuit PLL, XIN, XCIN, on-chip oscillator When placed in low power mode, a divide- by-8 value is used for these clocks. The XIN drive capability is set to HIGH. XIN, XCIN When placed in low power mode, the divide-by-n value for the main clock does not change. Nor does the XIN drive capability change. System clock protective function Built-in None (protected by protect register) Oscillation Stop, Re-oscillation Detection Function Built-in None Low power consumption 18mA (VCC1=VCC2=5V, f(BCLK)=24MHz) 8mA (VCC1=VCC2=3V, f(BCLK)=10MHz) 1.8µA (VCC1=VCC2=3V, f(XCIN)=32kHz, when wait mode) 32.5mA (VCC=5V, f(XIN)=16MHz) 8.5mA (VCC=3V, f(XCIN)=10MHz with software one-wait) 0.9µA (VCC=3V, f(XCIN)=32kHz, when wait mode) Memory Area Memory area expandable (4 Mbytes)

1 Mbytes fixed

04000h to 07FFFh(PM13=0) 08000h to 0FFFFh(PM10=0) 10000h to 26FFFh 28000h to 7FFFFh 80000h to CFFFFh(PM13=0) D0000h to FFFFFh(Microprocessor mode) 04000h to 05FFFh(PM13=0) 06000h to CFFFFh D0000h to FFFFFh(Microprocessor mode) Upper address in memory expansion mode and microprocessor mode P4_0 to P4_3 (A16 to A19), P3_4 to P3_7 (A12 to A15) : Switchable between address bus and I/O port P4_0 to P4_3 (A16 to A19) : Switchable between address bus and I/O port A12 to A15 : No switchable Access to SFR Variable (1 to 2 waits) 1 wait fixed Software wait to external area Variable (0 to 3 waits) Variable (0 to 1 wait) Protect Can be set for PM0, PM1, PM2, CM0, CM1, CM2, PLC0, INVC0, INVC1, PD9, S3C, S4C, TB2SC, PCLKR, VCR2, D4INT registers Can be set for PM0, PM1, CM0, CM1, PD9, S3C, S4C registers Watchdog timer Watchdog timer interrupt or watchdog timer reset is selected Count source protective mode is available Watchdog timer interrupt No count source protective mode Address match interrupt

M16C/62P Group (M16C/62P , M16C/62PT) Appendix 2. Difference between M16C/62P and M16C/30P Rev.2.41 Jan 10, 2006 Page 388 of 390 REJ09B0185-0241 NOTES: 1. About the details and the electric char acteristics, refer to hardware manual. Appendix Table 2.2 Function Difference (1) (1) Item M16C/62P M16C/62A Timers A, B count source Selectable: f1, f2, f8, f32, fC32 Selectable: f1, f8, f32, fC32 Timer A two-phase pulse signal processing Function Z-phase (counter reset) input No function Z-phase (counter reset) input Timer functions for three-phase motor control Function protect by protect register Count source is selected: f1, f2, f8, f32, fC32 Dead time timer count source is selected: f1, f1 divided by 2, f2, f2 divided by 2 Three-phase output forcible shutoff function based on NMI input is available, output polarity change, carrier wave phase detection. Function protect by protect register Count source is selected: f1, f8, f32, fC32 Dead time timer count source is fixed at f1 divided by 2 Serial I/O (UART0 to UART2) (UART, clock synchronous, I 2C bus, IEBus) x 3 (UART, clock synchronous) x 2 (UART, clock synchronous, I2C bus, IEBus) x 1 UART0 to UART2, SI/O3, SI/O4 count source Select from f1SIO, f2SIO, f8SIO, f32SIO Select from f1, f8, f32 Serial I/O RTS timing Assert low when receive buffer is read Assert low when reception is completed UART0 to UART2 Overrun Error Generation Timing This error occurs if the serial I/O started receiving the next data before reading the UiRB register (i=0 to 2) and received the 7 th bit of the next data (clock synchronous) This error occurs if the serial I/O started receiving the next data before reading the UiRB register and received the bit one before the last stop bit of the next data (UART) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out CTS /RTS separate function Have None UART2 data transmit timing After data was written, transfer starts at the 2nd BRG overflow timing (same as UART0 and UART1) After data was written, transfer starts at the 1st BRG overflow timing (Output starts one cycle of BRG overflow earlier than UART0 and UART1) Serial I/O sleep function None Have Serial I/O I 2C mode Start condition, stop condition: Auto-generationable Start condition, stop condition: Not auto-generationable Serial I/O I2C mode SDA delay Only digital delay is selected as SDA delay SDA digital delay count source: BRG Analog or digital delay is selected as SDA delay SDA digital delay count source: 1/ f(XIN) SI/O3, SI/O4 clock polarity Selectable Fixed A/D Converter 10 bits X 8 channels Expandable up to 26 channels 10 bits X 8 channels Expandable up to 10 channels A/D converter operation clock Selectable: fAD, fAD divided by 2, 3, 4, 6, 12 Selectable: fAD, fAD/2, fAD/4 A/D Converter Input Pin Select from por ts P0, P2, P10 Fixed at port P10

M16C/62P Group (M16C/62P , M16C/62PT) Appendix 2. Difference between M16C/62P and M16C/30P Rev.2.41 Jan 10, 2006 Page 389 of 390 REJ09B0185-0241 NOTES: 1. About the details and the electric char acteristics, refer to hardware manual. Appendix Table 2.3 Function Difference (1) (1) Item M16C/62P M16C/62A User ROM blocks 14 blocks: 4 Kbytes x 3, 8 Kbytes x 3,

32 Kbytes x1, 64 Kbytes x 7

(Flash memory: max. 512 Kbytes) 7 blocks: 8 Kbytes x 2, 16 Kbytes x1,

32 Kbytes x 1, 64 Kbytes x 3

(Flash memory: max. 256 Kbytes) Program manner Word Page Program command (software command) Page program command: none Program command: have (program method: in units of word, in units of byte) Page program command: have Program command: none (program method: in units of page) Block status after program function None Have CPU rewrite mode EW1 mode is available No EW1 mode

Rev.2.41 Jan 10, 2006 Page 390 of 390 REJ09B0185-0241 M16C/62P Group (M16C/62P , M16C/62PT) Register Index A B C D F I K O P R S T U V W Register Index

REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual Rev. Date 1.0 Jan 31, 2003 1 Applications are partly revised. 2 Table 1.1.1 is partly revised. 5 Table 1.1.3 is partly revised. Figure 1.1.2 is partly revised. 11 Explanation of “Memory” is partly revised. 20 Explanation of “Hardware Re set 1” is partly revised. 21 Figure 1.5.1 is partly revised. 22 Figure 1.5.2 is partly revised. 24 Figure 1.5.4 is partly revised. 25 VCR2 Register in Figur e 1.5.6 is partly revised. 26 Figure 1.5.6 is partly revised. 27 Explanation of “Power Supply Down De tection Interrupt” is partly revised. 30 Figure 1.6.1 is partly revised. 31 Figure 1.6.2 is partly revised. 39 Table 1.7.5 is partly revised. 41 Table 1.7.7 is partly revised. 43 Figure 1.7.8 is partly revised. 44 Explanation of “4 Mbyte Mode” is partly revised. 53 Notes 12 and 13 in Figure 1.9.2 is partly revised. 54 Notes 2 and 5 in Figure 1.9.3 is partly revised. 55 Figure 1.9.4 is partly revised. 57 Note 4 in Figure 1.9.6 is partly revised. 60 Explanation of “PLL Clock” is partly revised. 61 Figure 1.9.9 is partly revised. 62 Explanation of “CPU Clock and BCLK” is partly revised. 63 Explanation of “Low-speed Mode” is partly revised. Explanation of “Low Power Dissipation Mode” is partly revised. 64 Explanation of “Low Power Diss ipation Mode” is partly revised. Explanation of “On-chip Oscillator Low Power Dissipation Mode” is partly revised. Table 1.9.3 is partly revised. 65 Table 1.9.5 is partly revised. 68 Figure 1.9.10 is partly revised. 69 Figure 1.9.11 is partly revised. 70 Table 1.9.7 is added. 71 Explanation of “System Clock Protec tive Function” is partly revised. 77 Explanation of “Power Supply Down De tection Interrupt” is partly revised. 78 Table 1.11.1 is partly revised.

REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual Rev. Date 88 Figure 1.11.9 is partly revised. 96 WDTS Register in Figure 1.12.2 is partly revised. 99 Figure 1.13.2 is partly revised. 100 Figure 1.13.3 is partly revised. 103 Figure 1.13.5 is partly revised. 104 Table 1.13.3 is partly revised. 105 Explanation of “DMA Enable” is partly revised. 109 Figure 1.14.3 is partly revised. 115 Table 1.14.5 is partly revised.

117 Explanation of “Counter Initia lization by Two-Phase Pulse Signal

Processing” is partly revised. 117 Figure 1.14.10 is partly revised. 122 Figure 1.14.14 is partly revised. Figure 1.14.15 is partly revised. 124 Figure 1.15.3 is partly revised. 128 Figure 1.15.7 is partly revised. 128 Figure 1.15.8 is partly revised. 130 Figure 1.16.1 is partly revised. 132 Figure 1.16.3 is partly revised. 134 Note 7 is added to TAi, TAi1 Register in Figure 1.16.5. 137 Figure 1.16.8 is partly revised. 146 UiSMR2 Register in Figure 1.17.7 is partly revised. 163 Figure 1.20.1 is partly revised. 164, 169 Figure 1.20.4 is partly revised. Explanation of “Arbitration” is partly revised. 170 Explanation of “Transfer Clock” is partly revised. 171 Explanation of “ACK and NACK” is partly revised. 179 Explanation of “Special Mode 4 (SIM Mode)” is partly revised. Table 1.20.9 is partly revised. 184 Figure 1.21.1 is partly revised. 187 Figure 1.21.4 is partly revised.

203 Explanation of “External Operation Amp Connection Mode” is partly

revised. 205 Explanation of “Caution of Usin g A/D Converter” is partly revised. Figure 1.22.11 is partly revised 206 Table 1.23.1 is partly revised. 207 Figure 1.23.3 is partly revised.

REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual 218 Figure 1.25.9 is partly revised. 223 Table 1.26.1 is partly revised. 224 Table 1.26.2 is partly revised. 225 Note 1 of Table 1.26.3 is partly revised. Note 1 of Table 1.26.4 is partly revised. Table 1.26.6 is partly revised. 227 Note 1 of Table 1.26.9 is partly revised. 228 Note 1 of Table 1.26.10 is partly revised. 229 Measurement conditions of timing requirements are partly revised. Table 1.26.11 is partly revised. 230 Measurement conditions of timing requirements are partly revised. 230 Table 1.26.18 is added. 231 Measurement conditions of timing requirements are partly revised. 232 Measurement conditions of switchi ng characteristics are partly revised. 233 Measurement conditions of switchi ng characteristics are partly revised. 234 Measurement conditions of switchi ng characteristics are partly revised. 235 Figure 1.26.2 is partly revised. 242 Figure 1.26.9 is partly revised. 244 Note of Table 1.26.28 is partly revised. 245 Figure 1.26.29 is partly revised. 246 Measurement conditions of timing requirements are partly revised. Table 1.26.30 is partly revised. 247 Measurement conditions of timing requirements are partly revised. 247 Table 1.26.37 is added. 248 Measurement conditions of timing requirements are partly revised. 249 Measurement conditions of switchi ng characteristics are partly revised. 250 Measurement conditions of switchi ng characteristics are partly revised. 251 Measurement conditions of switchi ng characteristics are partly revised. 252 Figure 1.26.12 is partly revised. 255 Figure 1.26.15 is partly revised. 256 Figure 1.26.16 is partly revised. 257 Figure 1.26.17 is partly revised. 258 Figure 1.26.18 is partly revised. 259 Figure 1.26.19 is partly revised. 260 Figure 1.26.20 is partly revised. 262 Explanation of “Memory Map” is partly revised. 263 Explanation of “Boot Mode” is partly revised. 264 Figure 1.27.3 is partly revised. 268 Note of FIDR Register in Figure 1.27.4 is partly revised. Rev. Date

REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual 271 Figure 1.27.7 is partly revised. 272 Explanation of “Interrupts” is partly revised. Explanation of “Writing in the User ROM Space” is partly revised. 274 Table 1.27.4 is partly revised. Explanation of “Read Array Command” is partly revised. 278 Explanation of “Program Command” is partly revised. 287 Figure 1.27.15 is partly revised. 293 Partly revised. 1.10 May 28, 2003 2 Table 1. 1.1 is partly revised. 14-19 SFR is partly revised. Note 1 is partly revised. 20 Explanation of “Hardware Re set 1” is partly revised. 23 Note 1 is added. 24 Figure 1.5.4 is partly revised. Note 1 of Figure 1.5.5 is partly revised. 26 Figure 1.5.7 is partly revised. 27 Table 1.5.2 is partly revised. Table 1.5.3 is partly revised. Explanation of “1. Limitations on Stop Mode” is partly revised. 28 Explanation of “1. Limitations on WAIT instruction” is partly revised. Figure 1.5.8 is partly revised. 31 Note is added. 33 Explanation of “Multiplexed Bus” is revised. 34 Explanation of “(2) Data Bus” is revised. 38 Explanation of “(7) Hold Signal” is revised. Note 3 of Table 1.7.4 is added. 39 Note 4 of Table 1.7.5 is added. 40 Explanation of “(10) Software Wait” is revised. 41 Table 1.7.7 is revised. 46 Table of Figure 1.8.5 is revised. 47 Explanation is revised. 51 Explanation of “Clock Generation Circuit” is revised. 52 Figure 1.9.1 is revised. 53 Note of Figure 1.9.2 is revised. 55 Note 12 is added. 58 Explanation of “(1) Main clock” is partly revised. 60 Explanation of “(4) PLL Clock” is partly revised. Rev. Date

REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual 63 Explanation of “Low power Dissipation Mode” is partly revised. 64 Explanation of “Entering Wait mode” is partly revised. 66 Explanation of “(3) Stop Mode” is partly revised. 69 Note 9 is added. 70 Table 1.9.7 is revised. 75 Figure 1.11.1 is revised. 79 Note 6 is added. 83 Note 2 is added to Figure 1.11.4. 84 Table 1.11.5 is partly revised. 85 Figure 1.11.6 is partly revised. 86 Figure 1.11.8 is partly revised. 89 Notes 1 to 2 is added to IFSR register of Figure 1.11.4. 91 Explanation of “Address Match Interrupt” is partly revised. 93-94 Notes are deleted. (All notes are indicated in “M16C/62 GROUP (M16C/ 62P) USAGE NOTES”). 93 Explanation of “Watchdog Timer” is partly revised. 94 A formula is added. 104 Explanation of “Channel Priority Transfer Timing” is partly revised. 109 TRGSR register of Figure 1.14.6 is partly revised. 116 Table 1.14.4 is partly revised. 117 Figure 1.14.12 is partly revised. 129 Figure 1.16.2 is partly revised. 130 Figure 1.16.3 is partly revised. 143 U0SMR to U2SMR of Figure 1.17.6 is partly revised. 144 U0SMR2 to U2SMR2 of Figure 1.17.7 is partly revised. 154,162, 175 161 Figure 1.20.1 is partly revised. 164 Table 1.20.4 is partly revised. Notes 5 to 7 is added. 166 Explanation of “Output of Start and Stop Condition” is partly revised. 177 Note 2 is added to Table 1.20.9. 178 “ −” of U2BRG of Table 1.20.10 is changed into “0 to 7”. 179 Figure 1.20.10 is revised. 183 Note of SiC register of Figure 1.21.2 is partly revised. 187 Note 2 of Table 1.22.1 is revised. 188 Figure 1.22.1 is partly revised. 190 Table of ADCON2 register of Figure 1.22.3 is partly revised. 202 The value of a capacitor of Figure 1.22.10 is changed. Rev. Date

REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual 202 Notes are deleted. (All notes are indicated in “M16C/62 GROUP (M16C/ 62P) USAGE NOTES”). 208- 212 219 Figure 1.25.12 is partly revised. 222 Table 1.26.3 is partly revised. 223 Table 1.26.5 is partly revised. Table 1.26.6 is added. 224 Table 1.26.9 is partly revised. 230 Notes 1 and 2 in Table 1.26.26 is partly revised. 231 Notes 1 in Table 1.26.27 is partly revised. 230- 231 Note 3 is added to “Data output hold time (refers to BCLK)” in Table 232 Note 4 is added to “th(ALE-AD)” in Table 1.26.28. 230- 232 Switching Characteristics is partly revised. 236- 239 240- 241 th(ALE-AD), th(WR-CS), th(WR-DB) and th(WR-AD) in Figure 1.26.9 to 1.5.10 is partly revised. 242 Note 2 is added to Table 1.26.29. 247 Notes 1 and 2 in Table 1.26.45 is partly revised. 248 Notes 1 in Table 1.26.46 is partly revised. 247- 248 Note 3 is added to “Data output hold time(refers to BCLK)” in Table 1.26.45 and 1.26.46 249 Note 4 is added to “th(ALE-AD)” in Table 1.26.47. 247- 249 Switching Characteristics is partly revised. 253- 256 257- 258 th(ALE-AD), th(WR-CS), th(WR-DB) and th(WR-AD) in Figure 1.26.19 to 1.5.20 is partly revised. 259 Table 1.27.1 is partly revised. Notes 3 and 4 is added. 260 Notes 1 and 2 is added to Table 1.27.2. 264 Note 2 is added to Table 1.27.3. 267 Notes 1 and 3 of FMR0 register of Table 1.27.4 is partly revised. 268 Figure 1.27.5 is partly revised. Note 2 is added. 270 Figure 1.27.7 is partly revised. 277 Figure 1.27.11 is partly revised. 281 Figure 1.27.12 is partly revised. Rev. Date

REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual 283 Table 1.27.7 is partly revised. 284- 286 287- 288 292- 293 Difference in Mask ROM Version and Flash Memory Version is revised. 294 Difference in Flash Memory Version is revised. 1.11 Jun 20, 2003 259 Number of program and er asure in Table 1.26.27 is partly revised. 1.20 Sep 11, 2003 94 Figure 1.12.2 is revised. 2.30 Sep 01, 2004 − Since high reliability version is added, a group name is revised. M16C/62P Group (M16C/62P) M16C/62P Group (M16C/62P, M16C/ 62PT) 2-4 Table 1.1 to 1.3 are revised. Note 3 is partly revised. 6 Figure 1.2 Note5 is deleted. 7-9 Table 1.4 to 1.7 Product List is partly revised. 11 Table 1.8 and Figure 1.4 are added. 12 Table 1.9 and Figure 1.5 are added. 13-16 Figure 1.6 to 1.9 ZP is added. 17 Table 1.10 and 1.13 ZP is added to timer A. 18, 20 Table 1.11 to 1.13 are revised. 19, 21 Table 1.12 to 1.14 are revised. 24 Figure 3.1 is partly revised. Note 3 is added. 25 Note 6 is added. 30 After Reset of D/A register 0, 1 are revised. 31 5.2 Voltage Down Detection Reset (Hardware Reset 2) is revised. 32 Figure 5.1 is partly revised. 35 Figure 6.1 is partly revised. 36 Figure 6.2 is revised. 37 Figure 6.3 is revised. 39 Figure 6.4 is revised. 40 6.2 Limitations on Exiting Stop Mode and 6.3 Limitations on Exiting Wait Mode are revised. 41 Note in 7. Processor is added. 44 Figure 7.2 is partly revised. 46 Note in 8. Bus is added.

8.1.2.2 When the input level on BYTE pin is low (16-bit data bus) is

revised. Rev. Date

REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual 297 Table 23.30 is revised. 298 Table 23.32 is partly revised. 300 Table 23.43 is partly revised. 301 Figure 23.12 is partly revised. Table 23.45 is partly revised. 302 Table 23.46 is partly revised. 303 Table 23.47 is partly revised. 304 Figure 23.13 is partly revised. 307- 308 Figure 23.16 to 23.17 is partly revised. 309- 310 Figure 23.18 to 23.19 is partly revised. 313- 339 23.2 Electrical Characteristics (M16C/62PT) is added. 340 24.1 Reset is added. 341 24.2 External Bus is partly revised. 342 Figure 24.2 is added. 343 24.4 Power Control is partly revised. 346 24.9.2.1 Special Mode (I 2C mode) is added. 347 24.9.3 SI/O3, SI/O4 is added. 348- 349 24.10 A/D Converter is partly revised. 352 24.13 Mask ROM Version is added. 356 24.15 Noise is added. 357 25. Differences Depending on Manufacturing Period is a

2.40 Dec 15, 2005 - voltage down detection reset -> brown-out detection Reset

2-4 Tables 1.1 to 1.3 Performance outline of M16C/62P group are partly revised. 7 Table 1.4 Product List (1) is partly revised. Note 1 is added. 8 Table 1.5 Product List (2) is partly revised. Note 1 and 2 are added. 9 Table 1.6 Product List (3) is partly revised. Note 1 and 2 are added. 10 Table 1.7 Product List (4) is partly revised. Note 1 and 2 are added. 11 Figure 1.3 Type No., Memory Size, and Package is partly revised 12 Table 1.8 Product Code of Flash Memory version and ROMless version for M16C/62P is partly revised. 13 Table 1.9 Product Code of Flash Memo ry version for M16C/62P is partly revised. Rev. Date

REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual 125 13.1 Cold Start / Warm Start moved to 5. Reset. 127 Table 14.1 DMAC Specificat ions is partly revised. 132 14.1.3 Effect of Software Wait is partly revised. 165 Table 16.1 Three-phase Motor Control Timer Functions Specifications is partly revised. 167 Notes 5 and 7 of Figure 16.2 INVC0 Register are partly revised. 177- 179 Figures 17.1 to 17.3 UART Block Diagram are partly revised. 181 Note 3 of Figure 17.5 UiRB Register is added. 186 Figure 17.10 UCON and UiSMR Registers Notes 3 is revised. 188 Table 17.1 Clock Synchronous Serial I/O Mode Specifications is partly revised. Note 2 is partly revised. 192 Figure 17.13 Transmit and Re ceive Operation is revised. 193 17.1.1.1 Counter Measure for Comm unication Error Occurs is partly revised. 197 Table 17.5 UART Mode Specif ications is partly revised. Note 1 is partly revised 200 Figure 17.19 Transmit Operation is revised. 201 17.1.2.1 Bit Rate is partly revised. Table 17.9 Example of Bit Rates and Settings is partly revised. 202 17.1.2.2 Counter Measure for Comm unication Error Occurs is partly revised. 205 Table 17.10 I 2C Mode Specifications is partly revised. 207 Note 4 of Table 17.11 Registers to Be Used and Settings in I 2C Mode (1) is added. 215 Table 17.15 Special Mode Specifications is partly revised. 222 Table 17.18 SIM Mode Specific ations is partly revised. 224 Figure 17.34 Transmit and Receive Timi ng in SIM Mode is partly revised. 226 17.1.6.2 Format is partly revised. 230 Table 17.20 SI/O3 and SI/O4 Spec ifications is partly revised. 231 Figure 17.41 SI/Oi Operatio n Timing is partly revised. Figure 17.42 Polarity of Transfer Clock is partly revised. 232 17.2.3 Functions for Settings an SOUTi Internal Value is partly revised. 249 18.2.6 Output Impedance of Sensor under A/D Conversion is partly revised. 250 Figure 18.11 Analog Input Pin and Exte rnal Sensor Equivalent Circuit is partly revised. 251 Table 19.1 D/A Converter Performance is partly revised. Rev. Date

REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual 252 Figure 19.2 DA0 and DA1 Re gister is partly revised. Note 2 of Figure 19.3 D/A Converter is added. 254 Figure 20.3 CRC Calculation is partly revised. 261 Note 2 of Figure 21.6 I/O Pin is deleted. 270 Table 22.1 Flash Memory Version Sp ecifications is partly revised. 274 Figure 22.2 ROMCP Register is partly revised. 275 Note 1 of Table 22.3 EM0 Mode and EW1 Mode is partly revised. 276 22.3.2 EW1 Mode is partly revised. 279 22.3.3.4 FMSTP Bit is partly revised. 283 Figure 22.9 Processing Before and After Low Power Dissipation mode is partly revised. 285 22.3.4.12 Low- Power Consumption Mode and On-chip Oscillator Low- power Consumption Mode is partly revised. 288 22.3.5.5 Block Erase Command is partly revised. Figure 22.11 Block Erase Command is partly revised. 292 Table 22.5 Status Register is partly revised. 294 Figure 22.14 Full Status Check and Handling Procedure for Each Error is partly revised. 297 Table 22.7 Pin Functions (Flash Memory Standard Serial I/O Mode) is partly revised. Note 2 is partly revised. Note 3 is added. 297- 300 Figures 22.15 to 22.18 are partly revised. 301 Figure 22.19 Circuit Application in Standard I/O Mode 1 is partly revised. 302 Figure 22.20 Circuit Application in Standard I/O Mode 2 is partly revised. 307 Table 23.4 A/D Conversion Characteristics is partly revised. 309 Table 23.6 Flash Memory Version El ectrical Characteristics for 100 cycle products is partly revised. Table 23.7 Flash Memory Version Electrical Characteristics for 10,000 cycle products is partly revised. Table 23.8 Flash Memory Version Program / Erase Voltage and Read Operation Voltage Characteristics is partly revised. 310 Table 23.9 Low Voltage Detection Circ uit Electrical Characteristics is partly revised. 311 Figure 23.1 Power Supply Circuit Timing Diagram is partly revised. 313 Table 23.12 Electrical Characteristics (2) is partly revised. 314 Note 1 of Table 23.13 External Clock Input (XIN input) is added. 331 Notes 1 to 4 of Table 23.32 External Clock Input (XIN input) are added. 349 Table 23.53 Flash Memory Version Electrical Characteristics for 100 cycle products is partly revised. Standard (Min.) is partly revised. Rev. Date

REVISION HISTORY M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual 349 Table 23.54 Flash Memory Version El ectrical Characteristics for 10,000 cycle products is partly revised. Standard (Min.) is partly revised. Note 5 is revised. Table 23.55 Flash Memory Version Program / Erase Voltage and Read Operation Voltage Characteristics is partly revised. 352 359 Table 23.58 Electrical Characteristics is partly revised. 24.1 SFR and 24.1.1 Register Settings, Table 24.1 Registers with Write- only Bits are added. 360 363 Figure 24.1 Timing of SV CC is revised. 24.5 Power Control is revised. 375 Figure 24.4 Use of Capacitors to Reduce Noise is partly revised. 375 24.11 A/D Converter is partly revised. 377 24.12 Programable I/O Ports is partly revised. 379 24.15.2 Stop mode is partly revised. 380 24.15.8 Operation speed is partly revised. 381 24.15.14 Regarding Programming/ Erasing Endurance and Execution Time is partly revised. (Title change.) 383 Table 25.1 Technical Update Applic able of M16C/62P Flash and ROM External Versions is partly revised.

2.41 Jan 10, 2006 - voltage down detec tion -> low voltage detection

Figure 10.10 State Transition to Stop Mode and Wait Mode is partly revised. 100 Figure 10.11 State Transition in No rmal Operating Mode is partly revised. 132 14.1.3 Effect of Software Wait is partly revised. 186 Figure 17.10 UCON and UiSMR Registers Notes 4 is added. Bit3(LSYN) is added. 252 Figure 19.3 D/A Converter Equiva lent Circuit is partly revised. Rev. Date

M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual Publication Date : Rev.2.41 Jan 10, 2006 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2006. Renesas Technology Corp., All rights reserved. Printed in Japan

2-6-2, Ote-machi, Chiyoda-ku, Tokyo,100-0004, Japan M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual