M16C21E8MC-AXXXFP

M30218 RENESAS | Alldatasheet

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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description

Description

The M30218 group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. They also feature a built-in multiplier and DMAC, making them ideal for controlling musical instruments, house- hold appliances and other high-speed processing applications. The M30218 group includes a wide range of products with different internal memory types and sizes and various package types.

Features

• Shortest instruction execution time.100ns (f(X IN)=10MHz) 2.7V to 5.5V (f(XIN)=3.5MHz)(Note) (high-breakdown-voltage P-channel open-drain output : 52pins) 1 channels for clock synchronous (max.256 bytes automatic transfer function) (built-in feedback resistor, and external ceramic or quartz oscillator) Note: Only mask ROM version.

Applications

Household appliances, office equipment, Audio etc.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description Pin Configuration Figures AA-1 show the pin configurations (top view). PIN CONFIGURATION (top view) FigureAA-1. Pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 515253545556575859606162636465666768697071727374757677787980 100 M30218MC-AXXXFP P60/FLD0 P61/FLD1 P62/FLD2 P63/FLD3 P64/FLD4 P65/FLD5 P66/FLD6 P67/FLD7 0/FLD8 V CCX IN RESET X OUTV SS CNV SS 6/X COUT 7/X CIN 0/SRDY2 6/TA3 IN /TA1 OUT /CLK1 7/TA4 IN /TA2 OUT /CTS1/RTS1/CLKS1 4/S OUT 5/SCLK21 6/DA1/SCLK22 7/DA0/CLK OUT /DIM OUT 2/SSTB2P9 3/S IN2 3/TA0 IN /TA3 OUT 2/TB2 IN 1/SBUSY2 Package:100P6S-A VEE P107/AN7 P106/AN6 P105/AN5 P103/AN3 P102/AN2 P104/AN4 P101/AN1 AV SS P100/AN0 VREF AV CC 1/FLD9 2/FLD10 3/FLD11 4/FLD12 5/FLD13 6/FLD14 7/FLD15 0/FLD16 1/FLD17 2/FLD18 3/FLD19 4/FLD20 5/FLD21 6/FLD22 V SS 7/FLD23 V CC 0/FLD24 1/FLD25 2/FLD26 3/FLD27 4/FLD28 5/FLD29 6/FLD30 7/FLD31 0/FLD32 1/FLD33 2/FLD34 3/FLD35 P24/FLD36 P25/FLD37 P26/FLD38 P27/FLD39 P30/FLD40 P31/FLD41 P32/FLD42 P33/FLD43 P34/FLD44 P35/FLD45 P36/FLD46 P37/FLD47 P40/FLD48 P41/FLD49 P42/FLD50 P43/FLD51 P44/TXD0/FLD52 P45/RXD0/FLD53 P46/CLK0/FLD54 P47/CTS0/RTS0/FLD55 5/TA2 IN /TA0 OUT XD1 4/TA1 IN /TA4 OUT XD1 1/TB1 IN 0/TB0 IN 5/INT5 4/INT4 3/INT3 2/INT2 1/INT1 0/INT0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description Block Diagram Figure AA-2 is a block diagram of the M30218 group. Block diagram of the M30218 group FigureAA-2. Block diagram of M30218 group /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Timer Timer TA0 (16 bits) Timer TA1 (16 bits) Timer TA2 (16 bits) Timer TA3 (16 bits) Timer TA4 (16 bits) Timer TB0 (16 bits) Timer TB1 (16 bits) Timer TB2 (16 bits) Internal peripheral functions Watchdog timer (15 bits) DMAC (2 channels) D-A converter (8 bits X 2 channels) A-D converter (10 bits X 8 channels) SI/O2 (clock synchronous) (256 bytes automatic transfer) System clock generator XIN-XOUT XCIN-XCOUT M16C/60 series16-bit CPU core I/O ports Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 R0L R0H H R1L R 3A0 FB R0L R0H R1H R1L FB Registers ISP USP Stack pointer Vector table INTB CRC arithmetic circuit (CCITT) (Polynomial : X16+X12+X5+1) Multiplier Port P10 Port P9 Port P8 Port P7 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Memory ROM (Note 1) RAM (Note 2) (includes FLDC,ASI/O RAM) SB FLG PC Program counter Fluorescent display function (56 contorol pins) (52 high-breakdown-voltage ports) Serial I/O UART/clock synchronous SI/O (8 bits X 2 channels) Note 1: ROM size depends on MCU type. Note 2: RAM size depends on MCU type.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description ROM RAM P3, P4, P7 to P10 P0 to P2, P5, P6 TA0, TA1, TA2, TA3, TA4 TB0, TB1, TB2 UART0, UART1 SI/O2 Table AA-1. Performance outline of M30218 group Performance Outline Table AA-1 is a performance outline of M30218 group. Item Performance Number of basic instructions 91 instructions Shortest instruction execution time 100ns(f(X IN)=10MHz) See figure memory expansion See figure memory expansion 8 bits x 6 8 bit x 5 16 bits x 5 16 bits x 3 (UART or clock synchronous) x 2 (Clock synchronous) x 1 (with automatic transfer function) Fluorescent display 56 pins A-D converter 10 bits x 8 channels D-A converter 8 bits x 2 DMAC 2 channels (triggers :15 sources) CRC calculation circuit 1 circuit (polynomial: X 16 + X12 + X5 + 1) Watchdog timer 15 bits x 1 (with prescaler) Interrupt 19 internal and 6 external sources, 4 software sources, 7 levels Clock generating circuit 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) Supply voltage 4.0 to 5.5V (f(X IN)=10MHz) 2.7 to 5.5V (f(XIN)=3.5MHz) (Note) Power consumption 18 mW (V CC =3V, f(XIN)=5MHz) VCC -48V (output ports : P0 to P2, P5, P6, I/O ports : P3, P40 to P43) 0 to VCC (I/O ports :P44 to P47, P7 to P10) - 18mA (P0 to P3, P40 to P43, P5, P6) :high-breakdown-voltage, P-channel open-drain - 5mA (P44 to P47, P7 to P10) 5mA (P44 to P47, P7 to P10) Operating ambient temperature –20 to 85 oC Device configuration CMOS silicon gate Package 100-pin plastic mold QFP Memory capacity I/O port Output port Multifunction timer Serial I/O I/O withstand voltage Output current I/O characteristics H L Note: Only mask ROM version.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description Mitsubishi plans to release the following products in the M30218 group: (1) Support for mask ROM version and flash memory version (2) Memory capacity (3) Package 100P6S : Plastic molded QFP (mask ROM version and flash memory version) Figure AA-4. Type No., memory size, and package Figure AA-3. ROM expansion RAM size (Byte) 12K 512 M30218MC-AXXXFP M30218FCFP 128K ROM size (Byte) M30217MA-AXXXFP5K 96K Package type: FP : Package 100P6S-A ROM No. Omitted for flash memory version ROM capacity: 2 : 16K bytes 4 : 32K bytes 6 : 48K bytes 8 : 64K bytes A : 96K bytes C : 128K bytes Memory type: M : Mask ROM version F : Flash memory version Type No. M 3 0 2 1 8 M C – A X X X F P M16C/21 Group M16C Family Shows RAM capacity, pin count, etc (The value itself has no specific meaning)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin Description Pin Description VCC , VSS CNV SS XIN XOUT AV CC AV SS VEE P00/FLD16 to P07/FLD23 P10/FLD24 to P17/FLD31 P20/FLD32 to P27/FLD39 P30/FLD40 to P37/FLD47 P40/FLD48 to P47/FLD56 Signal name Power supply input CNV SS Reset input Clock input Clock output Analog power supply input pull-down power source Output port P0 Output port P1 Output port P2 I/O port P3 I/O port P4 Supply 2.7V(Note1) to 5.5 V to the V CC pin. Supply 0 V to the VSS pin. Connect a bypass capacitor across the VCC pin and VSS pin. Function Connect it to the VSS pin. A “L” on this input resets the microcomputer. These pins are provided for the main clock generating circuit.Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. This pin is a power supply input for the A-D converter. Connect this pin to V CC . This pin is a power supply input for the A-D converter. Connect this pin to V SS . This is an 8-bit CMOS output port and high-breakdown-voltage P- channel open-drain output structure. A pull-down resistor is built in between port P0 and V EE pin. At reset, this port is set to VEE level. P0 function as FLD controller output pins as selected by software. This is an 8-bit output port equivalent to P0. Pins in this port also function as FLD controller output pins as selected by software. This is an 8-bit output port equivalent to P0. A pull-down resistor is not built in between P2 and V EE pin. Pins in this port also function as FLD controller output pins as selected by software. This is an 8-bit I/O port. A pull-down resistor is not built in between P3 and V EE pin. It has an input/output port direction register that allows the user to set each pin for input or output. This is low-voltage input level, and high-breakdown-voltage P-channel open-drain output structure. Pins in this port also function as FLD controller output pins as selected by software. This is an 8-bit I/O port equivalent to P3. This is low-voltage input level. 0 to P43 is high-breakdown-voltage P-channel open-drain output structure, P44 to P47 is CMOS output. A pull-down resistor is not built in between P4(P40 to P43) and VEE pin. Pins in this port also function as FLD controller output pins as selected by software. P44 to P47 also function as UART0 I/O pins as selected by software. When set for input, the user can specify in units of four bits by software whether or not they are tied to a pull-up resistor. Pin name Input Input Input Output Output Output Output I/O type Analog power supply input Input/output Input/output RESET VREF This pin is a reference voltage input for the A-D converter.InputReference voltage input Apply voltage supplied to pull-down resistors of ports P0 to P1,P5,P6. P50/FLD8 to P57/FLD15 Output port P5 This is an 8-bit output port equivalent to P0. Pins in this port also function as FLD controller output pins as selected by software. Output P60/FLD0 to P67/FLD7 Output port P6 This is an 8-bit output port equivalent to P0. Pins in this port also function as FLD controller output pins as selected by software. Output

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin Description Pin Description Signal name FunctionPin name I/O type Input/output Input/output I/O port P9 I/O port P10 P90 to P97 P100 to P107 This is an 8-bit I/O port equivalent to P7. When set for input, the user can specify in units of four bits by software whether or not they are tied to a pull-up resistor. P9 7 function as D-A converter output pins, clock output pins (same frequency of XIN/8, XIN/32 or XCIN) and DIM signal output pin of FLD controller as selected by software. P96 function as D- A converter output pins and clock I/O pin of serial I/O with automatic transfer as selected by software. P9 0 to P95 function as I/O pin of serial I/O with automatic transfer as selected by software. This is an 8-bit I/O port equivalent to P7. When set for input, the user can specify in units of four bits by software whether or not they are tied to a pull-up resistor. Pins in this port also function as A-D converter input pins as selected by software. P70 to P77 I/O port P7 This is an 8-bit I/O port equivalent to P3. This is CMOS input/output. When set for input, the user can specify in units of four bits by software whether or not they are tied to a pull-up resistor. P7 0 to P72 function as TimerB0 to B2 input pins as selected by software. P73 function as TimerA0 I/O pin as selected by software. P74 to P77 function as TimerA1 to A4 I/O pins, and UART1 I/O pins as selected by software. Input/output P80 to P87 I/O port P8 This is an 8-bit I/O port equivalent to P7. When set for input, the user can specify in units of four bits by software whether or not they are tied to a pull-up resistor. P8 0 to P85 function as external interrupt input pins as selected by software. P86,P87 function as sub-clock input pin as selected by software. In this case, connect a quarts oscillator between 6(XOUT pin) and P87(XCIN pin) Input/output Note 1: Supply 4.0V to 5.5V to the VCC pin in flash memory version.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory Operation of Functional Blocks The M30218 group accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also included are peripheral units such as timers, FLD controller, serial I/O, D-A converter, DMAC, CRC calculation circuit, A-D converter, and I/O ports. The following explains each unit. Memory Figure BA-1 is a memory map of the M30218 group. The address space extends the 1M bytes from ad- dress 00000 16 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30218MC-AXXXFP, there is 128K bytes of internal ROM from E000016 to FFFFF16. The vector table for fixed interrupts such as the reset are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the section on interrupts for details. From 00400 16 up is RAM. For example, in the M30218MC-AXXXFP, there is 12K bytes of internal RAM from 0040016 to 033FF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated. (From 0040016 to 004FF16 is RAM for SIO2. From 0050016 to 005DF16 is RAM for FLD.) The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for periph- eral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Any part of the SFR area that is not occupied is reserved and cannot be used for other purposes. The special page vector table is mapped to FFE00 16 to FFFDB16. If the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps. Figure BA-1. Memory map 0000016 XXXXX 16 FFFFF 16 0040016 0050016 005E016 YYYYY 16 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Internal ROM area SFR area (For details, see Figures BA-2 and BA-3) RAM area for SI/O2 FFE00 16 FFFDC 16 FFFFF 16 Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer Reset Special page vector table DBC Type No. Address XXXXX 16 M30218MC M30218FC E000016 Address YYYYY 16 033FF16 Internal RAM area RAM area for FLD (224 bytes) M30217MA E800016 017FF16

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory Figure BA-2. Location of peripheral unit control registers (1) 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C 16 001D 16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C 16 004D 16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C 16 005D 16 005E16 005F16 INT1 interrupt control register (INT1IC) Timer B0 interrupt control register (TB0IC) Timer B2 interrupt control register (TB2IC) Timer A1 interrupt control register (TA1IC) Timer A3 interrupt control register (TA3IC) UART0 transmit interrupt control register (S0TIC) INT2 interrupt control register (INT2IC) INT0 interrupt control register (INT0IC) Timer B1 interrupt control register (TB1IC) Timer A0 interrupt control register (TA0IC) Timer A2 interrupt control register (TA2IC) Timer A4 interrupt control register (TA4IC) UART0 receive interrupt control register (S0RIC) UART1 transmit interrupt control register (S1TIC) UART1 receive interrupt control register (S1RIC) DMA1 interrupt control register (DM1IC) DMA0 interrupt control register (DM0IC) A-D conversion interrupt control register (ADIC) DMA0 control register (DM0CON) DMA0 source pointer (SAR0) DMA0 transfer counter (TCR0) DMA0 destination pointer (DAR0) DMA1 control register (DM1CON) DMA1 source pointer (SAR1) DMA1 transfer counter (TCR1) DMA1 destination pointer (DAR1) Watchdog timer start register (WDTS) Watchdog timer control register (WDC) Processor mode register 0 (PM0) Address match interrupt register 0 (RMAD0) Address match interrupt register 1 (RMAD1) System clock control register 0 (CM0) System clock control register 1 (CM1) Address match interrupt enable register (AIER) Protect register (PRCR) Processor mode register 1(PM1) INT4 interrupt control register (INT4IC) INT3 interrupt control register (INT3IC) INT5 interrupt control register (INT5IC) SI/O automatic transfer interrupt control register (ASIOIC) FLD interrupt control register (FLDIC) 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C 16 034D 16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C 16 035D 16 035E16 035F16 P3 FLD/port switch register (P3FPR) P5 digit output set register (P5DOR) Toff2 time set register (TOFF2) FLD data pointer (FLDDP) FLD output control register (FLDCON) P6 digit output set register (P6DOR) P4 FLD/port switch register (P4FPR) P2 FLD/port switch register (P2FPR) Tdisp time set register (TDISP) Toff1 time set register (TOFF1) FLD mode register (FLDM) Serial I/O2 automatic transfer data pointer (SIO2DP) Serial I/O2 control register 1 (SIO2CON1) Serial I/O2 control register 2 (SIO2CON2) Serial I/O2 register / transfer counter (SIO2) Serial I/O2 control register 3 (SIO2CON3)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory Figure BA-3. Location of peripheral unit control registers (2) 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C 16 038D 16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C 16 039D 16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA 16 03AB 16 03AC 16 03AD 16 03AE 16 03AF 16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA 16 03BB 16 03BC 16 03BD 16 03BE 16 03BF 16 DMA1 request cause select register (DM1SL) DMA0 request cause select register (DM0SL) UART0 transmit/receive mode register (U0MR) UART0 transmit buffer register (U0TB) UART0 receive buffer register (U0RB) UART1 transmit/receive mode register (U1MR) UART1 transmit buffer register (U1TB) UART1 receive buffer register (U1RB) Timer A0 (TA0) Timer A1 (TA1) Timer A2 (TA2) Timer B0 (TB0) Timer B1 (TB1) Timer B2 (TB2) Count start flag (TABSR) One-shot start flag (ONSF) Timer A0 mode register (TA0MR) Timer A1 mode register (TA1MR) Timer A2 mode register (TA2MR) Timer B0 mode register (TB0MR) Timer B1 mode register (TB1MR) Timer B2 mode register (TB2MR) Up-down flag (UDF) Timer A3 (TA3) Timer A4 (TA4) Timer A3 mode register (TA3MR) Timer A4 mode register (TA4MR) Trigger select register (TRGSR) UART0 bit rate generator (U0BRG) UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1) UART1 bit rate generator (U1BRG) UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1) UART transmit/receive control register 2 (UCON) CRC data register (CRCD) CRC input register (CRCIN) Clock prescaler reset flag (CPSRF) 03C0 16 03C1 16 03C2 16 03C3 16 03C4 16 03C5 16 03C6 16 03C7 16 03C8 16 03C9 16 03CA 16 03CB 16 03CC 16 03CD 16 03CE 16 03CF 16 03D0 16 03D1 16 03D2 16 03D3 16 03D4 16 03D5 16 03D6 16 03D7 16 03D8 16 03D9 16 03DA 16 03DB 16 03DC 16 03DD 16 03DE 16 03DF 16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA 16 03EB 16 03EC 16 03ED 16 03EE 16 03EF 16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA 16 03FB 16 03FC 16 03FD 16 03FE 16 03FF16 Port P0 (P0) Port P1 (P1) Port P2 (P2) Port P3 (P3) Port P3 direction register (PD3) Port P4 (P4) Port P4 direction register (PD4) Port P5 (P5) Port P6 (P6) Port P7 (P7) Port P7 direction register (PD7) Port P8 (P8) Port P8 direction register (PD8) Port P9 (P9) Port P9 direction register (PD9) Port P10 (P10) Port P10 direction register (PD10) Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) A-D register 7 (AD7) A-D register 0 (AD0) A-D register 1 (AD1) A-D register 2 (AD2) A-D register 3 (AD3) A-D register 4 (AD4) A-D register 5 (AD5) A-D register 6 (AD6) A-D control register 0 (ADCON0) A-D control register 1 (ADCON1) D-A register 0 (DA0) D-A register 1 (DA1) D-A control register (DACON) A-D control register 2 (ADCON2) Flash memory control register 0 (FCON0) (Note) Flash memory control register 1 (FCON1) (Note) Flash command register (FCMD) (Note) Note: This register is only exist in flash memory version.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Central Processing Unit (CPU) The CPU has a total of 13 registers shown in Figure CA-1. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks. (1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3) Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H, R1H), and low-order bits as (R0L, R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32-bit data registers (R2R0, R3R1). (2) Address registers (A0 and A1) Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). Figure CA-1. Central processing unit register /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines H L b15 b8 b7 b0 R0 (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines H L b15 b8 b7 b0 R1 (Note) R2 (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 R3 (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 A0(Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 A1(Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 FB (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 Data registers Address registers Frame base registers b15 b0 b15 b0 b15 b0 b15 b0 b0 b19 b0 b19 H L Program counter Interrupt table register User stack pointer Interrupt stack pointer Static base register Flag register PC INTB USP ISP SB FLG Note: These registers consist of two register banks. /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines C D Z S B O I UIPL

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU (3) Frame base register (FB) Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing. (4) Program counter (PC) Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed. (5) Interrupt table register (INTB) Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table. (6) Stack pointer (USP/ISP) Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config- ured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG). (7) Static base register (SB) Static base register (SB) is configured with 16 bits, and is used for SB relative addressing. (8) Flag register (FLG) Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure CA-2 shows the flag register (FLG). The following explains the function of each flag:

• Bit 0: Carry flag (C flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag) This flag enables a single-step interrupt. When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag) This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag) This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”.
• Bit 4: Register bank select flag (B flag) This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
• Bit 5: Overflow flag (O flag) This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag) This flag enables a maskable interrupt. An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0” when the interrupt is acknowledged.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Figure CA-2. Flag register (FLG)

• Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected when this flag is “1”. This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled.
• Bit 15: Reserved area The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details. Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area F l a g r e g i s t e r ( F L G )C D Z S B O I UI P L b0b 1 5

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Reset Reset There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset. (See “Software Reset” for details of software resets.) This section explains on hardware resets. When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level “L” (0.2V CC max.) for at least 20 cycles. When the reset pin level is then returned to the “H” level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. Figure DA-1 shows the example reset circuit. Figure DA-2 shows the reset sequence. Figure DA-1. Example reset circuit RESET VCC 0.8V RESET VCC 4.0V Exam ple when f(XIN) = 10MHz and VCC = 5V. BCLK Address BCLK 24cycles FFFFC 16 FFFFE 16 Content of reset vector XIN RESET More than 20 cycles are needed (Internal clock) (Internal address signal) Figure DA-2. Reset sequence

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Reset Figure DA-3. Device's internal status after a reset is cleared x : Nothing is mapped to this bit ? : Undefined The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. (1) (0004 16)···Processor mode register 0 (2) (0005 16)···Processor mode register 1 0 0 (3) (0006 16)···System clock control register 0 100 00 10 0 (4) (0007 16)···System clock control register 1 000 10 00 0 (5) (6) (000916)···Address match interrupt enable register 00 (7) (12) (13) (21) (22) (23) (20) (8) (001216)··· 0 (000F16)···Watchdog timer control register 0 0? 0? ? ? ? (001016)···Address match interrupt register 0 (001116)··· 0016 0016 0 0 0 (14) (9) (001416)···Address match interrupt register 1 (001516)··· (001616)··· 0 0016 0016 0 0 0 (002C16)···DMA0 control register 00000?00 (003C16)···DMA1 control register 00000?00 (004416)···INT3 interrupt control register 00?000 (15) (16) (17) (18) (19) (0048 16)···INT4 interrupt control register 00?000 (004916)···INT5 interrupt control register 00?000 (29) (30) (31) (32) (33) (34) (35) (36) (37) Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register (38) Timer B2 interrupt control register (39) INT0 interrupt control register (40) INT1 interrupt control register (41) INT2 interrupt control register (45) FLDC mode register (46) FLD output control register Serial I/O 2 control register 2 (43) Serial I/O 2 control register 3 (44) (42) Serial I/O 2 control register 1 (47) Tdisp time set register Toff1 time set register Toff2 time set register P2 FLD/port switch register P4 FLD/port switch register P6 digit output set register (005516)··· (005616)··· (005716)··· (005816)··· (005916)··· (005A16)··· (005B16)··· (005C16)··· (005D16)··· (005E16)··· (005F16)··· (035016)··· (035116)··· (034416)··· (034816)··· (034216)··· (035216)··· (035416)··· (035616)··· (035916)··· (035B16)··· (035D16)··· (035A16)···P3 FLD/port switch registerA-D conversion interrupt control register SI/O automatic transfer interrupt control register FLD interrupt control register (004F16)··· (005016)··· ? 0 0 0 ? 0 0 0 UART0 transmit interrupt control register UART0 receive interrupt control register (005116)··· (005216)··· ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 00000 ? 00000 ? 00000 P5 digit output set register (035C16)··· (000A16)···Protect register 00 0 (10) (11) (004B16)···DMA0 interrupt control register ? 0 0 0 (004C16)···DMA1 interrupt control register ? 0 0 0 UART1 transmit interrupt control register UART1 receive interrupt control register (005316)··· (005416)··· ? 0 0 0 ? 0 0 0 (24) (25) (26) (27) (28) 00 00 0016 0016 0016 0016 0016 0016 FF16 FF16 0016 0016 0016 0016 0016

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Reset Figure DA-4. Device's internal status after a reset is cleared (038316)···Trigger select flag (038416)···Up-down flag(52) (51) (039616)···Timer A0 mode register(53) (039716)···Timer A1 mode register(54) (039816)···Timer A2 mode register (57) (039B16)···Timer B0 mode register(58) (039C16)···Timer B1 mode register (039D16)···Timer B2 mode register (70) (55) (039916)···Timer A3 mode register(56) (039A16)···Timer A4 mode register (038216)···One-shot start flag(50) 0016 0016 0016 0016 0016 0016 0016 0? 0000 00? 0000 00? 0000 (03AC16)···UART1 transmit/receive control register 0 (75) (03AD16)···UART1 transmit/receive control register 1 (76) (03B016)···UART transmit/receive control register 2 (77) (03B816)···DMA0 cause select register (78) (03BA16)···DMA1 cause select register (79) (03A016)···UART0 transmit/receive mode register (71) (03A416)···UART0 transmit/receive control register 0 (72) (03A516)···UART0 transmit/receive control register 1 (73) 0016 000 1000 000 0010 (03A816)···UART1 transmit/receive mode register (74) 0016 000 1000 000 0010 00 0 0 00 0016 0016 (03D416)···A-D control register 2 (80) (03D616)···A-D control register 0 (81) (03D716)···A-D control register 1 (82) 000 0???0 0016 000 00 0 0 Count start flag (0380 16)··· 0016 0(038116)···Clock prescaler reset flag (48) (49) x : Nothing is mapped to this bit ? : Undefined The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. (84) (85) (86) (03E716)···Port P3 direction register (87) (03EA16)···Port P4 direction register (88) (89) (03EF 16)···Port P7 direction register (03F216)···Port P8 direction register (03F316)···Port P9 direction register (03F616)···Port P10 direction register (03FD16)···Pull-up control register 0 (03FE16)···Pull-up control register 1 0016 0016 0016 0016 0016 0016 0016 Frame base register (FB) Address registers (A0/A1) Interrupt table register (INTB) User stack pointer (USP) Interrupt stack pointer (ISP) Static base register (SB) Flag register (FLG) 000016 000016 0000016 000016 000016 000016 000016 Data registers (R0/R1/R2/R3) 000016 (03DC16)···D-A control register 0016 (62) (61) (63) (64) (67) (68) (65) (66) (60) (59) (69) (83) 0016 Flash memory control register 0 (Note ) Flash memory control register 1 (Note) Flash command register (Note) Note: This register is only exist in flash memory version. (03B416)··· 01 00000 (03B516)··· 0 (03B616)··· 0016 (90) (91) (92)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Software Reset Software Reset Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software reset) reset to the microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal RAM are preserved. Figure DA-5 shows the processor mode register 0 and 1. Figure DA-5. Processor mode register 0 and 1. Processor mode register 0 (Note) Symbol Address When reset PM0 0004 16 XXXX0000 2 Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 PM03 Reserved bit Software reset bit The device is reset when this bit is set to “1”. The value of this bit is “0” when read. Note: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register. Processor mode register 1 (Note) Symbol Address When reset PM1 0005 16 00XXXXX0 2 Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 Reserved bit Must always be set to “0” Note: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register. /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines Must always be set to “0” Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. 0 0 0 0 Reserved bit Must always be set to “0” /LiteDiagLines/LiteDiagLines Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.

t Mitsubishi microcomputers M30218 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock Generating Circuit Figure WA-2. Examples of sub clock Clock Generating Circuit The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral units. Table WA-1. Main clock and sub clock generating circuits Example of oscillator circuit Figure WA-1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Figure WA-2 shows some examples of sub clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Circuit constants in Figures WA-1 and WA-2 vary with each oscillator used. Use the values recommended by the manufacturer of your oscillator. Figure WA-1. Examples of main clock Main clock generating circuit Sub clock generating circuit Use of clock • CPU’s operating clock source • CPU’s operating clock source

• Internal peripheral units’ • Timer A/B’s count clock operating clock source source Usable oscillator Ceramic or crystal oscillator Crystal oscillator Pins to connect oscillator X IN, XOUT XCIN, XCOUT Oscillation stop/restart function Available Available Oscillator status immediately after reset Oscillating Stopped Other Externally derived clock can be input Microcomputer (Built-in feedback resistor) XIN XOUT Externally derived clock Open Vcc Vss Microcomputer (Built-in feedback resistor) XIN XOUT R d C IN C OUT (Note) Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between X IN and XOUT following the instruction. Microcomputer (Built-in feedback resistor) XCIN XCOUT Externally derived clock Open Vcc Vss Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between X CIN and XCOUT following the instruction. Microcomputer (Built-in feedback resistor) XCIN XCOUT (Note) C CIN C COUT R Cd

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock Generating Circuit Clock Control Figure WA-3 shows the block diagram of the clock generating circuit. Figure WA-3. Clock generating circuit Sub clock CM04 fC32 CM0i : Bit i at address 000616 CM1i : Bit i at address 000716 WDCi : Bit i at address 000F16 XCIN CM10 “1” Write signal XCOUT QS R WAIT instruction XOUT Main clock CM05 fC CM02 Q S R Interrupt request level judgment output RESET Software reset fC CM07=0 CM07=1 fAD /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Dividera d 1/2 1/2 1/2 1/2 CM06=0 CM17,CM16=00 CM06=0 CM17,CM16=01 CM06=0 CM17,CM16=10 CM06=1 CM06=0 CM17,CM16=11 d a Details of divider XIN f32 cb b c BCLK f8SIO2 f1SIO2

t Mitsubishi microcomputers M30218 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock Generating Circuit The following paragraphs describes the clocks generated by the clock generating circuit. (1) Main clock The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation. After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the X IN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is re- tained. (2) Sub-clock The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset. After oscillation is started using the port Xc select bit (bit 4 at address 0006 16), the sub-clock can be selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the sub-clock oscillation has fully stabilized before switching. After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock oscillation circuit can be reduced using the X CIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit changes to “1” when shifting to stop mode and at a reset. (3) BCLK The BCLK is the clock that drives the CPU, and is fc or the clock is derived by dividing the main clock by 1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK signal can be output from BCLK pin by the BCLK output disable bit (bit 7 at address 0004 16) in the memory expan- sion and the microprocessor modes. The main clock division select bit 0(bit 6 at address 0006 16) changes to “1” when shifting from high- speed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. (4) Peripheral function clock(f1, f8, f32, fAD , f1SIO2, f8SIO2) The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 0006 16) to “1” and then executing a WAIT instruction. (5) fC32 This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts. (6) fC This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock Generating Circuit Figure WA-4 shows the system clock control registers 0 and 1. System clock control register 0 (Note 1) Symbol Address When reset CM0 0006 16 4816 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : I/O port P97/DA0 0 1 : fC output 1 0 : f8 output 1 1 : f32 output b1 b0 CM07 CM05 CM04 CM03 CM01 CM02 CM00 CM06 Clock output function select bit (Valid only in single-chip mode) WAIT peripheral function clock stop bit 0 : Do not stop peripheral function clock in wait mode 1 : Stop peripheral function clock in wait mode (Note 8) XCIN-XCOUT drive capacity select bit (Note 2) 0 : LOW 1 : HIGH Port XC select bit 0 : I/O port 1 : XCIN-XCOUT generation Main clock (XIN-XOUT ) stop bit (Note 3, 4, 5) 0 : On 1 : Off Main clock division select bit 0 (Note 7) 0 : CM16 and CM17 valid 1 : Division by 8 mode System clock select bit (Note 6) 0 : XIN, XOUT 1 : XCIN, XCOUT Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register. Note 2: Changes to “1” when shiffing to stop mode and at a reset. Note 3: When entering power saving mode, main clock stops using this bit. When returning from stop mode and operating with XIN, set this bit to “0”. When main clock oscillation is operating by itself, set system clock select bit (CM07) to “1” before setting this bit to “1”. Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. Note 5: If this bit is set to “1”, X OUT turns “H”. The built-in feedback resistor remains being connected, so XIN turns pulled up to XOUT (“H”) via the feedback resistor. Note 6: Set port Xc select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting to this bit from “0” to “1”. Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the main clock oscillating before setting this bit from “1” to “0”. Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Note 8: f C32 is not included. System clock control register 1 (Note 1) Symbol Address When reset CM1 0007 16 2016 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 CM10 All clock stop control bit (Note4) 0 : Clock on 1 : All clocks off (stop mode) Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register. Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is “0”. If “1”, division mode is fixed at 8. Note 4: If this bit is set to “1”, XOUT turns “H”, and the built-in feedback resistor is cut off. XCIN and XCOUT turn high- impedance state. CM15 XIN-XOUT drive capacity select bit (Note 2) 0 : LOW 1 : HIGH W R W R CM16 CM17 Reserved bit Always set to “0” Reserved bit Always set to “0” Main clock division select bit 1 (Note 3) 0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode b7 b6 0 0 Reserved bit Always set to “0” Reserved bit Always set to “0” 0 0 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Figure WA-4. Clock control registers 0 and 1

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock output Clock Output The clock output function select bit (bit 0,1 at address 000616) allows you to choose the clock from f8, f32, or fc to be output from the P97/DA0/CLKOUT /DIMOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address 000616) is set to “1”, the output of f8 and f32 stop by executing of WAIT instruction. Stop Mode Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcom- puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC re- mains above 2V. Because the oscillation of BCLK, f1 to f32, fc, fC32 , and fAD stops in stop mode, peripheral functions such as the fluorescent display function, serial I/O 2, A-D converter and watchdog timer do not function. However, timer A and timer B operate provided that the event counter mode is set to an external pulse, and UART0 and UART2 functions provided an external clock is selected. Table WA-2 shows the status of the ports in stop mode. Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled. If returning by an interrupt, that interrupt routine is executed. When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division select bit 0 (bit 6 at address 0006 16) is set to “1”. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Table WA-2. Port status during stop mode Pin States Port Retains status before stop mode CLK OUT When fC selected “H” When f8, f32 selected Retains status before stop mode Wait Mode When a WAIT instruction is executed, BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. Table WA-3 shows the status of the ports in wait mode. Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, the microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected when the WAIT instruction was executed. Table WA-3. Port status during wait mode Pin States Port Retains status before wait mode CLK OUT When fC selected Does not stop When f8, f32 selected Does not stop when the WAIT peripheral function clock stop bit is “0”. (Note) When the WAIT peripheral function clock stop bit is “1”, the status immediately prior to entering wait mode is maintained. Note: Attention that reducing the power dissipation is impossible.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Status Transition of BCLK CM17 CM16 CM07 CM06 CM05 CM04 Operating mode of BCLK 0 1 0 0 0 Invalid Division by 2 mode 1 0 0 0 0 Invalid Division by 4 mode Invalid Invalid 0 1 0 Invalid Division by 8 mode 1 1 0 0 0 Invalid Division by 16 mode 0 0 0 0 0 Invalid No-division mode Invalid Invalid 1 Invalid 0 1 Low-speed mode Invalid Invalid 1 Invalid 1 1 Low power dissipation mode Table WA-4. Operating modes dictated by settings of system clock control registers 0 and 1 Status Transition Of BCLK Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table WA-4 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address 0006 16) changes to “1” when shifting from high-speed/medium-speed to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. The following shows the operational modes of BCLK. (1) Division by 2 mode The main clock is divided by 2 to obtain the BCLK. (2) Division by 4 mode The main clock is divided by 4 to obtain the BCLK. (3) Division by 8 mode The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption mode, make sure the sub-clock is oscillating stably. (4) Division by 16 mode The main clock is divided by 16 to obtain the BCLK. (5) No-division mode The main clock is divided by 1 to obtain the BCLK. (6) Low-speed mode fC is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub- clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled. (7) Low power dissipation mode fC is the BCLK and the main clock is stopped. Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which the count source is going to be switched must be oscillating stably. Allow a wait time in software for the oscillation to stabilize before switching over the clock.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Power control Power control The following is a description of the three available power control modes: Modes Power control is available in three modes. (a) Normal operation mode

• High-speed mode Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the internal clock selected. Each peripheral function operates according to its assigned clock.
• Medium-speed mode Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the BCLK. The CPU operates according to the internal clock selected. Each peripheral function oper- ates according to its assigned clock.
• Low-speed mode f C becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the secondary clock. Each peripheral function operates according to its assigned clock.
• Low power consumption mode The main clock operating in low-speed mode is stopped. The CPU operates according to the fC clock. The fc clock is supplied by the secondary clock. The only peripheral functions that operate are those with the sub-clock selected as the count source. (b) Wait mode The CPU operation is stopped. The oscillators do not stop. (c) Stop mode All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three modes listed here, is the most effective in decreasing power consumption. Figure WA-5 is the state transition diagram of the above modes.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Power control Figure WA-5. State transition diagram of Power control mode Transition of stop mode, wait mode Transition of normal mode Reset Medium-speed mode (divided-by-8 mode)Interrupt CM10 = “1” All oscillators stopped CPU operation stopped Medium-speed mode (divided-by-8 mode) BCLK : f(XIN)/8 Low-speed mode High-speed mode Main clock is oscillating Sub clock is stopped Main clock is oscillating Sub clock is stopped Main clock is stopped Sub clock is oscillating Main clock is oscillating Sub clock is oscillating Low power dissipation mode High-speed/medium- speed mode Low-speed/low power dissipation mode Normal mode Stop mode Stop mode Stop mode All oscillators stopped All oscillators stopped Wait mode Wait mode Wait mode CPU operation stopped CPU operation stopped Interrupt WAIT instruction Interrupt WAIT instruction Interrupt WAIT instruction CM10 = “1” Interrupt Interrupt CM10 = “1” BCLK : f(XIN)/2 Medium-speed mode (divided-by-2 mode) BCLK : f(XIN)/16 Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/4 Medium-speed mode (divided-by-4 mode) BCLK : f(XIN) BCLK : f(XIN)/8 Medium-speed mode (divided-by-8 mode) CM07 = “0” CM06 = “1” High-speed mode BCLK : f(XIN)/2 Medium-speed mode (divided-by-2 mode) BCLK : f(XIN)/16 Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/4 Medium-speed mode (divided-by-4 mode) BCLK : f(XIN) BCLK : f(XCIN) CM07 = “1” BCLK : f(XCIN) CM07 = “1” Main clock is oscillating Sub clock is oscillating CM07 = “0” (Note 1, 3) CM07 = “0” (Note 1) CM06 = “1” (Note 2) CM07 = “0” (Note 1) CM06 = “0” (Note 3) CM04 = “1” CM07 = “1” (Note 2) CM05 = “1” CM06 = “0” (Notes 1,3) CM06 = “1” (Notes 1, 3) Note 1: Switch clock after oscillation of main clock is sufficiently stable. Note 2: Switch clock after oscillation of sub clock is sufficiently stable. Note 3: Change CM06 after changing CM17 and CM16. Note 4: Transit in accordance with arrow. (Refer to the following for the transition of normal mode.)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Protection Protection The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure WA-6 shows the protect register. The values in the processor mode register 0 (address 0004 16), processor mode register 1 (address 000516), system clock control reg- ister 0 (address 000616), and system clock control register 1 (address 000716) can only be changed when the respective bit in the protect register is set to “1”. The system clock control registers 0 and 1 write-enable bit (bit 0 at address 000A 16) and processor mode register 0 and 1 write-enable bit (bit 1 at address 000A16) do not automatically return to “0” after a value has been written to an address. The program must therefore be written to return these bits to “0”. Figure WA-6. Protect register P r o t e c t r e g i s t e r Symbol Address When reset PRCR 000A 16 XXXXX000 2 Bit nameB i t s y m b o l b 4b 3b 0 : W r i t e - i n h i b i t e d W r i t e e n a b l e d P R C 1 P R C 0 Enables writing to processor mode registers 0 and 1 (addresses 0004 and 000516) F u n c t i o n 0 : W r i t e - i n h i b i t e d W r i t e e n a b l e d E n a b l e s w r i t i n g t o s y s t e m c l o c k c o n t r o l r e g i s t e r s a n d a d d r e s s e s a n d W R Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt

• Maskable interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level. Figure DD-1. Classification of interrupts Interrupt Software Hardware Special Peripheral I/O (Note) Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Reset DBC Watchdog timer Single step Address matched Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system. Overview of Interrupt Type of Interrupts Figure DD-1 lists the types of interrupts.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts.

• Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to “1”. The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt An INT interrupt occurs when specifying one of software interrupt numbers 0 through 63 and execut- ing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O inter- rupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/ O interrupt does. The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is involved. So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt re- quest. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts. (1) Special interrupts Special interrupts are non-maskable interrupts.

• Reset Reset occurs if an “L” is input to the RESET pin.
• DBC interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt Generated by the watchdog timer.
• Single-step interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
• Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to “1”. If an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. (2) Peripheral I/O interrupts A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func- tions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• DMA0 interrupt, DMA1 interrupt These are interrupts that DMA generates.
• A-D conversion interrupt This is an interrupt that the A-D converter generates.
• UART0 and UART1 transmission interrupt These are interrupts that the serial I/O transmission generates.
• UART0 and UART1 reception interrupt These are interrupts that the serial I/O reception generates.
• SI/O automatic transfer interrupt This is an interrupt that the SI/O automatic transfer generates.
• Timer A0 interrupt through timer A4 interrupt These are interrupts that timer A generates
• Timer B0 interrupt through timer B2 interrupt These are interrupts that timer B generates.
• INT0 interrupt through INT5 interrupt An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt source Vector table addresses Remarks Address (L) to address (H) Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction Overflow FFFE0 16 to FFFE316 Interrupt on INTO instruction BRK instruction FFFE4 16 to FFFE716 If the vector contains FF16, program execution starts from the address shown by the vector in the variable vector table Address match FFFE8 16 to FFFEB16 There is an address-matching interrupt enable bit Single step (Note) FFFEC 16 to FFFEF16 Do not use Watchdog timer FFFF0 16 to FFFF316 DBC (Note) FFFF4 16 to FFFF716 Do not use - FFFF8 16 to FFFFB16 - Reset FFFFC 16 to FFFFF16 Note: Interrupts used for debugging purposes only. Figure DD-2. Format for specifying interrupt vector addresses Mid address Low address 0 0 0 0H i g h a d d r e s s 0 0 0 0 0 0 0 0 Vector address + 0 Vector address + 1 Vector address + 2 Vector address + 3 L S BMSB Interrupts and Interrupt Vector Tables If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Figure DD-2 shows the format for specifying the address. Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting.

• Fixed vector tables The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFDC 16 to FFFFF16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table DD-1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. Table DD-1. Interrupts assigned to the fixed vector tables and addresses of vector tables

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Table DD-2. Interrupts assigned to the variable vector tables and addresses of vector tables Software interrupt number Interrupt sourceVector table address Address (L) to address (H) Remarks Cannot be masked I flag+0 to +3 (Note) BRK instructionSoftware interrupt number 0 +44 to +47 (Note) Software interrupt number 11 +48 to +51 (Note)Software interrupt number 12 +56 to +59 (Note)Software interrupt number 14 +68 to +71 (Note)Software interrupt number 17 +72 to +75 (Note)Software interrupt number 18 +76 to +79 (Note)Software interrupt number 19 +80 to +83 (Note)Software interrupt number 20 +84 to +87 (Note)Software interrupt number 21 +88 to +91 (Note)Software interrupt number 22 +92 to +95 (Note)Software interrupt number 23 +96 to +99 (Note)Software interrupt number 24 +100 to +103 (Note) Software interrupt number 25 +104 to +107 (Note) Software interrupt number 26 +108 to +111 (Note) Software interrupt number 27 +112 to +115 (Note) Software interrupt number 28 +116 to +119 (Note) Software interrupt number 29 +120 to +123 (Note) Software interrupt number 30 +124 to +127 (Note) Software interrupt number 31 +128 to +131 (Note) Software interrupt number 32 +252 to +255 (Note) Software interrupt number 63 to Note : Address relative to address in interrupt table register (INTB). Cannot be masked I flag to A-D UART0 transmit UART0 receive UART1 transmit UART1 receive Timer A0 Timer A1 Timer A2 Timer A3 Timer B0 Timer B1 INT0 INT1 Software interrupt +28 to +31 (Note) INT3 Software interrupt number 7 +32 to +35 (Note) INT4 Software interrupt number 8 +36 to +39 (Note) INT5 Software interrupt number 9 DMA0 DMA1 +60 to +63 (Note)Software interrupt number 15 SI/O automatic transfer +64 to +67 (Note)Software interrupt number 16 FLD Timer A4 Timer B2 INT2

• Variable vector tables The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the ad- dress the INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes. Set the first address of the interrupt routine in each vector table. Table DD-2 shows the interrupts assigned to the variable vector tables and addresses of vector tables.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Control Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selec- tion bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are located in the flag register (FLG). Figure DD-3 shows the memory map of the interrupt control registers.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Figure DD-3. Interrupt control registers Symbol Address When reset INTiIC(i=0 to 5) 005D16 to 005F16 XX00X000 2 004716 to 004916 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines ILVL0 IR POL Interrupt priority level select bit Interrupt request bit Polarity select bit Reserved bit 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Always set to “0” ILVL1 ILVL2 Note1 : This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts. (Note1) Interrupt control register(Note2) b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines Bit name FunctionBit symbol W R Symbol Address When reset DMiIC(i=0, 1) 004B 16 to 004C16 XXXXX000 2 ADIC 004E 16 XXXXX000 2 ASIOIC 004F 16 XXXXX000 2 FLDIC 0050 16 XXXXX000 2 SiTIC(i=0, 1) 0051 16, 005316 XXXXX000 2 SiRIC(i=0, 1) 0052 16, 005416 XXXXX000 2 TAiIC(i=0 to 4) 0055 16 to 005916 XXXXX000 2 TBiIC(i=0 to 2) 005A 16 to 005C16 XXXXX000 2 ILVL0 IR Interrupt priority level select bit Interrupt request bit 0 : Interrupt not requested 1 : Interrupt requested ILVL1 ILVL2 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. (Note1) Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts. 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Enable Flag (I flag) The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set to “0” after reset. Interrupt Request Bit The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The interrupt request bit can also be set to "0" by software. (Do not set this bit to "1"). Table DD-4. Interrupt levels enabled according to the contents of the IPL Table DD-3. Settings of interrupt priority levels Interrupt priority level select bit Interrupt priority level Priority order 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Low High b2 b1 b0 Enabled interrupt priority levels 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 4 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled IPL2 IPL1 IPL0 IPL Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL) Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt priority level to “0” disables the interrupt. Table DD-3 shows the settings of interrupt priority levels and Table DD-4 shows the interrupt levels enabled, according to the consist of the IPL. The following are conditions under which an interrupt is accepted:

• interrupt enable flag (I flag) = 1
• interrupt request bit = 1
• interrupt priority level > IPL The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are independent, and they are not affected by one another.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Example 1: INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. NOP ; NOP FSET I ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. MOV.W MEM, R0 ; Dummy read. FSET I ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG ; FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. POPC FLG ; Enable interrupts. The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. Rewrite the interrupt control register To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow: When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. In the interrupt sequence, the processor carries out the following in sequence given: (1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading ad- dress 00000 16. (2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU. (3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to “0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed) (4) Saves the content of the temporary register (Note) within the CPU in the stack area. (5) Saves the content of the program counter (PC) in the stack area. (6) Sets the interrupt priority level of the accepted instruction in the IPL. After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. Note: This register cannot be utilized by the user. Interrupt Response Time 'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). Figure DD-4 shows the interrupt response time. Instruction Interrupt sequence Instruction in interrupt routine Time Interrupt response time (a) (b) Interrupt request acknowledgedInterrupt request generated (a) Time from interrupt request is generated to when the instruction then under execution is completed. (b) Time in which the instruction sequence is executed. Figure DD-4. Interrupt response time

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Interrupt sources without priority levels Value set in the IPL Watchdog timer Other Not changed Variation of IPL when Interrupt Request is Accepted If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in Table DD-6 is set in the IPL. Table DD-6. Relationship between interrupts without interrupt priority levels and IPL Stack pointer (SP) valueInterrupt vector address 16-Bit bust 8-Bit bus Even Even Odd (Note 2) Odd (Note 2) Even Odd Even Odd 18 cycles (Note 1) 19 cycles (Note 1) 19 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) Table DD-5. Time required for executing the interrupt sequence Reset Indeterminate 123456789 1 0 1 1 12 13 14 15 16 17 18 The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs. Indeterminate SP-2

contents

0000 Indeterminate SP-2 SP-4 vec vec+2 PC

W R Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction. Time (b) is as shown in Table DD-5. Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence interrupt or of a single-step interrupt. Note 2: Locate an interrupt vector address in an even address, if possible. Figure DD-5. Time required for executing the interrupt sequence

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Saving Registers In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the stack area. First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. Figure DD-6 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM instruction alone can save all the registers except the stack pointer (SP). Address Content of previous stack Stack area [SP] Stack pointer value before interrupt occurs m m – 1 m – 2 m – 3 m – 4 Stack status before interrupt request is acknowledged Stack status after interrupt request is acknowledged Content of previous stackm + 1 MSB LSB m m – 1 m – 2 m – 3 m – 4 Address Flag register (FLG Content of previous stack Stack area Flag register (FLGH ) Program counter (PCH ) [SP] New stack pointer value Content of previous stackm + 1 MSB LSB Program counter (PC Program counter (PCM ) Figure DD-6. State of stack before and after acceptance of interrupt request

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Figure DD-7. Operation of saving registers (2) Stack pointer (SP) contains odd number [SP] (Odd) [SP] – 1 (Even) [SP] – 2(Odd) [SP] – 3 (Even) [SP] – 4(Odd) [SP] – 5 (Even) Address Sequence in which order registers are saved (2) (1) Finished saving registers in four operations. (3) (4) (1) Stack pointer (SP) contains even number [SP] (Even) [SP] – 1(Odd) [SP] – 2 (Even) [SP] – 3(Odd) [SP] – 4 (Even) [SP] – 5 (Odd) Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. Address Program counter (PCM ) Stack area Flag register (FLGL) Program counter (PCL) Sequence in which order registers are saved (2) Saved simultaneously, all 16 bits (1) Saved simultaneously, all 16 bits Finished saving registers in two operations. Program counter (PCM ) Stack area Flag register (FLGL) Program counter (PCL) Saved simultaneously, all 8 bits Flag register (FLGH ) Program counter (PCH ) Flag register (FLGH ) Program counter (PCH ) The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer, at the time of acceptance of an interrupt request, is even or oDD- If the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Figure DD-7 shows the operation of the saving registers. Note: Stack pointer indicated by U flag.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Priority If there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted. Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. Figure DD-8 shows the priorities of hardware interrupts. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine. Returning from an Interrupt Routine Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter (PC), both of which have been saved in the stack area. Then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process resumes. Return the other registers saved by software within the interrupt routine using the POPM or similar instruc- tion before executing the REIT instruction. Interrupt resolution circuit When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest priority level. Figure DD-9 shows the circuit that judges the interrupt priority level. Figure DD-8. Hardware interrupts priorities Reset > DBC > Watchdog timer > Peripheral I/O > Single step > Address match

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Figure DD-9. Maskable interrupts priorities Timer B0 Timer A3 INT2 Timer B1 INT3 UART1 reception UART0 reception FLD Timer A0 UART1 transmission UART0 transmission SI/O2 automatic transfer Processor interrupt priority level (IPL) Interrupt enable flag (I flag) Timer B2 INT0 Watchdog timer Reset DBC Interrupt request accepted Level 0 (initial value) Priority level of each interrupt High Low Priority of peripheral I/O interrupts (if priority levels are same) Address match INT1 Timer A1 INT4 Timer A4 Timer A2 INT5 A-D conversion DMA1 DMA0 Interrupt request level judgment output

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Address Match Interrupt An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not affected by the inter- rupt enable flag (I flag) and processor interrupt priority level (IPL). The value of the program counter (PC) for an address match interrupt varies depending on the instruction being executed. Figure DD-12 shows the address match interrupt-related registers. B i t n a m e B i t s y m b o l S y m b o lA d d r e s s W h e n r e s e t A I E 6 X X X X X X A d d r e s s m a t c h i n t e r r u p t e n a b l e r e g i s t e r Function W R Address match interrupt 0 enable bit 0 : Interrupt disabled 1 : Interrupt enabled A I E R 0 A d d r e s s m a t c h i n t e r r u p t 1 e n a b l e b i t AIER1 S y m b o lA d d r e s s W h e n r e s e t R M A D t o 6 X R M A D t o 6 X b W R A d d r e s s s e t t i n g r e g i s t e r f o r a d d r e s s m a t c h i n t e r r u p t F u n c t i o nV a l u e s t h a t c a n b e s e t Address match interrupt register i (i = 0, 1) 0000016 to FFFFF16 0 : Interrupt disabled 1 : Interrupt enabled b 0 b b ) (b16) b b )( b 8 ) b b Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. N o t h i n g i s a s s i g n e d . I n a n a t t e m p t t o w r i t e t o t h e s e b i t s w r i t e T h e v a l u e i f r e a d t u r n s o u t t o b e i n d e t e r m i n a t e .Figure DD-12. Address match interrupt-related registers

Precautions for Interrupts Mitsubishi microcomputers M30218 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure DD-13. Switching condition of INT interrupt request Set the polarity select bit Clear the interrupt request bit to “0” Set the interrupt priority level to level 1 to 7 (Enable the accepting of INTi interrupt request) Set the interrupt priority level to level 0 (Disable INTi interrupt) Clear the interrupt enable flag to “0” (Disable interrupt) Set the interrupt enable flag to “1” (Enable interrupt) Precautions for Interrupts (1) Reading address 0000016

• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”. Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”. Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 00000 16 by software. (2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the stack pointer before accepting an interrupt. (3) External interrupt
• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0 through INT5 regardless of the CPU operation clock.
• When the polarity of the INT0 through INT5 pins is changed, the interrupt request bit is sometimes set to “1”. After changing the polarity, set the interrupt request bit to “0”. Figure DD-13 shows the procedure for changing the INT interrupt generate factor.

Precautions for Interrupts Mitsubishi microcomputers M30218 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Example 1: INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. NOP ; NOP FSET I ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. MOV.W MEM, R0 ; Dummy read. FSET I ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG ; FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. POPC FLG ; Enable interrupts. The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. (5) Rewrite the interrupt control register

• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow:
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Watchdog Timer Figure FA-1. Block diagram of watchdog timer BCLK Write to the watchdog timer start register (address 000E 16) RESET Watchdog timer interrupt request Watchdog timer Set to “7FFF16” “CM07 = 0” “WDC7 = 1” “CM07 = 0” “WDC7 = 0” “CM07 = 1” Prescaler Watchdog Timer The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. When X IN is selected for the BCLK , bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000F16). Thus the watchdog timer's period can be calcu- lated as given below. The watchdog timer's period is, however, subject to an error due to the prescaler. For example, suppose that BCLK runs at 10 MHz and that 16 has been chosen for the dividing ratio of the prescaler, then the watchdog timer's period becomes approximately 52.4 ms. The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by writing to the watchdog timer start register (address 000E 16). Figure FA-1 shows the block diagram of the watchdog timer. Figure FA-2 shows the watchdog timer-related registers. With X IN chosen for BCLK Watchdog timer period = prescaler dividing ratio (16 or 128) X watchdog timer count (32768) BCLK With XCIN chosen for BCLK Watchdog timer period = prescaler dividing ratio (2) X watchdog timer count (32768) BCLK

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Watchdog Timer Figure FA-2. Watchdog timer control and start registers Watchdog timer control register Symbol Address When reset WDC 000F 16 000XXXXX 2 FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 High-order bit of watchdog timer WDC7 Bit name Prescaler select bit 0 : Divided by 16 1 : Divided by 128 Watchdog timer start register Symbol Address When reset WDTS 000E 16 Indeterminate W R b7 b0 Function The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to “7FFF16” regardless of whatever value is written. Reserved bit Reserved bit Must always be set to “0” Must always be set to “0” 0 0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC Figure EC-1. Block diagram of DMAC DMAC This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16- bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure EC-1 shows the block diagram of the DMAC. Table EC-1 shows the DMAC specifications. Figure EC-2 to Figure EC-3 show the registers used by the DMAC. Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt priority level. The DMA transfer doesn't affect any interrupts either. If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the number of transfers. For details, see the description of the DMA request bit. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Data bus low-order bits DMA latch high-order bitsDMA latch low-order bits DMA0 source pointer SAR0(20) DMA0 destination pointer DAR0 (20) DMA0 forward address pointer (20) (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Data bus high-order bits /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Address bus /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines DMA1 destination pointer DAR1 (20) DMA1 source pointer SAR1 (20) DMA1 forward address pointer (20) (Note)/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines DMA0 transfer counter reload register TCR0 (16) DMA0 transfer counter TCR0 (16) DMA1 transfer counter reload register TCR1 (16) DMA1 transfer counter TCR1 (16)/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines (addresses 002916, 002816) (addresses 003916, 003816) (addresses 002216 to 002016) (addresses 002616 to 002416) (addresses 003216 to 003016) (addresses 003616 to 003416) Note: Pointer is incremented by a DMA request. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC Item Specification No. of channels 2 (cycle steal method) Transfer memory space • From any address in the 1M bytes space to a fixed address

• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address (Note that DMA-related registers [002016 to 003F16] cannot be accessed) Maximum No. of bytes transferred128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers) DMA request factors (Note) Falling edge of INT0 or INT1 (INT0 can be selected by DMA0, INT1 by DMA1) Timer A0 to timer A4 interrupt requests Timer B0 to timer B2 interrupt requests UART0 transmission and reception interrupt requests UART1 transmission and reception interrupt requests A-D conversion interrupt requests Software triggers Channel priority DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously Transfer unit 8 bits or 16 bits Transfer address direction forward or fixed (forward direction cannot be specified for both source and destination simultaneously) Transfer mode • Single transfer mode After the transfer counter underflows, the DMA enable bit turns to “0”, and the DMAC turns inactive
• Repeat transfer mode After the transfer counter underflows, the value of the transfer counter reload register is reloaded to the transfer counter. The DMAC remains active unless a “0” is written to the DMA enable bit. DMA interrupt request generation timingWhen an underflow occurs in the transfer counter Active When the DMA enable bit is set to “1”, the DMAC is active. When the DMAC is active, data transfer starts every time a DMA transfer request signal occurs. Inactive • When the DMA enable bit is set to “0”, the DMAC is inactive.
• After the transfer counter underflows in single transfer mode At the time of starting data transfer immediately after turning the DMAC active, re the value of one of source pointer and destination pointer - the one specified for the forward direction - is reloaded to the forward direction address pointer,and the value of the transfer counter reload register is reloaded to the transfer counter. Writing to register Registers specified for forward direction transfer are always write enabled. Registers specified for fixed address transfer are write-enabled when the DMA enable bit is “0”. Reading the register Can be read at any time. However, when the DMA enable bit is “1”, reading the register set up as the forward register is the same as reading the value of the forward address pointer. Table EC-1. DMAC specifications Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt priority level. Forward address pointer and load timing for transfer counter

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC Figure EC-2. DMAC-related registers (1) DMAi request cause select register Symbol Address When reset DMiSL(i=0,1) 03B8 16,03BA16 0016 Bit name Function RBit symbol W b7 b6 b5 b4 b3 b2 b1 b0 DMA request cause select bitDSEL0 DSEL1 DSEL2 DSEL3 Software DMA request bitIf software trigger is selected, a DMA request is generated by setting this bit to “1” (When read, the value of this bit is always “0”) DSR DMAi control register Symbol Address When reset DMiCON(i=0,1) 002C 16, 003C16 00000X002 Bit name FunctionBit symbol R W b7 b6 b5 b4 b3 b2 b1 b0 Transfer unit bit select bit0 : 16 bits 1 : 8 bits DMBIT DMASL DMAS DMAE Repeat transfer mode select bit 0 : Single transfer 1 : Repeat transfer DMA request bit (Note 1)0 : DMA not requested 1 : DMA requested 0 : Disabled 1 : Enabled 0 : Fixed 1 : Forward DMA enable bit Source address direction select bit (Note 3) Destination address direction select bit (Note 3) 0 : Fixed 1 : Forward DSD DAD Note 1: DMA request can be cleared by resetting the bit. Note 2: This bit can only be set to “0”. Note 3: Source address direction select bit and destination address direction select bit cannot be set to “1” simultaneously. b3 b2 b1 b0 0 0 0 0 : Falling edge of INT0 / INT1 pin (Note) 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3 0 1 1 0 : Timer A4 0 1 1 1 : Timer B0 1 0 0 0 : Timer B1 1 0 0 1 : Timer B2 1 0 1 0 : UART0 transmit 1 0 1 1 : UART0 receive 1 1 0 0 : UART1 transmit 1 1 0 1 : UART1 receive 1 1 1 0 : A-D conversion 1 1 1 1 : Inhibited Note: Address 03B816 is for INT0; address 03BA16 is for INT1. (Note 2) Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC Figure EC-3. DMAC-related registers (2) b7 b0 b7 b0 (b8) (b15) Function RW

• Transfer counter Set a value one less than the transfer count Symbol Address When reset TCR0 0029 16, 002816 Indeterminate TCR1 0039 16, 003816 Indeterminate DMAi transfer counter (i = 0, 1) Transfer count specification 000016 to FFFF16 (b23) b3 b0 b7 b0 b7 b0 Function RW
• Source pointer Stores the source address Symbol Address When reset SAR0 0022 16 to 002016 Indeterminate SAR1 0032 16 to 003016 Indeterminate DMAi source pointer (i = 0, 1) Transfer count specification 0000016 to FFFFF16 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Symbol Address When reset DAR0 0026 16 to 002416 Indeterminate DAR1 0036 16 to 003416 Indeterminate b3 b0 b7 b0 b7 b0 Function RW
• Destination pointer Stores the destination address DMAi destination pointer (i = 0, 1) Transfer count specification 0000016 to FFFFF16 (b23) Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC Figure EC-4. Example of transfer cycles for a source read (the state of internal bus) BCLK Address bus RD signal WR signal Data bus CPU use CPU use CPU use CPU useSource Source Destination Destination Dummy cycle Dummy cycle (1) 8-bit transfers 16-bit transfers and the source address is even. BCLK Address bus RD signal WR signal Data bus CPU use CPU use CPU use CPU useSource Source Destination Destination Dummy cycle Dummy cycle Source + 1 Source + 1 (2) 16-bit transfers and the source address is odd Note: The same timing changes occur with the respective conditions at the destination as at the source. (1) Transfer cycle The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) and the bus cycle in which the data is written to memory or to the SFR area (destination write). The number of read and write bus cycles depends on the source and destination addresses. (a) Effect of source and destination addresses When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there are one more source read cycle and destination write cycle than when the source and destination both start at even addresses. Figure EC-4 shows the example of the transfer cycles (a state of internal bus) for a source read. For convenience, the destination write cycle is shown as one cycle and the source read cycles for the differ- ent conditions are shown. In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respective conditions to both the destination write cycle and the source read cycle.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC (2) DMAC Transfer Any combination of even or odd transfer read and write addresses is possible. Table EC-2 shows the number of DMAC transfer cycles. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k Table EC-2. No. of DMAC transfer cycles singelchip mode Transfer unit Access address No. of No. of read cycles write cycles 8-bit transfers Even 1 1 (DMBIT="1") Odd 1 1 16-bit transfers Even 1 1 (DMBIT="0") Odd 2 2 Internal memory Internal ROM/RAM SFR area Coefficient j, k

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLD controller FLD Controller The M30218 group has fluorescent display (FLD) drive and control circuits. Table KA-0 shows the FLD controller specifications. Specification

• 52 pins ( 20 pins can switch general purpose port)
• 4 pins ( 4 pins can switch general purpose port) (A driver must be installed externally)
• Used FLD output 28 segment X 28 digit (segment number + digit number ≤ 56)
• Used digit output 40 segment X 16 digit (segment number ≤ 40, digit number ≤ 16)
• Connected to M35501 56 segment X (connect number of M35501) digit (segment number ≤ 56, digit number ≤ number of M35501 X 16)
• Used P4 4 to P47 expansion 52 segment X 16 digit (segment number ≤ 52, digit number ≤ 16)
• 3.2 µs to 819.2 µs (count source XIN/32,10MHz)
• 12.8 µs to 3276.8 µs (count source XIN/128,10MHz)
• 3.2 µs to 819.2 µs (count source XIN/32,10MHz)
• 12.8 µs to 3276.8 µs (count source XIN/128,10MHz)
• Digit interrupt
• FLD blanking interrupt
• Key-scan used digit
• Key-scan used segment
• Digit pulse output function This function automatically outputs digit pulse.
• M35501 connect function The number of digits can be increased easily by using the output of DIM OUT (P97) as CLK for the M35501.
• Toff section generate / not generate function This function does not generate Toff1 section when the connected outputs are the same.
• Gradation display function This function allows each segment to be set for dark or bright display.
• P4 4 to P47 expansion function This function provides 16 lines of digit outputs from four ports by attaching a 4 16 decoder. Item FLD controller port High-breakdown-volt- age output port CMOS port Display pixel number Period Dimmer time Interrupt Key-scan Expand function Table KA-0. FLD controller specifications

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLD controller Figure KA-1. Block Diagram for FLD Control Circuit 03E816035B16 P40/FLD48 P41/FLD49 P42/FLD50 P43/FLD51 P44/FLD52 P45/FLD53 P46/FLD54 P47/FLD55 FLD/P FLD/P FLD/P FLD/P FLD/P FLD/P FLD/P FLD/P 050016 05DF 16 03E116 P10/FLD24 P11/FLD25 P12/FLD26 P13/FLD27 P14/FLD28 P15/FLD29 P16/FLD30 P17/FLD31 Main address bus Local address bus FLD automatic display RAM P60/FLD0 P61/FLD1 P62/FLD2 P63/FLD3 P64/FLD4 P65/FLD5 P66/FLD6 P67/FLD7 035D 16 03E916 P50/FLD8 P51/FLD9 P52/FLD10 P53/FLD11 P54/FLD12 P55/FLD13 P56/FLD14 P57/FLD15 Main data bus Local data bus FLD blanking interrupt FLD digit interrupt FLDC mode register (0350 16) FLD data pointer reload register (035816) FLD data pointer (035816) Timing generator Address decoder 03E416035916 P20/FLD32 P21/FLD33 P22/FLD34 P23/FLD35 P24/FLD36 P25/FLD37 P26/FLD38 P27/FLD39 FLD/P FLD/P FLD/P FLD/P FLD/P FLD/P FLD/P FLD/P 03E516035A16 P30/FLD40 P31/FLD41 P32/FLD42 P33/FLD43 P34/FLD44 P35/FLD45 P36/FLD46 P37/FLD47 FLD/P FLD/P FLD/P FLD/P FLD/P FLD/P FLD/P FLD/P 03E016 P00/FLD16 P01/FLD17 P02/FLD18 P03/FLD19 P04/FLD20 P05/FLD21 P06/FLD22 P07/FLD23 DIG/FLD DIG/FLD DIG/FLD DIG/FLD DIG/FLD DIG/FLD DIG/FLD DIG/FLD DIG/FLD DIG/FLD DIG/FLD DIG/FLD DIG/FLD DIG/FLD DIG/FLD DIG/FLD 035C 03EC 16 FLD/port switch register Digit output set register

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLD controller Figure KA-2. FLDC-related Register(1) F L D C m o d e r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t F L D 6 0 Bit name F u n c t i o n B i t s y m b o l b 6b 5b A u t o m a t i c d i s p l a y c o n t r o l b i t 0 : General-purpose mode 1 : Automatic display modeF L D M 0 F L D M 1 F L D M 2 F L D M 3 D i s p l a y s t a r t b i t 0 : Stop display 1 : Display (start to display by switching “0” to “1”) T s c a n c o n t r o l b i t s 00 : FLD digit interrupt (at rising edge of each digit) 01 : 1 X Tdisp 10 : 2 X Tdisp 11 : 3 X Tdisp 0 : 16 timing mode 1 : 32 timing mode T i m i n g n u m b e r c o n t r o l b i t G r a d a t i o n d i s p l a y m o d e s e l e c t i o n c o n t r o l b i t 0 : Not selecting 1 : Selecting (Note )F L D M 4 F L D M 5 Note : When a gradation display mode is selected, a number of timing is max. 16 timing. (Set the timing number control bit to “0”.) T d i s p c o u n t e r c o u n t s o u r c e s e l e c t i o n b i t 0 : f(XIN)/32 1 : f(XIN)/128F L D M 6 H i g h - b r e a k d o w n v o l t a g e p o r t d r i v a b i l i t y s e l e c t b i t 0 : Drivability strong 1 : Drivability weakF L D M 7 FLD output control register S y m b o lA d d r e s sW h e n r e s e t F L D C O 6 0 Bit name FunctionB i t s y m b o l b7 b6 b5 b4 b3 b2 b1 b0 F L D C O N 7 FLDCON5 FLDCON4 F L D C O N 2 FLDCON0 F L D C O N 6 P44 to P47 FLD output reverse bit P 44 t o P 47 F L D T o f f i s i n v a l i d b i t 0 : Perform normally 1 : Toff is invalid P97 dimmer output control bit 0 : Output normally 1 : Dimmer output C M O S p o r t s : s e c t i o n o f T o f f g e n e r a t e n o t g e n e r a t e b i t 0 : section of Toff does NOT generate 1 : section of Toff generates High-breakdown-voltage ports: section of Toff generate/not generate bit 0 : section of Toff does NOT generate 1 : section of Toff generates Toff2 SET/RESET change bit 0 : gradation display data is reset at Toff2 (set at Toff1) 1 : gradation display data is set at Toff2 (reset at Toff1) W R 0 : Output normally 1 : Reverse output Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”. N o t h i n g i s a s s i g n e d . I n a n a t t e m p t t o w r i t e t o t h i s b i t w r i t e T h e v a l u e i f r e a d t u r n s o u t t o b e T d i s p t i m e s e t r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t T D I S 6 0 Values that can be set b 7 b 0 Counts Tdisp time. Count source is selected by Tdisp counter count source select bit. W R 016 to FF16 Function F L D b l a n k i n g i n t e r r u p t a t f a l l i n g e d g e o f l a s t d i g i t b 3 b 2 W R

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLD controller Figure KA-2A. FLDC-related Register(2) Toff1 time set register Symbol Address When reset TOFF1 0354 16 FF16 W R b7 b0 Function Values that can be set Counts Toff1 time. Count source is selected by Tdisp counter count source select bit. 3 to FF16 Toff2 time set register Symbol Address When reset TOFF2 0356 16 FF16 W R b7 b0 Counts Toff2 time. Count source is selected by Tdisp counter count source select bit. 3 to FF16 FLD data pointer Symbol Address When reset FLDDP 0358 16 indeterminate W R b7 b0 Counts FLD output timing. Set this register to “FLD output data - 1 ”. 1 to 1F16 Note: Reading the FLD data pointer takes out the count at that moment. 0 : Normal port 1 : FLD output port Port P2 FLD / port switch register Symbol Address When reset P2FPR 0359 16 0016 W R b7 b6 b5 b4 b3 b2 b1 b0 P2FPR0 P2FPR2 P2FPR1 P2FPR3 P2FPR4 P2FPR6 P2FPR5 P2FPR7 Port P20 FLD/port switch bit 0 : Normal port 1 : FLD output port Port P21 FLD/port switch bit 0 : Normal port 1 : FLD output port Port P2

2 FLD/port switch bit

0 : Normal port 1 : FLD output port Port P2

3 FLD/port switch bit

0 : Normal port 1 : FLD output port Port P2

4 FLD/port switch bit

0 : Normal port 1 : FLD output port Port P2

5 FLD/port switch bit

0 : Normal port 1 : FLD output port Port P2

6 FLD/port switch bit

0 : Normal port 1 : FLD output port Port P2

7 FLD/port switch bit

Function Values that can be set Function Values that can be set Bit name FunctionBit symbol /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLD controller Figure KA-2B. FLDC-related Register(3) 0 : Normal port 1 : FLD output port Port P3 FLD / port switch register Symbol Address When reset P3FPR 035A 16 0016 W R b7 b6 b5 b4 b3 b2 b1 b0 P3FPR0 P3FPR2 P3FPR1 P3FPR3 P3FPR4 P3FPR6 P3FPR5 P3FPR7 Port P30 FLD/port switch bit 0 : Normal port 1 : FLD output port Port P31 FLD/port switch bit 0 : Normal port 1 : FLD output port Port P3 0 : Normal port 1 : FLD output port Port P3 0 : Normal port 1 : FLD output port Port P3 0 : Normal port 1 : FLD output port Port P3 0 : Normal port 1 : FLD output port Port P3 0 : Normal port 1 : FLD output port Port P3 Bit name FunctionBit symbol /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines 0 : Normal port 1 : FLD output port Port P4 FLD / port switch register Symbol Address When reset P4FPR 035B 16 0016 W R b7 b6 b5 b4 b3 b2 b1 b0 P4FPR0 P4FPR2 P4FPR1 P4FPR3 P4FPR4 P4FPR6 P4FPR5 P4FPR7 Port P40 FLD/port switch bit 0 : Normal port 1 : FLD output port Port P41 FLD/port switch bit 0 : Normal port 1 : FLD output port Port P4 0 : Normal port 1 : FLD output port Port P4 0 : Normal port 1 : FLD output port Port P4 0 : Normal port 1 : FLD output port Port P4 0 : Normal port 1 : FLD output port Port P4 0 : Normal port 1 : FLD output port Port P4 Bit name FunctionBit symbol /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines 0 : FLD output 1 : Digit output Port P5 digit output set register Symbol Address When reset P5DOR 035C 16 0016 W R b7 b6 b5 b4 b3 b2 b1 b0 P5DOR0 P5DOR2 P5DOR1 P5DOR3 P5DOR4 P5DOR6 P5DOR5 P5DOR7 Port P50 FLD/digit switch bit 0 : FLD output 1 : Digit output Port P51 FLD/digit switch bit 0 : FLD output 1 : Digit output Port P5

2 FLD/digit switch bit

0 : FLD output 1 : Digit output Port P5

3 FLD/digit switch bit

0 : FLD output 1 : Digit output Port P5

4 FLD/digit switch bit

0 : FLD output 1 : Digit output Port P5

5 FLD/digit switch bit

0 : FLD output 1 : Digit output Port P5

6 FLD/digit switch bit

0 : FLD output 1 : Digit output Port P5

7 FLD/digit switch bit

Bit name FunctionBit symbol /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLD controller Figure KA-2C. FLDC-related Register(4) 0 : FLD output 1 : Digit output Port P6 digit output set register Symbol Address When reset P6DOR 035D 16 0016 W R b7 b6 b5 b4 b3 b2 b1 b0 P6DOR0 P6DOR2 P6DOR1 P6DOR3 P6DOR4 P6DOR6 P6DOR5 P6DOR7 Port P60 FLD/digit switch bit 0 : FLD output 1 : Digit output Port P61 FLD/digit switch bit 0 : FLD output 1 : Digit output Port P6 0 : FLD output 1 : Digit output Port P6 0 : FLD output 1 : Digit output Port P6 0 : FLD output 1 : Digit output Port P6 0 : FLD output 1 : Digit output Port P6 0 : FLD output 1 : Digit output Port P6 Bit name FunctionBit symbol /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLD controller Figure KA-3. Segment/Digit Setting Example FLD automatic display pins P0 to P6 are the pins capable of automatic display output for the FLD. The FLD start operating by setting the automatic display control bit (bit 0 at address 035016) to “1”. There is the FLD output function that outputs RAM contents from the port every timing or the digit output function that drives the port high with digit timing. The FLD can be displayed using the FLD output for the segments and the digit or FLD output for the digits. When using the FLD output for the digits, be sure to write digit display patterns to the RAM in advance. The remaining segment and digit lines can be used as general-purpose ports. Settings of each port are shown below. Table KA-1. Pins in FLD Automatic Display Mode Port Name Automatic Display Pins Setting Method P5, P6 FLD 0 to FLD15 P0, P1 FLD 16 to FLD31 P2, P3, FLD 32 to FLD51 P44 to P43 P44 to P47 FLD 52 to FLD55 The individual bits of the digit output set register (address 035C16, 035D 16) can set each pin either FLD port (“0”) or digit port (“1”). When the pins are set for the digit port, the digit pulse output func- tion is enabled, so the digit pulses can always be output regardless the value of FLD automatic display RAM. FLD exclusive use port (automatic display control bit (bit 0 of ad- dress 0350 16)=“1”) The individual bits of the FLD/port switch register (addresses 0359 16 to 035B16) can set each pin to either FLD port (“1”) or gen- eral-purpose port (“0”). The individual bits of the FLD/port switch register (address 035B 16) can set each pin to either FLD port (“1”) or general-purpose port (“0”). The digit pulse output function turns to available, and the digit pulse can output by setting of the FLD output set register (address 0351 16). The port output format is the CMOS output. When using the port as a display pin, a driver must be installed externally. Port P5 Port P0 Number of segments Number of digits Port P6 Port P1 Setting example 1 Shown below is a register setup example where only FLD output is used. In this case, the digit display output pattern must be set in the FLD automatic display RAM in advance. FLD 32(SEG output) FLD 33(SEG output) FLD 34(SEG output) FLD 35(SEG output) FLD 36(SEG output) FLD 37(SEG output) FLD 38(SEG output) FLD 39(SEG output) FLD 16(SEG output) FLD 17(SEG output) FLD 18(SEG output) FLD 19(SEG output) FLD 20(SEG output) FLD 21(SEG output) FLD 22(SEG output) FLD 23(SEG output) FLD 0(DIG output) FLD 1(DIG output) FLD 2(DIG output) FLD 3(DIG output) FLD 4(DIG output) FLD 5(DIG output) FLD 6(DIG output) FLD 7(DIG output) FLD 8(DIG output) FLD 9(DIG output) FLD 10(DIG output) FLD 11(DIG output) FLD 12(DIG output) FLD 13(DIG output) FLD 14(DIG output) FLD 15(DIG output) FLD 24(SEG output) FLD 25(SEG output) FLD 26(SEG output) FLD 27(SEG output) FLD 28(SEG output) FLD 29(SEG output) FLD 30(SEG output) FLD 31(SEG output) Port P2 FLD 40(SEG output) FLD 41(SEG output) FLD 42(SEG output) FLD 43(SEG output) FLD 44(SEG output) FLD 45(SEG output) FLD 46(SEG output) FLD 47(SEG output) Port P3 FLD 48(SEG output) FLD 49(SEG output) FLD 50(SEG output) FLD 51(SEG output) FLD 52(port output) FLD 53(port output) FLD 54(port output) FLD 55(port output) Port P4 Port P5 Port P0 Port P6 Port P1 Setting example 2 Shown below is a register setup example where both FLD output and digit waveform output are used. In this case, because the digit display output is automatically generated, there is no need to set the display pattern in the FLD automatic display RAM. FLD 32(SEG output) FLD 33(SEG output) FLD 34(SEG output) FLD 35(SEG output) FLD 36(SEG output) FLD 37(SEG output) FLD 38(SEG output) FLD 39(SEG output) FLD 16(SEG output) FLD 17(SEG output) FLD 18(SEG output) FLD 19(SEG output) FLD 20(SEG output) FLD 21(SEG output) FLD 22(SEG output) FLD 23(SEG output) FLD 0(DIG output) FLD 1(DIG output) FLD 2(DIG output) FLD 3(DIG output) FLD 4(DIG output) FLD 5(DIG output) FLD 6(DIG output) FLD 7(DIG output) FLD 8(DIG output) FLD 9(DIG output) FLD 10(DIG output) FLD 11(DIG output) FLD 12(SEG output) FLD 13(SEG output) FLD 14(SEG output) FLD 15(SEG output) FLD 24(SEG output) FLD 25(SEG output) FLD 26(SEG output) FLD 27(SEG output) FLD 28(SEG output) FLD 29(SEG output) FLD 30(SEG output) FLD 31(SEG output) Port P2 FLD 40(SEG output) FLD 41(SEG output) FLD 42(SEG output) FLD 43(SEG output) FLD 44(port output) FLD 45(port output) FLD 46(port output) FLD 47(port output) Port P3 FLD 48(port output) FLD 49(port output) FLD 50(port output) FLD 51(port output) FLD 52(port output) FLD 53(port output) FLD 54(port output) FLD 55(port output) Port P4 DIG output : This output is connected to digit of the FLD. SEG output : This output is connected to segment of the FLD. Port out put : This output is general-purpose port ( used program). DIG output : This output is connected to digit of the FLD. SEG output : This output is connected to segment of the FLD. Port output : This output is general-purpose port ( used program). The contents of digit output set register (035C16, 035D16) FLD/port switch register (035916, 035B16) Number of segments Number of digits The contents of digit output set register (035C16, 035D16) FLD/port switch register (0359 16, 035B16)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLD controller FLD automatic display RAM The FLD automatic display RAM uses the 224 bytes of addresses 050016 to 05DF16. For FLD, the 3 modes of 16-timing ordinary mode, 16-timing•gradation display mode and 32-timing mode are available depending on the number of timings and the use/not use of gradation display. The automatic display RAM in each mode is as follows: (1) 16-timing•Ordinary Mode This mode is used when the display timing is 16 or less. The 112 bytes of addresses 057016 to 05DF16 are used as a FLD display data store area. Because addresses 050016 to 056F16 are not used as the automatic display RAM, they can be the ordinary RAM. (2) 16-timing•Gradation Display Mode This mode is used when the display timing is 16 or less, in which mode each segment can be set for dark or bright display. The 224 bytes of addresses 0500 16 to 05DF16 are used. The 112 bytes of addresses 057016 to 05DF16 are used as an FLD display data store area, while the 112 bytes of addresses 050016 to 056F16 are used as a gradation display control data store area. (3) 32-timing Mode This mode is used when the display timing is 16 or greater. This mode can be used for up to 32-timing. The 224 bytes of addresses 0500 16 to 05DF16 are used as an FLD display data store area. The FLD data pointer (address 035816) is a register to count display timings. This pointer has a reload register and when the terminal count is reached, it starts counting over again after being reloaded with the initial count. Make sure the timing count – 1 is set to the FLD data pointer. When writing data to this address, the data is written to the FLD data pointer reload register; when reading data from this address, the value in the FLD data pointer is read. Figure KA-4. FLD Automatic Display RAM Assignment 16-timing•ordinary mode 05DF 16 057016 050016 05DF 16 050016 05DF 16 057016 050016 16-timing•gradation display mode 32-timing mode 1 to 32 timing display data stored area Gradation display control data stored area 1 to 16 timing display data stored area 1 to 16 timing display data stored area Not used

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLD controller Data setup (1) 16-timing•Ordinary Mode The area of addresses 057016 to 05DF16 are used as a FLD automatic display RAM. When data is stored in the FLD automatic display RAM, the last data of FLD port P4 is stored at address 057016, the last data of FLD port P3 is stored at address 058016, the last data of FLD port P2 is stored at address 059016, the last data of FLD port P1 is stored at address 05A016, the last data of FLD port P0 is stored at address 05B016, the last data of FLD port P5 is stored at address 05C016, and the last data of FLD port P6 is stored at address 05D016, to assign in sequence from the last data respectively. The first data of the FLD port P4, P3, P2, P1, P0, P5, and P6 is stored at an address which adds the value of (the timing number – 1) to the corresponding address 057016, 058016, 059016, 05A016, 05B016, 05C016 and 05DF16. Set the FLD data pointer reload register to the value given by the number of digits – 1. (2) 16-timing•Gradation Display Mode Display data setting is performed in the same way as that of the 16-timing•ordinary mode. Gradation display control data is arranged at an address resulting from subtracting 0070 16 from the display data store address of each timing and pin. Bright display is performed by setting “0”, and dark display is performed by setting “1” . (3) 32-timing Mode The area of addresses 050016 to 05DF16 are used as a FLD automatic display RAM. When data is stored in the FLD automatic display RAM, the last data of FLD port P4 is stored at address 050016, the last data of FLD port P3 is stored at address 052016, the last data of FLD port P2 is stored at address 054016, the last data of FLD port P1 is stored at address 056016, the last data of FLD port P0 is stored at address 058016, the last data of FLD port P5 is stored at address 05A016, and the last data of FLD port P6 is stored at address 05C016, to assign in sequence from the last data respectively. The first data of the FLD port P4, P3, P2, P0, P1, P5, and P6 is stored at an address which adds the value of (the timing number – 1) to the corresponding address 050016, 052016, 054016, 056016, 058016, 05A016 and 05C016. Set the FLD data pointer reload register to the value given by the number of digits - 1. Figure KA-5. Example of Using the FLD Automatic Display RAM in 16-timing•Ordinary Mode Number of timing: 8 (FLD data pointer reload register = 7) Address 058F16 057116 057216 057316 057416 057516 057616 057716 057816 057916 057A16 057B16 057C 16 057D 16 057E16 057F16 058016 058116 058216 058316 058416 058516 058616 058716 058816 058916 058A16 058B16 058C 16 058D 16 058E16 059016 059116 059216 059316 059416 059516 059616 059716 059816 059916 059A16 059B16 059C 16 059D 16 059E16 059F16 05A116 05A216 05A316 05A416 05A516 05A616 05A716 05A816 05A916 05AA 16 05AB 16 05AC 16 05AD 16 05AE 16 05AF 16 05A016

057016 The last timing

(The last data of FLDP4) Timing for start (The first data of FLDP4) The last timing (The last data of FLDP3) Timing for start (The first data of FLDP3) The last timing (The last data of FLDP2) Timing for start (The first data of FLDP2) The last timing (The last data of FLDP1) Timing for start (The first data of FLDP1) 76543210 Bit Address 05B116 05B216 05B316 05B416 05B516 05B616 05B716 05B816 05B916 05BA 16 05BB 16 05BC 16 05BD 16 05BE 16 05BF 16 05B016 The last timing (The last data of FLDP0) FLDP0 data area Timing for start (The first data of FLDP0) 76543210 Bit 05C1 16 05C2 16 05C3 16 05C4 16 05C5 16 05C6 16 05C7 16 05C8 16 05C9 16 05CA 16 05CB 16 05CC 16 05CD 16 05CE 16 05CF 16 05C0 16 05D1 16 05D2 16 05D3 16 05D4 16 05D5 16 05D6 16 05D7 16 05D8 16 05D9 16 05DA 16 05DB 16 05DC 16 05DD 16 05DE 16 05DF 16 05D0 16 The last timing (The last data of FLDP5) FLDP5 data area Timing for start (The first data of FLDP5) The last timing (The last data of FLDP6) FLDP6 data area Timing for start (The first data of FLDP6) FLDP1 data area FLDP2 data area FLDP4 data area FLDP3 data area

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLD controller Figure KA-6. Example of Using the FLD Automatic Display RAM in 16-timing•Gradation Display Mode Number of timing: 15 (FLD data pointer reload register = 14) Address 058F16 057116 057216 057316 057416 057516 057616 057716 057816 057916 057A16 057B16 057C 16 057D 16 057E16 057F16 058016 058116 058216 058316 058416 058516 058616 058716 058816 058916 058A16 058B16 058C 16 058D 16 058E16 059016 059116 059216 059316 059416 059516 059616 059716 059816 059916 059A16 059B16 059C 16 059D 16 059E16 059F16 05A116 05A216 05A316 05A416 05A516 05A616 05A716 05A816 05A916 05AA 16 05AB 16 05AC 16 05AD 16 05AE 16 05AF 16 05A016 05B116 05B216 05B316 05B416 05B516 05B616 05B716 05B816 05B916 05BA 16 05BB 16 05BC 16 05BD 16 05BE 16 05BF 16 05B016 (The last data of FLDP4) 76543210 Bit The last timing (The last data of FLDP3) The last timing (The last data of FLDP2) The last timing (The last data of FLDP1) The last timing (The last data of FLDP0) FLDP4 data area FLDP3 data area FLDP2 data area FLDP1 data area FLDP0 data area 05C1 16 05C2 16 05C3 16 05C4 16 05C5 16 05C6 16 05C7 16 05C8 16 05C9 16 05CA 16 05CB 16 05CC 16 05CD 16 05CE 16 05CF 16 05C0 16 The last timing (The last data of FLDP5) FLDP5 data area 05D1 16 05D2 16 05D3 16 05D4 16 05D5 16 05D6 16 05D7 16 05D8 16 05D9 16 05DA 16 05DB 16 05DC 16 05DD 16 05DE 16 05DF 16 05D0 16 The last timing (The last data of FLDP6) FLDP6 data area Address 051F16 050116 050216 050316 050416 050516 050616 050716 050816 050916 050A16 050B16 050C 16 050D 16 050E16 050F16 051016 051116 051216 051316 051416 051516 051616 051716 051816 051916 051A16 051B16 051C 16 051D 16 051E16 052016 052116 052216 052316 052416 052516 052616 052716 052816 052916 052A16 052B16 052C 16 052D 16 052E16 052F16 053116 053216 053316 053416 053516 053616 053716 053816 053916 053A16 053B16 053C 16 053D 16 053E16 053F16 053016 054116 054216 054316 054416 054516 054616 054716 054816 054916 054A16 054B16 054C 16 054D 16 054E16 054F16 054016

050016 The last timing

(The last data of FLDP4) 76543210 Bit The last timing (The last data of FLDP3) The last timing (The last data of FLDP2) The last timing (The last data of FLDP1) The last timing (The last data of FLDP0) FLDP4 gradation display data area FLDP3 gradation display data area FLDP2 gradation display data area FLDP1 gradation display data area FLDP0 gradation display data area 055116 055216 055316 055416 055516 055616 055716 055816 055916 055A16 055B16 055C 16 055D 16 055E16 055F16

055016 The last timing

(The last data of FLDP5) FLDP5 gradation display data area 056116 056216 056316 056416 056516 056616 056716 056816 056916 056A16 056B16 056C 16 056D 16 056E16 056F16

056016 The last timing

(The last data of FLDP6) FLDP6 gradation display data area Timing for start (The first data of FLDP4) Timing for start (The first data of FLDP3) Timing for start (The first data of FLDP2) Timing for start (The first data of FLDP1) Timing for start (The first data of FLDP0) Timing for start (The first data of FLDP5) Timing for start (The first data of FLDP6) Timing for start (The first data of FLDP4) Timing for start (The first data of FLDP3) Timing for start (The first data of FLDP2) Timing for start (The first data of FLDP1) Timing for start (The first data of FLDP0) Timing for start (The first data of FLDP5) Timing for start (The first data of FLDP6)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLD controller Figure KA-7. Example of Using the FLD Automatic Display RAM in 32-timing Mode Number of timing: 20 (FLD data pointer reload register = 19) Address 058F16 057116 057216 057316 057416 057516 057616 057716 057816 057916 057A16 057B16 057C 16 057D 16 057E16 057F16 058016 058116 058216 058316 058416 058516 058616 058716 058816 058916 058A16 058B16 058C 16 058D 16 058E16 059016 059116 059216 059316 059416 059516 059616 059716 059816 059916 059A16 059B16 059C 16 059D 16 059E16 059F16 05A116 05A216 05A316 05A416 05A516 05A616 05A716 05A816 05A916 05AA 16 05AB 16 05AC 16 05AD 16 05AE 16 05AF 16 05A016 05B116 05B216 05B316 05B416 05B516 05B616 05B716 05B816 05B916 05BA 16 05BB 16 05BC 16 05BD 16 05BE 16 05BF 16 05B016 057016 76543210 Bit FLDP0 data area 05C1 16 05C2 16 05C3 16 05C4 16 05C5 16 05C6 16 05C7 16 05C8 16 05C9 16 05CA 16 05CB 16 05CC 16 05CD 16 05CE 16 05CF 16 05C0 16 The last timing (The last data of FLDP5) FLDP5 data area 05D1 16 05D2 16 05D3 16 05D4 16 05D5 16 05D6 16 05D7 16 05D8 16 05D9 16 05DA 16 05DB 16 05DC 16 05DD 16 05DE 16 05DF 16 05D0 16 The last timing (The last data of FLDP6) FLDP6 data area Address 051F16 050116 050216 050316 050416 050516 050616 050716 050816 050916 050A16 050B16 050C 16 050D 16 050E16 050F16 051016 051116 051216 051316 051416 051516 051616 051716 051816 051916 051A16 051B16 051C 16 051D 16 051E16 052016 052116 052216 052316 052416 052516 052616 052716 052816 052916 052A16 052B16 052C 16 052D 16 052E16 052F16 053116 053216 053316 053416 053516 053616 053716 053816 053916 053A16 053B16 053C 16 053D 16 053E16 053F16 053016 054116 054216 054316 054416 054516 054616 054716 054816 054916 054A16 054B16 054C 16 054D 16 054E16 054F16 054016 (The last data of FLDP4) 76543210 Bit The last timing (The last data of FLDP3) The last timing (The last data of FLDP2) The last timing (The last data of FLDP1) The last timing (The last data of FLDP0) FLDP4 data area FLDP3 data area FLDP2 data area FLDP1 data area 055116 055216 055316 055416 055516 055616 055716 055816 055916 055A16 055B16 055C 16 055D 16 055E16 055F16 055016 056116 056216 056316 056416 056516 056616 056716 056816 056916 056A16 056B16 056C 16 056D 16 056E16 056F16 056016 Timing for start (The first data of FLDP0) Timing for start (The first data of FLDP5) Timing for start (The first data of FLDP6) Timing for start (The first data of FLDP4) Timing for start (The first data of FLDP3) Timing for start (The first data of FLDP2) Timing for start (The first data of FLDP1)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLD controller Figure KA-11. FLDC Timing Toff1 Tdisp Toff1 Toff2 Tdisp

• Grayscale display mode is not selected (Address 035016 bit 5 = “0”)
• Grayscale display mode is selected and set for bright display (Address 035016 bit 5 = “1” and the corresponding grayscale display control data = “0”) Low output period for blurring prevention Display output period Display output period Low output period for blurring prevention
• Grayscale display mode is selected and set for dark display (Address 0350 16 bit 5 = “1” and the corresponding grayscale display control data = “1”) Low output period for dark display Timing setting Each timing is set by the FLDC mode register, Tdisp time set register, Toff1 time set register, and Toff2 time set register.
• Tdisp time setting The Tdisp time represents the length of display timing. In non-gradation display mode, it consists of a FLD display output period and a Toff1 time. In gradation display mode, it consists of the display output period and Toff1 time plus a low signal output period for dark display. Set the Tdisp time by the Tdisp counter count source select bit of the FLDC mode register and the Tdisp time set register. Supposing that the value of the Tdisp time set register is n, the Tdisp time is represented as Tdisp = (n+1) x t (t: count source). When the Tdisp counter count source select bit of the FLDC mode register is “0” and the value of the Tdisp time set register is 200 (C8 16), the Tdisp time is: Tdisp = (200+1) x 3.2 (at XIN= 10 MHz) = 643 µs. When reading the Tdisp time set register, the value in the counter is read out.
• Toff1 time setting The Toff1 time represents a non-output (low signal output) time to prevent blurring of FLD, and to dim the display. Use the Toff1 time set register to set this Toff1 time. Make sure the value set to Toff1 is smaller than Tdisp and Toff2. Supposing that the value of the Toff1 time set register is n1, the Toff1 time is represented as Toff1 = n1 x t. When the Tdisp counter count source select bit of the FLDC mode register is “0” and the value of the Toff1 time set register is 30 (1E 16), Toff1 = 30 x 3.2 (at XIN = 10 MHz) = 96 µs.
• Toff2 time setting The Toff2 time is provided for dark display. For bright display, the FLD display output remains effective until the counter that is counting Tdisp reaches the terminal count. For dark display, however, “L” (or “off”) signal is output when the counter that is counting Toff2 reaches the terminal count. This Toff2 time setting is valid only for FLD ports which are in the gradation display mode and whose gradation display control RAM value is “1” . Set the Toff2 time by the Toff2 time set register. Make sure the value set to Toff2 is smaller than Tdisp but larger than Toff1. Supposing that the value of the Toff2 time set register is n2, the Toff2 time is repre- sented as Toff2 = n2 x t. When the Tdisp counter count source select bit of the FLDC mode register is “0” and the value of the Toff2 time set register is 180 (B4 16), Toff2 = 180 x 3.2 (at XIN = 10 MHz) = 576 µs.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLD controller Figure KA-12A. Timing using digit interrupt FLD digit output Tdisp Repeat synchronous Tn Tn-1 Tn-2 T4 T3 T2 T1 Tn Tn-1 Tn-2 T4 Toff1 FLD digit interrupt generated at the rising edge of digit ( each timing) FLD automatic display start Automatic display starts by setting both the automatic display control bit (bit 0 of address 035016) and the display start bit (bit 1 of address 035016) to “1”. The RAM content at a location apart from the start address of the automatic display RAM for each port by (FLD data pointer (address 035816) – 1) is output to each port. The FLD data pointer (address 035816) counts down in the Tdisp interval. When the count “FF16” is reached, the pointer is reloaded and starts counting over again. Before setting the display start bit (bit 1 of address 035016) to “1”, be sure to set the FLD/port switch register, FLD/DIG switch register, FLDC mode register, Tdisp time set register, Toff1 time set register, Toff2 time set register, and FLD data pointer. During FLD automatic display, bit 1 of the FLDC mode register (address 0350 16) always keeps “1”, and FLD automatic display can be interrupted by writing “0” to bit 1. Key-scan and interrupt Either a FLD digit interrupt or FLD blanking interrupt can be selected using the Tscan control bits (bits 2, 3 of address 0350 16). The FLD digit interrupt is generated when the Toff1 time in each timing expires (at rising edge of digit output). Key scanning that makes use of FLD digits can be achieved using each FLD digit interrupt. To use FLD digit interrupts for key scanning, follow the procedure described below. (1) Read the port value each time the interrupt occurs. (2) The key is fixed on the last digit interrupt. The digit positions output can be determined by reading the FLD data pointer (address 0358 16).

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLD controller Figure KA-12B. Timing using FLD blanking interrupt Tdisp Tscan Tn Tn-1 Tn-2 T4 T3 T2 T1 Tn Tn-1 Tn-2 Segment setting by software FLD blanking interrupt generated at the falling of edge of the last digit FLD digit output Repeat synchronous The FLD blanking interrupt is generated when the FLD data pointer (address 035816) reaches “FF16”. The FLD automatic display output is turned off for a duration of 1 x Tdisp, 2 x Tdisp, or 3 x Tdisp depending on post-interrupt settings. During this time, key scanning that makes use of FLD segments can be achieved. When a key-scan is performed with the segment during key-scan blanking period Tscan, take the following sequence: 1. Write “0” to bit 0 of the FLDC mode register (address 035016). 2. Set the port corresponding to the segment for key-scan to the output port. 3. Perform the key-scan. After the key-scan is performed, write “1” to bit 0 of FLDC mode register (address 035016).

• Note: When performing a key-scan according to the above steps 1 to 4, take the following points into consideration. 1. Do not set “0” in bit 1 of the FLDC mode register (address 035016). 2. Do not set “1” in the ports corresponding to digits.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLD controller P44 to P47 Expansion Function P44 to P47 are CMOS output-type ports. FLD digit outputs can be increased as many as 16 lines by con- necting a 4-bit to 16-bit decoder to these ports. P44 to P47 have the function to allow for connection to a 4- bit to 16-bit decoder. (1) P44 to P47 Toff invalid Function This function disables the Toff1 time and Toff2 time and outputs display data for the duration of Tdisp. (See Figure KA-13.) This can be accomplished by setting the P44 to P47 Toff disable bit (address 035016 bit 2) to “1”. Unlike the Toff section generate/not generate function, this function disables all display data. (2) Dimmer signal output Function This function allows a dimmer signal creation signal to be output from DIMOUT (P97). The dimmer function can be materialized by controlling the decoder with this signal. (See Figure KA-13.) This function can be set by writing P9 7 dimmer output control bit (bit 4 of address 035116) to “1”. (3) P44 to P47 FLD Output Reverse Bit P44 to P47 are provided with a function to reverse the polarity of the FLD output. This function is useful in adjusting the polarity when using an externally installed driver. The output polarity can be reversed by setting bit 0 of the FLD output control register (address 0351 16) to “1” . Figure KA-13. P4 to P47 FLD Output pulses Tdisp Toff2 Toff1 For dimmer signal DIMOUT(P9 7) FLD output

• Grayscale display mode is not selected
• Grayscale display mode is selected and set for bright display (grayscale display control data = “0”)
• Grayscale display mode is selected and set for dark display (grayscale display control data = “1”)
• Grayscale display mode is selected and Toff2 SET/RESET bit is “1” (grayscale display control data = “1”) Output selecting P4 4 to P47 Toff invalid

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLD controller Toff2 SET/RESET change bit In gradation display mode, the values set by the Toff2 time set register (TOFF2) are effective. When the FLD output control register (bit 7 of address 035116 ) in the initial state = “0”, RAM data is output to the FLD output ports (SET) at the time that is set by TOFF1 and is turned to “0” (RESET) at the time that is set by TOFF2. When bit 7 = “1”, RAM data is output (SET) at the time that is set by TOFF2 and is turned to “0” (RESET) when the Tdisp time expires. Toff section generate/not generate Function The function is for reduction of useless noises which generated as every switching of ports, because of the combined capacity of among FLD ports. In case the continuous data output to each FLD ports, the Toff1 section of the continuous parts is not generated. (See Figure KA-15) If it needs Toff1 section on FLD pulses, set “CMOS ports: section of Toff generate / not generate bit” to “1” and set “high-breakdown-voltage ports: section of Toff generate / not generate bit” to “1”. High-breakdown- voltage ports (P5, P6, P3, P2, P1, P0, P40 to P43, total 52 pins) generate Toff1 section, by setting “high- breakdown-voltage ports: section of Toff generate / not generate bit” to “1”. The CMOS ports ( P44 to P47, total 4 pins ) generate Toff1 section, by setting “high-breakdown-voltage ports: section of Toff generate / not generate bit” to “1”. Fig. KA-15. Toff Section Generated/not generated Function P1X P2X P1X P2X “H” output Output waveform when “high- breakdown-voltage ports: section of Toff generate/not generate bit”(bit 6 of 035116) is “0”. Tdisp Toff1 Section of Toff1 is not generated because of output is same. Output waveform when “high- breakdown-voltage ports: section of Toff generate/not generate bit”(bit 6 of 03511 6) is “1”. “H” output “H” output “H” output “H” output “H” output “H” output “H” output “H” output “H” output “H” output “H” output “L” output “L” output “L” output “L” output Section of Toff1 is not generated because of output is same.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLD controller Fig. KA-16. Digit Pulses Output Function Digit pulses output Function P50 to P57 and P60 to P67 allow digit pulses to be output using the FLD/digit switch register. Set the digit output set register by writing as many consecutive 1s as the timing count from P60. The contents of FLD automatic display RAM for the ports that have been selected for digit output are disabled, and the pulse shown in Figure KA-16 is output automatically. In gradation display mode use, Toff2 time becomes effective for the port which selected digit output. Because the contents of FLD automatic display RAM are disabled, the segment data can be changed easily even when segment data and digit data coexist at the same address in the FLD automatic display RAM. This function is effective in 16-timing normal mode and 16-timing gradation display mode. If a value is set exceeding the timing count (FLD data pointer reload register's set value + 1) for any port, the output of such port is “L”. Low-order 4bits of the data pointer FE D C B A 0 1 23 4 567 8 9 P57 P56 P55 P54 P53 P52 P51 P50 P67 P66 P65 P64 P63 P62 P61 P60 Tdisp Toff1

t Mitsubishi microcomputers M30218 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer Timer There are eight 16-bit timers. These timers can be classified by function into timers A (five) and timers B (three). All these timers function independently. Figures FB-1 show the block diagram of timers. Figure FB-1. Timer block diagram

• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Timer mode
• Pulse width measuring mode
• Timer mode
• Pulse width measuring mode
• Timer mode
• Pulse width measuring mode TA0 IN/ TA3 OUT TA1 IN/ TA4 OUT TA2 IN/ TA0 OUT TA3 IN/ TA1 OUT TA4 IN/ TA2 OUT TB0 IN TB1 IN TB2 IN Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 f1 f8 f32 fc32 Timer A0 interrupt Timer A1 interrupt Timer A2 interrupt Timer A3 interrupt Timer A4 interrupt Timer B0 interrupt Timer B1 interrupt Timer B2 interrupt Noise filter Noise filter Noise filter Noise filter Noise filter Noise filter Noise filter Noise filter 1/32 fC32 f32 XIN XCIN Clock prescaler reset flag (bit 7 at address 038116) set to “1” Reset Clock prescaler

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Timer A Figure FB-2 shows the block diagram of timer A. Figures FB-3 to FB-5 show the timer A-related registers. Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode. Timer A has the four operation modes listed as follows:

• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer's over flow.
• One-shot timer mode: The timer stops counting when the count reaches “0000 16”.
• Pulse width modulation (PWM) mode: The timer outputs pulses of a given width. Figure FB-2. Block diagram of timer A Figure FB-3. Timer A-related registers (1) Counter (16) Count start flag (Address 038016) Up count/down count TAi Addresses TAj TAk TAiOUT Timer A0 038716 038616 Timer A4 Timer A1 Timer A3 Timer A1 038916 038816 Timer A0 Timer A2 Timer A4 Timer A2 038B16 038A16 Timer A1 Timer A3 Timer A0 Timer A3 038D16 038C 16 Timer A2 Timer A4 Timer A1 Timer A4 038F16 038E16 Timer A3 Timer A0 Timer A2 Always down count except in event counter mode Reload register (16) L o w - o r d e r b i t s High-order 8 bits C l o c k s o u r c e s e l e c t i o n
• T i m e r g a t e f u n c t i o n
• T i m e r O n e s h o t P W M E x t e r n a l t r i g g e r TAiIN (i = 0 to 4) TB2 overflow
• E v e n t c o u n t e r fC C l o c k s e l e c t i o n T A j o v e r f l o w j i N o t e h o w e v e r t h a t j w h e n i P u l s e o u t p u t T o g g l e f l i p - f l o p T A iO U T i t o Data bus low-order bits Data bus high-order bits Up/down flag D o w n c o u n t (Address 038416) T A k o v e r f l o w k i N o t e h o w e v e r t h a t k w h e n i P o l a r i t y s e l e c t i o n Timer Ai mode register Symbol Address When reset TAiMR(i=0 to 4) 039616 to 039A16 0016 Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode b1 b0 TCK1 MR3 MR2 MR1 TMOD1 MR0 TMOD0 TCK0 Function varies with each operation mode Count source select bit (Function varies with each operation mode) Operation mode select bit /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Figure FB-4. Timer A-related registers (2) Timer A4 up/down flag Timer A3 up/down flag Timer A2 up/down flag Timer A1 up/down flag Timer A0 up/down flag Timer A2 two-phase pulse signal processing select bit Timer A3 two-phase pulse signal processing select bit Timer A4 two-phase pulse signal processing select bit Symbol Address When reset UDF 0384 16 0016 T A 4 P T A 3 P T A 2 P U p / d o w n f l a g B i t n a m e FunctionB i t s y m b o l WR b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 TA4UD TA3UD TA2UD TA1UD TA0UD 0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled When not using the two-phase pulse signal processing function, set the select bit to “0” Symbol Address When reset TABSR 0380 16 0016 Count start flag B i t n a m e FunctionB i t s y m b o l WR b7 b6 b5 b4 b3 b2 b1 b0 Timer B2 count start flag Timer B1 count start flag Timer B0 count start flag Timer A4 count start flag Timer A3 count start flag Timer A2 count start flag Timer A1 count start flag Timer A0 count start flag0 : Stops counting 1 : Starts counting T B 2 S TB1S T B 0 S T A 4 S TA3S T A 2 S T A 1 S TA0S Symbol Address When reset TA0 0387 16,038616 Indeterminate TA1 0389 16,038816 Indeterminate TA2 038B 16,038A16 Indeterminate TA3 038D 16,038C16 Indeterminate TA4 038F 16,038E16 Indeterminate b 7 b 0b 7 b 0 ( b 1 5 ) ( b 8 ) T i m e r A i r e g i s t e r ( N o t e ) WR

• T i m e r m o d e0 0 0 01 6 t o F F F F C o u n t s a n i n t e r n a l c o u n t s o u r c e Function Values that can be set
• E v e n t c o u n t e r m o d e C o u n t s p u l s e s f r o m a n e x t e r n a l s o u r c e o r t i m e r o v e r f l o t o F F F
• O n e - s h o t t i m e r m o d e0 0 0 01 6 t o F F F F1 C o u n t s a o n e s h o t w i d t h
• P u l s e w i d t h m o d u l a t i o n m o d e ( 1 6 - b i t P W M ) F u n c t i o n s a s a b i t p u l s e w i d t h m o d u l a t o r 0016 to FE16 (Both high-order and low-order addresses) 0 0 0 01 6 t o F F F E1 N o t e : R e a d a n d w r i t e d a t a i s i n 1 6 - b i t u n i t s .
• P u l s e w i d t h m o d u l a t i o n m o d e ( 8 - b i t P W M ) T i m e r l o w o r d e r a d d r e s s f u n c t i o n s a s a n b i t p r e s c a l e r a n d h i g h o r d e r a d d r e s s f u n c t i o n s a s a n b i t p u l s e w i d t h m o d u l a t o r

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Figure FB-5. Timer A-related registers (3) Symbol Address When reset CPSRF 0381 16 0XXXXXXX 2 C l o c k p r e s c a l e r r e s e t f l a g Bit name FunctionBit symbol b 7 b 6 b 5 b 4 b3 b 2 b 1 b 0 C l o c k p r e s c a l e r r e s e t f l a g 0 : N o e f f e c t P r e s c a l e r i s r e s e t W h e n r e a d t h e v a l u e i s CPSR WR N o t h i n g i s a s s i g n e d . T h e s e b i t s c a n n e i t h e r b e s e t n o r r e s e t W h e n r e a d t h e i r c o n t e n t s a r e i n d e t e r m i n a t e TA1TGL Symbol Address When reset TRGSR 0383 16 0016 T i m e r A 1 e v e n t / t r i g g e r s e l e c t b i t 0 0 : Input on TA1IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected T r i g g e r s e l e c t r e g i s t e r B i t n a m eF u n c t i o n B i t s y m b o l b7 b6 b5 b4 b3 b2 b1 b0 0 0 : Input on TA2IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA1 overflow is selected 1 1 : TA3 overflow is selected 0 0 : Input on TA3IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA2 overflow is selected 1 1 : TA4 overflow is selected 0 0 : I n p u t o n T A N i s s e l e c t e d N o t e T B o v e r f l o w i s s e l e c t e d T A o v e r f l o w i s s e l e c t e d T A o v e r f l o w i s s e l e c t e d Timer A2 event/trigger select bit T i m e r A 3 e v e n t / t r i g g e r s e l e c t b i t T i m e r A 4 e v e n t / t r i g g e r s e l e c t b i t WR T A 1 T G H TA2TGL T A 2 T G H TA3TGL TA3TGH T A 4 T G L TA4TGH b1 b0 b b b b b7 b6 Note: Set the corresponding port direction register to “0”. When TAiIN is selected, TAiOUT assigned on same pin can not be used. (i=0 to 4) TA1OS TA2OS TA0OS O n e - s h o t s t a r t f l a g S y m b o lA d d r e s sW h e n r e s e t O N S 6 0 X T i m e r A 0 o n e - s h o t s t a r t f l a g T i m e r A 1 o n e - s h o t s t a r t f l a g T i m e r A 2 o n e - s h o t s t a r t f l a g T i m e r A 3 o n e - s h o t s t a r t f l a g T i m e r A 4 o n e - s h o t s t a r t f l a g TA3OS TA4OS B i t n a m eF u n c t i o n B i t s y m b o l b 7 b 6 b 5 b 4 b3 b 2 b 1 b 0 N o t h i n g i s a s s i g n e d . T h i s b i t c a n n e i t h e r b e s e t n o r r e s e t W h e n r e a d t h e c o n t e n t i s i n d e t e r m i n a t e T A 0 T G L T A 0 T G H 0 0 : I n p u t o n T A N i s s e l e c t e d N o t e T B o v e r f l o w i s s e l e c t e d T A o v e r f l o w i s s e l e c t e d T A o v e r f l o w i s s e l e c t e d T i m e r A 0 e v e n t / t r i g g e r s e l e c t b i t b b N o t e : S e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o “ 0 ” . W h e n T A iI N i s s e l e c t e d T A iO U T a s s i g n e d o n s a m e p i n c a n n o t b e u s e d i t o WR 1 : T i m e r s t a r t W h e n r e a d t h e v a l u e i s

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Item Specification Count source f 1, f8, f32, fC32 Count operation • Down count

• When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingWhen the timer underflows TAiIN pin function Programmable I/O port or gate input TAiOUT pin function Programmable I/O port or pulse output Read from timer Count value can be read out by reading timer Ai register Write to timer • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Select function • Gate function Counting can be started and stopped by the TAiIN pin’s input signal
• Pulse output function Each time the timer underflows, the TAiOUT pin’s polarity is reversed (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table FB-1.) Figure FB-6 shows the timer Ai mode register in timer mode. Table FB-1. Specifications of timer mode N o t e 1 : T h e s e t t i n g s o f t h e c o r r e s p o n d i n g p o r t r e g i s t e r a n d p o r t d i r e c t i o n r e g i s t e r a r e i n v a l i d N o t e T h e b i t c a n b e o r N o t e S e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o T i m e r A i m o d e r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t T A i M R i t o t o 6 0 Bit name F u n c t i o n B i t s y m b o l WR b 7 b 6 b 5 b4 b 3 b 2 b1 b 0 O p e r a t i o n m o d e s e l e c t b i t 0 0 : Timer mode b1 b0 T M O D 1 TMOD0 M R 0 P u l s e o u t p u t f u n c t i o n s e l e c t b i t 0 : Pulse is not output (TA iOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin) G a t e f u n c t i o n s e l e c t b i t 0 X (Note 2): Gate function not available (TAiIN pin is a normal port pin) 1 0 : Timer counts only when TAiIN pin is held “L” (Note 3) 1 1 : Timer counts only when TAiIN pin is held “H” (Note 3) b4 b3 M R 2 M R 1 M R 3 0 ( M u s t a l w a y s b e f i x e d t o “ 0 ” i n t i m e r m o d e ) 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b b T C K 1 T C K 0 C o u n t s o u r c e s e l e c t b i t 000 Figure FB-6. Timer Ai mode register in timer mode

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A (2) Event counter mode In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase external signal. Table FB-2 lists timer specifications when counting a single-phase external signal. Fig- ure FB-7 shows the timer Ai mode register in event counter mode. Table FB-3 lists timer specifications when counting a two-phase external signal. Figure FB-8 shows the timer Ai mode register in event counter mode. Table FB-2. Timer specifications in event counter mode (when not processing two-phase pulse signal) Item Specification Count source •External signals input to TAiIN pin (effective edge can be selected by software)

• TB2 overflow, TAj overflow Count operation •Up count or down count can be selected by external signal or software
• When the timer overflows or underflows, the reload register's content is reloaded and the timer starts over again.(Note) Divide ratio 1/ (FFFF 16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingThe timer overflows or underflows TAiIN pin function Programmable I/O port or count source input TAiOUT pin function Programmable I/O port, pulse output, or up/down count select input Read from timer Count value can be read out by reading timer Ai register Write to timer •When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Select function •Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded to it
• Pulse output function Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed Note: This does not apply when the free-run function is selected. B i t n a m eF u n c t i o n T i m e r A i m o d e r e g i s t e r N o t e I n e v e n t c o u n t e r m o d e t h e c o u n t s o u r c e i s s e l e c t e d b y t h e e v e n t t r i g g e r s e l e c t b i t a d d r e s s e s a n d N o t e T h e s e t t i n g s o f t h e c o r r e s p o n d i n g p o r t r e g i s t e r a n d p o r t d i r e c t i o n r e g i s t e r a r e i n v a l i d N o t e V a l i d o n l y w h e n c o u n t i n g a n e x t e r n a l s i g n a l N o t e W h e n a n L s i g n a l i s i n p u t t o t h e T A iO U T p i n t h e d o w n c o u n t i s a c t i v a t e d W h e n H t h e u p c o u n t i s a c t i v a t e d S e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o S y m b o lA d d r e s sW h e n r e s e t T A i M R i 6 0 WR b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 O p e r a t i o n m o d e s e l e c t b i t E v e n t c o u n t e r m o d e ( N o t e b b T M O D 0 M R 0 P u l s e o u t p u t f u n c t i o n s e l e c t b i t 0 : P u l s e i s n o t o u t p u t T A i O U T p i n i s a n o r m a l p o r t p i n P u l s e i s o u t p u t N o t e T Ai O U T p i n i s a p u l s e o u t p u t p i n C o u n t p o l a r i t y s e l e c t b i t N o t e M R 2 M R 1 M R 3 0 ( M u s t a l w a y s b e f i x e d t o “ 0 ” i n e v e n t c o u n t e r m o d e ) T C K 0 C o u n t o p e r a t i o n t y p e s e l e c t b i t 010 0 : C o u n t s e x t e r n a l s i g n a l ' s f a l l i n g e d g e C o u n t s e x t e r n a l s i g n a l s r i s i n g e d g e U p / d o w n s w i t c h i n g c a u s e s e l e c t b i t 0 : U p / d o w n f l a g ' s c o n t e n t T Ai O U T p i n s i n p u t s i g n a l N o t e 0 : R e l o a d t y p e F r e e r u n t y p e B i t s y m b o l T C K 1 I n v a l i d i n e v e n t c o u n t e r m o d e C a n b e o r T M O D 1 Figure FB-7. Timer Ai mode register in event counter mode

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Item Specification Count source •Two-phase pulse signals input to TAi IN or TAiOUT pin Count operation •Up count or down count can be selected by two-phase pulse signal

• When the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (Note) Divide ratio 1/ (FFFF 16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingTimer overflows or underflows TAiIN pin function Two-phase pulse input TAiOUT pin function Two-phase pulse input Read from timer Count value can be read out by reading timer A2, A3, or A4 register Write to timer •When counting stopped When a value is written to timer A2, A3, or A4 register, it is written to both reload register and counter
• When counting in progress When a value is written to timer A2, A3, or A4 register, it is written to only reload register. (Transferred to counter at next reload time.) Select function •Normal processing operation The timer counts up rising edges or counts down falling edges on the TAiIN pin when input signal on the TAiOUT pin is “H”
• Multiply-by-4 processing operation If the phase relationship is such that the TAiIN pin goes “H” when the input signal on the TAiOUT pin is “H”, the timer counts up rising and falling edges on the TAiOUT and TAiIN pins. If the phase relationship is such that the TAiIN pin goes “L” when the input signal on the TAiOUT pin is “H”, the timer counts down rising and falling edges on the TAiOUT and TAiIN pins. Note: This does not apply when the free-run function is selected. Table FB-3. Timer specifications in event counter mode (when processing two-phase pulse signal with timer A2,A3 and A4 TAiOUT Up count Up count Up count Down count Down count Down count TAiIN (i=2,3) TAiOUT TAiIN (i=3,4) Count up all edges Count up all edges Count down all edges Count down all edges

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Bit symbol Bit name Function Bit name F u n c t i o n Note 1: The settings of the corresponding port register and port direction register are invalid Note 2: This bit is valid when only counting an external signal. Note 3: Set the corresponding port direction register to “0”. Note 4: This bit is valid for timer A3 mode register. For timer A2 and A4 mode registers, this bit can be “0 ”or “1”. Note 5: When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 0384 16) is set to “1”. Also, always be sure to set the event/trigger select bit (addresses 038216 and 038316) to “00”. T i m e r A i m o d e r e g i s t e r W h e n n o t u s i n g t w o p h a s e p u l s e s i g n a l p r o c e s s i n g S y m b o lA d d r e s sW h e n r e s e t T A i M R i t o t o 6 0 B i t s y m b o l b O p e r a t i o n m o d e s e l e c t b i t 0 1 : Event counter mode b1 b0 T M O D 1 T M O D 0 M R 0 P u l s e o u t p u t f u n c t i o n s e l e c t b i t 0 : Pulse is not output (TAi OUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin) C o u n t p o l a r i t y s e l e c t b i t N o t e M R 2 M R 1 M R 3 0 ( M u s t a l w a y s b e “ 0 ” i n e v e n t c o u n t e r m o d e ) TCK1 T C K 0 010 0 : Counts external signal's falling edges 1 : Counts external signal's rising edges U p / d o w n s w i t c h i n g c a u s e s e l e c t b i t 0 : Up/down flag's content 1 : TAiOUT pin's input signal (Note 3) WR Count operation type select bit Two-phase pulse signal processing operation select bit (Note 4)(Note 5) 0 : Reload type 1 : Free-run type 0 : Normal processing operation 1 : Multiply-by-4 processing operation Note 1: This bit is valid for timer A3 mode register. For timer A2 and A4 mode registers, this bit can be “0” or “1”. Note 2: When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 0384 16) is set to “1”. Also, always be sure to set the event/trigger select bit (addresses 038216 and 038316) to “00”. Timer Ai mode register (When using two-phase pulse signal processing) S y m b o lA d d r e s sW h e n r e s e t T A i M R i t o t o 6 0 b7 b 6 b5 b4 b 3 b2 b1 b 0 O p e r a t i o n m o d e s e l e c t b i t 0 1 : Event counter mode b1 b0 T M O D 1 T M O D 0 MR0 0 ( M u s t a l w a y s b e “ 0 ” w h e n u s i n g t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g 0 ( M u s t a l w a y s b e “ 0 ” w h e n u s i n g t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g M R 2 M R 1 M R 3 0 (Must always be “0” when using two-phase pulse signal processing) T C K 1 TCK0 010 1 ( M u s t a l w a y s b e “ 1 ” w h e n u s i n g t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g WR Count operation type select bit Two-phase pulse processing operation select bit (Note 1)(Note 2) 0 : Reload type 1 : Free-run type 0 : Normal processing operation 1 : Multiply-by-4 processing operation 0 0 1 Figure FB-8. Timer Ai mode register in event counter m

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Item Specification Count source f1, f 8, f32, fC32 Count operation • The timer counts down

• When the count reaches 000016, the timer stops counting after reloading a new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting Divide ratio 1/n n : Set value Count start condition • An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1) Count stop condition • A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0) Interrupt request generation timingThe count reaches 000016 TAiIN pin function Programmable I/O port or trigger input TAiOUT pin function Programmable I/O port or pulse output Read from timer When timer Ai register is read, it indicates an indeterminate value Write to timer •When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) (3) One-shot timer mode In this mode, the timer operates only once. (See Table FB-4.) When a trigger occurs, the timer starts up and continues operating for a given period. Figure FB-9 shows the timer Ai mode register in one-shot timer mode. Table FB-4. Timer specifications in one-shot timer mode Figure FB-9. Timer Ai mode register in one-shot timer mode Bit name F u n c t i o n Bit symbol T i m e r A i m o d e r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t T A i M R i t o t o 6 0 b 5 b 3b 2 b Operation mode select bit1 0 : O n e - s h o t t i m e r m o d e b b T M O D 1 T M O D 0 MR0 P u l s e o u t p u t f u n c t i o n s e l e c t b i t 0 : P u l s e i s n o t o u t p u t T Ai O U T p i n i s a n o r m a l p o r t p i n P u l s e i s o u t p u t N o t e T A iO U T p i n i s a p u l s e o u t p u t p i n MR2 MR1 WR MR3 0 0 : f1 fC b 7 b 6 T C K 1 T C K 0 C o u n t s o u r c e s e l e c t b i t 100 0 : O n e - s h o t s t a r t f l a g i s v a l i d S e l e c t e d b y e v e n t t r i g g e r s e l e c t r e g i s t e r T r i g g e r s e l e c t b i t E x t e r n a l t r i g g e r s e l e c t b i t N o t e 0 : F a l l i n g e d g e o f T A iI N p i n ' s i n p u t s i g n a l ( N o t e 3 ) R i s i n g e d g e o f T A iI N p i n s i n p u t s i g n a l N o t e Note 1: The settings of the corresponding port register and port direction register are invalid Note 2: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”. Note 3: Set the corresponding port direction register to “0”. 0 ( M u s t a l w a y s b e “ 0 ” i n o n e - s h o t t i m e r m o d e )

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A (4) Pulse width modulation (PWM) mode In this mode, the timer outputs pulses of a given width in succession. (See Table FB-5.) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure FB-10 shows the timer Ai mode register in pulse width modulation mode. Figure FB-11 shows the example of how a 16-bit pulse width modulator operates. Figure FB-12 shows the example of how an 8-bit pulse width modulator operates. Table FB-5. Timer specifications in pulse width modulation mode Figure FB-10. Timer Ai mode register in pulse width modulation mode Item Specification Count source f 1, f8, f32, fC32 Count operation • The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)

• The timer reloads a new count at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs when counting 16-bit PWM •High level width n / fi n : Set value
• Cycle time (2 16-1) / fi fixed 8-bit PWM •High level width n X (m+1) / fi n : values set to timer Ai register’s high-order address
• Cycle time (28-1) X (m+1) / fi m : values set to timer Ai register’s low-order address Count start condition •External trigger is input
• The timer overflows
• The count start flag is set (= 1) Count stop condition •The count start flag is reset (= 0) Interrupt request generation timingPWM pulse goes “L” TAiIN pin function Programmable I/O port or trigger input TAiOUT pin function Pulse output Read from timer When timer Ai register is read, it indicates an indeterminate value Write to timer •When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Timer Ai mode register Symbol Address When reset TAiMR(i=0 to 4) 039616 to 039A16 0016 B i t n a m e FunctionB i t s y m b o lb 7 b 6b 5b 3 b O p e r a t i o n m o d e s e l e c t b i t 1 1 : P W M m o d e b 1 b 0 T M O D 1 T M O D 0 M R 0 MR2 M R 1 M R 3 0 0 : f1 fC b 7 b 6 TCK1 TCK0 C o u n t s o u r c e s e l e c t b i t WR 111 1 ( M u s t a l w a y s b e f i x e d t o “ 1 ” i n P W M m o d e ) 6 / 8 - b i t P W M m o d e s e l e c t b i t 0 : F u n c t i o n s a s a 1 6 - b i t p u l s e w i d t h m o d u l a t o r F u n c t i o n s a s a n b i t p u l s e w i d t h m o d u l a t o r Trigger select bit E x t e r n a l t r i g g e r s e l e c t b i t N o t e 0 : F a l l i n g e d g e o f T A iI N p i n ' s i n p u t s i g n a l ( N o t e 2 ) R i s i n g e d g e o f T A iI N p i n s i n p u t s i g n a l N o t e 0 : C o u n t s t a r t f l a g i s v a l i d S e l e c t e d b y e v e n t t r i g g e r s e l e c t r e g i s t e r N o t e 1 : V a l i d o n l y w h e n t h e T Ai I N p i n i s s e l e c t e d b y t h e e v e n t / t r i g g e r s e l e c t b i t a d d r e s s e s a n d I f t i m e r o v e r f l o w i s s e l e c t e d t h i s b i t c a n b e o r N o t e S e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Figure FB-11. Example of how a 16-bit pulse width modulator operates Figure FB-12. Example of how an 8-bit pulse width modulator operates fi : Frequency of count source (f1, f8, f32, fC32 ) Trigger is not generated by this signal Count source Condition : Reload register = 000316, when external trigger (falling edge of TA0IN pin's input signal) is selected. 1 / fi X (2 –1) 16 TA0 IN pin's input signal PWM pulse output from TA0OUT pin “H” “H” “L” “L” Timer A0 interrupt request bit “1” “0” Cleared to “0” by software, or when interrupt request is accepted. Note: n = 000016 to FFFE16. 1 / fi X n C o u n t s o u r c e N o t e TA0 IN pin's input signal U n d e r f l o w s i g n a l o f b i t p r e s c a l e r N o t e P W M p u l s e o u t p u t f r o m T A U T p i n “ H ” H ” L ” L ” T i m e r A 0 i n t e r r u p t r e q u e s t b i t fi : F r e q u e n c y o f c o u n t s o u r c e f1, f8, fC N o t e 1 : T h e 8 - b i t p r e s c a l e r c o u n t s t h e c o u n t s o u r c e . N o t e T h e b i t p u l s e w i d t h m o d u l a t o r c o u n t s t h e b i t p r e s c a l e r s u n d e r f l o w s i g n a l N o t e m t o F n t o F Condition : Reload register's high-order 8 bits = 0216 Reload register's low-order bits 8 = 0216 When external trigger (falling edge of TA0IN pin's input signal) is selected. 1 / fi X ( m + 1 ) X ( 2 – 1 )8 1 / fi X ( m + 1 ) X n 1 / fi X ( m + 1 ) C l e a r e d t o “ 0 ” b y s o f t w a r e , o r w h e n i n t e r r u p t r e q u e s t i s a c c e p t e d . “ H ” L ” 1 ” 0 ”

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B Timer B Figure TA-1 shows the block diagram of timer B. Figures TA-2 and TA-3 show the timer B-related registers. Use the timer Bi mode register (i = 0 to 2) bits 0 and 1 to choose the desired mode. Timer B has three operation modes listed as follows:

• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer overflow. Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or pulse width. Figure TA-1. Block diagram of timer B Clock source selection (address 038016)
• Event counter
• Timer
• Pulse period/pulse width measurement Reload register (16) Low-order 8 bits High-order 8 bits Data bus low-order bits Data bus high-order bits f32 TBj overflow (j = i - 1. Note, however, j = 2 when i = 0) Can be selected in only event counter mode Count start flag fc32 Polarity switching and edge pulse(i = 0 to 2) Counter reset circuit Counter (16) TBi Address TBj Timer B0 039116 039016 Timer B2 Timer B1 039316 039216 Timer B0 Timer B2 039516 039416 Timer B1 TBiIN Timer Bi mode register S y m b o lA d d r e s sW h e n r e s e t T B i M R i t o t o D 1 6 0 X X B i t s y m b o l Bit name F u n c t i o n WR b 6b 5b 4b 3b 2b 1b 0 0 : T i m e r m o d e E v e n t c o u n t e r m o d e P u l s e p e r i o d p u l s e w i d t h m e a s u r e m e n t m o d e I n h i b i t e d b1 b0 TCK1 MR3 MR2 MR1 TMOD1 MR0 TMOD0 TCK0 F u n c t i o n v a r i e s w i t h e a c h o p e r a t i o n m o d e C o u n t s o u r c e s e l e c t b i t F u n c t i o n v a r i e s w i t h e a c h o p e r a t i o n m o d e O p e r a t i o n m o d e s e l e c t b i t N o t e N o t e N o t e 1 : T i m e r B 0 . N o t e T i m e r B t i m e r B Figure TA-2. Timer B-related registers (1)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B Figure TA-3. Timer B-related registers (2) S y m b o lA d d r e s sW h e n r e s e t T A B S 6 0 C o u n t s t a r t f l a g B i t n a m eF u n c t i o nBit symbol W R b Timer B2 count start flag Timer B1 count start flag Timer B0 count start flag Timer A4 count start flag Timer A3 count start flag Timer A2 count start flag Timer A1 count start flag Timer A0 count start flag0 : S t o p s c o u n t i n g S t a r t s c o u n t i n g TB2S TB1S T B 0 S T A 4 S TA3S TA2S TA1S TA0S Symbol Address When reset CPSRF 0381 16 0XXXXXXX 2 C l o c k p r e s c a l e r r e s e t f l a g Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 Clock prescaler reset flag0 : No effect 1 : Prescaler is reset (When read, the value is “0”) C P S R S y m b o lA d d r e s sW h e n r e s e t T B 6 I n d e t e r m i n a t e T B 6 I n d e t e r m i n a t e T B 6 I n d e t e r m i n a t e b 7b 0 b b )T i m e r B i r e g i s t e r ( N o t e ) WR

• P u l s e p e r i o d / p u l s e w i d t h m e a s u r e m e n t m o d e M e a s u r e s a p u l s e p e r i o d o r w i d t h
• T i m e r m o d e0 0 0 01 6 t o F F F F1 C o u n t s t h e t i m e r s p e r i o d Function V a l u e s t h a t c a n b e s e t
• E v e n t c o u n t e r m o d e0 0 0 01 6 t o F F F F1 C o u n t s e x t e r n a l p u l s e s i n p u t o r a t i m e r o v e r f l o w N o t e R e a d a n d w r i t e d a t a i n b i t u n i t s Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B Item Specification Count source f 1, f8, f32, fC32 Count operation •Counts down

• When the timer underflows, the reload register's content is reloaded and the timer starts over again. Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingThe timer underflows TBiIN pin function Programmable I/O port Read from timer Count value is read out by reading timer Bi register Write to timer •When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table TA-1.) Figure TA-4 shows the timer Bi mode register in timer mode. Table TA-1. Timer specifications in timer mode Figure TA-4. Timer Bi mode register in timer mode N o t e 1 : T i m e r B 0 . N o t e T i m e r B t i m e r B T i m e r B i m o d e r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t T B i M R i t o t o D 1 6 0 X X B i t n a m eF u n c t i o nB i t s y m b o l WR b 7b 6b Operation mode select bit0 0 : Timer mode b1 b0 TMOD1 TMOD0 M R 0 Invalid in timer mode Can be “0” or “1” M R 2 M R 1 M R 3 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 TCK1 TCK0 Count source select bit Invalid in timer mode. In an attempt to write to these bits, write “0”. The value, if read in timer mode, turns out to be indeterminate. 0 (Fixed to “0” in timer mode ; i = 0) Nothing is assigned (i = 1,2). In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. ( N o t e 1 ) ( N o t e 2 ) b7 b6

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B Figure TA-5. Timer Bi mode register in event counter mode (2) Event counter mode In this mode, the timer counts an external signal or an internal timer's overflow. (See Table TA-2.) Figure TA-5 shows the timer Bi mode register in event counter mode. Table TA-2. Timer specifications in event counter mode Item Specification Count source •External signals input to TBi IN pin

• Effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software Count operation •Counts down
• When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingThe timer underflows TBiIN pin function Count source input Read from timer Count value can be read out by reading timer Bi register Write to timer •When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) T i m e r B i m o d e r e g i s t e r Symbol Address When reset TBiMR(i=0 to 2) 039B16 to 039D16 00XX0000 2 Bit name F u n c t i o n B i t s y m b o l W R b 5b 4b O p e r a t i o n m o d e s e l e c t b i t 0 1 : E v e n t c o u n t e r m o d e b1 b0 T M O D 1 T M O D 0 MR0 C o u n t p o l a r i t y s e l e c t b i t N o t e M R 2 M R 1 M R 3 I n v a l i d i n e v e n t c o u n t e r m o d e . I n a n a t t e m p t t o w r i t e t o t h i s b i t w r i t e T h e v a l u e i f r e a d i n e v e n t c o u n t e r m o d e t u r n s o u t t o b e i n d e t e r m i n a t e TCK1 TCK0 0 0 : C o u n t s e x t e r n a l s i g n a l ' s f a l l i n g e d g e s C o u n t s e x t e r n a l s i g n a l s r i s i n g e d g e s C o u n t s e x t e r n a l s i g n a l s f a l l i n g a n d r i s i n g e d g e s I n h i b i t e d b3 b2 N o t h i n g i s a s s i g n e d ( i = 1 , 2 ) . I n a n a t t e m p t t o w r i t e t o t h i s b i t w r i t e T h e v a l u e i f r e a d t u r n s o u t t o b e i n d e t e r m i n a t e N o t e 1 : V a l i d o n l y w h e n i n p u t f r o m t h e T B iI N p i n i s s e l e c t e d a s t h e e v e n t c l o c k . I f t i m e r s o v e r f l o w i s s e l e c t e d t h i s b i t c a n b e o r N o t e T i m e r B N o t e T i m e r B t i m e r B N o t e S e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o I n v a l i d i n e v e n t c o u n t e r m o d e . C a n b e o r E v e n t c l o c k s e l e c t 0 : I n p u t f r o m T B i I N p i n ( N o t e 4 ) T B j o v e r f l o w j i h o w e v e r j w h e n i 0 ( F i x e d t o “ 0 ” i n e v e n t c o u n t e r m o d e ; i = 0 ) ( N o t e 2 ) (Note 3)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B Item Specification Count source f 1, f8, f32, fC32 Count operation •Up count

• Counter value “000016” is transferred to reload register at measurement pulse's effective edge and the timer continues counting Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing•When measurement pulse's effective edge is input (Note 1)
• When an overflow occurs. (Simultaneously, the timer Bi overflow flag changes to “1”. The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value is written to the timer Bi mode register.) TBiIN pin function Measurement pulse input Read from timer When timer Bi register is read, it indicates the reload register’s content (measurement result) (Note 2) Write to timer Cannot be written to Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting. Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer. (3) Pulse period/pulse width measurement mode In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table TA-3.) Figure TA-6 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure TA-7 shows the operation timing when measuring a pulse period. Figure TA-8 shows the operation timing when measuring a pulse width. Table TA-3. Timer specifications in pulse period/pulse width measurement mode Figure TA-6. Timer Bi mode register in pulse period/pulse width measurement mode T i m e r B i m o d e r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t T B i M R i t o t o D 1 6 0 X X Bit nameBit symbol W R b O p e r a t i o n m o d e s e l e c t b i t 1 0 : P u l s e p e r i o d / p u l s e w i d t h m e a s u r e m e n t m o d e b b T M O D 1 T M O D 0 M R 0 M e a s u r e m e n t m o d e s e l e c t b i t M R 2 M R 1 M R 3 T C K 1 T C K 0 0 1 0 0 : P u l s e p e r i o d m e a s u r e m e n t ( I n t e r v a l b e t w e e n m e a s u r e m e n t p u l s e s f a l l i n g e d g e t o f a l l i n g e d g e P u l s e p e r i o d m e a s u r e m e n t I n t e r v a l b e t w e e n m e a s u r e m e n t p u l s e s r i s i n g e d g e t o r i s i n g e d g e P u l s e w i d t h m e a s u r e m e n t I n t e r v a l b e t w e e n m e a s u r e m e n t p u l s e s f a l l i n g e d g e t o r i s i n g e d g e a n d b e t w e e n r i s i n g e d g e t o f a l l i n g e d g e I n h i b i t e d Function b b N o t h i n g i s a s s i g n e d ( i = 1 , 2 ) . I n a n a t t e m p t t o w r i t e t o t h i s b i t w r i t e T h e v a l u e i f r e a d i n e v e n t c o u n t e r m o d e t u r n s o u t t o b e i n d e t e r m i n a t e Count source select bit T i m e r B i o v e r f l o w f l a g N o t e 0 : T i m e r d i d n o t o v e r f l o w T i m e r h a s o v e r f l o w e d 0 0 : f1 fC b7 b6 N o t e 1 : T h e t i m e r B i o v e r f l o w f l a g c h a n g e s t o “ 0 ” w h e n t h e c o u n t s t a r t f l a g i s “ 1 ” a n d a v a l u e i s w r i t t e n t o t h e t i m e r B i m o d e r e g i s t e r T h i s f l a g c a n n o t b e s e t t o b y s o f t w a r e N o t e T i m e r B N o t e T i m e r B t i m e r B 0 ( F i x e d t o “ 0 ” i n p u l s e p e r i o d / p u l s e w i d t h m e a s u r e m e n t m o d e ; i = 0 ) ( N o t e 2 ) ( N o t e 3 )

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B Figure TA-8. Operation timing when measuring a pulse width Figure TA-7. Operation timing when measuring a pulse period Count source Measurement pulse Count start flag Timer Bi interrupt request bit Timing when counter reaches “0000 16” “H” “1” Transfer (indeterminate value) Reload register counter transfer timing “L” “0” “0” Timer Bi overflow flag “1” “0” Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. (Note 1)(Note 1) Measurement of puls time interval from falling edge to falling edge (Note 2) Cleared to “0” by software, or when interrupt request is accepted. Transfer (measured value) “1” Measurement pulse “H” Count source Reload register counter transfer timing Count start flag Timer Bi interrupt request bit Timing when counter reaches “000016” “1” “1” “L” “0” “0” Timer Bi overflow flag“1” “0” Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. (Note 1) (Note 1) (Note 1)(Note 1) Cleared to “0” by software, or when interrupt request is accepted. (Note 2) Transfer (measured value)Transfer (indeterminate value)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O Figure GA-1. Block diagram of UARTi (i = 0, 1) Serial I/O Serial I/O is configured as two channels: UART0 and UART1. UART0 and UART1 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figure GA-1 shows the block diagram of UART0 and UART1. Figures GA-2 shows the block diagram of the transmit/receive unit. UARTi (i=0, 1) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 03A0 16 and 03A816) determine whether UARTi is used as a clock synchronous serial I/O or as a UART. Although a few function are different, UART0 and UART1 have almost same functions. Figures GA-3 through GA-5 show the registers related to UARTi. m: Values set to UART0 bit rate generator (U0BRG) n : Values set to U ART1 bit rate generator (U1BR G) RxD 0 1 / (m+1) Bit rate generator (address 03A116) Clock synchronous type (when internal clock is selected) UART reception Clock synchronous type UART transmission Clock synchronous type Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) Receive clock Transmit clock CLK 0 Clock source selection CTS 0 / RTS0 f32 Internal External Vcc RTS0 CTS0 TxD 0 Transmit/ receive unit RxD 1 1 / (n+1) Bit rate generator (address 03A916) Clock synchronous type (when internal clock is selected) UART reception Clock synchronous type UART transmission Clock synchronous type Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) Receive clock Transmit clock CLK 1 Clock source selection f32 Internal External RTS 1 CTS 1 TxD 1 (UART1) (UART0) Polarity reversing circuit Polarity reversing circuit CTS/RTS disabled Clock output pin select switch CTS 1 / RTS1 CLKS 1 CTS/RTS disabled CTS/RTS selected CTS/RTS disabled VCC CTS/RTS disabled Reception control circuit Transmission control circuit Reception control circuit Transmission control circuit Transmit/ receive unit

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O Figure GA-2. Block diagram of transmit/receive unit SP SP PAR 2SP 1SP UART UART (7 bits) UART (8 bits) UART (7 bits) UART (9 bits) Clock synchronous type Clock synchronous type TxDi UARTi transmit register PAR enabled PAR disabled D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 SP: Stop bit PAR: Parity bit UARTi transmit buffer register MSB/LSB conversion circuit UART (8 bits) UART (9 bits) Clock synchronouss type UARTi receive buffer register UARTi receive register 2SP 1SP PAR enabled PAR disabled UART UART (7 bits) UART (9 bits) Clock synchronous type Clock synchronous type UART (7 bits) UART (8 bits) RxDi Clock synchronous type UART (8 bits) UART (9 bits) Address 03A616 Address 03A716 Address 03AE16 Address 03AF16 Address 03A216 Address 03A316 Address 03AA16 Address 03AB16 Data bus low-order bits MSB/LSB conversion circuit 0000000 SP SP PAR "0" Data bus high-order bits D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0D 8

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O Figure GA-3. Serial I/O-related registers (1) b7 b0 (b15) (b8) b7 b0 UARTi transmit buffer register Function Transmission data Symbol Address When reset U0TB 03A3 16, 03A216 Indeterminate U1TB 03AB 16, 03AA16 Indeterminate UARTi bit rate generator b7 b0 Symbol Address When reset U0BRG 03A1 16 Indeterminate U1BRG 03A9 16 Indeterminate Function Assuming that set value = n, BRGi divides the count source by (n + 1) 0016 to FF16 Values that can be set Symbol Address When reset U0RB 03A7 16, 03A616 Indeterminate U1RB 03AF 16, 03AE16 Indeterminate b7 b0 (b15) (b8) b7 b0 UARTi receive buffer register Function (During UART mode) Function (During clock synchronous serial I/O mode) Bit nameBit symbol 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found Note: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses 03A0 16 and 03A816) are set to “0002” or the receive enable bit is set to “0”. (Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the lower byte of the UARTi receive buffer register (addresses 03A6 16 and 03AE16) is read out. Invalid Invalid Invalid OER FER PER SUM Overrun error flag (Note) Framing error flag (Note) Parity error flag (Note) Error sum flag (Note) 0 : No overrun error 1 : Overrun error found 0 : No overrun error 1 : Overrun error found Reception data W R W R W R Reception data Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O Figure GA-4. Serial I/O-related registers (2) WR U A R T i t r a n s m i t / r e c e i v e m o d e r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t U i M R i A A 6 0 b B i t n a m eB i t s y m b o l Must be fixed to 001 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited b2 b1 b0 C K D I R S M D 1 S M D 0 S e r i a l I / O m o d e s e l e c t b i t S M D 2 I n t e r n a l / e x t e r n a l c l o c k s e l e c t b i t S T P S PRY P R Y E S L E P P a r i t y e n a b l e b i t 0 : Internal clock 1 : External clock S t o p b i t l e n g t h s e l e c t b i t O d d / e v e n p a r i t y s e l e c t b i t Sleep select bit 0 : O n e s t o p b i t T w o s t o p b i t s 0 : Parity disabled 1 : Parity enabled 0 : S l e e p m o d e d e s e l e c t e d S l e e p m o d e s e l e c t e d 1 0 0 : T r a n s f e r d a t a 7 b i t s l o n g T r a n s f e r d a t a b i t s l o n g T r a n s f e r d a t a b i t s l o n g S e r i a l I O i n v a l i d I n h i b i t e d I n h i b i t e d I n h i b i t e d b 2 b 1 b 0 0 : I n t e r n a l c l o c k E x t e r n a l c l o c k Invalid V a l i d w h e n b i t 6 = “ 1 ” O d d p a r i t y E v e n p a r i t y Invalid Invalid Must always be “0” F u n c t i o n D u r i n g U A R T m o d e Function (During clock synchronous serial I/O mode) UARTi transmit/receive control register 0 S y m b o lA d d r e s sW h e n r e s e t U i C i A A C 1 6 0 b7 b6 b5 b4 b3 b2 b1 b0 F u n c t i o n D u r i n g U A R T m o d e F u n c t i o n D u r i n g c l o c k s y n c h r o n o u s s e r i a l I O m o d e T X E P T CLK1 C L K 0 CRS CRD N C H CKPOL B R G c o u n t s o u r c e s e l e c t b i t T r a n s m i t r e g i s t e r e m p t y f l a g 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge C L K p o l a r i t y s e l e c t b i t CTS/RTS function select bit CTS/RTS disable bit D a t a o u t p u t s e l e c t b i t 0 : f 1 i s s e l e c t e d i s s e l e c t e d i s s e l e c t e d I n h i b i t e d b1 b0 0 : LSB first 1 : MSB first 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : C T S / R T S f u n c t i o n e n a b l e d C T S R T S f u n c t i o n d i s a b l e d P a n d P f u n c t i o n a s p r o g r a m m a b l e I O p o r t 0 : T X D i p i n i s C M O S o u t p u t T X D i p i n i s N c h a n n e l o p e n d r a i n o u t p u t U F O R M Transfer format select bit 0 : f 1 i s s e l e c t e d i s s e l e c t e d i s s e l e c t e d I n h i b i t e d b1 b0 V a l i d w h e n b i t 4 = “ 0 ” C T S f u n c t i o n i s s e l e c t e d N o t e R T S f u n c t i o n i s s e l e c t e d N o t e V a l i d w h e n b i t 4 = “ 0 ” C T S f u n c t i o n i s s e l e c t e d N o t e R T S f u n c t i o n i s s e l e c t e d N o t e 0 : D a t a p r e s e n t i n t r a n s m i t r e g i s t e r d u r i n g t r a n s m i s s i o n N o d a t a p r e s e n t i n t r a n s m i t r e g i s t e r t r a n s m i s s i o n c o m p l e t e d 0 : T X D i p i n i s C M O S o u t p u t T X D i p i n i s N c h a n n e l o p e n d r a i n o u t p u t M u s t a l w a y s b e “ 0 ” B i t n a m eB i t s y m b o l M u s t a l w a y s b e “ 0 ” Note 1: Set the corresponding port direction register to “0”. Note 2: The settings of the corresponding port register and port direction register are invalid. 0 : C T S / R T S f u n c t i o n e n a b l e d C T S R T S f u n c t i o n d i s a b l e d P a n d P f u n c t i o n a s p r o g r a m m a b l e I O p o r t W R

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O Figure GA-5. Serial I/O-related registers (3) UARTi transmit/receive control register 1 Symbol Address When reset UiC1(i=0,1) 03A5 16, 03AD 16 0216 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol W RFunction (During UART mode) Function (During clock synchronous serial I/O mode) TE TI RE RI Transmit enable bit Receive enable bit Receive complete flag Transmit buffer empty flag 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : No data present in receive buffer register 1 : Data present in receive buffer register Note: When using multiple pins to output the transfer clock, the following requirement must be met:

• UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”. UART transmit/receive control register 2 Symbol Address When reset UCON 03B0 16 X00000002 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol W RFunction (During UART mode) Function (During clock synchronous serial I/O mode) CLKMD0 CLKMD1 UART0 transmit interrupt cause select bit UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enable UART1 continuous receive mode enable bit CLK/CLKS select bit 0 UART1 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Normal mode (CLK output is CLK1 only) 1 : Transfer clock output from multiple pins function selected 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) Must always be “0” U0IRS U1IRS U0RRM U1RRM Invalid Invalid Invalid CLK/CLKS select bit 1 (Note) Valid when bit 5 = “1” 0 : Clock output to CLK1 1 : Clock output to CLKS1 Reserved bit Must always be “0” Must always be “0” Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock synchronous serial I/O mode (1) Clock synchronous serial I/O mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table GA-1 lists the specifications of the clock synchronous serial I/O mode. Figure GA-6 shows the UARTi transmit/ receive mode register. Table GA-1. Specifications of clock synchronous serial I/O mode Specification

• Transfer data length: 8 bits
• When internal clock is selected (bit 3 at address 03A016, 03A816 = “0”) : fi/ 2(n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at address 03A016, 03A816 =“1”) : Input from CLKi pin (Note 2)
• CTS function/ RTS function/ CTS,RTS function chosen to be invalid
• To start transmission, the following requirements must be met: _ Transmit enable bit (bit 0 at address 03A516, 03AD16) = “1” _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”_______ _______ _ When CTS function is selected, CTS input level = "L"
• Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at address 03A416, 03AC16) = “0”: CLKi input level = “H” _ CLKi polarity select bit (bit 6 at address 03A416, 03AC16) = “1”: CLKi input level = “L”
• To start reception, the following requirements must be met: _ Receive enable bit (bit 2 at address 03A516, 03AD16) = “1” _ Transmit enable bit (bit 0 at address 03A516, 03AD16) = “1” _ Transmit buffer empty flag (bit 1 at address 03A516, 03AD16) = “0”
• Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at address 03A416, 03AC16) = “0”: CLKi input level = “H” _ CLKi polarity select bit (bit 6 at address 03A416, 03AC16) = “1”: CLKi input level = “L”
• When transmitting _ Transmit interrupt cause select bit (bits 0,1 at address 03B016) = “0”: Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed _ Transmit interrupt cause select bit (bits 0,1 at address 03B016) = “1”: Interrupts requested when data transmission from UARTi transfer register is completed
• When receiving _ Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed
• Overrun error (Note 3) This error occurs when the next data is ready before contents of UARTi re- ceive buffer register are read out
• CLK polarity selection Whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected
• LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection UART1 transfer clock can be set 2 pins, and can be selected to output from which pin. Note 1: “n” denotes the value 00 16 to FF16 that is set to the UART bit rate generator. Note 2: Maximum 5 Mbps. Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit is not set to “1”. Item Transfer data format Transfer clock Transmission/reception control Transmission start condi- tion Reception start condition Interrupt request generation timing Error detection Select function

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock synchronous serial I/O mode Figure GA-6. UARTi transmit/receive mode register in clock synchronous serial I/O mode (i=0,1) Table GA-2 lists the functions of the input/output pins during clock synchronous serial I/O mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”. (If the N-channel open-drain is selected, this pin is in floating state.) Table GA-2. Input/output pin functions in clock synchronous serial I/O mode (i=0,1) Symbol Address When reset UiMR(i=0,1) 03A0 16, 03A816 0016 CKDIR UARTi transmit/receive mode register Internal/external clock select bit STPS PRY PRYE SLEP 0 : Internal clock 1 : External clock Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 0 (Must always be "0" in clock synchronous serial I/O mode) 010 SMD0 SMD1 SMD2 Serial I/O mode select bit0 0 1 : Clock synchronous serial I/O mode b2 b1 b0 Invalid in clock synchronous serial I/O mode Pin name Function Method of selection TxDi (P44, P74) Serial data output Serial data input Transfer clock output Transfer clock input Programmable I/O port (Outputs dummy data when performing reception only) RxDi (P45, P75) CLKi (P46, P76) Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “0” Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “1” Port P46, P76 direction register (bits 6 at address 03EA16 and 03EF16) = “0” Port P45, P75 direction register (bits 5 at address 03EA16 and 03EF16)= “0” (Can be used as an input port when performing transmission only) CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) =“0” CTS/RTS function select bit (bit 2 at address 03A416, 03AC16) = “0” Port P47, P77 direction register (bits 7 address 03EA16 and 03EF16) = “0” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) = “0” CTS/RTS function select bit (bit 2 at address 03A416, 03AC16) = “1” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) = “1” CTS input RTS output CTSi/RTSi (P47, P77)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock synchronous serial I/O mode Figure GA-7. Typical transmit/receive timings in clock synchronous serial I/O mode

• Example of transmit timing (when internal clock is selected)
• Example of receive timing (when external clock is selected) D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 T c TC L K Stopped pulsing because transfer enable bit = “0” D a t a i s s e t i n U A R T i t r a n s m i t b u f f e r r e g i s t e r Tc = TCLK = 2(n + 1) / fi fi: frequency of BRGi's count source (f1, f8, f32) n: value set to BRGi T r a n s f e r c l o c k T r a n s m i t e n a b l e b i t T E T r a n s m i t b u f f e r e m p t y f l a g T l C L K i T x D i T r a n s m i t r e g i s t e r e m p t y f l a g T X E P T “ H ” “ L “0” “ 1 ” “ 0 ” “1” “0” “ 1 ” C T S i Shown in ( ) are bit symbols. The above timing applies to the following settings:
• Internal clock is selected.
• CTS function is selected.
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”. Transmit interrupt request bit (IR)“0” “ 1 ” C l e a r e d t o “ 0 ” b y s o f t w a r e , o r w h e n a n i n t e r r u p t r e q u e s t i s a c c e p t e d . S t o p p e d p u l s i n g b e c a u s e C T S = “ H ” 1 / fE X T Dummy data is set in UARTi transmit buffer register Transmit enable bit (TE) Transmit buffer empty flag (Tl) C L K i RxDi R e c e i v e c o m p l e t e f l a g R l R T S i “ H ” L ” 0 ” 1 ” 0 ” “1” “0” “ 1 ” R e c e i v e e n a b l e b i t R E ) “0” “ 1 ” R e c e i v e d a t a i s t a k e n i n T r a n s f e r r e d f r o m U A R T i t r a n s m i t b u f f e r r e g i s t e r t o U A R T i t r a n s m i t r e g i s t e r Read out from UARTi receive buffer register S h o w n i n ( ) a r e b i t s y m b o l s . T h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s E x t e r n a l c l o c k i s s e l e c t e d R T S f u n c t i o n i s s e l e c t e d C L K p o l a r i t y s e l e c t b i t fEXT : frequency of external clock Transferred from UARTi receive register to UARTi receive buffer register R e c e i v e i n t e r r u p t r e q u e s t b i t I R ) “ 0 ” 1 ” D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 Transferred from UARTi transmit buffer register to UARTi transmit register C l e a r e d t o “ 0 ” b y s o f t w a r e , o r w h e n a n i n t e r r u p t r e q u e s t i s a c c e p t e d . M e e t t h e f o l l o w i n g c o n d i t i o n s w h e n t h e C L K i n p u t b e f o r e d a t a r e c e p t i o n H T r a n s m i t e n a b l e b i R e c e i v e e n a b l e b i D u m m y d a t a w r i t e t o U A R T i t r a n s m i t b u f f e r r e g i s t e r

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock synchronous serial I/O mode (a) Polarity select function As shown in Figure GA-8, the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16) allows selection of the polarity of the transfer clock. Figure GA-8. Polarity of transfer clock (b) LSB first/MSB first select function As shown in Figure GA-9, when the transfer format select bit (bit 7 at addresses 03A416, 03AC16) = “0”, the transfer format is “LSB first”; when the bit = “1”, the transfer format is “MSB first”. Figure GA-9. Transfer format

• When CLK polarity select bit = “1” Note 2: The CLKi pin level when not transferring data is “L”.D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 0 TXD i R XD i CLK i
• When CLK polarity select bit = “0” Note 1: The CLKi pin level when not transferring data is “H”.D 1 D 2 D 3 D 4 D 5 D 6 D 7D0 D 1 D 2 D 3 D 4 D 5 D 6 D 7D 0 TXD i R XD i CLK i LSB first
• When transfer format select bit = “0” D 1 D 2 D 3 D 4 D 5 D 6 D 7D0 D 1 D 2 D 3 D 4 D 5 D 6 D 7D 0 TXD i R XD i CLK i
• When transfer format select bit = “1” D 6 D 5 D 4 D 3 D 2 D 1 D 0D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0D 7 TXD i R XD i CLK i MSB first Note: This applies when the CLK polarity select bit = “0”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock synchronous serial I/O mode (c) Transfer clock output from multiple pins function This function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure GA-10.) The multiple pins function is valid only when the internal clock is selected for UART1. Note that when this function is selected, CTS/RTS function of UART1 cannot be used. Figure GA-10. The transfer clock output from the multiple pins function usage (d) Continuous receive mode If the continuous receive mode enable bit (bits 2 and 3 at address 03B016) is set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. Microcomputer TXD 1 (P74) CLKS 1 (P77) CLK 1 (P76) IN CLK IN CLK Note: This applies when the internal clock is selected and transmission is performed only in clock synchronous serial I/O mode.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode (2) Clock asynchronous serial I/O (UART) mode The UART allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Tables GA-3 lists the specifications of the UART mode. Figure GA-11 shows the UARTi transmit/ receive mode register. Table GA-3. Specifications of clock synchronous serial I/O mode Item Specification Transfer data format •Character bit (transfer data): 7 bits, 8 bits or 9 bits as selected

• Start bit: 1 bit
• Parity bit: Odd, even or nothing as selected
• Stop bit: 1 bit or 2 bits as selected Transfer clock •When internal clock is selected (bit 3 at addresses 03A016, 03A816 = “0”) : fi/16(n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at addresses 03A016, 03A816 =“1”) : fEXT /16(n+1) (Note 1) (Note 2) Transmission/reception control
• CTS function/RTS function/CTS, RTS function chosen to be invalid Transmission start condition•To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 at addresses 03A516, 03AD16) = “1” - Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”_______ _______ - When CTS function is selected, CTS input level = “L” Reception start condition •To start reception, the following requirements must be met: - Receive enable bit (bit 2 at addresses 03A516, 03AD16) = “1” - Start bit detection Interrupt request •When transmitting generation timing - Transmit interrupt cause select bits (bits 0,1 at address 03B016) = “0”: Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed - Transmit interrupt cause select bits (bits 0, 1 at address 03B0 16) = “1”: Interrupts requested when data transmission from UARTi transfer register is completed
• When receiving - Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed Error detection •Overrun error (Note 3) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out
• Framing error This error occurs when the number of stop bits set is not detected
• Parity error This error occurs when if parity is enabled, the number of 1’s in parity and character bits does not match the number of 1’s set
• Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered select function •Sleep mode selection This mode is used to transfer data to and from one of multiple slave microcomputers Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: fEXT is input from the CLKi pin. Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit is not set to “1”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode Table GA-4 lists the functions of the input/output pins during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”. (If the N- channel open-drain is selected, this pin is in floating state.) Table GA-4. Input/output pin functions in UART mode (i=0,1) Figure GA-11. UARTi transmit/receive mode register in UART mode Pin name Function Method of selection TxDi (P44, P74) Serial data output Serial data input Programmable I/O port Transfer clock input Programmable I/O port RxDi (P45, P75) CLKi (P46, P76) Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “0” Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “1” Port P45, P75 direction register (bits 5 at address 03EA16 and 03EF16)= “0” (Can be used as an input port when performing transmission only) CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) =“0” CTS/RTS function select bit (bit 2 at address 03A416, 03AC16) = “0” Port P47, P77 direction register (bits 7 at address 03EA16 and 03EF16) = “0” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) = “0” CTS/RTS function select bit (bit 2 at address 03A416, 03AC16) = “1” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) = “1” CTS input RTS output CTSi/RTSi (P47, P77) (Outputs dummy data when performing reception only) Symbol Address When reset UiMR (i=0,1) 03A0 16, 03A816 0016 CKDIR UARTi transmit/receive mode register Internal/external clock select bit STPS PRY PRYE SLEP 0 : Internal clock 1 : External clock Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 SMD0 SMD1 SMD2 Serial I/O mode select bit b2 b1 b0 0 : One stop bit 1 : Two stop bits 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity Stop bit length select bit Odd/even parity select bit Parity enable bit Sleep select bit

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode

• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) Figure GA-12. Typical transmit timings in UART mode T r a n s m i t e n a b l e e b i t T E T r a n s m i t b u f f e r e m p t y f l a g T I T r a n s m i t r e g i s t e r e m p t y f l a g T X E P T D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7S T P S t a r t b i t P a r i t y b i t T x D i C T S i The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• CTS function is selected.
• Transmit interrupt cause select bit = “1”. “ 1 ” “ 0 ” “ 1 ” “ L ” “ H ” “ 0 ” “1” Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi's count source (f1, f8, f32) fEXT : frequency of BRGi's count source (external clock) n : value set to BRGi T r a n s m i t i n t e r r u p t r e q u e s t b i t I R ) “ 0 ” “ 1 ” Cleared to “0” by software, or when an interrupt request is accepted. D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7S T P S P D 0 D 1S T T r a n s m i t e n a b l e b i t T E T r a n s m i t b u f f e r e m p t y f l a g T I T x D i T r a n s m i t r e g i s t e r e m p t y f l a g T X E P T “0” “1” “0” “ 1 ” “ 0 ” “1” T h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s : P a r i t y i s d i s a b l e d T w o s t o p b i t s C T S f u n c t i o n i s d i s a b l e d T r a n s m i t i n t e r r u p t c a u s e s s e l e c t b i t T r a n s f e r c l o c k T c T c = 1 6 ( n + 1 ) / f i o r 1 6 ( n + 1 ) / fE X T f i f r e q u e n c y o f B R G i s c o u n t s o u r c e f1, f8, fE X T f r e q u e n c y o f B R G i s c o u n t s o u r c e e x t e r n a l c l o c k n v a l u e s e t t o B R G i T r a n s m i t i n t e r r u p t r e q u e s t b i t I R ) “ 0 ” “1” Shown in ( ) are bit symbols. S h o w n i n ( ) a r e b i t s y m b o l s . Tc T r a n s f e r c l o c k SP S t o p p e d p u l s i n g b e c a u s e t r a n s m i t e n a b l e b i t = “ 0 ”Stop bit T r a n s f e r r e d f r o m U A R T i t r a n s m i t b u f f e r r e g i s t e r t o U A R T i t r a n s m i t r e g i s t e r S t a r t b i t D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST D 8 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST D 8 D 0 D 1STS P SP S t o p b i t SP T h e t r a n s f e r c l o c k s t o p s m o m e n t a r i l y a s C T S i s “ H ” w h e n t h e s t o p b i t i s c h e c k e d . T h e t r a n s f e r c l o c k s t a r t s a s t h e t r a n s f e r s t a r t s i m m e d i a t e l y C T S c h a n g e s t o L Data is set in UARTi transmit buffer register S P T r a n s f e r r e d f r o m U A R T i t r a n s m i t b u f f e r r e g i s t e r t o U A R T i t r a n s m i t r e g i s t e r Stop bit D a t a i s s e t i n U A R T i t r a n s m i t b u f f e r r e g i s t e r .“0” C l e a r e d t o “ 0 ” b y s o f t w a r e , o r w h e n a n i n t e r r u p t r e q u e s t i s a c c e p t e d .

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode 100

• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) Figure GA-13. Typical receive timing in UART mode (a) Sleep mode (UART0, UART1) This mode is used to transfer data between specific microcomputers among multiple microcomputers D 0 D 1Start bit Sampled “L” R e c e i v e d a t a t a k e n i n B R G i ' s c o u n t s o u r c e R e c e i v e e n a b l e b i t R x D i T r a n s f e r c l o c k R e c e i v e c o m p l e t e f l a g R T S i Stop bit “ 1 ” 0 ” 0 ” 1 ” H ” L ” T h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s : P a r i t y i s d i s a b l e d O n e s t o p b i t R T S f u n c t i o n i s s e l e c t e d R e c e i v e i n t e r r u p t r e q u e s t b i t “ 0 ” 1 ” Cleared to “0” by software, or when an interrupt request is accepted. Transferred from UARTi receive register to UARTi receive buffer register R e c e p t i o n t r i g g e r e d w h e n t r a n s f e r c l o c k i s g e n e l a t e d b y f a l l i n g e d g e o f s t a r t b i t D 7 connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses 03A016, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O2 101 Serial I/O2 Serial I/O2 is used as the clock synchronous serial I/O and has an ordinary mode and an automatic transfer mode. In the automatic transfer mode, serial transfer is performed through the serial I/O automatic transfer RAM which has up to 256 bytes (addresses 00400 16 to 004FF16). The SRDY2 , SBUSY2 and SSTB2 pins each have a handshake I/O signal function and can select either “H” active or “L” active for active logic. Specification

• 8-bit serial I/O mode (non-automatic transfer)
• Automatic transfer serial I/O mode
• Transfer data length: 8 bits
• Full duplex mode / transmit-only mode selected by bit 5 at address 034216
• When internal clock is selected (bit 2 at address 034216 = “0”) : selected by bits 5 to 7 at address 034816
• When external clock is selected (bit 2 at address 034216 = “1”) : Input from SCLK21 pin, SCLK22 pin(Note 2)
• When internal clock is selected : f(XIN)/4, f(XIN)/8, f(XIN)/16, f(XIN)/32, f(XIN)/64, f(XIN)/128, f(XIN)/256
• When external clock is selected : input cycle 0.95 µs or less
• SSTB2 output / SBUSY2 input or output / SRDY2 input or output chosen
• To start transmission / reception, the following requirements must be met: _ Serial I/O initialization bit (bit 4 at address 034216) = “1” _ When SBUSY2 input, or SRDY2 input is selected : selected input level = “L”
• Furthermore, if external clock is selected, the following requirements must also be met: _ Input level of SCLK21 or SCLK22 = “H”
• To stop transmission and reception, set serial I/O initialization bit (bit 4 at address 034216) to “0” regardless internal clock and external clock.
• 8-bit serial I/O mode : Interrupts requested when 8-bit data transfer is com- pleted
• Automatic transfer serial I/O mode :Interrupts requested when last receive data transfer to Automatic transfer RAM
• SOUT2 P-channel output disable function CMOS output or N-channel open-drain output can be selected
• LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Serial I/O2 clock pin select bit Serial clock input/output can be selected; S CLK21 or SCLK22
• SBUSY output, SSTB2 output select function (only automatic transfer serial mode) SBUSY output, SSTB2 output can be selected; 1-byte data transfer unit or all data transfer unit
• SOUT2 pin control bit Either output active or high-impedance can be selected as a SOUT2 pin state at serial non-transfer . Note 1: It is necessary to set the serial I/O clock pin select bit ( bit 7 at address 034216) Item Serial mode Transfer data format Transfer clock Transfer rate Transmission/reception control Transmission / reception start condition Transmission and reception stop condition Interrupt request generation timing Select function Table GA-1. Specifications of clock synchronous serial I/O2

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O2 102 Figure GA-1. Block Diagram of Serial I/O2 Main data bus Serial I/O2 automatic transfer controller Local data busSerial I/O automatic transfer RAM (0040016—004FF 16) Serial I/O2 control register 3 XIN Serial I/O2 automatic transfer data pointer Address decoder Main address bus Local address bus Serial I/O2 interrupt request Port latch Serial I/O2 counter Synchronous circuit Serial I/O2 synchronous clock selection bit “1” Port latch SCLK21 “0” “1” S CLK2 Internal synchronous clock selection bits Port latch SBUSY2 SSTB2 (SSTB2 pin control bit) Serial transfer status flag “0” “1” “0” “1” “0” “1” Port latch SOUT2 SIN2 Port latch Serial I/O2 register (8) “0” “1” Serial transfer selection bits Divider Serial I/O2 clock pin selection bit SCLK22 “1” “0” Port latch “0” “1” “0” “1” Serial I/O2 clock pin selection bits SRDY2 SRDY2 •SBUSY2 pin control bit SRDY2 •SBUSY2 pin control bit

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O2 103 Figure GA-2. Serial I/O2 Control Registers 1, 2 S e r i a l I / O 2 c o n t r o l r e g i s t e r 2 Symbol Address When reset SIO2CON2 0344 16 0016 Bit name Function RB i t s y m b o l W b 7b 6b 4 b 3b 2b SRDY2 • SBUSY2 pin control bitsS C O N 2 0 SCON21 S C O N 2 2 S C O N 2 3 S e r i a l I / O 2 c o n t r o l r e g i s t e r 1 S y m b o lA d d r e s sW h e n r e s e t S I O C O N 6 0 B i t n a m e FunctionB i t s y m b o l R W b 7b 6b 3b 2b S e r i a l t r a n s f e r s e l e c t b i t sS C O N 1 0 S C O N 1 1 S C O N 1 2 S C O N 1 3 S e r i a l I / O 2 s y n c h r o n o u s c l o c k s e l e c t b i t s SS T B p i n c o n t r o l b i t 0 0 : I n t e r n a l s y n c h r o n o u s c l o c k SS T B p i n i s a n I O p o r t E x t e r n a l s y n c h r o n o u s c l o c k SS T B p i n i s a n I O p o r t I n t e r n a l s y n c h r o n o u s c l o c k SS T B p i n i s a n SS T B o u t p u t I n t e r n a l s y n c h r o n o u s c l o c k SS T B p i n i s a n SS T B o u t p u t 0: Serial I/O initialization 1: Serial I/O enabled S e r i a l I / O i n i t i a l i z a t i o n b i t Transfer mode select bit0 : F u l l d u p l e x ( t r a n s m i t a n d r e c e i v e ) m o d e SI N p i n i s a SI N i n p u t T r a n s m i t o n l y m o d e SI N p i n i s a n I O p o r t S C O N 1 4 S C O N 1 5 Serial I/O2 clock pin select bit T r a n s f e r d i r e c t i o n s e l e c t b i tSCON16 SCON17 0 0 : S e r i a l I / O d i s a b l e d s e r i a l I O p i n s a r e I O p o r t s b i t s s e r i a l I O I n h i b i t A u t o m a t i c t r a n s f e r s e r i a l I O b i t s 0 : L S B f i r s t M S B f i r s t 0:SCLK21 (SCLK22 pin is an I/O port.) 1:SCLK22 (SCLK21 pin is an I/O port.) 0: Functions as each 1-byte signal 1: Functions as signal for all transfer data SBUSY2 output • SSTB2 output function select bit (Valid in automatic transfer mode) S e r i a l t r a n s f e r s t a t u s f l a g 0: Serial transfer completion 1: Serial transferring SCON24 S C O N 2 5 SOUT2 P-channel output disable bit SO U T 2 p i n c o n t r o l b i t a t n o t r a n s f e r s e r i a l d a t a )SCON26 S C O N 2 7 0: Output active 1: Output high-impedance 0: CMOS 3-state (P-channel output is valid.) 1: N-channel open-drain (P-channel output is invalid.) b3b2b1b0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 S R D Y 2 p i nS B U S Y 2 p i n I O p o r tI O p o r t N o t u s e d SR D Y o u t p u tI O p o r t SR D Y o u t p u tI O p o r t I O p o r tS B U S Y i n p u t I O p o r tS B U S Y i n p u t I O p o r tS B U S Y o u t p u t I O p o r tS B U S Y o u t p u t SR D Y i n p u tS B U S Y o u t p u t SR D Y i n p u tS B U S Y o u t p u t SR D Y i n p u tS B U S Y o u t p u t SR D Y i n p u tS B U S Y o u t p u t SR D Y o u t p u tS B U S Y i n p u t SR D Y o u t p u tS B U S Y i n p u t SR D Y o u t p u tS B U S Y i n p u t SR D Y o u t p u tS B U S Y i n p u t b b b b

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O2 104 Figure GA-3. Serial I/O2 automatic transfer data pointer Serial I/O2 control register 3 Symbol Address When reset SIO2CON3 0348 16 000000002 Bit name Function Bit symbol RW b7 b6 b5 b4 b3 b2 b1 b0 Automatic transfer interval set bits TTRAN0 TTRAN1 TTRAN2 TTRAN3 Internal synchronous clock selection bits 000:f(XIN)/4 001:f(XIN)/8 010:f(XIN)/16 011:f(XIN)/32 100:f(XIN)/64 101:f(XIN)/128 110:f(XIN)/256 TTRAN4 TCLK0 TCLK1 TCLK2 00000 :2 cycles of transfer clocks 00001 :3 cycles of transfer clocks 11110 :32 cycles of transfer clocks 11111 :33 cycles of transfer clocks Data is written to a latch and read from a decrement counter. b4b3b2b1b0 b7b6b5 Serial I/O2 automatic transfer data pointer Symbol Address When reset SIO2DP 0340 16 0016 Function R W b7 b6 b5 b4 b3 b2 b1 b0

• Automatic transfer data pointer set Specify the low-order 8 bits of the first data store address on the serial I/O automatic transfer RAM. Data is written into the latch and read from the decrement counter. Serial I/O2 register/transfer counter Symbol Address When reset SIO2 0346 16 0016 Function R W b7 b6 b5 b4 b3 b2 b1 b0
• Number of automatic transfer data set Set the number of automatic transfer data. Set a value one less than number of transfer data. Data is written into the latch and read from the decrement counter.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O2 105 Table GA-2. Functions of the serial I/O2 input/output pins Table GA-2 lists the functions of the serial I/O2 input/output pins Pin name Function Method of selection SOUT2 (P94) Serial data output Serial data input Transfer clock output Transfer clock input Port P94 direction register (bit 4 at address 03F316)= “1” SOUT2 P-channel output disable bit (bit 7 at address 034416)= “0” , “1” SOUT2 pin control bit (bit 6 at address 034416)= “0” , “1” (Outputs dummy data when performing reception only) SIN2 (P93) SCLK21 (P95) Serial I/O2 synchronous clock select bits (bits 2, 3 at address 034216) = “00” , “01” Serial I/O2 clock pin select bit (bit 7 at address 034216) = “0” Serial I/O2 synchronous clock select bits (bits 2, 3 at address 034216) = “01” , “11” Serial I/O2 clock pin select bit (bit 7 at address 034216) = “0” Port P95 direction register (bit 5 at address 03F316)= “0” Port P93 direction register (bit 4 at address 03F316)= “0” Transfer mode select bit (bit 5 at address 034216)= “0” (Input/output port when transfer mode select bit (bit 5 at address 034216)= “1”) Transfer clock output Transfer clock input SCLK22 (P96) Serial I/O2 synchronous clock select bits (bits 2, 3 at address 034216) = “00” , “01” Serial I/O2 clock pin select bit (bit 7 at address 034216) = “1” Serial I/O2 synchronous clock select bits (bits 2, 3 at address 034216) = “01” , “11” Serial I/O2 clock pin select bit (bit 7 at address 034216) = “1” Port P96 direction register (bit 6 at address 03F316)= “0” SRDY input / outputSRDY2 (P90) Set by SRDY2 • SBUSY2 pin control bits (bits 0 to 3 at address 034416) SBUSY input / outputSBUSY2 (P91) Set by SRDY2 • SBUSY2 pin control bits (bits 0 to 3 at address 034416) SBUSY2 output • SSTB2 output function select bit (bit 4 at address 034416)= “0” , “1” SSTB input / outputSSTB2 (P92) Serial I/O2 synchronous clock select bits (bits 2, 3 at address 034216) = “10” , “11” SBUSY2 output • SSTB2 output function select bit (bit 4 at address 034416)= “0” , “1” SOUT2 Output Either output active or high-impedance can be selected as a SOUT2 pin state at serial non-transfer by the SOUT2 pin control bit (bit 6 of address 034416). However, when the external synchronous clock is selected, perform the following setup to put the SOUT2 pin into a high-impedance state. When the SCLK2i ( i = 1, 2) input is “H” after completion of transfer, set the SOUT2 pin control bit to “1”. When the SCLK2i ( i = 1, 2) input goes to “L” after the start of the next serial transfer, the SOUT2 pin control bit is automatically reset to “0” and put into an output active state.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O2 106 Serial I/O2 Mode There are two types of serial I/O2 modes: 8-bit serial I/O mode where automatic transfer RAM is not used, and an automatic transfer serial I/O mode. (1) 8-bit Serial I/O Mode Address 034616 is assigned to the serial I/O2 register. When the internal synchronous clock is selected, a serial transfer of the 8-bit serial I/O is started by a write signal to the serial I/O2 register (address 0346 16). The serial transfer status flag (bit 5 of address 034416) is set to “1” by writing into the serial I/O2 register and reset to “0” after completion of 8-bit transfer. At the same time, a serial I/O2 interrupt request occurs. If the transfer is completed, the receive data is read out from serial I/O2 register. When the external synchronous clock is selected, the contents of the serial I/O2 register are con- tinuously shifted while transfer clocks are input to S CLK21 or SCLK22 . Therefore, the clock needs to be controlled externally. (2) Automatic Transfer Serial I/O Mode Address 034616 is assigned to the transfer counter (1-byte units). The serial I/O2 automatic trans- fer controller controls the write and read operations of the serial I/O2 register. The serial I/O auto- matic transfer RAM is mapped to addresses 00400 16 to 004FF16. Before starting transfer, make sure the 8 low-order bits of the address that contains the beginning data to be serially transferred is set to the automatic transfer data pointer (address 0340 16). When the internal synchronous clock is selected, the transfer interval is inserted between one data and another in the following cases: 1. When using no handshake signal 2. When using the S RDY2 output, SBUSY2 output, and SSTB2 output of the handshake signal inde pendently 3. When using a combination of S RDY2 output and SSTB2 output or a combination of SBUSY2 output and SSTB2 output of the handshake signal The transfer interval can be set in the range of 2 to 23 cycles using the automatic transfer interval set bit (bits 0–4 of address 0348 16 ). Also, when using SBUSY2 output as a signal for each occurrence of the all transfer data, a transfer interval is inserted before the system starts sending or receiving the first data and after the system finished sending or receiving the last data, not just between one data and another. Furthermore, when using S STB2 output, the transfer interval between each 1-byte data is extended by 2 cycles from the set value no matter how the SBUSY2 output. SSTB2 output function select bit (bit 4 of address 034416) is set. When using SBUSY2 output and SSTB2 output in combination as a signal for each occurrence of the all transfer data, the transfer interval after the system finished sending or receiving the last data is extended by 2 cycles from the set value. When an external synchronous clock is selected, the automatic transfer interval is disabled.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O2 107 Figure GA-5. Automatic Transfer Serial I/O Operation 004FF16 Automatic transfer RAM Transfer counter Automatic transfer data pointer Serial I/O2 register 0045216 0045116 0045016 0044F16 0044E16 0040016 0416 5216 SIN2 SOUT2 When the internal synchronous clock is selected, automatic serial transfer starts by writing 1 less than the number of transfer bytes to the transfer counter (address 034616). When an external sync clock is selected, automatic serial transfer starts by writing 1 less than the number of transfer bytes to the transfer counter and the transfer clock is input. In this case, allow for at least 5 cycles of internal system clock before the transfer clock is input after writing to the transfer counter. Also, for data to data transfer intervals, allow at least 5 cycles of internal system clock reckoning from a rise of clock at the last bit of one-byte data. Regardless of whether the internal or external synchronous clock is selected, the automatic transfer data pointer and the transfer counter are decreased after each 1-byte data is received and then written into the automatic transfer RAM. The serial transfer status flag (bit5 of address 0344 16) is set to “1” by writing data into the transfer counter. The serial transfer status flag is reset to “0” after the last data is written into the automatic transfer RAM. At the same time, a serial I/O2 interrupt request occurs. The values written in the automatic transfer data pointer (address 0340 16) and the automatic transfer interval set bits (bit 0 to bit 4 of address 034816) are held in the latch. When data is written into the transfer counter, the values latched in the automatic transfer data pointer (address 0340 16) and the automatic transfer interval set bits (bit 0 to bit 4) are transferred to the decrement counter.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O2 108 Handshake Signal There are five types of handshake signal : SSTB2 output, SBUSY2 input/output, and SRDY2 input/output. (1) SSTB2 output signal The SSTB2 output is a signal to inform an end of transmission/reception to the serial transfer destina- tion. The SSTB2 output signal can be used only when the internal synchronous clock is selected. In the initial status [ serial I/O initialization bit (bit 4 of address 034216) = “0” ], the SSTB2 output goes to “L” (bits 2, 3 of address 034216=11), or the SSTB2 output goes to “H” (bits 2, 3 of address 034216=10). At the end of transmit/receive operation, after the all data of the serial I/O2 register (address 034616) is output from SOUT2 , SSTB2 output is “H” (or SSTB2 output is “L”) in the period of 1 cycle of the transfer clock. Furthermore, after 1 cycle, the serial transfer status flag (bit 5 of address 034416) is reset to “0”. In the automatic transfer serial I/O mode, whether the SSTB2 output is to be output at an end of each 1-byte data or after completion of transfer of all data can be selected by the SBUSY2 output • SSTB2 output function select bit (bit 4 of address 034416). Figure GA-6. SSTB2 Output Operation "1" "0" SSTB2 (output) "H" "L" D 0 Tc D 1 D 2 D 3 D 4 D 5 D 6 D 7 "1" "0" "H" "L" D 0 Tc D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Automatic transfer interval

• Serial operation used SSTB2 output Operation mode : 8-bit serial I/O mode Transfer clock : Internal synchronous clock SSTB2 output timing : Each 1-byte data Internal clock Serial transfer status flag (bit 5 at address 0344 16) SCLK2i (i=1, 2)(output) SOUT2 Tc : Internal synchronous clock is selected by bits 5 to 7 of address 034816
• Serial operation used SSTB2 output Operation mode : Automatic transfer serial I/O mode Transfer clock : Internal synchronous clock S STB2 output timing : Each transfer of all data Internal clock Serial transfer status flag (bit 5 at address 0344 16) SCLK2i (i=1, 2)(output) SSTB2 (output) SOUT2 Tc : Internal synchronous clock is selected by bits 5 to 7 of address 034816

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O2 109 Figure GA-8. SBUSY2 Input Operation (2) Figure GA-7. SBUSY2 Input Operation (1) (2) SBUSY2 input signal The SBUSY2 input is a signal requested to stop of transmission/reception from the serial transfer des- tination. When the internal synchronous clock is selected, input a “H” level signal into the SBUSY2 input (or a “L” level signal into the SBUSY2 input) in the initial status [serial I/O initialization bit (bit 4 of address 034216) = “0”]. When a “L” level signal into the SBUSY2 ( or “H” on SBUSY2 ) input for 1.5 cycles or more of transfer clock, transfer clocks are output from SCLK2i (i = 1, 2), and transmit/receive operation is started. When SBUSY2 input is driven “H” (or SBUSY2 input is driven “L”) during transmit/receive operation, the transfer clock being output from SCLK2i (i = 1, 2) remains active until after the system finishes sending or receiving the designated number of bits, without stopping the transmit/receive operation immediately. The handshake unit of the 8-bit serial I/O is 8 bits, and that of the automatic transfer serial I/O is 8 bits. Internal clock "1" "0" "H" "L" Tc D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 1.5 cycle or more

• Serial operation used SBUSY2 input Operation mode : 8-bit serial I/O mode Transfer clock : Internal synchronous clock SBUSY2 input timing : Each 1-byte data Serial transfer status flag (bit 5 at address 0344 16) SCLK2i (i = 1, 2)(output) SOUT2 SBUSY2 (input) Tc : Internal synchronous clock is selected by bits 5 to 7 of address 034816 "1" "0" "H" "L" Note: The last output data D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Invalid Note
• Serial operation used SBUSY2 input Operation mode : 8-bit serial I/O mode Transfer clock : External synchronous clock SBUSY2 input timing : Each 1-byte data Serial transfer status flag (bit 5 at address 0344 16) SCLK2i (i = 1, 2)(input) SOUT2 SBUSY2 (input) High-impedance High-impedance When the external synchronous clock is selected, input a “H” level signal into the SBUSY2 input (or a “L” level signal into the SBUSY2 input) in the initial status[serial I/O initialization bit (bit 4 of address 034216) = “0”]. At this time, the transfer clock become invalid. The transfer clock become valid while a “L” level signal is input into the SBUSY2 input (or a “H” level signal into the SBUSY2 input) and transmit/receive operation work. When changing the input values into the SBUSY2 (or SBUSY2 ) input at these operations, change them when the transfer clock input is in a “H” state. When the high-impedance of the SOUT2 output is selected by the SOUT2 pin control bit (bit 6 of address 034416), the SOUT2 becomes high-impedance, while a “H” level signal is input into the SBUSY2 input (or a “L” level signal into the SBUSY2 input.)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O2 110 Figure GA-9. SBUSY2 Output Operation (1) Figure GA-10. SBUSY2 Output Operation (2) Internal clock "1" "0" "H" "L" D 0 Tc TC : Internal synchronous clock is selected by bits 5 to 7 of address 034816 D 1 D 2 D 3 D 4 D 5 D 6 D 7

• Serial operation used SBUSY2 output Operation mode : 8-bit serial I/O mode Transfer clock : Internal synchronous clock SBUSY2 output timing : Each 1-byte data Serial transfer status flag (bit 5 at address 0344 16) SOUT2 SCLK2i (i = 1, 2)(output) SBUSY2 (output) "1" "0" "H" "L" D 0SOUT2 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Write to serial I/O register (Address 034616)
• Serial operation used SBUSY2 output Operation mode : 8-bit serial I/O mode Transfer clock : External synchronous clock S BUSY2 output timing : Each 1-byte data Serial transfer status flag (bit 5 at address 0344 16) SCLK2i (i = 1, 2)(Input) SBUSY2 (output) (3) SBUSY2 output signal The SBUSY2 output is a signal which requests to stop of transmission/reception to the serial transfer destination. In the automatic transfer serial I/O mode, regardless of the internal or external synchro- nous clock, whether the SBUSY2 output is to be output at transfer of each 1-byte data or during transfer of all data can be selected by the SBUSY2 output • SSTB2 output function select bit (bit 4 of address 034416). In the initial status[ serial I/O initialization bit (bit 4 of address 034216) = “0” ], the status in which the SBUSY2 outputs “H” (or the SBUSY2 outputs “L”). When the internal synchronous clock is selected, in the 8-bit serial I/O mode and the automatic trans- fer serial I/O mode (S BUSY2 output function: each 1-byte signal is selected), the SBUSY2 output goes to “L” (or the SBUSY2 output goes to “H”) before 0.5 cycle of the timing at which the transfer clock goes to “L” . In the automatic transfer serial I/O mode (the SBUSY2 output function: all transfer data is selected), the SBUSY2 output goes to “L” (or the SBUSY2 output goes to “H”) when the first transmit data is written into the serial I/O2 register (address 034616). When the external synchronous clock is selected, the SBUSY2 output goes to “L” (or the SBUSY2 output goes to “H”) when transmit data is written into the serial I/O2 register(address 034616), regardless of the serial I/O transfer mode. At termination of transmit/receive operation, in the 8-bit serial I/O mode, the S BUSY2 output goes to “H” (or the SBUSY2 output returns to “L”), when the serial transfer status flag is set to “0”, regardless of whether the internal or external synchronous clock is selected. Furthermore, in the automatic transfer serial I/O mode (S BUSY2 output function: each 1-byte signal is selected), the SBUSY2 output goes to “H” (or the SBUSY2 output goes to “L”) each time 1-byte of receive data is written into the automatic trans- fer RAM.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O2 111 Figure GA-11. SBUSY2 Output Operation (3) Internal clock "1" "0" "H" "L" D 0 Tc D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Automatic transfer interval Automatic transfer RAM Serial I/O2 register Serial I/O2 register Automatic transfer RAM

• Serial operation used SBUSY2 output Operation mode : Automatic transfer serial I/O mode Transfer clock : Internal synchronous clock S BUSY2 output timing : Each 1-byte data Serial transfer status flag (bit 5 at address 0344 16) SCLK2i (i = 1, 2)(output) SOUT2 Tc : Internal synchronous clock is selected by bits 5 to 7 of address 034816 SBUSY2 (output) Internal clock "1" "0" "H" "L" D 0 Tc D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Automatic transfer interval Automatic transfer RAM Serial I/O2 register Serial I/O2 register Automatic transfer RAM
• Serial operation used SBUSY2 output Operation mode : Automatic transfer serial I/O mode Transfer clock : Internal synchronous clock S BUSY2 output timing : Each transfer of all data Serial transfer status flag (bit 5 at address 0344 16) SCLK2i (i = 1, 2)(output) SOUT2 Tc : Internal synchronous clock is selected by bits 5 to 7 of address 034816 SBUSY2 (output)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O2 112 Figure GA-12. SRDY2 Output Operation Figure GA-13. SRDY2 Input Operation

• Serial operation used SRDY2 output Internal clock SRDY2 (output) "H" "L" Tc Tc : Internal synchronous clock is selected by bits 5 to 7 of address 034816 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 SCLK2i (i = 1, 2) (output) SOUT2 Operation mode : 8-bit serial I/O mode Transfer clock : Internal synchronous clock "1" "0" Serial transfer status flag (bit 5 at address 034416)
• Serial operation used SRDY2 input Internal clock "1" "0" SRDY2 (input) "H" "L" Tc Tc : Internal synchronous clock is selected by bits 5 to 7 of address 034816 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 1.5 cycle or more SCLK2i (i = 1, 2) (output) SOUT2 Operation mode : 8-bit serial I/O mode Transfer clock : Internal synchronous clock Serial transfer status flag (bit 5 at address 034416) (4) SRDY2 output signal The SRDY2 output is a transmit/receive enable signal which informs the serial transfer destination that transmit/receive is ready. In the initial status[serial I/O initialization bit (bit 4 of address 034216) = “0” ], the SRDY2 output goes to “L” (or the SRDY2 output goes to “H”). When the transmitted data is written to the serial I/O2 register (address 034616), the SRDY2 output goes to “H” (or the SRDY2 output goes to “L”). When a transmit/receive operation is started and the transfer clock goes to “L”, the SRDY2 output goes to “L” (or the SRDY2 output goes to “H”). (5) SRDY2 input signal The SRDY2 input is a signal for receiving a transmit/receive ready completion signal from the serial transfer destination. The SRDY2 input signal becomes valid only when the SRDY2 input and the SBUSY2 output are used. When the internal synchronous clock is selected, input a “L” level signal into the SRDY2 input (or a “H” level signal into the SRDY2 input) in the initial status[serial I/O initialization bit (bit 4 of address 034216) = “0” ]. When a “H” level signal is input into the SRDY2 input (or a “L” level signal is input into the SRDY2 input) for a period of 1.5 cycles or more of transfer clock, transfer clocks are output from the SCLK2i (i = 1, 2) output and a transmit/receive operation is started. When SRDY2 input is driven “L” (or SRDY2 input is driven “H”) during transmit/receive operation, the transfer clock being output from SCLK2i (i = 1, 2) remains active until after the system finishes sending or receiving the designated number of bits, without stopping the transmit/receive operation immediately. The handshake unit of the 8-bit serial I/O is 8 bits, and that of the automatic transfer serial I/O is 8 bits. When the external synchronous clock is selected, the S RDY2 input becomes one of the triggers to output the SBUSY2 signal. To start a transmit/receive operation (SBUSY2 output: “L”, (or SBUSY2 output: “H”)), input a “H” level signal into the SRDY2 input (or a “L” level signal into the SRDY2 input,) and also write transmit data into the serial I/O2 register (address 034616).

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O2 113 Figure GA-14. Handshake Operation at Serial I/O2 Mutual Connecting (1) Figure GA-15. Handshake Operation at Serial I/O2 Mutual Connecting (2) A: B: SCLK2i (i = 1, 2) SRDY2 SBUSY2 SBUSY2 SRDY2 SCLK2i (i = 1, 2) Write to serial I/O2 register SCLK2i (i = 1, 2) SRDY2 SBUSY2 Internal synchronous clock selection External synchronous clock selection Write to serial I/O2 register A: B: SCLK2i (i= 1, 2) SRDY2 SBUSY2 SBUSY2 SRDY2 SCLK2i (i= 1, 2) Write to serial I/O2 register SCLK2i (i= 1, 2) SRDY2 SBUSY2 Internal synchronous clock selection External synchronous clock selection Write to serial I/O2 register

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D converter 114 Item Performance Method of A-D conversion Successive approximation (capacitive coupling amplifier) Analog input voltage (Note 1) 0V to AVCC (VCC ) Operating clock φAD (Note 2) VCC = 5V f AD /divide-by-2 of fAD /divide-by-4 of fAD , fAD =f(XIN) VCC = 3V divide-by-2 of fAD /divide-by-4 of fAD , fAD =f(XIN) Resolution 8-bit or 10-bit (selectable) Absolute precision V CC = 5V • Without sample and hold function ±3LSB

• With sample and hold function (8-bit resolution) ±2LSB
• Without sample and hold function (10-bit resolution) ±3LSB VCC = 3V • Without sample and hold function (8-bit resolution)(Note 3) ±2LSB Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 Analog input pins 8pins (AN 0 to AN7) A-D conversion start condition•Software trigger A-D conversion starts when the A-D conversion start flag changes to “1” Conversion speed per pin •Without sample and hold function 8-bit resolution: 49 φAD cycles, 10-bit resolution: 59 φAD cycles
• With sample and hold function 8-bit resolution: 28 φAD cycles, 10-bit resolution: 33 φAD cycles Note 1: Does not depend on use of sample and hold function. Note 2: Without sample and hold function, set the φAD frequency to 250kHz min. With the sample and hold function, set the φAD frequency to 1MHz min. Note 3: Only mask ROM version. A-D Converter The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P10 0 to P107 also function as the analog signal input pins. The direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF ) when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from V REF , reducing the power dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF . The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses. Table JA-1 shows the performance of the A-D converter. Figure JA-1 shows the block diagram of the A-D converter, and Figures JA-2 and JA-3 show the A-D converter-related registers. Table JA-1. Performance of A-D converter

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D converter 115 Figure JA-1. Block diagram of A-D converter A D fA D A - D c o n v e r s i o n r a t e s e l e c t i o n ( 0 3 C 11 6, 0 3 C 01 0 3 C 3 6, 0 3 C 21 (03C516, 03C416) (03C716, 03C616) (03C916, 03C816) 0 3 C B 6, 0 3 C A1 0 3 C D 6, 0 3 C C 1 (03CF16, 03CE16) CKS 1=1 C K S 0 = 0 A-D register 0(16) A - D r e g i s t e r 1 ( 1 6 ) A - D r e g i s t e r 2 ( 1 6 ) A-D register 3(16) A-D register 4(16) A-D register 5(16) A - D r e g i s t e r 6 ( 1 6 ) A - D r e g i s t e r 7 ( 1 6 ) R e s i s t o r l a d d e r S u c c e s s i v e c o n v e r s i o n r e g i s t e r A N 0 A N 1 A N 2 A N 3 AN 5 AN 6 A N 7 A - D c o n t r o l r e g i s t e r 0 ( a d d r e s s 0 3 D 61 A - D c o n t r o l r e g i s t e r 1 ( a d d r e s s 0 3 D 7 Vref VIN V C U T = 0 D a t a b u s h i g h - o r d e r D a t a b u s l o w - o r d e r VR E F A VS S AN 4 VCUT =1 C K S 0 = 1 C K S 1 = 0 C H 2 , C H 1 , C H 0 = 0 0 0 C H 2 , C H 1 , C H 0 = 0 0 1 C H 2 , C H 1 , C H 0 = 0 1 0 C H 2 , C H 1 , C H 0 = 0 1 1 CH 2,CH 1,CH 0=100 CH 2,CH 1,CH 0=101 CH 2,CH 1,CH 0=110 C H 2 , C H 1 , C H 0 = 1 1 1 D e c o d e r C o m p a r a t o r Addresses

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D converter 116 Figure JA-2. A-D converter-related registers (1) A-D control register 0 (Note) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bit0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected CH0 CH1 CH2 A-D operation mode select bit 0 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 Repeat sweep mode 1 MD0 MD1 Must always be “0”. ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selected CKS0 W R A-D control register 1 (Note) Symbol Address When reset ADCON1 03D7 16 0016 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bitSCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit A-D operation mode select bit 1 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 0 : Vref not connected 1 : Vref connected Must always be “0”. W R b2 b1 b0 b4 b3 When single sweep and repeat sweep mode 0 are selected 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) b1 b0 When repeat sweep mode 1 is selected 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) b1 b0 Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Frequency select bit 1 0 : fAD /2 or fAD /4 is selected 1 : fAD is selected CKS1 Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. 0 0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D converter 117 Figure JA-3. A-D converter-related registers (2) Eight low-order bits of A-D conversion result A-D control register 2 (Note) Symbol Address When reset ADCON2 03D4 16 XXXXXXX0 2 Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion method select bit

0 Without sample and hold

1 With sample and hold

Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. A-D register i Symbol Address When reset ADi (i=0 to 7)03C0 16 to 03CF16 Indeterminate Function W R (b15) b7 b7 b0 b0 (b8)

• During 10-bit mode Two high-order bits of A-D conversion result Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read , turns out to be “0”.
• During 8-bit mode When read, the content is indeterminate Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D converter 118 (1) One-shot mode In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conversion. Table JA-2 shows the specifications of one-shot mode. Figure JA-4 shows the A-D control register in one-shot mode. Table JA-2. One-shot mode specifications Item Specification Function The pin selected by the analog input pin select bit is used for one A-D conversion Start condition Writing “1” to A-D conversion start flag Stop condition •End of A-D conversion (A-D conversion start flag changes to “0”)

• Writing “0” to A-D conversion start flag Interrupt request generation timingEnd of A-D conversion Input pin One of AN 0 to AN7, as selected Reading of result of A-D converterRead A-D register corresponding to selected pin Figure JA-4. A-D conversion register in one-shot mode A-D control register 0 (Note) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 RBit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bitCH0 CH1 CH2 A-D operation mode select bit 0 MD0 MD1 ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 00: fAD /4 is selected 1: fAD /2 is selected CKS0 W 0 0 A-D control register 1 (Note) Symbol Address When reset ADCON1 03D7 16 0016 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bit SCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit A-D operation mode select bit 1 0 : Any mode other than repeat sweep mode 1 1 : Vref connected W R Invalid in one-shot mode 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected b2 b1 b0 0 0 : One-shot mode b4 b3 Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Frequency select bit10 : fAD /2 or fAD /4 is selected 1 : fAD is selected CKS1 Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Must always be “0”. Must always be “0”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D converter 119 (2) Repeat mode In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion. Table JA-3 shows the specifications of repeat mode. Figure JA-5 shows the A-D control register in repeat mode. Table JA-3. Repeat mode specifications Item Specification Function The pin selected by the analog input pin select bit is used for repeated A-D conversion Star condition Writing “1” to A-D conversion start flag Stop condition Writing “0” to A-D conversion start flag Interrupt request generation timingNone generated Input pin One of AN 0 to AN7, as selected Reading of result of A-D converterRead A-D register corresponding to selected pin Figure JA-5. A-D conversion register in repeat mode A-D control register 0 (Note) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bit CH0 CH1 CH2 A-D operation mode select bit 0 MD0 MD1 ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selected CKS0 W R 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected b2 b1 b0 0 1 : Repeat mode b4 b3 Note: If the A-D control register is rewritten during A-D conversion, the conversin result is indeterminate. A-D control register 1 (Note) Symbol Address When reset ADCON1 03D7 16 0016 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bitSCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit A-D operation mode select bit 1 1 : Vref connected W R Invalid in repeat mode Frequency select bit 10 : fAD /2 or fAD /4 is selected 1 : fAD is selected CKS1 0 : Any mode other than repeat sweep mode 1 Note: If the A-D control register is rewritten during A-D conversion, the conversn result is indeterminate. 0 0 Must always be “0”. Must always be “0”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D converter 120 (3) Single sweep mode In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D conversion. Table JA-4 shows the specifications of single sweep mode. Figure JA-6 shows the A-D control register in single sweep mode. Table JA-4. Single sweep mode specifications Item Specification Function The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion Start condition Writing “1” to A-D converter start flag Stop condition •End of A-D conversion (A-D conversion start flag changes to “0”, except when external trigger is selected)

• Writing “0” to A-D conversion start flag Interrupt request generation timingEnd of A-D conversion Input pin AN 0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Reading of result of A-D converterRead A-D register corresponding to selected pin Figure JA-6. A-D conversion register in single sweep mode A-D control register 0 (Note) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bitCH0 CH1 CH2 A-D operation mode select bit 0 1 0 : Single sweep modeMD0 MD1 ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selected CKS0 WR A-D control register 1 (Note) Symbol Address When reset ADCON1 03D7 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bitSCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit 0 : Any mode other than repeat sweep mode 1A-D operation mode select bit 1 1 : Vref connected W R Invalid in single sweep mode Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. b4 b3 When single sweep and repeat sweep mode 0 are selected 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) b1 b0 Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Frequency select bit 10 : fAD /2 or fAD /4 is selected 1 : fAD is selected CKS1 Must always be “0”. Must always be “0”. 0 0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D converter 121 (4) Repeat sweep mode 0 In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep A-D conversion. Table JA-5 shows the specifications of repeat sweep mode 0. Figure JA-7 shows the A- D control register in repeat sweep mode 0. Table JA-5. Repeat sweep mode 0 specifications Item Specification Function The pins selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion Start condition Writing “1” to A-D conversion start flag Stop condition Writing “0” to A-D conversion start flag Interrupt request generation timingNone generated Input pin AN 0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Reading of result of A-D converterRead A-D register corresponding to selected pin (at any time) Figure JA-7. A-D conversion register in repeat sweep mode 0 A-D control register 0 (Note) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bitCH0 CH1 CH2 A-D operation mode select bit 0 1 1 : Repeat sweep mode 0MD0 MD1 ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selected CKS0 WR A-D control register 1 (Note) Symbol Address When reset ADCON1 03D7 16 0016 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bitSCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit 1 : Any mode other than repeat sweep mode 1A-D operation mode select bit 1 1 : Vref connected W R 1 1 Invalid in repeat sweep mode 0 Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. b4 b3 When repeat sweep mode 1 is selected 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) b1 b0 Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Frequency select bit 10 : fAD /2 or fAD /4 is selected 1 : fAD is selected CKS1 Must always be “0”. Must always be “0”. 0 0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D converter 122 Item Specification Function All pins perform repeat sweep A-D conversion, with emphasis on the pin or pins selected by the A-D sweep pin select bit Example : AN0 selected -> AN0 -> AN1 -> AN0 -> AN2 -> AN0 -> AN3, etc Start condition Writing “1” to A-D conversion start flag Stop condition Writing “0” to A-D conversion start flag Interrupt request generation timingNone generated Input pin Emphasis on the pin AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins) Reading of result of A-D converterRead A-D register corresponding to selected pin (at any time) (5) Repeat sweep mode 1 In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using the A-D sweep pin select bit. Table JA-6 shows the specifications of repeat sweep mode 1. Figure JA-8 shows the A-D control register in repeat sweep mode 1. Table JA-6. Repeat sweep mode 1 specifications Figure JA-8. A-D conversion register in repeat sweep mode 1 A-D control register 0 (Note) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bitCH0 CH1 CH2 A-D operation mode select bit 0 1 1 : Repeat sweep mode 1MD0 MD1 ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selected CKS0 WR A-D control register 1 (Note) Symbol Address When reset ADCON1 03D7 16 0016 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bitSCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit 1 : Repeat sweep mode 1A-D operation mode select bit 1 1 : Vref connected W R 1 1 Invalid in repeat sweep mode 0 Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. b4 b3 When repeat sweep mode 1 is selected 0 0 : AN0 (1 pins) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) b1 b0 Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Frequency select bit 10 : fAD /2 or fAD /4 is selected 1 : fAD is selected CKS1 Must always be “0”. Must always be “0”. 0 0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D converter 123 (a) Sample and hold Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”. When sample and hold is selected, the rate of conversion of each pin increases. As a result, 28 φ AD cycles are achieved with 8-bit resolution and 33 φ AD cycles with 10-bit resolution. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and hold is to be used.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER D-A converter 124 D-A Converter This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of this type. D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 (D-A output enable bits) of the D-A control register decide if the result of conversion is to be output. Do not set the target port to output mode if D-A conversion is to be performed. Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register. V = V REF X n/ 256 (n = 0 to 255) VREF : reference voltage Table JB-1 lists the performance of the D-A converter. Figure JB-1 shows the block diagram of the D-A converter. Figure JB-2 shows the D-A control register. Figure JB-3 shows the D-A converter equivalent circuit. Table JB-1. Performance of D-A converter Item Performance Conversion method R-2R method Resolution 8 bits Analog output pin 2 channels Figure JB-1. Block diagram of D-A converter /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines P97/DA0/CLKOUT /DIMOUT /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines P96/DA1/SCLK22 Data bus low-order bits D-A register0 (8) R-2R resistor ladder D-A0 output enable bit D-A register1 (8) R-2R resistor ladder D-A1 output enable bit (Address 03D816) (Address 03DA16)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER D-A converter 125 Figure JB-2. D-A control register D-A control register Symbol Address When reset DACON 03DC 16 0016 b7 b6 b5 b4 b3 b2 b1 b0 D-A0 output enable bit DA0E Bit symbol Bit name Function R W 0 : Output disabled 1 : Output enabled D-A1 output enable bit 0 : Output disabled 1 : Output enabled DA1E Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. D-A register Symbol Address When reset DAi (i = 0,1) 03D816, 03DA 16 Indeterminate W R b7 b0 Function R W Output value of D-A conversion Figure JB-3. D-A converter equivalent circuit VREF AV SS R R R R R R R DA0 MSB LSB D-A0 output enable bit "0" "1" D-A0 register0 Note 1: The above diagram shows an instance in which the D-A register is assigned 2A16. Note 2: The same circuit as this is also used for D-A1. Note 3: To reduce the current consumption when the D-A converter is not used, set the D-A output enable bit to 0 and set the D-A register to 0016 so that no current flows in the resistors Rs and 2Rs.

t Mitsubishi microcomputers M30218 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CRC Calculation Circuit 126 CRC Calculation Circuit The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcom- puter uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code. The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC code is set in a CRC data register each time one byte of data is transferred to a CRC input register after writing an initial value into the CRC data register. Generation of CRC code for one byte of data is com- pleted in two machine cycles. Figure UC-1 shows the block diagram of the CRC circuit. Figure UC-2 shows the CRC-related registers. Figure UC-3 shows the calculation example using the CRC calculation circuit Figure UC-2. CRC-related registers Figure UC-1. Block diagram of CRC circuit /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines CRC code generating circt x16 + x12 + x5 + 1 Eight low-order bits /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Eight high-order bits Data bus high-order bits Data bus low-order bits /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines CRC data register (16) CRC input register (8) (Addresses 03BD16, 03BC16) (Address 03BE16) Symbol Address When reset CRCD 03BD 16, 03BC16 Indeterminate b7 b0 b7 b0 (b15) (b8) CRC data register W R CRC calculation result output register Function Values that can be set 000016 to FFFF16 Symbo Address When reset CRCIN 03BE 16 Indeterminate b7 b0 CRC input register W R Data input register Function Values that can be set 0016 to FF16

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CRC Calculation Circuit 127 Figure UC-3. Calculation example using the CRC calculation circuit b15 b0 (1) Setting 000016 CRC data register CRCD [03BD16, 03BC16] b0 b7 b15 b0 (2) Setting 0116 CRC input register CRCIN [03BE16] 2 cycles After CRC calculation is complete CRC data register CRCD [03BD16, 03BC16] 118916 Stores CRC code b0 b7 b15 b0 (3) Setting 2316 CRC input register CRCIN [03BE16] After CRC calculation is complete CRC data register CRCD [03BD16, 03BC16]0A4116 Stores CRC code The code resulting from sending 0116 in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial, (X16 + X12 + X5 + 1), becomes the remainder resulting from dividing (1000 0000) X16 by (1 0001 0000 0010 0001) in conformity with the modulo-2 operation. Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000) corresponds to 118916 in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC operation. Also switch between the MSB and LSB of the result as stored in CRC data. 1 0001 0000 0010 00011000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 1000 1000 LSB MSB LSB MSB 98 1 1 Modulo-2 operation is operation that complies with the law given below. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 -1 = 1

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Ports 128 Programmable I/O Ports There are 48 programmable I/O ports: P3, P4 and P7 to P10. Each port can be set independently for input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P3 and P4 0 to P43 are high-breakdown-voltage, P-channel open drain outputs, and have no built-in pull- down resistance. Figures UA-1, UA-2 show the programmable I/O ports. Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices. To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A con- verter), they function as outputs regardless of the contents of the direction registers. When pins are to be used as the outputs for the D-A converter, do not set the direction registers to output mode. See the descriptions of the respective functions for how to set up the built-in peripheral devices. (1) Direction registers Figure UA-3 shows the direction registers. These registers are used to choose the direction of the programmable I/O ports. Each bit in these regis- ters corresponds one for one to each I/O pin. (2) Port registers Figure UA-4 shows the port registers. These registers are used to write and read data for input and output to and from an external device. A port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit in port registers corresponds one for one to each I/O pin. (3) Pull-up control registers Figure UA-5 shows the pull-up control registers. The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. Note: P3, P4 0 to P43 have no built-in pull-up resistance, because of these pin's are high-breakdown- voltage, P-channel open drain outputs. Exclusive High-breakdown-voltage Output Ports There are 40 exclusive output Ports: P0 to P2, P5 and P6. All ports have structure of high-breakdown-voltage P-channel open drain output. Exclusive output ports except P2 have built-in pull-down resistance. Figure UA-1 shows the configuration of the exclusive high-breakdown-voltage output ports.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Ports 129 Figure UA-1. Programmable I/O ports (1) P70 to P72, P80 to P85, P87, P93 (inside dotted-line included) P86 (inside dotted-line not included) P30 to P37, P40 to P43 P44, P92,P94 Data bus Pull-up selection Data bus Data bus Data bus Pull-up selection output “1” output “1” Input to respective peripheral functions Direction register Port latch Port latch Port latch Direction register Port latch Direction register P00 to P07, P10 to P17, P50 to P57, P60 to P67, (inside dotted-line included) P20 to P27 (inside dotted-line not included) Output VEE

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Ports 130 Figure UA-2. Programmable I/O ports (2) P45 to P47, P73 to P77 P90, P91, P95 P96 (inside dotted-line included) P97 (inside dotted-line not included) Data bus Pull-up selection Data bus Direction register Port latch Pull-up selection Analog output D-A output enabled Direction register Port latch output “1” output “1” P100 to P107 Data bus Pull-up selection Direction register Port latch Analog input Input to respective peripheral functions Input to respective peripheral functions

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Ports 131 Figure UA-3. Direction register P o r t P i d i r e c t i o n r e g i s t e r S y m b o lA d d r e s s W h e n r e s e t P D i i t o e x c e p t E E E 6 001 F F F 6 001 B i t n a m e FunctionB i t s y m b o l WR b P D i _ 0P o r t P i0 d i r e c t i o n r e g i s t e r P D i _ 1P o r t P i 1 d i r e c t i o n r e g i s t e r P D i _ 2P o r t P i2 d i r e c t i o n r e g i s t e r P D i _ 3P o r t P i3 d i r e c t i o n r e g i s t e r P D i _ 4P o r t P i4 d i r e c t i o n r e g i s t e r P D i _ 5P o r t P i5 d i r e c t i o n r e g i s t e r P D i _ 6P o r t P i6 d i r e c t i o n r e g i s t e r P D i _ 7P o r t P i7 d i r e c t i o n r e g i s t e r 0 : I n p u t m o d e F u n c t i o n s a s a n i n p u t p o r t O u t p u t m o d e F u n c t i o n s a s a n o u t p u t p o r t ( i = 3 t o 1 0 e x c e p t 5 , 6 ) Port Pi register Symbol Addres When reset Pi (i = 0 to 10) 03E016, 03E116, 03E416, 03E516, 03E816 Indeterminate 03E916, 03EC16, 03ED16, 03F016, 03F116, 03F416 Indeterminate Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 Pi_0 Port Pi 0 register Pi_1 Port Pi 1 register Pi_2 Port Pi 2 register Pi_3 Port Pi 3 register Pi_4 Port Pi 4 register Pi_5 Port Pi 5 register Pi_6 Port Pi 6 register Pi_7 Port Pi 7 register Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : “L” level data 1 : “H” level data (i = 0 to 10) Figure UA-4. Port register

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Ports 132 Figure UA-5. Pull-up control register Pull-up control register 0 Symbol Address When reset PUR0 03FD 16 0016 Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 PU01 P4 4 to P47 pull-up PU06 P7 0 to P73 pull-up PU07 P7 4 to P77 pull-up Pull-up control register 1 Symbol Address When reset PUR1 03FE 16 0016 Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 PU10 P8 0 to P83 pull-up PU11 P8 4 to P87 pull-up PU12 P9 0 to P93 pull-up PU13 P9 4 to P97 pull-up PU14 P10 0 to P103 pull-up PU15 P10 4 to P107 pull-up The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Ports 133 Table UA-1. Example connection of unused pins Figure UA-6. Example connection of unused pins Pin name Connection Ports P3, P4, P7 to P10 Specify output mode, and leave these pins open; or specify input mode, and connect to VSS via resistor (pull-down) Note 1: With external clock input to XIN pin. Note 2: Connect a bypass capacitor. XOUT (Note 1), VEE AV SS , VREF AV CC Open Connect to VCC (Note 2) Connect to VSS (Note 2) Ports P0 to P2, P5, P6 Leave these pins open CNV SS Connect to VSS via resistor Port P3, P4, P7 to P10 (Input mode) (Output mode) Port P0 to P2, P5, P6 (Output mode) XOUT AVCC (Note) CNV SS AVSS (Note) VREF (Note) Microcomputer VCC VSS Open Open Open VEE Open Note: Connect a bypass capacitor.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-down 134 Power Dissipation Calculating Method (Fixed number depending on microcomputer’s standard)

• VOH output fall voltage of high-breakdown port 2 V (max.); | Current value | = at 18 mA
• Resistor value = 68 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V X 38 mA = 190 mW (Fixed number depending on use condition)
• Apply voltage to VEE pin: Vcc – 50 V
• Timing number a; digit number b; segment number c
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: d
• All segment number during repeat cycle: e (= a X c)
• Total number of built-in resistor: for digit; f, for segment; g
• Digit pin current value h (mA)
• Segment pin current value i (mA) (1) Digit pin power dissipation {h X b X (1–Toff / Tdisp) X voltage} / a (2) Segment pin power dissipation {i X d X (1–Toff / Tdisp) X voltage} / a (3) Pull-down resistor power dissipation (digit) {power dissipation per 1 digit X (b X f / b) X (1–Toff / Tdisp) } / a (4) Pull-down resistor power dissipation (segment) {power dissipation per 1 segment X (d X g / c) X (1–Toff / Tdisp) } / a (5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 190 mW

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-down 135 Power Dissipation Calculating example 1 Fixed number depending on microcomputer’s standard

• VOH output fall voltage of high-breakdown port 2 V (max.); | Current value | = at 18 mA
• Resistor value 68 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V X 38 mA = 190 mW Fixed number depending on use condition
• Apply voltage to VEE pin: Vcc – 50 V
• Timing number 17; digit number 16; segment number 20
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: 31
• All segment number during repeat cycle: 340 (= 17 X 20)
• Total number of built-in resistor: for digit; 16, for segment; 20
• Digit pin current value: 18 (mA)
• Segment pin current value: 3 (mA) (1) Digit pin power dissipation {18 X 16 X (1–1/16) X 2} / 17 = 31.77 mW (2) Segment pin power dissipation {3 X 31 X (1–1/16) X 2} / 17 = 10.26 mW (3) Pull-down resistor power dissipation (digit) (50 – 2)2 /68 X (16 X 16/16) X (1 – 1/16) / 17 = 29.90 mW (4) Pull-down resistor power dissipation (segment) (50 – 2)2 /68 X (31 X 20/20) X (1 – 1/16) / 17 = 57.93 mW (5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 190.00 mW DIG0 DIG1 DIG2 DIG3 DIG13 DIG14 DIG15 Timing number 12 3 16 1715 14 Tscan Repeat cycle Figure S-1. Digit timing waveform (1)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-down 136 Power Dissipation Calculating example 2(when 2 or more digit is turned ON at same time) Fixed number depending on microcomputer’s standard

• VOH output fall voltage of high-breakdown port 2 V (max.); | Current value | = at 18 mA
• Resistor value 68 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V X 38 mA = 190 mW Fixed number depending on use condition
• Apply voltage to VEE pin: Vcc – 50 V
• Timing number 11; digit number 12; segment number 24
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: 114
• All segment number during repeat cycle: 264 (= 11 X 24)
• Total number of built-in resistor: for digit; 10, for segment; 22
• Digit pin current value: 18 (mA)
• Segment pin current value: 3 (mA) (1) Digit pin power dissipation {18 X 12 X (1–1 / 16) X 2} / 11 = 36.82 mW (2) Segment pin power dissipation {3 X 114 X (1–1 / 16) X 2} / 11 = 58.30 mW (3) Pull-down resistor power dissipation (digit) (50– 2)2 / 68 X (12 X 10 / 12) X (1 – 1 / 16) / 11 = 28.88 mW (4) Pull-down resistor power dissipation (segment) (50 – 2)2 / 68 X (114 X 22 / 24) X (1 – 1 / 16) / 11 = 301.77 mW (5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 190.00 mW (1) + (2)+ (3) + (4) + (5) = 615.77 mW (There is a limit of use temperature) DIG0 DIG1 DIG2 DIG3 DIG7 DIG8 DIG9 Timing number 12 3 45 6 7 89 1 0 1 1 DIG4 DIG5 DIG6 Tscan Repeat cycle Figure S-2. Digit timing waveform (2)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-down 137 Power Dissipation Calculating example 3 (when 2 or more digit is turned ON at same time, and used Toff invalid function) Fixed number depending on microcomputer’s standard

• VOH output fall voltage of high-breakdown port 2 V (max.); | Current value | = at 18 mA
• Resistor value 68 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V X 38 mA = 190 mW Fixed number depending on use condition
• Apply voltage to VEE pin: Vcc – 50 V
• Timing number 11; digit number 12; segment number 24
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: 114 ( for Toff invalid waveform;50)
• All segment number during repeat cycle: 264 (= 11 X 24)
• Total number of built-in resistor: for digit; 10, for segment; 22
• Digit pin current value: 18 (mA)
• Segment pin current value: 3 (mA) (1) Digit pin power dissipation [{18 X 10 X (1–1/16) X 2} + {18 X 2 X 2}] / 11 = 37.23 mW (2) Segment pin power dissipation [{3 X 64 X (1–1/16) X 2} + {3 X 50 X 2}] / 11 = 60.00 mW (3) Pull-down resistor power dissipation (digit) (4) Pull-down resistor power dissipation (segment) (5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 190.00 mW (1) + (2)+ (3) + (4) + (5) = 627.02 mW (There is a limit of use temperature) Figure S-3. Digit timing waveform (3) DIG0 DIG1 DIG2 DIG3 DIG7 DIG8 DIG9 Timing number 12 3 45 6 7 89 1 0 1 1 DIG4 DIG5 DIG6 Tscan Repeat cycle

Table Z-1. Absolute maximum ratings Operating ambient temperature Parameter Unit VREF, XIN Input voltageRESET , CNVss , Analog supply voltage Supply voltage Output voltageVO - 0.3 to Vcc+0.3 (Note) Pd Storage temperature - 0.3 to 6.5 Standard - 0.3 to 6.5 V V V Condition VI AVcc Vcc Tstg Topr Symbol V -40 to 150 -20 to 85 P44 to P47, P70 to P77, P80 to P87, P90 to P97, P100 to P107, 2.7(Note1) 5.5 Typ. Max. UnitParameter Vcc 5.0Supply voltage Symbol Min Standard Analog supply voltage VccAVcc V V 0 0Analog supply voltage Supply voltageVss AVss 0.8Vcc V V V V 0.52Vcc Vcc Vcc 0.16Vcc 0 HIGH input voltage LOW input voltage HIGH input voltage P30 to P37, P40 to P43 V P30 to P37, P40 to P43 P70 to P77, P80 to P87, P90 to P97, P100 to P107, XIN, RESET , CNV SS VIH VIH V IL Pull-down supply voltage Vcc - 50 to Vcc+0.3V VVEE VI P30 to P37, P40 to P43Input voltage Vcc - 50 to Vcc+0.3 V P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P43, P50 to P57, Output voltageVO P60 to P67 Vcc - 50 to Vcc+0.3 V VEE Pull-down supply voltage Vcc-48 Vcc V V IL LOW input voltage P70 to P77, P80 to P87, P90 to P97, P100 to P107, XIN, RESET , CNV SS 0 V0.2Vcc XOUT P44 to P47, P70 to P77, P80 to P87, P90 to P97, P100 to P107, -0.3 to Vcc+0.3 Power dissipation Ta=-20 to 60 750 750-12 X (Ta-60)Ta=60 to 85 mW mW VIH P44 to P47 0.50Vcc Vcc VHIGH input voltage V0.16Vcc 0LOW input voltage P44 to P47V IL C C C C Note 1: When writing to flash ,only CNVss is –0.3 to 13 (V) . Note: VCC = 4.0V to 5.5V in flash memory version. Table Z-2. Recommended operating conditions (referenced to VCC = 2.7V to 5.5V at Ta = – 20 to 85oC unless otherwise specified) (Note)

Table Z-3. Recommended operating conditions (referenced to VCC = 2.7V to 5.5V at Ta = – 20 to 85oC unless otherwise specified) (Note 6) Note 1: The total output current is the sum of all the currents through the applicable ports. The total average value measured over 100ms. The total peak current is the peak of all the currents. Note 2: The peak output current is the peak current flowing in each port. Note 3: The average output current in an average value measured over 100ms. Note 4: When the oscillating frequency has a duty cycle of 50 %. Note 5: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(X CIN) < f(XIN) / 3. Note 6: VCC =4.0V to 5.5V in flash memory version. Note 7: Relationship between main clock oscillation frequency and supply voltage. /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 10.0 3.5 0.0 2.7 4.0 5.5 Main clock input oscillation frequency (No wait) 5 X VCC -10.000MHZ Flash memory version Operating maximum frequency [MH Supply voltage[V](BCLK: no division) IOH (avg) mA mA IOH (peak) -18 -40 P00 to P07, P10 to P17, P20 to P27,P30 to P37, P40 to P43, P50 to P57, P60 to P67 f (XIN) MHz10 f (XcIN) kHz5032.768 Vcc=4.0V to 5.5V Vcc=2.7V to 4.0V MHz 0 5 X Vcc-10 Symbol Parameter UnitStandard Min Typ. Max. HIGH peak output current (Note 2) HIGH average output current (Note 3) Main clock input oscillation frequency (Note 4, 7) Sub clock oscillation frequency (Note 4, 5) 0 to P07, P50 to P57, P60 to P67 HIGH total peak output current (Note 1) IOH (peak) -240 mA P10 to P17, P20 to P27, P30 to P37, P40 to P43 HIGH total peak output current (Note 1) IOH (peak) -240 mA P44 to P47, P70 to P77, P80 to P85 HIGH total peak output current (Note 1) IOH (peak) -80 mA P86, P87, P90 to P97, P100 to P107 HIGH total peak output current (Note 1) IOH (peak) -80 mA P44 to P47, P70 to P77, P80 to P85 LOW total peak output current (Note 1) IOL (peak) 80 mA P86, P87, P90 to P97, P100 to P107 LOW total peak output current (Note 1) IOL (peak) 80 mA P00 to P07, P50 to P57, P60 to P67 HIGH total average output current (Note 1) IOH (avg) -120 mA P10 to P17, P20 to P27, P30 to P37, P40 to P43 HIGH total average output current (Note 1) IOH (avg) -120 mA P44 to P47, P70 to P77, P80 to P85 HIGH total average output current (Note 1) IOH (avg) -40 mA P86, P87, P90 to P97, P100 to P107 HIGH total average output current (Note 1) IOH (avg) -40 mA P44 to P47, P70 to P77, P80 to P85 LOW total average output current (Note 1) IOL (avg) 40 mA P86, P87, P90 to P97, P100 to P107 LOW total average output current (Note 1) IOL (avg) 40 mA mAIOH (peak) -10 P44 to P47, P70 to P77, P80 to P87HIGH peak output current (Note 2) P90 to P97, P100 to P107 mAIOL (peak) 10 P44 to P47, P70 to P77, P80 to P87LOW peak output current (Note 2) P90 to P97, P100 to P107 P00 to P07, P10 to P17, P20 to P27,P30 to P37, P40 to P43, P50 to P57, P60 to P67 IOH (avg) mA-5 HIGH average output current (Note 3) P44 to P47, P70 to P77, P80 to P87 P90 to P97, P100 to P107 IOL (avg) mA5 LOW average output current (Note 3) P44 to P47, P70 to P77, P80 to P87 P90 to P97, P100 to P107

VCC =5V 140 Table Z-4. Electrical characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25oC, f(XIN) =10MHZ unless otherwise specified) XIN, RESET, CNVss S y m b o l VO H VO H H I G H o u t p u t v o l t a g eVO H VO L L O W o u t p u t v o l t a g e LOW input currentIIL H I G H o u t p u t v o l t a g e H I G H o u t p u t v o l t a g e Standard T y p . U n i tM e a s u r i n g c o n d i t i o n V V VXO U T 3.0 3.0 V 2 . 0 µA Min. M a x 3.5 P a r a m e t e r IOH = - 18mA IOH = - 1mA IOH = - 5mA IOH = - 0.5mA IOL =5mA P 00 t o P 07, P 10 t o P 17, P 20 t o P 27, P 0 t o P 37, P 40 t o P 43, P 50 t o P 57, P 0 t o P 67 VI=0V - 5.0 H I G H P O W E R L O W P O W E R L O W o u t p u t v o l t a g e VO L H y s t e r e s i s Hysteresis H I G H i n p u t c u r r e n tII H VT -VT VT+-VT- VXO U T 2 . 0 2 . 0 0.2 0.8 V 0.2 1.8 V 5 . 0 µA IOL =1mA IOL =0.5mA RESET P 44 t o P 47, P 70 t o P 77, P 80 t o P 87, VI=5V H I G H P O W E R L O W P O W E R P 44 t o P 47, P 70 t o P 77, P 80 t o P 87, P 0 t o P 97, P 1 00 t o P 1 07 P44 to P47,P70 to P77,P80 to P87, P44 to P47,P70 to P77,P80 to P87, P 0 t o P 97, P 1 00 t o P 1 07 T A 0 I N t o T A 4I N , T B 0I N t o T B 2I N , CLK0,CLK1,SRDY2 IN,SBSY2 IN, I N T 0 t o I N T5, C T S0, C T S1, S I N 2 , S C L K 2 1 , S C L K 2 2 , R x D 0 , II H P30 to P37,P40 to P43(Note 1) VI=5V 5.0 µ A II L P30 to P37,P40 to P43(Note1) VI=0V - 5.0 µ A R P U L L U P Pull-up resistance P 44 t o P 47, P 70 t o P 77, P t o P 87, P t o P 97, P t o P P 90 t o P 97, P 1 00 t o P 1 07, XIN, RESET, CNVss P 0 t o P 97, P 1 00 t o P 1 07, IOH = - 5mA 4 . 5 30.0 50.0 167.0 kΩ 3.0 R x D 1 R f X I N F e e d b a c k r e s i s t a n c e X I N 1 . 0 R P U L L D P u l l - d o w n r e s i s t a n c e P 00 t o P 07, P 10 t o P 17, P t o P 57, P t o P VEE =V CC - 48V,VOL =VCC Output transistors “off” ILEAK O u t p u t l e a k c u r r e n t P00 to P07,P10 to P17, P20 to P27,P30 to P37, P40 to P44,P50 to P57, P60 to P67 VEE =V CC - 48V,VOL =VCC - 48V Output transistors “off” 68 80 120 kΩ - 1 0 µ A VI=0V VR A M R A M r e t e n t i o n v o l t a g e I c cP o w e r s u p p l y c u r r e n t ( N o t e 3 ) W h e n c l o c k i s s t o p p e d2 . 0 V Square wave, no division 1.0 µ A mA 2 0 . 0 1 9 . 03 8 . 0f(XIN)=10MHz f(XCIN)=32kHz 4.0 µA Square wave, 8 division f(XIN)=10MHz 4 . 2m A Square wave (Note2) f ( XC I N ) = 3 2 k H z 90.0 µ A M Ω R fXCIN Feedback resistance XCIN 6.0 M Ω The output pins are open and other pins are V SS Wh en a WAIT instruction is executed (Note2) Ta=85 when clock is stopped Ta=25 when clock is stopped C C Note 1: Except when reading ports P3, P40 to P43. Note 2: Fixed XCIN-XCOUT drive capacity select bit to “HIGH ” and XIN pin to “H ” level. Note 3: This contains an electric current to flow into AVCC pin.

VCC =5V 141 Table Z-5. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 5V, Vss = AVSS = 0V at Ta = 25oC, f(XIN) = 10MHZ unless otherwise specified) Table Z-6. D-A conversion characteristics (referenced to VCC = 5V, VSS = AVSS = 0V, VREF = 5V at Ta = 25oC, f(XIN) = 10MHZ unless otherwise specified) µs Standard Min. Typ. Max. Resolution Absolute accuracy Bits LSB VREF = VCC Symbol Parameter Measuring condition Unit V REF = VCC = 5V R LADDER tCONV Ladder resistance Conversion time(10bit) Reference voltage Analog input voltage kΩ V VIA VREF V 0 VCC VREF 3.3 Conversion time(8bit) 2.8tCONV tSAMP Sampling time 0.3 VREF = VCC Sample & hold function not available Sample & hold function available(10bit) AN 0 to AN7 inputV REF =VCC = 5V LSB Sample & hold function available(8bit)V REF = VCC = 5V ±2 LSB µs µs Min. Typ. Max. tsu R O Resolution Absolute accuracy Setup time Output resistance Reference power supply input current Bits kΩ mAIVREF 1.0 1.5 Symbol Parameter Measuring condition Unit 20 10 4 µs (Note) Standard Note: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to “0016”. The A-D converter's ladder resistance is not included. Also, when the Vref is unconnected at the A-D control register, IVREF is sent.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing (VCC =5V) VCC =5V 142 Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified) Table Z-7. External clock input Max. External clock rise time nstr Min. External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock fall time ns ns ns ns tc tw(H) tw(L) tf ParameterSymbol UnitStandard 100 Switching characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified) Table Z-8. High-breakdown voltage p-channel open-drain output port Symbol StandardMeasuring condition Max. Typ.Parameter Unit Min. tr(Pch-strg) P-channel high-breakdown voltage output rising time (Note 1) µs ns t r(Pch-weak) P-channel high-breakdown voltage output rising time (Note 2) 1.8 C L=100pF VEE =V CC - 43V C L=100pF VEE =V CC - 43V Note 1: When bit 7 of the FLDC mode register (address 035016) is at “0”. Note 2: When bit 7 of the FLDC mode register (address 035016) is at “1”. VEE P0, P1, P2, P3, P40 to P43, P5, P6 P-channel high- breakdown voltage output port (Note) Note: Ports P2, P3, and P40 to P43 need external resistors. C L Figure Z-2. Circuit for measuring output switching characteristics

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing (VCC =5V) VCC =5V 143 Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified) Table Z-9. Timer A input (counter input in event counter mode) Table Z-10. Timer A input (gating input in timer mode) Table Z-11. Timer A input (external trigger input in one-shot timer mode) Table Z-12. Timer A input (external trigger input in pulse width modulation mode) Table Z-13. Timer A input (up/down input in event counter mode) Standard Max. nsTAiIN input LOW pulse widthtw(TAL) Min. ns ns Unit Standard Max.Min. ns ns ns Unit Standard Max.Min. ns ns ns Unit Standard Max.Min. ns ns Unit Standard Max.Min. ns ns ns Unit ns ns TAiIN input HIGH pulse widthtw(TAH) Parameter Symbol TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width tc(TA) tw(TAH) tw(TAL) Symbol Parameter TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width tc(TA) tw(TAH) tw(TAL) Symbol Parameter tw(TAH) tw(TAL) Symbol Parameter TAiIN input HIGH pulse width TAiIN input LOW pulse width Symbol Parameter tc(TA) TAiIN input cycle time TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) 100 400 200 200 200 100 100 100 100 2000 1000 1000 400 400

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing (VCC =5V) VCC =5V 144 Table Z-15. Timer B input (pulse period measurement mode) Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified) Table Z-14. Timer B input (counter input in event counter mode) ns ns ns ns ns ns ns Standard Max. Min. TBi IN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) ns ns ns tc(TB) tw(TBH) tw(TBL) ParameterSymbol Unit tc(TB) tw(TBL) tw(TBH) ns ns ns TBi IN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges) TBiIN input cycle time (counted on both edges) Standard Max.Min. ns ns tc(TB) tw(TBH) Symbol Parameter Unit tw(TBL) ns TBiIN input HIGH pulse width TBiIN input cycle time TBiIN input LOW pulse width Standard Max.Min. ns ns tc(TB) Symbol Parameter Unit tw(TBL) ns tw(TBH) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Standard Max.Min. ns ns tw(INH) tw(INL) Symbol Parameter Unit INTi input LOW pulse width INTi input HIGH pulse width Standard Max. Min. CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width tc(CK) tw(CKH) tw(CKL) Parameter Symbol Unit td(C-Q) tsu(D-C) th(C-Q) TxDi hold time RxDi input setup time TxDi output delay time th(C-D) RxDi input hold time 100 200 400 200 200 400 200 200 250 250 200 100 100 µs ns ns ns Standard Max. Min. Serial I/O clock input cycle time Serial I/O clock input HIGH pulse width Serial I/O clock input LOW pulse width tc(SCLK) twH(SCLK) twL(SCLK) Parameter Symbol Unit tsu(SCLK-SIN) Serial I/O input setup time th(SCLK-SIN) Serial I/O input hold time 0.95 400 200 200 ns400 Table Z-16. Timer B input (pulse width measurement mode) Table Z-17. Serial I/O Table Z-18. External interrupt INTi inputs Table Z-19. Automatic transfer serial I/O

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing (VCC =5V) VCC =5V 145 tsu(D-C) TAiIN input TAiOUT input During event counter mode TBiIN input CLK i TxD i RxD i tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) INTi input td(C-Q) th(C-D) th(C-Q) th(TIN-UP) tsu(UP-TIN) TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) TAiOUT input (Up/down input) SOUT SIN SCLK 0.2VCC td(SCLK-SOUT) 0.2VCC 0.8VCC 0.8VCC tSU(SiN-SCLK) th(SCLK-SiN) tV(SCLK-SOUT) tWL(SCLK) tWH(SCLK)tf(SCLK) tC(SCLK) tr

VCC =3V 146 Table Z-20. Electrical characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25oC, f(XIN) =5MHZ unless otherwise specified) XIN, RESET, CNVss S y m b o l VO H VO H H I G H o u t p u t v o l t a g eVO H VO L L O W o u t p u t v o l t a g e LOW input currentII L H I G H o u t p u t v o l t a g e H I G H o u t p u t v o l t a g e Standard T y p . U n i tM e a s u r i n g c o n d i t i o n V V VXO U T 2.5 2 . 5 V0.5 µA Min. Max. 1 . 5 P a r a m e t e r IO H = - 1 8 m A IOH = - 0.1mA IOH = - 1mA IOH = - 50µA IOL =1mA P 00 t o P 07, P 10 t o P 17, P 20 t o P 27, P 0 t o P 37, P 40 t o P 43, P 50 t o P 57, P 0 t o P 67 VI=0V - 4 . 0 HIGH POWER L O W P O W E R L O W o u t p u t v o l t a g e VO L H y s t e r e s i s Hysteresis H I G H i n p u t c u r r e n tIIH VT -VT VT+-VT- VXO U T 0.5 0.5 0.2 0.8 V 0.2 1.8 V 4.0 µA IOL =0.1mA IOL =50µA R E S E T P 44 t o P 47, P 70 t o P 77, P 80 t o P 87, VI=3V HIGH POWER LOW POWER P 44 t o P 47, P 70 t o P 77, P 80 t o P 87, P 0 t o P 97, P 1 00 t o P 1 07 P44 to P47,P70 to P77,P80 to P87, P 4 t o P 47, P 70 t o P 77, P 80 t o P 87, P90 to P97,P100 to P107 T A 0 I N t o T A 4I N , T B 0I N t o T B 2I N , C L K 0, C L K1, S R D Y 2I N , S B S Y 2I N , I N T 0 t o I N T5, C T S0, C T S1, SIN2,SCLK21,SCLK22 IIH P 30 t o P 37, P 40 t o P 43( N o t e 1 ) VI=3V 4 . 0 µA II L P 30 t o P 37, P 40 t o P 43( N o t e 1 ) VI=0V - 4 . 0 µA R PULLUP P u l l - u p r e s i s t a n c e P44 to P47,P70 to P77, P80 to P87,P90 to P97, P100 to P107 P 90 t o P 97, P 1 00 t o P 1 07, XIN, RESET, CNVss P90 to P97,P100 to P107, IO H = - 5 m A 2 . 5 6 6 . 0 120.0 5 0 0 . 0 kΩ 2.5 R T S 0 , R T S 1 R f X I N F e e d b a c k r e s i s t a n c e X I N 3 . 0 R P U L L D P u l l - d o w n r e s i s t a n c e P 00 t o P 07, P 10 t o P 17, P t o P 57, P t o P VE E= VC C - 4 8 V , VO L= VC C Output transistors “off” IL E A K O u t p u t l e a k c u r r e n t P 00 t o P 07, P 10 t o P 17, P t o P 27, P t o P 37, P t o P 44, P t o P 57, P t o P VEE =V CC - 48V,VOL =VCC - 48V Output transistors “off” 6 88 01 2 0 kΩ - 10 µA VI=0V VRAM RAM retention voltage Icc Power supply current (Note 3) When clock is stopped 2.0 V Square wave, no division 1.0 µ A mA 2 0 . 0 The output pins are open and other pins are V SS 6 . 01 5 . 0f(XIN)=5MHz f(XCIN)=32kHz 2 . 8 µ A Square wave, 8 division f ( XI N ) = 5 M H z 1.6 mA f(XCIN)=32kHz 0.9 µA M Ω R f X C I N F e e d b a c k r e s i s t a n c e XC I N 1 0 . 0 M Ω Square wave f ( XC I N ) = 3 2 k H z 50.0 µA Ta=85 when clock is stopped Ta=25 when clock is stopped C C W h e n a W A I T i n s t r u c t i o n i s e x e c u t e d O s c i l l a t i o n c a p a c i t y H i g h N o t e W h e n a W A I T i n s t r u c t i o n i s e x e c u t e d O s c i l l a t i o n c a p a c i t y L o w N o t e Note 1: Except when reading ports P3, P40 to P43. Note 2: With one timer operated using fC32 . Note 3: This contains an electric current to flow into AVCC pin.

VCC =3V 147 Table Z-21. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 3V, Vss = AVSS = 0V at Ta = 25oC, f(XIN) = 5MHZ unless otherwise specified) Table Z-22. D-A conversion characteristics (referenced to VCC = 3V, VSS = AVSS = 0V, VREF = 3V at Ta = 25oC, f(XIN) = 5MHZ unless otherwise specified) R LADDER Ladder resistance Reference voltage Analog input voltage V VIA VREF V 0 2.7 VCC VREF Conversion time(8bit) 14.0tCONV VREF = VCC Standard Min. Typ. Max Resolution Absolute accuracy Bits LSB VREF = VCC Symbol Parameter Measuring condition Unit VREF = VCC = 3V, φAD = f(XIN)/2Sample & hold function not available (8 bit) kΩ µs Standard Min. Typ. Max tsu R O Resolution Absolute accuracy Setup time Output resistance Reference power supply input current Bits mAIVREF 1.0 1.0 Symbol Parameter Measuring condition Unit 20 10 4 (Note) kΩ µs Note: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to “0016”. The A-D converter's ladder resistance is not included. Also, when the Vref is unconnected at the A-D control register, IVREF is sent.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing(VCC =3V, only mask ROM version) VCC =3V 148 Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified) Table Z-23. External clock input ns ns ns ns ns tc tw(H) tw(L) tr tf Max.Min.Parameter Symbol UnitStandard External clock rise time External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock fall time 200

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing(VCC =3V, only mask ROM version) VCC =3V 149 Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified) Table Z-24. Timer A input (counter input in event counter mode) Table Z-25. Timer A input (gating input in timer mode) Table Z-26. Timer A input (external trigger input in one-shot timer mode) Table Z-27. Timer A input (external trigger input in pulse width modulation mode) Table Z-28. Timer A input (up/down input in event counter mode) Standard Max.Min. UnitParameter Symbol nstw(TAL) TAiIN input LOW pulse width 60 nstc(TA) TAiIN input cycle time 150 nstw(TAH) TAiIN input HIGH pulse width 60 Standard Max. Min.UnitParameter Symbol nstc(TA) TAiIN input cycle time 600 nstw(TAH) TAiIN input HIGH pulse width 300 nstw(TAL) TAiIN input LOW pulse width 300 Standard Max.Min. UnitParameter Symbol nstc(TA) TAiIN input cycle time 300 nstw(TAH) TAiIN input HIGH pulse width 150 nstw(TAL) TAiIN input LOW pulse width 150 Standard Max.Min. UnitParameter Symbol nstw(TAH) TAiIN input HIGH pulse width 150 nstw(TAL) TAiIN input LOW pulse width 150 Standard Max.Min. UnitParameter Symbol nstc(UP) TAiOUT input cycle time 3000 nstw(UPH) TAiOUT input HIGH pulse width 1500 nstw(UPL) TAiOUT input LOW pulse width 1500 nstsu(UP-TIN) TAiOUT input setup time 600 nsth(TIN-UP) TAiOUT input hold time 600

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing(VCC =3V, only mask ROM version) VCC =3V 150 Table Z-30. Timer B input (pulse period measurement mode) Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified) Table Z-29. Timer B input (counter input in event counter mode) Table Z-31. Timer B input (pulse width measurement mode) Table Z-32. Serial I/O Table Z-33. External interrupt INTi inputs Table Z-34. Automatic transfer serial I/O Standard Max. Min.ParameterSymbol Unit nstc(TB) TBiIN input cycle time (counted on one edge) 150 nstw(TBH) TBiIN input HIGH pulse width (counted on one edge) 60 nstw(TBL) TBiIN input LOW pulse width (counted on one edge) 60 tw(TBH) nsTBiIN input HIGH pulse width (counted on both edges) 160 tw(TBL) nsTBiIN input LOW pulse width (counted on both edges) 160 tc(TB) nsTBiIN input cycle time (counted on both edges) 300 Standard Max.Min. ParameterSymbol Unit nstc(TB) TBiIN input cycle time 600 nstw(TBH) TBiIN input HIGH pulse width 300 tw(TBL) nsTBiIN input LOW pulse width 300 Standard Max.Min.ParameterSymbol Unit nstc(TB) TBiIN input cycle time 600 nstw(TBH) TBiIN input HIGH pulse width 300 tw(TBL) nsTBiIN input LOW pulse width 300 Standard Max.Min. Parameter Symbol Unit nstw(INH) INTi input HIGH pulse width 380 nstw(INL) INTi input LOW pulse width 380 Standard Max.Min. Parameter Symbol Unit nstc(CK) CLKi input cycle time 300 nstw(CKH) CLKi input HIGH pulse width 150 nstw(CKL) CLKi input LOW pulse width 150 th(C-Q) nsTxDi hold time 0 tsu(D-C) nsRxDi input setup time 50 th(C-D) nsRxDi input hold time 90 td(C-Q) nsTxDi output delay time 160 µs ns ns ns Standard Max. Min. Serial I/O clock input cycle time Serial I/O clock input HIGH pulse width Serial I/O clock input LOW pulse width tc(SCLK) twH(SCLK) twL(SCLK) ParameterSymbol Unit tsu(SCLK-SIN) Serial I/O input setup time th(SCLK-SIN) Serial I/O input hold time 2.0 ns 1000 1000 400 400

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing(VCC =3V, only mask ROM version) VCC =3V 151 tsu(D-C) TAiIN input TAiOUT input During event counter mode TBiIN input CLK i TxD i RxD i tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) INTi input td(C-Q) th(C-D) th(C-Q) th(TIN-UP) tsu(UP-TIN) TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) TAiOUT input (Up/down input) SOUT SIN SCLK 0.2VCC td(SCLK-SOUT) 0.2VCC 0.8VCC 0.8VCC tSU(SiN-SCLK) th(SCLK-SiN) tV(SCLK-SOUT) tWL(SCLK) tWH(SCLK)tf(SCLK) tC(SCLK) tr

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 152 Item Power supply voltage Program/erase voltage Flash memory operation mode Erase block division Program method Erase method Program/erase control method Number of commands Program/erase count ROM code protect Performance 4.0V to 5.5 V (f(XIN)=10MHz) VPP =12V ± 5% (f(XIN)=10MHz) Three modes (parallel I/O, standard serial I/O, CPU rewrite) See Figure 1.AA.3. One division (3.5 K bytes) (Note) In units of byte Collective erase / block erase Program/erase control by software command 6 commands 100 times Standard serial I/O mode is supported. Note: The boot ROM area contains a standard serial I/O mode control program which is stored in it when shipped from the factory. This area can be erased and programmed in only parallel I/O mode. User ROM area Boot ROM area VCC =5V ± 10% (f(XIN)=10MHz) Table AA-1. Outline Performance of the M30218 group (flash memory version) Outline Performance Table AA-1 shows the outline performance of the M30218 group (flash memory version).

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 153 Flash Memory The M30218 group (flash memory version) contains the NOR type of flash memory that requires a high- voltage VPP power supply for program/erase operations, in addition to the VCC power supply for device operation. For this flash memory, three flash memory modes are available in which to read, program, and erase: parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a programmer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Pro- cessing Unit (CPU). Each mode is detailed in the pages to follow. In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user’s application system. This boot ROM area can be rewritten in only parallel I/O mode. Figure AA-3. Block diagram of flash memory version SFR RAM SFR RAM SFR RAM User ROM area 0000016 0040016 YYYYY 16 DF000 16 XXXXX 16 FFFFF 16 Microcomputer mode Parallel I/O mode CPU rewrite mode Standard serial I/O mode Boot ROM area (3.5K bytes) User ROM area User ROM area Boot ROM area (3.5K bytes)DFDFF E000016 E800016 F000016 F800016 FFFFF 16 Block 0 Block 1 Block 2 Block 3 Type No. XXXXX 16 YYYYY 16 M30218FC E0000 16 033FF 16 Collective erasable/ programmable area Collective erasable/ programmable area Collective erasable/ programmable area Note 1: In CPU rewrite and standard serial I/O modes, the user ROM is the only erasable/programmable area. Note 2: In parallel I/O mode, the area to be erased/programmed can be selected by the address A17 input. The user ROM area is selected when this address input is high and the boot ROM area is selected when this address input is low.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 154 CPU Rewrite Mode In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). In CPU rewrite mode, the flash memory can be operated on by reading or writing to the flash memory control register and flash command register. Figure BB-1, Figure BB- 2 show the flash memory control register, and flash command register respectively. Also, in CPU rewrite mode, the CNV SS pin is used as the VPP power supply pin. Apply the power supply voltage, VPP H, from an external source to this pin. In CPU rewrite mode, only the user ROM area shown in Figure AA-3 can be rewritten; the boot ROM area cannot be rewritten. Make sure the program and block commands are issued for only the user ROM area. The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to internal RAM before it can be executed. Flash memory control register 0 Symbol Address When reset FCON0 03B4 16 001000002 W R b7 b6 b5 b4 b3 b2 b1 b0 CPU rewrite mode select bit FCON00 Bit symbol Bit name Function RW 0: CPU rewrite mode is invalid 1: CPU rewrite mode is valid This bit can not write. The value, if read, turns out to be indeterminate. Reserved bit CPU rewrite mode monitor flag 0: CPU rewrite mode is invalid 1: CPU rewrite mode is valid Must always be set to "0". FCON02 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines Reserved bit 000: Block 3 program/erase 001: Block 2 program/erase 010: Block 1 program/erase 011: Block 0 program/erase 110: Block 0 to 3 erase 111: Inhibit /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLinesMust always be set to "0".Reserved bit Flash memory control register 1 Symbol Address When reset FCON1 03B5 16 XXXXXX00 2 W R b7 b6 b5 b4 b3 b2 b1 b0 Bit symbol Bit name Function RW /LiteDiagLines/LiteDiagLines Reserved bit /LiteDiagLines Nothing is assigned. In an attempt to write these bits, write "0". The value, if read, turns out to be indeterminate. Must always be set to "0". /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines FCON04 FCON05 FCON06 b6b5b4 Erase / program area select bit Flash command register Symbol Address When reset FCMD 03B6 16 0016 W R b7 b6 b5 b4 b3 b2 b1 b0 Writing of software command <Software command name> <Command code>

• Read command "00 16"
• Program command "40 16"
• Program verify command "C0 16"
• Erase command "20 16" +"2016"
• Erase verify command "A0 16"
• Reset command "FF 16"+"FF6" Function RW /LiteDiagLines Figure BB-1. Flash memory control register Figure BB-2. Flash command register

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 155 Microcomputer Mode and Boot Mode The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard serial I/O mode becomes unusable.) See Figure AA-3 for details about the boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNV SS pin low (VSS ). In this case, the CPU starts operating using the control program in the user ROM area. When the microcomputer is reset by pulling the P52 pin high (VCC ), the CNVSS pin high(VPPH ), the CPU starts operating using the control program in the boot ROM area. This mode is called the “boot” mode. The control program in the boot ROM area can also be used to rewrite the user ROM area. CPU rewrite mode operation procedure The internal flash memory can be operated on to program, read, verify, or erase it while being placed on- board by writing commands from the CPU to the flash memory control register (addresses 03B4 16, 03B516) and flash command register (address 03B616). Note that when in CPU rewrite mode, the boot ROM area cannot be accessed for program, read, verify, or erase operations. Before this can be accom- plished, a CPU write control program must be written into the boot ROM area in parallel input/output mode. The following shows a CPU rewrite mode operation procedure. <Start procedure (Note 1)> (1) Apply VPP H to the CNVSS /VPP pin and VCC to the port P46 pin for reset release. Or the user can jump from the user ROM area to the boot ROM area using the JMP instruction and execute the CPU write control program. In this case, set the CPU write mode select bit of the flash memory control register to “1” before applying V PP H to the CNVSS /VPP pin. (2) After transferring the CPU write control program from the boot ROM area to the internal RAM, jump to this control program in RAM. (The operations described below are controlled by this program.) (3) Set the CPU rewrite mode select bit to “1”. (4) Read the CPU rewrite mode monitor flag to see that the CPU rewrite mode is enabled. (5) Execute operation on the flash memory by writing software commands to the flash command regis- ter. Note 1: In addition to the above, various other operations need to be performed, such as for entering the data to be written to flash memory from an external source (e.g., serial I/O), initializing the ports, and writing to the watchdog timer. <Clearing procedure> (1) Apply VSS to the CNVSS /VPP pin. (2) Set the CPU rewrite mode select bit to “0”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 156 Precautions on CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During erase/program mode, set BCLK to one of the following frequencies by changing the divide ratio:

5 MHz or less when wait bit (bit 7 at address 0005

16) = 0 (without internal access wait state)

10 MHz or less when wait bit (bit 7 at address 000516) = 1 (with internal access wait state)(Note 1)

(2) Instructions inhibited against use The instructions listed below cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction (3) Interrupts inhibited against use No interrupts can be used that look up the fixed vector table in the flash memory area. Maskable interrupts may be used by setting the interrupt vector table in a location outside the flash memory area. Note 1: Internal access wait state can be set in CPU rewrite mode. In this time, the following function is only used.

• CPU, ROM, RAM, timer, UART, SI/O2(non-automatic transfer), port In case of setting internal access wait state, refer to the following explain (software wait). Software wait A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 0005 16) (Note 2). A software wait is inserted in the internal ROM/RAM area by setting the wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK cycle. When set to “1”, each bus cycle is executed in two BCLK cycles. After the microcomputer has been reset, this bit defaults to “0”. The SFR area is always accessed in two BCLK cycles regardless of the setting of this control bit. Table DA-1 shows the software wait and bus cycles. Figure DA-6 shows example bus timing when using software waits. Note 2: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect register (address 000A 16) to “1”. Area Wait bit Bus cycle 1 2 BCLK cycles SFR Internal ROM/RAM 0 1 BCLK cycle Invalid 2 BCLK cycles Table DA-1. Software waits and bus cycles

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 157 Figure DA-6. Typical bus timings using software wait Output Input Address Address Bus cycle < Internal bus (with wait) > BCLK Read signal Write signal Data bus Address bus BCLK Read signal Write signal Address bus Address Address Bus cycle < Internal bus (no wait) > OutputData bus Input

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 158 Command Program verify Read Program 03B616 First bus cycle Second bus cycle 0016 4016 C0 16 Write Write Write Program address Write Read Erase verify A016Write Verify address Verify data Read Erase 2016Write 03B616 2016Write Verify address Reset FF16Write Mode Address Mode Address Data (D0 to D7) Data (D0 to D7) 03B616 03B616 03B616 03B616 03B616 Program data Verify data FF16Write 03B616 Software Commands Table BB-1 lists the software commands available with the M30218 group (flash memory version). When CPU rewrite mode is enabled, write software commands to the flash command register to specify the operation to erase or program. The content of each software command is explained below. Table BB-1. List of Software Commands (CPU Rewrite Mode) Read Command (00 16) The read mode is entered by writing the command code “0016” to the flash command register in the first bus cycle. When an address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data bus (D 0–D 7), 8 bits at a time. The read mode is retained intact until another command is written. After reset and after the reset command is executed, the read mode is set. Program Command (40 16) The program mode is entered by writing the command code “4016” to the flash command register in the first bus cycle. When the user execute an instruction to write byte data to the desired address (e.g., STE instruction) in the second bus cycle, the flash memory control circuit executes the program op- eration. The program operation requires approximately 20 µs. Wait for 20 µs or more before the user go to the next processing. During program operation, the watchdog timer remains idle, with the value “7FFF 16” set in it. Note 1: The write operation is not completed immediately by writing a program command once. The user must always execute a program-verify command after each program command executed. And if verification fails, the user need to execute the program command repeatedly until the verification passes. See Figure BB.3 for an example of a programming flowchart.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 159 Program-verify command (C016) The program-verify mode is entered by writing the command code “C0 16” to the flash command register in the first bus cycle. When the user execute an instruction (e.g., LDE instruction) to read byte data from the address to be verified (the previously programmed address) in the second bus cycle, the content that has actually been written to the address is read out from the memory. The CPU compares this read data with the data that it previously wrote to the address using the program command. If the compared data do not match, the user need to execute the program and program-verify operations one more time. Erase command (20 16 + 2016) The flash memory control circuit executes an erase operation by writing command code “2016” to the flash command register in the first bus cycle and the same command code to the flash command register again in the second bus cycle. The erase operation requires approximately 20 ms. Wait for 20 ms or more before the user go to the next processing. Before this erase command can be performed, all memory locations to be erased must have had data “00 16” written to by using the program and program-verify commands. During erase operation, the watchdog timer remains idle, with the value “7FFF 16 set in it. Note 1: The erase operation is not completed immediately by writing an erase command once. The user must always execute an erase-verify command after each erase command executed. And if verification fails, the user need to execute the erase command repeatedly until the verification passes. See Figure BB-3 for an example of an erase flowchart. Erase-verify command (A0 16) The erase-verify mode is entered by writing the command code “A016” to the flash command register in the first bus cycle. When the user execute an instruction to read byte data from the address to be verified (e.g., LDE instruction) in the second bus cycle, the content of the address is read out. The CPU must sequentially erase-verify memory contents one address at a time, over the entire area erased. If any address is encountered whose content is not “FF 16” (not erased), the CPU must stop erase-verify at that point and execute erase and erase-verify operations one more time. Note 1: If any unerased memory location is encountered during erase-verify operation, be sure to execute erase and erase-verify operations one more time. In this case, however, the user does not need to write data “00 16” to memory before erasing.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 160 Start Address = first location Loop counter : X=0 Write program command Write : 4016 Duration = 20 µs Duration = 6 µs X=25 ? Verify OK ? PASS FAIL FAIL PASS YES PASS NO NO FAIL Write program data/ address Loop counter : X=X+1 Write program verify command Last address ?Next address ? Write read command Write read command Verify OK ? Write : Program data Write : C016 Write : 0016 Write:2016 Duration = 6µs X=1000 ? Verify OK? PASS FAIL FAIL PASS YES PASS NO NO FAIL Duration = 20ms YES NO Start All bytes = "0016"? Program all bytes = "0016" Address = First address Loop counter X=0 Write erase command Write erase command Loop counter X=X+1 Write erase verify command/address Verify OK? Last address?Next address Write read command Write read command Write:2016 Write:A016 Write:0016 Read: expect value=FF16 Figure BB-3. Program and erase execution flowchart in the CPU rewrite mode Program Erase Reset command (FF16 + FF16) The reset command is used to stop the program command or the erase command in the middle of operation. After writing command code “4016” or “2016” twice to the flash command register, write command code “FF16” to the flash command register in the first bus cycle and the same command code to the flash command register again in the second bus cycle. The program command or erase command is disabled, with the flash memory placed in read mode.

Appendix Standard Serial I/O Mode Mitsubishi microcomputers M30218 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 161 Pin Description VCC ,VSS Apply 5V ± 10 % to Vcc pin and 0 V to Vss pin. CNV SS Apply 12V ± 5 % to this pin. RESET Reset input pin. While reset is "L" level, a 20 cycle or longer clock must be input to XIN pin. XIN Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin.XOUT AV CC , AVSS VREF Connect AVSS to Vss and AVcc to Vcc, respectively. Enter the reference voltage for AD from this pin. P00 to P07 Output exclusive use pin. P10 to P17 Output exclusive use pin. P20 to P27 Output exclusive use pin. P30 to P37 Input "H" or "L" level signal or open. P40 to P43 Input "H" or "L" level signal or open. P44 Serial data output pin. P45 P46 Serial clock input pin. P47 P50 to P57 Output exclusive use pin. Name Power input CNV SS Reset input Clock input Clock output Analog power supply input Reference voltage input Output port P0 Output port P1 Output port P2 Input port P3 Input port P4 TxD output SCLK input BUSY output Output port P5 I/O I I I O I O O O I I I I O O RxD input Serial data input pin. O BUSY signal output pin. P60 to P67 Output exclusive use pin. P70 to P77 Input "H" or "L" level signal or open. Output port P6 Input port P7 O I P80 to P87 Input "H" or "L" level signal or open.Input port P8 I P90 to P97 Input "H" or "L" level signal or open.Input port P9 I P100 to P107 Input "H" or "L" level signal or open.Input port P10 I Pin functions (Flash memory standard serial I/O mode)

Appendix Standard Serial I/O Mode Mitsubishi microcomputers M30218 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 162 Figure DD-1. Pin connections for serial I/O mode (1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 515253545556575859606162636465666768697071727374757677787980 100 M30218FCFP P60/FLD0 P61/FLD1 P62/FLD2 P63/FLD3 P64/FLD4 P65/FLD5 P66/FLD6 P67/FLD7 0/FLD8 V CCX IN RESET X OUTV SS CNV SS 6/X COUT 7/X CIN 0/SRDY2 6/TA3 IN /TA1 OUT /CLK1 7/TA4 IN /TA2 OUT /CTS1/RTS1/CLKS1 4/S OUT 5/SCLK21 6/DA1/SCLK22 7/DA0/CLK OUT /DIM OUT 2/SSTB2P9 3/S IN2 3/TA0 IN /TA3 OUT 2/TB2 IN 1/SBUSY2 VEE P107/AN7 P106/AN6 P105/AN5 P103/AN3 P102/AN2 P104/AN4 P101/AN1 AV SS P100/AN0 VREF AV CC 1/FLD9 2/FLD10 3/FLD11 4/FLD12 5/FLD13 6/FLD14 7/FLD15 0/FLD16 1/FLD17 2/FLD18 3/FLD19 4/FLD20 5/FLD21 6/FLD22 V SS 7/FLD23 V CC 0/FLD24 1/FLD25 2/FLD26 3/FLD27 4/FLD28 5/FLD29 6/FLD30 7/FLD31 0/FLD32 1/FLD33 2/FLD34 3/FLD35 P24/FLD36 P25/FLD37 P26/FLD38 P27/FLD39 P30/FLD40 P31/FLD41 P32/FLD42 P33/FLD43 P34/FLD44 P35/FLD45 P36/FLD46 P37/FLD47 P40/FLD48 P41/FLD49 P42/FLD50 P43/FLD51 P44/TXD0/FLD52 P45/RXD0/FLD53 P46/CLK0/FLD54 P47/CTS0/RTS0/FLD55 5/TA2 IN /TA0 OUT XD1 4/TA1 IN /TA4 OUT XD1 1/TB1 IN 0/TB0 IN 5/INT5 4/INT4 3/INT3 2/INT2 1/INT1 0/INT0 Vss Vcc CNVss VssVcc CNVss VppH RESET TxD SCLK RxD BUSY RESET Vss Vcc Mode setup method Signal Value VSS VCC Connect oscillator circuit.

Appendix Standard Serial I/O Mode Mitsubishi microcomputers M30218 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 163 Standard Serial I/O Mode The standard serial I/O mode serially inputs and outputs the software commands, addresses and data necessary for operating (read, program, erase, etc.) the internal flash memory. It uses a purpose-specific serial programmer. The standard serial I/O mode differs from the parallel I/O mode in that the CPU controls operations like rewriting (uses the CPU rewrite mode) in the flash memory or serial input for rewriting data. The standard serial I/O mode is started by clearing the reset with V PPH at the CNVss pin. (For the normal microprocessor mode, set CNVss to “L”.) This control program is written in the boot ROM area when shipped from Mitsubishi Electric. Therefore, if the boot ROM area is rewritten in the parallel I/O mode, the standard serial I/O mode cannot be used. Figures DD-1 shows the pin connections for the standard serial I/O mode. Serial data I/O uses three UART0 pins: CLK 0, RxD0, TxD0, and RTS0 (BUSY). The CLK0 pin is the transfer clock input pin and it transfers the external transfer clock. The TxD0 pin outputs the CMOS signal. The RTS0 (BUSY) pin outputs an “L” level when reception setup ends and an “H ” level when the reception operation starts. Transmission and reception data is transferred serially in 8-byte blocks. In the standard serial I/O mode, only the user ROM area shown in Figure AA-3 can be rewritten, the boot ROM area cannot. The standard serial I/O mode has a 7-byte ID code. When the flash memory is not blank and the ID code does not match the content of the flash memory, the command sent from the programmer is not accepted. Function Overview (Standard Serial I/O Mode) In the standard serial I/O mode, software commands, addresses and data are input and output between the flash memory and an external device (serial programmer, etc.) using a clock synchronized serial I/O (UART0) . In reception, the software commands, addresses and program data are synchronized with the rise of the transfer clock input to the CLK 0 pin and input into the flash memory via the RxD0 pin. In transmission, the read data and status are synchronized with the fall of the transfer clock and output to the outside from the TxD 0 pin. The TxD0 pin is CMOS output. Transmission is in 8-bit blocks and LSB first. When busy, either during transmission or reception, or while executing an erase operation or program, the RTS 0 (BUSY) pin is “H ” level. Accordingly, do not start the next transmission until the RTS0 (BUSY) pin is “L” level. Also, data in memory and the status register can be read after inputting a software command. It is pos- sible to check flash memory operating status or whether a program or erase operation ended success- fully or in error by reading the status register. Software commands and the status register are explained here following.

Appendix Standard Serial I/O Mode Mitsubishi microcomputers M30218 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 164 Software Commands Table DD-1 lists software commands. In the standard serial I/O mode, erase operations, programs and reading are controlled by transferring software commands via the RxD pin. Software commands are explained here below. Table DD-1. Software commands (Standard serial I/O mode) Control command 2nd byte 3rd byte 4th byte 5th byte 6th byte

1 Page read

2 Page program

3 Bclock ease

4 Erase all unlocked blocks

5 Read status register

6 Clear status register

7 Read lockbit status

8 ID check function

9 Download function

10 Version data output function

11 Boot area output function

Note1: Shading indicates transfer from flash memory microcomputer to serial programmer. All other data is transferred from the serial programmer to the flash memory microcomputer. Note2: SRD refers to status register data. SRD1 refers to status register 1 data. Note3: All commands can be accepted when the flash memory is totally blank. When ID is not verificate Not acceptable Not acceptable Not acceptable Not acceptable Acceptable Not acceptable Not acceptable Acceptable Not acceptable Acceptable Not acceptable Version data output to 9th byte Data output to 259th byte Data output to 259th byte Data input to 259th byte To ID7 Data output Data input ID1 To required number of times Version data output Data output Data output Data input ID size Data input Version data output Data output Data output Data input D0 16 Lock bit data output Address (high) Check- sum Version data output Data output Address (high) Address (high) Address (high) SRD1 output Address (high) Address (middle) Size (high) Version data output Address (high) Address (middle) Address (middle) Address (middle) D0 16 SRD output Address (middle) Address (low) Size (low) Version data output Address (middle) FF 16 4116 2016 A7 16 7016 5016 7116 F516 FA 16 FB 16 FC 16 1st byte transfer

Appendix Standard Serial I/O Mode Mitsubishi microcomputers M30218 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 165 Page Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Send the “FF16” command code in the 1st byte of the transmission. (2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respec- tively. (3) From the 4th byte onward, data (D0–D 7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first in sync with the rise of the clock. data0 data255 CLK0 RxD0 TxD0 RTS0(BUSY) A8 to A15 A16 to A23FF16 SRD output SRD1 output CLK0 RxD0 TxD0 RTS0(BUSY) 7016 Figure DD-2. Timing for page read Read Status Register Command This command reads status information. When the “7016” command code is sent in the 1st byte of the transmission, the contents of the status register (SRD) specified in the 2nd byte of the transmission and the contents of status register 1 (SRD1) specified in the 3rd byte of the transmission are read. Figure DD-3. Timing for reading the status register

Appendix Standard Serial I/O Mode Mitsubishi microcomputers M30218 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 166 Figure DD-4. Timing for clearing the status register Page Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Send the “4116” command code in the 1st byte of the transmission. (2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respectively. (3) From the 4th byte onward, as write data (D0–D 7) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is automatically written. When reception setup for the next 256 bytes ends, the RTS0 (BUSY) signal changes from the “H ” to the “L” level. The result of the page program can be known by reading the status register. For more information, see the section on the status register. CLK0 RxD0 TxD0 RTS0(BUSY) 5016 Clear Status Register Command This command clears the bits (SR3–SR4) which are set when the status register operation ends in error. When the “5016” command code is sent in the 1st byte of the transmission, the aforementioned bits are cleared. When the clear status register operation ends, the RTS0 (BUSY) signal changes from the “H ” to the “L” level. CLK0 RxD0 TxD0 RTS0(BUSY) A8 to A15 A16 to A234116 data0 data255 Figure DD-5. Timing for the page program

Appendix Standard Serial I/O Mode Mitsubishi microcomputers M30218 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 167 Block Erase Command This command erases the data in the specified block. Execute the block erase command as explained here following. (1) Send the “2016” command code in the 1st byte of the transmission. (2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respec- tively. (3) Send the verify command code “D0 16” in the 4th byte of the transmission. With the verify com- mand code, the erase operation will start for the specified block in the flash memory. Write the highest address of the specified block for addresses A 16 to A23. When block erasing ends, the RTS0 (BUSY) signal changes from the “H ” to the “L” level. After block erase ends, the result of the block erase operation can be known by reading the status register. For more information, see the section on the status register. Each block can be erase-protected with the lock bit. For more information, see the section on the data protection function. Figure DD-6.Timing for block erasing A8 to A15 A16 to A232016 D0 16 CLK0 RxD0 TxD0 RTS0(BUSY)

Appendix Standard Serial I/O Mode Mitsubishi microcomputers M30218 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 168 Read Lock Bit Status Command This command reads the lock bit status of the specified block. Execute the read lock bit status com- mand as explained here following. (1) Send the “7116” command code in the 1st byte of the transmission. (2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respec- tively. (3) The lock bit data of the specified block is output in the 4th byte of the transmission. Write the highest address of the specified block for addresses A8 to A23. The M30218 group (flash memory version) does not have the lock bit, so the read value is always “1” (block unlock). CLK0 RxD0 TxD0 RTS0(BUSY) A8 to A15 A16 to A237116 DQ6 Figure DD-8. Timing for reading lock bit status Erase All Unlocked Blocks Command This command erases the content of all blocks. Execute the erase all unlocked blocks command as explained here following. (1) Send the “A716” command code in the 1st byte of the transmission. (2) Send the verify command code “D0 16” in the 2nd byte of the transmission. With the verify com- mand code, the erase operation will start and continue for all blocks in the flash memory. When block erasing ends, the RTS 0 (BUSY) signal changes from the “H ” to the “L” level. The result of the erase operation can be known by reading the status register. CLK0 RxD0 TxD0 RTS0(BUSY) A716 D0 16 Figure DD-7. Timing for erasing all unlocked blocks

Appendix Standard Serial I/O Mode Mitsubishi microcomputers M30218 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 169 Download Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Send the “FA 16” command code in the 1st byte of the transmission. (2) Send the program size in the 2nd and 3rd bytes of the transmission. (3) Send the check sum in the 4th byte of the transmission. The check sum is added to all data sent in the 5th byte onward. (4) The program to execute is sent in the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM. FA 16 Program data Program data Data size (high) Data size (low) Check sum CLK0 RxD0 TxD0 RTS0(BUSY) Figure DD-9. Timing for download

Appendix Standard Serial I/O Mode Mitsubishi microcomputers M30218 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 170 Version Information Output Command This command outputs the version information of the control program stored in the boot area. Execute the version information output command as explained here following. (1) Send the “FB 16” command code in the 1st byte of the transmission. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters. Figure DD-10. Timing for version information output Boot Area Output Command This command outputs the control program stored in the boot area in one page blocks (256 bytes). Execute the boot area output command as explained here following. (1) Send the “FC 16” command code in the 1st byte of the transmission. (2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respec- tively. (3) From the 4th byte onward, data (D0–D 7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first, in sync with the rise of the clock. FB 16 'X''V' 'E' 'R' CLK0 RxD0 TxD0 RTS0(BUSY) data0 data255 CLK0 RxD0 TxD0 RTS0(BUSY) A8 to A15 A16 to A23FC 16 Figure DD-11. Timing for boot area output

Appendix Standard Serial I/O Mode Mitsubishi microcomputers M30218 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 171 ID Check This command checks the ID code. Execute the boot ID check command as explained here following. (1) Send the “F516” command code in the 1st byte of the transmission. (2) Send addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code in the 2nd, 3rd and 4th bytes of the transmission respectively. (3) Send the number of data sets of the ID code in the 5th byte. (4) The ID code is sent in the 6th byte onward, starting with the 1st byte of the code. ID size ID1 ID7 CLK0 RxD0 TxD0 RTS0(BUSY) F516 DF 16 FF16 0F16 Figure DD-12. Timing for the ID check ID Code When the flash memory is not blank, the ID code sent from the serial programmer and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the com- mand sent from the serial programmer is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses 0FFFDF 16, 0FFFE316, 0FFFEB 16, 0FFFEF 16, 0FFFF316, and 0FFFF7 16 . Write a program into the flash memory, which already has the ID code set for these addresses. Reset vector Watchdog timer vector Single step vector Address match vector BRK instruction vector Overflow vector Undefined instruction vector ID7 ID6 ID5 ID4 ID3 ID2 ID1 DBC vector 0FFFFF 16 to 0FFFFC16 0FFFFB 16 to 0FFFF816 0FFFF7 16 to 0FFFF416 0FFFF3 16 to 0FFFF016 0FFFEF 16 to 0FFFEC16 0FFFEB 16 to 0FFFE816 0FFFE7 16 to 0FFFE416 0FFFE3 16 to 0FFFE016 0FFFDF 16 to 0FFFDC16 4 bytes Address Figure DD-13. ID code storage addresses

Appendix Standard Serial I/O Mode Mitsubishi microcomputers M30218 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 172 Status Register (SRD) The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read status register command (70 16). Also, the status register is cleared by writing the clear status register command (5016). Table DD-2 gives the definition of each status register bit. After clearing the reset, the status register outputs “80 16”. Table DD-2. Status register (SRD) Status Bit (SR7) The status bit indicates the operating status of the flash memory. When power is turned on, “1” (ready) is set for it. The bit is set to “0” (busy) during an auto write or auto erase operation, but it is set back to “1” when the operation ends. Erase Bit (SR5) The erase bit reports the operating status of the auto erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is set to “0”. Program Bit (SR4) The program bit reports the operating status of the auto write operation. If a write error occurs, it is set to “1”. When the program status is cleared, it is set to “0”. SRD0 bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Status name Status bit Reserved Erase bit Program bit Reserved Reserved Reserved Reserved Definition "1" "0" Ready Terminated in error Terminated in error Busy Terminated normally Terminated normally

Appendix Standard Serial I/O Mode Mitsubishi microcomputers M30218 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 173 Status Register 1 (SRD1) Status register 1 indicates the status of serial communications, results from ID checks and results from check sum comparisons. It can be read after the SRD by writing the read status register command (7016). Also, status register 1 is cleared by writing the clear status register command (5016). Table DD-3 gives the definition of each status register 1 bit. “0016” is output when power is turned ON and the flag status is maintained even after the reset. Table DD-3. Status register 1 (SRD1) Boot Update Completed Bit (SR15) This flag indicates whether the control program was downloaded to the RAM or not, using the down- load function. Check Sum Consistency Bit (SR12) This flag indicates whether the check sum matches or not when a program, is downloaded for execu- tion using the download function. ID Check Completed Bits (SR11 and SR10) These flags indicate the result of ID checks. Some commands cannot be accepted without an ID check. Data Reception Time Out (SR9) This flag indicates when a time out error is generated during data reception. If this flag is attached during data reception, the received data is discarded and the microcomputer returns to the command wait state. SRD1 bits SR15 (bit7) SR14 (bit6) SR13 (bit5) SR12 (bit4) SR11 (bit3) SR10 (bit2) SR9 (bit1) SR8 (bit0) Status name Boot update completed bit Reserved Reserved Checksum match bit ID check completed bits Data receive time out Reserved Definition "1" "0" Update completed Match Not update Mismatch Normal operation Not verified Verification mismatch Reserved Verified Time out

Appendix Standard Serial I/O Mode Mitsubishi microcomputers M30218 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 174 Example Circuit Application for The Standard Serial I/O Mode The below figure shows a circuit application for the standard serial I/O mode. Control pins will vary ac- cording to programmer, therefore see the programmer manual for more information. RTS0(BUSY) CLK0 R XD0 TXD0 CNVss Clock input RTS output Data input Data output M30218 Flash memory version (1) Control pins and external circuitry will vary according to programmer. For more information, see the programmer manual. (2) In this example, the microprocessor mode and standard serial I/O mode are switched via a switch. VPP Figure DD-14. Example circuit application for the standard serial I/O mode

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 175 QFP100-P-1420-0.65 1.58 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Alloy 42 100P6S-A Plastic 100pin 14✕ 20mm body QFP 0.1 0.2 – – Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.35 – –I2 1.3 – –M D 14.6 – –M E 20.6 10°0° 0.1 1.4 0.8 0.6 0.4 23.1 22.8 22.5 17.1 16.8 16.5 0.65 20.2 20.0 19.8 14.2 14.0 13.8 0.2 0.15 0.13 0.4 0.3 0.25 2.8 3.05 e e e E c H E H D D M D M E A F A1 A2 L y Recommended Mount Pad Detail F 100 x – – 0.13 b x M MMP

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M30218 Group Data Sheet REV.B Feb. First Edition 2001 Editioned by Committee of editing of Mitsubishi Semiconductor Published by Mitsubishi Electric Corp., Kitaitami Works This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. ©2001 MITSUBISHI ELECTRIC CORPORATION