M14D128168A

Elite Semiconductor Mem...

Internal pipelined double-data-rate architecture; two data access per clock cycle

Manufacturer: Elite Semiconductor Mem...

Document: 59 Pages / 786Kb

Request Quote Download Datasheet Read online HTML view

More from Elite Semiconductor Mem... Browse M parts

Online Datasheet

Read M14D128168A online.

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 59

Technical content

Features

 JEDEC Standard  VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V  Internal pipelined double-data-rate architecture; two data access per clock cycle  Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.  On-chip DLL  Differential clock inputs (CLK and CLK )  DLL aligns DQ and DQS transition with CLK transition  1KB page size - Row address: A0 to A11 - Column address: A0 to A8  Quad bank operation  CAS Latency : 3, 4, 5, 6, 7  Additive Latency: 0, 1, 2, 3, 4, 5  Burst Type : Sequential and Interleave  Burst Length : 4, 8  All inputs except data & DM are sampled at the rising edge of the system clock(CLK)  Data I/O transitions on both edges of data strobe (DQS)  DQS is edge-aligned with data for READ; center-aligned with data for WRITE  Data mask (DM) for write masking only  On-Die-Termination for better signal quality  Special function support - 50/ 75/ 150 ohm ODT - High Temperature Self refresh rate enable - DCC (Duty Cycle Corrector)  Auto & Self refresh  Refresh cycle : - 4096 cycles/64ms (15.6 μ s refresh interval) at -40 ℃ ≦ TC ≦ + 85 ℃ - 4096 cycles/32ms (7.8 μ s refresh interval) at +85 ℃ ＜ TC ≦ +95 ℃  SSTL_18 interface

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 2/59 Ordering Information: Product ID Max Freq. VDD Data Rate (CL-tRCD-tRP) Package Comments M14D128168A - 1.8BIG2M 533MHz 1.8V DDR2-1066 (7-7-7) M14D128168A - 2.5BIG2M 400MHz 1.8V DDR2-800 (5-5-5) 84 ball FBGA (Window BGA) A (max) = 1.2mm M14D128168A - 1.8BVIG2M 533MHz 1.8V DDR2-1066 (7-7-7) M14D128168A - 2.5BVIG2M 400MHz 1.8V DDR2-800 (5-5-5) 84 ball VFBGA A (max) = 1.2mm M14D128168A - 1.8BBIG2M 533MHz 1.8V DDR2-1066 (7-7-7) M14D128168A - 2.5BBIG2M 400MHz 1.8V DDR2-800 (5-5-5) 84 ball FBGA (Window BGA) A (max) = 1.0mm M14D128168A - 1.8BBVIG2M 533MHz 1.8V DDR2-1066 (7-7-7) M14D128168A - 2.5BBVIG2M 400MHz 1.8V DDR2-800 (5-5-5) 84 ball VFBGA A (max) = 1.0mm Pb-free Functional Block Diagram

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 3/59 Ball Configuration (Top View) (FBGA / VFBGA 84, 8mmX12.5mmX1.2mm Body, 0.8mm Ball Pitch) (FBGA / VFBGA 84, 8mmX12.5mmX1.0mm Body, 0.8mm Ball Pitch) VDD DQ14 DQ12 DQ6 A B C D E F G H J K L M N P R NC VSSQ VDDQ VSSQ VSSQ DQ1 CKE BA0 A10 VSS UDM DQ11 VDDQ DQ15 DQ13 VSSQ DQ10 LDQS DQ2 UDQS VSSQ VDDQ VSSQ CLK 123 789 A12 DQ4 NC DQ9 VDD VDDQ VDDL VSS VDD NC VSSQ VREF VDDQ VSS LDM VDDQ BA1 NC DQ3 VSS WE UDQS DQ8 V DDQ RAS CAS A11 NC CS NC CLK VSSQ LDQS VDDQ DQ7 DQ5 VDD VDDQ VDD VSS VDDQDQ0 VSSQ VSSDL ODT VSSQ Note: A12 (ball R2) is used for MRS/EMRS.

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 4/59 Ball Description Pin Name Function Pin Name Function A0~A12, BA0,BA1 Address inputs - Row address A0~A11 - Column address A0~A8 A12: use for MRS/EMRS A10/AP : Auto Precharge BA0, BA1 : Bank selects (4 Banks) DM (LDM, UDM) DM is an input mask signal for write data. LDM is DM for DQ0~DQ7 and UDM is DM for DQ8~DQ15. DQ0~DQ15 Data-in/Data-out CLK, CLK Differential clock input RAS Command input CKE Clock enable CAS Command input CS Chip select WE Command input V DDQ Supply Voltage for DQ VSS Ground V SSQ Ground for DQ VDD Power V REF Reference Voltage DQS, DQS (LDQS, LDQS UDQS, UDQS ) Bi-directional differential Data Strobe. LDQS and /LDQS are DQS for DQ0~DQ7; UDQS and /UDQS are DQS for DQ8~DQ15. V DDL Supply Voltage for DLL ODT On-Die-Termination. ODT is only applied to DQ0~DQ15, DM, DQS and /DQS. V SSDL Ground for DLL NC No connection Absolute Maximum Rating Parameter Symbol Value Unit Voltage on any pin relative to VSS V IN, VOUT -0.5 ~ 2.3 V Voltage on VDD supply relative to VSS V DD -1.0 ~ 2.3 V Voltage on VDDL supply relative to VSS V DDL -0.5 ~ 2.3 V Voltage on VDDQ supply relative to VSS V DDQ -0.5 ~ 2.3 V Storage temperature T STG -55 ~ +100 C° ( Note *) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions abov e those indicated in the operational sections of this spec ification is not impli ed. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Note *: Storage Temperature is the case surface temperature on the center/top side of the DRAM.

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 5/59 Operation Temperature Condition Parameter Symbol Value Unit Operation temperature T C -40 ~ +95 C° Note: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. 2. Supporting -40 to +85 ℃ with full AC and DC specifications. Supporting -40 to + 85 ℃ and being able to extend to + 95 ℃ with doubling auto-refresh commands in frequency to a 3 2 m s p e r i o d ( tREFI = 7.9μ s ) and higher temperature Self-Refresh entry via A7 “1” on EMRS(2). DC Operation Condition & Specifications DC Operation Condition (Recommended DC operating conditions) Parameter Symbol Min. Typ. Max. Unit Note Supply voltage V DD 1.7 1.8 1.9 V 4,7 Supply voltage for DLL V DDL 1.7 1.8 1.9 V 4,7 Supply voltage for output V DDQ 1.7 1.8 1.9 V 4,7 Input reference voltage V REF 0.49 x V DDQ 0.5 x VDDQ 0.51 x V DDQ V 1,2,7 Termination voltage (system) V TT V REF - 0.04 V REF V REF + 0.04 V 3,7 Input logic high voltage V IH (DC) V REF + 0.125 - V DDQ + 0.3 V Input logic low voltage V IL (DC) -0.3 - V REF - 0.125 V (All voltages referenced to VSS) Parameter Symbol Value Unit Note Output minimum source DC current ( VDDQ(min); VOUT =1.42V ) I OH -13.4 mA 5,6 Output minimum sink DC current ( V DDQ(min); V OUT = 0.28V ) I OL +13.4 mA 5,6 Note: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of V REF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). 3. VTT of transmitting device must track VREF of receiving device. 4. VDDQ and VDDL track VDD. AC parameters are measured with VDD, VDDQ and VDDL tied together. 5. The DC value of V REF applied to the receiving device is expected to be set to VTT. 6 . TC = 25℃, VDD = VDDQ = 1.8V. 7. There is no specific device V DD supply voltage requirement for SSTL_18 compliance. However, under all conditions V DDQ must be less than or equal to VDD.

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 6/59 DC Specifications (IDD values are for the operation range of Voltage and Temperature) Version Parameter Symbol Test Condition -1.8 -2.5 Unit Operating Current (Active - Precharge) IDD0 One bank; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS (IDD)min; CKE is High, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING 85 75 mA Operating Current (Active - Read - Precharge) IDD1 One bank; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; t CK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS (IDD)min, tRCD = tRCD (IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W 100 95 mA Precharge Power-Down Standby Current IDD2P All banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING 12 12 mA Precharge Quiet Standby Current IDD2Q All banks idle; tCK = tCK (IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING 55 50 mA Idle Standby Current IDD2N All banks idle; tCK = tCK (IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING 55 50 mA Fast PDN Exit MRS(12) = 0 45 40 Active Power-down Standby Current IDD3P All banks open; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus input are FLOATING Slow PDN Exit MRS(12) = 1 18 18 mA Active Standby Current IDD3N All banks open; tCK = tCK (IDD), tRAS = tRAS (IDD)max, tRP = tRP (IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING 80 70 mA Operation Current (Read) IDD4R All banks open, continuous burst Reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; t CK = tCK (IDD), tRAS = tRAS (IDD)max, tRP = tRP (IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is the same as IDD4W; 210 170 mA Operation Current (Write) IDD4W All banks open, continuous burst Writes; BL = 4, CL = CL (IDD), AL = 0; t CK = tCK (IDD), tRAS = tRAS (IDD)max, tRP = tRP (IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING 200 160 mA

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 7/59 Version Parameter Symbol Test Condition -1.8 -2.5 Unit Burst Refresh Current IDD5 tCK = tCK (IDD); Refresh command every tRFC (IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING 100 95 mA Self Refresh Current IDD6 Self Refresh Mode; CLK and CLK at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING 4 4 mA Operating Current (Bank interleaving) IDD7 All bank interleaving Reads, IOUT = 0mA; BL = 4, CL= CL (IDD), AL = tRCD (IDD) – 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = 1 × tCK (IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during Deslects; Data pattern is the same as IDD4W; 220 180 mA Note: 1. IDD specifications are tested after the device is properly initialized. 2. Input slew rate is sp ecified by AC Input Test Condition. 3. IDD parameters ar e specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS and /DQS, IDD va lues must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD: L O W i s d e f i n e d a s V IN  VIL (AC) (max.). HIGH is defined as VIN  V IH (AC) (min.). STABLE is defined as i nputs stable at a HIGH or LOW level. FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: Address and control signal Inputs are chan ged between HIGH and LOW every other clock cycle (once per two clocks), and DQ (not including mask or strobe) signal inputs are changed between HIGH and LOW every other data transfer (once per clock). 6 . W h e n T C ≧ + 85 ℃, IDD6 must be derated by 80%. IDD6 will increase by this amount if T C ≧ + 85 ℃ and double refresh option is still enabled. 7. AC Timing for IDD test conditions For purposes of IDD testing, the following parameters are to be utilized. -1.8 -2.5 Parameter DDR2-1066 Unit CL (IDD) 7 5 t CK tRCD (IDD) 13.125 12.5 ns tRC (IDD) 53.125 57.5 ns tRRD (IDD)-1KB 7.5 7.5 ns tFAW (IDD)-1KB 35 35 ns tCK (IDD) 1.875 2.5 ns tRAS (IDD) min. 40 45 ns tRAS (IDD) max. 70000 ns tRP (IDD) 13.125 12.5 ns tRFC (IDD) 75 75 ns

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 8/59 AC Operation Conditions & Timing Specification AC Operation Conditions -1.8 -2.5 Parameter Symbol Min. Max. Min. Max. Unit Note Input High (Logic 1) Voltage V IH(AC) V REF + 0.2 V REF + 0.2 V Input Low (Logic 0) Voltage V IL(AC) V REF - 0.2 V REF - 0.2 V Input Differential Voltage V ID(AC) 0.5 V DDQ + 0.6 0.5 V DDQ V 1 Input Crossing Point Voltage V IX(AC) 0.5 x VDDQ - 0.175 0.5 x VDDQ + 0.175 0.5 x VDDQ - 0.175 0.5 x VDDQ + 0.175 V 2 Output Crossing Point Voltage V OX(AC) 0.5 x VDDQ - 0.125 0.5 x VDDQ + 0.125 0.5 x VDDQ - 0.125 0.5 x VDDQ + 0.125 V 2 Note: 1. VID(AC) specifies the input differential voltage |VTR – VCP| required for switching, where VTR is the true input signal (such as CLK,DQS) and V CP is the complementary input signal (such as CLK , DQS ). The minimum value is equal to VIH(AC) – V IL(AC). 2. The typical value of V IX / VOX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VIX / VOX(AC) is expected to track variations in VDDQ. VIX / VOX(AC) indicates the voltage at which differential input / output signals must cross. Input / Output Capacitance Parameter Symbol Min. Max. Unit Note Input capacitance (A0~A12, BA0~BA1, CKE, CS ,RAS , CAS , WE , ODT) CIN1 0.5 1.5 pF 1 Input capacitance (CLK, CLK ) CIN2 0.5 1.0 pF 1 DQS, DQS & Data input/output capacitance CI / O 1.5 3.5 pF 2 Input capacitance (DM) CIN3 0.5 1.5 pF 2 Note: 1. Maximum capacitance delta is 0.25 pF. 2. Maximum capacitance delta is 0.5 pF.

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 9/59 AC Overshoot / Undershoot Specification Value Parameter Pin -1.8 -2.5 Unit Maximum peak amplitude allowed for overshoot Address, CKE, CS ,RAS , CAS , WE , ODT, CLK, CLK , DQ, DQS, DQS , DM 0.5 V Maximum peak amplitude allowed for undershoot Address, CKE, CS ,RAS , CAS , WE , ODT, CLK, CLK , DQ, DQS, DQS , DM 0.5 V Address, CKE, CS ,RAS , CAS , WE , ODT, 0.5 0.66 V-nsMaximum overshoot area above VDD CLK, CLK , DQ, DQS, DQS , DM 0.19 0.23 V-ns Address, CKE, CS ,RAS , CAS , WE , ODT, 0.5 0.66 V-nsMaximum undershoot area below VSS CLK, CLK , DQ, DQS, DQS , DM 0.19 0.23 V-ns

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 10/59 AC Operating Test Conditions Parameter Value Unit Note Input reference voltage ( VREF ) 0.5 x V DDQ V 1 Input signal maximum peak swing ( VSWING(max.) ) 1.0 V 1 Input signal minimum slew rate (SLEW) 1.0 V/ns 2,3 Input level V IH / VIL V Input timing measurement reference level V REF V Output timing measurement reference level (VOTR) 0.5 x V DDQ V 4 Note: 1. Input waveform timing is referenced to the input signal crossing through the VIH / VIL (AC) level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from V REF to VIH (AC) (min.) for rising edges and the range from VREF to VIL (AC)(max.) for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from V IL (AC) to VIH (AC) on the positive transitions and VIH (AC) to VIL (AC) on the negative transitions. 4. The V DDQ of the device under test is reference.

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 11/59 AC Timing Parameter & Specifications -1.8 -2.5 Parameter Symbol Min. Max. Min. Max. Unit Note CL=7 1875 7500 - - CL=6 2500 7500 - - CL=5 3000 7500 2500 8000 Clock period CL=4 tCK (avg) 3750 7500 3750 8000 ps 12 DQ output access time from CLK/ CLK tAC -350 +350 -400 +400 ps 9 CLK high-level width t CH (avg) 0.48 0.52 0.48 0.52 tCK (avg) 12 CLK low-level width t CL (avg) 0.48 0.52 0.48 0.52 tCK (avg) 12 DQS output access time from CLK/ CLK tDQSCK -325 +325 -350 +350 ps 9 Clock to first rising edge of DQS delay t DQSS -0.25 +0.25 -0.25 +0.25 tCK (avg) Data-in and DM setup time (to DQS) tDS (base) 0 50 ps 3 Data-in and DM hold time (to DQS) tDH (base) 75 125 ps 4 DQ and DM input pulse width (for each input) tDIPW 0.35 0.35 tCK (avg) Address and Control Input setup time t IS (base) 125 175 ps 3 Address and Control Input hold time t IH (base) 200 250 ps 4 Control and Address input pulse width t IPW 0.6 0.6 tCK (avg) DQS input high pulse width t DQSH 0.35 0.35 tCK (avg) DQS input low pulse width t DQSL 0.35 0.35 tCK (avg) DQS falling edge to CLK rising setup time tDSS 0.2 0.2 tCK (avg) DQS falling edge from CLK rising hold time tDSH 0.2 0.2 tCK (avg) Data strobe edge to output data edge t DQSQ 175 200 ps Data-out high-impedance window from CLK/ CLK tHZ t AC(max.) t AC(max.) ps 9 Data-out low-impedance window from CLK/ CLK tLZ (DQS) tAC(min.) t AC(max.) t AC(min.) t AC(max.) ps 9 DQ low-impedance window from CLK/ CLK tLZ (DQ) 2 x tAC(min.) t AC(max.) 2 x t AC(min.) t AC(max.) ps 9 Half clock period t HP Min (tCL, tCH) Min (t CL, tCH) ps 5, 12 DQ/DQS output hold time from DQS t QH tHP-tQHS t HP-tQHS ps DQ hold skew factor t QHS 250 300 ps

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 12/59 AC Timing Parameter & Specifications - Continued -1.8 -2.5 Parameter Symbol Min. Max. Min. Max. Unit Note Active to Precharge command t RAS 40 70K 45 70K ns Active to Active command (same bank) tRC 53.125 57.5 ns Auto Refresh row cycle time t RFC 75 75 ns Active to Read, Write delay t RCD 13.125 12.5 ns Precharge command period t RP 13.125 12.5 ns Active bank A to Active bank B command (1KB page size) tRRD 7.5 7.5 ns Four activate window (1KB page size) t FAW 35 35 ns Write recovery time t WR 15 15 ns Write data in to Read command delay t WTR 7.5 7.5 ns Col. address to Col. address delay t CCD 2 2 t CK Average periodic Refresh interval ( -40℃ ≦ TC ≦ + 85℃ ) tREFI 15.6 15.6 μ s Average periodic Refresh interval Write preamble t WPRE 0.35 0.35 t CK (avg) Write postamble t WPST 0.4 0.6 0.4 0.6 t CK (avg) DQS Read preamble t RPRE 0.9 1.1 0.9 1.1 t CK (avg) 10 DQS Read postamble t RPST 0.4 0.6 0.4 0.6 t CK (avg) 11 Load Mode Register / Extended Mode Register cycle time tMRD 2 2 t CK Auto Precharge write recovery + Precharge time tDAL WR + tnRP WR + tn RP t CK 18 Internal Read to Precharge command delay tRTP 7.5 7.5 ns Exit Self Refresh to Read command t XSRD 200 200 t CK Exit Self Refresh to non-Read command tXSNR tRFC + 10 t RFC + 10 ns Exit Precharge Power-Down to any non-Read command tXP 3 2 t CK Exit Active Power-Down to Read command tXARD 3 2 t CK 2 Exit active power-down to Read command (slow exit / low power mode) tXARDS 10 - AL 8 - AL t CK 1,2 CKE minimum pulse width (high and low pulse width) tCKE 3 3 t CK Minimum time clocks remains ON after CKE asynchronously drops low tDELAY tIS + tCK(avg)+tIH tIS + tCK(avg)+tIH ns

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 13/59 AC Timing Parameter & Specifications - Continued -1.8 -2.5 Parameter Symbol Min. Max. Min. Max. Unit Note Output impedance test driver delay t OIT 0 12 0 12 ns MRS command to ODT update delay t MOD 0 12 0 12 ns ODT turn-on delay t AOND 2 2 2 2 tCK ODT turn-on t AON tAC(min.) tAC(max.) +2.575 tAC(min.) t AC(max.) +0.7 ns 13,15 ODT turn-on (Power-Down mode) t AONPD tAC(min.) + 2 3 x tCK (avg) +tAC(max.) + 1 tAC(min.) + 2 2 x tCK (avg) +tAC(max.) + 1 ns ODT turn-off delay t AOFD 2.5 2.5 2.5 2.5 tCK 14, 16,17 ODT turn-off (Power-Down mode) t AOFPD tAC(min.) + 2 2.5 x tCK (avg) +tAC(max.) + 1 tAC(min.) + 2 2.5 x tCK (avg) +tAC(max.) + 1 ns ODT to Power-Down entry latency t ANPD 4 3 tCK ODT Power-Down exit latency t AXPD 11 8 tCK Note: 1. AL: Additive Latency. 2. MRS A12 bit defines which Active Power-Down Exit timing to be applied. 3. The figures of Input Waveform Timing 1 and 2 are re ferenced from the input signal crossing at the V IH (AC) level for a rising signal and VIL (AC) for a falling signal applied to the device under test. 4. The figures of Input Waveform Timing 1 and 2 are re ferenced from the input signal crossing at the VIL (DC) level for a rising signal and VIH (DC) for a falling signal applied to the device under test. 5. t HP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; t HP = Min ( tCH (abs), tCL (abs) ), where: t CH (abs) is the minimum of the actual instantaneous clock HIGH time; t CL (abs) is the minimum of the actual instantaneous clock LOW time; 6. t QHS accounts for: a. The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and b. The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and p-channel to n-channel variation of the output drivers. 7. t QH = tHP - tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 14/59 column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples: a. If the system provides t HP of 1200 ps into a DDR2-800 SDRAM, the DRAM provides tQH of 900 ps minimum. b. If the system provides t HP of 1300 ps into a DDR2-800 SDRAM, the DRAM provides tQH of 1000 ps minimum. 8. RU stands for round up. WR refers to the t WR parameter stored in the MRS. 9. When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual tERR (6-10per) of the input clock. (output de-ratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-800 SDRAM has tERR (6-10per)(min.) = - 272 ps and tERR (6-10per)(max.) = + 293 ps, then tDQSCK (min.)(derated) = tDQSCK (min.) - tERR (6-10per)(max.) = -350 ps - 293 ps = -643 ps and tDQSCK (max.) (derated) = tDQSCK (max.) - tERR (6-10per)(min.) = 350 ps + 272 ps = +622 ps. Similarly, tLZ (DQ) for DDR2-800 de-rates to tLZ (DQ)(min.)(derated) = -800 ps - 293 ps = -1093 ps and tLZ (DQ)(max.)(derated) = 400 ps + 272 ps = +672 ps. 10. When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual tJIT (per) of the input clock. (output de-ratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-800 SDRAM has tJIT (per)(min.) = - 72 ps and tJIT (per)(max.) = + 93 ps, tRPRE (max.) + tJIT (per)(max.) = 1.1 x tCK (avg) + 93 ps = + 2843 ps. 11. When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual tJIT (duty) of the input clock. (output de-ratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-800 SDRAM has tJIT (duty)(min.) = - 72 ps and tJIT (duty)(max.) = + 93 ps, tRPST (max.) + tJIT (duty)(max.) = 0.6 x tCK (avg) + 93 ps = + 1593 ps. 12. Refer to the Clock Jitter table. 13. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from t AOND. 14. ODT turn off time min is when the dev ice starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from t AOFD. 15. When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual tERR (6-10per) of the input clock. (output de-ratings are relative to the SDRAM input clock.) 16. When the device is operated with input clock jitte r, this parameter needs to be derated by { - tJIT (duty)(max.) - tERR (6-10per)(max.) } and { - tJIT (duty)(min.) - tERR (6-10per)(min.) } of the actual input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-800 SDRAM has tERR (6-10per)(min.) = - 272 ps, tERR (6- 10per)(max.) = + tERR (6-10per)(max.) } = -400 ps + { - 94 ps - 293 ps} = -787 ps and tAOF(max.)(derated) = tAOF(max.) + { - tJIT (duty)(min.) - tERR (6-10per)(min.) } = 1000 ps + { 96 ps + 272 ps } = +1368 ps. 17. For t AOFD of DDR2-800/1066, the 1/2 clock of tCK in the 2.5 x tCK assumes a tCH (avg), average input clock HIGH pulse width of 0.5 relative to tCK (avg). tAOF (min.) and tAOF (max.) should each be derated by the same amount as the actual amount of tCH (avg) offset present at the DRAM input with respect to 0.5. For example, if an input clock has a worst case tCH (avg) of 0.48, the tAOF (min.) should be derated by subtracting 0.02 x tCK (avg) from it, whereas if an input clock has a worst case tCH (avg) of 0.52, the tAOF (max.) should be derated by adding 0.02 x tCK (avg) to it. Therefore, we have; or tCH (avg)(min.) and tCH (avg)(max.) are the minimum and maximum of tCH (avg) actually measured at the DRAM input balls. 18. t DAL [nCLK] = WR [nCLK] + tnRP [nCLK] = WR + RU {tRP [ps] / tCK (avg) [ps] }, where WR is the value programmed in the mode register set. 19. t DAL = WR + RU{ tRP[ns] / tCK [ns] }, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For DDR2-800 (5-5-5) at tCK =2.5ns with WR programmed to 6 clocks. tDAL = 6 + (12.5 ns / 2.5 ns) clocks = 6 + 5 clocks = 11 clocks.

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 15/59 Parameter Symbol Min. Typ. Max. Unit Rtt effective impedance value for 75Ω setting EMRS(1) [A6, A2] = 0, 1 Rtt1(eff) 60 75 90 Ω Rtt effective impedance value for 150Ω setting EMRS(1) [A6, A2) = 1, 0 Rtt2(eff) 120 150 180 Ω Rtt effective impedance value for 50Ω setting EMRS(1) [A6, A2] = 1, 1 Rtt3(eff) 40 50 60 Ω Deviation of VM with respect to VDDQ /2 △VM -6 - +6 % Note: Measurement Defini tion for Rtt(eff) : Rtt(eff) is determined by separately applying V IH(AC) and VIL(AC) to test pin, and then measuring current I(V IH(AC)) and I(VIL(AC)) respectively. Measurement Definition for △VM : Measure voltage (VM) at test pin with no load.

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 16/59 Clock Jitter [ DDR2- 1066, 800] Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec parameters' and these parameters apply to DDR2-1066 and DDR2-800 only. The jitter specified is a random jitter meeting a Gaussian distribution. Clock period jitter t JIT (per) -90 90 -100 100 ps 5 Clock period jitter during DLL locking period tJIT (per,lck) -80 80 -80 80 ps 5 Cycle to cycle period jitter t JIT (cc) -180 180 -200 200 ps 6 Cycle to cycle clock period jitter During DLL locking period tJIT (cc, lck) -160 160 -160 160 ps 6 Cumulative error across 2 cycles t ERR (2per) -132 132 -150 150 ps 7 Cumulative error across 3 cycles t ERR (3per) -157 157 -175 175 ps 7 Cumulative error across 4 cycles t ERR (4per) -175 175 -200 200 ps 7 Cumulative error across 5 cycles t ERR (5per) -188 188 -200 200 ps 7 Cumulative error across n=6,7,8,9,10 cycles tERR (6-10per) -250 250 -300 300 ps 7 Cumulative error across n=11,12,….49,50 cycles tERR (11-50per) -425 425 -450 450 ps 7 Duty cycle jitter t JIT (duty) -75 75 -100 100 ps 4 Note: 1. t CK (avg) is calculated as the average clock period across any consecutive 200 cycle window. 2. t CH (avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses. 3. t CL (avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses. 4. t JIT (duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from tCH (avg). tCL jitter is the largest deviation of any single tCL from tCL (avg). tJIT (duty) is not subject to production test. tJIT (duty) = Min./Max. of { tJIT (CH), tJIT (CL)}, where: tJIT (CH) = { tCH j - tCH (avg) where j =1 to 200} tJIT (CL) = {tCL j - tCL (avg) where j =1 to 200} 5. t JIT (per) is defined as the largest deviation of any single tCK from tCK (avg). tJIT (per) = Min./Max. of { tCK j - tCK (avg) where j =1 to 200} tJIT (per) defines the single period jitter when the DLL is already locked. tJIT (per, lck) uses the same definition for single period jitter, during the DLL locking period only. tJIT (per) and tJIT (per, lck) are not subject to production testing.

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 17/59 6. t JIT (cc) is defined as the difference in clock period between two consecutive clock cycles : tJIT (cc) = Max. of | tCK i +1 - tCK i| tJIT (cc) defines the cycle to cycle jitter when the DLL is already locked. tJIT (cc, lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only. tJIT (cc) and tJIT (cc, lck) are not subject to production testing. 7. t ERR (nper) is defined as the cumulative error across multiple consecutive cycles from tCK (avg). tERR (nper) is not subject to production testing. 8. These parameters are specifie d per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. (Min. and max. of SPEC values are to be used for calculations in the table below.) Parameter Symbol Min. Max. Unit Absolute clock period t CK (abs) t CK (avg)(min.) + tJIT (per)(min.) t CK (avg)(max.) + tJIT (per)(max.) ps Absolute clock high pulse width tCH (abs) tCH (avg)(min.) x tCK (avg)(min.) + tJIT (duty)(min.) tCH (avg)(max.) x tCK (avg)(max.) + tJIT (duty)(max.) ps Absolute clock low pulse width tCL (abs) tCL (avg)(min.) x tCK (avg)(min.) + tJIT (duty)(min.) tCL (avg)(max.) x tCK (avg)(max.) + tJIT (duty)(max.) ps Example: For DDR2-800, tCH (abs)(min.) = (0.48 x 2500ps) – 100 ps = 1100 ps Input Slew Rate De-rating For all input signals the total tIS, tDS (setup time) and tIH, tDH (hold time) required is calculated by adding the data sheet tIS (base), tDS (base) and tIH (base), tDH (base) value to the ΔtIS, ΔtDS and ΔtIH, ΔtDH de-rating value respectively. Example: tDS (total setup time) = tDS (base) + ΔtDS. Setup (tIS, tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V REF (DC) and the first crossing of VIH (AC)(min.). Setup (tIS, tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF (DC) and the first crossing of V IL (AC)(max.). If the actual signal is always earlier than the nominal slew rate line between shaded ‘VREF (DC) to AC region’, use nominal slew rate for de-rating value (See the figure of Slew Rate Definition Nominal). If the actual signal is later than the nominal slew rate line anywhere between shaded ‘V REF (DC) to AC region’, the slew rate of a tangent line to the actual signal from the AC level to DC level is used for de-rating value (see the figure of Slew Rate Defini tion Tangent). Hold (tIH, tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V IL (DC)(max.) and the first crossing of VREF (DC). Hold (tIH, tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH (DC)(min.) and the first crossing of V REF (DC). If the actual signal is always la ter than the nominal slew rate line between shaded ‘DC level to VREF (DC) region’, use nominal slew rate for de-rating value (See the figure of Slew Rate Definition Nominal). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘DC to V REF (DC) region’, the slew rate of a tangent line to the actual si gnal from the DC level to V REF (DC) level is used for de-rating value (see the figure of Slew Rate Definition Tangent). Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached V IH / VIL (AC) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH / VIL (AC). For slew rates in between the values listed in the tables belo w, the de-rating values may be obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization.

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 18/59 De-rating Value of tDS/tDH with Differential DQS (DDR2-800, 1066) DQS, DQS differential slew rate ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH Unit DQ slew rate (V/ns) De-rating Value of tIS/tIH (DDR2-800, 1066) CLK, CLK differential slew rate 2.0 V/ns 1.5 V/ ns 1.0 V/ns ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH Unit 4.0 +150 +94 +180 +124 +210 +154 ps 3.5 +143 +89 +173 +119 +203 +149 ps 3.0 +133 +83 +163 +113 +193 +143 ps 2.5 +120 +75 +150 +105 +180 +135 ps 2.0 +100 +45 +130 +75 +160 +105 ps 1.5 +67 +21 +97 +51 +127 +81 ps 1.0 0 0 +30 +30 +60 +60 ps 0.9 -5 -14 +25 +16 +55 +46 ps 0.8 -13 -31 +17 -1 +47 +29 ps 0.7 -22 -54 +8 -24 +38 +6 ps 0.6 -34 -83 -4 -53 +26 -23 ps 0.5 -60 -125 -30 -95 0 -65 ps 0.4 -100 -188 -70 -158 -40 -128 ps 0.3 -168 -292 -138 -262 -108 -232 ps 0.25 -200 -375 -170 -345 -140 -315 ps 0.2 -325 -500 -295 -470 -265 -440 ps 0.15 -517 -708 -487 -678 -457 -648 ps Command / Address slew rate (V/ns) 0.1 -1000 -1125 -970 -1095 -940 -1065 ps

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 19/59 Slew Rate Definition Nominal

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 20/59 Slew Rate Definition Tangent

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 21/59 Command Truth Table COMMAND Note 7 CKE(n-1) Note 7 CKE(n) CS RAS CAS WE DM BA0,1 A10/AP A11, A9~A0 Note (Extended) Mode Register Set H H L L L L X OP Code (included A12) 1,2 Auto Refresh H Entry H L L L L H X X 10,12 L H H H Refresh Self Refresh Exit L H HX X X X X 6,9, 12 Bank Active H H L L H H X V Row Address Auto Precharge Disable L Read Auto Precharge Enable H H L H L H X V H Column Address (A8~A0) 1,3 Auto Precharge Disable L Write Auto Precharge Enable H H L H L L X V H Column Address (A8~A0) 1,3 Bank Selection V L Precharge All Banks H H L L H L X X H X HX X XEntry H L L H H H X 4,11, 12,14 HX X X Active Power-Down Exit L H L H H H X X 4,8, 12,14 HX X XEntry H L L H H H X 4,11, 12,14 HX X X Precharge Power-Down Exit L H L H H H X X 4,8, 12,14 DM H H X V X 15 Device Deselect H X H X X X X X No Operation H X L H H H X X (OP Code = Operand Code, V = Valid, X = Don’t Care, H = Logic High, L = Logic Low) Note: 1. BA during a MRS/EMRS command selects which mode register is programmed. 2. MRS/EMRS can be issued only at all bank Precharge state. 3. Burst Reads or Writes at BL = 4 cannot be terminated or interrupted. 4. The Power-Down mode does not perform any Refresh op erations. The duration of Power-Down is limited by the Refresh requirements. Need one cl ock delay to entry and exit mode. 5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 6. Self Refresh Exit is asynchronous. 7. CKE (n) is the logic state of CKE at clock edge n; CKE (n–1) was the state of CKE at the previous clock edge. 8. All states not shown are illegal or reserv ed unless explicitly described elsewhere in this document. 9. On Self Refresh, Exit Deselect or NOP co mmands must be issued on every clock edge occurring during the t XSNR period. Read commands may be issued only after t XSRD is satisfied. 10. Self Refresh mode can only be entered from all banks idle state. 11. Power-Down and Self Refresh can not be entered whil e Read or Write operations, MRS/EMRS operations or Precharge operations are in progress. 12. Minimum CKE HIGH / LOW time is t CKE (min). 13. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 14. ODT must be driven HIGH or LOW in Power-Down if the ODT function is enabled. 15. Used to mask write data, provid ed coincident with the corresponding data.

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 22/59 Power On and Initialization DDR2 SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power-Up and Initialization Sequence The following sequence is required for Power-Up and Initialization. 1. Apply power and attempt to maintain CKE below 0.2 x V DDQ and ODT (*1) at a low state (all other inputs may be undefined). - V DD(*2), VDDL(*2) and VDDQ are driven from a single power converter output, AND - V TT is limited to 0.95V max, AND - V REF tracks VDDQ /2. or - Apply V DD(*2) before or at the same time as VDDL. - Apply V DDL(*2) before or at the same time as VDDQ. - Apply V DDQ before or at the same time as VTT and VREF. at least one of these two sets of conditions must be met. 2. Start clock and maintain stable condition. 3. For the minimum of 200us after stable power and clock (CLK, CLK ), then apply NOP or Deselect and take CKE High. 4. Waiting minimum of 400ns then issue Precharge commands for all banks of the device. NOP or Deselect applied during 400ns period. 5. Issue EMRS(2) command. (To issue EMRS(2) co mmand, provide “LOW” to BA0, “HIGH” to BA1.) 6. Issue EMRS(3) command. (To issue EMRS(3 ) command, provide “HIGH” to BA0 and BA1.) 7. Issue EMRS(1) to enable DLL. (To issue "DLL Enable" command, provide "LOW" to A0, "HIGH" to BA0 and "LOW" to BA1.) 8. Issue a Mode Register Set command for “DLL reset” (* 3). (To issue DLL reset command, pr ovide “HIGH” to A8 and “LOW” to BA0-1) 9. Issue Precharge commands fo r all banks of the device. 10. Issue 2 or more Auto Refresh commands. 11. Issue a Mode Register Set command with LOW to A8 to init ialize device operation. (To program operation parameters without resetting the DLL.) 12. At least 200 clocks after step 8, execute EMRS(1) OCD default command (A9=A8= A7=1) followed by EMRS(1) OCD exit command (A9=A8=A7=0) must be issued with other operating parameters of EMRS(1). 13. The DDR2 SDRAM is now ready for normal operation. Note: *1) To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin. *2) If DC voltage level of VDDL or VDD is intentionally changed during normal operation, (for example, for the purpose of VDD corner test, or power saving) “DLL Reset” must be executed. *3) Every “DLL enable” command resets DLL. Therefore sequence 8 can be skipped during power up. Instead of it, the additional 200 cycles of clock input is required to lock the DLL after enabling DLL. Initialization Sequence after Power-Up CLK CLK Command 400ns PALL t RP EMRS(2) 200 Cycle (min.) NOP EMRS(3) EMRS(1) MRS PALL REF MRS EMRS(1) Any CommandEMRS(1) t MRD t MRD t MRD t MRD t RP t RFC t RFC t MRD tOIT Precharge All DLL enable DLL Reset OCD default OCD exit REF tMRD t IS t CLt CH CKE

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 23/59 Mode Register Definition Mode Register Set [MRS] The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It programs CAS latency, burst length, burst type, test mode, DLL reset, WR and various vendor s pecific options to make the device useful for variety of different applications. The default value of the mode register is not defi ned, therefore the mode register must be written after Power-Up for proper operation. The mode register is written by asserting LOW on CS , RAS , CAS , WE , BA0 and BA1 (The device should be in all bank Precharge with CKE already high prior to writing in to the mode register). The stat e of address pins A0~A12 in th e same cycle as CS , RAS , CAS , WE , BA0 and BA1 going LOW are written in the mode register. The tMRD time is required to complete the write operation to the m ode register. The mode register contents can be changed using the same command and clock cycle requirements during normal operat ion as long as all banks are in the idle state. The mode register is divided into various fields depending on functiona lity. The burst length is defined by A0 ~ A2. Burst address seque nce type is defined by A3, CAS latency (read latency from column address) is defined by A4 ~ A6. The DDR2 doesn’t support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to lo w for normal MRS operation. Write recovery time WR is defined by A9 ~ A11. Refer to the table for specific codes. BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 0 0 PD WR DLL TM CAS Latency BT Burst Length Mode Register Note: 1. WR(min.) (write recovery for Au to Precharge) is determined by t CK (max.) and WR(max.) is determined by tCK (min.) WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up a non-integer value to the next integer ( WR[cycles] = tWR (ns)/ tCK (ns)). The mode register must be programmed to this value. This is also used with tRP to determine tDAL. A3 Burst Type

0 Sequential

1 Interleave

1 Yes

Active Power down exit timing A12 PD

0 Fast Exit (normal)

1 Slow Exit (low power)

0 1 EMRS(1) 1 0 EMRS(2) 1 1 EMRS(3) : Reserved CAS Latency A6 A5 A4 Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 Reserved 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 Write recovery for Auto Precharge A11 A10 A9 WR(cycles)*1 0 0 0 Reserved 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 DDR2-1066 DDR2-800

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 24/59 Burst Address Ordering for Burst Length Burst Length Starting Column Address (A2, A1,A0) Sequential Mode Interleave Mode 000 0, 1, 2, 3 0, 1, 2, 3 001 1, 2, 3, 0 1, 0, 3, 2 010 2, 3, 0, 1 2, 3, 0, 1 4 011 3, 0, 1, 2 3, 2, 1, 0 Mode Register Set 01 234 5678 COMMAND tCK Precharge All Banks Mode Register Set Any Command t RP CLK CLK t MRD *1 : MRS can be issued only at all banks precharge state. * 2 : M i n i m u m tRP is required to issue MRS command. DLL Enable / Disable The DLL must be enabled for normal operation. DLL enable is re quired during power-up initialization, and upon returning to normal operation after having the DLL disabled for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL is enabled automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. Output Drive Impedance Control The normal drive strength for all outputs is specified to be SSTL_18. The device also s upports a reduced drive strength option, intended for lighter load and/or point-to-point environments.

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 25/59 Extended Mode Register Set-1 [EMRS(1)] The EMRS(1) stores the data for enabling or disabling DLL, output driver impedance control, additive latency, ODT, disable DQS , OCD program. The default value of the EMRS(1) is not defined, therefore EMRS(1) must be written after power up for proper operation. The EMRS(1) is written by asserting LOW on CS , RAS , CAS , WE , BA1 and HIGH on BA0 (The device should be in all bank Precharge with CKE already high prior to writing in to EMRS(1)). The state of address pins A0~A12 in the same cycle as CS , RAS , CAS , WE and BA1 going LOW and BA0 going HIGH are written in the EMRS(1). The tMRD time is required to complete the write operation to the EMRS(1). The EMRS(1) contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. A1 is used for reducing output driver impedance control. The additive latency is defined by A3~A5. A7~A9 are used for OCD control. A10 is used for DQS disable. ODT setting is defined by A2 and A6. BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 1 Qoff 0 *1 DQS OCD program Rtt Additive Latency Rtt D.I.C DLL A10 DQS Enable

0 Enable

1 Disable

Note: 1. A11 is reserved for future use and must be set to 0. 2. As detailed in the Initialization sect ion notes, during initialization of the OCD operation, all three bits must be set to “1” for the OCD default state, then set to “0” before initialization finished. 3. Output disabled - DQs, DQSs, DQS s. This feature is used in conjunction with DIMM IDD measurements when IDDQ is not desired to be included. A0 DLL Enable A6 A2 Rtt (nominal) 0 0 Disable 0 1 75 Ω 1 0 150 Ω 1 1 50 Ω A1 Output Driver Impedance Control

0 Full strength

1 Reduced strength

A12 Qoff*3

0 Output buffer enable

1 Output buffer disable

A9 A8 A7 OCD operation*2 0 0 0 OCD exit 0 0 1 Reversed 0 1 0 Reversed 1 0 0 Reversed 1 1 1 Enable OCD default BA1 BA0 Mode Register 0 0 MRS 0 1 EMRS(1) 1 0 EMRS(2) 1 1 EMRS(3): Reserved

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 26/59 Extended Mode Register Set-2 [EMRS(2)] The EMRS(2) controls refresh related feat ures. The default value of the EMRS(2) is not defined, therefore EMRS(2) must be written after power up for proper operation. The EMRS(2) is written by asserting LOW on CS , RAS , CAS , WE , BA0 and HIGH on BA1 (The device should be in all bank Precharge with CKE already high prior to writing into EMRS(2)). The state of address pins A0~A12 in the same cycle as CS , RAS , CAS , WE and BA0 going LOW and BA1 going HIGH are written in the EMRS(2). The tMRD time is required to complete the write operation to the EMRS(2). The EMRS(2) contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the idle state. A7 is used for high temperature self refresh rate enable or disable. A3 is used for DCC enable or disable. BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 0 0 *1 SRF 0 *1 DCC *2 0 *1 Note: 1. A0~A2, A4~A6 and A8~A12 are reserved for future use and must be set to 0. 2. User may enable or disable the DCC (Duty Cycle Corrector) by programming A3 bit accordingly. BA1 BA0 Mode Register 0 0 MRS 0 1 EMRS(1) 1 0 EMRS(2) 1 1 EMRS(3): Reserved A3 DCC Enable

0 Disable

1 Enable

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 27/59 Extended Mode Register Set-3 [EMRS(3)] BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 1 0 Note: EMRS(3) is reserved for future. All bits except BA0 and BA1 are reserved for future use and must be set to 0 when setting to mode register during initialization. BA1 BA0 Mode Register 0 0 MRS 0 1 EMRS(1) 1 0 EMRS(2) 1 1 EMRS(3): Reserved

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 28/59 Off-Chip Driver (OCD) Impedance Adjustment The Off-Chip Driver function is an optional DDR2 JEDEC feature not sup ported by ESMT and thereby mu st be set to the default state. Enabling OCD beyond the default settings will alter the I/O drive charac teristics and the timing and output I/O specific ations will no longer be valid (see Initialization for proper setting of OCD defaults). ODT (On Die Termination) On Die Termination (ODT) is a feature that allows a DDR2 SDRAM to turn on/off terminatio n resistance for each DQ, all DQS/ DQS , and all DM signals via the ODT control pin. The ODT feature is designed to im prove signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all devices. The ODT function is supported for Active and Standby modes. ODT is turned off and not supported in Self Refresh mode. Timing for ODT Update Delay CLK CLK EMRS(1) tAOFD Command ODT Internal Rtt Setting tIS NOP tMOD(min.) tMOD(max.) Old setting Updating New Setting Note: tAOFD must be met before issuing EMRS(1) command. ODT must remain low for the entire duration of t MOD window. ODT Timing for Active and Standby Mode CLK CLK CKE ODT Internal Term Res. T0 T1 T2 T3 T4 T5 T6 tAOFD tIS tAOND tIS tAON(min.) tAON(max.) tAOF(min.) tAOF(max.) Rtt

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 29/59 ODT Timing for Power-Down Mode CLK CLK CKE ODT Internal Term Res. T0 T1 T2 T3 T4 T5 T6 tIStIS tAONPD(min.) tAONPD(max.) tAOFPD(min.) Rtt tAOFPD(max.)

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 30/59 ODT Timing Mode Switch at Entering Power-Down Mode CKE CLK CLK T-5 T-4 T-3 T-2 T-1 T0 T1 T2 T3 tIS tANPD Entering slow exit Active Power-Down mode or Precharge Power-Down mode. Active and Standby mode timings to be applied. ODT Internal Term Res. tIS tAOFD Rtt Power-Down mode timings to be applied. ODT Internal Term Res. tIS Rtt Active and Standby mode timings to be applied. ODT Internal Term Res. tIS Rtt Power-Down mode timings to be applied. ODT Internal Term Res. tIS Rtt tAOFPD(max.) tAOND tAONPD(max.)

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 31/59 ODT Timing Mode Switch at Exiting Power-Down Mode CKE CLK CLK T0 T1 T4 T5 T6 T7 T8 T9 T10 T11 tIS tAXPD Exiting from slow Active Power-Down mode or Precharge Power-Down mode. Active and Standby mode timings to be applied. ODT Internal Term Res. tIS tAOFD Rtt Power-Down mode timings to be applied. ODT Internal Term Res. tIS Rtt Active and Standby mode timings to be applied. ODT Internal Term Res. tIS Rtt Power-Down mode timings to be applied. ODT Internal Term Res. tIS Rtt tAOFPD(max.) tAOND tAONPD(max.)

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 32/59 Precharge The Precharge command is used to precharge or close a bank that has activated. The command is issued when CS , RAS and WE are LOW and CAS is HIGH at the rising edge of the clock. T he Precharge command can be used to precharge each bank respectively or all banks simultaneously. The bank select addresses (BA0, BA1) and A10 are used to define which bank is precharged when the command is initiated. For write cycle, t WR(min.) must be satisfied until the Precharge command can be issued. After tRP from the precharge, a Bank Active command to the same bank can be initiated. Bank Selection for Precharge by Address bits A10/AP BA1 BA0 Precharge 0 0 0 Bank A Only 0 1 0 Bank B Only 0 0 1 Bank C Only 0 1 1 Bank D Only

1 X X All Banks

NOP & Device Deselect The device should be deselected by deactivating the CS signal. In this mode, DDR2 SDRAM would ignore all the control inputs. The DDR2 SDRAM are put in NOP mode when CS is active and by deactivating RAS , CAS and WE . For both Deselect and NOP, the device should finish the current operation when this command is issued. Bank Active The Bank Active command is issued by holding CAS and WE HIGH with CS and RAS LOW at the rising edge of the clock (CLK). The DDR2 SDRAM has four independent banks, so two Bank Select addresses (BA0, BA1) are required. The Bank Active command to the first Read or Write command must meet or exceed the minimum of RAS to CAS delay time (t RCD(min.)). Once a bank has been activated, it must be pr echarged before another Bank Active command can be applied to the same bank. The minimum time interval between interleaved Bank Active command (B ank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD min). Bank Active Command Cycle CLK CLK ACT tCCD T0 T1 T2 T3 Tn Tn+1 Tn+2 Tn+3 Command Posted READ ACT Posted READ PRE ACT Bank A Row Addr. Bank BAddress Bank B Row Addr. Bank B Col. Addr. Bank A Row Addr. Additive latency (AL)tRCD=1 tRRD Bank A Col. Addr. tRAS tRC PRE Bank A tRP Bank A Active Bank B Active Bank A Precharge Bank B Precharge Bank A Active Bank A Read begins

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 33/59 Read Bank This command is used after the Bank Active command to initia te the burst read of data. T he Read command is initiated by activating CS , CAS , and deasserting WE at the same clock sampling (rising) edge as described in the command truth table. The length of the burst and the CAS latency time will be determined by the values programmed during the MRS command. Write Bank This command is used after the Bank Active command to initia te the burst write of data. The Write command is initiated by activating CS , CAS , and WE at the same clock sampling (rising) edge as de scribe in the command truth table. The length of the burst will be determined by the values programmed during the MRS command. Posted Posted CAS operation is supported to make command and data bus e fficient for sustainable bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a Read or Write command to be issued immedi ately after the Bank Active command (or any time during the tRRD period). The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of AL and the CAS latency (CL). Therefore if a user chooses to issue a R/W command before the t RCD(min), then AL (greater than 0) must be written into the EMRS(1). The Write Latency (WL) is always defined as RL - 1 (read latency -1) where read latenc y is defined as the sum of additive latency plus CAS latency (RL=AL+CL). Read or Write operations using AL allow seamless bursts. Read followed by a Write to the Same Bank < A L = 2 ; C L = 3 ; B L = 4 > -1 03 4 5 6 7 89 10 11 12 CMD CLK CLK Active Bank A Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 WL = RL -1 =4 AL = 2 CL = 3 >= tRCD RL = AL + CL = 5 DQS/DQS DQ Read Bank A Write Bank A < AL= 0; CL= 3; BL = 4 > -1 0 34 5 6 7 8 9 10 11 12 CMD CLK CLK Write Bank A Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 WL = RL -1 = 2 AL = 0 CL = 3 >= tRCD RL = AL + CL = 3 DQS/DQS DQ Active Bank A Read Bank A

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 34/59 Essential Functionality for DDR2 SDRAM Burst Read Operation The Burst Read command is initiated by having CS and CAS LOW while holding RAS and WE HIGH at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency (R L). The DQS is driven LOW 1 clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of DQS. Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the MRS and the AL is defined by the EMRS(1). Read (Data Output) Timing CLK CLK Dout0 tCH DQS tDQSQ(max.) tCL DQS DQ Dout1 Dout2 Dout3 tQH tRPST tQH tDQSQ(max.) tRPRE Burst Read < RL= 5 (AL= 2; CL= 3); BL= 4 > CLK CLK T0 T1 T2 T3 T4 T5 T6 T7 CMD Posted CAS READ A NOP AL = 2 NOP NOPNOP NOPNOP NOPNOP DQS,DQS CL = 3 RL = 5 DoutA0 DoutA1 DoutA2 DoutA3DQs =< tDQSCK < RL= 3 (AL= 0; CL= 3); BL= 8 > CLK CLK T0 T1 T2 T3 T4 T5 T6 T7 CMD NOP NOP NOPNOP NOPNOP NOPNOP DQS,DQS CL = 3 RL = 3 DoutA4 DoutA5 DoutA6 DoutA7 READ A DQs DoutA0 DoutA1 DoutA2 DoutA3 =< tDQSCK

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 35/59 Burst Read followed by Burst Write < RL= 5; WL= (RL-1) = 4; BL= 4 > CLK CLK T0 T1 Tn-1 Tn Tn+1 Tn+2 Tn+3 Tn+4 CMD Posted CAS READ A NOP Tn+5 NOP NOP NOPNOP NOPNOP DQS,DQS WL = RL-1 = 4 RL = 5 DoutA0 DoutA1 DoutA2 DoutA3DQs Posted CAS WRITE A tRTW (Read to Write-turn around-time) DinA0 DinA1 DinA2 DinA3 Note: The minimum time from the Burst Read command to the Burst Write command is defined by a read to write-turn around-time(t RTW), which is 4 clocks in case of BL = 4 operation, 6 clocks in case of BL = 8 operation. Seamless Burst Read < RL= 5; AL= 2; CL= 3; BL = 4 > CLK CLK T0 T1 T2 T3 T4 T5 T6 T7 CMD Posted CAS READ A AL = 2 NOP NOPNOP NOPNOP NOPNOP DQS,DQS CL = 3 RL = 5 DoutA0 DoutA1 DoutA2 DoutA3DQs Posted CAS READ B DoutB0 DoutB1 DoutB2 Note: The seamless burst read operation is supported by enabling a Read command at every other clock for BL = 4 operation, and every 4 clock for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated.

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 36/59 Burst Write Operation The Burst Write command is issued by having CS , CAS and WE LOW while holding RAS HIGH at the rising edge of the clock (CLK). The address inputs determine the starting column addr ess. Write latency (WL) is def ined by a read latency (RL) minus one and is equal to (AL + CL -1); and is the number of clocks of delay that are required from the time the write command is registered to the clock edge associated to the first DQS strobe. A data strobe signal (DQS) should be driven low (preamble) one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The t DQSS specification must be satisfied for each posit ive DQS transition to its associated clock edge during write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed, which is 4 or 8 bit burst. When the burst has finished, any additi onal data supplied to the DQ pi ns will be ignored. The DQ sig nal is ignored after the burst write operation is complete. The time from the comple tion of the burst write to bank precharge is th e write recovery time (tWR). Write (Data Input) Timing DQS DQS DQ tDS tWPRE Din0 Din1 Din2 Din3 tDS DM tDH tDH DQS DQS tDQSH tDQSL tWPST Burst Write < RL= 5 (AL= 2; CL= 3); WL= 4; BL= 4 > CLK CLK T0 T1 T2 T3 T4 T5 T6 T7 CMD Posted CAS WRITE A NOP W L=R L- 1=4 Tn NOP NOPNOP NOPNOP PrechargeNOP DQS,DQS DinA0 DinA1 DinA2 DinA3DQs Case1 : with tDQSS(max) tDSS W L=R L- 1=4 DQS,DQS DinA0 DinA1 DinA2 DinA3DQs tDSH Case2 : with tDQSS(min) tDQSS tDQSS >= tWR >= tWR < RL= 3 (AL= 0; CL= 3); WL= 2; BL= 4 > CLK CLK T0 T1 T2 T3 T4 T5 T6 T7 CMD NOP Tn NOP NOPNOP NOP Bank A ActiveNOPWRITE A W L=R L- 1=2 DQS,DQS DinA0 DinA1 DinA2 DinA3DQs tDQSS tWR Precharge >= tRP

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 37/59 Burst Write followed by Burst Read < RL= 5 (AL= 2; CL= 3); WL= 4; BL= 4 > CLK CLK T0 T1 T2 T3 T4 T5 T6 T7 CMD NOP W L=R L- 1=4 NOP NOP NOPNOP NOP DQS,DQS DinA0 DinA1 DinA2 DinA3DQ W r i t et oR e a d=C L- 1 + B L / 2 + tWTR >=t WTR CL = 3 NOP NOPNOP DQS DQS AL = 2 DoutA0 Posted CAS READ A RL = 5 Note: The minimum number of clock from the Burst Write command to the Burst Read command is [CL - 1 + BL/2 + tWTR]. This tWTR is not a write recovery time (WR) but the ti me required to transfer the 4 bit write data from the input buffer into sense amplifiers in the array. Seamless Burst Write < RL= 5; WL= 4; BL= 4 > CLK CLK T0 T1 T2 T3 T4 T5 T6 T7 CMD NOP NOPNOP NOPNOP NOPNOP DQS,DQS WL = RL-1 = 4 DQs DinA0 Posted CAS WRITE A Posted CAS WRITE B DinA1 DinA2 DinA3 DinB0 DinB1 DinB2 DinB3 Note: The seamless burst write operation is supported by enabling a Write command at every other clock for BL = 4 operation, and every 4 clock for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated.

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 38/59 Read Interrupted by a Read Burst Read can only be interrupted by another read with 4 bit burst boundary. Any other case of read interrupt is not allowed. < CL= 3; AL= 0; RL= 3; BL= 8 > CLK CLK CMD NOP NOP NOPNOP NOPNOP DQS,DQS DQs A0 READ A READ B NOP A1 A3A2 B0 B3B2B1 B4 B7B6B5 NOP Note: 1. Read burst interrupt function is only allo wed on burst of 8. Burst interrupt of 4 is prohibited. 2. Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write command or Precharge command is prohibited. 3. Read burst interrupt must occur exactly tw o clocks after previous Read command. Any other Read burst interrupt timings are prohibited. 4. Read burst interruption is allowed to any bank inside DRAM. 5. Read burst with Auto Precharge enabled is not allowed to interrupt. 6. Read burst interruption is allowed by another Read with Auto Precharge command. 7. All command timings are referenced to burst l ength set in the mode register. They are not referenced to actual burst. For example, Minimum Read to Prec harge timing is AL + BL/2 where BL is the burst length set in the MRS and not the actual burst (which is shorter because of interrupt).

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 39/59 Write Interrupted by a Write Burst Wirte can only be interrupted by another Write with 4 bit burst boundary. Any other case of Write interrupt is not allowed. < CL= 3; AL= 0; RL= 3; WL= 2; BL= 8 > CLK CLK T0 T1 T2 T3 T4 T5 T6 T7 CMD Write A NOP NOPNOP NOPNOP DQS,DQS DQs A0 NOP NOP NOP A1 A3A2 B0 B3B2B1 B4 B7 B6B5 Write B Note: 1. Write burst interrupt function is only allo wed on burst of 8. Burst interrupt of 4 is prohibited. 2. Write burst of 8 can onl y be interrupted by another Write command. Write burst interruption by Read command or Precharge command is prohibited. 3. Write burst interrupt must occur exactly two clocks after previous Write command. Any other Write burst interrupt timings are prohibited. 4. Write burst interruption is allowed to any bank inside DRAM. 5. Write burst with Auto Precharge enabled is not allowed to interrupt. 6. Write burst interruption is allowe d by another Write with Auto Precharge command. 7. All command timings are referenced to burst l ength set in the MRS. They are not referenced to actual burst. For example, minimum Write to Precharge timing is WL+BL/2+ t WR where tWR starts with the rising clock after the un-interrupted burst end and not from the end of actual burst end.

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 40/59 Burst Read Followed by Precharge Minimum Read to Precharge command spacing to the same bank = AL + BL/2 + max(tRTP, 2) - 2 clocks. For the earliest possible Precharge, the Precharge command may be issued on the rising edge which is “Additive latency (AL) + BL/2 clocks” after a Read command. A new Bank Active command may be issued to the same bank after the Precharge time (t RP). A Precharge command cannot be issued until tRAS is satisfied. The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the last 4-bit prefetch of a Read to Precharge command. This time is called tRTP (Read to Precharge). For BL = 4, this is the time from the actual read (AL after the Read command) to Precharge command. For BL = 8, this is the time from AL + 2 clocks after the Read to the Precharge command. < RL= 4 (AL= 1; CL= 3) > CLK CLK T0 T1 T2 T3 T4 T5 T6 T7 CMD Posted CAS READ A NOP AL + BL/2 clks NOP NOP NOPNOPPrecharge Bank A Active DQS,DQS DoutA0 DQs >= tRP NOP AL = 1 CL = 3 RL = 4 DoutA1 DoutA2 DoutA3 >= tRAS CL = 3>= tRTP CMD Posted CAS READ A NOP AL + BL/2 clks NOP NOPNOP NOPPrecharge A DQS,DQS DoutA0 DQs NOP AL = 1 CL = 3 RL = 4 DoutA1 DoutA2 DoutA3 DoutA4 DoutA5 DoutA6 DoutA7 >= tRTP NOP BL = 8 BL = 4 < RL= 5 (AL= 2; CL= 3); BL= 4 > CLK CLK T0 T1 T2 T3 T4 T5 T6 T7 CMD Posted CAS READ A NOP AL + BL/2 clks NOP NOP NOPNOPPrecharge A Bank A Active DQS,DQS DoutA0 DQs >= tRP NOP AL = 2 CL = 3 RL = 5 DoutA1 DoutA2 DoutA3 >= tRAS CL = 3>= tRTP < RL= 6 (AL= 2; CL= 4); BL= 4 > CLK CLK T0 T1 T2 T3 T4 T5 T6 T7 CMD Posted CAS READ A NOP AL + BL/2 clks NOP NOP NOPNOPPrecharge A Bank A Active DQS,DQS DoutA0 DQs >= tRP NOP AL = 2 CL = 4 RL = 6 DoutA1 DoutA2 DoutA3 >= tRAS CL = 4>= tRTP

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 41/59 < RL= 4 (AL= 0; CL= 4); BL=8 > CLK CLK CMD NOP NOPNOP NOPPrecharg A Bank A ActiveNOP DQS,DQS AL+2 clks + max(tRTP;2) DQs Posted CAS WRITE A T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP >=t RP CL = 4AL = 0 >= tRAS DoutA0 DoutA1 DoutA2 DoutA3 DoutA4 DoutA5 DoutA6 DoutA7 RL = 4 Burst Write Followed by Precharge Minimum Write to Precharge command spacing to the same bank = WL + BL/2 clocks + tWR. For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge command can b e issued. This delay is known as a write recovery time (t WR) referenced from the completion of the Burst Write to the Precharge command. No Precharge command should be issued prior to the tWR delay. < WL= (RL-1) = 3; BL=4> CLK CLK CMD NOP NOPNOP NOP Precharg ANOP DQS,DQS DQs Posted CAS WRITE A T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP >=t WR WL = 3 DinA0 NOP DinA1 DinA2 DinA3 < WL= (RL-1) = 4; BL=4 > CLK CLK CMD NOP NOPNOP NOP Precharg ANOP DQS,DQS DQs Posted CAS WRITE A T0 T1 T2 T3 T4 T5 T6 T7 T9 NOP >=t WR WL = 4 DinA0 NOP DinA1 DinA2 DinA3

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 42/59 Write data mask by DM One write data mask (DM) pin for each 8 data bits (DQ) will be s upported on DDR2 SDRAM, Consistent with the implementation on DDR2 SDRAM. It has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM is not used during read cycles. Data Mask Timing DQS DQS T1 T2 T3 T4 T5 Tn DQ DM Din Din Din Din Din Din Din Din Din Write mask Iatency = 0 Example: < WL= 3; AL= 0; BL= 4 > CLK CLK T0 T1 T2 T3 T4 T5 T6 T7 Command WL DQS,DQS Din0DQ tWR NOPWRIT tDQSS Din2 DM [tDQSS(min.)] WL DQS,DQS Din0DQ tDQSS Din2 DM [tDQSS(max.)]

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 43/59 Read with Auto Precharge If A10 is HIGH when a Read command is issued, the Read with Auto Precharge function is engaged. The device starts an Auto Precharge operation on the rising edge which is (AL + BL/2) cycles later than the Read with AP command if tRAS (min) and tRTP(min) are satisfied. If tRAS(min) is not satisfied at the edge, the start point of Auto Precharge operation will be delayed until tRAS(min) is satisfied. If tRTP (min) is not satisfied at the edge, the start point of Auto Precharge operation will be delayed until tRTP (min) is satisfied. In case the internal precharge is pushed out by t RTP, tRP starts at the point where the inter nal precharge happens (not at the next rising clock edge after this event). So for BL = 4, the minimum time from Read_AP to the next Bank Active command becomes AL + (tRTP + t RP)*. For BL = 8, the time from Read_AP to the next Bank Active command is AL + 2 + (t RTP + t RP)*. (Note: “*” means “rouded up to the next integer”). < RL= 4 (AL= 1; CL= 3) > CLK CLK T0 T1 T2 T3 T4 T5 T6 T7 CMD NOP NOPNOP NOPNOP Bank A ActiveNOP DQS,DQS DQs Posted CAS READ A NOP AL+BL/2 clks >=t RP Autoprecharge CL = 3AL = 1 >= tRTP DoutA0 DoutA1 DoutA2 DoutA3 DoutA4 DoutA5 DoutA6 DoutA7 RL = 4 tRTP Precharge begins here BL = 8 t RTP <= 2 clocks CMD NOP NOPNOP NOPNOP Bank A Active NOP DQS,DQS DQs Posted CAS READ A NOP >=AL+tRTP+tRP Autoprecharge CL = 3AL = 1 tRP DoutA0 DoutA1 DoutA2 DoutA3 RL = 4 tRTP Precharge begins here BL = 4 t RTP > 2 clocks A new Bank Active command may be issued to the same bank if the following two conditions are satisfied simultaneously. (1) The Precharge time (tRP) has been satisfied from the clock at which the Auto Precharge begins. (2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 44/59 < RL= 5 (AL= 2; CL= 3); BL= 4; tRCD = 3 clocks; tRTP <= 2 clocks > CLK CLK T0 T1 T2 T3 T4 T5 T6 T7 CMD Posted CAS READ A NOP >= tRAS(min) NOP NOP NOPNOP Bank A Active DQS,DQS DoutA0DQs >= tRP NOP AL = 2 CL = 3 RL = 5 DoutA1 DoutA2 DoutA3 >= tRC tRC Limit NOP Autoprecharge Autoprecharge begins CLK CLK CMD Posted CAS READ A NOP >= tRAS(min) NOP NOP NOPNOP Bank A Active DQS,DQS DoutA0DQs >= tRP NOP AL = 2 CL = 3 RL = 5 DoutA1 DoutA2 DoutA3 tRP Limit NOP Autoprecharge Autoprecharge begins >= tRC Write with Auto Precharge If A10 is HIGH when a Write command is issued, the Write with Auto Precharge function is engaged. The device automatically begins precharge operation after the completion of the burst write plus write recovery time (t WR). The Bank Active command undergoing Auto Precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied. (1) The data-in to bank activate delay time (tWR + tRP) has been satisfied. (2) The RAS cycle time (tRC) from the previous bank activation has been satisfied. < WR = 2; BL= 4; tRP = 3 clocks > CLK CLK T0 T1 T2 T3 T4 T5 T6 T7 CMD Posted CAS WRITE A NOP Tm NOP NOP NOPNOP Bank A Active DQS,DQS DinA0DQs >= tRP NOP WL = RL-1 = 2 >= tRC tRC Limit NOP Autoprecharge Auto Precharge begins CLK CLK CMD Posted CAS WRITE A NOPNOP NOP NOPNOP Bank A Active DQS,DQS DinA0DQs NOP DinA1 DinA2 DinA3 >= tRC tWR + tRP NOP Autoprecharge DinA1 DinA2 DinA3 >= tWR T0 T3 T4 T5 T6 T7 T8 T9 T12 Auto Precharge begins >= tRP>= tWRWL = RL-1 = 4

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 45/59 Auto Refresh & Self Refresh Auto Refresh An Auto Refresh command is issued by having CS , RAS and CAS held LOW with CKE and WE HIGH at the rising edge of the clock(CLK). All banks must be precharged and idle for t RP(min) before the Auto Refresh comm and is applied. An address counter, internal to the device, supplies the bank address during the refr esh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has completed, all banks will be in the idle state. A delay between the Auto Ref resh command and the next Bank Active command or subsequent Auto Refresh command must be greater than or equal to the tRFC(min).To allow for improved efficiency in scheduling and switch ing between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight Refresh commands can be posted, meaning that the maximum absolute interval between any Refresh command and the next Refresh command is 9 x tREFI. COMMAND CKE = High t RP PRE Auto Refresh CMD t RFC CLK CLK

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 46/59 Self Refresh A Self Refresh command is defined by having CS , RAS , CAS and CKE held LOW with WE HIGH at the rising edge of the clock (CLK). ODT must be turned off before issuing Self Refres h command, by either driving ODT pin low or using EMRS(1) command. Once the command is registered, CKE must be held LO W to keep the device in Self Refresh mode. The DLL is automatically disabled upon entering Self Refresh and is automa tically enabled upon exiting Self Refresh. When the device has entered Self Refresh mode, all of the external signals except CKE, are “don’t care”. For proper Self Refresh operation all power supply pins (V DD, VDDQ, VDDL and VREF) must be at valid levels. The device initiates a minimum of one refresh command internally within t CKE period once it enters Self Refresh mode. The clock is internally disabled during Self Refresh operation to save power. Self Refresh mode must be remained tCKE (min). The user may change the external clock frequency or halt the exte rnal clock one clock after Self Refresh entry is registered, however, the clock must be restarted and st able before the device can exit Self Refr esh operation. The procedure for exiting Se lf Refresh requires a sequence of commands. First, the clock must be stable prior to CKE going back HIGH. Once Self Refresh Exit is registered, a delay of t XSRD(min) must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. CKE must remain HIGH for the entire Self Refresh exit period t XSRD for proper operation except for Self Refresh re-entry. Upon exit from Self Refresh, the device can be put back into Self Refresh mode after waiting t XSNR(min) and issuing one Refresh command. NOP or deselect commands must be registered on each positiv e clock edge during the Self Refresh exit interval t XSNR. ODT should be turned off during t XSRD. The use of Self Refresh mode in troduces the possibility that an internally timed refresh event can be missed when CKE is raised fo r exit from Self Refresh mode. Upon exit from Self Refresh, t he device requires a minimum of one extra auto refresh command before it is put back into Self Refresh mode. CLK CLK T0 T1 T2 T3 T4 T5 T6 Tn CKE Tm ODT >= tXSNR tRP Command tAOFD >= tXSRD tIS tIS tIS tIH tIS tCK tCH tCL Note: 1. Device must be in the “All banks idle” state prior to entering Self Refresh mode. 2. ODT must be turned off t AOFD before entering Self Refresh mode, and can be turned on again when tXSRD t i m i n g i s s a t i s f i e d . 3 . t XSRD is applied for a Read or a Read with Auto Precharge command. 4 . t XSNR is applied for any command except a Read or a Read with Auto Precharge command.

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 47/59 Power-Down Power-Down is synchronously entered when CKE is registered LOW (no accesses can be in progress). CKE is not allowed to go LOW while MRS or EMRS command time, or read or write operation is in progress. CKE is allowed to go LOW while any of other operations such as Bank Active, Precharge or Auto Precharge, or Auto Refresh is in progress. The DLL should be in a locked state when Power-Down is entered. Otherwise DLL should be reset after exiting Power-Down mode for proper read operation. If Power-Down occurs when all banks are idle, this mode is referred to as Precharge Power-Down; if Power-Down occurs when there is a Bank Active command in any bank, this mode is referred to as Active Power-Down. Entering Power-Down deactivates the input and output buffers, excluding CLK, CLK , ODT and CKE. Also the DLL is disabled upon entering Precharge Power-Down or slow exit Active Power-Down, but the DLL is kept enabled during fast exit Active Power-Down. In Power-Down mode, CKE LOW and a stable clock signal must be maintained at the inputs of the device, and ODT should be in a valid state but all other input signals are “Don’t Care”. CKE LOW must be maintained until tCKE has been satisfied. Power-Down duration is limited by 9 times tREFI of the device. The Power-Down state is synchronously exited when CKE is registered HIGH (along with a NOP or DESELECT command). CKE HIGH must be maintained until tCKE has been satisfied. A valid, executable command can be applied with Power-Down exit latency, tXP, tXARD, or tXARDS, after CKE goes HIGH. CLK CLK CKE Command VALID tIS tIH tIS tIH tIH tIS tIH NOP NOP VALID VALIDVALID tCKE tCKE Enter power-down mode tXP, tXARD, tXARDS Exit power-down mode tCKE :D o n ’ tc a r e Read to Power-Down Entry CLK CLK Command READ CKE CKE should be kept high until the end of burst operation DQ T0 T1 T2 Tx Tx+1 Tx+2 Tx+3 High AL + CL DoutA0 DoutA1 DoutA2 DoutA3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 DQS DQS BL = 4 CLK CLK Command READ CKE CKE should be kept high until the end of burst operation DQ T0 T1 T2 Tx Tx+1 Tx+2 Tx+3 High AL + CL DoutA0 DoutA1 DoutA2 DoutA3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 DQS DQS BL = 8 DoutA4 DoutA5 DoutA6 DoutA7

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 48/59 Read with Auto Precharge to Power-Down Entry CLK CLK Command READ CKE CKE should be kept high until the end of burst operation DQ T0 T1 T2 Tx Tx+1 Tx+2 Tx+3 AL+BL/2 with tRTP =7.5ns and tRAS(min.) satisfied AL + CL DoutA0 DoutA1 DoutA2 DoutA3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 DQS DQS BL = 4 CLK CLK Command READ CKE CKE should be kept high until the end of burst operation DQ T0 T1 T2 Tx Tx+1 Tx+2 Tx+3 AL + CL DoutA0 DoutA1 DoutA2 DoutA3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 DQS DQS BL = 8 DoutA4 DoutA5 DoutA6 DoutA7 PRE PRE Start internal precharge AL+BL/2 with tRTP =7 . 5 n s and tRAS(min.) satisfied Write to Power-Down Entry CLK CLK Command WRITE CKE DQ T0 T1 Tm Tm+1 Tm+2 Tm+3 Tx WL DinA0 DinA1 DinA2 DinA3 Tx+1 Tx+2 Ty Ty+1 Ty+2 Ty+3 DQS DQS BL = 4 CLK CLK Command WRITE CKE DQ T0 T1 Tm Tm+1 Tm+2 Tm+3 Tm+4 DinA0 DinA1 Tm+5 Tx Tx+1 Tx+2 Tx+3 Tx+4 DQS DQS BL = 8 tWTR DinA2 DinA3 DinA4 DinA5 DinA6 DinA7 tWTR WL

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 49/59 Write with Auto Precharge to Power-Down Entry CLK CLK Command WRITE A CKE DQ T0 T1 Tm Tm+1 Tm+2 Tm+3 Tx WL DinA0 DinA1 DinA2 DinA3 Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 DQS DQS BL = 4 CLK CLK Command WRITE A CKE DQ T0 T1 Tm Tm+1 Tm+2 Tm+3 Tm+4 DinA0 DinA1 Tm+5 Tx Tx+1 Tx+2 Tx+3 Tx+4 DQS DQS BL = 8 tWR DinA2 DinA3 DinA4 DinA5 DinA6 DinA7 tWR WL PRE PRE Auto Refresh/ Bank Active/ Precharge to Power-Down Entry CLK CLK Command CMD CKE T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 CKE can go to low one clock after a command Note: CMD could be Auto Refresh/ Bank Active/ Precharge command. MRS/EMRS to Power-Down Entry CLK CLK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 CKE MRS/ EMRSCommand tMRD

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 50/59 Asynchronous CKE Low event DDR2 SDRAM requires CKE to be maintained “HIGH” for all valid operations as defined in this data sheet. If CKE asynchronously drops “LOW” during any valid operation, the device is not guaranteed to preserve the c ontents of array. If this event occurs, memory controller must satisfy t DELAY before turning off the clocks. Stable clocks must exist at the input of device before CKE is raised “HIGH” again. The device must be fully re-initialized (s teps 4 ~ 13) as described in initialization sequence. The device is ready for normal operation after the initialization sequence. CLK CLK CKE tCK tDELAY Stable clocks CKE asynchronously drops low C l o c k sc a nb et u r n e do f f after this point Clock Frequency change in Precharge Power-Down mode DDR2 SDRAM input clock frequency can be changed under following condition: The device is in Precharge Power-Down mode. ODT must be tur ned off and CKE must be at logic LOW level. A minimum of 2 clocks must be waited after CKE goes LOW before clock frequenc y may change. The device input clock frequency is allowed to change only between t CK (min) and t CK (max). During input clock frequency change, ODT and CKE must be held at stable LOW levels. Once input clock frequency is ch anged, stable new clocks must be provided before Prechar ge Power-Down may be exited and DLL must be RESET via MRS after Precharge Power-Down exit. Depending on new clock frequency an additional MRS command may need to be issued to appropriately set the WR, CL etc. . During DLL re-lock period, ODT must remain off. After the DLL lock time, the device is ready to operate with new clock frequency. CLK CLK Minimum 2 clocks required before changing frequency T0 T1 T2 T4 tRP Tx Tx+1 Ty Ty+1 Ty+2 Ty+3 Ty+4 Tz CKE ODT NOPcommand NOP NOP NOP DLL Reset NOP Vaild tAOFD txP 200 clocks Frequency change occurs here Stable new clock before power down exit ODT is off during DLL RESET

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 51/59 Functional Truth Table Current State CS RAS CAS WE Address Command Action H X X X X DESEL NOP or Power-Down L H H H X NOP NOP or Power-Down L H L X BA, CA, A10 READ / READA / WRITE / WRITEA ILLEGAL (*1) L L H H BA, RA Active Bank Active, Latch RA L L H L BA, A10 / A10 PRE / PREA Precharge / Precharge All L L L H X Refresh Refresh (*2) IDLE L L L L Op-Code Mode-Add MRS / EMRS Mode Register setting / Extended Mode Register setting (*2) H X X X X DESEL NOP L H H H X NOP NOP L H L H BA, CA, A10 READ / READA Begin Read, Latch CA, Determine Auto Precharge L H L L BA, CA, A10 WRITE / WRITEA Begin Write, Latch CA, Determine Auto Precharge L L H H BA, RA Active ILLEGAL (*1) L L H L BA, A10 /A10 PRE / PREA Precharge / Precharge All L L L H X Refresh ILLEGAL BANK ACTIVE L L L L Op-Code Mode-Add MRS / EMRS ILLEGAL H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H L H BA, CA, A10 READ / READA Terminate Burst, Latch CA, Begin New Read, Determine Auto Precharge (*1, 4) L H L L BA, CA, A10 WRITE / WRITEA ILLEGAL (*1) L L H H BA, RA Active ILLEGAL (*1) L L H L BA, A10 / A10 PRE / PREA ILLEGAL (*1) / ILLEGAL L L L H X Refresh ILLEGAL READ L L L L Op-Code Mode-Add MRS / EMRS ILLEGAL H X X X X DESEL NOP (Continue Burst to end) L H H H X NOP NOP (Continue Burst to end) L H L H BA, CA, A10 READ / READA ILLEGAL (*1) L H L L BA, CA, A10 WRITE / WRITEA Terminate Burst, Latch CA, Begin new Write, Determine Auto-Precharge (*1, 4) L L H H BA, RA Active ILLEGAL (*1) L L H L BA, A10 / A10 PRE / PREA ILLEGAL (*1) / ILLEGAL L L L H X Refresh ILLEGAL WRITE L L L L Op-Code Mode-Add MRS / EMRS ILLEGAL

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 52/59 Current State CS RAS CAS WE Address Command Action H X X X X DESEL NOP (Continue Burst to end) L H H H X NOP NOP (Continue Burst to end) L H L H BA, CA, A10 READ / READA ILLEGAL (*1) L H L L BA, CA, A10 WRITE / WRITEA ILLEGAL (*1) L L H H BA, RA Active ILLEGAL (*1) L L H L BA, A10 / A10 PRE / PREA ILLEGAL (*1) / ILLEGAL L L L H X Refresh ILLEGAL READ with AUTO PRECHARGE L L L L Op-Code Mode-Add MRS / EMRS ILLEGAL H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H L H BA, CA, A10 READ / READA ILLEGAL (*1) L H L L BA, CA, A10 WRITE / WRITEA ILLEGAL (*1) L L H H BA, RA Active ILLEGAL (*1) L L H L BA, A10 PRE / PREA ILLEGAL (*1) / ILLEGAL L L L H X Refresh ILLEGAL WRITE with AUTO PRECHARGE L L L L Op-Code Mode-Add MRS / EMRS ILLEGAL H X X X X DESEL NOP (Idle after t RP) L H H H X NOP NOP (Idle after t RP) L H L X BA, CA, A10 READ / READA / WRITE / WRITEA ILLEGAL (*1) L L H H BA, RA Active ILLEGAL (*1) L L H L BA, A10 / A10 PRE / PREA NOP (Idle after t RP) L L L H X Refresh ILLEGAL PRE-CHARGIN G L L L L Op-Code Mode-Add MRS / EMRS ILLEGAL H X X X X DESEL NOP (Bank Active after t RCD) L H H H X NOP NOP (Bank Active after t RCD) L H L X BA, CA, A10 READ / READA / WRITE / WRITEA ILLEGAL (*1, 5) L L H H BA, RA Active ILLEGAL (*1) L L H L BA, A10 / A10 PRE / PREA ILLEGAL L L L H X Refresh ILLEGAL ROW ACTIVATING L L L L Op-Code Mode-Add MRS / EMRS ILLEGAL

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 53/59 Current State CS RAS CAS WE Address Command Action H X X X X DESEL NOP (Bank Active after t WR) L H H H X NOP NOP (Bank Active after t WR) L H L H BA, CA, A10 READ / READA ILLEGAL (*1, 6) L H L L BA, CA, A10 WRITE / WRITEA WRITE / WRITEA L L H H BA, RA Active ILLEGAL (*1) L L H L BA, A10 / A10 PRE / PREA ILLEGAL (*1) / ILLEGAL L L L H X Refresh ILLEGAL WRITE RECOVERING L L L L Op-Code Mode-Add MRS / EMRS ILLEGAL H X X X X DESEL NOP (Bank Active after t WR) L H H H X NOP NOP (Bank Active after t WR) L H L X BA, CA, A10 READ / READA / WRITE / WRITEA ILLEGAL (*1) L L H H BA, RA Active ILLEGAL (*1) L L H L BA, A10 / A10 PRE / PREA ILLEGAL (*1) / ILLEGAL L L L H X Refresh ILLEGAL WRITE RECOVERING with AUTO PRECHARGE L L L L Op-Code Mode-Add MRS / EMRS ILLEGAL H X X X X DESEL NOP (Idle after t RFC) L H H H X NOP NOP (Idle after t RFC) L H L X BA, CA, A10 READ / READA / WRITE / WRITEA ILLEGAL L L H H BA, RA Active ILLEGAL L L H L BA, A10 / A10 PRE / PREA ILLEGAL L L L H X Refresh ILLEGAL REFRESH L L L L Op-Code Mode-Add MRS / EMRS ILLEGAL H X X X X DESEL NOP (Idle after t MRD) L H H H X NOP NOP (Idle after t MRD) L H L X BA, CA, A10 READ / READA / WRITE / WRITEA ILLEGAL L L H H BA, RA Active ILLEGAL L L H L BA, A10 / A10 PRE / PREA ILLEGAL L L L H X Refresh ILLEGAL (Extended) MODE REGISTER SETTING L L L L Op-Code Mode-Add MRS / EMRS ILLEGAL H = High Level, L = Low level, X = Don’t Care BA = Bank Address, RA =Row Address, CA = Column Address, NOP = No Operation ILLEGAL = Device operation and / or data integrity are not guaranteed. Note : 1. This command may be issued for other bank s, depending on the state of the banks. 2. All banks must be in “IDLE”. 3. All AC timing specs must be met. 4. Only allowed at the boundary of 4 bits burst. Burst interruption at other timings is illegal. 5. Available in case t RCD is satisfied by AL setting. 6. Available in case t WTR is satisfied.

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 54/59 Simplified States Diagram CKEL = CKE LOW CKEH = CKE HIGH ACT = Activate WR(A) = Write (with Auto Precharge) RD(A) = Read (with Auto Precharge) PR(A) = Precharge (All) (E)MRS = (Extended) Mode Register Set SRF = Enter Self Refresh REF = Auto Refresh

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 55/59 PACKING DIMENSIONS 84-BALL FBGA (Window BGA) / VFBGA DDRII SDRAM ( 8x12.5x1.2 mm ) Symbol Dimension in mm Dimension in inch Min Norm Max Min Norm Max D1 6.40 BSC 0.252 BSC E1 11.20 BSC 0.441 BSC e 0.80 BSC 0.031 BSC Controlling dimension : Millimeter.

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 56/59 PACKING DIMENSIONS 84-BALL FBGA (Window BGA) DDRII SDRAM ( 8x12.5x1.0 mm ) Symbol Dimension in mm Dimension in inch Min Norm Max Min Norm Max D1 6.40 BSC 0.252 BSC E1 11.20 BSC 0.441 BSC e 0.80 BSC 0.031 BSC Controlling dimension : Millimeter.

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 57/59 PACKING DIMENSIONS 84-BALL VFBGA DDRII SDRAM ( 8x12.5x1.0 mm ) Symbol Dimension in mm Dimension in inch Min Norm Max Min Norm Max D1 6.40 BSC 0.252 BSC E1 11.20 BSC 0.441 BSC e 0.80 BSC 0.031 BSC Controlling dimension : Millimeter.

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 58/59

Revision History

1.0 2014.02.27 Original

ESMT M14D128168A (2M) Operation Temperature Condition (TC) -40°C~95°C Elite Semiconductor Memory Technology Inc. Publication Date : Feb. 2014 Revision : 1.0 59/59 Important Notice All rights reserved. No part of this document may be reproduc ed or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be acc urate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the product s or specification in this document without notice. The information contained herein is presen ted only as a guide or examples for the application of our products. No res ponsibility is assumed by ESMT for any infringement of patents, copyrights, or ot her intellectual propert y rights of third parties which may result from its use. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inhere ntly a certain rate of failure. To minimize risks associated with custom er's application, adeq uate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or caus e physical injury or property damage. If products described here are to be used for such kinds of applicat ion, purchaser must do its own quality assurance testing appropriate to such applications.

Product Information

M14D128168A specifications and overview.

Summary

Internal pipelined double-data-rate architecture; two data access per clock cycle

Description

Internal pipelined double-data-rate architecture; two data access per clock cycle

Source title M14D128168A Datasheet(PDF) - Elite Semiconductor Memory Technology Inc.

Related Parts

More parts from the same family.

Browse manufacturer