ADM1025 AD | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 16
Technical content
REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a ADM1025/ADM1025A* Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 Low-Cost PC Hardware Monitor ASIC FUNCTIONAL BLOCK DIAGRAM VALUE AND LIMIT REGISTERS MEASUREMENT STATUS REGISTERS OFFSET REGISTER CONFIGURATION REGISTER LIMIT COMPARATORS ADC 2.5V BANDGAP REFERENCEBANDGAP TEMPERATURE SENSOR VCCPIN 2.5VIN 3.3VIN 5VIN D–/NTI 100k/H9024 PULLUPS VDD VID0 VID1 VID2 VID3 12V IN/VID4 300k/H9024 ADD/RST/INT/NTO SDA SCL ADDRESS POINTER REGISTERINPUT ATTENUATORS AND ANALOG MULTIPLEXER POWER TO CHIP VID0–3 REGISTER VID4 REGISTER VCC GND SERIAL BUS INTERFACE ADM1025/ ADM1025A
FEATURES
Up to Eight Measurement Channels Five Inputs to Measure Supply Voltages VCC Monitored Internally External Temperature Measurement with Remote Diode On-Chip Temperature Sensor Five Digital Inputs for VID Bits Integrated 100 k/H9024 Pull-Ups on VID Pins ( ADM1025 Only) LDCM Support I 2C®-Compatible System Management Bus (SMBus) Programmable RESET Output Pin Programmable INT Output Pin Configurable Offset for Internal/External Channel Shutdown Mode to Minimize Power Consumption Limit Comparison of all Monitored Values
APPLICATIONS
Network Servers and Personal Computers Microprocessor-Based Office Equipment Test Equipment and Measuring Instruments *Patent Pending. I2C is a registered trademark of Philips Corporation. PRODUCT DESCRIPTION The ADM1025/ADM1025A is a complete system hardware monitor for microprocessor-based systems, providing measure- ment and limit comparison of various system parameters. Five voltage measurement inputs are provided, for monitoring 2.5 V,
3.3 V, 5 V and 12 V power supplies and the processor core
voltage. The ADM1025/ADM1025A can monitor a sixth power supply voltage by measuring its own V CC. One input (two pins) is dedicated to a remote temperature-sensing diode, and an on-chip temperature sensor allows ambient temperature to be m oni- tored. The ADM1025A has open-drain VID inputs while the ADM1025 has on-chip 100 k Ω pull-ups on the VID inputs. Measured values and in/out of limit status can be read out via an I2C-compatible serial System Management Bus. The device can be controlled and configured over the same serial bus. The device also has a programmable INT output to indicate under- voltage, overvoltage and over-temperature conditions. The ADM1025/ADM1025A’s 3.0 V to 5.5 V supply voltage range, low supply current, and I 2C-comp atible interface make it ideal for a wide range of applications. These include hardware monitoring and protection applications in personal computers, electronic test equipment, and office electronics.
REV. A–2– ADM1025/ADM1025A–SPECIFICATIONS(TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.) Parameter Min Typ Max Unit Test Conditions/Comments POWER SUPPLY Supply Voltage, V CC 3.0 3.30 5.5 V (Note 1) Supply Current, I CC 1.4 2.5 mA Interface Inactive, ADC Active 32 500 µA Standby Mode (Note 2) TEMPERATURE-TO-DIGITAL CONVERTER Internal Sensor Accuracy ±3 °C Resolution 1 °C External Diode Sensor Accuracy ±5 °C ±3 °C6 0 °C ≤ TA ≤ 100°C; VCC = 3.3 V Resolution 1 °C Remote Sensor Source Current 180 µA High Level 11 µA Low Level ANALOG-TO-DIGITAL CONVERTER (INCLUDING MUX AND ATTENUATORS) Total Unadjusted Error, TUE ±2 % (Note 3) Differential Nonlinearity, DNL ±1 LSB Power Supply Sensitivity ±1 %/V Conversion Time (Analog Input or Internal Temperature) 11.6 ms (Note 4) Conversion Time (External Temperature) 34.8 ms (Note 4) Input Resistance (2.5 V, 3.3 V, 5 V, 12 V, V CCPIN) 100 140 250 k Ω OPEN-DRAIN DIGITAL OUTPUT ADD/RST/INT/NTO Output Low Voltage, V OL 0.4 V I OUT = –6.0 mA; VCC = 3 V High Level Output Leakage Current, I OH 0.1 1 µAV OUT = VCC; VCC = 3 V RST Pulsewidth 20 45 ms OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA) Output Low Voltage, V OL 0.4 V I OUT = –6.0 mA; VCC = 3 V High Level Output Leakage Current, I OH 0.1 1 µAV OUT = VCC SERIAL BUS DIGITAL INPUTS (SCL, SDA) Input High Voltage, V IH 2.1 V Input Low Voltage, V IL 0.8 V Hysteresis 500 mV DIGITAL INPUT LOGIC LEVELS (ADD, VID0–VID4, NTI) 5 VID0–3 Input Resistance 100 k Ω ADM1025 Only VID4 Input Resistance 300 k Ω ADM1025 Only 100 k Ω ADM1025A Input High Voltage, V IH 6 2.1 V Input Low Voltage, V IL 6 0.8 V DIGITAL INPUT LEAKAGE CURRENT Input High Current, I IH –1 µAV IN = VCC Input Low Current, I IL 1 µAV IN = 0 Input Capacitance, C IN 5p F SERIAL BUS TIMING Clock Frequency, f SCLK 400 kHz See Figure 1 Glitch Immunity, t SW 50 ns See Figure 1 Bus Free Time, t BUF 1.3 µs See Figure 1 Start Setup Time, t SU:STA 600 ns See Figure 1 Start Hold Time, t HD:STA 600 ns See Figure 1 Stop Condition Setup Time t SU:STO 600 ns See Figure 1 SCL Low Time, t LOW 1.3 µs See Figure 1 SCL High Time, t HIGH 0.6 µs See Figure 1 SCL, SDA Rise Time, t R 300 ns See Figure 1 SCL, SDA Fall Time, t F 300 ns See Figure 1 Data Setup Time, t SU:DAT 100 ns See Figure 1 Data Hold Time, t HD:DAT 300 ns See Figure 1 NOTES 1All voltages are measured with respect to GND, unless otherwise specified. 2Typicals are at T A = 25°C and represent most likely parametric norm. Shutdown current typ is measured with V CC = 3.3 V. 3TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC, multiplexer and on-chip input attenuators, including an external series input protection resistor value between zero and 1 k Ω. 4Total monitoring cycle time is nominally 114.4 ms. Monitoring Cycle consists of 6 Voltage + 1 Internal Temperature + 1 External Temperature readings. 5ADD is a three-state input that may be pulled high, low or left open-circuit. 6Timing specifications are tested at logic levels of V IL = 0.8 V for a falling edge and V IH = 2.2 V for a rising edge. Specifications subject to change without notice.
Figure 1. Diagram for Serial Bus Timing conditions for extended periods may affect device reliability.
REV. A ADM1025/ADM1025A –4– PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 SDA Digital I/O. Serial bus bidirectional data. Open-drain output. 2 SCL Digital Input. Serial bus clock. 3 GND System Ground. CC Power. Can be powered by +3.3 V standby power if monitoring in low power states is required. This pin also serves as the analog input to monitor V CC. 5 VID0 Digital Input. Core voltage ID readouts from the processor. This value is read into the VID0–VID3 Status Register. It has an on-chip 100 k Ω pull-up resistor (ADM1025 only). 6 VID1 Digital Input. Core voltage ID readouts from the processor. This value is read into the VID0–VID3 Status Register. It has an on-chip 100 k Ω pull-up resistor (ADM1025 only). 7 VID2 Digital Input. Core voltage ID readouts from the processor. This value is read into the VID0–VID3 Status Register. It has an on-chip 100 k Ω pull-up resistor (ADM1025 only). 8 VID3 Digital Input. Core voltage ID readouts from the processor. This value is read into the VID0–VID3 Status Register. It has an on-chip 100 k Ω pull-up resistor (ADM1025 only). 9 D–/NTI Analog/Digital Input. Connected to cathode of external temperature sensing diode. If held high at power-up, initiates NAND tree test mode. 10 D+ Analog Input. Connected to anode of external temperature sensing diode. 11 12 V IN/VID4 Programmable Analog/Digital Input. Defaults to 12 V IN analog input at power-up, but may be pro- grammed as VID4 Core Voltage ID readout from the processor. This value is read into the VID4 Status Register. In analog 12 V IN mode it has an on-chip voltage attenuator. In VID4 mode it has an on-chip 300 kΩ pull-up resistor. 12 5 V IN Analog Input. Monitors 5 V supply. 13 3.3 V IN Analog Input. Monitors 3.3 V supply. 14 2.5 V IN Analog Input. Monitors 2.5 V supply. 15 V CCPIN Analog Input. Monitors processor core voltage (0 V to 3.0 V). 16 ADD/ RST/INT/NTO Programmable Digital I/O. The lowest order programmable bit of the SMBus Address, sampled on SMB activity as a three-state input. Can also be configured to give a minimum 20 ms low reset output pulse. Alternatively, can be programmed as an interrupt output for temperature/voltage interrupts. Functions as the output of the NAND tree in NAND tree test mode. PIN CONFIGURATION TOP VIEW (Not to Scale) SDA ADD/ RST/INT/NTO ADM1025/ ADM1025A SCL VCCPIN GND 2.5VIN VCC 3.3VIN VID0 5VIN VID1 12VIN/VID4 VID2 D+ VID3 D–/NTI
Figure 8. Standby Current vs. Temperature nicates with the system via a serial System Management Bus. ADM1025A are performed over the serial bus. as a digital input for Bit 4 of the processor voltage ID code. monitors the voltage on this pin. sensing transistor may be connected. serial bus to flag out of limit conditions. up default), the VID4 bit in the VID4 register will default to 0. are described in more detail later. the function of each register is given in Tables V to XV. Configuration Register:Provides control and configuration. address, which is written to the Address Pointer Register. processor can read from these registers. ters, along with their limit values. LSBs are determined by the logical states of Pin 16 at power-up.
REV. A ADM1025/ADM1025A –7– If ADD is left open-circuit the default address will be 0101110. ADD is sampled only after power-up, so any changes made will have no effect, unless power is cycled. The facility to make hardwired changes to A1 and A0 allows the user to avoid conflicts with other devices sharing the same serial bus if, for example, more than one ADM1025/ADM 1025A is used in a system. However, as previously mentioned, the ADD pin may also function as a reset output or interrupt output. Use of these functions may restrict the addresses that can be set. See the sections on RST and INT for further information. The serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, defined as a high-to-low transition on the serial data line SDA while the serial clock line SCL remains high. This indicates that an address/data stream will follow. All slave peripherals connected to the serial bus respond to the START condition, and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/ W bit, which deter- mines the direction of the data transfer, i.e., whether data will be written to or read from the slave device. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the Acknowl- edge Bit. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master will write to the slave device. If the R/W bit is a 1, the master will read from the slave device. 2. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an Acknowledge Bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low-to-high transition when the clock is high may be interpreted as a STOP signal. The number of data bytes that can be transmitted over the serial bus in a single READ or WRITE operation is limited only by what the master and slave devices can handle. 3. When all data bytes have been read or written, stop condi- tions are established. In WRITE mode, the master will pull the data line high during the 10th clock pulse to assert a STOP condition. In READ mode, the master device will override the acknowledge bit by pulling the data line high during the low period before the 9th clock pulse. This is known as No Acknowledge. The master will then take the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a STOP condition. Any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. In the case of the ADM1025/ADM1025A, write operations contain either one or two bytes, and read operations contain one byte, and perform the following functions: To write data to one of the device data registers or read data from it, the Address Pointer Register must be set so that the correct data register is addressed, data can then be written into that register or read from it. The first byte of a write operation always contains an address that is stored in the Address Pointer Register. If data is to be written to the device, the write opera- tion contains a second data byte that is written to the register selected by the address pointer register. This is illustrated in Figure 9a. The device address is sent over the bus followed by R/ W set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the Address Pointer Register. The second data byte is the data to be written to the internal data register. R/W0 SCL SDA 1 0 1 1 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY ADM1025 START BY MASTER 19 1 ACK. BY ADM1025 D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY ADM1025 STOP BY MASTER 1 9 SCL (CONTINUED) SDA (CONTINUED) FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 ADDRESS POINTER REGISTER BYTE FRAME 3 DATA BYTE Figure 9a. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
- If the ADM1025/ADM1025A’s Address Pointer Regi ster
written to the register. This is shown in Figure 9b. the data register. This is shown in Figure 9c.
- If the Address Pointer Register is known to be already at the
Register, so Figure 9b can be omitted.
- Although it is possible to read a data byte from a data register
write is always written to the Address Pointer Register.
- In Figures 9a to 9c, the serial bus address is shown as the
- In addition to supporting the Send Byte and Receive Byte
tions Rev. 1.1 for more information).
- If Reset or Interrupt functionality is required, address pin
RST/INT/NTO pin permanently low. inputs, five for voltage and one (two pins) for temperature.
3.3 V, 5 V, 12 V and the processor core voltage V
input takes nominally 34.8 ms.
- Each input circuit consists of an input protection diode, an
which gives the input immunity to high frequency noise. Figure 10. Structure of Analog Inputs
REV. A ADM1025/ADM1025A –9– Table II. A/D Output Code vs. V IN Input Voltage A/D Output 12 VIN 5 VIN VCC/3.3 VIN 2.5 VIN VCCPIN Decimal Binary
REV. A ADM1025/ADM1025A –11– 4. Try to minimize the number of copper/solder joints, which can cause thermocouple effects. Where copper/solder joints are used, make sure that they are in both the D+ and D– path and at the same temperature. Thermocouple effects should not be a major problem as 1 °C corresponds to about 240 µV, and thermocouple voltages are about 3 µV/ oC of temperature difference. Unless there are two thermocouples with a big temperature differential between them, thermocouple voltages should be much less than 200 µV. 5. Place 0.1 µF bypass and 1 nF input filter capacitors close to the ADM1025/ADM1025A. 6. If the distance to the remote sensor is more than 8 inches, the use of twisted pair cable is recommended. This will work up to about 6 to 12 feet. 7. For really long distances (up to 100 feet) use shielded twisted pair such as Belden #8451 microphone cable. Connect the twisted pair to D+ and D– and the shield to GND close to the ADM1025/ADM1025A. Leave the remote end of the shield unconnected to avoid ground loops. Because the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect the measurement. When using long cables, the filter capacitor may be reduced or removed. Cable resistance can also introduce errors. 1 Ω series resistance introduces about 0.5 °C error. LIMIT VALUES High and low limit values for each measurement channel are stored in the appropriate limit registers. As each channel is measured, the measured value is stored and compared with the programmed limit. STATUS REGISTERS The results of limit comparisons are stored in Status Registers 1 and 2. The Status Register bit for a particular measurement channel reflects the status of the last measurement and limit comparison on that channel. If a measurement is within limits the corresponding Status Register bit will be cleared to “0.” If the measurement is out of limits the corresponding status regis- ter bit will be set to “1.” The state of the various measurement channels may be polled by reading the Status Registers over the serial bus. Reading the Status Registers does not affect their contents. Out-of-limit temperature/voltage events may also be used to generate an interrupt, so that remedial action such as turning on a cooling fan may be taken immediately. This is described in the section on RST and INT. MONITORING CYCLE TIME The monitoring cycle begins when a one is written to the Start Bit (Bit 0) of the Configuration Register. The ADC measures each analog input in turn and as each measurement is com- pleted the result is automatically stored in the appropriate value register. This “round-robin” monitoring cycle continues until it is disabled by writing a 0 to Bit 0 of the Configuration Register. As the ADC will normally be left to free-run in this manner, the time taken to monitor all the analog inputs will normally not be of interest, as the most recently measured value of any input can be read out at any time. INPUT SAFETY Scaling of the analog inputs is performed on-chip, so external attenuators are normally not required. However, since the power supply voltages will appear directly at the pins, its is advisable to add small external resistors in series with the supply traces to the chip to prevent damaging the traces or power supplies should an accidental short such as a probe connect two power sup- plies together. As the resistors will form part of the input attenuators, they will affect the accuracy of the analog measurement if their value is too high. The analog input channels are calibrated assuming an external series resistor of 500 Ω, and the accuracy will remain within specification for any value from zero to 1 k Ω, so a stan- dard 510 Ω resistor is suitable. The worst such accident would be connecting 0 V to 12 V—a total of 12 V difference, with the series resistors this would draw a maximum current of approximately 12 mA. LAYOUT AND GROUNDING Analog inputs will provide best accuracy when referred to a clean ground. A separate, low impedance ground plane for analog ground, which provides a ground point for the voltage dividers and analog components, will provide best performance but is not mandatory. The power supply bypass, the parallel combination of 10 µF (electrolytic or tantalum) and 0.1 µF (ceramic) bypass capacitors connected between Pin 9 and ground, should also be located as close as possible to the ADM1025/ADM1025A. RST/INT OUTPUT As previously mentioned, Pin 16 is a multifunction pin. Its state after power-on is latched to set the lowest two bits of the serial bus address. During NAND tree board-level connectivity testing it functions as the output of the NAND tree. It may also be used as a reset output, or as an interrupt output for out-of-limit tem- perature/voltage events. Pin 16 is programmed as a reset output by clearing bit 0 of the Test Register and setting Bit 7 of the VID Register. A low going, 20 ms, reset output pulse can then be generated by setting Bit 4 of the Configuration Register. If Bit 7 of the VID Register is cleared, Pin 16 can be programmed as an interrupt output for out-of-limit temperature/voltage events (INT). Desired interrupt operation is achieved by changing the values of Bits 1 and 0 of the Test Register as shown in Table IV. Note, however, that Bits 2 to 7 of the Test Register must be zeros (not don’t cares). If, for example, INT is programmed for thermal and voltage interrupts, then if any temperature or volt- age measurement goes outside its respective high or low limit, the INT output will go low. It will remain low until Status Reg- ister 1 is read, when it will be cleared. If the temperature or voltage remains out of limit, INT will be reasserted on the next monitoring cycle. INT can also be cleared by issuing an Alert Response Address Call.
REV. A ADM1025/ADM1025A –13– USING THE ADM1025/ADM1025A Power-On RESET When power is first applied, the ADM1025/ADM1025A per- forms a “power- on reset” on several of its registers. Registers whose power-on values are not shown have power-on conditions that are indeterminate. Value and limit registers are reset to 00h on power-up. The ADC is inactive. In most applications, usu- ally the first action after power-on would be to write limits into the Limit Registers. Power-on reset clears or initializes the following registers (the initialized values are shown in Table VI): – Configuration Register – Status Registers #1 and #2 – VID0-3 Register – VID4 Register – Test Register INITIALIZATION Configuration Register Initialization performs a similar, but not identical, function to power-on reset. Configuration Register Initialization is accomplished by setting Bit 7 of the Configuration Register high. This bit automatically clears after being set. USING THE CONFIGURATION REGISTER Control of the ADM1025/ADM1025A is provided through the configuration register. The Configuration Register is used to start and stop the ADM1025/ADM1025A, programming the operating modes of Pins 11 and 16, and provide the initializa- tion function described above. Bit 0 of the Configuration Register controls the monitoring loop of the ADM1025/ADM1025A. Setting Bit 0 low stops the moni- toring loop and puts the ADM1025/ADM1025A into a low power mode thereby reducing power consumption. Serial bus commu- nication is still possible with any register in the ADM1025/ ADM1025A while in low power mode. Setting Bit 0 high starts the monitoring loop. Bit 4 of the Configuration Register causes a low going 20 ms (typ) pulse at the RST pin (Pin 16) when set. This bit is self-clearing. Bit 5 of the Configuration Register selects the operating mode of pin 11 between the default of 12 V analog input (Bit 5 = 0) and VID4 (Bit 5 = 1). Bit 7 of the Configuration Register is used to start a Configura- tion Register Initialization when it is set to 1. USING THE OFFSET REGISTER This register contains a two’s complement value that is added (or subtracted if the number is negative) to either the internal or external temperature reading. Note that the default value in the offset register is zero, so zero is always added to the temperature reading. The offset register is configured for the external tem- perature channel by default. It may be switched to the internal channel by setting Bit 0 of the Test Register to 1, setting Bit 6 of the VID Register to 1, and clearing Bit 7 of the VID Register. STARTING CONVERSION The monitoring function of the ADM1025/ADM1025A is started by writing to the Configuration Register and setting Start (Bit 0), high. Limit values should be written into the Limit Registers before starting the ADC to avoid spurious out-of-limit condi- tions. The time taken to complete the analog measurements depends on how they are configured, as described elsewhere. Once the measurements have been completed, the results can be read from the Value Registers at any time. REDUCED POWER AND SHUTDOWN MODE The ADM1025/ADM1025A can be placed in a low power mode by setting Bit 0 of the Configuration Register to 0. This disables the internal ADC. Full shutdown mode may then be achieved by setting Bit 7 of the VID Register to 1 AND Bit 0 of the Test Register to 1. This turns off power to all analog circuits and stops the monitoring cycle, if running, but it does not affect the condition of any of the registers. The device will return to its previous state when these bits are reset to zero.
5 V OPERATION
The ADM1025/ADM1025A may be operated with V CC con- nected to any supply voltage between 3.0 V and 5.5 V, but it should be noted that the device has been optimized for 3.3 V operation. In particular, the internal voltage divider used to measure the supply voltage is optimized for 3.3 V. Powering the device from 5 V will cause the V CC Reading Register (Register 25h) to overrange. In this case, the 5 V measurement should be read from the 5 V Reading Register (Register 23h), instead of the VCC Reading Register. Note also that when 12 V IN/VID4 pin is programmed to read VID4, due to its internal voltage divider, it will only read VIH = 2.1 V on 12 VIN/VID4 pin as logic high if device is being powered from 3.3 V supply. REGISTERS Table V. Address POINTER Register Bit Name R/ W Description 7–0 Address Pointer Write Address of ADM1025/ ADM1025A Registers. See the tables below for detail. Table VI. List of Registers Address Power On Register A7–A0 Value of Name in Hex Registers: <7:0> Configuration Register 40h 0000 1000 Status Register 1 41h 0000 0000 Status Register 2 42h 0000 0000 VID Register 47h < 7:4> = 0000, <3:0> = VID3–VID0 VID4 Register 49h <0> = VID4; Default = 1000 000 (VID4) Value and Limit Registers 15–3Dh Company ID 3Eh 0100 0001 Stepping 3Fh 0010 (Bits 3:0 Version Number)
REV. A ADM1025/ADM1025A –14– Table VII. Register 40H – Configuration Register Bit Name R/ W Description
0 START Read/Write Logic 1 enables start-up of
monitor ASIC, Logic 0 places the ASIC in standby mode. At start-up, limit checking func- tions and scanning begins. Note, all HIGH and LOW LIMITS should be set into the ADM1025/ ADM1025A prior to turning on this bit. (Power-up Default = 0)
1 Reserved Read
2 Reserved Read
3 Reserved Read
4 RESET Read/Write Setting this bit generates a
minimum 20 ms low pulse on Pin 16, if the function is enabled. 5 +12/VID4 Read/Write Selects whether Pin 11 acts Select as a 12 V Analog Input monitor- ing pin, or as a VID[4] input. This pin defaults to the 12 V Analog Input. (Default = 0)
6 Reserved Read
7 Initialization Read/Write Logic 1 restores power-up
default values to the Configu- ration Register and Status Registers. This bit automati- cally clears itself and the power- on default is zero. Table VIII. Register 41H – STATUS Register 1 (Power-On Default <7:0> = 00h) Bit Name R/ W Description 0 +2.5 V_Error Read Only A one indicates a High or Low limit has been exceeded. 1V CCP_Error Read Only A one indicates a High or Low limit has been exceeded. 2 +3.3 V_Error Read Only A one indicates a High or Low limit has been exceeded. 3 +5 V_Error Read Only A one indicates a High or Low limit has been exceeded.
4 Local Temp Read Only A one indicates that a
exceeded.
5 Remote Temp Read Only A one indicates a High
exceeded.
6 Reserved
7 Reserved
Table IX. Register 42H – Status Register 2 (Power-On Default <7:0> = 00h) Bit Name R/ W Description 0 +12 V_Error Read Only A one indicates a High or Low limit has been exceeded. CC_Error Read Only A one indicates a High or Low limit has been exceeded.
2 Reserved Read Only Undefined
3 Reserved Read Only Undefined
4 Reserved Read Only Undefined
5 Reserved Read Only Undefined
6 Remote Diode Read Only A one indicates either a
Fault short or open circuited fault on the remote ther- mal diode inputs.
7 Reserved Read Only Undefined
Table X. Register 47h – VID REGISTER (Power-On Default = 0000 (VID[3:0])) Bit Name R/ W Description 0–3 VID[3:0] Read Only The VID[3:0] in puts from Pentium/PRO power supplies to indicate the operating 4–5 Reserved Read Only Undefined
6 Offset Config Read/Write Configures offset register to
external channel. If Bit 0 of Test Register = 1, and Bit 7 of VID Register = 0, then setting this bit to 1 config- ures the Offset Register to the internal temperature chan- nel. Clearing this bit config- ures the Offset Register to the external temperature chan- nel. (Default = 0)
7 RST ENABLE Read/Write When set to 1, enables the
RST output function on Pin 16. This bit defaults to 0 on power-up. (RST Disabled.) Table XI. Register 49h – VID4 Register (Power-On Default = 1000 000(VID4)) Bit Name R/ W Description
0 VID4 Read VID4 Input (If Selected)
(Defaults to 0) 1–7 Reserved Read
REV. A ADM1025/ADM1025A –15– Table XIV. Register 3Eh – Company ID Value (Bits 7:0) R/ W Description 0100 0001 Read Only This location contains the company identification number which may be used by software to determine the manufacturer’s device. This register is read only. Table XV. Register 3Fh – Stepping Value (Bits 7:0) R/ W Description 0010 [Version] Read Only Stepping ID Number and Version Table XVI. NAND Tree Test Vectors Vector ADD/ RST/ No. SDA SCL VID0 VID1 VID2 VID3 INT/NTO 10 0 0 0 0 0 1 20 0 0 0 0 1 0 30 0 0 0 1 1 1 40 0 0 1 1 1 0 50 0 1 1 1 1 1 60 1 1 1 1 1 0 71 1 1 1 1 1 1 Table XII. Registers 15h–3Dh – Value and Limit Registers Address R/ W Description 15h Read/Write Manufacturers Test Register 1Fh Read/Write Offset Register 20h Read Only 2.5 V Reading 21h Read Only V CCP Reading 22h Read Only 3.3 V Reading 23h Read Only 5 V Reading 24h Read Only 12 V Reading 25h Read Only V CC Reading 26h Read Only Remote Diode Temperature Reading 27h Read Only Local Temperature Reading 2Bh Read/Write 2.5 V High Limit 2Ch Read/Write 2.5 V Low Limit 2Dh Read/Write V CCP High Limit 2Eh Read/Write V CCP Low Limit 2Fh Read/Write 3.3 V High Limit 30h Read/Write 3.3 V Low Limit 31h Read/Write 5 V High Limit 32h Read/Write 5 V Low Limit 33h Read/Write 12 V High Limit 34h Read/Write 12 V Low Limit 35h Read/Write V CC High Limit 36h Read/Write V CC Low Limit 37h Read/Write Remote Temperature High Limit 38h Read/Write Remote Temperature Low Limit 39h Read/Write Local Temperature High Limit 3Ah Read/Write Local Temperature Low Limit NOTE For the high limits of the voltages, the device is doing a greater-than compari- son. For the low limits, however, it is doing a less-than or equal comparison. Table XIII. Register 15h – Manufacturers Test Register Bit Name R/ W Description
0 Read/Write Used to select RST or INT
functions. Refer to RST/INT Input section.
1 Read/Write Used to select RST or INT
functions. Refer to RST/INT Input section. 2–7 Reserved Read/Write Reserved. Only values written to these bits should be zeros.
REV. A ADM1025/ADM1025A –16– PRINTED IN U.S.A. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead QSOP (RQ-16) 16 9 0.197 (5.00) 0.189 (4.80) 0.244 (6.20) 0.228 (5.79) PIN 1 0.157 (3.99) 0.150 (3.81) SEATING PLANE 0.010 (0.25) 0.004 (0.10) 0.012 (0.30) 0.008 (0.20) 0.025 (0.64) BSC 0.059 (1.50) MAX 0.069 (1.75) 0.053 (1.35) 0.010 (0.20) 0.007 (0.18) 0.050 (1.27) 0.016 (0.41) 8/H11543 0/H11543 REF: JEDEC 0.150" SSOP – DRAWING NUMBER MO-137