LTC2411 LINER | Alldatasheet
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2411/LTC2411-1 are 2.7V to 5.5V micropower 24-bit differential DS analog-to-digital converters with an integrated oscillator, 2ppm INL and 0.29ppm RMS noise. They use delta-sigma technology and provide single cycle settling time for multiplexed applications. Through a single pin, the LTC2411 can be configured for better than 110dB differential mode rejection at 50Hz or 60Hz – 2%, and the LTC2411-1 can provide better than 87dB input differential mode rejection over the range of 49Hz to 61.2Hz, or they can be driven by an external oscillator for a user-defined rejection frequency. The LTC2411 and LTC2411-1 are identical when driven by an external oscillator. The internal oscillator requires no external frequency setting components. The converters accept any external differential reference voltage from 0.1V to V CC for flexible ratiometric and remote sensing measurement configurations. The full- scale differential input range is from – 0.5VREF to 0.5VREF. The reference common mode voltage, V REFCM, and the input common mode voltage, V INCM, may be indepen- dently set anywhere within the GND to V CC range of the LTC2411/LTC2411-1. The DC common mode input rejec- tion is better than 140dB. The LTC2411/LTC2411-1 communicate through a flexible 3-wire digital interface that is compatible with SPI and MICROWIRE TM protocols. n Direct Sensor Digitizer n Weight Scales n Direct Temperature Measurement n Gas Analyzers n Strain Gauge Transducers n Instrumentation n Data Acquisition n Industrial Process Control n 6-Digit DVMs , LTC and LT are registered trademarks of Linear Technology Corporation. n 24-Bit ADC in an MS10 Package n Low Supply Current (200mA in Conversion Mode and 4mA in Autosleep Mode) n Differential Input and Differential Reference with GND to VCC Common Mode Range n 2ppm INL, No Missing Codes n 4ppm Full-Scale Error and 1ppm Offset n 0.29ppm Noise n No Latency: Digital Filter Settles in a Single Cycle. Each Conversion Is Accurate, Even After an Input Step n Single Supply 2.7V to 5.5V Operation n Internal Oscillator—No External Components Required n 110dB Min, Pin Selectable 50Hz/60Hz Notch Filter (LTC2411) n Simultaneous 50Hz/60Hz Rejection (LTC2411-1) 24-Bit No Latency DS TM ADC with Differential Input and Reference in MSOP No Latency DS is a trademark of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. DESCRIPTIO UFEATURES APPLICATIO SU TYPICAL APPLICATIO U VCC FO REF+ REF– SCK IN+ IN– SDO GND CS 11 0 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE –0.5VREF TO 0.5VREF = INTERNAL OSC/50Hz REJECTION (LTC2411) = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION (LTC2411) = SIMULTANEOUS 50Hz/60Hz REJECTION (LTC2411-1) 3-WIRE SPI INTERFACE 1µF 2.7V TO 5.5V LTC2411/ LTC2411-1
2411 TA01
REF– VCC GND F O IN– 1µF SCK 3-WIRE SPI INTERFACE SDO
2411 TA02
100Ω TO 10kΩ
(Notes 1, 2) Analog Input Pins Voltage Reference Input Pins Voltage CC + 0.3V) Operating Temperature Range TJMAX = 125°C, qJA = 120°C/W LTC2411CMS LTC2411IMS LTC2411-1CMS LTC2411-1IMS PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes) 0.1V £ VREF £ VCC, – 0.5 • VREF £ VIN £ 0.5 • VREF (Note 5) l 24 Bits Integral Nonlinearity 4.5V £ VCC £ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V (Note 6) 1 ppm of V REF 5V £ VCC £ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V (Note 6) l 2 14 ppm of V REF REF+ = 2.5V, REF– = GND, VINCM = 1.25V (Note 6) 6 ppm of V REF Offset Error 2.5V £ REF+ £ VCC, REF– = GND, l 52 0 mV GND £ IN+ = IN– £ VCC (Note 14) Offset Error Drift 2.5V £ REF+ £ VCC, REF– = GND, 20 nV/ °C GND £ IN+ = IN– £ VCC Positive Full-Scale Error 2.5V £ REF+ £ VCC, REF– = GND, l 4 12 ppm of V REF IN+ = 0.75REF+, IN– = 0.25 • REF+ Positive Full-Scale Error Drift 2.5V £ REF+ £ VCC, REF– = GND, 0.04 ppm of V REF/°C IN+ = 0.75REF+, IN– = 0.25 • REF+ Negative Full-Scale Error 2.5V £ REF+ £ VCC, REF– = GND, l 4 12 ppm of V REF IN+ = 0.25 • REF+, IN– = 0.75 • REF+ Negative Full-Scale Error Drift 2.5V £ REF+ £ VCC, REF– = GND, 0.04 ppm of V REF/°C IN+ = 0.25 • REF+, IN– = 0.75 • REF+ Total Unadjusted Error 4.5V £ VCC £ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V 3 ppm of V REF 5V £ VCC £ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V 3 ppm of V REF REF+ = 2.5V, REF– = GND, VINCM = 1.25V 6 ppm of V REF Output Noise 5V £ VCC £ 5.5V, REF+ = 5V, VREF – = GND, 1.45 mVRMS GND £ IN– = IN+ £ 5V, (Note 13) The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) MS10 PART MARKING ABSOLUTE AXI U RATI GSW WW U PACKAGE/ORDER I FOR ATIOUU W V CC REF+ REF– IN+ IN– F O SCK SDO CS GND TOP VIEW MS10 PACKAGE 10-LEAD PLASTIC MSOP
ELECTRICAL CHARACTERISTICS
Consult LTC Marketing for parts specified with wider operating temperature ranges.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IN+ Absolute/Common Mode IN+ Voltage l GND – 0.3V V CC + 0.3V V IN– Absolute/Common Mode IN– Voltage l GND – 0.3V V CC + 0.3V V VIN Input Differential Voltage Range l –V REF/2 V REF/2 V (IN+ – IN–) REF+ Absolute/Common Mode REF+ Voltage l 0.1 V CC V REF– Absolute/Common Mode REF– Voltage l GND V CC – 0.1V V VREF Reference Differential Voltage Range l 0.1 V CC V (REF+ – REF–) CS (IN+)I N + Sampling Capacitance 6 pF CS (IN–)I N – Sampling Capacitance 6 pF CS (REF+)R E F + Sampling Capacitance 6 pF CS (REF–)R E F – Sampling Capacitance 6 pF IDC_LEAK (IN+)I N + DC Leakage Current CS = V CC = 5.5V, IN+ = GND l –10 1 10 nA IDC_LEAK (IN–)I N – DC Leakage Current CS = V CC = 5.5V, IN– = GND l –10 1 10 nA IDC_LEAK (REF+)R E F + DC Leakage Current CS = V CC = 5.5V, REF+ = 5V l –10 1 10 nA IDC_LEAK (REF–)R E F – DC Leakage Current CS = V CC = 5.5V, REF– = GND l –10 1 10 nA The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) PARAMETER CONDITIONS MIN TYP MAX UNITS Input Common Mode Rejection DC 2.5V £ REF+ £ VCC, REF– = GND, l 130 140 dB GND £ IN– = IN+ £ 5V Input Common Mode Rejection 2.5V £ REF+ £ VCC, REF– = GND, l 140 dB 60Hz – 2% (LTC2411) GND £ IN– = IN+ £ 5V, (Note 7) Input Common Mode Rejection 2.5V £ REF+ £ VCC, REF– = GND, l 140 dB 50Hz – 2% (LTC2411) GND £ IN– = IN+ £ 5V, (Note 8) Input Common Mode Rejection 2.5V < REF + < VCC, REF– = GND, l 140 dB 49Hz to 61.2Hz (LTC2411-1) GND < IN – = IN+ < VCC (Note 15) Input Normal Mode Rejection (Note 7) l 110 140 dB 60Hz – 2% (LTC2411) Input Normal Mode Rejection (Note 8) l 110 140 dB 50Hz – 2% (LTC2411) Input Normal Mode Rejection (Note 15) l 87 dB 49Hz to 61.2Hz (LTC2411-1) Reference Common Mode 2.5V £ REF+ £ VCC, GND £ REF– £ 2.5V, l 130 140 dB Rejection DC V REF = 2.5V, IN– = IN+ = GND Power Supply Rejection, DC REF + = 2.5V, REF– = GND, IN– = IN+ = GND 110 dB Power Supply Rejection, 60Hz –2% REF + = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 7) 120 dB (LTC2411) Power Supply Rejection, 50Hz –2% REF + = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 8) 120 dB (LTC2411) Power Supply Rejection, REF + = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 15) 120 dB 49Hz to 61.2Hz (LTC2411-1) The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) CO VERTER CHARACTERISTICSU A ALOG I PUT A D REFERE CEU U U U
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC Supply Voltage l 2.7 5.5 V ICC Supply Current Conversion Mode CS = 0V (Note 12) l 200 300 mA Sleep Mode CS = V CC (Note 12) l 41 0 mA Sleep Mode CS = V CC, 2.7V £ VCC £ 3.3V (Note 12) 2 mA The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIH High Level Input Voltage 2.7V £ VCC £ 5.5V l 2.5 V CS, FO 2.7V £ VCC £ 3.3V 2.0 V VIL Low Level Input Voltage 4.5V £ VCC £ 5.5V l 0.8 V CS, FO 2.7V £ VCC £ 5.5V 0.6 V VIH High Level Input Voltage 2.7V £ VCC £ 5.5V (Note 9) l 2.5 V SCK 2.7V £ VCC £ 3.3V (Note 9) 2.0 V VIL Low Level Input Voltage 4.5V £ VCC £ 5.5V (Note 9) l 0.8 V SCK 2.7V £ VCC £ 5.5V (Note 9) 0.6 V IIN Digital Input Current 0V £ VIN £ VCC l –10 10 mA CS, FO IIN Digital Input Current 0V £ VIN £ VCC (Note 9) l –10 10 mA SCK CIN Digital Input Capacitance 10 pF CS, FO CIN Digital Input Capacitance (Note 9) 10 pF SCK VOH High Level Output Voltage I O = –800 mA l VCC – 0.5V V SDO VOL Low Level Output Voltage I O = 1.6mA l 0.4 V SDO VOH High Level Output Voltage I O = –800 mA (Note 10) l VCC – 0.5V V SCK VOL Low Level Output Voltage I O = 1.6mA (Note 10) l 0.4 V SCK IOZ Hi-Z Output Leakage l –10 10 mA SDO DIGITAL I PUTS A D DIGITAL OUTPUTSU U POWER REQUIRE E TSW U
Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7 to 5.5V unless otherwise specified. VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2; VIN = IN+ – IN–, VINCM = (IN+ + IN–)/2. Note 4: FO pin tied to GND or to VCC or to external conversion clock source with fEOSC = 153600Hz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: F O = 0V (internal oscillator) or fEOSC = 153600Hz – 2% (external oscillator). Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz – 2% (external oscillator). Note 9: The converter is in external SCK mode of operation such that the SCK pin is used as digital input. The frequency of the clock signal driving SCK during the data output is f ESCK and is expressed in kHz. Note 10: The converter is in internal SCK mode of operation such that the SCK pin is used as digital output. In this mode of operation the SCK pin has a total equivalent load capacitance CLOAD = 20pF. Note 11: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 12: The converter uses the internal oscillator. FO = 0V or FO = VCC. Note 13: The output noise includes the contribution of the internal calibration operations. Note 14: Guaranteed by design and test correlation. Note 15: FO = 0V (internal oscillator) or fEOSC = 139800Hz –2% (external oscillator). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fEOSC External Oscillator Frequency Range l 2.56 2000 kHz tHEO External Oscillator High Period l 0.25 390 ms tLEO External Oscillator Low Period l 0.25 390 ms tCONV Conversion Time F O = 0V (LTC2411) l 130.86 133.53 136.20 ms FO = VCC (LTC2411) l 157.03 160.23 163.44 ms FO = 0V (LTC2411-1) l 143.78 146.71 149.64 ms External Oscillator (Note 11) l 20510/fEOSC (in kHz) ms fISCK Internal SCK Frequency Internal Oscillator (LTC2411) (Note 10) 19.2 kHz Internal Oscillator (LTC2411-1) (Note 10) 17.5 kHz External Oscillator (Notes 10, 11) f EOSC/8 kHz DISCK Internal SCK Duty Cycle (Note 10) l 45 55 % fESCK External SCK Frequency Range (Note 9) l 2000 kHz tLESCK External SCK Low Period (Note 9) l 250 ns tHESCK External SCK High Period (Note 9) l 250 ns tDOUT_ISCK Internal SCK 32-Bit Data Output Time Internal Oscillator (LTC2411) (Notes 10, 12) l 1.64 1.67 1.70 ms Internal Oscillator (LTC2411-1) (Notes 10, 12) l 1.80 1.83 1.86 ms External Oscillator (Notes 10, 11) l 256/fEOSC (in kHz) ms tDOUT_ESCK External SCK 32-Bit Data Output Time (Note 9) l 32/fESCK (in kHz) ms t1 CS fl to SDO Low Z l 0 200 ns t2 CS › to SDO High Z l 0 200 ns t3 CS fl to SCK fl (Note 10) l 0 200 ns t4 CS fl to SCK › (Note 9) l 50 ns tKQMAX SCK fl to SDO Valid l 220 ns tKQMIN SDO Hold After SCK fl (Note 5) l 15 ns t5 SCK Set-Up Before CS fl l 50 ns t6 SCK Hold After CS fl l 50 ns The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) TI I G CHARACTERISTICSUW
(VCC = 5V, VREF = 5V) VIN (V) TUE (ppm OF VREF)
2411 G01
TA = 25°C VCC = 5V REF+ = 5V REF– = GND VINCM = 2.5V FO = GND TA = –45°C TA = 90°C VIN (V) TUE (ppm OF VREF)
2411 G02
1.5 1.0 0.5 –0.5 –1.0 –1.5 VCC = 5V REF+ = 2.5V REF– = GND VINCM = 2.5V FO = GND TA = –45°C TA = 90°C TA = 25°C VIN (V) –1.25 TUE (ppm OF VREF) 0.75
2411 G03
–10 TA = 90°C VCC = 2.7V REF+ = 2.5V REF– = GND VINCM = 1.25V FO = GND TA = –45°C TA = 25°C Total Unadjusted Error (VCC = 5V, VREF = 2.5V) Total Unadjusted Error (VCC = 2.7V, VREF = 2.5V) Integral Nonlinearity (VCC = 5V, VREF = 5V) VIN (V) INL (ppm OF VREF)
2411 G04
TA = 25°C TA = 90°C VCC = 5V REF+ = 5V REF– = GND VINCM = 2.5V FO = GND TA = –45°C Integral Nonlinearity (VCC = 5V, VREF = 2.5V) Integral Nonlinearity (VCC = 2.7V, VREF = 2.5V) VIN (V) INL (ppm OF VREF) 1.5 1.0 0.5 –0.5 –1.0 –1.5 VCC = 5V REF+ = 2.5V REF– = GND VINCM = 2.5V FO = GND TA = 90°C TA = –45°C TA = 25°C VIN (V) –1.25 INL (ppm OF VREF) 0.75
2411 G06
–10 TA = 90°C VCC = 2.7V REF+ = 2.5V REF– = GND VINCM = 1.25V FO = GND TA = –45°C TA = 25°C Noise Histogram OUTPUT CODE (ppm OF VREF) –2.0 NUMBER OF READINGS (%) –0.5 0.5
2411 G07
–1.5 –1.0 0 10,000 CONSECUTIVE READINGS V CC = 5V VREF = 5V VIN = 0V VINCM = 2.5V FO = GND TA = 25°C GAUSSIAN DISTRIBUTION m = –0.647ppm s = 0.287ppm TIME (HOURS) –2.0 ADC READING (ppm OF VREF) –1.5 –1.0 –0.5 1.0 5 10 15 20
2411 G08
0.5 VCC = 5V, VREF = 5V, VIN = 0V, VINCM = 2.5V, FO = GND, TA = 25°C, RMS NOISE = 0.29ppm Long Term ADC Readings INPUT DIFFERENTIAL VOLTAGE (V) RMS NOISE (ppm OF VREF)
2411 G09
0.5 0.4 0.3 0.2 0.1 TA = 25°C VCC = 5V VREF = 5V VINCM = 2.5V FO = GND RMS Noise vs Input Differential Voltage TYPICAL PERFOR A CE CHARACTERISTICS UW
TYPICAL PERFOR A CE CHARACTERISTICS UW RMS Noise vs VINCM RMS Noise vs Temperature RMS Noise vs V CC Offset Error vs VCC Offset Error vs VREF + Full-Scale Error vs Temperature VINCM (V) RMS NOISE (µV)1.50 1.55 1.60
2411 G10
1.45 1.40 01 35 6 1.35 1.30 VCC = 5V REF+ = 5V REF– = GND VIN = 0V FO = GND TA = 25°C TEMPERATURE (°C) –45
1.30 RMS NOISE (µV)
1.35 1.45 1.50 1.55 –15 15 30 90
2411 G11
1.40 –30 0 45 60 75 1.60 VCC = 5V VREF = 5V VIN = 0V VINCM = GND FO = GND VCC (V) 2.7 RMS NOISE (µV)1.50 1.55 1.60 3.9 4.7
2411 G12
1.45 1.40 1.35 1.30 REF+ = 2.5V REF– = GND VIN = 0V FO = GND TA = 25°C RMS Noise vs VREF Offset Error vs VINCM Offset Error vs Temperature VREF (V) 1.35 1.40 1.45 1.50 1.55 1.60 1234
2411 G13
VCC = 5V REF– = GND VIN = 0V FO = GND TA = 25°C VINCM (V) OFFSET ERROR (ppm OF VREF) 1 3 46
2411 G14
–0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 –0.8 –0.9 –1.0 02 5 VCC = 5V REF+ = 5V REF– = GND VIN = 0V FO = GND TA = 25°C TEMPERATURE (°C) –45 OFFSET ERROR (ppm OF VREF) –15 15 30 90
2411 G15
–0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 –0.8 –0.9 –1.0 –30 0 45 60 75 VCC = 5V VREF = 5V VIN = 0V VINCM = GND FO = GND VCC (V) 2.7 OFFSET ERROR (ppm OF VREF) 3.5 4.3 4.7 5.5
2411 G16
0.8 0.6 0.4 0.2 –0.2 –0.4 –0.6 –0.8 –1.0 3.1 3.9 5.1 REF+ = 2.5V REF– = GND VIN = 0V VINCM = GND FO = GND TA = 25°C VREF (V) OFFSET ERROR (ppm OF VREF) 1 2 5
2411 G17
0.8 0.6 0.4 0.2 –0.2 –0.4 –0.6 –0.8 –1.0 VCC = 5V REF– = GND V IN = 0V VINCM = GND FO = GND TA = 25°C TEMPERATURE (°C) –45 FULL-SCALE ERROR (ppm OF VREF) –15 15 30 90
2411 G18
–30 0 45 60 75 VCC = 5V REF+ = 5V REF– = GND IN+ = 2.5V IN– = GND FO = GND
TYPICAL PERFOR A CE CHARACTERISTICS UW + Full-Scale Error vs Temperature PSRR vs Frequency at VCC (LTC2411) TEMPERATURE (°C) –45 FULL-SCALE ERROR (ppm OF VREF) –15 15 30 90
2411 G19
–30 0 45 60 75 VCC = 2.7V REF+ = 2.5V REF– = GND IN+ = 1.25V IN– = GND FO = GND –Full-Scale Error vs Temperature TEMPERATURE (°C) –45 –FULL-SCALE ERROR (ppm OF VREF) –15 15 30 90
2411 G20
–30 0 45 60 75 VCC = 5V REF+ = 5V REF– = GND IN+ = GND IN– = 2.5V FO = GND –Full-Scale Error vs Temperature TEMPERATURE (°C) –45 –FULL-SCALE ERROR (ppm OF VREF) –15 15 30 90
2411 G21
–30 0 45 60 75 VCC = 2.7V REF+ = 2.5V REF– = GND IN+ = GND IN– = 1.25V FO = GND FREQUENCY AT VCC (Hz) –20 –40 –60 –80 –100 –120 –140 1k 100k
2411 G22
REJECTION (dB) VCC = 4.1V DC REF+ = 2.5V REF– = GND IN+ = GND IN– = GND FO = GND TA = 25°C PSRR vs Frequency at VCC (LTC2411) FREQUENCY AT VCC (Hz) REJECTION (dB) –60 –40 –20 120 180
2411 G23
–80 –100 30 60 150 210 –120 –140 90 240 VCC = 4.1V DC –1.4V REF+ = 2.5V REF– = GND IN+ = GND IN– = GND FO = GND TA = 25°C PSRR vs Frequency at VCC (LTC2411) FREQUENCY AT VCC (Hz) 7600 –60 –40 7750
2411 G24
–80 –100 7650 7700 7800 –120 –140 –20 REJECTION (dB) VCC = 4.1V DC –0.7VP-P REF+ = 2.5V REF– = GND IN+ = GND IN– = GND FO = GND TA = 25°C PSRR vs Frequency at VCC (LTC2411-1) PSRR vs Frequency at VCC (LTC2411-1) PSRR vs Frequency at VCC (LTC2411-1) FREQUECY AT VCC (Hz) –20 –40 –60 –80 –100 –120 –140 1k 100k
2411 G31
REJECTION (dB) VCC = 4.1V DC REF+ = 2.5V REF– = GND IN+ = GND IN– = GND FO = GND TA = 25°C FREQUENCY AT VCC (Hz) –140 REJECTION (dB) –120 –80 –60 –40 20 100 140
2411 G32
–100 –20 80 200 180 22040 60 120 160 VCC = 4.1V DC –1.4V REF+ = 2.5V REF– = GND IN+ = GND IN– = GND FO = GND TA = 25°C FREQUENCY AT VCC (Hz) 6880 –60 –40 7030
2411 G33
–80 –100 6930 6980 7080 –120 –140 –20 REJECTION (dB) VCC = 4.1V DC –0.7V REF+ = 2.5V REF– = GND IN+ = GND IN– = GND FO = GND TA = 25°C
TYPICAL PERFOR A CE CHARACTERISTICS UW Offset Error vs Output Data Rate Resolution (NOISERMS £ 1LSB) vs Output Data Rate OUTPUT DATA RATE (READINGS/SEC) –120 OFFSET ERROR (ppm OF VREF) –60 –20 –80 –100 –40 20 40 60 80
2411 G28
VCC = 5V REF– = GND VINCM = 2.5V VIN = 0V FO = EXT OSC TA = 25°C VREF = 2.5V VREF = 5V OUTPUT DATA RATE (READINGS/SEC) RESOLUTION (BITS)
2411 G29
VCC = 5V REF– = GND VINCM = 2.5V VIN = 0V FO = EXT OSC RES = LOG2(VREF/NOISERMS) TA = 25°C VREF = 2.5V VREF = 5V Resolution (INLMAX £ 1LSB) vs Output Data Rate OUTPUT DATA RATE (READINGS/SEC) RESOLUTION (BITS)14 20 40 60 80
2411 G30
VCC = 5V REF– = GND VINCM = 2.5V VIN = 0V FO = EXT OSC RES = LOG2(VREF/INLMAX) TA = 25°C VREF = 2.5V VREF = 5V VCC (Pin 1): Positive Supply Voltage. Bypass to GND (Pin␣ 6) with a 10mF tantalum capacitor in parallel with 0.1mF ceramic capacitor as close to the part as possible. REF+ (Pin 2), REF– (Pin 3): Differential Reference Input. The voltage on these pins can have any value between GND and V CC as long as the reference positive input, REF +, is more positive than the reference negative input, REF–, by at least 0.1V. IN+ (Pin 4), IN – (Pin 5): Differential Analog Input. The voltage on these pins can have any value between GND – 0.3V and V CC + 0.3V. Within these limits, the converter bipolar input range (V IN = IN + – IN –) extends from – 0.5 • (V REF ) to 0.5 • (V REF). Outside this input range, the converter produces unique overrange and underrange output codes. GND (Pin 6): Ground. Connect this pin to a ground plane through a low impedance connection. CS (Pin 7): Active LOW Digital Input. A LOW on this pin enables the SDO digital output and wakes up the ADC. Following each conversion the ADC automatically enters UUUPI FU CTIO S Conversion Current vs Temperature Sleep Mode Current vs Temperature TEMPERATURE (°C) –45 CONVERSION CURRENT (µA) 200 210 220
2411 G25
–15 15 45–30 90 0 30 60 170 240 230 FO = GND CS = GND SCK = NC SDO = NC VCC = 5.5V VCC = 2.7V VCC = 5V VCC = 3V Conversion Current vs Output Data Rate OUTPUT DATA RATE (READINGS/SEC) SUPPLY CURRENT (µA) 450 550 650
2411 G26
REF+ = VCC REF– = GND IN+ = GND IN– = GND TA = 25°C SCK = NC SDO = NC CS = GND F O = EXT OSC VCC = 3V VCC = 5V TEMPERATURE (°C) –45 SLEEP MODE CURRENT (µA)
2411 G27
–15 15 45–30 90 0 30 60 FO = GND CS = VCC SCK = NC SDO = NC VCC = 5.5V VCC = 2.7V VCC = 5V VCC = 3V
the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion. SDO (Pin 8): Three-State Digital Output. During the Data Output period, this pin is used as the serial data output. When the chip select CS is HIGH (CS = VCC), the SDO pin is in a high impedance state. During the Conversion and Sleep periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW. SCK (Pin 9): Bidirectional Digital Clock Pin. In Internal Serial Clock Operation mode, SCK is used as the digital output for the internal serial interface clock during the Data Output period. In External Serial Clock Operation mode, SCK is used as the digital input for the external serial interface clock during the Data Output period. A weak internal pull-up is automatically activated in Internal Serial Clock Operation mode. The Serial Clock Operation mode is determined by the logic level applied to the SCK pin at power up or during the most recent falling edge of CS. F O (Pin 10): Frequency Control Pin. Digital input that controls the ADC’s notch frequencies and conversion time. For the LTC2411, when the F O pin is connected to VCC (FO = VCC), the converter uses its internal oscillator and the digital filter first null is located at 50Hz. When the FO pin is connected to GND (FO = OV), the converter uses its internal oscillator and the digital filter first null is located at 60Hz. For the LTC2411-1, the converter provides simultaneous 50Hz/60Hz rejection with the F O pin connected to GND. When F O is driven by an external clock signal with a frequency fEOSC, the converters use this signal as their system clock and the digital filter first null is located at a frequency fEOSC/2560. UU WFU CTIO AL BLOCK DIAGRA UUUPI FU CTIO S AUTOCALIBRATION AND CONTROL DAC DECIMATING FIR INTERNAL OSCILLATOR SERIAL INTERFACEADC∑ ∫∫∫ GND VCC IN+ IN– SDO SCK REF+ REF– CS FO (INT/EXT) 2411 FD TEST CIRCUITS 1.69k SDO
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CLOAD = 20pF 1.69k SDO
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CLOAD = 20pF VCC
The LTC2411/LTC2411-1 are low power, delta-sigma ana- log-to-digital converters with an easy-to-use 3-wire serial interface (see Figure 1). Their operation is made up of three states. The converter operating cycle begins with the con- version, followed by the low power sleep state and ends with the data output (see Figure 2). The 3-wire interface consists of serial data output (SDO), serial clock (SCK) and chip select (CS). Initially, the LTC2411/LTC2411-1 perform a conversion. Once the conversion is complete, the devices enter the sleep state. While in this sleep state, power consumption is reduced by an order of magnitude. The parts remain in the sleep state as long as CS is HIGH. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state. Once CS is pulled LOW, the devices begin outputting the conversion result. There is no latency in the conversion result. The data output corresponds to the conversion just performed. This result is shifted out on the serial data out pin (SDO) under the control of the serial clock (SCK). Data is updated on the falling edge of SCK allowing the user to reliably latch data on the rising edge of SCK (see Figure 3). The data output state is concluded once 32 bits are read out of the ADC or when CS is brought HIGH. The devices automatically initiate a new conversion and the cycle repeats. Through timing control of the CS and SCK pins, the LTC2411/LTC2411-1 offer several flexible modes of op- eration (internal or external SCK and free-running conver- sion modes). These various modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section. Conversion Clock A major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital filter (commonly implemented as a Sinc or Comb filter). For high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50 or 60Hz plus their harmonics. The filter rejection performance is directly related to the accuracy of the converter system clock. The LTC2411/LTC2411-1 incorporate a highly ac- curate on-chip oscillator. This eliminates the need for external frequency setting components such as crystals or oscillators. Clocked by the on-chip oscillator, the LTC2411 achieves a minimum of 110dB rejection at the line fre- quency (50Hz or 60Hz –2%) and the LTC2411-1 achieves a minimum of 87dB rejection over 49Hz to 61.2Hz. Ease of Use The LTC2411/LTC2411-1 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog voltages is easy. The LTC2411/LTC2411-1 perform offset and full-scale calibrations in every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation described above. The advantage of continuous calibration is extreme stability of offset and full-scale read- ings with respect to time, supply voltage change and tem- perature drift. Power-Up Sequence The LTC2411/LTC2411-1 automatically enter an internal reset state when the power supply voltage V CC drops below approximately 1.9V. This feature guarantees theFigure 2. LTC2411/LTC2411-1 State Transition Diagram CONVERT SLEEP DATA OUTPUT
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FALSE CS = LOW AND SCK APPLICATIO S I FOR ATIOWU UU
integrity of the conversion result and of the serial interface mode selection. (See the 2-wire I/O sections in the Serial Interface Timing Modes section.) When the V CC voltage rises above this critical threshold, the converter creates an internal power-on-reset (POR) signal with a duration of approximately 1ms. The POR signal clears all internal registers. Following the POR signal, the LTC2411/LTC2411-1 start a normal conversion cycle and follow the succession of states described above. The first conversion result following POR is accurate within the specifications of the device if the power supply voltage is restored within the operating range (2.7V to 5.5V) before the end of the POR time interval. Reference Voltage Range The LTC2411/LTC2411-1 accept a truly differential exter- nal reference voltage. The absolute/common mode volt- age specification for the REF + and REF – pins covers the entire range from GND to V CC. For correct converter operation, the REF+ pin must always be more positive than the REF– pin. The LTC2411/LTC2411-1 can accept a differential refer- ence voltage from 0.1V to VCC. The converter output noise is determined by the thermal noise of the front-end cir- cuits, and, as such, its value in nanovolts is nearly constant with reference voltage. A decrease in reference voltage will not significantly improve the converter’s effective resolu- tion. On the other hand, a reduced reference voltage will improve the converter’s overall INL performance. A reduced reference voltage will also improve the converter perfor- mance when operated with an external conversion clock (external F O signal) at substantially higher output data rates. Input Voltage Range The analog input is truly differential with an absolute/ common mode range for the IN + and IN – input pins extending from GND – 0.3V to V CC + 0.3V. Outside these limits, the ESD protection devices begin to turn on and the errors due to input leakage current increase rapidly. Within these limits, the LTC2411/LTC2411-1 con- vert the bipolar differential input signal, V IN = IN+ – IN –, from – FS = – 0.5 • VREF to +FS = 0.5 • VREF where VREF = REF+ – REF –. Outside this range the converter indicates the overrange or the underrange condition using distinct output codes. Input signals applied to IN+ and IN– pins may extend by 300mV below ground and above VCC. In order to limit any fault current, resistors of up to 5k may be added in series with the IN + and IN – pins without affecting the perfor- mance of the device. In the physical layout, it is important to maintain the parasitic capacitance of the connection between these series resistors and the corresponding pins as low as possible; therefore, the resistors should be located as close as practical to the pins. In addition, series resistors will introduce a temperature dependent offset error due to the input leakage current. A 1nA input leakage current will develop a 1ppm offset error on a 5k resistor if V REF = 5V. This error has a very strong temperature dependency. Output Data Format The LTC2411/LTC2411-1 serial output data stream is 32 bits long. The first 3 bits represent status information in- dicating the sign and conversion state. The next 24 bits are the conversion result, MSB first. The remaining 5 bits are sub LSBs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. The third and fourth bits together are also used to indicate an underrange condition (the differential input voltage is be- low –FS) or an overrange condition (the differential input voltage is above + FS). Bit 31 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the conversion and sleep states whenever the CS pin is LOW. This bit is HIGH during the conversion and goes LOW when the conversion is complete. Bit 30 (second output bit) is a dummy bit (DMY) and is always LOW. Bit 29 (third output bit) is the conversion result sign indi- cator (SIG). If V IN is >0, this bit is HIGH. If VIN is <0, this bit is LOW. Bit 28 (fourth output bit) is the most significant bit (MSB) of the result. This bit in conjunction with Bit 29 also provides the underrange or overrange indication. If both Bit 29 and Bit 28 are HIGH, the differential input voltage is APPLICATIO S I FOR ATIOWU UU
differential input voltage is below –FS. The function of these bits is summarized in Table 1. Table 1. LTC2411/LTC2411-1 Status Bits Bits 28-5 are the 24-bit conversion result MSB first. Bit 5 is the least significant bit (LSB). Table 2. LTC2411/LTC2411-1 Output Data Format *The differential input voltage VIN = IN+ – IN–. **The differential reference voltage VREF = REF+ – REF–. Figure 3. Output Data Timing
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corresponding to –FS – 1LSB. rejection the FO pin should be connected to VCC. conversions will not be affected. Figure 4. LTC2411 Normal Mode Rejection When
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Table 3. LTC2411/LTC2411-1 State Duration to read the conversion result. the SDO pin on the falling edge of the serial clock. rising edge of SCK occurs while CS = LOW. described in the previous sections.
Figure 5. External Serial Clock, Single Cycle Operation Table 4. LTC2411/LTC2411-1 Interface Timing Modes
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of operation, see Serial Interface Timing Modes section. nal serial clock, 2- or 3-wire I/O, single cycle conversion. = HIGH) or an external oscillator connected to the FO pin. Refer to Table␣ 4 for a summary. control the state of the conversion cycle, see Figure 5. The serial clock mode is selected on the falling edge of CS. (SCK) must be LOW during each CS falling edge. pulled LOW in order to monitor the state of the converter. While CS is pulled LOW, EOC is output to the SDO pin.
(EOC = 1) indicating a conversion is in progress. and EOC monitored as an end-of-conversion interrupt. Alternatively, CS may be driven HIGH setting SDO to Hi-Z. order to monitor the conversion status. Typically, CS remains LOW during the data output state. conversion cycle or synchronizing the start of a conversion. interface or isolation barrier. in order to enter the external serial clock timing mode. remains in the sleep state until the first rising edge of SCK. Figure 6. External Serial Clock, Reduced Data Output Length
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Figure 7. External Serial Clock, CS = 0 Operation
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Figure 8. Internal Serial Clock, Single Cycle Operation of SCK. EOC can be latched on the first rising edge of SCK. indicating a new conversion has begun. control the state of the conversion cycle, see Figure 8.
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matically selected if SCK is not externally driven. pulled LOW in order to monitor the state of the converter. and EOC = 0 if the device is in the sleep state. HIGH and a new conversion starts. Typically, CS remains LOW during the data output state. Figure 9. Internal Serial Clock, Reduced Data Output Length
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the SCK pin or by never pulling CS HIGH when SCK is LOW. will remain in the internal SCK timing mode. adding an external 10k pull-up resistor to the SCK pin. Figure 10. CS may be permanently tied to ground, simpli- fying the user interface or isolation barrier. Figure 10. Internal Serial Clock, CS = 0 Continuous Operation
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The internal serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded approximately 1ms after V CC exceeds 1.9V. An internal weak pull-up is active during the POR cycle; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven LOW (if SCK is loaded such that the internal pull-up cannot pull the pin HIGH, the external SCK mode will be selected). During the conversion, the SCK and the serial data output pin (SDO) are HIGH (EOC = 1). Once the conversion is complete, SCK and SDO go LOW (EOC = 0) indicating the conversion has finished and the device has entered the low power sleep state. The part remains in the sleep state a minimum amount of time (1/2 the internal SCK period) then immediately begins outputting data. The data output cycle begins on the first rising edge of SCK and ends after the 32nd rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 32nd rising edge of SCK. After the 32nd rising edge, SDO goes HIGH (EOC = 1) indicating a new conversion is in progress. SCK remains HIGH during the conversion. PRESERVING THE CONVERTER ACCURACY The LTC2411/LTC2411-1 are designed to reduce as much as possible the conversion result sensitivity to device decoupling, PCB layout, antialiasing circuits, line fre- quency perturbations and so on. Nevertheless, in order to preserve the extreme accuracy capability of this part, some simple precautions are desirable. Digital Signal Levels The LTC2411/LTC2411-1’s digital interface is easy to use. Its digital inputs (F O, CS and SCK in External SCK mode of operation) accept standard TTL/CMOS logic levels and the internal hysteresis receivers can tolerate edge rates as slow as 100ms. However, some considerations are required to take advantage of the exceptional accuracy and low supply current of this converter. The digital output signals (SDO and SCK in Internal SCK mode of operation) are less of a concern because they are not generally active during the conversion state. While a digital input signal is in the range 0.5V to (VCC␣ –␣ 0.5V), the CMOS input receiver draws additional current from the power supply. It should be noted that, when any one of the digital input signals (FO, CS and SCK in External SCK mode of operation) is within this range, the LTC2411/LTC2411-1 power supply current may in- crease even if the signal in question is at a valid logic level. For micropower operation, it is recommended to drive all digital input signals to full CMOS levels [V IL < 0.4V and VOH > (VCC – 0.4V)]. During the conversion period, the undershoot and/or overshoot of a fast digital signal connected to the LTC2411/ LTC2411-1 pins may severely disturb the analog to digital conversion process. Undershoot and overshoot can oc- cur because of the impedance mismatch at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to LTC2411/LTC2411-1. For reference, on a regular FR-4 board, signal propagation velocity is approximately 183ps/inch for internal traces and 170ps/inch for surface traces. Thus, a driver generating a control signal with a minimum transition time of 1ns must be connected to the converter pin through a trace shorter than 2.5 inches. This problem becomes particularly difficult when shared con- trol lines are used and multiple reflections may occur. The solution is to carefully terminate all transmission lines close to their characteristic impedance. Parallel termination near the LTC2411/LTC2411-1 pin will eliminate this problem but will increase the driver power dissipation. A series resistor between 27 W and 56 W placed near the driver or near the LTC2411/LTC2411-1 pin will also eliminate this problem without additional power dissipation. The actual resistor value depends upon the trace impedance and connection topology. An alternate solution is to reduce the edge rate of the control signals. It should be noted that using very slow edges will increase the converter power supply current during the transition time. The differential input and refer- ence architecture reduce substantially the converter’s sensitivity to ground currents. APPLICATIO S I FOR ATIOWU UU
converter input terminals may result into a DC offset error. the differential input and reference connections. pins transfering small amounts of charge in the process. A simplified equivalent circuit is shown in Figure 11. case circumstances, the errors may add. Figure 11. LTC2411/LTC2411-1 Equivalent Analog Input Circuit
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- - • () = -• - +
- + • V REF REF V REF REF VI N I N V IN IN R M INTERNAL OSCILLATOR Hz Notch F LOW LTC R M INTERNAL OSCILLATOR Hz Notch F HIGH LTC R M INTERNAL OSCILLATOR F LOW LTC REF REFCM IN INCM EQ O EQ O EQ O = +æ Łç ö = -æ Łç ö == () ( ) == () ( ) == () 10 8 60 2411 13 0 50 2411 11 9 W W W 24112411 1 16 7 1 0 -() =•()R f EXTERNAL OSCILLATOREQ EOSC./
stantial time period (longer than 64 internal clock cycles). O = GND are plotted out as a typical case. For simplicity, two distinct situations can be considered.
- These measured results may be slightly different from
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Figure 12. An RC Network at IN+ and IN– Figure 13. +FS Error vs RSOURCE at IN+ or IN– (Small CIN) Figure 14. –FS Error vs RSOURCE at IN+ or IN– (Small CIN)
Larger values of input capacitors (C IN > 0.01mF) may be required in certain configurations for antialiasing or gen- eral input signal filtering. Such capacitors will average the input sampling charge and the external source resistance will see a quasi constant input differential impedance. For the LTC2411, when F O = LOW (internal oscillator and 60Hz notch), the typical differential input resistance is 5.4M W which will generate a gain error of approximately 0.093ppm for each ohm of source resistance driving IN + or IN –. When FO = HIGH (internal oscillator and 50Hz notch), the typical differential input resistance is 6.5M W which will generate a gain error of approximately 0.077ppm for each ohm of source resistance driving IN + or IN –. For the LTC2411-1, the typical differential input resistance is 6MW which will generate a gain error of approximately 0.084ppm for each ohm of source resistance driving IN or IN – (F O = LOW). When F O is driven by an external oscillator with a frequency f EOSC (external conversion clock operation), the typical differential input resistance is 0.83 • 1012/fEOSCW and each ohm of source resistance driving IN+ or IN– will result in 0.59 • 10–6 • fEOSCppm gain error. The effect of the source resistance on the two input pins is additive with respect to this gain error. The typical +FS and –FS errors as a function of the sum of the source resistance seen by IN + and IN– for large values of CIN are shown in Figure 15. In addition to this gain error, an offset error term may also appear. The offset error is proportional with the mismatch between the source impedance driving the two input pins IN + and IN– and with the difference between the input and reference common mode voltages. While the input drive circuit nonzero source impedance combined with the converter average input current will not degrade the INL performance, indirect distortion may result from the modu- lation of the offset error by the common mode component of the input signal. Thus, when using large C IN capacitor values, it is advisable to carefully match the source imped- ance seen by the IN+ and IN– pins. For the LTC2411, when FO = LOW (internal oscillator and 60Hz notch), every 1W mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 0.093ppm. When F O = HIGH (internal oscillator and 50Hz notch), every 1 W mismatch in source imped- ance transforms a full-scale common mode input signal into a differential mode input signal of 0.077ppm. For the LTC2411-1, when internal oscillator is used (F O = LOW), every 1W mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 0.084ppm. When FO is driven by an external oscillator with a frequency fEOSC, every 1W mis- match in source impedance transforms a full-scale com- mon mode input signal into a differential mode input signal of 0.59 • 10 –6 • fEOSCppm. Figure 16 shows the typical offset error due to input common mode voltage for various values of source resistance imbalance between the IN+ and IN– pins when large CIN values are used. If possible, it is desirable to operate with the input signal common mode voltage very close to the reference signal common mode voltage as is the case in the ratiometric measurement of a symmetric bridge. This configuration APPLICATIO S I FOR ATIOWU UU RSOURCE (Ω ) 0 100 200 300 400 500 600 700 800 900 1000 +FS ERROR (ppm OF VREF)
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VCC = 5V REF+ = 5V REF– = GND IN+ = 3.75V IN– = 1.25V FO = GND TA = 25°C CIN = 1µF CIN = 0.1µF CIN = 0.01µF CIN = 10µF Figure 15a. + FS Error vs RSOURCE at IN+ or IN– (Large CIN) Figure 15b. – FS Error vs RSOURCE at IN+ or IN– (Large CIN) RSOURCE (Ω ) 0 100 200 300 400 500 600 700 800 900 1000 –FS ERROR (ppm OF VREF)
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–120 –100 –80 –60 –40 –20 VCC = 5V REF+ = 5V REF– = GND IN+ = 1.25V IN– = 3.75V FO = GND TA = 25°C CIN = 1µF CIN = 0.1µF CIN = 0.01µF CIN = 10µF
tive values over the entire temperature and voltage range). calibration operation may be sufficient. a 0.1mV typical and 1mV maximum offset voltage. can be analyzed in the same two distinct situations. filtering and the user is advised to avoid them. errors are similar to + FS errors with opposite polarity. mance is degraded by the reference source impedance.
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Figure 16. Offset Error vs Common Mode Voltage
REF– translates into about 0.45ppm additional INL error. two reference pins is additive with respect to this INL error.
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Figure 19. INL vs Differential Input Voltage (VIN = IN+ = IN–)
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user is thus advised to minimize the combined source impedance driving the REF+ and REF– pins rather than to try to match it. The magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capaci- tors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typical better than 1%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/°C) are used for the external source impedance seen by REF and REF–, the expected drift of the dynamic current gain error will be insignificant (about 1% of its value over the entire temperature and voltage range). Even for the most stringent applications, a one-time calibration operation may be sufficient. In addition to the reference sampling charge, the reference pins ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (–10nA max), results in a small gain error. A 100W source resistance will create a 0.05 mV typical and 0.5 mV maxi- mum full-scale error. Output Data Rate When using its internal oscillator, the LTC2411 can pro- duce up to 7.5 readings per second with a notch frequency of 60Hz (F O = LOW) and 6.25 readings per second with a notch frequency of 50Hz (FO = HIGH) and the LTC2411-1 can produce up to 6.8 readings per second with FO = LOW. The actual output data rate will depend upon the length of the sleep and data output phases which are controlled by the user and which can be made insignificantly short. When operated with an external conversion clock (F O connected to an external oscillator), the LTC2411/LTC2411- 1 output data rate can be increased as desired. The duration of the conversion phase is 20510/fEOSC. If fEOSC = 153600Hz, the converter behaves as if the internal oscillator is used and the notch is set at 60Hz. There is no significant difference in the LTC2411/LTC2411-1 perfor- mance between these two operation modes. An increase in f EOSC over the nominal 153600Hz will translate into a proportional increase in the maximum output data rate. This substantial advantage is nevertheless APPLICATIO S I FOR ATIOWU UU accompanied by three potential effects, which must be carefully considered. First, a change in fEOSC will result in a proportional change in the internal notch position and in a reduction of the converter differential mode rejection at the power line frequency. In many applications, the subsequent perfor- mance degradation can be substantially reduced by rely- ing upon the LTC2411/LTC2411-1’s exceptional common mode rejection and by carefully eliminating common mode to differential mode conversion sources in the input circuit. The user should avoid single-ended input filters and should maintain a very high degree of matching and symmetry in the circuits driving the IN + and IN– pins. Second, the increase in clock frequency will increase proportionally the amount of sampling charge transferred through the input and the reference pins. If large external input and/or reference capacitors (C IN, CREF) are used, the previous section provides formulae for evaluating the effect of the source resistance upon the converter perfor- mance for any value of f EOSC. If small external input and/ or reference capacitors (CIN, CREF) are used, the effect of the external source resistance upon the LTC2411/ LTC2411-1 typical performance can be inferred from Figures 13, 14 and 17 in which the horizontal axis is scaled by 153600/f EOSC. Third, an increase in the frequency of the external oscilla- tor above 460800Hz (a more than 3· increase in the output data rate) will start to decrease the effectiveness of the internal autocalibration circuits. This will result in a progres- sive degradation in the converter accuracy and linearity. Typical measured performance curves for output data rates up to 100 readings per second are shown in Figures␣ 20 to 27. In order to obtain the highest possible level of accuracy from this converter at output data rates above 20 readings per second, the user is advised to maximize the power supply voltage used and to limit the maximum ambient operating temperature. In certain circumstances, a reduc- tion of the differential reference voltage may be beneficial. Input Bandwidth The combined effect of the internal sinc 4 digital filter and of the analog and digital autocalibration circuits deter- mines the LTC2411/LTC2411-1 input bandwidth. When
Figure 23. Resolution (NoiseRMS £ 1LSB)
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Figure 24. Resolution (INLRMS £ 1LSB)
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Figure 21. + FS Error vs Output Data Rate and Temperature Figure 22. – FS Error vs Output Data Rate and Temperature
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Figure 20. Offset Error vs Output Data Rate and Temperature Figure 25. Offset Error vs Output
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LOW) and 3.02Hz for 50Hz notch frequency (FO = HIGH). bandwidth is 0.236 • 10–6 • fEOSC. Figure 27. Resolution (INLMAX £ 1LSB)
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Figure 26. Resolution (NoiseRMS £ 1LSB)
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Figure 28. Input Signal Bandwidth
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followed by a high bandwidth unity-gain buffer.
amplifiers lose significance. nificantly simplifies antialiasing filter requirements. mode signal filtering both in the analog and digital domain.
- fOUTMAX where fN is the notch frequency and fOUTMAX is the maximum output data rate. In the internal oscillator mode, for the LTC2411, FS = 12800Hz with a 50Hz notch setting and fS = 15360Hz with a 60Hz notch setting. For the LTC2411-1, fS = 13980Hz (F O = LOW). In the external oscillator mode, fS = fEOSC/10. The combined normal mode rejection performance is shown in Figure␣ 30 for the internal oscillator with 50Hz notch setting (FO = HIGH) and in Figure␣ 31 for the internal oscillator with FO = LOW and for the external oscillator mode. The regions of low rejection occurring at integer multiples of fS have a very narrow bandwidth. Magnified details of the normal mode rejection curves are shown in APPLICATIO S I FOR ATIOWU UU DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 0f S 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS10fS11fS12fS INPUT NORMAL MODE REJECTION (dB)
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Figure 30. Input Normal Mode Rejection, Figure 31. Input Normal Mode Rejection, Internal Figure 29. Input Referred Noise Equivalent Bandwidth
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Figure 32. Input Normal Mode Rejection Figure 33. Input Normal Mode Rejection
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Figure 34. Input Normal Mode Rejection Figure 35. Input Normal Mode Rejection fS = 256f N) where f N represents the notch frequency. superimposed over the theoretical calculated curve. minimize the effects of dynamic input current.
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Figure 36. Input Normal Mode Rejection Figure 37. Measured Input Normal Mode Rejection Figure 38. Measured Input Normal Mode Rejection LTC2411/LTC2411-1 are eminently suited for such tasks. many solid state sensors, this is comparable to the sensor.
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Figure 39. Measured Input Normal Mode Rejection
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average a large number of readings is usually not an issue. and gain to be interleaved with weighing measurements. duce a precision divide operation on the reference signal. amplifiers, as shown in Figures 45 and 46. the ADC is located within the load-cell housing. Figure 40. Simple Bridge Connection
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referred noise dominates the LTC2411/LTC2411-1 noise. Figure 41. Using Autozero Amplifiers to Reduce Input Referred Noise benefit in terms of noise reduction.
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Figure 42. Bridge Amplification Using a Single Amplifier gain stability and linearity. to match the temperature coefficient of the strain gauges. need for resistors with a high degree of absolute accuracy. as opposed to 1/2 VREF in the 2-amplifier topology above. Figure 43. Remote Half Bridge Interface
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and R2, as it will store charge from the sampling process. from the input lines with a high value resistor (R3). result as the two resistor version, but has a few benefits. and more protection for remote applications. Figure 44. Remote Half Bridge Sensing with Noise Suppression on Reference
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Figure 45. LTC1043 Provides Precise 4· Reference for Excitation Voltages
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Figure 46. Use a Differential Multiplexer to Expand Channel Capability inverting gain of 2, to produce –10V from a 5V reference. as 130ppm, the average of the two. inexpensive multiplexer such as the 74HC4052. are inserted as a protection mechanism from overvoltage.
2411 F46
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. UPACKAGE DESCRIPTIO MSOP (MS10) 1100 * DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE 0.021 – 0.006 (0.53 – 0.015) 0° – 6° TYP SEATING PLANE 0.007 (0.18) 0.043 (1.10) MAX 0.007 – 0.011 (0.17 – 0.27) 0.005 – 0.002 (0.13 – 0.05) 0.034 (0.86) REF 0.0197 (0.50) BSC 12 3 45 0.193 – 0.006 (4.90 – 0.15) 8910 7 6 0.118 – 0.004* (3.00 – 0.102) 0.118 – 0.004** (3.00 – 0.102) 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661)
Figure 47. Use Resistor Arrays to Provide Precise Matching in Excitation Amplifier