LTC1967 LINEAR | Alldatasheet
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Bandwidth, RMS-to-DC Converter n High Linearity: 0.02% Linearity Allows Simple System Calibration n Wide Input Bandwidth: Bandwidth to 0.1% Additional Gain Error: 40kHz Bandwidth Independent of Input Voltage Amplitude n No-Hassle Simplicity: True RMS-DC Conversion with Only One External Capacitor Delta Sigma Conversion Technology n Low Supply Current: 330mA Typ n Ultralow Shutdown Current: 0.1mA n Flexible Inputs: Differential or Single Ended Rail-to-Rail Common Mode Voltage Range Up to 1V PEAK Differential Voltage n Flexible Output: Rail-to-Rail Output Separate Output Reference Pin Allows Level Shifting n Small Size: Space Saving 8-Pin MSOP Package n True RMS Digital Multimeters and Panel Meters n True RMS AC + DC Measurements DESCRIPTIO UFEATURES APPLICATIO SU The LTC 1967 is a true RMS-to-DC converter that uses an innovative delta-sigma computational technique. The ben- efits of the LTC1967 proprietary architecture when com- pared to conventional log-antilog RMS-to-DC converters are higher linearity and accuracy, bandwidth independent of amplitude and improved temperature behavior. The LTC1967 operates with single-ended or differential in- put signals (for EMI/RFI rejection) and supports crest fac- tors up to 4. Common mode input range is rail-to-rail. Dif- ferential input range is 1V PEAK, and offers unprecedented linearity. The LTC1967 allows hassle-free system calibra- tion at any input voltage. The LTC1967 has a rail-to-rail output with a separate out- put reference pin providing flexible level shifting; it oper- ates on a single power supply from 4.5V to 5.5V. A low power shutdown mode reduces supply current to 0.1mA. The LTC1967 is packaged in the space-saving MSOP pack- age, which is ideal for portable applications. Single Supply RMS-to-DC Converter CAVE 1µF VOUT
1967 TA01
4.5V TO 5.5V OUTPUT DIFFERENTIAL INPUT LTC1967 0.1µF OPT. AC COUPLING EN GND OUT RTN IN1 IN2 TYPICAL APPLICATIO U VIN (mV ACRMS) –1.0LINEARITY ERROR (VOUT mV DC – VIN mV ACRMS) –0.8 –0.6 –0.4 –0.2 0.2 100 200 300 400
1967 TA01b
LTC1967, ∆S 60Hz SINEWAVE CONVENTIONAL LOG/ANTILOG Linearity Performance , LTC and LT are registered trademarks of Linear Technology Corporation. Protected under U.S. Patent Numbers 6,359,576, 6,362,677 and 6,516,291
Operating Temperature Range (Note 4) Specified Temperature Range (Note 5) ORDER PART NUMBER LTC1967CMS8 LTC1967IMS8 TJMAX = 150°C, qJA = 220°C/ W ABSOLUTE AXI U RATI GSW WW U PACKAGE/ORDER I FOR ATIOUU W (Note 1) MS8 PART MARKING LTTJ The l denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. V+ = 5V, VOUTRTN = 2.5V, CAVE = 10mF, VIN = 200mVRMS, VENABLE = 0.5V unless otherwise noted.
ELECTRICAL CHARACTERISTICS
Consult LTC Marketing for parts specified with wider operating temperature ranges. GND IN1 IN2 NC ENABLE V OUT RTN V OUT TOP VIEW MS8 PACKAGE 8-LEAD PLASTIC MSOP SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Conversion Accuracy GERR Low Frequency Gain Error 50Hz to 5kHz Input (Notes 6, 7) –0.1 –0.3 % l –0.4 % VOOS Output Offset Voltage (Notes 6, 7) 0.1 0.55 mV DVOOS/DT Output Offset Drift (Note 11) l 21 0 mV/°C LINERR Linearity Error 50mV to 350mV (Notes 7, 8) l 0.02 0.15 % PSRRG Power Supply Rejection (Note 9) 0.02 0.15 %/V l 0.20 %/V VIOS Input Offset Voltage (Notes 6, 7, 10) 0.2 1.5 mV DVIOS/DT Input Offset Drift (Note 11) l 11 0 mV/°C Additional Error vs Crest Factor (CF) CF = 3 60Hz Fundamental, 200mV RMS l 0.2 mV CF = 5 60Hz Fundamental, 200mV RMS l 5m V Input Characteristics VIMAX Maximum Peak Input Swing Accuracy = 1% (Note 14) l 1 1.05 V IVR Input Voltage Range l 0V + V ZIN Input Impedance Average, Differential (Note 12) 5 M W Average, Common Mode (Note 12) 100 M W CMRRI Input Common Mode Rejection (Note 13) l 50 400 mV/V VIMIN Minimum RMS Input l 5m V PSRRI Power Supply Rejection (Note 9) l 250 600 mV/V
The l denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. V+ = 5V, VOUTRTN = 2.5V, CAVE = 10mF, VIN = 200mVRMS, VENABLE = 0.5V unless otherwise noted. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The inputs (IN1, IN2) are protected by shunt diodes to GND and V+. If the inputs are driven beyond the rails, the current should be limited to less than 10mA. Note 3: The LTC1967 output (VOUT) is high impedance and can be overdriven, either sinking or sourcing current, to the limits stated. Note 4: The LTC1967C/LTC1967I are guaranteed functional over the operating temperature range of –40 °C to 85°C. Note 5: The LTC1967C is guaranteed to meet specified performance from 0°C to 70°C. The LTC1967C is designed, characterized and expected to meet specified performance from –40 °C to 85°C but is not tested nor QA sampled at these temperatures. The LTC1967I is guaranteed to meet specified performance from –40 °C to 85°C. Note 6: High speed automatic testing cannot be performed with C AVE = 10mF. The LTC1967 is 100% tested with CAVE = 47nF. Correlation tests have shown that the performance limits can be guaranteed with the additional testing being performed to guarantee proper operation of all the internal circuitry. Note 7: High speed automatic testing cannot be performed with 60Hz inputs. The LTC1967 is 100% tested with DC and 10kHz input signals. Measurements with DC inputs from 50mV to 350mV are used to calculate the four parameters: G ERR, VOOS, VIOS and linearity error. Correlation tests have shown that the performance limits can be guaranteed with the additional testing being performed to guarantee proper operation of all internal circuitry. Note 8: The LTC1967 is inherently very linear. Unlike older log/antilog circuits, its behavior is the same with DC and AC inputs, and DC inputs are used for high speed testing. Note 9: The power supply rejections of the LTC1967 are measured with DC inputs from 50mV to 350mV. The change in accuracy from V + = 4.5V to V+ = 5.5V is divided by 1V. Note 10: Previous generation RMS-to-DC converters required nonlinear input stages as well as a nonlinear core. Some parts specify a “DC reversal error,” combining the effects of input nonlinearity and input offset voltage. The LTC1967 behavior is simpler to characterize and the input offset voltage is the only significant source of “DC reversal error.” Note 11: Guaranteed by design. Note 12: The LTC1967 is a switched capacitor device and the input/output impedance is an average impedance over many clock cycles. The input impedance will not necessarily lead to an attenuation of the input signal measured. Refer to the Applications Information section titled “Input Impedance” for more information. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Output Characteristics OVR Output Voltage Range l 0V + V ZOUT Output Impedance (Note 12) l 40 50 65 k W CMRRO Output Common Mode Rejection (Note 13) l 50 250 mV/V VOMAX Maximum Differential Output Swing Accuracy = 1%, DC Input (Note 14) 1.0 1.05 V l 0.9 V PSRRO Power Supply Rejection (Note 9) l 250 1000 mV/V Frequency Response f1P 0.1% Additional Gain Error (Note 15) 40 kHz f–3dB –3dB Frequency (Note 15) 4 MHz Power Supplies V+ Supply Voltage l 4.5 5.5 V IS Supply Current IN1 = 20mV, IN2 = 0V l 320 390 mA IN1 = 200mV, IN2 = 0V 340 mA Shutdown Characteristics ISS Supply Current V ENABLE = 4.5V l 0.1 10 mA IIH ENABLE Pin Current High V ENABLE = 4.5V l –1 –0.1 mA IIL ENABLE Pin Current Low V ENABLE = 0.5V l –3 –0.5 –0.1 mA VTH ENABLE Threshold Voltage 2.1 V VHYS ENABLE Threshold Hysteresis 0.1 V
Note 13: The common mode rejection ratios of the LTC1967 are measured with DC inputs from 50mV to 350mV. The input CMRR is defined as the change in V IOS measured between input levels of 0V to 350mV and input levels of V+ – 350mV to V+ divided by V+ – 350mV. The output CMRR is defined as the change in VOOS measured with OUT RTN = 0V and OUT RTN = V+ – 350mV divided by V+ – 350mV. Note 14: The LTC1967 input and output voltage swings are limited by internal clipping. However, its DS topology is relatively tolerant of momentary internal clipping. TYPICAL PERFOR A CE CHARACTERISTICS UW Gain and Offset vs Output Common Mode Voltage Gain and Offset vs Input Common Mode Voltage Note 15: The LTC1967 exploits oversampling and noise shaping to reduce the quantization noise of internal 1-bit analog-to-digital conversions. At higher input frequencies, increasingly large portions of this noise are aliased down to DC. Because the noise is shifted in frequency, it becomes a low frequency rumble and is only filtered at the expense of increasingly long settling times. The LTC1967 is inherently wideband, but the output accuracy is degraded by this aliased noise. INPUT COMMON MODE VOLTAGE (V) –0.7 GAIN ERROR (%) OFFSET VOLTAGE (mV) –0.6 –0.4 –0.3 –0.2 0.3
1967 G01
–0.5 0.1 0.2 –0.1 –1.0 –0.8 –0.4 –0.2 1.0 0.4 –0.6 0.6 0.8 0.2 0.5 50mV ≤ VIN(PEAK) ≤ 350mV 1.5 3.0 3.5 4.0 VIOS VOOS GAIN ERROR OUTPUT COMMON MODE VOLTAGE (V) –0.5 GAIN ERROR (%) OFFSET VOLTAGE (mV) –0.4 –0.2 –0.1 0.5 0.2
1967 G02
–0.3 0.3 0.4 0.1 –1.0 –0.8 –0.4 –0.2 1.0 0.4 –0.6 0.6 0.8 0.2 VIOS VOOS GAIN ERROR 50mV ≤ VIN(PEAK) ≤ 350mV Gain and Offsets vs Temperature Gain and Offset vs Supply Voltage TEMPERATURE (°C) –40 GAIN ERROR (%) OFFSET VOLTAGE (mV) 0.01 0.03 0.05 V OOS
1967 G03
–0.01 –0.03 0.02 0.04 –0.02 –0.04 –0.05 0.1 0.3 0.5 –0.1 –0.3 0.2 0.4 –0.2 –0.4 –0.5 –15 10 35 85 VIOS GAIN ERROR 50mV ≤ VIN(PEAK) ≤ 350mV SUPPLY VOLTAGE (V) 4.5 –0.5 GAIN ERROR (%) OFFSET VOLTAGE (mV) –0.4 –0.2 –0.1 0.5 0.2 4.8 5.1 6.0
1967 G04
–0.3 0.3 0.4 0.1 –1.0 –0.8 –0.4 –0.2 1.0 0.4 –0.6 0.6 0.8 0.2 5.4 5.7 VIOS VOOS GAIN ERROR 50mV ≤ VIN(PEAK) ≤ 350mV
TYPICAL PERFOR A CE CHARACTERISTICS UW Performance vs Large Crest Factors AC Linearity DC Linearity Supply Current vs Supply Voltage Supply Current vs Temperature Shutdown Current vs ENABLE Voltage Input Signal Bandwidth vs RMS Value Performance vs Crest Factor CREST FACTOR 199.0 199.8 199.6 199.4
199.2 OUTPUT VOLTAGE (mV DC)
200.0 200.2 200.4 200.6 23 4 5 1kHz
1967 G05
200.8 201.0 200mVRMS SCR WAVEFORMS CAVE = 10µF O.1%/DIV 60Hz20Hz CREST FACTOR OUTPUT VOLTAGE (mV DC) 220
1967 G06
CAVE = 10µF 5%/DIV 60Hz 10Hz 10kHz 1kHz20Hz VIN1 (mV ACRMS) VOUT (mV DC) – VIN (mV ACRMS) 0.20 0.15 0.10 0.05 –0.05 –0.10 –0.15 –0.20 400
1967 G07
CAVE = 10µF VIN2 = MIDSUPPLY VIN1 (mV) –500 {VOUTDC – |VINDC|} (mV)0.02 0.06 0.10 300
1967 G08
–0.02 –0.06 0.04 0.08 –0.04 –0.08 –0.10 –300 –100 100 500 CAVE = 1µF VIN2 = MIDSUPPLY EFFECTS OF OFFSETS MAY BE POSITIVE OR NEGATIVE AT V IN = 0V SUPPLY VOLTAGE (V) SUPPLY CURRENT (µA) 450 400 350 300 250 200 150 100
1967 G09
TEMPERATURE (°C) –55
315 SUPPLY CURRENT (µA)
–15 25 45 125
1967 G10
–35 5 65 85 105
345 VS = 5V
ENABLE PIN VOLTAGE (V) 500 400 300 200 100 –100 –100 100 I S IEN –200 200 –300 300 –400
1967 G11
SUPPLY CURRENT (µA) ENABLE PIN CURRENT (nA) INPUT SIGNAL FREQUENCY (Hz) OUTPUT DC VOLTAGE (mV) 100 100 10k 100k 1M
1967 G12
0.1% ERROR 10% ERROR –3dB 1% ERROR Input Signal Bandwidth INPUT SIGNAL FREQUENCY (Hz) 100 190OUTPUT DC VOLTAGE (mV) 192 194 196 198 1k 10k 100k 1M 10M
1967 G13
1%/DIV CAVE = 1µF
TYPICAL PERFOR A CE CHARACTERISTICS UW Bandwidth to 200kHz DC Transfer Function Near Zero Input Common Mode Rejection Ratio vs Frequency Output Accuracy vs Signal Amplitude INPUT FREQUENCY (Hz) 199 200 202 150k
1967 G14
201OUTPUT VOLTAGE (mV) 0.5%/DIV CAVE = 47µF VIN1 (mV DC) –30 –10 VOUT (mV DC) –20 –10 01 0
1967 G15
VIN2 = MIDSUPPLY THREE REPRESENTATIVE UNITS INPUT FREQUENCY (Hz) INPUT CMRR (dB) 100 1k 10k 100k
1967 G16
4.5V COMMON MODE INPUT CONVERSION TO DC OUTPUT VIN1 (VRMS) –20 {VOUT (mV DC) – VIN (mVRMS)} (mV) –15 –10 0.5 1 1.5 DC
1967 G17
1% ERROR VIN2 = MIDSUPPLY –1% ERROR AC – 60Hz SINEWAVE Output Noise vs Input Frequency INPUT FREQUENCY (Hz) 0.001PEAK OUTPUT NOISE (% OF READING) 0.01 0.1 10k 100k
1967 G18
10 SECOND MEASUREMENT
CAVE = 1µF CAVE = 100µF CAVE = 10µF
GND (Pin 1): Ground. The power return pin. V+ (Pin 7): Positive Voltage Supply. 4.5V to 5.5V. will generate the same heat in a resistive load as will 1V DC.
1967 F01
Table 1. Errors with Average Rectification vs True RMS
RMS-to-DC conversion with real SCR waveforms as well. only with a non-sinusoidal waveform that errors occur.
1967 F02a
1967 F02b
Figure 3. RMS-to-DC Converter with Implicit Computation
1967 F03
1Protected by multiple patents.
processes: squaring and square rooting. from a whole range of input values together. instance, has a peak that is four times its RMS value. which, as shown above, results in RMS-to-DC conversion. Simplified Schematic towards the end of this data sheet. Figure 4. Topology of LTC1967
1967 F04
- VIOS
- INPUT NONLINEARITY IDEAL RMS-TO-DC CONVERTER OUTPUT CIRCUITRY
- V OOS
- OUTPUT NONLINEARITY INPUT OUTPUT
1967 F05
Figure 5. Linearity Model of an RMS-to-DC Converter
linearity throughout the LTC1967.
- It is appropriate for most applications, in which
Figure 6. DC Error vs Input Frequency
1967 F06
Figure 7. Output Ripple Exceeds DC Error
1967 F07
occur with CAVE = 1.5mF and fINPUT = 10Hz. A 2.2mF capacitor is a good choice for many applications. will be <0.1% with frequencies of 10Hz or more. The LTC1967 can operate with many types of capacitors. parasitics, package styles and costs. assure the low frequency accuracy desired. LTC1967 will create a constant offset of the output voltage. a large value of capacitance and at high temperature. a high quality dielectric such as X7R or NPO/COG. Figure 8. Peak Error vs Input Frequency with One Cap Averaging
1967 F08
inputs must be connected with a DC-return path to ground. input is left floating, a zero volt output will result. be created with two resistors as shown in Figure 9b. average of the input voltage. two inputs can be connected through a series capacitor. ceramic chip capacitor will usually suffice. Figure 9. Single-Ended AC-Coupled Input Connection Alternatives
The LTC1967 output is differentially, but not symmetri- cally, generated. That is to say, the RMS value that the LTC1967 computes will be generated on the output (Pin 5) relative to the output return (Pin 6), but these two pins are not interchangeable. For most applications, Pin 6 will be tied to ground (Pin 1). However, Pin 6 can be tied to any voltage between 0V and V + (Pin 7) less the maximum output voltage swing desired. This last restriction keeps VOUT itself (Pin 5) within the range of 0V to V +. If a reference level other than ground is used, it should be a low impedance, both AC and DC, for proper operation of the LTC1967. In any configuration, the averaging capacitor should be connected between Pins 5 and 6. The LTC1967 RMS-DC output will be a positive voltage created at V OUT (Pin 5) with respect to OUT RTN (Pin 6). Power Supply Bypassing The LTC1967 is a switched capacitor device, and large transient power supply currents will be drawn as the switching occurs. For reliable operation, standard power supply bypassing must be included. A 0.01 mF capacitor from V+ (Pin 7) to GND (Pin␣ 1) located close to the device will suffice. If there is a good quality ground plane avail- able, the capacitors can go directly to that instead. Power supply bypass capacitors can, of course, be inexpensive ceramic types. Up and Running! If you have followed along this far, you should have the LTC1967 up and running by now! Don’t forget to enable the device by grounding Pin 8, or driving it with a logic low. Keep in mind that the LTC1967 output impedance is fairly high, and that even the standard 10MW input impedance of a digital multimeter (DMM) or a 10· scope probe will load down the output enough to degrade its typical gain error of 0.1%. In the end application circuit, either a buffer or another component with an extremely high input imped- ance (such as a dual slope integrating ADC) should be used. APPLICATIO S I FOR ATIOWU UU For laboratory evaluation, it may suffice to use a bench-top DMM with the ability to disconnect the 10MW shunt. If you are still having trouble, it may be helpful to skip ahead a few pages and review the Troubleshooting Guide. What About Response Time? With a large value averaging capacitor, the LTC1967 can easily perform RMS-to-DC conversion on low frequency signals. It compares quite favorably in this regard to prior- generation products because nothing about the DS circuitry is temperature sensitive. So the RMS result doesn’t get distorted by signal driven thermal fluctuations like a log-antilog circuit output does. However, using large value capacitors results in a slow response time. Figure 10 shows the rising and falling step responses with a 1mF averaging capacitor. Although they both appear at first glance to be standard exponential- decay type settling, they are not. This is due to the nonlinear nature of an RMS-to-DC calculation. Also note the change in the time scale between the two; the rising edge is more than twice as fast to settle to a given accuracy. Again this is a necessary consequence of RMS- to-DC calculation. Although shown with a step change between 0mV and 100mV, the same response shapes will occur with the LTC1967 for ANY step size. This is in marked contrast to prior generation log/antilog RMS-to-DC converters, whose averaging time constants are dependent on the signal level, resulting in excruciatingly long waits for the output to go to zero. The shape of the rising and falling edges will be dependent on the total percent change in the step, but for less than the 100% changes shown in Figure 10, the responses will be less distorted and more like a standard exponential decay. For example, when the input amplitude is changed from
3 To convince oneself of this necessity, consider a pulse train of 50% duty cycle between 0mV and
100mV. At very low frequencies, the LTC1967 will essentially track the input. But as the input frequency is increased, the average result will converge to the RMS value of the input. If the rise and fall characteristics were symmetrical, the output would converge to 50mV. In fact though, the RMS value of a 100mV DC-coupled 50% duty cycle pulse train is 70.71mV, which the asymmetrical rise and fall characteristics will converge to as the input frequency is increased.
that of the rising edge and falling edge cases of Figure 10. it goes to zero, and it can be used as a design guide. gives an acceptable settling time, your design is done. seconds is just 3.2 cycles of this extremely low frequency. Averaging very low frequency signals takes a long time.
1967 F10a
Figure 11. Settling Time with One Cap Averaging
1967 F10b
1966 F12
simply increasing the averaging capacitor. these errors for four of Linear Technology’s op amps. ential return for the circuitry that follows. the filter, thus the (relatively) low noise requirement. Figure 13. DC Accurate Post FilterFigure 12. Buffered Post Filter
1967 F12
1067 F13
edge makes for a better intuitive comparison. improves due to the initial speedup. double frequency output ripple is just 150mV. 3:1 or 216:1 for a 6:1 change in frequency. each possible with the other by scaling it accordingly. of scaling is shown in Table 2. Figure 15. Step Responses with 60Hz BurstFigure 14. Step Responses with 10Hz Burst
1967 F14
1967 F15
change in overall bandwidth as mentioned earlier. Figure 17. Peak Error vs Input Frequency with DC-Accurate Post Filter Figure 16. Peak Error vs Input Frequency with Buffered Post Filter
1967 F16
1967 F17
- ±32 using the same design curves presented in Figures 6, 8, 16 and 17. For the worst case of square top pulse trains, that are always either zero volts or the peak voltage, base the selection on the lowest fundamental input frequency divided by twice as much: f f CF DESIGN INPUT MIN= ()
- ±62 The effects of crest factor and DC offsets are cumulative. So for example, a 10% duty cycle pulse train from 0V PEAK to 1VPEAK (CF = Ö10 = 3.16) repeating at 16.67ms (60Hz) input is effectively only 30Hz due to the DC asymmetry and is effectively only: fH zDESIGN == 30 6 3 16 2 37 8
- . ± for the purposes of Figures 6, 8, 16 and 17. Obviously, the effect of crest factor is somewhat simplified above given the factor of two difference based on a subjective description of the waveform type. The results will vary somewhat based on actual crest factor and
Figure 19. Settling Time with DC-Accurate Post Filter Figure 18. Settling Time with Buffered Post Filter
1967 F18
1967 F19
waveform dynamics and the type of filtering used. The above method is conservative for some cases and about right for others. The LTC1967 works well with signals whose crest factor is 4 or less. At higher crest factors, the internal DS modulator will saturate, and results will vary depending on the exact frequency, shape and (to a lesser extent) ampli- tude of the input waveform. The output voltage could be higher or lower than the actual RMS of the input signal. The DS modulator may also saturate when signals with crest factors less than 4 are used with insufficient averag- ing. This will only occur when the output droops to less than 1/4 of the input voltage peak. For instance, a DC- coupled pulse train with a crest factor of 4 has a duty cycle of 6.25% and a 1V PEAK input is 250mVRMS. If this input is 50Hz, repeating every 20ms, and CAVE = 1mF, the output will droop during the inactive 93.75% of the waveform. This droop is calculated as: V V eMIN RMS INACTIVE TIME æ Ł çç ö ł Łç ö 2 1± 2 · Z · COUT AVE For the LTC1967, whose output impedance (Z OUT) is 50kW , this droop works out to – 8.54%, so the output would be reduced to 229mV at the end of the inactive portion of the input. When the input signal again climbs to PEAK, the peak/output ratio is 4.36. With CAVE = 10mF, the droop is only – 0.929% to 247.7mV and the peak/output ratio is just 4.038, which the LTC1967 has enough margin to handle without error. For crest factors less than 3.5, the selection of C AVE as previously described should be sufficient to avoid this droop and modulator saturation effect. But with crest factors above 3.5, the droop should also be checked for each design. Error Analyses Once the RMS-to-DC conversion circuit is working, it is time to take a step back and do an analysis of the accuracy of that conversion. The LTC1967 specifications include three basic static error terms, V OOS, VIOS and GAIN. The output offset is an error that simply adds to (or subtracts APPLICATIO S I FOR ATIOWU UU from) the voltage at the output. The conversion gain of the LTC1967 is nominally 1.000 VDCOUT/VRMSIN and the gain error reflects the extent to which this conversion gain is not perfectly unity. Both of these affect the results in a fairly obvious way. Input offset on the other hand, despite its conceptual simplicity, effects the output in a nonobvious way. As its name implies, it is a constant error voltage that adds directly with the input. And it is the sum of the input and V IOS that is RMS converted. This means that the effect of V IOS is warped by the nonlinear RMS conversion. With 0.2mV (typ) VIOS, and a 200mVRMS AC input, the RMS calculation will add the DC and AC terms in an RMS fashion and the effect is negligible: VOUT = Ö(200mV AC)2 + (0.2mV DC)2 = 200.0001mV = 200mV + 1/2ppm But with 10 · less AC input, the error caused by V IOS is 100· larger: VOUT = Ö(20mV AC)2 + (0.2mV DC)2 = 20.001mV = 20mV + 50ppm This phenomena, although small, is one source of the LTC1967’s residual nonlinearity. On the other hand, if the input is DC coupled, the input offset voltage adds directly. With +200mV and a +0.2mV VIOS, a 200.2mV output will result, an error of 0.1% or 1000ppm. With DC inputs, the error caused by VIOS can be positive or negative depending if the two have the same or opposing polarity. The total conversion error with a sine wave input using the typical values of the LTC1967 static errors is computed as follows: VOUT = (Ö(500mV AC)2 + (0.2mV DC)2) • 1.001 + 0.1mV = 500.600mV = 500mV + 0.120% VOUT = (Ö(50mV AC)2 + (0.2mV DC)2) • 1.001 + 0.1mV = 50.150mV = 50mV + 0.301%
so this represents the worst-case of usable input levels. tions cause additional errors with high frequency inputs. Performance Characteristics. inputs, provided a large enough averaging capacitor is used. quency in the Typical Performance Characteristics. frequency. This accounts for the 5MW input impedance. Figure 20. LTC1967 Equivalent Analog Input Circuit
1967 F20
APPLICATIO S I FOR ATIOWU UU devoted to sampling, ten time constants elapse. This allows each sample to settle to within 46ppm and it is these samples that are used to compute the RMS value. This is a much higher accuracy than the LTC1967 conver- sion limits, and far better than the accuracy computed via the simplistic resistive divider model: Output Impedance The LTC1967 output impedance during operation is simi- larly due to a switched capacitor action. In this case, 20pF of on-chip capacitance operating at 500kHz translates into 100kW . The closed-loop RMS-to-DC calculation cuts that in half to the nominal 50kW specified. In order to create a DC result, a large averaging capacitor is required. Capacitive loading and time constants are not an issue on the output. However, resistive loading is an issue and the 10M W impedance of a DMM or 10 · scope probe will drag the output down by –0.5% typ. During shutdown, the switching action is halted and a fixed 50k resistor shunts V OUT to OUT RTN so that CAVE is discharged. Interfacing with an ADC The LTC1967 output impedance and the RMS averaging ripple need to be considered when using an analog-to- digital converter (ADC) to digitize the LTC1967 RMS result. The simplest configuration is to connect the LTC1967 directly to the input of a type 7106/7136 ADC as shown in Figure 21a. These devices are designed specifically for DVM/DPM use and include display drivers for a 3 1/2 digit LCD segmented display. Using a dual-slope conversion, the input is sampled over a long integration window, which results in rejection of line frequency ripple when integra- tion time is an integer number of line cycles. Finally, these parts have an input impedance in the G W range, with specified input leakage of 10pA to 20pA. Such a leakage, combined with the LTC1967 output impedance, results in just 1mV to 2mV of additional output offset voltage. Another type of ADC that has inherent rejection of RMS averaging ripple is an oversampling DS ADC such as the LTC2420. Its input impedance is 6.5MW , but only when it is sampling. Since this occurs only half the time at most, if it directly loads the LTC1967, a gain error of –0.32% to –0.43% results. In fact, the LTC2420 DC input current is VV R RR V M Mk V IN SOURCE IN IN SOURCE SOURCE SOURCE = + = W W+ W 56 2 12 5–. % This resistive divider calculation does give the correct model of what voltage is seen at the input terminals by a parallel load averaged over a several clock cycles, which is what a large shunt capacitor will do—average the current spikes over several clock cycles. When high source impedances are used, care must be taken to minimize shunt capacitance at the LTC1967 input so as not to increase the settling time. Shunt capacitance of just 0.8pF will double the input settling time constant and the error in the above example grows from 46ppm to 0.67% (6700ppm). As a consequence, it is important to not try to filter the input with large input capacitances unless driven by a low impedance. Keep time constant < < 500ns. When the LTC1967 is driven by op amp outputs, whose low DC impedance can be compromised by sharp capaci- tive load switching, a small series resistor may be added. A 1k resistor will easily settle with the 0.8pF input sampling capacitor to within 1ppm. These are important points to consider both during design and debug. During lab debug, and even production testing, a high value series resistor to any test point is advisable.
not zero at 0V, but rather at one half its reference, so both an output offset and a gain error will result. These errors will vary from part to part, but with a specific LTC1967 and LTC2420 combination, the errors will be fixed, varying less than –0.05% over temperature. So a system that has digi- tal calibration can be quite accurate despite the nominal gain and offset error. With 20 bits of resolution, this part is more accurate than the LTC1967, but the extra resolu- tion is helpful because it reduces nonlinearity at the LSB transitions as a digital gain correction is made. Further- more, its small size and ease of use make it attractive. This connection is shown in Figure 21b, where the LTC2420 is set to continuously convert by grounding the CS pin. The gain error will be less if CS is driven at a slower rate, however, the rate should either be consistent or at a rate low enough that the LTC1967 and its output capacitor have fully settled by the beginning of each conversion, so that the loading errors are consistent. Other types of ADCs sample the input signal once and perform a conversion on that one sample. With these ADCs (Nyquist ADCs), a post filter will be needed in most cases to reduce the peak error with low input frequencies. The DC-accurate filter of Figure 13 is attractive from an error standpoint, but it increases the impedance at the ADC input. In most cases, the buffered post filter of Figure␣ 12 will be more appropriate for use with Nyquist analog-to- digital converters. SYSTEM CALIBRATION The LTC1967 static accuracy can be improved with end- system calibration. Traditionally, calibration has been done at the factory, or at a service depot only, typically using manually adjusted potentiometers. Increasingly, systems are being designed for electronic calibration where the accuracy corrections are implemented in digital code wherever possible, and with calibration DACs where necessary. Additionally, many systems are now designed for self calibration, in which the calibration occurs inside the machine, automatically without user intervention. Whatever calibration scheme is used, the linearity of the LTC1967 will improve the calibrated accuracy over that achievable with older log/antilog RMS-to-DC converters. Additionally, calibration using DC reference voltages are essentially as accurate with the LTC1967 as those using AC reference voltages. Older log/antilog RMS-to-DC con- verters required nonlinear input stages (rectifiers) whose linearity would typically render DC-based calibration unworkable. The following are four suggested calibration methods. Implementations of the suggested adjustments are de- pendent on the system design, but in many cases, gain and output offset can be corrected in the digital domain, and will include the effect of all gains and offsets from the LTC1967 output through the ADC. Input offset voltage, on the other hand, will have to be corrected with adjustment to the actual analog input to the LTC1967. AC-Only, 1 Point The dominant error at full scale will be caused by the gain error, and by applying a full-scale sine wave input, this error can be measured and corrected for. Unlike older log/ antilog RMS-to-DC converters, the correction should be made for zero error at full scale to minimize errors through- out the dynamic range. The best frequency for the calibration signal is roughly ten times the –0.1% DC error frequency. For 1mF, –0.1% DC error occurs at 10Hz, so 100Hz is a good calibration frequency, although anywhere from 60Hz to 100Hz should suffice. APPLICATIO S I FOR ATIOWU UU Figure 21a. Interfacing to DVM/DPM ADC Figure 21b. Interfacing to LTC2420 CAVE LTC1967 OUTPUT OUT RTN
7106 TYPE
1967 F21a
1967 F21b
The trade-off here is that on the one hand, the DC error is input frequency dependent, so a calibration signal fre- quency high enough to make the DC error negligible should be used. On the other hand, as low a frequency as can be used is best to avoid attenuation of the calibrated AC signal, either from parasitic RC loading or insufficient op amp gain. For instance, with a 1kHz calibration signal, a 1MHz op amp will typically only have 60dB of open-loop gain, so it could attenuate the calibration signal a full 0.1%. AC-Only, 2 Point The next most significant error for AC-coupled applica- tions will be the effect of output offset voltage, noticeable at the bottom end of the input scale. This too can be calibrated out if two measurements are made, one with a full-scale sine wave input and a second with a sine wave input (of the same frequency) at 10% of full scale. The trade-off in selecting this second level is that it should be small enough that the gain error effect becomes small compared to the gain error effect at full scale, while on the other hand, not using so small an input that the input offset voltage becomes an issue. The calculations of the error terms for a 200mV full-scale case are: Gain = Reading at 200mV ± Reading at 20mV 180mV Output Offset = Reading at 20mV Gain ±2 0 m V DC, 2 Point DC-based calibration is preferable in many cases because a DC voltage of known, good accuracy is easier to gener- ate than such an AC calibration voltage. The only down side is that the LTC1967 input offset voltage plays a role. It is therefore suggested that a DC-based calibration scheme check at least two points: –full scale. Applying the –full-scale input can be done by physically inverting the voltage or by applying the same +full-scale input to the opposite LTC1967 input. For an otherwise AC-coupled application, only the gain term may be worth correcting for, but for DC-coupled applications, the input offset voltage can also be calcu- lated and corrected for. The calculations of the error terms for a 200mV full-scale case are: Gain = Reading at 200mV + Reading at ± 200mV 400mV Input Offset = Reading at ± 200mV ± Reading at 200mV 2 ·Gain Note: Calculation of and correction for input offset voltage are the only way in which the two LTC1967 inputs (IN1, IN2) are distinguishable from each other. The calculation above assumes the standard definition of offset; that a positive offset is the case of a positive voltage error inside the device that must be corrected by applying a like negative voltage outside. The offset is referred to which- ever pin is driven positive for the +full-scale reading. DC, 3 Point One more point is needed with a DC calibration scheme to determine output offset voltage: +10% of full scale. The calculation of the input offset is the same as for the 2-point calibration above, while the gain and output offset are calculated for a 200mV full-scale case as: Gain = Reading at 200mV ± Reading at 20mV 180mV Output Offset = Reading at 200mV +Reading at ± 200mV ± 400mV · Gain APPLICATIO S I FOR ATIOWU UU
APPLICATIO S I FOR ATIOWU UU TROUBLESHOOTING GUIDE Top Ten LTC1967 Application Mistakes 1. Circuit won’t work–Dead On Arrival–no power drawn. – Probably forgot to enable the LTC1967 by pulling Pin␣ 8 low. Solution: Tie Pin 8 to Pin 1. 2. Circuit won’t work, but draws power. Zero or very little output, single-ended input application. – Probably didn’t connect both input pins. Solution: Tie both inputs to something. See “Input Connections” in the Design Cookbook. 4. Gain is low by a few percent, along with other screwy results. – Probably tried to use output in a floating, differential manner. Solution: Tie Pin 6 to a low impedance. See “Output Connections” in the Design Cookbook. LTC1967 CONNECT PIN 3 IN12 3NC IN2 1967TS02 LTC1967 IN12
3 IN2
1967 TS03
- Screwy results, particularly with respect to linearity or high crest factors; differential input application. – Probably AC-coupled both input pins. Solution: Make at least one input DC-coupled. See “Input Connections” in the Design Cookbook. TYPE 7136 ADC LTC1967 HI31 6 LO VOUT OUT RTN
1967 TS04
- Offsets perceived to be out of specification because 0V in „ 0V out. – The offsets are not specified at 0V in. No RMS-to- DC converter works well at 0 due to a divide-by-zero calculation. Solution: Measure VIOS/VOOS by extrapolating read- ings > –5mVDC. 6. Linearity perceived to be out of specification particu- larly with small input signals. – This could again be due to using 0V in as one of the measurement points. Solution: Check Linearity from 5mV RMS to 500mVRMS. – The input offset voltage can cause small AC linear ityerrors at low input amplitudes as well. See “Error Analyses” section. Possible Solution: Include a trim for input offset.
APPLICATIO S I FOR ATIOWU UU 7. Output is noisy with >50kHz inputs. – This is a fundamental characteristic of this topol- ogy. The LTC1967 is designed to work very well with inputs of 20kHz or less. It works okay as high as 1MHz, but it is limited by aliased DS noise. Solution: Bandwidth limit the input or digitally filter the resulting output. 8. Large errors occur at crest factors approaching, but less than 4. – Insufficient averaging. Solution: Increase CAVE. See “Crest Factor and AC + DC Waveforms” section for discussion of output droop. 9. Screwy results, errors > spec limits, typically 1% to 5%. – High impedance (50k W ) and high accuracy (0.1%) require clean boards! Flux residue, finger grime, etc. all wreak havoc at this level. Solution: Wash the board. 10. Gain is low by @ 1% or more, no other problems. – Probably due to circuit loading. With a DMM or a 10· scope probe, Z IN = 10M W . The LTC1967 output is 50k W , resulting in – 0.5% gain error. Output impedance is higher with the DC accurate post filter. Solution: Remove the shunt loading or buffer the output. – Loading can also be caused by cheap averaging capacitors. Solution: Use a high quality metal film capacitor for CAVE. LTC1967 KEEP BOARD CLEAN
1967 TS09
–0.5% DMM DCV LTC1967 10M 50k VOUT OUT RTN
1967 TS10
5V Single Supply, Differential, AC-Coupled RMS-to-DC Converter Single Supply RMS Current Measurement LTC1967 IN1 DC OUTPUT CAVE 1µF CC 0.1µF IN2
1967 TA02
(1VPEAK DIFFERENTIAL) OUT RTN GND EN LTC1967 IN1 VOUT = 4mVDC/ARMSCAVE 1µF 0.1µF IN2
1967 TA03
10Ω T1: CR MAGNETICS CR8348-2500-N www.crmagnetics.com 2nd ORDER ∆S MODULATOR IN1 IN2 EN OUTPUT OUT RTN 50k BLEED RESISTOR FOR C AVE CAVE 1967 SS TO BIAS CONTROL GND Y1 Y2 C12 C11 CLOSED DURING SHUTDOWN C10 C5C3 A2A1
(Reference LTC DWG # 05-08-1660) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. MSOP (MS8) 0204 0.53 – 0.152 (.021 – .006) SEATING PLANE NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.18 (.007) 0.254 (.010) 1.10 (.043) MAX 0.22 – 0.38 (.009 – .015) TYP 0.127 – 0.076 (.005 – .003) 0.86 (.034) REF 0.65 (.0256) BSC 0° – 6° TYP DETAIL “A” DETAIL “A” GAUGE PLANE 12 3 4 4.90 – 0.152 (.193 – .006) 8 7 6 5 3.00 – 0.102 (.118 – .004) (NOTE 3) 3.00 – 0.102 (.118 – .004) (NOTE 4) 0.52 (.0205) REF 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.889 – 0.127 (.035 – .005) RECOMMENDED SOLDER PAD LAYOUT 0.42 – 0.038 (.0165 – .0015) TYP 0.65 (.0256) BSC TYPICAL APPLICATIO SU –2.5V Supplies, Single Ended, DC-Coupled RMS-to-DC Converter with Shutdown RMS Noise Measurement 2.5V –2.5V –2.5V LTC1967 IN1 DC OUTPUT CAVE 1µF 0.1µF X7R IN2
1967 TA04
(1VPEAK) OUT RTN GND EN OFF‡2V ≤–2VON V+ 2.5V –2.5V 2.5V –2.5V LTC1967 IN1 CAVE 1µF 0.1µF 1.5µF IN2
1967 TA05
1µVRMS NOISEVOUT = 100Ω 100Ω 100k BW ≈ 1kHz TO 100kHz INPUT SENSITIVITY = 1µVRMS TYP LTC6203
ª LINEAR TECHNOLOGY CORPORATION 2004 LT/TP 0504 1K • PRINTED IN USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 l FAX: (408) 434-0507 l www.linear.com RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT
1077 Micropower, Single Supply Precision Op Amp 48 mA ISY, 60mV VOS(MAX), 450pA IOS(MAX)
LT1175-5 Negative, –5V Fixed, Micropower LDO Regulator 45 mA IQ, Available in SO-8 or SOT-223 LT1494 1.5 mA Max, Precision Rail-to-Rail I/O Op Amp 375 mV VOS(MAX), 100pA IOS(MAX) LT1782 General Purpose SOT-23 Rail-to-Rail Op Amp 40 mA ISY, 800mV VOS(MAX), 2nA IOS(MAX) LT1880 SOT-23 Rail-to-Rail Output Precision Op Amp 1.2mA I SY, 150mV VOS(MAX), 900pA IOS(MAX) LTC2054 Zero Drift Op Amp in SOT-23 150 mA ISY, 3mV VOS(MAX), 150pA IB(MAX) LT2178/LT2178A 17 mA Max, Single Supply Precision Dual Op Amp 14 mA ISY, 120mV VOS(MAX), 350pA IOS(MAX) LTC1966 Precision Micropower DS RMS-to-DC Converter 155 mA ISY LTC2402 2-Channel, 24-bit, Micropower, No Latency DS TM ADC 200 mA ISY, 4ppm INL, 10ppm TUE LTC2420 20-bit, Micropower, No Latency DS ADC in SO-8 200 mA ISY, 8ppm INL, 16ppm TUE LTC2422 2-Channel, 20-bit, Micropower, No Latency DS ADC Dual channel version of LTC2420 No Latency DS is a trademark of Linear Technology Corporation. Audio Amplitude Compressor TYPICAL APPLICATIO U 2.49k 100k VIN 7.5k 5.9k R15 47Ω VFS 0.47µF 47nF LT1256 V– V+ VOUT 0.1µF R13 3.3k R14 3.3k R FS RC VC R10 200k R12 10k 10k 15k LT1636 ATTENUATION CONTROL GAIN OF 4 ATTENUATE BY 1/4 5.9k 0.22µF 0.33µF LTC1967 VS = –5V
1967 TA07
0.1µF