LTM9100

LTM9100 (Rev. A)

Document overview

• Manufacturer or author: Analog Devices Inc.
• PDF pages: 54

Technical content

Rev. AFor more information www.analog.comDocument Feedback TYPICAL APPLICATION FEATURES DESCRIPTION Anyside™ High Voltage Isolated Switch Contr oller with I2C Command and Telemetry The LT M®9100 µModule® (micromodule) controller is a complete, galvanically isolated switch controller with I2C interface, for use as a load switch or hot swap controller. The load is soft started and controlled by an external N-channel MOSFET switch. Overcurrent protection minimizes MOSFET stress during start-up, input step and output short-circuit conditions. Owing to the isolated, floating character of the switch, it is easily configured for use in high side, low side and floating applications. A single 5V supply powers both sides of the switch con- troller through an integrated, isolated DC/DC converter. A separate logic supply input allows easy interfacing with logic levels from 3V to 5.5V, independent of the main supply. Isolated measurements of load current and two additional voltage inputs are made by a 10-bit ADC, and accessed via the I2C interface. The logic and I2C interface is separated from the switch controller by a 5 kVRMS isolation barrier, making the LTM9100 ideal for systems where the switch operates on buses up to 1000V DC, as well as for providing galvanic isolation in systems where a ground path is broken to al- low large common mode voltage swings. Uninterrupted communication is guaranteed for common mode transients of up to 30kV/μs. 270V Load Soft-Start

APPLICATIONS

n CSA (IEC/UL) Approved, File #255632 n Reinforced Insulation n Integrated Isolated Power Supply n Adjustable Turn-On Ramp Rate and Current Limit n I2C/SMBus Interface n 10-Bit ADC Monitors Current and T wo Uncommitted Channels n High Common Mode T ransient Immunity: ≥ 30kV/μs n Fault Status Alert and Power Good Outputs n Independent 3V to 5.5V Logic Supply n ±20kV ESD Across the Isolation Barrier n Maximum Continuous Working Voltage: 690VRMS n 14.6mm Creepage Distance n Low Current Shutdown Mode (<10µA) n 22mm × 9mm × 5.16mm BGA Package n High Voltage DC Hot Swap n Live Backplane Insertion n Isolated Distributed Power Systems n Power Monitors n Industrial Control Systems n Breaking Ground Loops Isolated High Side Load Switch Driver 10nF , 400V 100µF 400V LOAD(s) 0.01/uni03A9 FDA50N50 VCC VL ON SCL SDA 1.5k GND EN ISOLATION BARRIER RAMP VCC2 UVH UVL SENSE– OV VEE SENSE+ DRAIN GATE PINS NOT USED IN THIS CIRCUIT : ADIN, ADIN2, ADR0, ADR1, ALERT, ALERT2, EN2, PG, PG2, PGIO, SCL2, SDA2, SS, TMR, VS LTM9100 GATE ENABLE 270V 270V RTN

9100 TA01a

V LOAD 100V/DIV PG 5V/DIV I LOAD 200mA/DIV

9100 TA01b

All registered trademarks and trademarks are the property of their respective owners.

Rev. A For more information www.analog.com TABLE OF CONTENTS T

Description

T T O µM D P Lo H S H Ch I P T T O O U ndervoltage Comparator and Undervoltage F E F Res D Co D De D E B N Pa DC B I S S Ac W A S R R P T T

Rev. AFor more information www.analog.com PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS PG, ALERT, EN, SDA, SCL, 0.3V to (VL + 0.3V) SCL2, SDA2, ADR0, ADR1, ALERT2, PG2, ADIN, ADIN2, RAMP, OV, SS, EN2, (Notes 1, 2) VL VCCON SCL SDA EN ALERT PG GND BGA PACKAGE 42-LEAD (22mm × 9mm × 5.16mm) TJMAX = 125°C, PCB = JESD51-9 2s2p: θJA = 25.6°C/W , θJCtop = 24.8°C/W , θJCbottom = 11.7°C/W , θJB = 12.1°C/W HEAT FLOW: θJA = NORMAL, θJCtop = 100%, θJCbottom = 100%, θJB = 100% WEIGHT = 2g TOP VIEW A B C D E F G H J K L M N P R S T SENSE+ GATE DRAIN RAMP OV UVH UVL ALERT2 EN2 SDA2 SCL2 PGIO SS TMR ADR1 ADIN2 ADR0 VEE ADIN VCC2VS SENSE–VEEPG2 Ambient Operating Temperature Range (Note 5) °C to 70°C 40°C to 85°C 0°C to 105°C 5°C 55°C to 125°C 5°C ORDER INFORMATION PART NUMBER PAD OR BALL FINISH PART MARKING PACKAGE TYPE MSL RA TING TEMPERATURE RANGEDEVICE FINISH CODE LTM9100CY#PBF SAC305 (RoHS) LTM9100Y e1 BGA 3 0°C to 70°C LTM9100IY#PBF –40°C to 85°C LTM9100HY#PBF –40°C to 105°C

• Device temperature grade is indicated by a label on the shipping container.
• Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Contact the factor y for parts specified with wider operating temperature ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Terminal Finish Part Marking: Material Declarations|Analog Devices
• Recommended LGA and BGA PCB Assembly and Manufacturing Procedures LGA and BGA Package and Tray Drawings
• This product is moisture sensitive. For more information, go to: Assembly Considerations for Analog Devices µModule LGA & BGA Packages
• This product is not recommended for second side reflow. For more information, go to: Assembly Considerations for Analog Devices µModule LGA & BGA Packages

Rev. A For more information www.analog.com

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supplies VCC Input Supply Range l 4.5 5.5 V ICC Input Supply Current ON = 0V ON = VL, No Load l l µA mA VL Logic Input Supply Range l 3 5.5 V Logic Input Supply Current ON = 0V ON = VL l l 3.2 4.5 µA mA VL Undervoltage Lockout Threshold V L Rising l 2.3 2.7 V VL Undervoltage Lockout Hysteresis 100 mV VS Regulated Output Voltage I LOAD = 0mA to 35mA l 9.65 10.4 11.15 V VZ Shunt Regulator Voltage at VS IS = 10mA, VCC = 0V l 10.4 11.2 12 V Shunt Regulator Load Regulation I S = 10mA to 25mA, VCC = 0V l 370 600 mV IS VS Supply Current VS = 10.4V, VCC = 0V l 7 12 mA VS Undervoltage Lockout Threshold VS Rising, VCC = 0V l 8.5 9 9.5 V VS Undervoltage Lockout Hysteresis VCC = 0V l 0.3 0.7 1.1 V VCC2 Regulated Output Voltage I LOAD = 0mA to 15mA l 4.75 5 5.25 V Gate Drive (EN = VL, UVL = UVH = VCC2, OV = 0V, unless otherwise noted) VGATEH GATE Pin Output High Voltage V S = 10.4V, VCC = 0V l 9.75 10 10.25 V IGATE(UP) GATE Pin Pull-Up Current V GATE = 4V l –7.5 –11.5 –15.5 µA IGATE(OFF) GATE Turn-Off Current VSENSE = 400mV, VGATE = 4V EN = 0V, VGATE = 4V l l 120 100 175 150 250 mA mA t PHL(SENSE) SENSE High to Current Limit Propagation Delay V SENSE = 100mV to GATE Low VSENSE = 300mV to GATE Low l l 0.5 0.2 1.5 0.5 µs µs GATE Off Propagation Delay EN ↓ to GATE Low OV↑, UVL↓ to GATE Low l l 0.2 1.4 0.5 µs µs Circuit Breaker Gate Off Delay VSENSE = 300mV to PG2↑ l 440 530 620 µs IRAMP RAMP Pin Current VSS = 2.56V l –18 –20 –22 µA VSS SS Pin Clamp Voltage l 2.43 2.56 2.69 V SS Pin Pull-Up Current VSS = 0V l –7 –10 –13 µA SS Pin Pull-Down Current EN = 0V, V SS = 2.56V l 6 12 20 mA Input Pins EN, ON Input Threshold Voltage l 0.33 • VL 0.67 • VL V EN, ON Input Hysteresis (Note 6) 150 mV VUVH(TH) UVH Threshold Voltage VUVH Rising l 2.518 2.56 2.598 V VUVL(TH) UVL Threshold Voltage VUVL Falling l 2.248 2.291 2.328 V ∆VUV(HYST) UV Hysteresis UVH and UVL Tied Together l 236 269 304 mV δVUV UVH, UVL Hysteresis 15 mV UVL Reset Threshold Voltage V UVL Falling l 1.12 1.21 1.30 V UVL Reset Hysteresis 60 mV VOV(TH) OV Pin Threshold Voltage V OV Rising l 1.735 1.770 1.805 V The l denotes the specifications which apply over the specified operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VL = 3.3V, and GND = VEE = 0V, ON = VL unless otherwise noted.

Rev. AFor more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VL = 3.3V, and GND = VEE = 0V, ON = VL unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS OV Pin Hysteresis l 18 37.5 62 mV Current Limit Sense Voltage Threshold SENSE+ – SENSE– l 45 50 55 mV PGIO Pin Input Threshold Voltage V PGIO Rising l 1.10 1.25 1.40 V PGIO Pin Input Hysteresis 100 mV Input Current ON, EN, UVH, UVL, OV, SENSE+ SENSE– l l –10 –20 µA µA Timer TMR Pin High Threshold VTMR Rising l 2.43 2.56 2.69 V TMR Pin Low Threshold VTMR Falling l 40 75 110 mV TMR Pin Pull-Up Current Turn-On and Auto-Retry (Except OC) Delays, VTMR = 0.2V l –7 –10 –13 µA Power Good and OC Auto-Retry Delays, VTMR = 0.2V l –3.5 –5 –7 µA TMR Pin Pull-Down Current Delays Except OC Auto-Retry, V TMR = 2.56V l 6 12 20 mA OC Auto-Retry Delays, VTMR = 2.56V l 3 5 7 µA Output Pins VOH Output High Voltage ALERT, ILOAD = –4mA, PG, ILOAD = –2mA l VL – 0.4 V VOL Output Low Voltage ALERT, ILOAD = 4mA, PG, ILOAD = 2mA PGIO, ILOAD = 3mA ALERT2, PG2, PGIO, ILOAD = 500µA l l l 0.8 0.15 0.4 1.6 0.4 V V V Input Current PGIO = 80V l 0 10 µA Short-Circuit Current 0V ≤ ALERT ≤ VL 0V ≤ PG ≤ VL 0V ≤ ALERT2, PG2 ≤ VCC2 0V ≤ EN2 ≤ VCC2 l l ±30 ±30 ±85 mA mA mA mA ADC Resolution (No Missing Codes) (Note 6) l 10 Bits INL Integral Nonlinearity SENSE ADIN, ADIN2 l l ±0.5 ±0.25 ±2.5 ±1.25 LSB LSB Offset Error SENSE ADIN, ADIN2 l l ±2.25 ±1.25 LSB LSB Full-Scale V oltage SENSE ADIN, ADIN2 l l 62.8 2.514 2.560 65.2 2.606 mV V Total Unadjusted Error SENSE ADIN, ADIN2 l l ±1.8 ±1.6 Conversion Rate l 5.5 7.3 9 Hz ADIN, ADIN2 Pin Input Resistance ADIN, ADIN2 = 1.28V l 2 10 MΩ ADIN, ADIN2 Pin Input Current ADIN, ADIN2 = 2.56V l 0 ±2 µA I2C Interface ADR0, ADR1 Input High Threshold l VCC2 – 0.8 V CC2 – 0.5 V CC2 – 0.3 V ADR0, ADR1 Input Low Threshold l 0.3 0.5 0.8 V ADR0, ADR1 Input Current ADR0, ADR1 = 0V, V CC2 ADR0, ADR1 = 0.8V, (VCC2 – 0.8V) l l ±10 ±80 µ A µA Input Threshold V oltage SCL, SDA SDA2 l l 0.3 • VL 0.3 • VCC2 0.7 • VL 0.7 • VCC2 V V

Rev. A For more information www.analog.com SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Input Current SCL, SDA = VL or 0V l ±2 µA Input Hysteresis SCL, SDA SDA2 0.05 • VL 0.05 • VCC2 mV mV VOH Output High Voltage SCL2, ILOAD = –2mA l VCC2 – 0.4 V VOL Output Low Voltage SDA, ILOAD = 3mA, SCL2, ILOAD = 2mA SDA2, No Load, SDA = 0V l l 0.4 0.45 V V Input Pin Capacitance SCL, SDA, SDA2 (Note 6) l 10 pF Bus Capacitive Load SCL2, Standard Speed (Note 6) SCL2, Fast Speed SDA, SDA2, SR ≥ 1V/µ s, Standard Speed (Note 6) SDA, SDA2, SR ≥ 1V/µs, Fast Speed l l l l 400 200 400 200 pF pF pF pF Minimum Bus Slew Rate SDA, SDA2 1 V/µs Short-Cir cuit Current SDA2 = 0, SDA = VL 0V ≤ SCL2 ≤ VCC2 SDA = 0, SDA2 = VCC2 SDA = VL, SDA2 = 0 l ±30 –1.8 100 mA mA mA mA ESD (HBM) (Note 6) Isolation Boundary (VCC2, VS, VEE) to (VCC, VL, GND) in Any Combination ±20 kV Isolated Side Interface Pins GATE to (V S, VEE) in Any Combination (RAMP, DRAIN, SENSE+, SENSE–) to (VCC2, VEE) in Any Combination ±8 kV All Other Pins ±3.5 kV ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VL = 3.3V, and GND = VEE = 0V, ON = VL unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Logic Timing tPHL, tPLH Propagation Delay (PG2, ALERT2) to (PG, ALERT), CL = 15pF (Figure 1) EN to EN2 (0.5 • VL to 0.1 • VCC2), CL = 15pF (Figure 1) l 35 60 150 ns tR, tF Rise and Fall Time ALERT, CL = 15pF (Figure 1) PG, CL = 15pF (Figure 1) l l ns ns t PZH, tPZL ON Enable Time ON↑ to (PG, ALERT), RL = 1kΩ, CL = 15pF (Figure 2) l 320 µs tPHZ, tPLZ ON Disable Time ON↓ to (PG, ALERT), RL = 1kΩ, CL = 15pF (Figure 2) l 70 ns I2C Interface Timing Maximum Data Rate (Note 7) l 400 kHz tPHL, tPLH Propagation Delay SCL to SCL2, CL = 15pF (Figure 1) SDA to SDA2, RL = Open, CL = 15pF (Figure 3) SDA2 to SDA, RL = 1.1kΩ, CL = 15pF (Figure 3) l l l 150 150 300 225 250 500 ns ns ns Low Period of SCL Clock (Note 6) 1.3 µs SWITCHING CHARACTERISTICS The l denotes the specifications which apply over the specified operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VL = 3.3V, and GND = VEE = 0V, ON = VL unless otherwise noted.

Rev. AFor more information www.analog.com SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS High Period of SCL Clock (Note 6) 600 ns Hold Time (Repeated) Start (Note 6) 600 ns Set-Up Time Repeated Start (Note 6) 600 ns tHD(DAT) Data Hold Time (Note 6) 600 ns tSU(DAT) Data Set-Up Time (Note 6) 100 ns Set-Up Time for Stop (Note 6) 600 ns Stop to Start Bus Free Time (Note 6) 1.3 µs tR Rise Time SDA2, CL = 200pF (Figure 3) SDA, RL = 1.1kΩ, CL = 200pF (Figure 3) SCL2, CL = 200pF (Figure 1) l l l 350 250 250 ns ns ns t F Fall Time SDA2, CL = 200pF (Figure 3) SDA, RL = 1.1kΩ, CL = 200pF (Figure 3) SCL2, CL = 200pF (Figure 1) l l l 250 250 250 ns ns ns t PZL ON Enable Time ON↑ to SDA, RL = 1kΩ, CL = 15pF (Figure 2) l 320 µs tPLZ ON Disable Time ON↓ to SDA, RL = 1kΩ, CL = 15pF (Figure 2) l 70 ns Pulse Width of Spikes Suppressed by Input Filter SDA, SDA2, SCL l 0 50 ns Power Supply Power-Up Time ON↑ to VS (Min) ON↑ to VCC2 (Min) l l 0.2 0.2 1.5 ms ms SWITCHING CHARACTERISTICS The l denotes the specifications which apply over the specified operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VL = 3.3V, and GND = VEE = 0V, ON = VL unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Rated Dielectric Insulation Voltage 1 Minute, Derived from 1 Second Test

1 Second (Notes 8, 9)

Common Mode T ransient Immunity V CC = VL = ON = 5V, ∆VCM = 1kV, ∆t = 33ns (Note 6) 30 50 kV/µs VIORM Maximum Continuous Working Voltage (Notes 6,10) 1000 690 VPEAK VRMS Partial Discharge VPD = 1840VPEAK (Note 8) 5 pC CTI Comparative T racking Index IEC 60112 (Note 6) 600 VRMS Depth of Erosion IEC 60112 (Note 6) 0.017 mm DTI Distance Through Insulation (Note 6) 0.2 mm Input to Output Resistance (Notes 6, 8) 1 5 TΩ Input to Output Capacitance (Notes 6, 8) 5 pF Creepage Distance (Note 6) 14.6 mm ISOLATION CHARACTERISTICS Specifications are at TA = 25°C.

Rev. A For more information www.analog.com Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive; all voltages are referenced to 0V unless otherwise noted. Note 3: An internal shunt regulator limits the V S pin to a minimum of 10.65V. Driving this pin to voltages beyond 10.65V may damage the part. The pin can be safely tied to higher voltages through a resistor that limits the current to less than 50mA. Note 4: An internal clamp limits the DRAIN pin to a minimum of 3.5V. Driving this pin to voltages beyond the clamp may damage the part. The pin can be safely tied to higher voltages through a resistor that limits the current to less than 2mA. Note 5: This µModule includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above specified maximum operating junction temperature may result in device degradation or failure. Thermal shutdown will result in the loss of the internally generated supply voltages (V S and VCC2) and subsequent shutdown of the GATE pin. Thermal shutdown is not internally latched, the part will automatically restart once the junction temperature decreases and start-up conditions are met. Note that any I data configuration is lost on power failure. Note 6: Guaranteed by design and not subject to production test. Note 7: Maximum data rate is guaranteed by other measured parameters and is not tested directly. Note 8: Device is considered a 2-terminal device. Pin group A1 through B7 shorted together and pin group P1 through T7 shorted together. Note 9: The rated dielectric insulation voltage should not be interpreted as a continuous voltage rating. Note 10: The DC continuous working voltage is equivalent to the peak value. Note 11: Ratings are for pollution degree 2, material group 3 and overvoltage category II where applicable. Ratings for other environmental and electrical conditions to be determined from the appropriate safety standard. REGULATORY INFORMATION CSA (Note 11) CSA 60950-1-07+A1+A2 and IEC 60950-1, second edition, +A1 +A2: Basic Insulation at 1440VRMS Reinforced Insulation at 720VRMS CSA 62368-1-14 and IEC 62368-1-14:2014, second edition: Basic Insulation at 600VRMS Reinforced Insulation at 300VRMS UL 1577-2015: Single Protection, 5000VRMS Isolation Voltage File 255632

Rev. AFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS VS Efficiency and Power Loss vs Load Current VCC2 Output Voltage vs Load Current VCC2 Output Voltage vs Temperature Gate Output High Voltage vs Temperature Gate Turn-Off Current vs SENSE Voltage V CC Supply Current vs Temperature VS Output Voltage vs Load Current VS Output Voltage vs Temperature TEMPERATURE (°C) –50 –25 100 125 I CC CURRENT (mA)

9100 G01

LOAD CURRENT (mA) 100 125 150 8.50 8.75 9.00 9.25 9.50 9.75 10.00 10.25 10.50 OUTPUT VOL TAGE (V)

9100 G02

V CC = 4.5V V CC = 5V V CC = 5.5V TEMPERATURE (°C) –50 –25 100 125 9.5 9.8 10.1 10.4 10.7 11.0 VOL TAGE (V)

9100 G03

V CC = 4.5V V CC = 5V V CC = 5.5V LOAD CURRENT (mA) 100 200 0.3 0.6 0.9 1.1 1.4 1.7 2.0 EFFICIENCY (%) POWER LOSS (W)

9100 G04

Gate Pull-Up Current vs Gate Voltage T A = 25°C, unless otherwise noted. VSENSE (mV) IGATE(OFF) (mA) 100

9100 G09

VGATE = 4V LOAD CURRENT (mA) 4.90 4.92 4.94 4.96 4.98 5.00 5.02 5.04 5.06 OUTPUT VOL TAGE (V)

9100 G05

TEMPERATURE (°C) –50 –25 100 125 4.90 4.92 4.94 4.96 4.98 5.00 5.02 5.04 5.06 OUTPUT VOL TAGE (V)

9100 G06

V S = 10.4V TEMPERATURE (°C) –50 –25 100 125 9.7 9.8 9.9 10.0 10.1 10.2 VGATEH (V)

9100 G07

GATE VOL TAGE (V) –10 –12 IGATE(UP) (µA)

9100 G08

Rev. A For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS OV Threshold vs Temperature OV Hysteresis vs Temperature Current Limit Voltage vs Temperature Current Limit Propagation Delay PHL(SENSE)) vs VSENSE Logic Input Threshold vs VL Supply Voltage Ramp Pin Current vs Temperature UVH Threshold vs Temperature UVL Threshold vs Temperature TEMPERATURE (°C) –50 –25 100 125 OV HYSTERESIS (mV)

9100 G14

TEMPERATURE (°C) –50 –25 100 125 48.0 48.5 49.0 49.5 50.0 50.5 51.0 CURRENT LIMIT SENSE VOL TAGE (mV)

9100 G15

VSENSE (mV) tPHL(SENSE) (ns) 400

9100 G16

CGATE = 1pF PGIO, T A = 25°C PGIO, T A = 100°C PG2 , T A = 25°C PG2 , T A = 100°C LOAD CURRENT (mA) OUTPUT VOL TAGE (V)

9100 G17

TA = 25°C, unless otherwise noted. TEMPERATURE (°C) –50 –25 100 125 –18.0 –18.5 –19.0 –19.5 –20.0 –20.5 –21.0 IRAMP (µA)

9100 G10

TEMPERATURE (°C) –50 –25 100 125 2.545 2.550 2.555 2.560 2.565 2.570 2.575 VUVH(TH) (V)

9100 G11

TEMPERATURE (°C) –50 –25 100 125 2.285 2.290 2.295 2.300 2.305 2.310 2.315 VUVL(TH) (V)

9100 G12

TEMPERATURE (°C) –50 –25 100 125 1.755 1.760 1.765 1.770 1.775 1.780 1.785 VOV(TH) (V)

9100 G13

VL SUPPL Y VOL TAGE (V) THRESHOLD VOL TAGE (V) 3.5 2.5 0.5 1.0 2.0 3.0 1.5 5 5.53.5 4

9100 G18

64.5 INPUT RISING INPUT FALLING PG2, PGIO Output Low Voltage vs Load Current

Rev. AFor more information www.analog.com ADC INL vs Code (ADIN Pin) ADC DNL vs Code (ADIN Pin) Input Current vs Shunt Regulator Voltage Power-On Sequence Logic Output Voltage vs Load Current ADC Total Unadjusted Error vs Code (ADIN Pin) ADC Full-Scale Error vs Temperature (ADIN Pin) TYPICAL PERFORMANCE CHARACTERISTICS CODE ADC TOTAL UNADJUSTED ERROR (LSB) 0.5 1024

9100 G20

–0.5 –1.0 256 512 768 1.0 TEMPERATURE (°C) –50 –25 100 125 ADC FULL–SCALE ERROR (LSB)

9100 G21

ADC INL (LSB) 0.5 1024

9100 G22

–0.5 –1.0 256 512 768 1.0 CODE ADC DNL (LSB) 0.5 1024

9100 G23

–0.5 –1.0 256 512 768 1.0 T A = –50°C T A = 25°C T A = 125°C SHUNT REGULATOR VOL TAGE AT V S (V) 9.8 10.2 10.6 11.0 11.4 11.8 INPUT CURRENT (mA)

9100 G24

TA = 25°C, unless otherwise noted. Derating for 125°C Maximum Internal Operating Temperature LOAD CURRENT (mA) OUTPUT VOL TAGE (V) 2 1 3

9100 G19

VL = 5.5V VL = 3.3V 60µs/DIV ON 5V/DIV V S 2.5V/DIV V CC2 2.5V/DIV

9100 G25

AMBIENT TEMPERATURE (°C) 100 125 100 150 200 250 300 350 400 450 500 I CC CURRENT (mA)

9100 G26

Rev. A For more information www.analog.com PIN FUNCTIONS Logic Side PG (A1): Power Good Status Output, Referenced to VL and GND. This logic pin pulls low and stays latched two timer delays after the isolated side power switch is on (when GATE reaches approximately 9.5V and DRAIN is within 1.77V of V EE). The power good output is reset in all GATE pull-down events except an overvoltage fault. Under the condition of an isolation communication failure this output is in a high impedance state. A communication failure may occur due to extreme electromagnetic events including common mode transients or electrical overstress. Com- munication is automatically re-established if permanent damage has not occurred. ALERT (A2): Fault Alert Output, Referenced to VL and GND. This logic pin pulls low when an isolated side fault occurs as configured by the I2C ALERT register. See Applications Information. Under the condition of an isolation commu- nication failure this output is in a high impedance state. EN ( A3): GATE Enable Input, Referenced to VL and GND. A rising edge turns on the isolated side GATE pin while a falling edge turns it off. This pin is also used to configure the state of bit 3 (GATE_CTRL) in the I 2C CONTROL (D) register (and hence the GATE pin) at power-up. For example if EN is tied high, then register bit D3 goes high one timer cycle after power-up. Likewise, if the EN pin is tied low, then the GATE pin remains low after power-up until the EN pin is transitioned high. The GATE pin may be controlled directly by I 2C via register bit D3. A high to low transition clears any driver faults. Connect to VL if not used. SDA (A4): Serial I2C Data Pin, Referenced to VL and GND. Bidirectional logic pin connected to isolated side SDA2 pin and configurable switch driver through isolation barrier. An external pull-up resistor or current source is required. Under the condition of an isolation communication failure this pin is in a high impedance state. Connect to VL if not used. SCL (A5): Serial I 2C Clock Pin, Referenced to V L and GND. Logic input connected to isolated side SCL2 pin and configurable switch driver through isolation barrier. An external pull-up resistor or current source is required. Connect to VL if not used. ON (A6): Module Enable Pin. Enables power and data communication through the isolation barrier. If ON is high the part is enabled and power and communications are functional to the isolated side. If ON is low the logic side is held in reset, all digital outputs are in a high impedance state, and the isolated side is unpowered. The ON pin may be used to enable the isolated side power switch driver by connecting EN to VL. A low to high transition of ON would then enable the isolated side gate drive after the internal isolated side supply voltage exceeds approximately 9V followed by a timer delay. Connect to V L if not used. VL (A7): Logic Supply. Interface supply voltage for pins PG, ALERT, EN, SDA, SCL, and ON. Operating voltage is 3V to 5.5V. Internally bypassed with 1µF. GND (B1 TO B5): Circuit Ground. V CC (B6, B7): Isolated Power Converter Supply Voltage. Operating voltage is 4.5V to 5.5V. Internally bypassed with 1µF. This pin may be left unconnected or grounded if VS is driven by an external voltage. Isolated Side PG2 (P1): Power Good Status Output, Referenced to V CC2 and VEE. This logic pin pulls low and stays latched two timer delays after the power switch is on (when GATE reaches approximately 9.5V and DRAIN is within 1.77V of VEE). The power good output is reset in all GATE pull-down events except an overvoltage fault. Internally connected to VCC2 by a 10k resistor. ALERT2 (P2): Fault Alert Output, Referenced to VCC2 and VEE. This logic pin pulls low when an isolated side fault occurs as configured by the I 2C ALERT register. See through a 10k resistor. EN2 (P3): Enable Output, Referenced to V CC2 and V EE. Logic output connected to logic side EN pin through isola- tion barrier and 4k resistor and to the switch driver. EN2 may be driven externally, see Applications Information. Internally connected to VEE through 4k and 10k resistors. SDA2 (P4): Serial I2C Data Pin, Referenced to V CC2 and VEE. Bidirectional logic pin connected to logic side SDA pin through isolation barrier and to the switch driver. Al- lows for I2C bus expansion. Output is biased high by a

Rev. AFor more information www.analog.com PIN FUNCTIONS 1.8mA current source. Under the condition of an isolation communication failure this output defaults to a high state. SCL2 (P5): Serial I2C Clock Output, Referenced to VCC2 and VEE. Logic output connected to logic side SCL pin through isolation barrier and to the switch driver. Allows for I2C bus expansion. Clock is unidirectional from logic to isolated side. Under the condition of an isolation communication failure this output defaults to a high state. PGIO (P6): General Purpose Input/Output. Logic input and open-drain output. Default is output which pulls low two timer delays after the PG pin goes low to indicate a second power good output. Configure according to Table 4. V S (P7): 10.4V Nominal Isolated Supply Output Voltage. Internally generated from VCC by an isolated DC/DC con- verter and regulated to 10.4V. V S may be driven by an external supply if V CC is not connected or grounded. If driven externally connect pin to a positive supply through a dropping resistor, see Applications Information. An internal shunt regulator clamps VS (VZ) at 11.2V. An undervoltage lockout (UVLO) circuit holds GATE low until VS is above 9V. Internally bypassed with 1µF. VEE (R1 to R3, R5 to R7): Isolated Circuit Common. ADR0, ADR1 (R4, S4): Serial Bus Address Inputs, Refer- enced to VCC2 and VEE. Connecting these pins to VEE, VCC2, or floating configures one of nine possible addresses. See Table 1 in Applications Information. SENSE– (S1): Negative Current Limit Sense Input. Kelvin connection for external current sense resistor (RS). Inter- nally filtered with 220pF. SS ( S2): Soft-Start Input. This pin is used to ramp inrush current during start-up, thereby effecting control over di/dt. Pin connected internally to a 220nF capacitor, additional external capacitance (CSS) may be added. An internal 10µA current source charges the internal and external capaci- tance creating a voltage ramp. This voltage is converted to a current to charge the GATE pin up and to ramp the output voltage down. The SS pin is internally clamped to 2.56V limiting IGATE(UP) to 11.5µA and IRAMP to 20µA. TMR (S3): Delay Timer Input. This pin is used to create timing delays at power-up, when power good outputs pull down and when auto-retrying after faults (except overvolt- age fault). Pin connected internally to a 47 nF capacitor, additional external capacitance (CTMR) may be added to extend the nominal delay beyond 12ms. Internal pull-up currents of 10µA and 5µA and pull-down currents of 5µA and 12mA configure the delay periods as multiples of a nominal delay tD = 12ms + 256ms • CTMR/µF. Delays for power-up and auto-retry following an undervoltage fault are the same as the nominal delay. Delays for sequenced power good outputs are twice the nominal delay. Delay for auto-retry following overcurrent fault are four times the nominal delay. ADIN2, ADIN (S5, S6): ADC Inputs, Referenced to V EE. A voltage between 0V and 2.56V applied to these pins is measured by the internal module ADC. Connect to VEE if unused. V CC2 (S7): 5V Nominal Isolated Supply Output Voltage. Linear regulated output generated from V S with a UVLO threshold of 4.25V. This voltage powers up the isolated data converter and logic control circuitry. Internally by - passed with 1µF. SENSE + (T1): Positive Current Limit Sense Input. Load current through an external current sense resistor (RS) is monitored and controlled by an active current limit amplifier to 50mV/RS. Once VSENSE reaches 50mV, a circuit breaker timer starts and turns off the switch after 530µs. In the event of a catastrophic short-circuit, if V SENSE crosses 250mV, a fast response comparator immediately pulls the GATE pin down to turn off the MOSFET. Internally filtered with 220pF. GATE (T2): N-Channel MOSFET Switch (FET) Gate Drive Output. This pin is pulled up by an internal current source IGATE (11.5µA when the SS pin reaches its clamping volt- age). GATE stays low until V S and VCC2 cross the UVLO thresholds, EN is high, UV and OV conditions are satisfied and the adjustable power-up timer delay expires. During turn-off, caused by faults or undervoltage lockout, a 110mA pull-down current between GATE and V EE is activated. Internally filtered with 220pF. Under the condition of an isolation communication failure the switch is turned off. DRAIN (T3): Drain Sense Input. Connect an external re - sistor between this pin and the drain terminal of the FET. Size the resistor for 50µA nominal current, do not exceed

Rev. A For more information www.analog.com PIN FUNCTIONS 2mA. The voltage at this pin is internally clamped to 4V. When the DRAIN pin voltage is less than 1.77V and the GATE pin voltage is approximately 9.5V the power good output is asserted after two timer delays. Internally filtered with 220pF. RAMP (T4): Inrush Current Ramp Control Pin. The inrush current is adjusted by placing a capacitor (C R) between the RAMP pin and the drain terminal of the FET. At start- up, the GATE pin is pulled up by I GATE(UP) until the FET begins to turn on. A current, I RAMP, then flows through CR to ramp down the drain voltage. The value of IRAMP is controlled by the SS pin voltage. When the SS pin reaches its clamp voltage (2.56V), IRAMP = 20µA. For a capacitive load the RAMP rate of the FET drain voltage (VDRAIN) and the load capacitor CL set the inrush current: IINRUSH = (CL /CR) • IRAMP. Internally filtered with 10nF; see Applications Information. OV (T5): Overvoltage Detection Input. Connect this pin to an external resistive divider from V EE. If the voltage at this pin rises above 1.77V, the FET is turned off. The overvoltage condition does not affect the status of the power good outputs. Internally filtered with 10nF. Connect to VEE if not used. UVH (T6): Undervoltage High Level Input. Connect this pin to an external resistive divider from VEE. If the voltage at the UVH pin rises above 2.56V and UVL is above 2.291V, the FET is allowed to turn on. Internally filtered with 10nF. Connect to VCC2 if not used. UVL (T7): Undervoltage Low Level Input. Connect this pin to an external resistive divider from VEE. If the voltage at the UVL pin drops below 2.291V and UVH is below 2.56V, the FET is turned off and the power good outputs go high. Pulling this pin below 1.21V resets faults and allows the FET to turn back on. Connect to VCC2 if unused.

Rev. AFor more information www.analog.com BLOCK DIAGRAM 1µF 1µF 10k 10k 1µF 220pF 220nF 47nF V CC V L GND ON SCL SDA EN PG ALERT DC/DC CONVERTER VCC ISOLATED COMMUNICATIONS INTERFACE ISOLATION BARRIER V L ISOLATED COMMUNICATIONS INTERFACE REGULATOR ALERT2 PG2 SDA2 SCL2 9100 BD EN2 VCC2 VEE V S ADR0 ADR1 ADIN ADIN2 PGIO TMR 220pF 220pF 220pF SS SWITCH CONTROLLER UVL UVH OV RAMP DRAIN GATE SENSE+ SENSE– 10nF 10k 10nF 10nF 61.9k 8.2k 1µF

Figure 3. I2C Timing Measurements Figure 1. Logic Timing Measurements Figure 2. ON Enable/Disable Time

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Rev. AFor more information www.analog.com Overview The LTM9100 µModule switch controller provides a galvanically-isolated robust driver interface, complete with decoupling capacitors. The LTM9100 is ideal for use in networks where grounds can take on different voltages. Isolation in the LTM9100 blocks high voltage differences and eliminates ground loops and is extremely tolerant of common mode transients between ground planes. Error- free operation is maintained through common-mode events as fast as 70kV/μs providing excellent noise isolation. The LTM9100 is designed to turn a supply voltage on and off in a controlled manner. In normal operation after initial power up and time delay (TMR), the GATE pin turns on a FET passing power to the load. The GATE pin is powered by an internal isolated DC/DC converter with output volt- age (VS) of approximately 10.4V. An amplifier connected to the SENSE pins is used for overcurrent and short-circuit protection. It monitors the load current through an external sense resistor RS. In an overcurrent condition, the current is limited to 50mV/RS by regulating GATE. If the overcurrent condition remains for more than 530μs, GATE is turned off. The DRAIN and GATE voltages are monitored to determine if the FET is fully enhanced. Upon successful turn on of the FET, two power good signals are presented on the PG and PGIO pins. They allow enabling and sequencing of loads. The PGIO pin can also be configured for a general purpose input or output. APPLICATIONS INFORMATION The isolated side logic circuits are powered by an inter- nally generated 5 V supply (VCC2). Prior to turning on the FET, both the internal gate drive supply voltage V S and VCC2 voltages must exceed their undervoltage lockout thresholds. In addition, the control inputs UVH, UVL, OV and EN are monitored. The FET is held off until all start-up conditions are met. A 10-bit analog-to-digital converter (ADC) is included in the LTM9100. The ADC measures the SENSE voltage as well as voltages at the ADIN2 and ADIN pins, for auxiliary functions such as sensing bus voltage or temperature, etc. An I2C interface is provided to read the ADC data registers. It also allows the host to poll the device and determine if a fault has occurred. If the ALERT line is used as an interrupt, the host can respond to a fault in real time. Tw o three-state pins, ADR0 and ADR1, are used to program eight possible device addresses. The interface can also be pin configured for a single-wire broadcast mode, sending ADC data and fault status through the SDA pin to the host without clocking the SCL line. This single-wire, one-way communication can simplify system design. The LTM9100 is ideally suited for distributed DC power systems and off-line power converter systems requiring an isolated communication and control interface. A basic 200W –48V distributed power application circuit using the LTM9100 is shown in Figure 4.

translate signals and power across an isolation barrier. powerful isolated DC/DC converter in one small package. transformer saturation caused by secondary imbalances. is decoupled internally by a 1µF capacitor. Figure 4. –48V/200W Low Side Hot Swap Controller Using LTM9100 with Current and Input Voltage

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Figure 6. NPN Buffer Relieves RLIM of Excessive Dissipation

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voltage to the step up converter, as shown in Figure 8. the bus voltage and power dissipation. Figure 8. Preregulator for VBUS > 100V

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Figure 5. Isolated Side Power Derived From External Bus

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Figure 7. VS Supply for VBUS ≤ 100V

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Overvoltage T ransients for a detailed discussion. ary by encoding and decoding of the inputs and outputs. high priority serial packet. ply VCC2 must cross its 4.25V undervoltage lockout level. in Figure 10. Simply connect the desired logic supply to VL. specified operating ranges and sequence in any order. VCC and VL are decoupled internally by 1µF capacitors. Figure 10. VCC and VL Are Independent

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Figure 9. External-to-Internal PowerPath Switch-Over

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Rev. AFor more information www.analog.com APPLICATIONS INFORMATION the voltage at TMR reaches 2.56V. C TMR is then quickly discharged with a 12mA current. The initial delay expires when TMR is brought below 75mV. The duration of the start-up delay is given by: tD ≅12ms + 256ms •CTMR 1µF If any of the above conditions is violated before the start- up delay expires, C TMR is quickly discharged and the turn-on sequence is restarted. After all the conditions are validated throughout the start-up delay, the EN pin is then checked. If it is high, the FET will be turned on. Otherwise, the FET will be turned on when the EN pin is raised or bit 3 (GATE_CTRL) in the CONTROL (D) register is set to 1 through the I2C interface, when configured for I2C only control. The FET turn-on sequence follows by charging an internal and external (C SS) capacitor at the SS pin with a 10µA pull-up current and the voltage at SS (V SS) is converted to a current (I GATE(UP)) of 11.5μA • V SS/2.56V for GATE pull-up. When the GATE reaches the FET threshold volt- age, current starts to flow through the FET and a current (IRAMP) of 20μA • V SS/2.56V flows out of the RAMP pin and through an external capacitor (CR) connected between RAMP and the drain voltage. The SS voltage is clamped to 2.56V, which corresponds to I GATE(UP) = 11.5µA and IRAMP = 20μA. The RAMP pin voltage is regulated at 1.1V and the ramp rate of VDRAIN determines the inrush current for capacitive load: IINRUSH = 20µA • CL CR The ramp rate of V SS determines the di/dt of the inrush current: dIINRUSH dt = 20µA • CL CR

• 1µF 256ms •(C SS + 220nF) If CSS is absent externally, the SS ramps from 0V to 2.56V in approximately 56ms. When V DRAIN is ramped down to V EE, IGATE returns to the GATE pin and pulls the GATE up to V GATEH. Figure 11 illustrates the start -up sequence of the LTM9100. During live board insertion or input power step, an internal clamp turns on to hold the RAMP pin low. Resistor R R and an internal 10nF capacitor to V EE suppress noise at the RAMP pin. For proper operation, RR • CR should not exceed 50µs. Additional capacitance may be added from RAMP to VEE for additional noise filtering. Power Good Monitors When the voltage across the FET falls below 1.77V and GATE pulls above approximately 9V, an internal power good signal is latched and a series of two delay cycles are started as shown in Figure 11. When the first delay cycle with a duration of 2tD expires, the PG2 and PG pins pull low as power good signals. When the second delay cycle (2t D) expires, the PGIO pin pulls low as another power good signal. The 2t D timer delay is obtained by charging the capacitance on TMR with a 5µA current and discharging with 12mA when TMR reaches 2.56V. The power good signals at PG and PGIO are reset in all FET turn-off conditions except the overvoltage fault. Turn-Off Sequence and Auto-Retry In any of the following conditions, the FET is turned off by pulling down GATE with a 110mA current, and the capaci- tances at SS and TMR are discharged with 12mA currents. 1. The EN (or EN2) pin is low or register bit D3 is set to 0. 2. The voltage at UVL is lower than 2.291V and the voltage at UVH is lower than 2.56V (undervoltage fault). 3. The voltage at OV is higher than 1.77V (overvoltage fault). 4. The voltage at VS is lower than 8.5V (VS undervoltage lockout). 5. The voltage at VCC2 is lower than 4.25V (VCC2 undervolt- age lockout). 6. VSENSE > 50mV and the condition lasts longer than 530μs (overcurrent fault). For conditions 1, 4, 5, after the condition is cleared, the LTM9100 will automatically enter the FET turn-on sequence as previously described.

following the overvoltage fault does not have a delay. latch-off following the overcurrent fault. Figure 11. LTM9100 Turn-On Sequence

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Rev. AFor more information www.analog.com APPLICATIONS INFORMATION Turning the GATE Pin (External FET) On Many methods of on/off control are possible using the ON, EN, EN2, UV/OV or PGIO pins along with the I2C port. The EN pin works well with logic inputs or floating switch contacts; I2C control is intended for systems where the board operates only under command of a central control processor and the ON pin is useful with systems with low standby current requirements. The UV (UVH, UVL) and OV pins are useful with signals referenced to V EE. PGIO controls nothing directly, but is useful for I2C monitoring of connection sense or other important signals. On/off control is possible with or without I2C intervention. Even when operating autonomously, the I2C port can still exercise control over the GATE output, although depend- ing on how they are connected, EN, EN2, and ON could subsequently override conditions set by I2C. UV, OV and other fault conditions seize control as needed to turn off the GATE output, regardless of the state of EN, EN2, ON or the I2C port. Figure 12 shows five configurations of on/ off control of the LTM9100. Logic Control with Isolation: Figure 12 a shows an application using logic signal control. Rising and falling edges of either the ON pin or EN pin, with alternate pin tied high, turn the GATE output on and off. Rising edge control of ON results in a delay of the GATE signal by the power converter turn-on time and one tD period, the falling edge will also be delayed by the converter discharge time (stored energy) and supply loading on VS and VCC2. The GATE will respond immediately to changes on the EN pin. The status of EN can be examined or overridden through the I 2C port at register bit D3. Register bit D3 is set low whenever VCC2 drops below its UVLO threshold. The status of the GATE pin output is indicated by register bit A7 (GATE_STAT), which is equal to register bit D3 and the absence of UV, OV, and other faults. Bootstrapped Power Connection: Figure 12b shows a low side application with control power derived on the isolated side. With EN2 tied high on the isolated side, GATE rises one t D period after power is applied. The logic supply (VL) or ON pin may be toggled either before or after the bus voltage is applied provided the EN pin is tied high, without interfering with the GATE signal. Ejector Switch or Loop-Through Connection Sense: Floating switch contacts, or a connection sense loop work well with the EN or EN2 pins. Figure 12c illustrates this configuration using the EN2 pin and includes a debounce delay. Short Pin to RTN: Figure 12d uses the UV divider string to detect board insertion. The short pin connection could also be wired to work in conjunction with either the ON or EN pins. I 2C Only Control: To lock out EN and ON, use the configu- ration shown in Figure 12e and control the GATE pin with register bit D3. The circuit defaults off at power up with EN2 tied to VEE. To default on, do not connect EN2. The PGIO pin can be used as an input to monitor a connec- tion sense or other control signal. PGIO is configured as an input by setting register bits D6 and D7 high; its input state is stored at register bit A6. Overcurrent Protection and Overcurrent Fault The LTM9100 features two levels of protection from short-circuit and overcurrent conditions. Load current is monitored by the SENSE pins and resistor RS. There are two distinct thresholds for the voltage at SENSE: 50mV for engaging the active current limit loop and starting a 530μs circuit breaker timer and 250mV for a fast GATE pull-down to limit peak current in the event of a catastrophic short-circuit or an input step. In an overcurrent condition, when the voltage drop across R S exceeds 50mV, the current limit loop is engaged and an internal 530μs circuit breaker timer is started. The current limit loop servos the GATE to maintain a constant output current of 50mV/R S. When the circuit breaker timer expires, the FET is turned off by pulling GATE down with a 110mA current, the capacitors at SS and TMR are discharged and the power good signals are reset. At this time, the overcurrent present bit A2 and the overcurrent fault bit B2 are set, and the circuit breaker timer is reset.

Figure 12. On/Off Control of the LTM9100

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Rev. AFor more information www.analog.com APPLICATIONS INFORMATION After the FET is turned off, the overcurrent condition register bit A2 is cleared. If the overcurrent auto-retry register bit D2 has been set, the switch will turn on again automatically after a cooling time of 4t D. Otherwise, the FET will remain off until the overcurrent fault register bit B2 is reset. When the overcurrent fault bit is reset (see Resetting Faults), the FET is allowed to turn on again after a delay of 4t D. The 4tD cooling time associated with the overcurrent fault will not be interrupted by any other fault condition. See Figure 13 for operation of LTM9100 under overcurrent condition followed by auto-retry. In the case of a low impedance short-circuit on the load side or an input step during battery replacement, current overshoot is inevitable. A fast SENSE comparator with a threshold of 250mV detects the overshoot and immediately pulls GATE low. Once the SENSE voltage drops to 50mV, the current limit loop takes over and servos the current as previously described. If the short-circuit condition lasts longer than 530μs, the FET is shut down and the overcur- rent fault is registered. In the case of an input step, after an internal clamp pulls the RAMP pin down to 1.1V, the inrush control circuit takes over and the current limit loop is disengaged before the circuit breaker timer expires. From this point on, the device works as in the initial start-up: V DRAIN is ramped down at the rate set by I RAMP and CR followed by GATE pull-up. The power good signals on the PG and PGIO pins, the TMR pin, and the SS pin are not interrupted through the input step sequence. The waveform in Figure 14 shows how the LTM9100 responds to an input step. Note that the current limit threshold should be set suf - ficiently high to accommodate the sum of the load current and the inrush current to avoid engagement of the current limit loop in the event of an input step. The maximum value of the inrush current is given by: IINRUSH ≤ 0.8 • 45mV RS –I LOAD where the 0.8 factor is used as a worst-case margin combined with the minimum SENSE threshold (45mV). The active current limit circuit is compensated using the capacitor C G with a series resistor R G (10Ω) connected between GATE and VEE, as shown in Figure 4. The sug- gested value for CG is 47nF. This value should work for most FETs (Q1). Overvoltage Fault An overvoltage fault occurs when the OV pin rises above its 1.77V threshold. This shuts off the FET immediately, sets the overvoltage present register bit A0 and the over- voltage fault register bit B0, and pulls the SS pin down. Note that the power good signals are not affected by the overvoltage fault. If the OV pin subsequently falls back below the threshold, the FET will be allowed to turn on again immediately (without delay) unless the overvoltage auto-retry has been disabled by clearing register bit D0. Undervoltage Comparator and Undervoltage Fault The LTM9100 provides two undervoltage pins, UVH and UVL, for adjustable UV threshold and hysteresis. The UVH and UVL pin have the following accurate thresholds: for UVH rising, VUVH(TH) = 2.56V, turn-on for UVL falling, VUVL(TH) = 2.291V, turn-off The UVH and UVL pins have a hysteresis of δVUV (15mV typical). In either a rising or a falling input supply, the undervoltage comparator works in such a way that both the UVH and the UVL pins have to cross their thresholds for the comparator output to change state. The UVH, UVL, and OV threshold ratio is designed to match the standard telecom operating range of 43V to 71V and UV hysteresis of 4.5V when UVH and UVL are tied together as in Figure 4, where the built-in UV hysteresis referred to the UVL pin is: VUV(HYST) = VUVH(TH) – VUVL(TH) = 0.269V Using R1 = 11.8k, R2 = 16.9k and R3 = 453k as in Figure 4 gives a typical operating range of 43.0V to 70.7V, with an undervoltage shutdown threshold of 38.5V and an overvoltage shutdown threshold of 72.3V. The UV hysteresis can be adjusted by separating the UVH and UVL pins with a resistor R H (Figure 15). To increase the UV hysteresis, the UVL tap should be placed above the UVH tap as in Figure 15a. To reduce the UV hysteresis,

Figure 13. Overcurrent Fault and Auto-Retry Figure 14. 36V to 72V Step Response

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an undervoltage fault will be logged in the fault register. FET_STAT register bit A5 and the FET_FAUL T register bit B5. Figure 30. If there is a collision between two LTM9100’s from chattering even when RH is larger than RH(MAX). register bit A1 and the undervoltage fault register bit B1. The power good signals at PG and PGIO are also reset. by clearing register bit D1. Figure 15. Adjustment of Undervoltage Thresholds for Larger

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Rev. A For more information www.analog.com the device with the lower address wins arbitration and responds first. The ALERT line will also be released if the device is addressed by the bus master. Once the ALERT signal has been released for one fault, it will not be pulled low again until the FAUL T register indicates a different fault has occurred, or the original fault is cleared and it occurs again. Note that this means repeated or continuing faults will not generate alerts until the associated FAUL T register bit has been cleared. Resetting Faults Faults are reset with any of the following conditions. First, writing zeros to the FAUL T register will clear the associated fault bits. Second, the entire FAUL T register is cleared when either the EN2 pin or register bit D3 goes from high to low, or if VCC2 falls below its 4.25V undervoltage lockout. Pull- ing the UVL pin below its 1.21V reset threshold also clears the entire FAUL T register. When the UVL pin is brought back above 1.21V but below 2.291V, the undervoltage fault register bit B1 is set if the UVH pin is below 2.56V. This can be avoided by holding the UVH pin above 2.56V while toggling the UVL pin to reset faults. Fault bits with associated conditions that are still present (as indicated in the STATUS (A) Register) cannot be cleared. The FAUL T register will not be cleared when auto-retrying. When auto-retry is disabled, the existence of register bits B0 (overvoltage), B1 (undervoltage) or B2 (overcurrent) keeps the FET off. After the fault bit is cleared and a delay of t D expires, the FET will turn on again. Note that if the overvoltage fault register bit B0 is cleared by writing a zero through I2C, the FET is allowed to turn on without a delay. If auto-retry is enabled, then a high value in register bits A0, A1 or A2 will hold the FET off and the FAUL T register is ignored. Subsequently, when register bits A0, A1 and A2 are cleared, the FET is allowed to turn on again. Data Converter The LTM9100 incorporates a 10-bit ∆∑ analog-to-digital converter (ADC) that continuously monitors three different voltages at (in the sequence of) SENSE, ADIN2 and ADIN. The ∆∑ architecture inherently averages signal noise during the measurement period. The voltage between the SENSE+ and SENSE– pins is monitored with a 64mV full-scale and 62.5μV resolution, and the data is stored in registers E and F. The ADIN and ADIN2 pins are monitored with a 2.56V full-scale and 2.5mV resolution. The data for the ADIN2 pin is stored in registers G and H. The data for the ADIN pin is stored in registers I and J. The results in registers E, F, G, H, I and J are updated at a frequency of 7.3Hz. Setting register bit D5 invokes a test mode that halts updating these registers so that they can be written to and read from for software testing. By invoking the test mode right before reading the ADC data registers, the 10-bit data separated in two registers are synchronized. The ADIN and ADIN2 pins can be used to monitor input and output voltages or temperature of the controller as shown in Figures 33 to 35, 39, 40, 43, and 45. Configuring the PGIO Pin Table 4 describes the possible states of the PGIO pin us- ing register bits D6 and D7. At power-up the default state is for the PGIO pin to pull low when the second power good signal is ready. Other uses for the PGIO pin are to go high impedance when the second power good is ready, a g eneral purpose output and a general purpose input. When the PGIO pin is configured as a general purpose output, the status of register bit C6 is sent out to the pin. When it is configured as a general purpose input, if the input voltage at PGIO is higher than 1.25V, both register bits A6 and B6 are set. If the input voltage at PGIO subsequently drops below 1.25V, register bit A6 is cleared. Register bit B6 can be cleared by resetting the FAUL T register as described previously. Design Procedure 1. Using the load current (I LOAD) requirement of the ap- plication, calculate the sense resistor (RS) value using the minimum SENSE threshold voltage of 45mV. RS = 45mV ILOAD IMAX = 55mV R S APPLICATIONS INFORMATION

Rev. AFor more information www.analog.com APPLICATIONS INFORMATION 2. For a capacitive load (CL) set the inrush (IINRUSH) cur- rent by calculating the ramp capacitor (CR) value. CR =CL • IRAMP IINRUSH =CL • 20µA IINRUSH The inrush current and ramp capacitor may need to be iterated based upon the selected switch safe operating area (SOA). For resistive or inductive loads the turn-on voltage rate of change is calculated by: dV dt = IRAMP CR = 20µA CR 3. Select an N-channel switch (Q1); MOSFET, SiC MOSFET, IGBT, etc. Switch selection is based upon maximum operating voltage (with margin), ON state power dis - sipation (IMAX2 • RDSON or IMAX • VCESAT), and SOA. The maximum ON state power dissipation (PON) is calculated using the maximum load current and maximum expected switch RDSON. The maximum switch resistance at 125°C is generally 2× the data sheet electrical table maximum ON resistance at 25°C junction temperature. PON = IMAX2 • RDSON(125°C) Multiple cases must be considered for the switch SOA including; normal inrush turn-on, turn-on into a short circuit, input voltage steps, and short-circuit while con- ducting. To evaluate the switch SOA between multiple manufacturers and operating cases the calculated data, and constant power (diagonally decreasing) portion of the data sheet SOA curves, can be normalized by cal - culating P2t or P√t and comparing. Switches designed and characterized for linear or DC operation are most suitable. These are generally switches fabricated using a planar process, as opposed to a high density vertical process (e.g. trench). a. Normal switch turn-on power dissipation (P TON) consists of a voltage ramp from VBUS to ≈ 0V with constant charging current of IINRUSH. Assuming no load current and ignoring slow start: PTON = VBUS •I INRUSH tINRUSH = CR • VBUS IRAMP(min) = CL • VBUS IINRUSH P t =PTON tINRUSH b. Load short-circuit turn-on power dissipation (PSCTON) consists of a current ramp to IMAX, this is the MOSFET transconductance period (tfs), followed by the circuit breaker period (t CB) at I MAX, each at constant bus voltage. Ignoring slow start: Pfs = VBUS •I MAX PCB = VBUS • IMAX tfs = CG +C iss(max)( )• 2 •IMAX IGATE(min) • gfs(min) where IGATE(min) = 7.5µA, C iss is the MOSFET gate input capacitance, and g fs is the MOSFET forward transconductance. tCB = 620µs (Maximum) Calculate the total power dissipation over the event: PSCTON = P fs• tfs+P CB • tCB tfs + tCB P t =PSCTON tfs+ tCB c. Power dissipation for an input voltage step (PSTEP) consists of a voltage ramp from VSTEP to ≈ 0V with constant current of IMAX = IINRUSH + ILOAD. Assum- ing load current is constant with operating voltage: PSTEP = VSTEP •IMAX tSTEP = CR • VSTEP IRAMP(min) = CL • VSTEP IINRUSH P t =PSTEP tSTEP

Rev. A For more information www.analog.com APPLICATIONS INFORMATION d. Load short-circuit while conducting power dissipa- tion (PSCON) consists of a constant bus voltage at maximum current for the circuit breaker period. PSCON = VBUS • IMAX tCB = 620µs P t = PSCON tCB On inspection case d will always result in a lower value than case b and will not need to be calculated. 4. Select the GATE compensation capacitance (C G). The total capacitance on the GATE pin should be ≈ 47nF to compensate the active current limit circuit. The total capacitance is equal to: CG(TOTAL) = CG + Ciss ≈ 47nF 5. Size divider resistors for undervoltage and overvoltage trip points, assuming UVL and UVH pins tied together, and one divider for both functions (Figure 4). These functions may be disabled by tying UVL and UVH to VCC2, and OV to VEE. a. Choose a nominal current to run in the divider (IDIV(NOM)). Typically this is 100μA. b. The current in the divider during an overvoltage condition is: IDIV(OV) =IDIV(NOM) • VBUS OV VBUS NOM where VBUS NOM is the nominal bus voltage and VBUSOV is the bus voltage in the overvoltage condi- tion. c. Calculate R1: R1= VOV(TH) IDIV(OV) = 1.77V IDIV(OV) d. Choose the undervoltage bus voltage (VBUS UV). Undervoltage may be set using the rising threshold (UVH) of 2.56V, the bus voltage where the system starts to operate, or falling threshold (UVL) of 2.291V, the bus voltage where the system ceases to operate, depending on the system requirements. e. The current in the divider at threshold of undervoltage event is: IDIV(UV) =IDIV(NOM) • VBUS UV VBUS NOM f. Calculate R2: R2 = VUV(TH) IDIV(UV) – R1 g. Calculate R3: R3 = VBUS NOM IDIV(NOM) – R1– R2 6. Size resistor to the DRAIN pin, the suggested bias cur- rent is 50μA, limit the value to < 2mA. RD = VBUS NOM 50µA Design Example #1 For this design example, consider the 200W application with CL = 330μF as shown in Figure 4. The operating volt- age range is from 43V to 71V with a UV turn-off threshold of 38.5V. For the purposes of calculation the minimum operating voltage is 36V and maximum is 72V. The design must tolerate short circuits and an input voltage step of 36V. 1. The sense resistor is calculated using the minimum sense threshold, minimum operating voltage, and ap- plication power: RS = 45mV • 36V 200W =0.008Ω IMAX = 55mV 0.008 = 6.875A 2. Set the inrush current to 0.66A. CR =CL • 20µA 0.66A =10nF RR is chosen to be 1k as discussed previously.

Rev. AFor more information www.analog.com 3. Select a MOSFET and compare the calculated power dissipation under all conditions. The IRF1310 is selected, worst case conduction loss is: PON = IMAX2 • RDSON(125°C) = 6.8752 • 72mΩ = 3.4W From the data sheet SOA curve the P√t for 10ms opera- tion is ≈ 25W√s (VDS = 50V, ID = 5A). Case 3a: P t = 72 • 0.66 330µ • 72 0.66 = 4.5W s Case 3b: Pfs = 72 • 6.875 = 248W, PCB = 72 • 6.875 = 495W 7.5µA • 14 = 6.4ms PSCTON = 248 • 6.4m + 495 • 620µ 6.4m + 620µ = 270W P t = 270 6.4m + 620µ = 22.6W s Case 3c: P t = 36 • 6.875 330µ • 36 0.66 = 16.6W s All cases are satisfied with P√t values < 25W√s. 4. The FET selected in step 3 has an input capacitance of 1.9nF, so the CG value of 47nF is appropriate. 5. Set the nominal UV/OV divider string to 100µA, resistors are rounded to the nearest 1% value. IDIV(OV) = 100µA • 72 = 150µA IDIV(UV) = 100µA • 43 = 89.6µA R1= 1.77 150µA = 11.8kΩ R2 = 2.56 89.6µA – 11.8kΩ = 16.9kΩ R3 = 48 100µA – 11.8kΩ – 16.9kΩ = 453kΩ 6. The DRAIN pin resistor is set to 1MΩ. Design Example #2 For this design example, consider the 380V application with CL = 330μF as shown on the back page. The operat- ing voltage range is from 260V to 420V with a UV turn-off threshold of 235V, and OV threshold of 435V. The design must tolerate short circuits, and be designed to maximize the available load current with an off-the-shelf MOSFET. With a 435V maximum operating voltage a MOSFET with 600V drain to source voltage is desired. In order to maximize load current, minimum R DSON and excellent SOA are needed. A device survey shows than an IXYS, IXTH30N60L2, is a good candidate. A reasonable, heat- sinkable, board level conduction loss (P ON) is 5W. The maximum operating current can now be calculated: IMAX = PON RDSON(125°C) = 5 0.48 = 3.25A APPLICATIONS INFORMATION

Rev. A For more information www.analog.com the input resistors to minimize current and power dis- sipation; 3.3MΩ is chosen, the divider resistors are then 3.3MΩ/102.3 = 32.4kΩ. As noted on the schematic the ADIN voltage should be 2.56V at 435V, and the OV voltage should be 1.77V at 435V. Set the maximum divider string current to 200µA. R1= 1.77 200µA = 8.87kΩ R2 = 2.56 200µA – 8.87kΩ = 3.92kΩ R3 = VBUS OV 102.3 200µA – 8.87kΩ – 3.92kΩ = 8.45kΩ 6. The DRAIN pin resistor is set to 3.3MΩ. External Switch While the primary application of the LTM9100 is the con- trol of an external N-Channel MOSFET switch, insulated gate bipolar transistors (IGBTs) may be used. This is of particular interest in voltage applications greater than 250V where traditional FETs with sufficient SOA and low RDSON are not available. IGBTs are readily available with voltage ratings of 600V, 1200V, and higher. Not all IGBTs are suitable, only those specified for DC or near DC operation as indicated in the data sheet SOA operating curves. Tw o additional areas of concern are the collector to emitter saturation voltage and gate to emitter threshold voltage. The LTM9100 monitors the collector voltage of the IGBT, via the DRAIN pin and series resistor, to insure the IGBT is turned on before the power good signals are transitioned. The DRAIN pin threshold is 1.77V. The saturation voltage, V CE(SAT), of the IGBT may be higher than this necessitat- ing a voltage divider on the DRAIN monitor input pin as shown in Figure 16. Resistor R1 is sized based on the bus voltage and maxi- mum DRAIN current of 2mA. Resistor R2 is then chosen to provide a voltage less than 1.77V on the DRAIN pin with APPLICATIONS INFORMATION 1. Calculate the sense resistor: RS = 55mV 3.25A = 0.017Ω 2. Set th e inrush current, by choosing an operating current below the DC SOA operating curve at 400V. IINRUSH = 0.3A, CR = 330µ • 20µA 0.3A = 22nF 3. The P√t of the device is ≈ 80W√s at a case temperature of 75°C. Case 3a: P t = 430 • 0.3 330µ • 430 0.3 = 44W s Case 3b: Pfs = 430 • 3.25 = 700W, PCB = 430 • 3.25 = 1.4kW 7.5µA • 10 = 4.3ms PSCTON = 700 • 4.3m +1400 • 620µ 4.3m + 620µ = 788W P t = 788 4.3m + 620µ = 55W s Case 3 c is not calculated since an input step was not specified. 4. The FET selected has an input capacitance of 10.7nF, so the CG value of 39nF is appropriate. 5. In this example the bus voltage must be level shifted and referenced to VEE to utilize the UV, OV, and analog inputs. This is accomplished by the differential ampli- fier stage using the LT C®2054. Since the output of the amplifier connects to the UV pins, the amplifier divide ratio is set for an output voltage of 2.291V at the UV turn-off threshold of 235V; 235/2.291=102.3. Choose

Figure 16. LTM9100 DRAIN Monitor Resistive Divider for Figure 17. Simple Gate Voltage Booster

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the IGBT at the minimum GATE voltage. the RDSON or VCE which in turn reduces power dissipation. calculation and sizing of CR. negative voltage (–VBIAS) to the switch. Figure 18. Negative Gate Bias Controlled by EN

9100 F18

of the turn-on current until fully enhanced. do not employ any dynamic current sharing methods. external FET which produces a constant charging current. beyond the scope of this discussion. Figure 19. The RAMP pin is not used due to coupling of GATE modulation during normal operation. Figure 19. Rectified AC High Side Charging Circuit

9100 F19

required, LTC4213 of Figure 19. Table 1. Component Values for 13.4% Ripple Single Phase and 3.4% Ripple Three Phase for the 120VAC case of Table 1. Figure 20. Load Capacitor Charging Voltage, Current, and Junction Temperature

9100 F20a

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allowing additional serial device expansion. guaranteeing sufficient data setup time (tSU(DAT)). greater than 400pF in STANDARD mode. be greater than 1V/µs for proper operation. Figure 23. Maximum Standard Speed Pull-Up Resistance on SDA Figure 22. Isolated SDA2 Pin Schematic Figure 24. Maximum Fast Speed Pull-Up Resistance on SDA Figure 21. I2C Timing Diagram

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Figure 28. LTM9100 Serial Bus SDA Read Word Protocol Figure 27. LTM9100 Serial Bus SDA Read Byte Protocol Figure 26. LTM9100 Serial Bus SDA Write Word Protocol Figure 25. LTM9100 Serial Bus SDA Write Byte Protocol to the left of the appropriate curve. and fall times and minimize noise. these commands are shown in Figures 25 to 28. free for another transmission. The LTM9100 I2C interface features a stuck-bus reset timer.

9100 F25

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9100 F27

9100 F28

and the I2C state machine is reset. Table 2. Note that the configuration of ADR0 = L and a STOP condition to terminate the transmission. Figure 29. Open Drain Buffer for Shared ALERT Bus

9100 F29

sion is ended when the master sends a STOP condition. to repeatedly read a specific register. until the associated FAUL T register bit has been cleared. enters the idle mode with SDA pulled high. tions to measure 1/2 of the internal clock cycle. Figure 30. LTM9100 Serial Bus SDA Alert Response Protocol individually addressed during a read or write transaction.

9100 F30

1. Wait 3/4 of a clock cycle.
2. Sample bit CH1, wait for transition.
3. Wait 3/4 of a clock cycle.
4. Sample bit CH0, wait for transition.
5. Wait 3/4 of a clock cycle.
6. Sample ADC9, wait for transition.
7. Continue until all bits are read.

all 18 bits to be clocked out. voltage, VDS of the FET and VSENSE are monitored. Figure 31. Single-Wire Broadcast Mode Figure 32. Single-Wire Broadcast Data Format

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Rev. AFor more information www.analog.com APPLICATIONS INFORMATION Table 2. LTM9100 Device Addressing ADDRESS BINARY DEVICE ADDRESS LTM9100 ADDRESS PINS h b6 b5 b4 b3 b2 b1 b0 (R/W) ADR1 ADR0 Mass Write 3E 0 0 1 1 1 1 1 0 X X Alert Response 19 0 0 0 1 1 0 0 1 X X 0 20 0 0 1 0 0 0 0 X L L 1 22 0 0 1 0 0 0 1 X L NC 2 24 0 0 1 0 0 1 0 X H NC 3 26 0 0 1 0 0 1 1 X L H 4 28 0 0 1 0 1 0 0 X NC L 5 2A 0 0 1 0 1 0 1 X NC NC 6 2C 0 0 1 0 1 1 0 X H H 7 2E 0 0 1 0 1 1 1 X NC H

8 Single-Wire Broadcast Mode X H L

H = Tie to VCC2; L = Tie to VEE; NC = No connect, open; X = Don’t care Table 3. ADC Channel Labeling for Single-Wire Broadcast Mode

Table 4. Register Map NOTE: Underlined text denotes the default condition.

signed per the data sheet PCB layout recommendations. Table 5. Test Frequency Field Strength some layout considerations are necessary.

• To achieve accurate current sensing, a Kelvin connec- tion is recommended. The minimum trace width for 1oz copper foil is 0.02" per amp to minimize temperature rise. Using 0.03" per amp or wider is recommended. Note that 1oz copper exhibits a sheet resistance of about 530µV/square. Small resistances add up quickly in high current applications. To improve noise immunity, put the resistive divider to the UV and OV pins close to the module and keep traces to VEE short. Internal 10nF capacitors from the UVH pin and OV pin to VEE help reject supply noise.
• Under heavily loaded conditions, VCC and GND current can exceed 300mA. Use sufficient copper on the PCB to insure resistive losses do not cause the supply voltage to drop below the minimum allowed level.
• Input supply decoupling is not required, since these components are integrated within the package. An ad- ditional bulk capacitor with a value of 6.8µF to 22µF and ESR of 1Ω to 3Ω is recommended. The high ESR of this capacitor reduces board resonances and minimizes voltage spikes caused by hot plugging of the supply voltage. For EMI sensitive applications, an additional low ESL ceramic capacitor of 1µF to 4.7µF, placed as close to the power and ground terminals as possible, is recommended. Alternatively, a number of smaller value parallel capacitors may be used to reduce ESL and achieve the same net capacitance.
• Do not place copper on the PCB between the inner col- umns of pads. This area must remain open to withstand the rated isolation voltage.
• The use of solid ground planes for GND and V EE is recommended for non-EMI critical applications to optimize signal fidelity, thermal performance, and to minimize RF emissions due to uncoupled PCB trace conduction. The drawback of using ground planes, where EMI is of concern, is the creation of a dipole antenna structure, which can radiate differential volt - ages formed between GND and VEE. If ground planes are used it is recommended to minimize their area, and use contiguous planes as any openings or splits can increase RF emissions. APPLICATIONS INFORMATION

• For large ground planes a small capacitance (≤ 330pF) from GND to VEE, either discrete or embedded within the substrate, provides a low impedance current return path for common mode current conducted through the module parasitic capacitance, minimizing any high frequency differential voltages and substantially reduc- ing radiated emissions. Discrete capacitance will not be as effective due to parasitic ESL. In addition, voltage rating, leakage, and clearance must be considered for component selection. Embedding the capacitance within the PCB substrate provides a near ideal capacitor and eliminates the other component selection issues; however, the PCB must be four or more layers. Care must be exercised in applying either technique to ensure the voltage rating of the barrier is not compromised.
• In applications without an embedded PCB substrate capacitance, a slot may be added between the logic side and isolated side device pins. The slot extends the creepage path between terminals on the PCB side, and may reduce leakage caused by PCB contamination. The slot should be placed in the middle of the device terminals and extend beyond the package perimeter. APPLICATIONS INFORMATION TYPICAL APPLICATIONS

Figure 33. High Side Inrush Current Control with Switch Voltage Sense (R3, R4 to ADIN)

9100 F33

Figure 34. High Side Inrush Current Control with Line/Load Voltage Sense Figure 35. Low Side Inrush Current Control with Line/Load Voltage Sense (R1, R2, R3 to ADIN2)

9100 F34

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Figure 36. Boosted Gate Drive with Negative Off Bias

9100 F36

Figure 37. Switch Control with Reverse Conduction Blocking Figure 38. Bi-Directional Battery — Inverter Inrush Current Limiter

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Figure 39. Linear 10-Bit Remote (or Local) Thermistor Temperature Sense Figure 40. Precision 10-Bit Remote Temperature Sense

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Figure 42. Transformer Inrush Current Limiter, n Line Cycle Ramp Figure 41. I2C Precision 14-Bit Remote (or Local) Dual Temperature Sense

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Figure 43. Inductive Load Current Limiter – Controlled Turn-On Figure 44. AC Circuit Breaker

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Figure 45. Low Side Switch Controller with Rectified AC-DC Link (DC Bus with Ripple) Figure 46. Inrush Current Limiting for AC Voltage Doubler

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Rev. A For more information www.analog.com PACKAGE TOP VIEW PIN “A1” CORNER Y X aaa Z aaa Z 42-Lead (22mm × 9mm × 5.16mm) (Reference LTC DWG# 05-08-1973 Rev A) NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE DETAIL A Øb (42 PLACES) A DETAIL B PACKAGE SIDE VIEW M X Y Z ddd M Z eee D E SUGGESTED PCB LAYOUT TOP VIEW 0.00 8.89 10.16 2.54 1.27 2.54 3.81 3.81 1.27 0.00 10.16 8.89 7.62 6.35 9.84 10.48 0.635 ±0.025 Ø 42x 4.13 3.49 BGA 42 0517 REV A TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” L TMXXXXXX µModule PACKAGE BOTTOM VIEW T S R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 DETAIL A SEE NOTES PIN 1 e e F G b SEE NOTES b SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 4.91 0.50 4.41 0.60 0.60 0.46 3.95 NOM 5.16 0.60 4.56 0.75 0.63 22.0 9.0 1.27 20.32 7.62 0.56 4.00 MAX 5.41 0.70 4.71 0.90 0.66 0.66 4.05 0.15 0.10 0.15 0.15 0.08 TOTAL NUMBER OF BALLS: 42 DIMENSIONS NOTES BALL HT BALL DIMENSION PAD DIMENSION SUBSTRATE THK MOLD CAP HT DETAIL B SUBSTRATE ccc Z Z // bbb Z MOLD CAP 5. PRIMARY DATUM -Z- IS SEATING PLANE

6 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y Z PACKAGE DESCRIPTION

Rev. AFor more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 04/21 Added CSA (UL/IEC) Certifications. 1, 8

Rev. A For more information www.analog.com  ANALOG DEVICES, INC. 2017-2021 www.analog.com RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LTM2881 Isolated RS485/RS422 µModule T ransceiver with Integrated DC/DC Converter 20Mbps 2500VRMS Isolation with Power in LGA/BGA Package LTM2882 Dual Isolated RS232 µModule T ransceiver with Integrated DC/DC Converter 2500VRMS Isolation with Power in LGA/BGA Package LTM2883 SPI/Digital or I2C Isolated µModule with Adjustable 5V, and ±12.5V Nominal Voltage Rails 2500VRMS Isolation with Power in BGA Package LTM2884 Isolated High Speed USB µModule with Integrated DC/DC Converter 2500V RMS Isolation with Power in BGA Package LTM2885 Isolated RS485/RS422 µModule T ransceiver with integrated DC/DC converter 20Mbps 6500V RMS Isolation with Power in BGA Package LTM2886 SPI/Digital or I2C Isolated µModule with Adjustable 5V, and Fixed ±5V Power Rails 2500VRMS Isolation with Power in BGA Package LTM2887 SPI/Digital or I2C Isolated µModule with Tw o Adjustable 5V Rails 2500V RMS Isolation with Power in BGA Package LTM2889 Isolated CAN µModule T ransceiver with Integrated DC/DC Converter 4Mbps 2500V RMS Isolation with Power in BGA Package LTM2892 SPI/Digital or I2C Isolated µModule 3500VRMS Isolation in BGA Package LTM2893 Complete 100MHz SPI ADC µModule Isolator 6000VRMS Isolation in Surface Mount BGA LTM2894 Complete Isolated USB µModule T ransceiver 7500VRMS Isolation in Surface Mount Package LTC1535 Isolated RS485 T ransceiver 2500VRMS Isolation with External T ransformer Drive LTC4260 Positive High Voltage Hot Swap Controller With I2C and ADC, Supplies from 8.5V to 80V LTC4261 Negative High Voltage Hot Swap Controller With I2C and ADC, Supplies from –12V to –100V High Side 380V Bus Inrush Current Limiter with Line Voltage Monitor and I2C Only Control VCC VL ON EN SCL SDA GND SCL SDA LOAD– LOAD+ ISOLATION BARRIER VCC2 UVH UVL RAMP DRAIN GATE SENSE+ SENSE– VEE EN2 LTM9100

9100 TA02

PINS NOT USED IN THIS CIRCUIT : ADIN2, ADR0, ADR1, ALERT, ALERT2, PG, PG2, PGIO, SCL2, SDA2, SS, TMR, VS 32.4k 8.45k ADIN OV 3.92k 8.87k 2.56V AT 435V 2.29V AT 235V 100/uni03A9 1.77V AT 435V 3.3M 32.4k 3.3M 10/uni03A9 39nF 22nF IXTH30N60L2 3.3M 0.017/uni03A9 1.5k 1.5k 330µF