LTM8049 LINEAR | Alldatasheet
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Technical content
8049fFor more information www.linear.com/LTM8049 TYPICAL APPLICATION FEATURES DESCRIPTION Dual SEPIC or Inverting µModule DC/DC Converter The LT M®8049 is a Dual SEPIC/Inverting µModule® (power module) DC/DC Converter . Each of the two outputs can be easily configured as a SEPIC or Inverting converter by simply grounding the appropriate output rail. The LTM8049 includes power devices, inductors, control circuitry and passive components. All that is needed to complete the design are input and output caps, and small resistors to set the output voltages and switching frequency. Other components may be used to control the soft-start and undervoltage lockout. The LTM8049 is packaged in a thermally enhanced, com- pact (15mm × 9mm) over-molded Ball Grid Array (BGA) package suitable for automated assembly by standard sur- face mount equipment. The LTM8049 is RoHS compliant. Maximum Load Current vs VIN±12VOUT from 2.7VIN to 20VIN
APPLICATIONS
n Two Complete Switch Mode Power Supplies n SEPIC or Inverting Topology n Wide Input Voltage Range: 2.6V to 20V n 2.5V to 24V or –2.5V to –24V Output Voltage n 1A at 5VOUT from 12VIN n Selectable Switching Frequency: 200kHz to 2.5MHz n Power Good Outputs for Event Based Sequencing n User Configurable Undervoltage Lockout n (e4) RoHS Compliant Package with Gold Pad Finish n Low Profile 15mm × 9mm × 2.42mm Surface Mount n Battery Powered Regulator n Local Negative Voltage Regulator n Low Noise Amplifier Power L, L T , L TC, L TM, Linear Technology, the Linear logo and µModule are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. V IN (V) 0.5 1.0 1.5 LOAD CURRENT (A)
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80.6k 1MHz VIN 2.7V TO 20V VOUT1 12V VOUT2 –12V 4.7µF 22µF 47µF SYNC2 CLKOUT1 FBX1 RT2 80.6k 1MHz 143k VOUT2P VOUT2N VIN2 RUN2 SYNC1 PINS NOT USED: SS1, SS2, PG1, PG2, CLKOUT2, SHARE1, SHARE2 FBX2
8049f For more information www.linear.com/LTM8049 PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS SYNC SHA Max Max Stor (Note 1) TOP VIEW BGA PACKAGE 77-LEAD (15mm × 9mm × 2.42mm) BANK 3 VIN2 RUN2 SS2 SYNC2 RT2 RT1 SYNC1 SHARE1 SS1 RUN1 BANK 2 V IN1 BANK 1 GND BANK 5 V OUT2P FBX2 BANK 7 VOUT2N BANK 6 VOUT1N FBX1 BANK 4 VOUT1P A B C D E F G H J K L 7 6 5 4 3 2 1 SHARE2 CLKOUT1 PG1 PG2 CLKOUT2 TJMAX = 125°C, θJA = 16.2°C/W , θJB = 3.8°C/W , θJCtop = 8.8°C/W , θJCbottom = 3.8°C/W , θJCboard = 4.6°C/W , WEIGHT = 0.8g, θ VALUES DETERMINED PER JEDEC 51-9, 51-12 ORDER INFORMATION PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE TYPE MSL RATING TEMPERATURE RANGE (SEE NOTE 2)DEVICE FINISH CODE LTM8049EY#PBF SAC305 (RoHS) LTM8049Y e1 BGA 3 –40°C to 125°C LTM8049IY#PBF –40°C to 125°C * Device temperature grade is indicated by a label on the shipping container .
- Pad or ball finish code is per IPC/JEDEC J-STD-609.
- Terminal Finish Part Marking: www.linear .com/leadfree
- This product is not recommended for second side reflow. For more information, go to www.linear .com/BGA-assy
- Recommended BGA PCB Assembly and Manufacturing Procedures: www.linear .com/BGA-assy
- This product is moisture sensitive. For more information, go to: www.linear .com/BGA-assy (http://www.linear .com/product/LTM8049#orderinfo)
8049fFor more information www.linear.com/LTM8049
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM8049E is guaranteed to meet performance specifications from 0°C to 125°C. Specifications over the –40°C to 125°C internal temperature range are assured by design, characterization and correlation with statistical process controls. LTM8049I is guaranteed to meet specifications over the full –40°C to 125°C internal operating temperature range. Note that the maximum internal temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: This μModule regulator includes overtemperature protection that is intended to protect the device during momentary overload conditions. Internal temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum internal operating junction temperature may impair device reliability. Note 4: CLKOUTn is intended to drive other circuitry. Do not apply a positive or negative voltage or current source to CLKOUT , otherwise permanent damage may occur . Note 5: The duty cycle of CLKOUT2 is dependent upon the internal temperature. See the Applications Information section for more details. The l denotes the specifications which apply over the specified operating temperature range (Notes 2, 3), otherwise specifications are at TA = 25°C. RUN = 2V unless otherwise specified. PARAMETER CONDITIONS MIN TYP MAX UNITS Minimum Input Operating Voltage l 2.6 V Positive Output DC Voltage IOUT = 50mA, RFB = 15.4k, VOUTN Grounded IOUT = 50mA, RFB = 274k, VOUTN Grounded 2.5 V V Negative Output DC Voltage IOUT = 50mA, RFB = 30.1k, VOUTP Grounded IOUT = 50mA, RFB = 287k, VOUTP Grounded –2.5 –24 V V Maximum Continuous Output DC Current V IN = 12V, VOUT = 5V or –5V VIN = 12V, VOUT = 24 or –24V 0.25 A A V IN Quiescent Current VRUN = 0V VRUN = 2V, No Load 2 µA mA Line Regulation 4 ≤ VIN ≤ 20V, IOUT = 0.6A 0.1 % Load Regulation 0 ≤ IOUT ≤ 1A 0.3 % Switching Frequency RT = 31.6k RT = 412k l l 2100 160 2500 200 2900 240 kHz kHz Voltage at FBX Pin Positive Output Negative Output l l 1.185 1.204 1.22 V mV Current into FBX Pin Positive Output Negative Output l l 83.3 83.3 85.6 85.6 µA µA RUN pin Threshold Voltage RUN Pin Rising RUN Pin Falling 1.21 1.31 1.27 1.4 V V RUN Pin Current V RUN = 3V VRUN = 1.3V VRUN = 0V 10.1 12.1 14.1 0.1 µA µA µA SS Sourcing Current SS = 0V 5.7 8.8 11.7 µA Synchronization Frequency Range 200 2500 kHz SYNC Input Low Threshold 0.4 V SYNC Input High Threshold 1.3 V CLKOUT1 Duty Cycle (Note 5) 50 % CLKOUT Output Voltage (Low) 2k Pull-Up to 2V 0.2 V CLKOUT Output Voltage (High) 2k Pull-Down to GND 1.9 V PG Threshold for Positive Feedback Voltage FBX Rising 1.09 1.2 V PG Threshold for Negative Feedback Voltage FBX Falling 20 120 mV PG Output Voltage Low 100µA into PG, FBX = 1V 150 mV PG Leakage Current PG = 20V, Run = 0V 1 µA
8049f For more information www.linear.com/LTM8049 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency, VOUT ±2.5V Efficiency, VOUT ±3.3V Efficiency, VOUT ±5V Efficiency, VOUT ±8V Efficiency, VOUT ±12V Efficiency, VOUT ±15V Efficiency, VOUT ±18V Efficiency, VOUT ±24V Input vs Load Current, VOUT ±2.5V IN IN LOAD CURRENT (A) 0.5 1.5 EFFICIENCY (%)
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LOAD CURRENT (A) 0.5 1.5 EFFICIENCY (%)
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LOAD CURRENT (A) 0.20 0.40 0.60 0.80 EFFICIENCY (%)
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LOAD CURRENT (A) 0.5 1.5 EFFICIENCY (%)
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LOAD CURRENT (A) 0.50 1.50 EFFICIENCY (%)
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LOAD CURRENT (A) 0.2 0.4 0.6 EFFICIENCY (%)
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LOAD CURRENT (A) 0.5 1.5 EFFICIENCY (%)
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LOAD CURRENT (A) 0.25 0.50 0.75 EFFICIENCY (%)
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LOAD CURRENT (A) 0.5 1.5 0.5 1.0 1.5 2.0 2.5 INPUT CURRENT (A)
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8049fFor more information www.linear.com/LTM8049 TYPICAL PERFORMANCE CHARACTERISTICS Input vs Load Current, VOUT ±3.3V Input vs Load Current, V OUT ±5V Input vs Load Current, VOUT ±8V Input vs Load Current, VOUT ±12V Input vs Load Current, VOUT ±15V Input vs Load Current, VOUT ±18V Input vs Load Current, VOUT ±24V Maximum Load Current vs VIN Maximum Load Current vs VIN IN 12V IN LOAD CURRENT (A) 0.5 1.5 0.5 1.0 1.5 2.0 2.5 INPUT CURRENT (A)
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LOAD CURRENT (A) 0.50 1.50 1.0 2.0 3.0 INPUT CURRENT (A)
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LOAD CURRENT (A) 0.2 0.4 0.6 1.0 2.0 3.0 INPUT CURRENT (A)
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LOAD CURRENT (A) 0.5 1.5 1.0 2.0 3.0 INPUT CURRENT (A)
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LOAD CURRENT (A) 0.25 0.50 0.75 1.0 2.0 3.0 INPUT CURRENT (A)
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2.5V OUT 3.3V OUT OUT V IN (V) 0.5 1.0 1.5 2.0 LOAD CURRENT (A) PER CHANNEL
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LOAD CURRENT (A) 0.5 1.5 1.0 2.0 3.0 INPUT CURRENT (A)
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LOAD CURRENT (A) 0.2 0.4 0.6 0.8 1.0 2.0 3.0 INPUT CURRENT (A)
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V IN (V) 0.5 1.0 1.5 2.0 LOAD CURRENT (A)
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8049f For more information www.linear.com/LTM8049 TYPICAL PERFORMANCE CHARACTERISTICS Maximum Load Current vs VIN Derating Curve, VOUT ±2.5VOUT Derating Curve, VOUT ±3.3VOUT Derating Curve, VOUT ±5VOUT Derating Curve, VOUT ±8VOUT Derating Curve, VOUT ±12VOUT Derating Curve, VOUT ±15VOUT Derating Curve, VOUT ±18VOUT Derating Curve, VOUT ±24VOUT 18V OUT 24V OUT V IN (V) 0.25 0.50 0.75 1.00 LOAD CURRENT (A)
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0 LFM
0.50 1.00 1.50 2.00 OUTPUT CURRENT (A)
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AMBIENT TEMPERATURE ( °C) 0.25 0.50 0.75 1.00 OUTPUT CURRENT (A)
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AMBIENT TEMPERATURE ( °C) 0LFM IN IN 100 125 0.50 1.00 1.50 2.00 OUTPUT CURRENT (A)
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AMBIENT TEMPERATURE ( °C) 0.50 1.00 1.50 OUTPUT CURRENT (A)
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AMBIENT TEMPERATURE ( °C) 0.25 0.50 0.75 1.00 OUTPUT CURRENT (A)
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AMBIENT TEMPERATURE ( °C) AMBIENT TEMPERATURE ( °C) 100 125 0.50 1.00 1.50 2.00 OUTPUT CURRENT (A)
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0.50 1.00 1.50 OUTPUT CURRENT (A)
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AMBIENT TEMPERATURE ( °C) 0.25 0.50 0.75 OUTPUT CURRENT (A)
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AMBIENT TEMPERATURE ( °C)
8049fFor more information www.linear.com/LTM8049 TYPICAL PERFORMANCE CHARACTERISTICS CLKOUT2 Duty Cycle vs Temperature Output Ripple, DC2244A Board 800mA Load, 12V IN Measured Across C5, C6 f SW = 1MHz TEMPERATURE (°C) –50 –25 100 125 DUTY CYCLE (%)
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GND (Bank 1): Tie these GND pins to a local ground plane below the LTM8049 and the circuit components. GND MUST BE CONNECTED EITHER TO V OUTP OR VOUTN FOR PROPER OPERATION. In most applications, the bulk of the heat flow out of the LTM8049 is through these pads, so the printed circuit design has a large impact on the thermal performance of the part. See the PCB Layout and Thermal Considerations sections for more details. Return the feedback divider (RFB) to this net. V IN1, VIN2 (Banks 2, 3): The VINn pins supply current to the LTM8049’s internal regulator and to the internal power switch. This pin must be locally bypassed with an external, low ESR capacitor . V OUT1P, VOUT2P (Banks 4, 5): VOUTnP is the positive out- put of the LTM8049. Apply an external capacitor between VOUTnP and VOUTnN. Tie this net to GND to configure the LMT8049 as a negative output Inverting regulator . VOUT1N, VOUT2N (Banks 6, 7): VOUTnN is the negative out- put of the LTM8049. Apply an external capacitor between VOUTnP and VOUTnN. Tie this net to GND to configure the LTM8049 as a positive output SEPIC regulator . RUN1, RUN2 (Pins B7, K7): These pins are used to enable/ disable the chip and restart the soft-start sequence. Drive below 1.21V to stop the LTM8049 from switching. Drive above 1.4V to activate the device and restart the soft-start sequence. Do not float this pin. RT1, RT2 (Pins E7, G7): The RTn pins are used to program the switching frequency of the LTM8049 by connecting a resistor from this pin to ground. The switching frequency of the LTM8049 is determined by the equation RTn = (81.6/f OSC)-1, where the fOSC is the switching frequency in MHz. This pin must have a resistor to GND. Do not apply a voltage to this pin. SS1, SS2 (Pins C7, J7): Connect a soft-start capacitor from this pin to GND. Upon start-up, the SSn pins will be charged by an internal current source to about 2V. SYNC1, SYNC2 (Pins D7, H7): To synchronize the switch- ing frequency to an outside clock, simply drive this pin with a clock signal. The high voltage level of the clock needs to exceed 1.3V, and the low level must be less than 0.4V. Drive this pin to less than 0.4V to revert to the internal free running clock. Ground these pins if synchronization is not required. See the Applications Information section for more information. 500ns/DIV 12VOUT 50mV/DIV –12VOUT 20mV/DIV
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8049f For more information www.linear.com/LTM8049 BLOCK DIAGRAM PIN FUNCTIONS FBX1, FBX2 (Pins C1, J1): If configured as a SEPIC, the LTM8049 regulates its FBX pin to 1.204V. Apply a resis- tor between FBX and V OUTP. Its value should be R FB = [(VOUTP – 1.204)/0.0833]k. If the LTM8049 is configured as an inverting converter , the LTM8049 regulates the FBX pin to 7mV. Apply a resistor between FBX and V OUTN of value RFB = [(|V OUTN| + 0.007)/0.0833]k. The LTM8049 features frequency foldback to protect the power switches during a fault or output current overload. During start-up, frequency foldback also limits the current the LTM8049 delivers to the load. The user must evaluate the start-up behavior of the LTM8049 to ensure that it properly pow- ers up the load. PG1, PG2 (Pins D6, H6): These active high pins indicates that the FBn pin voltage for the corresponding channel is within 4% of its regulation voltage These open drain outputs requires a pull-up resistor to indicate power good. Also, the status of these pins is valid only when RUN > 1.4V and V IN > 2.6V. CLKOUT1, CLKOUT2 (Pins E6, G6): Use these pins to synchronize devices to either channel of the LTM8049. These pins oscillate at the same frequency as the LTM8049 internal oscillator or , if active, the SYNC pin. The CLKOUT1 signal is about 180° out of phase with the oscillator of channel 1 and duty cycle is about 50%. The CLKOUT2 signal is in phase with the internal oscillator of channel 2 and its duty cycle varies linearly with the internal temperature of the LTM8049. Please refer to the Applications Information section for detailed information on using CLKOUT2 as an indication of the LTM8049 internal temperature. Do not apply a voltage to this pin or use this pin to drive capaci- tive loads greater than 120pF. SHARE1, 2 (pins F3, F4): Connect these pins together if the two outputs of the LTM8049 are paralleled. Otherwise, leave these pins floating. CONTROLLER NOTE: CHANNEL 1. CHANNEL 2 IS FUNCTIONAL IDENTICAL, EXCEPT FOR THE CLKOUT2 VS TEMPERATURE BEHAVIOR. PLEASE SEE THE PIN DESCRIPTION AND APPLICATIONS INFORMATION SECTIONS FOR DETAILS. 8049 BD GND VOUT1P VOUT1N 4.7µH 0.1µF 2.2µF VIN1 RUN1 RT1 SHARE1 SYNC1 FBX1 PG1 CLKOUT1 4.7µH
8049fFor more information www.linear.com/LTM8049 OPERATION The LTM8049 contains two stand-alone switching DC/ DC converters; either one may be configured as a SEPIC (single-ended primary inductance converter) or inverting power supply simply by tying V OUTN or V OUTP to GND, respectively. It accepts an input voltage up to 20VDC. The output is adjustable between 2.5V and 24V for the SEPIC, and between –2.5V and –24V for the inverting configura- tion. The LTM8049 can provide 1.5A at V IN = 12V when VOUT = 5V or –5V at ambient room temperature. As shown in the Block Diagram, the LTM8049 contains a current mode controller , power switching element, power coupled inductor , power Schottky diode and a modest amount of input and output capacitance. The LTM8049 is a fixed frequency PWM regulator . The LTM8049 switching can free run by applying a resistor to the RT pin or synchronize to an external source at a frequency between 200kHz and 2.5MHz. To synchronize to an external source, drive a valid signal source into the SYNC pin. See Synchronization in the Applications Section for more details. For most applications, the design process is straight forward, summarized as follows: Look at Table 1 and find the row that has the desired input range and output voltage. 2. Apply the recommended CIN, COUT, RADJ and RT values. While these component combinations have been tested for proper operation, it is incumbent upon the user to verify proper operation over the intended system’s line, load and environmental conditions. Bear in mind that the maximum output current is limited by junction tempera- ture, the relationship between the input and output voltage magnitude and polarity and other factors. Please refer to the graphs in the Typical Performance Characteristics section for guidance. Table 1 gives the recommended component values and configuration for a single channel. Each channel may be configured independently. The maximum frequency (and attendant R T value) at which the LTM8049 should be al- lowed to switch is given in Table 1 in the f MAX column, while the recommended frequency (and R T value) for The LTM8049 also features RUN and SS pins to control the start-up behavior of the device. The RUN pin may also be used to implement an accurate undervoltage lockout function by applying a resistor network to the RUN pin. The LTM8049 features frequency foldback to protect the power switches during a fault or output current overload. During start-up, frequency foldback also limits the current the LTM8049 delivers to the load. The user must evaluate the start-up behavior of the LTM8049 to ensure that it properly powers up the load. The LTM8049 is equipped with a thermal shutdown to protect the device during momentary overload conditions. It is set above the 125°C absolute maximum internal tem- perature rating to avoid interfering with normal specified operation, so internal device temperatures will exceed the absolute maximum rating when the overtemperature protection is active. Therefore, continuous or repeated activation of the thermal shutdown may impair device reliability. optimal efficiency over the given input condition is given in the f OPTIMAL column. Running the LTM8049 faster than the recommended frequency may reduce the usable input voltage range. Capacitor Selection Considerations The C IN and C OUT capacitor values in Table 1 are the minimum recommended values for the associated oper- ating conditions. Applying capacitor values below those indicated in Table 1 is not recommended, and may result in undesirable operation. Using larger values is generally acceptable, and can yield improved dynamic response, if it is necessary. Again, it is incumbent upon the user to verify proper operation over the intended system ’ s line, load and environmental conditions. Ceramic capacitors are small, robust and have very low ESR. However , not all ceramic capacitors are suitable. X5R and X7R types are stable over temperature and ap - plied voltage and give dependable service. Other types, including Y5V and Z5U have very large temperature and voltage coefficients of capacitance. In an application APPLICATIONS INFORMATION
inductance forms a high Q (underdamped) tank circuit. avoided; see the Hot-Plugging Safely section. to ground. Do not leave this pin open under any condition. however , may necessitate another operating frequency. Table 1. Recommended Component Values and Configuration (TA = 25°C) Note: An input bulk capacitor is required.
these problems might occur . voltages when rising or falling respectively. 11.6µA at the 1.27V falling threshold. Figure 1. The RUN Pin May Be Used to Implement
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it properly powers up its load. active, possibly impairing the device’s reliability. heat-sinking are acceptable.
- Place the CIN capacitor as close as possible to the VIN
and GND connection of the LTM8049.
- Place the C OUT capacitor as close as possible to the
VOUT and GND connection of the LTM8049. Figure 2. Layout Showing Suggested External Components, GND Plane and Thermal Vias
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8049fFor more information www.linear.com/LTM8049 APPLICATIONS INFORMATION 4. Place the C IN and C OUT capacitors such that their ground current flow directly adjacent or underneath the LTM8049. 5. Connect all of the GND connections to as large a copper pour or plane area as possible on the top layer . Avoid breaking the ground connection between the external components and the LTM8049. 6. Use vias to connect the GND copper area to the board’s internal ground planes. Liberally distribute these GND vias to provide both a good ground connection and thermal path to the internal planes of the printed circuit board. Pay attention to the location and density of the thermal vias in Figure 2. The LTM8049 can benefit from the heat-sinking afforded by vias that connect to internal GND planes at these locations, due to their proximity to internal power handling components. The optimum number of thermal vias depends upon the printed circuit board design. For example, a board might use very small via holes. It should employ more thermal vias than a board that uses larger holes. Hot-Plugging Safely The small size, robustness and low impedance of ceramic capacitors make them an attractive option for the input bypass capacitor of LTM8049. However , these capacitors can cause problems if the LTM8049 is plugged into a live input supply (see Application Note 88 for a complete dis- cussion). The low loss ceramic capacitor combined with stray inductance in series with the power source forms an underdamped tank circuit, and the voltage at the V IN pin of the LTM8049 can ring to more than twice the nominal input voltage, possibly exceeding the LTM8049’s rating and damaging the part. If the input supply is poorly controlled or the user will be plugging the LTM8049 into an energized supply, the input network should be designed to prevent this overshoot. This can be accomplished by installing a small resistor in series to V IN, but the most popular method of controlling input voltage overshoot is to add an electrolytic bulk capacitor to the V IN net. This capacitor’s relatively high equivalent series resistance damps the circuit and eliminates the voltage overshoot. The extra capacitor improves low frequency ripple filtering and can slightly improve the ef- ficiency of the circuit, though it is physically large. Thermal Considerations The LTM8049 output current may need to be derated if it is required to operate in a high ambient temperature or deliver a large amount of continuous power . The amount of current derating is dependent upon the input voltage, output power and ambient temperature. The temperature rise curves given in the Typical Performance Character - istics section can be used as a guide. These curves were generated by a LTM8049 mounted to a 58cm 2 4-layer FR4 printed circuit board. Boards of other sizes and layer count can exhibit different thermal behavior , so it is incumbent upon the user to verify proper operation over the intended system’s line, load and environmental operating conditions. The thermal resistance numbers listed in Page 2 of the data sheet are based on modeling the µModule package mounted on a test board specified per JESD51-9 (Test Boards for Area Array Surface Mount Package Thermal Measurements). The thermal coefficients provided in this page are based on JESD 51-12 (Guidelines for Reporting and Using Electronic Package Thermal Information). For increased accuracy and fidelity to the actual application, many designers use FEA to predict thermal performance. To that end, Page 2 of the data sheet typically gives four thermal coefficients: θ JA: Thermal resistance from junction to ambient θJCbottom: Thermal resistance from junction to the bottom of the product case θ JCtop: Thermal resistance from junction to top of the product case θ JB: Thermal resistance from junction to the printed circuit board. While the meaning of each of these coefficients may seem to be intuitive, JEDEC has defined each to avoid confusion and inconsistency. These definitions are given in JESD 51-12, and are quoted or paraphrased below: θ JA is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as
still air although natural convection causes the air to move. application or viable operating condition. conditions don’t generally match the user’s application. two layer board. This board is described in JESD 51-9. converter , and the green are outside. heating, resulting in impaired performance or reliability.
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Figure 3. Graphical Representation of JESD51-12 Thermal Coefficients
8049fFor more information www.linear.com/LTM8049 TYPICAL APPLICATIONS L TM8049 45.3k
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2.7V TO 15V VOUT1 VOUT2 –5V 4.7µF 47µF 147µF SYNC2 CLKOUT1 FBX1 RT2 107k 750kHz 60.4k VOUT2P VOUT2N VIN2 RUN2 PINS NOT USED: SS1, SS2, PG1, PG2, CLKOUT2, SHARE1, SHARE2 SYNC1 FBX2 L TM8049 82.5k
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80.6k 1MHz VIN 2.7V TO 20V VOUT 47µF SYNC2 CLKOUT1 SHARE2 SHARE1 FBX1 RT2 80.6k 1MHz 82.5k VOUT2P VOUT2N VIN2 RUN2 PINS NOT USED: SS1, SS2, PG1, PG2, CLKOUT2 FBX2 4.7µF ±5V Converter Parallel 8V Outputs for Increased Current Maximum Load Current vs VIN Maximum Load Current vs VIN V IN (V) 0.5 1.0 1.5 2.0 LOAD CURRENT (A)
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V IN (V) 0.5 1.5 2.5 3.5 LOAD CURRENT (A)
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8049f For more information www.linear.com/LTM8049 Pin Assignment Table (Arranged by Pin Number) PACKAGE DESCRIPTION PACKAGE PHOTO PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME A1 VOUT1P B1 VOUT1P C1 FBX1 D1 VOUT1N E1 VOUT1N F1 GND A2 VOUT1P B2 VOUT1P C2 VOUT1N D2 VOUT1N E2 VOUT1N F2 GND A3 GND B3 GND C3 GND D3 GND E3 GND F3 SHARE1 A4 GND B4 GND C4 GND D4 GND E4 GND F4 SHARE2 A5 VIN1 B5 GND C5 GND D5 GND E5 GND F5 GND A6 VIN1 B6 GND C6 GND D6 PG1 E6 CLKOUT1 F6 GND A7 VIN1 B7 RUN1 C7 SS1 D7 SYNC1 E7 RT1 F7 GND PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME G1 VOUT2N H1 VOUT2N J1 FBX2 K1 VOUT2P L1 VOUT2P G2 VOUT2N H2 VOUT2N J2 VOUT2N K2 VOUT2P L2 VOUT2P G3 GND H3 GND J3 GND K3 GND L3 GND G4 GND H4 GND J4 GND K4 GND L4 GND G5 GND H5 GND J5 GND K5 GND L5 VIN2 G6 CLKOUT2 H6 PG2 J6 GND K6 GND L6 VIN2 G7 RT2 H7 SYNC2 J7 SS2 K7 RUN2 L7 VIN2
8049fFor more information www.linear.com/LTM8049 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION Please refer to http://www.linear .com/product/LTM8049#packaging for the most recent package drawings. PACKAGE TOP VIEW PIN “A1” CORNER Y X aaa Z aaa Z 77-Lead (15.00mm × 9.00mm × 2.42mm) (Reference LTC DWG# 05-08-1964 Rev A) NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE DETAIL A Øb (77 PLACES) DETAIL B SUBSTRATE A ccc Z DETAIL B PACKAGE SIDE VIEW MOLD CAP Z M X Y Z ddd M Z eee SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 2.22 0.50 1.72 0.60 0.60 0.27 1.45 NOM 2.42 0.60 1.82 0.75 0.63 15.00 9.00 1.27 12.70 7.62 0.32 1.50 MAX 2.62 0.70 1.92 0.90 0.66 0.37 1.55 0.15 0.10 0.20 0.30 0.15 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 77 D E // bbb Z Z BGA 77 0114 REV A TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” L TMXXXXXX µModule DETAIL A PACKAGE BOTTOM VIEW SEE NOTES A B C D E F G H J K L PIN 1 e b F G 7 6 5 4 3 2 1 SUGGESTED PCB LAYOUT TOP VIEW 0.000 2.540 3.810 5.080 6.350 1.270 3.810 2.540 1.270 5.080 6.350 3.810 2.540 1.270 3.810 2.540 1.270 0.3175 0.3175 0.000 0.630 ±0.025 Ø 77x
7 PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y SEE NOTES
8049f For more information www.linear.com/LTM8049 LINEAR TECHNOLOGY CORPORATION 2016 LT 0816 • PRINTED IN USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTM8049 RELATED PARTS TYPICAL APPLICATION DESIGN RESOURCES SUBJECT DESCRIPTION µModule Design and Manufacturing Resources Design:
- Selector Guides
- Demo Boards and Gerber Files
- Free Simulation Tools Manufacturing:
- Quick Start Guide
- PCB Design, Assembly and Manufacturing Guidelines
- Package and Board Level Reliability µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet. 2. Search using the Quick Power Search parametric table. TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products. Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging. Parallel Outputs to Increase –5V Output Current L TM8049 60.4k
8049 TA04a
2.7V TO 15V VOUT –5V 100µF SYNC2 CLKOUT1 SHARE2 SHARE1 FBX1 RT2 107k 750kHz 60.4k VOUT2P VOUT2N VIN2 RUN2 PINS NOT USED: SS1, SS2, PG1, PG2, CLKOUT2 FBX2 4.7µF Maximum Load Current vs VIN PART NUMBER DESCRIPTION COMMENT LTM8046 2kVAC, 2.75W Isolated DC/DC µModule Converter 3.1V ≤ V IN ≤ 31V, 1.8V ≤ VOUT ≤ 12V. 5V at 550mA from 24VIN, 9mm × 15mm × 4.92mm BGA LTM8048 725kVDC, 1.5W Isolated DC/DC µModule Converter with Integrated LDO 3.1V ≤ V IN ≤ 32V, 1.2V ≤ LDO VOUT ≤ 12V. 9mm × 11.25mm × 4.92mm BGA LTM8068 2kVAC, 2.25W Isolated DC/DC µModule Converter with Integrated LDO 2.8V ≤ V IN ≤ 40V, 1.2V ≤ LDO VOUT ≤ 18V. 9mm × 11.25mm × 4.92mm BGA LTM8023 36VIN, 2A, Step-Down DC/DC µModule Converter . Can Be Used for Inverting 9mm x 11.25mm x 3.52mm BGA LTM8053 40VIN, 3.5A Step-Down DC/DC µModule Regulator . Can be used for inverting. V IN (V) LOAD CURRENT (A)